xref: /freebsd/sys/dev/dpaa2/dpaa2_swp.h (revision 6e5dcc6113da649a79e5bc2c3ea9329bcd1d85d5)
1 /*-
2  * SPDX-License-Identifier: BSD-2-Clause
3  *
4  * Copyright © 2021-2023 Dmitry Salychev
5  *
6  * Redistribution and use in source and binary forms, with or without
7  * modification, are permitted provided that the following conditions
8  * are met:
9  * 1. Redistributions of source code must retain the above copyright
10  *    notice, this list of conditions and the following disclaimer.
11  * 2. Redistributions in binary form must reproduce the above copyright
12  *    notice, this list of conditions and the following disclaimer in the
13  *    documentation and/or other materials provided with the distribution.
14  *
15  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
16  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18  * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
19  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
25  * SUCH DAMAGE.
26  */
27 
28 #ifndef	_DPAA2_SWP_H
29 #define	_DPAA2_SWP_H
30 
31 #include <sys/param.h>
32 #include <sys/systm.h>
33 #include <sys/bus.h>
34 
35 #include "dpaa2_types.h"
36 #include "dpaa2_buf.h"
37 #include "dpaa2_bp.h"
38 
39 /*
40  * DPAA2 QBMan software portal.
41  */
42 
43 /* All QBMan commands and result structures use this "valid bit" encoding. */
44 #define DPAA2_SWP_VALID_BIT		((uint32_t) 0x80)
45 
46 #define DPAA2_SWP_TIMEOUT		100000	/* in us */
47 #define DPAA2_SWP_CMD_PARAMS_N		8u
48 #define DPAA2_SWP_RSP_PARAMS_N		8u
49 
50 /*
51  * Maximum number of buffers that can be acquired/released through a single
52  * QBMan command.
53  */
54 #define DPAA2_SWP_BUFS_PER_CMD		7u
55 
56 /*
57  * Number of times to retry DPIO portal operations while waiting for portal to
58  * finish executing current command and become available.
59  *
60  * We want to avoid being stuck in a while loop in case hardware becomes
61  * unresponsive, but not give up too easily if the portal really is busy for
62  * valid reasons.
63  */
64 #define DPAA2_SWP_BUSY_RETRIES		1000
65 
66 /* Versions of the QBMan software portals. */
67 #define DPAA2_SWP_REV_4000		0x04000000
68 #define DPAA2_SWP_REV_4100		0x04010000
69 #define DPAA2_SWP_REV_4101		0x04010001
70 #define DPAA2_SWP_REV_5000		0x05000000
71 
72 #define DPAA2_SWP_REV_MASK		0xFFFF0000
73 
74 /* Registers in the cache-inhibited area of the software portal. */
75 #define DPAA2_SWP_CINH_CR		0x600 /* Management Command reg.*/
76 #define DPAA2_SWP_CINH_EQCR_PI		0x800 /* Enqueue Ring, Producer Index */
77 #define DPAA2_SWP_CINH_EQCR_CI		0x840 /* Enqueue Ring, Consumer Index */
78 #define DPAA2_SWP_CINH_CR_RT		0x900 /* CR Read Trigger */
79 #define DPAA2_SWP_CINH_VDQCR_RT		0x940 /* VDQCR Read Trigger */
80 #define DPAA2_SWP_CINH_EQCR_AM_RT	0x980
81 #define DPAA2_SWP_CINH_RCR_AM_RT	0x9C0
82 #define DPAA2_SWP_CINH_DQPI		0xA00 /* DQRR Producer Index reg. */
83 #define DPAA2_SWP_CINH_DQRR_ITR		0xA80 /* DQRR interrupt timeout reg. */
84 #define DPAA2_SWP_CINH_DCAP		0xAC0 /* DQRR Consumption Ack. reg. */
85 #define DPAA2_SWP_CINH_SDQCR		0xB00 /* Static Dequeue Command reg. */
86 #define DPAA2_SWP_CINH_EQCR_AM_RT2	0xB40
87 #define DPAA2_SWP_CINH_RCR_PI		0xC00 /* Release Ring, Producer Index */
88 #define DPAA2_SWP_CINH_RAR		0xCC0 /* Release Array Allocation reg. */
89 #define DPAA2_SWP_CINH_CFG		0xD00
90 #define DPAA2_SWP_CINH_ISR		0xE00
91 #define DPAA2_SWP_CINH_IER		0xE40
92 #define DPAA2_SWP_CINH_ISDR		0xE80
93 #define DPAA2_SWP_CINH_IIR		0xEC0
94 #define DPAA2_SWP_CINH_ITPR		0xF40
95 
96 /* Registers in the cache-enabled area of the software portal. */
97 #define DPAA2_SWP_CENA_EQCR(n)		(0x000 + ((uint32_t)(n) << 6))
98 #define DPAA2_SWP_CENA_DQRR(n)		(0x200 + ((uint32_t)(n) << 6))
99 #define DPAA2_SWP_CENA_RCR(n)		(0x400 + ((uint32_t)(n) << 6))
100 #define DPAA2_SWP_CENA_CR		(0x600) /* Management Command reg. */
101 #define DPAA2_SWP_CENA_RR(vb)		(0x700 + ((uint32_t)(vb) >> 1))
102 #define DPAA2_SWP_CENA_VDQCR		(0x780)
103 #define DPAA2_SWP_CENA_EQCR_CI		(0x840)
104 
105 /* Registers in the cache-enabled area of the software portal (memory-backed). */
106 #define DPAA2_SWP_CENA_DQRR_MEM(n)	(0x0800 + ((uint32_t)(n) << 6))
107 #define DPAA2_SWP_CENA_RCR_MEM(n)	(0x1400 + ((uint32_t)(n) << 6))
108 #define DPAA2_SWP_CENA_CR_MEM		(0x1600) /* Management Command reg. */
109 #define DPAA2_SWP_CENA_RR_MEM		(0x1680) /* Management Response reg. */
110 #define DPAA2_SWP_CENA_VDQCR_MEM	(0x1780)
111 #define DPAA2_SWP_CENA_EQCR_CI_MEMBACK	(0x1840)
112 
113 /* Shifts in the portal's configuration register. */
114 #define DPAA2_SWP_CFG_DQRR_MF_SHIFT	20
115 #define DPAA2_SWP_CFG_EST_SHIFT		16
116 #define DPAA2_SWP_CFG_CPBS_SHIFT	15
117 #define DPAA2_SWP_CFG_WN_SHIFT		14
118 #define DPAA2_SWP_CFG_RPM_SHIFT		12
119 #define DPAA2_SWP_CFG_DCM_SHIFT		10
120 #define DPAA2_SWP_CFG_EPM_SHIFT		8
121 #define DPAA2_SWP_CFG_VPM_SHIFT		7
122 #define DPAA2_SWP_CFG_CPM_SHIFT		6
123 #define DPAA2_SWP_CFG_SD_SHIFT		5
124 #define DPAA2_SWP_CFG_SP_SHIFT		4
125 #define DPAA2_SWP_CFG_SE_SHIFT		3
126 #define DPAA2_SWP_CFG_DP_SHIFT		2
127 #define DPAA2_SWP_CFG_DE_SHIFT		1
128 #define DPAA2_SWP_CFG_EP_SHIFT		0
129 
130 /* Static Dequeue Command Register attribute codes */
131 #define DPAA2_SDQCR_FC_SHIFT		29 /* Dequeue Command Frame Count */
132 #define DPAA2_SDQCR_FC_MASK		0x1
133 #define DPAA2_SDQCR_DCT_SHIFT		24 /* Dequeue Command Type */
134 #define DPAA2_SDQCR_DCT_MASK		0x3
135 #define DPAA2_SDQCR_TOK_SHIFT		16 /* Dequeue Command Token */
136 #define DPAA2_SDQCR_TOK_MASK		0xff
137 #define DPAA2_SDQCR_SRC_SHIFT		0  /* Dequeue Source */
138 #define DPAA2_SDQCR_SRC_MASK		0xffff
139 
140 /*
141  * Read trigger bit is used to trigger QMan to read a command from memory,
142  * without having software perform a cache flush to force a write of the command
143  * to QMan.
144  *
145  * NOTE: Implemented in QBMan 5.0 or above.
146  */
147 #define DPAA2_SWP_RT_MODE		((uint32_t)0x100)
148 
149 /* Interrupt Enable Register bits. */
150 #define DPAA2_SWP_INTR_EQRI		0x01
151 #define DPAA2_SWP_INTR_EQDI		0x02
152 #define DPAA2_SWP_INTR_DQRI		0x04
153 #define DPAA2_SWP_INTR_RCRI		0x08
154 #define DPAA2_SWP_INTR_RCDI		0x10
155 #define DPAA2_SWP_INTR_VDCI		0x20
156 
157 /* "Write Enable" bitmask for a command to configure SWP WQ Channel.*/
158 #define DPAA2_WQCHAN_WE_EN		(0x1u) /* Enable CDAN generation */
159 #define DPAA2_WQCHAN_WE_ICD		(0x2u) /* Interrupt Coalescing Disable */
160 #define DPAA2_WQCHAN_WE_CTX		(0x4u)
161 
162 /* Definitions for parsing DQRR entries. */
163 #define DPAA2_DQRR_RESULT_MASK		(0x7Fu)
164 #define DPAA2_DQRR_RESULT_DQ		(0x60u)
165 #define DPAA2_DQRR_RESULT_FQRN		(0x21u)
166 #define DPAA2_DQRR_RESULT_FQRNI		(0x22u)
167 #define DPAA2_DQRR_RESULT_FQPN		(0x24u)
168 #define DPAA2_DQRR_RESULT_FQDAN		(0x25u)
169 #define DPAA2_DQRR_RESULT_CDAN		(0x26u)
170 #define DPAA2_DQRR_RESULT_CSCN_MEM	(0x27u)
171 #define DPAA2_DQRR_RESULT_CGCU		(0x28u)
172 #define DPAA2_DQRR_RESULT_BPSCN		(0x29u)
173 #define DPAA2_DQRR_RESULT_CSCN_WQ	(0x2au)
174 
175 /* Frame dequeue statuses */
176 #define DPAA2_DQ_STAT_FQEMPTY		(0x80u) /* FQ is empty */
177 #define DPAA2_DQ_STAT_HELDACTIVE	(0x40u) /* FQ is held active */
178 #define DPAA2_DQ_STAT_FORCEELIGIBLE	(0x20u) /* FQ force eligible */
179 #define DPAA2_DQ_STAT_VALIDFRAME	(0x10u) /* valid frame */
180 #define DPAA2_DQ_STAT_ODPVALID		(0x04u) /* FQ ODP enable */
181 #define DPAA2_DQ_STAT_VOLATILE		(0x02u) /* volatile dequeue (VDC) */
182 #define DPAA2_DQ_STAT_EXPIRED		(0x01u) /* VDC is expired */
183 
184 /*
185  * Portal flags.
186  *
187  * TODO: Use the same flags for both MC and software portals.
188  */
189 #define DPAA2_SWP_DEF			0x0u
190 #define DPAA2_SWP_NOWAIT_ALLOC		0x2u	/* Do not sleep during init */
191 #define DPAA2_SWP_LOCKED		0x4000u	/* Wait till portal's unlocked */
192 #define DPAA2_SWP_DESTROYED		0x8000u /* Terminate any operations */
193 
194 /* Command return codes. */
195 #define DPAA2_SWP_STAT_OK		0x0
196 #define DPAA2_SWP_STAT_NO_MEMORY	0x9	/* No memory available */
197 #define DPAA2_SWP_STAT_PORTAL_DISABLED	0xFD	/* QBMan portal disabled */
198 #define DPAA2_SWP_STAT_EINVAL		0xFE	/* Invalid argument */
199 #define DPAA2_SWP_STAT_ERR		0xFF	/* General error */
200 
201 #define DPAA2_EQ_DESC_SIZE		32u	/* Enqueue Command Descriptor */
202 #define DPAA2_FDR_DESC_SIZE		32u	/* Descriptor of the FDR */
203 #define DPAA2_FD_SIZE			32u	/* Frame Descriptor */
204 #define DPAA2_FDR_SIZE			64u	/* Frame Dequeue Response */
205 #define DPAA2_SCN_SIZE			16u	/* State Change Notification */
206 #define DPAA2_FA_SIZE			64u	/* SW Frame Annotation */
207 #define DPAA2_SGE_SIZE			16u	/* S/G table entry */
208 #define DPAA2_DQ_SIZE			64u	/* Dequeue Response */
209 #define DPAA2_SWP_CMD_SIZE		64u	/* SWP Command */
210 #define DPAA2_SWP_RSP_SIZE		64u	/* SWP Command Response */
211 
212 /* Opaque token for static dequeues. */
213 #define DPAA2_SWP_SDQCR_TOKEN		0xBBu
214 /* Opaque token for static dequeues. */
215 #define DPAA2_SWP_VDQCR_TOKEN		0xCCu
216 
217 #define DPAA2_SWP_LOCK(__swp, __flags) do {		\
218 	mtx_assert(&(__swp)->lock, MA_NOTOWNED);	\
219 	mtx_lock(&(__swp)->lock);			\
220 	*(__flags) = (__swp)->flags;			\
221 	(__swp)->flags |= DPAA2_SWP_LOCKED;		\
222 } while (0)
223 
224 #define DPAA2_SWP_UNLOCK(__swp) do {		\
225 	mtx_assert(&(__swp)->lock, MA_OWNED);	\
226 	(__swp)->flags &= ~DPAA2_SWP_LOCKED;	\
227 	mtx_unlock(&(__swp)->lock);		\
228 } while (0)
229 
230 enum dpaa2_fd_format {
231 	DPAA2_FD_SINGLE = 0,
232 	DPAA2_FD_LIST,
233 	DPAA2_FD_SG
234 };
235 
236 /**
237  * @brief Enqueue command descriptor.
238  */
239 struct dpaa2_eq_desc {
240 	uint8_t		verb;
241 	uint8_t		dca;
242 	uint16_t	seqnum;
243 	uint16_t	orpid;
244 	uint16_t	_reserved;
245 	uint32_t	tgtid;
246 	uint32_t	tag;
247 	uint16_t	qdbin;
248 	uint8_t		qpri;
249 	uint8_t		_reserved1[3];
250 	uint8_t		wae;
251 	uint8_t		rspid;
252 	uint64_t	rsp_addr;
253 } __packed;
254 CTASSERT(sizeof(struct dpaa2_eq_desc) == DPAA2_EQ_DESC_SIZE);
255 
256 /**
257  * @brief Frame Dequeue Response (FDR) descriptor.
258  */
259 struct dpaa2_fdr_desc {
260 	uint8_t		verb;
261 	uint8_t		stat;
262 	uint16_t	seqnum;
263 	uint16_t	oprid;
264 	uint8_t		_reserved;
265 	uint8_t		tok;
266 	uint32_t	fqid;
267 	uint32_t	_reserved1;
268 	uint32_t	fq_byte_cnt;
269 	uint32_t	fq_frm_cnt;
270 	uint64_t	fqd_ctx;
271 } __packed;
272 CTASSERT(sizeof(struct dpaa2_fdr_desc) == DPAA2_FDR_DESC_SIZE);
273 
274 /**
275  * @brief State Change Notification Message (SCNM).
276  */
277 struct dpaa2_scn {
278 	uint8_t		verb;
279 	uint8_t		stat;
280 	uint8_t		state;
281 	uint8_t		_reserved;
282 	uint32_t	rid_tok;
283 	uint64_t	ctx;
284 } __packed;
285 CTASSERT(sizeof(struct dpaa2_scn) == DPAA2_SCN_SIZE);
286 
287 /**
288  * @brief DPAA2 frame descriptor.
289  *
290  * addr:		Memory address of the start of the buffer holding the
291  *			frame data or the buffer containing the scatter/gather
292  *			list.
293  * data_length:		Length of the frame data (in bytes).
294  * bpid_ivp_bmt:	Buffer pool ID (14 bit + BMT bit + IVP bit)
295  * offset_fmt_sl:	Frame data offset, frame format and short-length fields.
296  * frame_ctx:		Frame context. This field allows the sender of a frame
297  *			to communicate some out-of-band information to the
298  *			receiver of the frame.
299  * ctrl:		Control bits (ERR, CBMT, ASAL, PTAC, DROPP, SC, DD).
300  * flow_ctx:		Frame flow context. Associates the frame with a flow
301  *			structure. QMan may use the FLC field for 3 purposes:
302  *			stashing control, order definition point identification,
303  *			and enqueue replication control.
304  */
305 struct dpaa2_fd {
306 	uint64_t	addr;
307 	uint32_t	data_length;
308 	uint16_t	bpid_ivp_bmt;
309 	uint16_t	offset_fmt_sl;
310 	uint32_t	frame_ctx;
311 	uint32_t	ctrl;
312 	uint64_t	flow_ctx;
313 } __packed;
314 CTASSERT(sizeof(struct dpaa2_fd) == DPAA2_FD_SIZE);
315 
316 /**
317  * @brief DPAA2 frame annotation.
318  */
319 struct dpaa2_fa {
320 	uint32_t		 magic;
321 	struct dpaa2_buf	*buf;
322 #ifdef __notyet__
323 	union {
324 		struct { /* Tx frame annotation */
325 			struct dpaa2_ni_tx_ring *tx;
326 		};
327 		struct { /* Rx frame annotation */
328 			uint64_t		 _notused;
329 		};
330 	};
331 #endif
332 } __packed;
333 CTASSERT(sizeof(struct dpaa2_fa) <= DPAA2_FA_SIZE);
334 
335 /**
336  * @brief DPAA2 scatter/gather entry.
337  */
338 struct dpaa2_sg_entry {
339 	uint64_t	addr;
340 	uint32_t	len;
341 	uint16_t	bpid;
342 	uint16_t	offset_fmt;
343 } __packed;
344 CTASSERT(sizeof(struct dpaa2_sg_entry) == DPAA2_SGE_SIZE);
345 
346 /**
347  * @brief Frame Dequeue Response (FDR).
348  */
349 struct dpaa2_fdr {
350 	struct dpaa2_fdr_desc	 desc;
351 	struct dpaa2_fd		 fd;
352 } __packed;
353 CTASSERT(sizeof(struct dpaa2_fdr) == DPAA2_FDR_SIZE);
354 
355 /**
356  * @brief Dequeue Response Message.
357  */
358 struct dpaa2_dq {
359 	union {
360 		struct {
361 			uint8_t	 verb;
362 			uint8_t	 _reserved[63];
363 		} common;
364 		struct dpaa2_fdr fdr; /* Frame Dequeue Response */
365 		struct dpaa2_scn scn; /* State Change Notification */
366 	};
367 } __packed;
368 CTASSERT(sizeof(struct dpaa2_dq) == DPAA2_DQ_SIZE);
369 
370 /**
371  * @brief Descriptor of the QBMan software portal.
372  *
373  * cena_res:		Unmapped cache-enabled part of the portal's I/O memory.
374  * cena_map:		Mapped cache-enabled part of the portal's I/O memory.
375  * cinh_res:		Unmapped cache-inhibited part of the portal's I/O memory.
376  * cinh_map:		Mapped cache-inhibited part of the portal's I/O memory.
377  *
378  * dpio_dev:		Device associated with the DPIO object to manage this
379  *			portal.
380  * swp_version:		Hardware IP version of the software portal.
381  * swp_clk:		QBMAN clock frequency value in Hz.
382  * swp_cycles_ratio:	How many 256 QBMAN cycles fit into one ns.
383  * swp_id:		Software portal ID.
384  *
385  * has_notif:		True if the notification mode is used.
386  * has_8prio:		True for a channel with 8 priority WQs. Ignored unless
387  *			"has_notif" is true.
388  */
389 struct dpaa2_swp_desc {
390 	struct resource		*cena_res;
391 	struct resource_map	*cena_map;
392 	struct resource		*cinh_res;
393 	struct resource_map	*cinh_map;
394 
395 	device_t		 dpio_dev;
396 	uint32_t		 swp_version;
397 	uint32_t		 swp_clk;
398 	uint32_t		 swp_cycles_ratio;
399 	uint16_t		 swp_id;
400 
401 	bool			 has_notif;
402 	bool			 has_8prio;
403 };
404 
405 /**
406  * @brief Command holds data to be written to the software portal.
407  */
408 struct dpaa2_swp_cmd {
409 	uint64_t	params[DPAA2_SWP_CMD_PARAMS_N];
410 };
411 CTASSERT(sizeof(struct dpaa2_swp_cmd) == DPAA2_SWP_CMD_SIZE);
412 
413 /**
414  * @brief Command response holds data received from the software portal.
415  */
416 struct dpaa2_swp_rsp {
417 	uint64_t	params[DPAA2_SWP_RSP_PARAMS_N];
418 };
419 CTASSERT(sizeof(struct dpaa2_swp_rsp) == DPAA2_SWP_RSP_SIZE);
420 
421 /**
422  * @brief QBMan software portal.
423  *
424  * res:		Unmapped cache-enabled and cache-inhibited parts of the portal.
425  * map:		Mapped cache-enabled and cache-inhibited parts of the portal.
426  * desc:	Descriptor of the QBMan software portal.
427  * lock:	Lock to guard an access to the portal.
428  * cv:		Conditional variable helps to wait for the helper object's state
429  *		change.
430  * flags:	Current state of the object.
431  * sdq:		Push dequeues status.
432  * mc:		Management commands data.
433  * mr:		Management response data.
434  * dqrr:	Dequeue Response Ring is used to issue frame dequeue responses
435  * 		from the QBMan to the driver.
436  * eqcr:	Enqueue Command Ring is used to issue frame enqueue commands
437  *		from the driver to the QBMan.
438  */
439 struct dpaa2_swp {
440 	struct resource		*cena_res;
441 	struct resource_map	*cena_map;
442 	struct resource		*cinh_res;
443 	struct resource_map	*cinh_map;
444 
445 	struct mtx		 lock;
446 	struct dpaa2_swp_desc	*desc;
447 	uint16_t		 flags;
448 
449 	/* Static Dequeue Command Register value (to obtain CDANs). */
450 	uint32_t		 sdq;
451 
452 	/* Volatile Dequeue Command (to obtain frames). */
453 	struct {
454 		uint32_t	 valid_bit; /* 0x00 or 0x80 */
455 	} vdq;
456 
457 	struct {
458 		bool		 atomic;
459 		bool		 writes_cinh;
460 		bool		 mem_backed;
461 	} cfg; /* Software portal configuration. */
462 
463 	struct {
464 		uint32_t	 valid_bit; /* 0x00 or 0x80 */
465 	} mc;
466 
467 	struct {
468 		uint32_t	 valid_bit; /* 0x00 or 0x80 */
469 	} mr;
470 
471 	struct {
472 		uint32_t	 next_idx;
473 		uint32_t	 valid_bit;
474 		uint8_t		 ring_size;
475 		bool		 reset_bug; /* dqrr reset workaround */
476 		uint32_t	 irq_threshold;
477 		uint32_t	 irq_itp;
478 	} dqrr;
479 
480 	struct {
481 		uint32_t	 pi; /* producer index */
482 		uint32_t	 pi_vb; /* PI valid bits */
483 		uint32_t	 pi_ring_size;
484 		uint32_t	 pi_ci_mask;
485 		uint32_t	 ci;
486 		int		 available;
487 		uint32_t	 pend;
488 		uint32_t	 no_pfdr;
489 	} eqcr;
490 };
491 
492 /* Management routines. */
493 int dpaa2_swp_init_portal(struct dpaa2_swp **swp, struct dpaa2_swp_desc *desc,
494     uint16_t flags);
495 void dpaa2_swp_free_portal(struct dpaa2_swp *swp);
496 uint32_t dpaa2_swp_set_cfg(uint8_t max_fill, uint8_t wn, uint8_t est,
497     uint8_t rpm, uint8_t dcm, uint8_t epm, int sd, int sp, int se, int dp,
498     int de, int ep);
499 
500 /* Read/write registers of a software portal. */
501 void dpaa2_swp_write_reg(struct dpaa2_swp *swp, uint32_t o, uint32_t v);
502 uint32_t dpaa2_swp_read_reg(struct dpaa2_swp *swp, uint32_t o);
503 
504 /* Helper routines. */
505 void dpaa2_swp_set_ed_norp(struct dpaa2_eq_desc *ed, bool resp_always);
506 void dpaa2_swp_set_ed_fq(struct dpaa2_eq_desc *ed, uint32_t fqid);
507 void dpaa2_swp_set_intr_trigger(struct dpaa2_swp *swp, uint32_t mask);
508 uint32_t dpaa2_swp_get_intr_trigger(struct dpaa2_swp *swp);
509 uint32_t dpaa2_swp_read_intr_status(struct dpaa2_swp *swp);
510 void dpaa2_swp_clear_intr_status(struct dpaa2_swp *swp, uint32_t mask);
511 void dpaa2_swp_set_push_dequeue(struct dpaa2_swp *swp, uint8_t chan_idx,
512     bool en);
513 int dpaa2_swp_set_irq_coalescing(struct dpaa2_swp *swp, uint32_t threshold,
514     uint32_t holdoff);
515 
516 /* Software portal commands. */
517 int dpaa2_swp_conf_wq_channel(struct dpaa2_swp *swp, uint16_t chan_id,
518     uint8_t we_mask, bool cdan_en, uint64_t ctx);
519 int dpaa2_swp_query_bp(struct dpaa2_swp *swp, uint16_t bpid,
520     struct dpaa2_bp_conf *conf);
521 int dpaa2_swp_release_bufs(struct dpaa2_swp *swp, uint16_t bpid, bus_addr_t *buf,
522     uint32_t buf_num);
523 int dpaa2_swp_dqrr_next_locked(struct dpaa2_swp *swp, struct dpaa2_dq *dq,
524     uint32_t *idx);
525 int dpaa2_swp_pull(struct dpaa2_swp *swp, uint16_t chan_id,
526     struct dpaa2_buf *buf, uint32_t frames_n);
527 int dpaa2_swp_enq(struct dpaa2_swp *swp, struct dpaa2_eq_desc *ed,
528     struct dpaa2_fd *fd);
529 int dpaa2_swp_enq_mult(struct dpaa2_swp *swp, struct dpaa2_eq_desc *ed,
530     struct dpaa2_fd *fd, uint32_t *flags, int frames_n);
531 
532 #endif /* _DPAA2_SWP_H */
533