1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause 3 * 4 * Copyright © 2021-2023 Dmitry Salychev 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25 * SUCH DAMAGE. 26 */ 27 28 #ifndef _DPAA2_SWP_H 29 #define _DPAA2_SWP_H 30 31 #include <sys/param.h> 32 #include <sys/systm.h> 33 #include <sys/bus.h> 34 35 #include "dpaa2_types.h" 36 #include "dpaa2_buf.h" 37 #include "dpaa2_bp.h" 38 #include "dpaa2_frame.h" 39 40 /* 41 * DPAA2 QBMan software portal. 42 */ 43 44 /* All QBMan commands and result structures use this "valid bit" encoding. */ 45 #define DPAA2_SWP_VALID_BIT ((uint32_t) 0x80) 46 47 #define DPAA2_SWP_TIMEOUT 100000 /* in us */ 48 #define DPAA2_SWP_CMD_PARAMS_N 8u 49 #define DPAA2_SWP_RSP_PARAMS_N 8u 50 51 /* 52 * Maximum number of buffers that can be acquired/released through a single 53 * QBMan command. 54 */ 55 #define DPAA2_SWP_BUFS_PER_CMD 7u 56 57 /* 58 * Number of times to retry DPIO portal operations while waiting for portal to 59 * finish executing current command and become available. 60 * 61 * We want to avoid being stuck in a while loop in case hardware becomes 62 * unresponsive, but not give up too easily if the portal really is busy for 63 * valid reasons. 64 */ 65 #define DPAA2_SWP_BUSY_RETRIES 1000 66 67 /* Versions of the QBMan software portals. */ 68 #define DPAA2_SWP_REV_4000 0x04000000 69 #define DPAA2_SWP_REV_4100 0x04010000 70 #define DPAA2_SWP_REV_4101 0x04010001 71 #define DPAA2_SWP_REV_5000 0x05000000 72 73 #define DPAA2_SWP_REV_MASK 0xFFFF0000 74 75 /* Registers in the cache-inhibited area of the software portal. */ 76 #define DPAA2_SWP_CINH_CR 0x600 /* Management Command reg.*/ 77 #define DPAA2_SWP_CINH_EQCR_PI 0x800 /* Enqueue Ring, Producer Index */ 78 #define DPAA2_SWP_CINH_EQCR_CI 0x840 /* Enqueue Ring, Consumer Index */ 79 #define DPAA2_SWP_CINH_CR_RT 0x900 /* CR Read Trigger */ 80 #define DPAA2_SWP_CINH_VDQCR_RT 0x940 /* VDQCR Read Trigger */ 81 #define DPAA2_SWP_CINH_EQCR_AM_RT 0x980 82 #define DPAA2_SWP_CINH_RCR_AM_RT 0x9C0 83 #define DPAA2_SWP_CINH_DQPI 0xA00 /* DQRR Producer Index reg. */ 84 #define DPAA2_SWP_CINH_DQRR_ITR 0xA80 /* DQRR interrupt timeout reg. */ 85 #define DPAA2_SWP_CINH_DCAP 0xAC0 /* DQRR Consumption Ack. reg. */ 86 #define DPAA2_SWP_CINH_SDQCR 0xB00 /* Static Dequeue Command reg. */ 87 #define DPAA2_SWP_CINH_EQCR_AM_RT2 0xB40 88 #define DPAA2_SWP_CINH_RCR_PI 0xC00 /* Release Ring, Producer Index */ 89 #define DPAA2_SWP_CINH_RAR 0xCC0 /* Release Array Allocation reg. */ 90 #define DPAA2_SWP_CINH_CFG 0xD00 91 #define DPAA2_SWP_CINH_ISR 0xE00 92 #define DPAA2_SWP_CINH_IER 0xE40 93 #define DPAA2_SWP_CINH_ISDR 0xE80 94 #define DPAA2_SWP_CINH_IIR 0xEC0 95 #define DPAA2_SWP_CINH_ITPR 0xF40 96 97 /* Registers in the cache-enabled area of the software portal. */ 98 #define DPAA2_SWP_CENA_EQCR(n) (0x000 + ((uint32_t)(n) << 6)) 99 #define DPAA2_SWP_CENA_DQRR(n) (0x200 + ((uint32_t)(n) << 6)) 100 #define DPAA2_SWP_CENA_RCR(n) (0x400 + ((uint32_t)(n) << 6)) 101 #define DPAA2_SWP_CENA_CR (0x600) /* Management Command reg. */ 102 #define DPAA2_SWP_CENA_RR(vb) (0x700 + ((uint32_t)(vb) >> 1)) 103 #define DPAA2_SWP_CENA_VDQCR (0x780) 104 #define DPAA2_SWP_CENA_EQCR_CI (0x840) 105 106 /* Registers in the cache-enabled area of the software portal (memory-backed). */ 107 #define DPAA2_SWP_CENA_DQRR_MEM(n) (0x0800 + ((uint32_t)(n) << 6)) 108 #define DPAA2_SWP_CENA_RCR_MEM(n) (0x1400 + ((uint32_t)(n) << 6)) 109 #define DPAA2_SWP_CENA_CR_MEM (0x1600) /* Management Command reg. */ 110 #define DPAA2_SWP_CENA_RR_MEM (0x1680) /* Management Response reg. */ 111 #define DPAA2_SWP_CENA_VDQCR_MEM (0x1780) 112 #define DPAA2_SWP_CENA_EQCR_CI_MEMBACK (0x1840) 113 114 /* Shifts in the portal's configuration register. */ 115 #define DPAA2_SWP_CFG_DQRR_MF_SHIFT 20 116 #define DPAA2_SWP_CFG_EST_SHIFT 16 117 #define DPAA2_SWP_CFG_CPBS_SHIFT 15 118 #define DPAA2_SWP_CFG_WN_SHIFT 14 119 #define DPAA2_SWP_CFG_RPM_SHIFT 12 120 #define DPAA2_SWP_CFG_DCM_SHIFT 10 121 #define DPAA2_SWP_CFG_EPM_SHIFT 8 122 #define DPAA2_SWP_CFG_VPM_SHIFT 7 123 #define DPAA2_SWP_CFG_CPM_SHIFT 6 124 #define DPAA2_SWP_CFG_SD_SHIFT 5 125 #define DPAA2_SWP_CFG_SP_SHIFT 4 126 #define DPAA2_SWP_CFG_SE_SHIFT 3 127 #define DPAA2_SWP_CFG_DP_SHIFT 2 128 #define DPAA2_SWP_CFG_DE_SHIFT 1 129 #define DPAA2_SWP_CFG_EP_SHIFT 0 130 131 /* Static Dequeue Command Register attribute codes */ 132 #define DPAA2_SDQCR_FC_SHIFT 29 /* Dequeue Command Frame Count */ 133 #define DPAA2_SDQCR_FC_MASK 0x1 134 #define DPAA2_SDQCR_DCT_SHIFT 24 /* Dequeue Command Type */ 135 #define DPAA2_SDQCR_DCT_MASK 0x3 136 #define DPAA2_SDQCR_TOK_SHIFT 16 /* Dequeue Command Token */ 137 #define DPAA2_SDQCR_TOK_MASK 0xff 138 #define DPAA2_SDQCR_SRC_SHIFT 0 /* Dequeue Source */ 139 #define DPAA2_SDQCR_SRC_MASK 0xffff 140 141 /* 142 * Read trigger bit is used to trigger QMan to read a command from memory, 143 * without having software perform a cache flush to force a write of the command 144 * to QMan. 145 * 146 * NOTE: Implemented in QBMan 5.0 or above. 147 */ 148 #define DPAA2_SWP_RT_MODE ((uint32_t)0x100) 149 150 /* Interrupt Enable Register bits. */ 151 #define DPAA2_SWP_INTR_EQRI 0x01 152 #define DPAA2_SWP_INTR_EQDI 0x02 153 #define DPAA2_SWP_INTR_DQRI 0x04 154 #define DPAA2_SWP_INTR_RCRI 0x08 155 #define DPAA2_SWP_INTR_RCDI 0x10 156 #define DPAA2_SWP_INTR_VDCI 0x20 157 158 /* "Write Enable" bitmask for a command to configure SWP WQ Channel.*/ 159 #define DPAA2_WQCHAN_WE_EN (0x1u) /* Enable CDAN generation */ 160 #define DPAA2_WQCHAN_WE_ICD (0x2u) /* Interrupt Coalescing Disable */ 161 #define DPAA2_WQCHAN_WE_CTX (0x4u) 162 163 /* Definitions for parsing DQRR entries. */ 164 #define DPAA2_DQRR_RESULT_MASK (0x7Fu) 165 #define DPAA2_DQRR_RESULT_DQ (0x60u) 166 #define DPAA2_DQRR_RESULT_FQRN (0x21u) 167 #define DPAA2_DQRR_RESULT_FQRNI (0x22u) 168 #define DPAA2_DQRR_RESULT_FQPN (0x24u) 169 #define DPAA2_DQRR_RESULT_FQDAN (0x25u) 170 #define DPAA2_DQRR_RESULT_CDAN (0x26u) 171 #define DPAA2_DQRR_RESULT_CSCN_MEM (0x27u) 172 #define DPAA2_DQRR_RESULT_CGCU (0x28u) 173 #define DPAA2_DQRR_RESULT_BPSCN (0x29u) 174 #define DPAA2_DQRR_RESULT_CSCN_WQ (0x2au) 175 176 /* Frame dequeue statuses */ 177 #define DPAA2_DQ_STAT_FQEMPTY (0x80u) /* FQ is empty */ 178 #define DPAA2_DQ_STAT_HELDACTIVE (0x40u) /* FQ is held active */ 179 #define DPAA2_DQ_STAT_FORCEELIGIBLE (0x20u) /* FQ force eligible */ 180 #define DPAA2_DQ_STAT_VALIDFRAME (0x10u) /* valid frame */ 181 #define DPAA2_DQ_STAT_ODPVALID (0x04u) /* FQ ODP enable */ 182 #define DPAA2_DQ_STAT_VOLATILE (0x02u) /* volatile dequeue (VDC) */ 183 #define DPAA2_DQ_STAT_EXPIRED (0x01u) /* VDC is expired */ 184 185 /* 186 * Portal flags. 187 * 188 * TODO: Use the same flags for both MC and software portals. 189 */ 190 #define DPAA2_SWP_DEF 0x0u 191 #define DPAA2_SWP_NOWAIT_ALLOC 0x2u /* Do not sleep during init */ 192 #define DPAA2_SWP_LOCKED 0x4000u /* Wait till portal's unlocked */ 193 #define DPAA2_SWP_DESTROYED 0x8000u /* Terminate any operations */ 194 195 /* Command return codes. */ 196 #define DPAA2_SWP_STAT_OK 0x0 197 #define DPAA2_SWP_STAT_NO_MEMORY 0x9 /* No memory available */ 198 #define DPAA2_SWP_STAT_PORTAL_DISABLED 0xFD /* QBMan portal disabled */ 199 #define DPAA2_SWP_STAT_EINVAL 0xFE /* Invalid argument */ 200 #define DPAA2_SWP_STAT_ERR 0xFF /* General error */ 201 202 #define DPAA2_EQ_DESC_SIZE 32u /* Enqueue Command Descriptor */ 203 #define DPAA2_FDR_DESC_SIZE 32u /* Descriptor of the FDR */ 204 #define DPAA2_FDR_SIZE 64u /* Frame Dequeue Response */ 205 #define DPAA2_SCN_SIZE 16u /* State Change Notification */ 206 #define DPAA2_SGE_SIZE 16u /* S/G table entry */ 207 #define DPAA2_DQ_SIZE 64u /* Dequeue Response */ 208 #define DPAA2_SWP_CMD_SIZE 64u /* SWP Command */ 209 #define DPAA2_SWP_RSP_SIZE 64u /* SWP Command Response */ 210 211 /* Opaque token for static dequeues. */ 212 #define DPAA2_SWP_SDQCR_TOKEN 0xBBu 213 /* Opaque token for static dequeues. */ 214 #define DPAA2_SWP_VDQCR_TOKEN 0xCCu 215 216 #define DPAA2_SWP_LOCK(__swp, __flags) do { \ 217 mtx_assert(&(__swp)->lock, MA_NOTOWNED); \ 218 mtx_lock(&(__swp)->lock); \ 219 *(__flags) = (__swp)->flags; \ 220 (__swp)->flags |= DPAA2_SWP_LOCKED; \ 221 } while (0) 222 223 #define DPAA2_SWP_UNLOCK(__swp) do { \ 224 mtx_assert(&(__swp)->lock, MA_OWNED); \ 225 (__swp)->flags &= ~DPAA2_SWP_LOCKED; \ 226 mtx_unlock(&(__swp)->lock); \ 227 } while (0) 228 229 enum dpaa2_fd_format { 230 DPAA2_FD_SINGLE = 0, 231 DPAA2_FD_LIST, 232 DPAA2_FD_SG 233 }; 234 235 /** 236 * @brief Enqueue command descriptor. 237 */ 238 struct dpaa2_eq_desc { 239 uint8_t verb; 240 uint8_t dca; 241 uint16_t seqnum; 242 uint16_t orpid; 243 uint16_t _reserved; 244 uint32_t tgtid; 245 uint32_t tag; 246 uint16_t qdbin; 247 uint8_t qpri; 248 uint8_t _reserved1[3]; 249 uint8_t wae; 250 uint8_t rspid; 251 uint64_t rsp_addr; 252 } __packed; 253 CTASSERT(sizeof(struct dpaa2_eq_desc) == DPAA2_EQ_DESC_SIZE); 254 255 /** 256 * @brief Frame Dequeue Response (FDR) descriptor. 257 */ 258 struct dpaa2_fdr_desc { 259 uint8_t verb; 260 uint8_t stat; 261 uint16_t seqnum; 262 uint16_t oprid; 263 uint8_t _reserved; 264 uint8_t tok; 265 uint32_t fqid; 266 uint32_t _reserved1; 267 uint32_t fq_byte_cnt; 268 uint32_t fq_frm_cnt; 269 uint64_t fqd_ctx; 270 } __packed; 271 CTASSERT(sizeof(struct dpaa2_fdr_desc) == DPAA2_FDR_DESC_SIZE); 272 273 /** 274 * @brief State Change Notification Message (SCNM). 275 */ 276 struct dpaa2_scn { 277 uint8_t verb; 278 uint8_t stat; 279 uint8_t state; 280 uint8_t _reserved; 281 uint32_t rid_tok; 282 uint64_t ctx; 283 } __packed; 284 CTASSERT(sizeof(struct dpaa2_scn) == DPAA2_SCN_SIZE); 285 286 /** 287 * @brief DPAA2 scatter/gather entry. 288 */ 289 struct dpaa2_sg_entry { 290 uint64_t addr; 291 uint32_t len; 292 uint16_t bpid; 293 uint16_t offset_fmt; 294 } __packed; 295 CTASSERT(sizeof(struct dpaa2_sg_entry) == DPAA2_SGE_SIZE); 296 297 /** 298 * @brief Frame Dequeue Response (FDR). 299 */ 300 struct dpaa2_fdr { 301 struct dpaa2_fdr_desc desc; 302 struct dpaa2_fd fd; 303 } __packed; 304 CTASSERT(sizeof(struct dpaa2_fdr) == DPAA2_FDR_SIZE); 305 306 /** 307 * @brief Dequeue Response Message. 308 */ 309 struct dpaa2_dq { 310 union { 311 struct { 312 uint8_t verb; 313 uint8_t _reserved[63]; 314 } common; 315 struct dpaa2_fdr fdr; /* Frame Dequeue Response */ 316 struct dpaa2_scn scn; /* State Change Notification */ 317 }; 318 } __packed; 319 CTASSERT(sizeof(struct dpaa2_dq) == DPAA2_DQ_SIZE); 320 321 /** 322 * @brief Descriptor of the QBMan software portal. 323 * 324 * cena_res: Unmapped cache-enabled part of the portal's I/O memory. 325 * cena_map: Mapped cache-enabled part of the portal's I/O memory. 326 * cinh_res: Unmapped cache-inhibited part of the portal's I/O memory. 327 * cinh_map: Mapped cache-inhibited part of the portal's I/O memory. 328 * 329 * dpio_dev: Device associated with the DPIO object to manage this 330 * portal. 331 * swp_version: Hardware IP version of the software portal. 332 * swp_clk: QBMAN clock frequency value in Hz. 333 * swp_cycles_ratio: How many 256 QBMAN cycles fit into one ns. 334 * swp_id: Software portal ID. 335 * 336 * has_notif: True if the notification mode is used. 337 * has_8prio: True for a channel with 8 priority WQs. Ignored unless 338 * "has_notif" is true. 339 */ 340 struct dpaa2_swp_desc { 341 struct resource *cena_res; 342 struct resource_map *cena_map; 343 struct resource *cinh_res; 344 struct resource_map *cinh_map; 345 346 device_t dpio_dev; 347 uint32_t swp_version; 348 uint32_t swp_clk; 349 uint32_t swp_cycles_ratio; 350 uint16_t swp_id; 351 352 bool has_notif; 353 bool has_8prio; 354 }; 355 356 /** 357 * @brief Command holds data to be written to the software portal. 358 */ 359 struct dpaa2_swp_cmd { 360 uint64_t params[DPAA2_SWP_CMD_PARAMS_N]; 361 }; 362 CTASSERT(sizeof(struct dpaa2_swp_cmd) == DPAA2_SWP_CMD_SIZE); 363 364 /** 365 * @brief Command response holds data received from the software portal. 366 */ 367 struct dpaa2_swp_rsp { 368 uint64_t params[DPAA2_SWP_RSP_PARAMS_N]; 369 }; 370 CTASSERT(sizeof(struct dpaa2_swp_rsp) == DPAA2_SWP_RSP_SIZE); 371 372 /** 373 * @brief QBMan software portal. 374 * 375 * res: Unmapped cache-enabled and cache-inhibited parts of the portal. 376 * map: Mapped cache-enabled and cache-inhibited parts of the portal. 377 * desc: Descriptor of the QBMan software portal. 378 * lock: Lock to guard an access to the portal. 379 * cv: Conditional variable helps to wait for the helper object's state 380 * change. 381 * flags: Current state of the object. 382 * sdq: Push dequeues status. 383 * mc: Management commands data. 384 * mr: Management response data. 385 * dqrr: Dequeue Response Ring is used to issue frame dequeue responses 386 * from the QBMan to the driver. 387 * eqcr: Enqueue Command Ring is used to issue frame enqueue commands 388 * from the driver to the QBMan. 389 */ 390 struct dpaa2_swp { 391 struct resource *cena_res; 392 struct resource_map *cena_map; 393 struct resource *cinh_res; 394 struct resource_map *cinh_map; 395 396 struct mtx lock; 397 struct dpaa2_swp_desc *desc; 398 uint16_t flags; 399 400 /* Static Dequeue Command Register value (to obtain CDANs). */ 401 uint32_t sdq; 402 403 /* Volatile Dequeue Command (to obtain frames). */ 404 struct { 405 uint32_t valid_bit; /* 0x00 or 0x80 */ 406 } vdq; 407 408 struct { 409 bool atomic; 410 bool writes_cinh; 411 bool mem_backed; 412 } cfg; /* Software portal configuration. */ 413 414 struct { 415 uint32_t valid_bit; /* 0x00 or 0x80 */ 416 } mc; 417 418 struct { 419 uint32_t valid_bit; /* 0x00 or 0x80 */ 420 } mr; 421 422 struct { 423 uint32_t next_idx; 424 uint32_t valid_bit; 425 uint8_t ring_size; 426 bool reset_bug; /* dqrr reset workaround */ 427 uint32_t irq_threshold; 428 uint32_t irq_itp; 429 } dqrr; 430 431 struct { 432 uint32_t pi; /* producer index */ 433 uint32_t pi_vb; /* PI valid bits */ 434 uint32_t pi_ring_size; 435 uint32_t pi_ci_mask; 436 uint32_t ci; 437 int available; 438 uint32_t pend; 439 uint32_t no_pfdr; 440 } eqcr; 441 }; 442 443 /* Management routines. */ 444 int dpaa2_swp_init_portal(struct dpaa2_swp **swp, struct dpaa2_swp_desc *desc, 445 uint16_t flags); 446 void dpaa2_swp_free_portal(struct dpaa2_swp *swp); 447 uint32_t dpaa2_swp_set_cfg(uint8_t max_fill, uint8_t wn, uint8_t est, 448 uint8_t rpm, uint8_t dcm, uint8_t epm, int sd, int sp, int se, int dp, 449 int de, int ep); 450 451 /* Read/write registers of a software portal. */ 452 void dpaa2_swp_write_reg(struct dpaa2_swp *swp, uint32_t o, uint32_t v); 453 uint32_t dpaa2_swp_read_reg(struct dpaa2_swp *swp, uint32_t o); 454 455 /* Helper routines. */ 456 void dpaa2_swp_set_ed_norp(struct dpaa2_eq_desc *ed, bool resp_always); 457 void dpaa2_swp_set_ed_fq(struct dpaa2_eq_desc *ed, uint32_t fqid); 458 void dpaa2_swp_set_intr_trigger(struct dpaa2_swp *swp, uint32_t mask); 459 uint32_t dpaa2_swp_get_intr_trigger(struct dpaa2_swp *swp); 460 uint32_t dpaa2_swp_read_intr_status(struct dpaa2_swp *swp); 461 void dpaa2_swp_clear_intr_status(struct dpaa2_swp *swp, uint32_t mask); 462 void dpaa2_swp_set_push_dequeue(struct dpaa2_swp *swp, uint8_t chan_idx, 463 bool en); 464 int dpaa2_swp_set_irq_coalescing(struct dpaa2_swp *swp, uint32_t threshold, 465 uint32_t holdoff); 466 467 /* Software portal commands. */ 468 int dpaa2_swp_conf_wq_channel(struct dpaa2_swp *swp, uint16_t chan_id, 469 uint8_t we_mask, bool cdan_en, uint64_t ctx); 470 int dpaa2_swp_query_bp(struct dpaa2_swp *swp, uint16_t bpid, 471 struct dpaa2_bp_conf *conf); 472 int dpaa2_swp_release_bufs(struct dpaa2_swp *swp, uint16_t bpid, bus_addr_t *buf, 473 uint32_t buf_num); 474 int dpaa2_swp_dqrr_next_locked(struct dpaa2_swp *swp, struct dpaa2_dq *dq, 475 uint32_t *idx); 476 int dpaa2_swp_pull(struct dpaa2_swp *swp, uint16_t chan_id, 477 struct dpaa2_buf *buf, uint32_t frames_n); 478 int dpaa2_swp_enq(struct dpaa2_swp *swp, struct dpaa2_eq_desc *ed, 479 struct dpaa2_fd *fd); 480 int dpaa2_swp_enq_mult(struct dpaa2_swp *swp, struct dpaa2_eq_desc *ed, 481 struct dpaa2_fd *fd, uint32_t *flags, int frames_n); 482 483 #endif /* _DPAA2_SWP_H */ 484