1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause 3 * 4 * Copyright © 2021-2023 Dmitry Salychev 5 * Copyright © 2022 Mathew McBride 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29 #ifndef _DPAA2_NI_H 30 #define _DPAA2_NI_H 31 32 #include <sys/rman.h> 33 #include <sys/bus.h> 34 #include <sys/queue.h> 35 #include <sys/taskqueue.h> 36 #include <sys/mbuf.h> 37 #include <sys/param.h> 38 #include <sys/socket.h> 39 #include <sys/buf_ring.h> 40 #include <sys/proc.h> 41 #include <sys/lock.h> 42 #include <sys/mutex.h> 43 44 #include <net/if.h> 45 #include <net/ethernet.h> 46 #include <net/if_media.h> 47 48 #include "dpaa2_types.h" 49 #include "dpaa2_mcp.h" 50 #include "dpaa2_swp.h" 51 #include "dpaa2_io.h" 52 #include "dpaa2_mac.h" 53 #include "dpaa2_ni_dpkg.h" 54 #include "dpaa2_channel.h" 55 56 /* Name of the DPAA2 network interface. */ 57 #define DPAA2_NI_IFNAME "dpni" 58 59 /* Maximum resources per DPNI: 16 DPIOs + 16 DPCONs + 1 DPBP + 1 DPMCP. */ 60 #define DPAA2_NI_MAX_RESOURCES 34 61 62 #define DPAA2_NI_MSI_COUNT 1 /* MSIs per DPNI */ 63 #define DPAA2_NI_MAX_POOLS 8 /* buffer pools per DPNI */ 64 65 #define DPAA2_NI_BUFS_INIT (5u * DPAA2_SWP_BUFS_PER_CMD) 66 67 /* Maximum number of buffers allocated per Tx ring. */ 68 #define DPAA2_NI_BUFS_PER_TX (1 << 7) 69 #define DPAA2_NI_MAX_BPTX (1 << 8) 70 71 /* Number of the DPNI statistics counters. */ 72 #define DPAA2_NI_STAT_COUNTERS 7u 73 #define DPAA2_NI_STAT_SYSCTLS 9u 74 75 /* Error and status bits in the frame annotation status word. */ 76 #define DPAA2_NI_FAS_DISC 0x80000000 /* debug frame */ 77 #define DPAA2_NI_FAS_MS 0x40000000 /* MACSEC frame */ 78 #define DPAA2_NI_FAS_PTP 0x08000000 79 #define DPAA2_NI_FAS_MC 0x04000000 /* Ethernet multicast frame */ 80 #define DPAA2_NI_FAS_BC 0x02000000 /* Ethernet broadcast frame */ 81 #define DPAA2_NI_FAS_KSE 0x00040000 82 #define DPAA2_NI_FAS_EOFHE 0x00020000 83 #define DPAA2_NI_FAS_MNLE 0x00010000 84 #define DPAA2_NI_FAS_TIDE 0x00008000 85 #define DPAA2_NI_FAS_PIEE 0x00004000 86 #define DPAA2_NI_FAS_FLE 0x00002000 /* Frame length error */ 87 #define DPAA2_NI_FAS_FPE 0x00001000 /* Frame physical error */ 88 #define DPAA2_NI_FAS_PTE 0x00000080 89 #define DPAA2_NI_FAS_ISP 0x00000040 90 #define DPAA2_NI_FAS_PHE 0x00000020 91 #define DPAA2_NI_FAS_BLE 0x00000010 92 #define DPAA2_NI_FAS_L3CV 0x00000008 /* L3 csum validation performed */ 93 #define DPAA2_NI_FAS_L3CE 0x00000004 /* L3 csum error */ 94 #define DPAA2_NI_FAS_L4CV 0x00000002 /* L4 csum validation performed */ 95 #define DPAA2_NI_FAS_L4CE 0x00000001 /* L4 csum error */ 96 97 /* Mask for errors on the ingress path. */ 98 #define DPAA2_NI_FAS_RX_ERR_MASK (DPAA2_NI_FAS_KSE | \ 99 DPAA2_NI_FAS_EOFHE | \ 100 DPAA2_NI_FAS_MNLE | \ 101 DPAA2_NI_FAS_TIDE | \ 102 DPAA2_NI_FAS_PIEE | \ 103 DPAA2_NI_FAS_FLE | \ 104 DPAA2_NI_FAS_FPE | \ 105 DPAA2_NI_FAS_PTE | \ 106 DPAA2_NI_FAS_ISP | \ 107 DPAA2_NI_FAS_PHE | \ 108 DPAA2_NI_FAS_BLE | \ 109 DPAA2_NI_FAS_L3CE | \ 110 DPAA2_NI_FAS_L4CE \ 111 ) 112 113 /* Option bits to select specific queue configuration options to apply. */ 114 #define DPAA2_NI_QUEUE_OPT_USER_CTX 0x00000001 115 #define DPAA2_NI_QUEUE_OPT_DEST 0x00000002 116 #define DPAA2_NI_QUEUE_OPT_FLC 0x00000004 117 #define DPAA2_NI_QUEUE_OPT_HOLD_ACTIVE 0x00000008 118 #define DPAA2_NI_QUEUE_OPT_SET_CGID 0x00000040 119 #define DPAA2_NI_QUEUE_OPT_CLEAR_CGID 0x00000080 120 121 /* DPNI link configuration options. */ 122 #define DPAA2_NI_LINK_OPT_AUTONEG ((uint64_t) 0x01u) 123 #define DPAA2_NI_LINK_OPT_HALF_DUPLEX ((uint64_t) 0x02u) 124 #define DPAA2_NI_LINK_OPT_PAUSE ((uint64_t) 0x04u) 125 #define DPAA2_NI_LINK_OPT_ASYM_PAUSE ((uint64_t) 0x08u) 126 #define DPAA2_NI_LINK_OPT_PFC_PAUSE ((uint64_t) 0x10u) 127 128 /* 129 * Number of times to retry a frame enqueue before giving up. Value determined 130 * empirically, in order to minimize the number of frames dropped on Tx. 131 */ 132 #define DPAA2_NI_ENQUEUE_RETRIES 10 133 134 /* Channel storage buffer configuration */ 135 #define DPAA2_ETH_STORE_FRAMES 16u 136 #define DPAA2_ETH_STORE_SIZE \ 137 ((DPAA2_ETH_STORE_FRAMES + 1) * sizeof(struct dpaa2_dq)) 138 139 /* 140 * NOTE: Don't forget to update dpaa2_ni_spec in case of any changes in macros! 141 */ 142 /* DPMCP resources */ 143 #define DPAA2_NI_MCP_RES_NUM (1u) 144 #define DPAA2_NI_MCP_RID_OFF (0u) 145 #define DPAA2_NI_MCP_RID(rid) ((rid) + DPAA2_NI_MCP_RID_OFF) 146 /* DPIO resources (software portals) */ 147 #define DPAA2_NI_IO_RES_NUM (16u) 148 #define DPAA2_NI_IO_RID_OFF (DPAA2_NI_MCP_RID_OFF + DPAA2_NI_MCP_RES_NUM) 149 #define DPAA2_NI_IO_RID(rid) ((rid) + DPAA2_NI_IO_RID_OFF) 150 /* DPBP resources (buffer pools) */ 151 #define DPAA2_NI_BP_RES_NUM (1u) 152 #define DPAA2_NI_BP_RID_OFF (DPAA2_NI_IO_RID_OFF + DPAA2_NI_IO_RES_NUM) 153 #define DPAA2_NI_BP_RID(rid) ((rid) + DPAA2_NI_BP_RID_OFF) 154 /* DPCON resources (channels) */ 155 #define DPAA2_NI_CON_RES_NUM (16u) 156 #define DPAA2_NI_CON_RID_OFF (DPAA2_NI_BP_RID_OFF + DPAA2_NI_BP_RES_NUM) 157 #define DPAA2_NI_CON_RID(rid) ((rid) + DPAA2_NI_CON_RID_OFF) 158 159 enum dpaa2_ni_dest_type { 160 DPAA2_NI_DEST_NONE = 0, 161 DPAA2_NI_DEST_DPIO, 162 DPAA2_NI_DEST_DPCON 163 }; 164 165 enum dpaa2_ni_ofl_type { 166 DPAA2_NI_OFL_RX_L3_CSUM = 0, 167 DPAA2_NI_OFL_RX_L4_CSUM, 168 DPAA2_NI_OFL_TX_L3_CSUM, 169 DPAA2_NI_OFL_TX_L4_CSUM, 170 DPAA2_NI_OFL_FLCTYPE_HASH /* FD flow context for AIOP/CTLU */ 171 }; 172 173 /** 174 * @brief DPNI ingress traffic distribution mode. 175 */ 176 enum dpaa2_ni_dist_mode { 177 DPAA2_NI_DIST_MODE_NONE = 0, 178 DPAA2_NI_DIST_MODE_HASH, 179 DPAA2_NI_DIST_MODE_FS 180 }; 181 182 /** 183 * @brief DPNI behavior in case of errors. 184 */ 185 enum dpaa2_ni_err_action { 186 DPAA2_NI_ERR_DISCARD = 0, 187 DPAA2_NI_ERR_CONTINUE, 188 DPAA2_NI_ERR_SEND_TO_ERROR_QUEUE 189 }; 190 191 struct dpaa2_channel; 192 struct dpaa2_ni_fq; 193 194 /** 195 * @brief Attributes of the DPNI object. 196 * 197 * options: ... 198 * wriop_ver: Revision of the underlying WRIOP hardware block. 199 */ 200 struct dpaa2_ni_attr { 201 uint32_t options; 202 uint16_t wriop_ver; 203 struct { 204 uint16_t fs; 205 uint8_t mac; 206 uint8_t vlan; 207 uint8_t qos; 208 } entries; 209 struct { 210 uint8_t queues; 211 uint8_t rx_tcs; 212 uint8_t tx_tcs; 213 uint8_t channels; 214 uint8_t cgs; 215 } num; 216 struct { 217 uint8_t fs; 218 uint8_t qos; 219 } key_size; 220 }; 221 222 /** 223 * @brief Configuration of the network interface queue. 224 * 225 * NOTE: This configuration is used to obtain information of a queue by 226 * DPNI_GET_QUEUE command and update it by DPNI_SET_QUEUE one. 227 * 228 * It includes binding of the queue to a DPIO or DPCON object to receive 229 * notifications and traffic on the CPU. 230 * 231 * user_ctx: (r/w) User defined data, presented along with the frames 232 * being dequeued from this queue. 233 * flow_ctx: (r/w) Set default FLC value for traffic dequeued from this queue. 234 * Please check description of FD structure for more information. 235 * Note that FLC values set using DPNI_ADD_FS_ENTRY, if any, take 236 * precedence over values per queue. 237 * dest_id: (r/w) The ID of a DPIO or DPCON object, depending on 238 * DEST_TYPE (in flags) value. This field is ignored for DEST_TYPE 239 * set to 0 (DPNI_DEST_NONE). 240 * fqid: (r) Frame queue ID, can be used to enqueue/dequeue or execute 241 * other commands on the queue through DPIO. Note that Tx queues 242 * are logical queues and not all management commands are available 243 * on these queue types. 244 * qdbin: (r) Queue destination bin. Can be used with the DPIO enqueue 245 * operation based on QDID, QDBIN and QPRI. 246 * type: Type of the queue to set configuration to. 247 * tc: Traffic class. Ignored for QUEUE_TYPE 2 and 3 (Tx confirmation 248 * and Rx error queues). 249 * idx: Selects a specific queue out of the set of queues in a TC. 250 * Accepted values are in range 0 to NUM_QUEUES–1. This field is 251 * ignored for QUEUE_TYPE 3 (Rx error queue). For access to the 252 * shared Tx confirmation queue (for Tx confirmation mode 1), this 253 * field must be set to 0xff. 254 * cgid: (r/w) Congestion group ID. 255 * chan_id: (w) Channel index to be configured. Used only when QUEUE_TYPE is 256 * set to DPNI_QUEUE_TX. 257 * priority: (r/w) Sets the priority in the destination DPCON or DPIO for 258 * dequeued traffic. Supported values are 0 to # of priorities in 259 * destination DPCON or DPIO - 1. This field is ignored for 260 * DEST_TYPE set to 0 (DPNI_DEST_NONE), except if this DPNI is in 261 * AIOP context. In that case the DPNI_SET_QUEUE can be used to 262 * override the default assigned priority of the FQ from the TC. 263 * options: Option bits selecting specific configuration options to apply. 264 * See DPAA2_NI_QUEUE_OPT_* for details. 265 * dest_type: Type of destination for dequeued traffic. 266 * cgid_valid: (r) Congestion group ID is valid. 267 * stash_control: (r/w) If true, lowest 6 bits of FLC are used for stash control. 268 * Please check description of FD structure for more information. 269 * hold_active: (r/w) If true, this flag prevents the queue from being 270 * rescheduled between DPIOs while it carries traffic and is active 271 * on one DPIO. Can help reduce reordering if one queue is services 272 * on multiple CPUs, but the queue is also more likely to be trapped 273 * in one DPIO, especially when congested. 274 */ 275 struct dpaa2_ni_queue_cfg { 276 uint64_t user_ctx; 277 uint64_t flow_ctx; 278 uint32_t dest_id; 279 uint32_t fqid; 280 uint16_t qdbin; 281 enum dpaa2_ni_queue_type type; 282 uint8_t tc; 283 uint8_t idx; 284 uint8_t cgid; 285 uint8_t chan_id; 286 uint8_t priority; 287 uint8_t options; 288 289 enum dpaa2_ni_dest_type dest_type; 290 bool cgid_valid; 291 bool stash_control; 292 bool hold_active; 293 }; 294 295 /** 296 * @brief Buffer layout attributes. 297 * 298 * pd_size: Size kept for private data (in bytes). 299 * fd_align: Frame data alignment. 300 * head_size: Data head room. 301 * tail_size: Data tail room. 302 * options: ... 303 * pass_timestamp: Timestamp is included in the buffer layout. 304 * pass_parser_result: Parsing results are included in the buffer layout. 305 * pass_frame_status: Frame status is included in the buffer layout. 306 * pass_sw_opaque: SW annotation is activated. 307 * queue_type: Type of a queue this configuration applies to. 308 */ 309 struct dpaa2_ni_buf_layout { 310 uint16_t pd_size; 311 uint16_t fd_align; 312 uint16_t head_size; 313 uint16_t tail_size; 314 uint16_t options; 315 bool pass_timestamp; 316 bool pass_parser_result; 317 bool pass_frame_status; 318 bool pass_sw_opaque; 319 enum dpaa2_ni_queue_type queue_type; 320 }; 321 322 /** 323 * @brief Buffer pools configuration for a network interface. 324 */ 325 struct dpaa2_ni_pools_cfg { 326 uint8_t pools_num; 327 struct { 328 uint32_t bp_obj_id; 329 uint16_t buf_sz; 330 int backup_flag; /* 0 - regular pool, 1 - backup pool */ 331 } pools[DPAA2_NI_MAX_POOLS]; 332 }; 333 334 /** 335 * @brief Errors behavior configuration for a network interface. 336 * 337 * err_mask: The errors mask to configure. 338 * action: Desired action for the errors selected in the mask. 339 * set_err_fas: Set to true to mark the errors in frame annotation 340 * status (FAS); relevant for non-discard actions only. 341 */ 342 struct dpaa2_ni_err_cfg { 343 uint32_t err_mask; 344 enum dpaa2_ni_err_action action; 345 bool set_err_fas; 346 }; 347 348 /** 349 * @brief Link configuration. 350 * 351 * options: Mask of available options. 352 * adv_speeds: Speeds that are advertised for autoneg. 353 * rate: Rate in Mbps. 354 */ 355 struct dpaa2_ni_link_cfg { 356 uint64_t options; 357 uint64_t adv_speeds; 358 uint32_t rate; 359 }; 360 361 /** 362 * @brief Link state. 363 * 364 * options: Mask of available options. 365 * adv_speeds: Speeds that are advertised for autoneg. 366 * sup_speeds: Speeds capability of the PHY. 367 * rate: Rate in Mbps. 368 * link_up: Link state (true if link is up, false otherwise). 369 * state_valid: Ignore/Update the state of the link. 370 */ 371 struct dpaa2_ni_link_state { 372 uint64_t options; 373 uint64_t adv_speeds; 374 uint64_t sup_speeds; 375 uint32_t rate; 376 bool link_up; 377 bool state_valid; 378 }; 379 380 /** 381 * @brief QoS table configuration. 382 * 383 * kcfg_busaddr: Address of the buffer in I/O virtual address space which 384 * holds the QoS table key configuration. 385 * default_tc: Default traffic class to use in case of a lookup miss in 386 * the QoS table. 387 * discard_on_miss: Set to true to discard frames in case of no match. 388 * Default traffic class will be used otherwise. 389 * keep_entries: Set to true to keep existing QoS table entries. This 390 * option will work properly only for DPNI objects created 391 * with DPNI_OPT_HAS_KEY_MASKING option. 392 */ 393 struct dpaa2_ni_qos_table { 394 uint64_t kcfg_busaddr; 395 uint8_t default_tc; 396 bool discard_on_miss; 397 bool keep_entries; 398 }; 399 400 /** 401 * @brief Context to add multicast physical addresses to the filter table. 402 * 403 * ifp: Network interface associated with the context. 404 * error: Result of the last MC command. 405 * nent: Number of entries added. 406 */ 407 struct dpaa2_ni_mcaddr_ctx { 408 struct ifnet *ifp; 409 int error; 410 int nent; 411 }; 412 413 struct dpaa2_eth_dist_fields { 414 uint64_t rxnfc_field; 415 enum net_prot cls_prot; 416 int cls_field; 417 int size; 418 uint64_t id; 419 }; 420 421 struct dpni_mask_cfg { 422 uint8_t mask; 423 uint8_t offset; 424 } __packed; 425 426 struct dpni_dist_extract { 427 uint8_t prot; 428 uint8_t efh_type; /* EFH type is in the 4 LSBs. */ 429 uint8_t size; 430 uint8_t offset; 431 uint32_t field; 432 uint8_t hdr_index; 433 uint8_t constant; 434 uint8_t num_of_repeats; 435 uint8_t num_of_byte_masks; 436 uint8_t extract_type; /* Extraction type is in the 4 LSBs */ 437 uint8_t _reserved[3]; 438 struct dpni_mask_cfg masks[4]; 439 } __packed; 440 441 struct dpni_ext_set_rx_tc_dist { 442 uint8_t num_extracts; 443 uint8_t _reserved[7]; 444 struct dpni_dist_extract extracts[DPKG_MAX_NUM_OF_EXTRACTS]; 445 } __packed; 446 447 /** 448 * @brief Software context for the DPAA2 Network Interface driver. 449 */ 450 struct dpaa2_ni_softc { 451 device_t dev; 452 struct resource *res[DPAA2_NI_MAX_RESOURCES]; 453 uint16_t api_major; 454 uint16_t api_minor; 455 uint64_t rx_hash_fields; 456 uint16_t tx_data_off; 457 uint16_t tx_qdid; 458 uint32_t link_options; 459 int link_state; 460 461 uint16_t buf_align; 462 uint16_t buf_sz; 463 464 uint64_t rx_anomaly_frames; 465 uint64_t rx_single_buf_frames; 466 uint64_t rx_sg_buf_frames; 467 uint64_t rx_enq_rej_frames; 468 uint64_t rx_ieoi_err_frames; 469 uint64_t tx_single_buf_frames; 470 uint64_t tx_sg_frames; 471 472 struct dpaa2_ni_attr attr; 473 474 struct ifnet *ifp; 475 uint32_t if_flags; 476 struct mtx lock; 477 device_t miibus; 478 struct mii_data *mii; 479 bool fixed_link; 480 struct ifmedia fixed_ifmedia; 481 int media_status; 482 483 bus_dma_tag_t rxd_dmat; /* for Rx distribution key */ 484 bus_dma_tag_t qos_dmat; /* for QoS table key */ 485 486 struct dpaa2_buf qos_kcfg; /* QoS table key config */ 487 struct dpaa2_buf rxd_kcfg; /* Rx distribution key config */ 488 489 uint32_t chan_n; 490 struct dpaa2_channel *channels[DPAA2_MAX_CHANNELS]; 491 struct dpaa2_ni_fq rxe_queue; /* one per DPNI */ 492 493 struct dpaa2_atomic buf_num; 494 struct dpaa2_atomic buf_free; /* for sysctl(9) only */ 495 496 int irq_rid[DPAA2_NI_MSI_COUNT]; 497 struct resource *irq_res; 498 void *intr; 499 500 struct taskqueue *bp_taskq; 501 502 struct callout mii_callout; 503 504 struct { 505 uint32_t dpmac_id; 506 uint8_t addr[ETHER_ADDR_LEN]; 507 device_t phy_dev; 508 int phy_loc; 509 } mac; /* Info about connected DPMAC (if exists) */ 510 }; 511 512 extern struct resource_spec dpaa2_ni_spec[]; 513 514 #endif /* _DPAA2_NI_H */ 515