1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause 3 * 4 * Copyright © 2021-2022 Dmitry Salychev 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25 * SUCH DAMAGE. 26 */ 27 28 #ifndef _DPAA2_MCP_H 29 #define _DPAA2_MCP_H 30 31 #include <sys/rman.h> 32 #include <sys/condvar.h> 33 #include <sys/mutex.h> 34 35 #include "dpaa2_types.h" 36 37 /* 38 * DPAA2 MC command interface helper routines. 39 */ 40 41 #define DPAA2_PORTAL_TIMEOUT 100000 /* us */ 42 #define DPAA2_MCP_MEM_WIDTH 0x40 /* Minimal size of the MC portal. */ 43 #define DPAA2_MCP_MAX_RESOURCES 1 /* resources per DPMCP: 1 SYS_MEM */ 44 45 /* 46 * Portal flags. 47 * 48 * TODO: Use the same flags for both MC and software portals. 49 */ 50 #define DPAA2_PORTAL_DEF 0x0u 51 #define DPAA2_PORTAL_NOWAIT_ALLOC 0x2u /* Do not sleep during init */ 52 #define DPAA2_PORTAL_LOCKED 0x4000u /* Wait till portal's unlocked */ 53 #define DPAA2_PORTAL_DESTROYED 0x8000u /* Terminate any operations */ 54 55 /* Command flags. */ 56 #define DPAA2_CMD_DEF 0x0u 57 #define DPAA2_CMD_HIGH_PRIO 0x80u /* High priority command */ 58 #define DPAA2_CMD_INTR_DIS 0x100u /* Disable cmd finished intr */ 59 #define DPAA2_CMD_NOWAIT_ALLOC 0x8000u /* Do not sleep during init */ 60 61 /* DPAA2 command return codes. */ 62 #define DPAA2_CMD_STAT_OK 0x0 /* Set by MC on success */ 63 #define DPAA2_CMD_STAT_READY 0x1 /* Ready to be processed */ 64 #define DPAA2_CMD_STAT_AUTH_ERR 0x3 /* Illegal object-portal-icid */ 65 #define DPAA2_CMD_STAT_NO_PRIVILEGE 0x4 /* No privilege */ 66 #define DPAA2_CMD_STAT_DMA_ERR 0x5 /* DMA or I/O error */ 67 #define DPAA2_CMD_STAT_CONFIG_ERR 0x6 /* Invalid/conflicting params */ 68 #define DPAA2_CMD_STAT_TIMEOUT 0x7 /* Command timed out */ 69 #define DPAA2_CMD_STAT_NO_RESOURCE 0x8 /* No DPAA2 resources */ 70 #define DPAA2_CMD_STAT_NO_MEMORY 0x9 /* No memory available */ 71 #define DPAA2_CMD_STAT_BUSY 0xA /* Device is busy */ 72 #define DPAA2_CMD_STAT_UNSUPPORTED_OP 0xB /* Unsupported operation */ 73 #define DPAA2_CMD_STAT_INVALID_STATE 0xC /* Invalid state */ 74 /* Driver-specific return codes. */ 75 #define DPAA2_CMD_STAT_UNKNOWN_OBJ 0xFD /* Unknown DPAA2 object. */ 76 #define DPAA2_CMD_STAT_EINVAL 0xFE /* Invalid argument */ 77 #define DPAA2_CMD_STAT_ERR 0xFF /* General error */ 78 79 /* Object's memory region flags. */ 80 #define DPAA2_RC_REG_CACHEABLE 0x1 /* Cacheable memory mapping */ 81 82 #define DPAA2_HW_FLAG_HIGH_PRIO 0x80u 83 #define DPAA2_SW_FLAG_INTR_DIS 0x01u 84 85 #define DPAA2_CMD_PARAMS_N 7u 86 #define DPAA2_LABEL_SZ 16 87 88 /* ------------------------- MNG command IDs -------------------------------- */ 89 #define CMD_MNG_BASE_VERSION 1 90 #define CMD_MNG_ID_OFFSET 4 91 92 #define CMD_MNG(id) (((id) << CMD_MNG_ID_OFFSET) | CMD_MNG_BASE_VERSION) 93 94 #define CMDID_MNG_GET_VER CMD_MNG(0x831) 95 #define CMDID_MNG_GET_SOC_VER CMD_MNG(0x832) 96 #define CMDID_MNG_GET_CONT_ID CMD_MNG(0x830) 97 98 /* ------------------------- DPRC command IDs ------------------------------- */ 99 #define CMD_RC_BASE_VERSION 1 100 #define CMD_RC_2ND_VERSION 2 101 #define CMD_RC_3RD_VERSION 3 102 #define CMD_RC_ID_OFFSET 4 103 104 #define CMD_RC(id) (((id) << CMD_RC_ID_OFFSET) | CMD_RC_BASE_VERSION) 105 #define CMD_RC_V2(id) (((id) << CMD_RC_ID_OFFSET) | CMD_RC_2ND_VERSION) 106 #define CMD_RC_V3(id) (((id) << CMD_RC_ID_OFFSET) | CMD_RC_3RD_VERSION) 107 108 #define CMDID_RC_OPEN CMD_RC(0x805) 109 #define CMDID_RC_CLOSE CMD_RC(0x800) 110 #define CMDID_RC_GET_API_VERSION CMD_RC(0xA05) 111 #define CMDID_RC_GET_ATTR CMD_RC(0x004) 112 #define CMDID_RC_RESET_CONT CMD_RC(0x005) 113 #define CMDID_RC_RESET_CONT_V2 CMD_RC_V2(0x005) 114 #define CMDID_RC_SET_IRQ CMD_RC(0x010) 115 #define CMDID_RC_SET_IRQ_ENABLE CMD_RC(0x012) 116 #define CMDID_RC_SET_IRQ_MASK CMD_RC(0x014) 117 #define CMDID_RC_GET_IRQ_STATUS CMD_RC(0x016) 118 #define CMDID_RC_CLEAR_IRQ_STATUS CMD_RC(0x017) 119 #define CMDID_RC_GET_CONT_ID CMD_RC(0x830) 120 #define CMDID_RC_GET_OBJ_COUNT CMD_RC(0x159) 121 #define CMDID_RC_GET_OBJ CMD_RC(0x15A) 122 #define CMDID_RC_GET_OBJ_DESC CMD_RC(0x162) 123 #define CMDID_RC_GET_OBJ_REG CMD_RC(0x15E) 124 #define CMDID_RC_GET_OBJ_REG_V2 CMD_RC_V2(0x15E) 125 #define CMDID_RC_GET_OBJ_REG_V3 CMD_RC_V3(0x15E) 126 #define CMDID_RC_SET_OBJ_IRQ CMD_RC(0x15F) 127 #define CMDID_RC_GET_CONN CMD_RC(0x16C) 128 129 /* ------------------------- DPIO command IDs ------------------------------- */ 130 #define CMD_IO_BASE_VERSION 1 131 #define CMD_IO_ID_OFFSET 4 132 133 #define CMD_IO(id) (((id) << CMD_IO_ID_OFFSET) | CMD_IO_BASE_VERSION) 134 135 #define CMDID_IO_OPEN CMD_IO(0x803) 136 #define CMDID_IO_CLOSE CMD_IO(0x800) 137 #define CMDID_IO_ENABLE CMD_IO(0x002) 138 #define CMDID_IO_DISABLE CMD_IO(0x003) 139 #define CMDID_IO_GET_ATTR CMD_IO(0x004) 140 #define CMDID_IO_RESET CMD_IO(0x005) 141 #define CMDID_IO_SET_IRQ_ENABLE CMD_IO(0x012) 142 #define CMDID_IO_SET_IRQ_MASK CMD_IO(0x014) 143 #define CMDID_IO_GET_IRQ_STATUS CMD_IO(0x016) 144 #define CMDID_IO_ADD_STATIC_DQ_CHAN CMD_IO(0x122) 145 146 /* ------------------------- DPNI command IDs ------------------------------- */ 147 #define CMD_NI_BASE_VERSION 1 148 #define CMD_NI_2ND_VERSION 2 149 #define CMD_NI_4TH_VERSION 4 150 #define CMD_NI_ID_OFFSET 4 151 152 #define CMD_NI(id) (((id) << CMD_NI_ID_OFFSET) | CMD_NI_BASE_VERSION) 153 #define CMD_NI_V2(id) (((id) << CMD_NI_ID_OFFSET) | CMD_NI_2ND_VERSION) 154 #define CMD_NI_V4(id) (((id) << CMD_NI_ID_OFFSET) | CMD_NI_4TH_VERSION) 155 156 #define CMDID_NI_OPEN CMD_NI(0x801) 157 #define CMDID_NI_CLOSE CMD_NI(0x800) 158 #define CMDID_NI_ENABLE CMD_NI(0x002) 159 #define CMDID_NI_DISABLE CMD_NI(0x003) 160 #define CMDID_NI_GET_API_VER CMD_NI(0xA01) 161 #define CMDID_NI_RESET CMD_NI(0x005) 162 #define CMDID_NI_GET_ATTR CMD_NI(0x004) 163 #define CMDID_NI_SET_BUF_LAYOUT CMD_NI(0x265) 164 #define CMDID_NI_GET_TX_DATA_OFF CMD_NI(0x212) 165 #define CMDID_NI_GET_PORT_MAC_ADDR CMD_NI(0x263) 166 #define CMDID_NI_SET_PRIM_MAC_ADDR CMD_NI(0x224) 167 #define CMDID_NI_GET_PRIM_MAC_ADDR CMD_NI(0x225) 168 #define CMDID_NI_SET_LINK_CFG CMD_NI(0x21A) 169 #define CMDID_NI_GET_LINK_CFG CMD_NI(0x278) 170 #define CMDID_NI_GET_LINK_STATE CMD_NI(0x215) 171 #define CMDID_NI_SET_QOS_TABLE CMD_NI(0x240) 172 #define CMDID_NI_CLEAR_QOS_TABLE CMD_NI(0x243) 173 #define CMDID_NI_SET_POOLS CMD_NI(0x200) 174 #define CMDID_NI_SET_ERR_BEHAVIOR CMD_NI(0x20B) 175 #define CMDID_NI_GET_QUEUE CMD_NI(0x25F) 176 #define CMDID_NI_SET_QUEUE CMD_NI(0x260) 177 #define CMDID_NI_GET_QDID CMD_NI(0x210) 178 #define CMDID_NI_ADD_MAC_ADDR CMD_NI(0x226) 179 #define CMDID_NI_REMOVE_MAC_ADDR CMD_NI(0x227) 180 #define CMDID_NI_CLEAR_MAC_FILTERS CMD_NI(0x228) 181 #define CMDID_NI_SET_MFL CMD_NI(0x216) 182 #define CMDID_NI_SET_OFFLOAD CMD_NI(0x26C) 183 #define CMDID_NI_SET_IRQ_MASK CMD_NI(0x014) 184 #define CMDID_NI_SET_IRQ_ENABLE CMD_NI(0x012) 185 #define CMDID_NI_GET_IRQ_STATUS CMD_NI(0x016) 186 #define CMDID_NI_SET_UNI_PROMISC CMD_NI(0x222) 187 #define CMDID_NI_SET_MULTI_PROMISC CMD_NI(0x220) 188 #define CMDID_NI_GET_STATISTICS CMD_NI(0x25D) 189 #define CMDID_NI_SET_RX_TC_DIST CMD_NI(0x235) 190 191 /* ------------------------- DPBP command IDs ------------------------------- */ 192 #define CMD_BP_BASE_VERSION 1 193 #define CMD_BP_ID_OFFSET 4 194 195 #define CMD_BP(id) (((id) << CMD_BP_ID_OFFSET) | CMD_BP_BASE_VERSION) 196 197 #define CMDID_BP_OPEN CMD_BP(0x804) 198 #define CMDID_BP_CLOSE CMD_BP(0x800) 199 #define CMDID_BP_ENABLE CMD_BP(0x002) 200 #define CMDID_BP_DISABLE CMD_BP(0x003) 201 #define CMDID_BP_GET_ATTR CMD_BP(0x004) 202 #define CMDID_BP_RESET CMD_BP(0x005) 203 204 /* ------------------------- DPMAC command IDs ------------------------------ */ 205 #define CMD_MAC_BASE_VERSION 1 206 #define CMD_MAC_2ND_VERSION 2 207 #define CMD_MAC_ID_OFFSET 4 208 209 #define CMD_MAC(id) (((id) << CMD_MAC_ID_OFFSET) | CMD_MAC_BASE_VERSION) 210 #define CMD_MAC_V2(id) (((id) << CMD_MAC_ID_OFFSET) | CMD_MAC_2ND_VERSION) 211 212 #define CMDID_MAC_OPEN CMD_MAC(0x80C) 213 #define CMDID_MAC_CLOSE CMD_MAC(0x800) 214 #define CMDID_MAC_RESET CMD_MAC(0x005) 215 #define CMDID_MAC_MDIO_READ CMD_MAC(0x0C0) 216 #define CMDID_MAC_MDIO_WRITE CMD_MAC(0x0C1) 217 #define CMDID_MAC_GET_ADDR CMD_MAC(0x0C5) 218 #define CMDID_MAC_GET_ATTR CMD_MAC(0x004) 219 #define CMDID_MAC_SET_LINK_STATE CMD_MAC_V2(0x0C3) 220 #define CMDID_MAC_SET_IRQ_MASK CMD_MAC(0x014) 221 #define CMDID_MAC_SET_IRQ_ENABLE CMD_MAC(0x012) 222 #define CMDID_MAC_GET_IRQ_STATUS CMD_MAC(0x016) 223 224 /* ------------------------- DPCON command IDs ------------------------------ */ 225 #define CMD_CON_BASE_VERSION 1 226 #define CMD_CON_ID_OFFSET 4 227 228 #define CMD_CON(id) (((id) << CMD_CON_ID_OFFSET) | CMD_CON_BASE_VERSION) 229 230 #define CMDID_CON_OPEN CMD_CON(0x808) 231 #define CMDID_CON_CLOSE CMD_CON(0x800) 232 #define CMDID_CON_ENABLE CMD_CON(0x002) 233 #define CMDID_CON_DISABLE CMD_CON(0x003) 234 #define CMDID_CON_GET_ATTR CMD_CON(0x004) 235 #define CMDID_CON_RESET CMD_CON(0x005) 236 #define CMDID_CON_SET_NOTIF CMD_CON(0x100) 237 238 /* ------------------------- DPMCP command IDs ------------------------------ */ 239 #define CMD_MCP_BASE_VERSION 1 240 #define CMD_MCP_2ND_VERSION 2 241 #define CMD_MCP_ID_OFFSET 4 242 243 #define CMD_MCP(id) (((id) << CMD_MCP_ID_OFFSET) | CMD_MCP_BASE_VERSION) 244 #define CMD_MCP_V2(id) (((id) << CMD_MCP_ID_OFFSET) | CMD_MCP_2ND_VERSION) 245 246 #define CMDID_MCP_CREATE CMD_MCP_V2(0x90B) 247 #define CMDID_MCP_DESTROY CMD_MCP(0x98B) 248 #define CMDID_MCP_OPEN CMD_MCP(0x80B) 249 #define CMDID_MCP_CLOSE CMD_MCP(0x800) 250 #define CMDID_MCP_RESET CMD_MCP(0x005) 251 252 #define DPAA2_MCP_LOCK(__mcp, __flags) do { \ 253 mtx_assert(&(__mcp)->lock, MA_NOTOWNED); \ 254 mtx_lock(&(__mcp)->lock); \ 255 *(__flags) = (__mcp)->flags; \ 256 (__mcp)->flags |= DPAA2_PORTAL_LOCKED; \ 257 } while (0) 258 259 #define DPAA2_MCP_UNLOCK(__mcp) do { \ 260 mtx_assert(&(__mcp)->lock, MA_OWNED); \ 261 (__mcp)->flags &= ~DPAA2_PORTAL_LOCKED; \ 262 mtx_unlock(&(__mcp)->lock); \ 263 } while (0) 264 265 enum dpaa2_rc_region_type { 266 DPAA2_RC_REG_MC_PORTAL, 267 DPAA2_RC_REG_QBMAN_PORTAL 268 }; 269 270 /** 271 * @brief Helper object to interact with the MC portal. 272 * 273 * res: Unmapped portal's I/O memory. 274 * map: Mapped portal's I/O memory. 275 * lock: Lock to send a command to the portal and wait for the 276 * result. 277 * flags: Current state of the object. 278 * rc_api_major: Major version of the DPRC API. 279 * rc_api_minor: Minor version of the DPRC API. 280 */ 281 struct dpaa2_mcp { 282 struct resource *res; 283 struct resource_map *map; 284 struct mtx lock; 285 uint16_t flags; 286 uint16_t rc_api_major; 287 uint16_t rc_api_minor; 288 }; 289 290 /** 291 * @brief Command object holds data to be written to the MC portal. 292 * 293 * header: 8 least significant bytes of the MC portal. 294 * params: Parameters to pass together with the command to MC. Might keep 295 * command execution results. 296 * 297 * NOTE: 64 bytes. 298 */ 299 struct dpaa2_cmd { 300 uint64_t header; 301 uint64_t params[DPAA2_CMD_PARAMS_N]; 302 }; 303 304 /** 305 * @brief Helper object to access fields of the MC command header. 306 * 307 * srcid: The SoC architected source ID of the submitter. This field is 308 * reserved and cannot be written by the driver. 309 * flags_hw: Bits from 8 to 15 of the command header. Most of them are 310 * reserved at the moment. 311 * status: Command ready/status. This field is used as the handshake field 312 * between MC and the driver. MC reports command completion with 313 * success/error codes in this field. 314 * flags_sw: ... 315 * token: ... 316 * cmdid: ... 317 * 318 * NOTE: 8 bytes. 319 */ 320 struct dpaa2_cmd_header { 321 uint8_t srcid; 322 uint8_t flags_hw; 323 uint8_t status; 324 uint8_t flags_sw; 325 uint16_t token; 326 uint16_t cmdid; 327 } __packed; 328 329 /** 330 * @brief Information about DPAA2 object. 331 * 332 * id: ID of a logical object resource. 333 * vendor: Object vendor identifier. 334 * irq_count: Number of interrupts supported by the object. 335 * reg_count: Number of mappable regions supported by the object. 336 * state: Object state (combination of states). 337 * ver_major: Major version of the object. 338 * ver_minor: Minor version of the object. 339 * flags: Object attributes flags. 340 * type: ... 341 * label: ... 342 */ 343 struct dpaa2_obj { 344 uint32_t id; 345 uint16_t vendor; 346 uint8_t irq_count; 347 uint8_t reg_count; 348 uint32_t state; 349 uint16_t ver_major; 350 uint16_t ver_minor; 351 uint16_t flags; 352 uint8_t label[DPAA2_LABEL_SZ]; 353 enum dpaa2_dev_type type; 354 }; 355 356 /** 357 * @brief Attributes of the DPRC object. 358 * 359 * cont_id: Container ID. 360 * portal_id: Container's portal ID. 361 * options: Container's options as set at container's creation. 362 * icid: Container's isolation context ID. 363 */ 364 struct dpaa2_rc_attr { 365 uint32_t cont_id; 366 uint32_t portal_id; 367 uint32_t options; 368 uint32_t icid; 369 }; 370 371 /** 372 * @brief Description of the object's memory region. 373 * 374 * base_paddr: Region base physical address. 375 * base_offset: Region base offset. 376 * size: Region size (in bytes). 377 * flags: Region flags (cacheable, etc.) 378 * type: Type of a software portal this region belongs to. 379 */ 380 struct dpaa2_rc_obj_region { 381 uint64_t base_paddr; 382 uint64_t base_offset; 383 uint32_t size; 384 uint32_t flags; 385 enum dpaa2_rc_region_type type; 386 }; 387 388 /** 389 * @brief DPAA2 endpoint descriptor. 390 * 391 * obj_id: Endpoint object ID. 392 * if_id: Interface ID; for endpoints with multiple interfaces 393 * (DPSW, DPDMUX), 0 - otherwise. 394 * type: Endpoint object type, null-terminated string. 395 */ 396 struct dpaa2_ep_desc { 397 uint32_t obj_id; 398 uint32_t if_id; 399 enum dpaa2_dev_type type; 400 }; 401 402 /** 403 * @brief Configuration of the channel data availability notification (CDAN). 404 * 405 * qman_ctx: Context value provided with each CDAN message. 406 * dpio_id: DPIO object ID configured with a notification channel. 407 * prior: Priority selection within the DPIO channel; valid values 408 * are 0-7, depending on the number of priorities in that channel. 409 */ 410 struct dpaa2_con_notif_cfg { 411 uint64_t qman_ctx; 412 uint32_t dpio_id; 413 uint8_t prior; 414 }; 415 416 /** 417 * @brief Attributes of the DPMCP object. 418 * 419 * id: DPMCP object ID. 420 * options: Options of the MC portal (disabled high-prio commands, etc.). 421 */ 422 struct dpaa2_mcp_attr { 423 uint32_t id; 424 uint32_t options; 425 }; 426 427 /** 428 * @brief Software context for the DPAA2 MC portal. 429 */ 430 struct dpaa2_mcp_softc { 431 device_t dev; 432 struct dpaa2_mcp_attr attr; 433 434 struct resource *res[DPAA2_MCP_MAX_RESOURCES]; 435 struct resource_map map[DPAA2_MCP_MAX_RESOURCES]; 436 }; 437 438 int dpaa2_mcp_init_portal(struct dpaa2_mcp **mcp, struct resource *res, 439 struct resource_map *map, uint16_t flags); 440 void dpaa2_mcp_free_portal(struct dpaa2_mcp *mcp); 441 442 /* to quickly update command token */ 443 struct dpaa2_cmd *dpaa2_mcp_tk(struct dpaa2_cmd *cmd, const uint16_t token); 444 /* to quickly update command flags */ 445 struct dpaa2_cmd *dpaa2_mcp_f(struct dpaa2_cmd *cmd, const uint16_t flags); 446 447 #define DPAA2_CMD_INIT_FLAGS(__cmd, __flags) do { \ 448 KASSERT((__cmd) != NULL, ("%s:%d: failed", __func__, __LINE__)); \ 449 struct dpaa2_cmd_header *__hdr; \ 450 uint32_t __dcpi; \ 451 \ 452 __hdr = (struct dpaa2_cmd_header *)&((__cmd)->header); \ 453 __hdr->srcid = 0; \ 454 __hdr->status = DPAA2_CMD_STAT_OK; \ 455 __hdr->token = 0; \ 456 __hdr->cmdid = 0; \ 457 __hdr->flags_hw = DPAA2_CMD_DEF; \ 458 __hdr->flags_sw = DPAA2_CMD_DEF; \ 459 if ((__flags) & DPAA2_CMD_HIGH_PRIO) { \ 460 __hdr->flags_hw |= DPAA2_HW_FLAG_HIGH_PRIO; \ 461 } \ 462 if ((__flags) & DPAA2_CMD_INTR_DIS) { \ 463 __hdr->flags_sw |= DPAA2_SW_FLAG_INTR_DIS; \ 464 } \ 465 for (__dcpi = 0; __dcpi < DPAA2_CMD_PARAMS_N; __dcpi++) { \ 466 (__cmd)->params[__dcpi] = 0; \ 467 } \ 468 } while (0) 469 #define DPAA2_CMD_INIT(c) DPAA2_CMD_INIT_FLAGS((c), DPAA2_CMD_DEF) 470 #define DPAA2_CMD_TK(c, t) dpaa2_mcp_tk((c), (t)) 471 #define DPAA2_CMD_F(c, f) dpaa2_mcp_f((c), (f)) 472 473 #endif /* _DPAA2_MCP_H */ 474