1 /*- 2 * Copyright (c) 1997, 1998, 1999 3 * Bill Paul <wpaul@ee.columbia.edu>. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 3. All advertising materials mentioning features or use of this software 14 * must display the following acknowledgement: 15 * This product includes software developed by Bill Paul. 16 * 4. Neither the name of the author nor the names of any co-contributors 17 * may be used to endorse or promote products derived from this software 18 * without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30 * THE POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33 #include <sys/cdefs.h> 34 __FBSDID("$FreeBSD$"); 35 36 /* 37 * DEC "tulip" clone ethernet driver. Supports the DEC/Intel 21143 38 * series chips and several workalikes including the following: 39 * 40 * Macronix 98713/98715/98725/98727/98732 PMAC (www.macronix.com) 41 * Macronix/Lite-On 82c115 PNIC II (www.macronix.com) 42 * Lite-On 82c168/82c169 PNIC (www.litecom.com) 43 * ASIX Electronics AX88140A (www.asix.com.tw) 44 * ASIX Electronics AX88141 (www.asix.com.tw) 45 * ADMtek AL981 (www.admtek.com.tw) 46 * ADMtek AN983 (www.admtek.com.tw) 47 * ADMtek CardBus AN985 (www.admtek.com.tw) 48 * Netgear FA511 (www.netgear.com) Appears to be rebadged ADMTek CardBus AN985 49 * Davicom DM9100, DM9102, DM9102A (www.davicom8.com) 50 * Accton EN1217 (www.accton.com) 51 * Xircom X3201 (www.xircom.com) 52 * Abocom FE2500 53 * Conexant LANfinity (www.conexant.com) 54 * 3Com OfficeConnect 10/100B 3CSOHO100B (www.3com.com) 55 * 56 * Datasheets for the 21143 are available at developer.intel.com. 57 * Datasheets for the clone parts can be found at their respective sites. 58 * (Except for the PNIC; see www.freebsd.org/~wpaul/PNIC/pnic.ps.gz.) 59 * The PNIC II is essentially a Macronix 98715A chip; the only difference 60 * worth noting is that its multicast hash table is only 128 bits wide 61 * instead of 512. 62 * 63 * Written by Bill Paul <wpaul@ee.columbia.edu> 64 * Electrical Engineering Department 65 * Columbia University, New York City 66 */ 67 /* 68 * The Intel 21143 is the successor to the DEC 21140. It is basically 69 * the same as the 21140 but with a few new features. The 21143 supports 70 * three kinds of media attachments: 71 * 72 * o MII port, for 10Mbps and 100Mbps support and NWAY 73 * autonegotiation provided by an external PHY. 74 * o SYM port, for symbol mode 100Mbps support. 75 * o 10baseT port. 76 * o AUI/BNC port. 77 * 78 * The 100Mbps SYM port and 10baseT port can be used together in 79 * combination with the internal NWAY support to create a 10/100 80 * autosensing configuration. 81 * 82 * Note that not all tulip workalikes are handled in this driver: we only 83 * deal with those which are relatively well behaved. The Winbond is 84 * handled separately due to its different register offsets and the 85 * special handling needed for its various bugs. The PNIC is handled 86 * here, but I'm not thrilled about it. 87 * 88 * All of the workalike chips use some form of MII transceiver support 89 * with the exception of the Macronix chips, which also have a SYM port. 90 * The ASIX AX88140A is also documented to have a SYM port, but all 91 * the cards I've seen use an MII transceiver, probably because the 92 * AX88140A doesn't support internal NWAY. 93 */ 94 95 #ifdef HAVE_KERNEL_OPTION_HEADERS 96 #include "opt_device_polling.h" 97 #endif 98 99 #include <sys/param.h> 100 #include <sys/endian.h> 101 #include <sys/systm.h> 102 #include <sys/sockio.h> 103 #include <sys/mbuf.h> 104 #include <sys/malloc.h> 105 #include <sys/kernel.h> 106 #include <sys/module.h> 107 #include <sys/socket.h> 108 109 #include <net/if.h> 110 #include <net/if_var.h> 111 #include <net/if_arp.h> 112 #include <net/ethernet.h> 113 #include <net/if_dl.h> 114 #include <net/if_media.h> 115 #include <net/if_types.h> 116 #include <net/if_vlan_var.h> 117 118 #include <net/bpf.h> 119 120 #include <machine/bus.h> 121 #include <machine/resource.h> 122 #include <sys/bus.h> 123 #include <sys/rman.h> 124 125 #include <dev/mii/mii.h> 126 #include <dev/mii/mii_bitbang.h> 127 #include <dev/mii/miivar.h> 128 129 #include <dev/pci/pcireg.h> 130 #include <dev/pci/pcivar.h> 131 132 #define DC_USEIOSPACE 133 134 #include <dev/dc/if_dcreg.h> 135 136 #ifdef __sparc64__ 137 #include <dev/ofw/openfirm.h> 138 #include <machine/ofw_machdep.h> 139 #endif 140 141 MODULE_DEPEND(dc, pci, 1, 1, 1); 142 MODULE_DEPEND(dc, ether, 1, 1, 1); 143 MODULE_DEPEND(dc, miibus, 1, 1, 1); 144 145 /* 146 * "device miibus" is required in kernel config. See GENERIC if you get 147 * errors here. 148 */ 149 #include "miibus_if.h" 150 151 /* 152 * Various supported device vendors/types and their names. 153 */ 154 static const struct dc_type dc_devs[] = { 155 { DC_DEVID(DC_VENDORID_DEC, DC_DEVICEID_21143), 0, 156 "Intel 21143 10/100BaseTX" }, 157 { DC_DEVID(DC_VENDORID_DAVICOM, DC_DEVICEID_DM9009), 0, 158 "Davicom DM9009 10/100BaseTX" }, 159 { DC_DEVID(DC_VENDORID_DAVICOM, DC_DEVICEID_DM9100), 0, 160 "Davicom DM9100 10/100BaseTX" }, 161 { DC_DEVID(DC_VENDORID_DAVICOM, DC_DEVICEID_DM9102), DC_REVISION_DM9102A, 162 "Davicom DM9102A 10/100BaseTX" }, 163 { DC_DEVID(DC_VENDORID_DAVICOM, DC_DEVICEID_DM9102), 0, 164 "Davicom DM9102 10/100BaseTX" }, 165 { DC_DEVID(DC_VENDORID_ADMTEK, DC_DEVICEID_AL981), 0, 166 "ADMtek AL981 10/100BaseTX" }, 167 { DC_DEVID(DC_VENDORID_ADMTEK, DC_DEVICEID_AN983), 0, 168 "ADMtek AN983 10/100BaseTX" }, 169 { DC_DEVID(DC_VENDORID_ADMTEK, DC_DEVICEID_AN985), 0, 170 "ADMtek AN985 CardBus 10/100BaseTX or clone" }, 171 { DC_DEVID(DC_VENDORID_ADMTEK, DC_DEVICEID_ADM9511), 0, 172 "ADMtek ADM9511 10/100BaseTX" }, 173 { DC_DEVID(DC_VENDORID_ADMTEK, DC_DEVICEID_ADM9513), 0, 174 "ADMtek ADM9513 10/100BaseTX" }, 175 { DC_DEVID(DC_VENDORID_ASIX, DC_DEVICEID_AX88140A), DC_REVISION_88141, 176 "ASIX AX88141 10/100BaseTX" }, 177 { DC_DEVID(DC_VENDORID_ASIX, DC_DEVICEID_AX88140A), 0, 178 "ASIX AX88140A 10/100BaseTX" }, 179 { DC_DEVID(DC_VENDORID_MX, DC_DEVICEID_98713), DC_REVISION_98713A, 180 "Macronix 98713A 10/100BaseTX" }, 181 { DC_DEVID(DC_VENDORID_MX, DC_DEVICEID_98713), 0, 182 "Macronix 98713 10/100BaseTX" }, 183 { DC_DEVID(DC_VENDORID_CP, DC_DEVICEID_98713_CP), DC_REVISION_98713A, 184 "Compex RL100-TX 10/100BaseTX" }, 185 { DC_DEVID(DC_VENDORID_CP, DC_DEVICEID_98713_CP), 0, 186 "Compex RL100-TX 10/100BaseTX" }, 187 { DC_DEVID(DC_VENDORID_MX, DC_DEVICEID_987x5), DC_REVISION_98725, 188 "Macronix 98725 10/100BaseTX" }, 189 { DC_DEVID(DC_VENDORID_MX, DC_DEVICEID_987x5), DC_REVISION_98715AEC_C, 190 "Macronix 98715AEC-C 10/100BaseTX" }, 191 { DC_DEVID(DC_VENDORID_MX, DC_DEVICEID_987x5), 0, 192 "Macronix 98715/98715A 10/100BaseTX" }, 193 { DC_DEVID(DC_VENDORID_MX, DC_DEVICEID_98727), 0, 194 "Macronix 98727/98732 10/100BaseTX" }, 195 { DC_DEVID(DC_VENDORID_LO, DC_DEVICEID_82C115), 0, 196 "LC82C115 PNIC II 10/100BaseTX" }, 197 { DC_DEVID(DC_VENDORID_LO, DC_DEVICEID_82C168), DC_REVISION_82C169, 198 "82c169 PNIC 10/100BaseTX" }, 199 { DC_DEVID(DC_VENDORID_LO, DC_DEVICEID_82C168), 0, 200 "82c168 PNIC 10/100BaseTX" }, 201 { DC_DEVID(DC_VENDORID_ACCTON, DC_DEVICEID_EN1217), 0, 202 "Accton EN1217 10/100BaseTX" }, 203 { DC_DEVID(DC_VENDORID_ACCTON, DC_DEVICEID_EN2242), 0, 204 "Accton EN2242 MiniPCI 10/100BaseTX" }, 205 { DC_DEVID(DC_VENDORID_XIRCOM, DC_DEVICEID_X3201), 0, 206 "Xircom X3201 10/100BaseTX" }, 207 { DC_DEVID(DC_VENDORID_DLINK, DC_DEVICEID_DRP32TXD), 0, 208 "Neteasy DRP-32TXD Cardbus 10/100" }, 209 { DC_DEVID(DC_VENDORID_ABOCOM, DC_DEVICEID_FE2500), 0, 210 "Abocom FE2500 10/100BaseTX" }, 211 { DC_DEVID(DC_VENDORID_ABOCOM, DC_DEVICEID_FE2500MX), 0, 212 "Abocom FE2500MX 10/100BaseTX" }, 213 { DC_DEVID(DC_VENDORID_CONEXANT, DC_DEVICEID_RS7112), 0, 214 "Conexant LANfinity MiniPCI 10/100BaseTX" }, 215 { DC_DEVID(DC_VENDORID_HAWKING, DC_DEVICEID_HAWKING_PN672TX), 0, 216 "Hawking CB102 CardBus 10/100" }, 217 { DC_DEVID(DC_VENDORID_PLANEX, DC_DEVICEID_FNW3602T), 0, 218 "PlaneX FNW-3602-T CardBus 10/100" }, 219 { DC_DEVID(DC_VENDORID_3COM, DC_DEVICEID_3CSOHOB), 0, 220 "3Com OfficeConnect 10/100B" }, 221 { DC_DEVID(DC_VENDORID_MICROSOFT, DC_DEVICEID_MSMN120), 0, 222 "Microsoft MN-120 CardBus 10/100" }, 223 { DC_DEVID(DC_VENDORID_MICROSOFT, DC_DEVICEID_MSMN130), 0, 224 "Microsoft MN-130 10/100" }, 225 { DC_DEVID(DC_VENDORID_LINKSYS, DC_DEVICEID_PCMPC200_AB08), 0, 226 "Linksys PCMPC200 CardBus 10/100" }, 227 { DC_DEVID(DC_VENDORID_LINKSYS, DC_DEVICEID_PCMPC200_AB09), 0, 228 "Linksys PCMPC200 CardBus 10/100" }, 229 { DC_DEVID(DC_VENDORID_ULI, DC_DEVICEID_M5261), 0, 230 "ULi M5261 FastEthernet" }, 231 { DC_DEVID(DC_VENDORID_ULI, DC_DEVICEID_M5263), 0, 232 "ULi M5263 FastEthernet" }, 233 { 0, 0, NULL } 234 }; 235 236 static int dc_probe(device_t); 237 static int dc_attach(device_t); 238 static int dc_detach(device_t); 239 static int dc_suspend(device_t); 240 static int dc_resume(device_t); 241 static const struct dc_type *dc_devtype(device_t); 242 static void dc_discard_rxbuf(struct dc_softc *, int); 243 static int dc_newbuf(struct dc_softc *, int); 244 static int dc_encap(struct dc_softc *, struct mbuf **); 245 static void dc_pnic_rx_bug_war(struct dc_softc *, int); 246 static int dc_rx_resync(struct dc_softc *); 247 static int dc_rxeof(struct dc_softc *); 248 static void dc_txeof(struct dc_softc *); 249 static void dc_tick(void *); 250 static void dc_tx_underrun(struct dc_softc *); 251 static void dc_intr(void *); 252 static void dc_start(struct ifnet *); 253 static void dc_start_locked(struct ifnet *); 254 static int dc_ioctl(struct ifnet *, u_long, caddr_t); 255 static void dc_init(void *); 256 static void dc_init_locked(struct dc_softc *); 257 static void dc_stop(struct dc_softc *); 258 static void dc_watchdog(void *); 259 static int dc_shutdown(device_t); 260 static int dc_ifmedia_upd(struct ifnet *); 261 static int dc_ifmedia_upd_locked(struct dc_softc *); 262 static void dc_ifmedia_sts(struct ifnet *, struct ifmediareq *); 263 264 static int dc_dma_alloc(struct dc_softc *); 265 static void dc_dma_free(struct dc_softc *); 266 static void dc_dma_map_addr(void *, bus_dma_segment_t *, int, int); 267 268 static void dc_delay(struct dc_softc *); 269 static void dc_eeprom_idle(struct dc_softc *); 270 static void dc_eeprom_putbyte(struct dc_softc *, int); 271 static void dc_eeprom_getword(struct dc_softc *, int, uint16_t *); 272 static void dc_eeprom_getword_pnic(struct dc_softc *, int, uint16_t *); 273 static void dc_eeprom_getword_xircom(struct dc_softc *, int, uint16_t *); 274 static void dc_eeprom_width(struct dc_softc *); 275 static void dc_read_eeprom(struct dc_softc *, caddr_t, int, int, int); 276 277 static int dc_miibus_readreg(device_t, int, int); 278 static int dc_miibus_writereg(device_t, int, int, int); 279 static void dc_miibus_statchg(device_t); 280 static void dc_miibus_mediainit(device_t); 281 282 static void dc_setcfg(struct dc_softc *, int); 283 static void dc_netcfg_wait(struct dc_softc *); 284 static uint32_t dc_mchash_le(struct dc_softc *, const uint8_t *); 285 static uint32_t dc_mchash_be(const uint8_t *); 286 static void dc_setfilt_21143(struct dc_softc *); 287 static void dc_setfilt_asix(struct dc_softc *); 288 static void dc_setfilt_admtek(struct dc_softc *); 289 static void dc_setfilt_uli(struct dc_softc *); 290 static void dc_setfilt_xircom(struct dc_softc *); 291 292 static void dc_setfilt(struct dc_softc *); 293 294 static void dc_reset(struct dc_softc *); 295 static int dc_list_rx_init(struct dc_softc *); 296 static int dc_list_tx_init(struct dc_softc *); 297 298 static int dc_read_srom(struct dc_softc *, int); 299 static int dc_parse_21143_srom(struct dc_softc *); 300 static int dc_decode_leaf_sia(struct dc_softc *, struct dc_eblock_sia *); 301 static int dc_decode_leaf_mii(struct dc_softc *, struct dc_eblock_mii *); 302 static int dc_decode_leaf_sym(struct dc_softc *, struct dc_eblock_sym *); 303 static void dc_apply_fixup(struct dc_softc *, int); 304 static int dc_check_multiport(struct dc_softc *); 305 306 /* 307 * MII bit-bang glue 308 */ 309 static uint32_t dc_mii_bitbang_read(device_t); 310 static void dc_mii_bitbang_write(device_t, uint32_t); 311 312 static const struct mii_bitbang_ops dc_mii_bitbang_ops = { 313 dc_mii_bitbang_read, 314 dc_mii_bitbang_write, 315 { 316 DC_SIO_MII_DATAOUT, /* MII_BIT_MDO */ 317 DC_SIO_MII_DATAIN, /* MII_BIT_MDI */ 318 DC_SIO_MII_CLK, /* MII_BIT_MDC */ 319 0, /* MII_BIT_DIR_HOST_PHY */ 320 DC_SIO_MII_DIR, /* MII_BIT_DIR_PHY_HOST */ 321 } 322 }; 323 324 #ifdef DC_USEIOSPACE 325 #define DC_RES SYS_RES_IOPORT 326 #define DC_RID DC_PCI_CFBIO 327 #else 328 #define DC_RES SYS_RES_MEMORY 329 #define DC_RID DC_PCI_CFBMA 330 #endif 331 332 static device_method_t dc_methods[] = { 333 /* Device interface */ 334 DEVMETHOD(device_probe, dc_probe), 335 DEVMETHOD(device_attach, dc_attach), 336 DEVMETHOD(device_detach, dc_detach), 337 DEVMETHOD(device_suspend, dc_suspend), 338 DEVMETHOD(device_resume, dc_resume), 339 DEVMETHOD(device_shutdown, dc_shutdown), 340 341 /* MII interface */ 342 DEVMETHOD(miibus_readreg, dc_miibus_readreg), 343 DEVMETHOD(miibus_writereg, dc_miibus_writereg), 344 DEVMETHOD(miibus_statchg, dc_miibus_statchg), 345 DEVMETHOD(miibus_mediainit, dc_miibus_mediainit), 346 347 DEVMETHOD_END 348 }; 349 350 static driver_t dc_driver = { 351 "dc", 352 dc_methods, 353 sizeof(struct dc_softc) 354 }; 355 356 static devclass_t dc_devclass; 357 358 DRIVER_MODULE_ORDERED(dc, pci, dc_driver, dc_devclass, NULL, NULL, 359 SI_ORDER_ANY); 360 DRIVER_MODULE(miibus, dc, miibus_driver, miibus_devclass, NULL, NULL); 361 362 #define DC_SETBIT(sc, reg, x) \ 363 CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) | (x)) 364 365 #define DC_CLRBIT(sc, reg, x) \ 366 CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) & ~(x)) 367 368 #define SIO_SET(x) DC_SETBIT(sc, DC_SIO, (x)) 369 #define SIO_CLR(x) DC_CLRBIT(sc, DC_SIO, (x)) 370 371 static void 372 dc_delay(struct dc_softc *sc) 373 { 374 int idx; 375 376 for (idx = (300 / 33) + 1; idx > 0; idx--) 377 CSR_READ_4(sc, DC_BUSCTL); 378 } 379 380 static void 381 dc_eeprom_width(struct dc_softc *sc) 382 { 383 int i; 384 385 /* Force EEPROM to idle state. */ 386 dc_eeprom_idle(sc); 387 388 /* Enter EEPROM access mode. */ 389 CSR_WRITE_4(sc, DC_SIO, DC_SIO_EESEL); 390 dc_delay(sc); 391 DC_SETBIT(sc, DC_SIO, DC_SIO_ROMCTL_READ); 392 dc_delay(sc); 393 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); 394 dc_delay(sc); 395 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CS); 396 dc_delay(sc); 397 398 for (i = 3; i--;) { 399 if (6 & (1 << i)) 400 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_DATAIN); 401 else 402 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_DATAIN); 403 dc_delay(sc); 404 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CLK); 405 dc_delay(sc); 406 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); 407 dc_delay(sc); 408 } 409 410 for (i = 1; i <= 12; i++) { 411 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CLK); 412 dc_delay(sc); 413 if (!(CSR_READ_4(sc, DC_SIO) & DC_SIO_EE_DATAOUT)) { 414 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); 415 dc_delay(sc); 416 break; 417 } 418 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); 419 dc_delay(sc); 420 } 421 422 /* Turn off EEPROM access mode. */ 423 dc_eeprom_idle(sc); 424 425 if (i < 4 || i > 12) 426 sc->dc_romwidth = 6; 427 else 428 sc->dc_romwidth = i; 429 430 /* Enter EEPROM access mode. */ 431 CSR_WRITE_4(sc, DC_SIO, DC_SIO_EESEL); 432 dc_delay(sc); 433 DC_SETBIT(sc, DC_SIO, DC_SIO_ROMCTL_READ); 434 dc_delay(sc); 435 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); 436 dc_delay(sc); 437 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CS); 438 dc_delay(sc); 439 440 /* Turn off EEPROM access mode. */ 441 dc_eeprom_idle(sc); 442 } 443 444 static void 445 dc_eeprom_idle(struct dc_softc *sc) 446 { 447 int i; 448 449 CSR_WRITE_4(sc, DC_SIO, DC_SIO_EESEL); 450 dc_delay(sc); 451 DC_SETBIT(sc, DC_SIO, DC_SIO_ROMCTL_READ); 452 dc_delay(sc); 453 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); 454 dc_delay(sc); 455 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CS); 456 dc_delay(sc); 457 458 for (i = 0; i < 25; i++) { 459 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); 460 dc_delay(sc); 461 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CLK); 462 dc_delay(sc); 463 } 464 465 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); 466 dc_delay(sc); 467 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CS); 468 dc_delay(sc); 469 CSR_WRITE_4(sc, DC_SIO, 0x00000000); 470 } 471 472 /* 473 * Send a read command and address to the EEPROM, check for ACK. 474 */ 475 static void 476 dc_eeprom_putbyte(struct dc_softc *sc, int addr) 477 { 478 int d, i; 479 480 d = DC_EECMD_READ >> 6; 481 for (i = 3; i--; ) { 482 if (d & (1 << i)) 483 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_DATAIN); 484 else 485 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_DATAIN); 486 dc_delay(sc); 487 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CLK); 488 dc_delay(sc); 489 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); 490 dc_delay(sc); 491 } 492 493 /* 494 * Feed in each bit and strobe the clock. 495 */ 496 for (i = sc->dc_romwidth; i--;) { 497 if (addr & (1 << i)) { 498 SIO_SET(DC_SIO_EE_DATAIN); 499 } else { 500 SIO_CLR(DC_SIO_EE_DATAIN); 501 } 502 dc_delay(sc); 503 SIO_SET(DC_SIO_EE_CLK); 504 dc_delay(sc); 505 SIO_CLR(DC_SIO_EE_CLK); 506 dc_delay(sc); 507 } 508 } 509 510 /* 511 * Read a word of data stored in the EEPROM at address 'addr.' 512 * The PNIC 82c168/82c169 has its own non-standard way to read 513 * the EEPROM. 514 */ 515 static void 516 dc_eeprom_getword_pnic(struct dc_softc *sc, int addr, uint16_t *dest) 517 { 518 int i; 519 uint32_t r; 520 521 CSR_WRITE_4(sc, DC_PN_SIOCTL, DC_PN_EEOPCODE_READ | addr); 522 523 for (i = 0; i < DC_TIMEOUT; i++) { 524 DELAY(1); 525 r = CSR_READ_4(sc, DC_SIO); 526 if (!(r & DC_PN_SIOCTL_BUSY)) { 527 *dest = (uint16_t)(r & 0xFFFF); 528 return; 529 } 530 } 531 } 532 533 /* 534 * Read a word of data stored in the EEPROM at address 'addr.' 535 * The Xircom X3201 has its own non-standard way to read 536 * the EEPROM, too. 537 */ 538 static void 539 dc_eeprom_getword_xircom(struct dc_softc *sc, int addr, uint16_t *dest) 540 { 541 542 SIO_SET(DC_SIO_ROMSEL | DC_SIO_ROMCTL_READ); 543 544 addr *= 2; 545 CSR_WRITE_4(sc, DC_ROM, addr | 0x160); 546 *dest = (uint16_t)CSR_READ_4(sc, DC_SIO) & 0xff; 547 addr += 1; 548 CSR_WRITE_4(sc, DC_ROM, addr | 0x160); 549 *dest |= ((uint16_t)CSR_READ_4(sc, DC_SIO) & 0xff) << 8; 550 551 SIO_CLR(DC_SIO_ROMSEL | DC_SIO_ROMCTL_READ); 552 } 553 554 /* 555 * Read a word of data stored in the EEPROM at address 'addr.' 556 */ 557 static void 558 dc_eeprom_getword(struct dc_softc *sc, int addr, uint16_t *dest) 559 { 560 int i; 561 uint16_t word = 0; 562 563 /* Force EEPROM to idle state. */ 564 dc_eeprom_idle(sc); 565 566 /* Enter EEPROM access mode. */ 567 CSR_WRITE_4(sc, DC_SIO, DC_SIO_EESEL); 568 dc_delay(sc); 569 DC_SETBIT(sc, DC_SIO, DC_SIO_ROMCTL_READ); 570 dc_delay(sc); 571 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); 572 dc_delay(sc); 573 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CS); 574 dc_delay(sc); 575 576 /* 577 * Send address of word we want to read. 578 */ 579 dc_eeprom_putbyte(sc, addr); 580 581 /* 582 * Start reading bits from EEPROM. 583 */ 584 for (i = 0x8000; i; i >>= 1) { 585 SIO_SET(DC_SIO_EE_CLK); 586 dc_delay(sc); 587 if (CSR_READ_4(sc, DC_SIO) & DC_SIO_EE_DATAOUT) 588 word |= i; 589 dc_delay(sc); 590 SIO_CLR(DC_SIO_EE_CLK); 591 dc_delay(sc); 592 } 593 594 /* Turn off EEPROM access mode. */ 595 dc_eeprom_idle(sc); 596 597 *dest = word; 598 } 599 600 /* 601 * Read a sequence of words from the EEPROM. 602 */ 603 static void 604 dc_read_eeprom(struct dc_softc *sc, caddr_t dest, int off, int cnt, int be) 605 { 606 int i; 607 uint16_t word = 0, *ptr; 608 609 for (i = 0; i < cnt; i++) { 610 if (DC_IS_PNIC(sc)) 611 dc_eeprom_getword_pnic(sc, off + i, &word); 612 else if (DC_IS_XIRCOM(sc)) 613 dc_eeprom_getword_xircom(sc, off + i, &word); 614 else 615 dc_eeprom_getword(sc, off + i, &word); 616 ptr = (uint16_t *)(dest + (i * 2)); 617 if (be) 618 *ptr = be16toh(word); 619 else 620 *ptr = le16toh(word); 621 } 622 } 623 624 /* 625 * Write the MII serial port for the MII bit-bang module. 626 */ 627 static void 628 dc_mii_bitbang_write(device_t dev, uint32_t val) 629 { 630 struct dc_softc *sc; 631 632 sc = device_get_softc(dev); 633 634 CSR_WRITE_4(sc, DC_SIO, val); 635 CSR_BARRIER_4(sc, DC_SIO, 636 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 637 } 638 639 /* 640 * Read the MII serial port for the MII bit-bang module. 641 */ 642 static uint32_t 643 dc_mii_bitbang_read(device_t dev) 644 { 645 struct dc_softc *sc; 646 uint32_t val; 647 648 sc = device_get_softc(dev); 649 650 val = CSR_READ_4(sc, DC_SIO); 651 CSR_BARRIER_4(sc, DC_SIO, 652 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 653 654 return (val); 655 } 656 657 static int 658 dc_miibus_readreg(device_t dev, int phy, int reg) 659 { 660 struct dc_softc *sc; 661 int i, rval, phy_reg = 0; 662 663 sc = device_get_softc(dev); 664 665 if (sc->dc_pmode != DC_PMODE_MII) { 666 if (phy == (MII_NPHY - 1)) { 667 switch (reg) { 668 case MII_BMSR: 669 /* 670 * Fake something to make the probe 671 * code think there's a PHY here. 672 */ 673 return (BMSR_MEDIAMASK); 674 case MII_PHYIDR1: 675 if (DC_IS_PNIC(sc)) 676 return (DC_VENDORID_LO); 677 return (DC_VENDORID_DEC); 678 case MII_PHYIDR2: 679 if (DC_IS_PNIC(sc)) 680 return (DC_DEVICEID_82C168); 681 return (DC_DEVICEID_21143); 682 default: 683 return (0); 684 } 685 } else 686 return (0); 687 } 688 689 if (DC_IS_PNIC(sc)) { 690 CSR_WRITE_4(sc, DC_PN_MII, DC_PN_MIIOPCODE_READ | 691 (phy << 23) | (reg << 18)); 692 for (i = 0; i < DC_TIMEOUT; i++) { 693 DELAY(1); 694 rval = CSR_READ_4(sc, DC_PN_MII); 695 if (!(rval & DC_PN_MII_BUSY)) { 696 rval &= 0xFFFF; 697 return (rval == 0xFFFF ? 0 : rval); 698 } 699 } 700 return (0); 701 } 702 703 if (sc->dc_type == DC_TYPE_ULI_M5263) { 704 CSR_WRITE_4(sc, DC_ROM, 705 ((phy << DC_ULI_PHY_ADDR_SHIFT) & DC_ULI_PHY_ADDR_MASK) | 706 ((reg << DC_ULI_PHY_REG_SHIFT) & DC_ULI_PHY_REG_MASK) | 707 DC_ULI_PHY_OP_READ); 708 for (i = 0; i < DC_TIMEOUT; i++) { 709 DELAY(1); 710 rval = CSR_READ_4(sc, DC_ROM); 711 if ((rval & DC_ULI_PHY_OP_DONE) != 0) { 712 return (rval & DC_ULI_PHY_DATA_MASK); 713 } 714 } 715 if (i == DC_TIMEOUT) 716 device_printf(dev, "phy read timed out\n"); 717 return (0); 718 } 719 720 if (DC_IS_COMET(sc)) { 721 switch (reg) { 722 case MII_BMCR: 723 phy_reg = DC_AL_BMCR; 724 break; 725 case MII_BMSR: 726 phy_reg = DC_AL_BMSR; 727 break; 728 case MII_PHYIDR1: 729 phy_reg = DC_AL_VENID; 730 break; 731 case MII_PHYIDR2: 732 phy_reg = DC_AL_DEVID; 733 break; 734 case MII_ANAR: 735 phy_reg = DC_AL_ANAR; 736 break; 737 case MII_ANLPAR: 738 phy_reg = DC_AL_LPAR; 739 break; 740 case MII_ANER: 741 phy_reg = DC_AL_ANER; 742 break; 743 default: 744 device_printf(dev, "phy_read: bad phy register %x\n", 745 reg); 746 return (0); 747 } 748 749 rval = CSR_READ_4(sc, phy_reg) & 0x0000FFFF; 750 if (rval == 0xFFFF) 751 return (0); 752 return (rval); 753 } 754 755 if (sc->dc_type == DC_TYPE_98713) { 756 phy_reg = CSR_READ_4(sc, DC_NETCFG); 757 CSR_WRITE_4(sc, DC_NETCFG, phy_reg & ~DC_NETCFG_PORTSEL); 758 } 759 rval = mii_bitbang_readreg(dev, &dc_mii_bitbang_ops, phy, reg); 760 if (sc->dc_type == DC_TYPE_98713) 761 CSR_WRITE_4(sc, DC_NETCFG, phy_reg); 762 763 return (rval); 764 } 765 766 static int 767 dc_miibus_writereg(device_t dev, int phy, int reg, int data) 768 { 769 struct dc_softc *sc; 770 int i, phy_reg = 0; 771 772 sc = device_get_softc(dev); 773 774 if (DC_IS_PNIC(sc)) { 775 CSR_WRITE_4(sc, DC_PN_MII, DC_PN_MIIOPCODE_WRITE | 776 (phy << 23) | (reg << 10) | data); 777 for (i = 0; i < DC_TIMEOUT; i++) { 778 if (!(CSR_READ_4(sc, DC_PN_MII) & DC_PN_MII_BUSY)) 779 break; 780 } 781 return (0); 782 } 783 784 if (sc->dc_type == DC_TYPE_ULI_M5263) { 785 CSR_WRITE_4(sc, DC_ROM, 786 ((phy << DC_ULI_PHY_ADDR_SHIFT) & DC_ULI_PHY_ADDR_MASK) | 787 ((reg << DC_ULI_PHY_REG_SHIFT) & DC_ULI_PHY_REG_MASK) | 788 ((data << DC_ULI_PHY_DATA_SHIFT) & DC_ULI_PHY_DATA_MASK) | 789 DC_ULI_PHY_OP_WRITE); 790 DELAY(1); 791 return (0); 792 } 793 794 if (DC_IS_COMET(sc)) { 795 switch (reg) { 796 case MII_BMCR: 797 phy_reg = DC_AL_BMCR; 798 break; 799 case MII_BMSR: 800 phy_reg = DC_AL_BMSR; 801 break; 802 case MII_PHYIDR1: 803 phy_reg = DC_AL_VENID; 804 break; 805 case MII_PHYIDR2: 806 phy_reg = DC_AL_DEVID; 807 break; 808 case MII_ANAR: 809 phy_reg = DC_AL_ANAR; 810 break; 811 case MII_ANLPAR: 812 phy_reg = DC_AL_LPAR; 813 break; 814 case MII_ANER: 815 phy_reg = DC_AL_ANER; 816 break; 817 default: 818 device_printf(dev, "phy_write: bad phy register %x\n", 819 reg); 820 return (0); 821 break; 822 } 823 824 CSR_WRITE_4(sc, phy_reg, data); 825 return (0); 826 } 827 828 if (sc->dc_type == DC_TYPE_98713) { 829 phy_reg = CSR_READ_4(sc, DC_NETCFG); 830 CSR_WRITE_4(sc, DC_NETCFG, phy_reg & ~DC_NETCFG_PORTSEL); 831 } 832 mii_bitbang_writereg(dev, &dc_mii_bitbang_ops, phy, reg, data); 833 if (sc->dc_type == DC_TYPE_98713) 834 CSR_WRITE_4(sc, DC_NETCFG, phy_reg); 835 836 return (0); 837 } 838 839 static void 840 dc_miibus_statchg(device_t dev) 841 { 842 struct dc_softc *sc; 843 struct ifnet *ifp; 844 struct mii_data *mii; 845 struct ifmedia *ifm; 846 847 sc = device_get_softc(dev); 848 849 mii = device_get_softc(sc->dc_miibus); 850 ifp = sc->dc_ifp; 851 if (mii == NULL || ifp == NULL || 852 (ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) 853 return; 854 855 ifm = &mii->mii_media; 856 if (DC_IS_DAVICOM(sc) && IFM_SUBTYPE(ifm->ifm_media) == IFM_HPNA_1) { 857 dc_setcfg(sc, ifm->ifm_media); 858 return; 859 } else if (!DC_IS_ADMTEK(sc)) 860 dc_setcfg(sc, mii->mii_media_active); 861 862 sc->dc_link = 0; 863 if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) == 864 (IFM_ACTIVE | IFM_AVALID)) { 865 switch (IFM_SUBTYPE(mii->mii_media_active)) { 866 case IFM_10_T: 867 case IFM_100_TX: 868 sc->dc_link = 1; 869 break; 870 } 871 } 872 } 873 874 /* 875 * Special support for DM9102A cards with HomePNA PHYs. Note: 876 * with the Davicom DM9102A/DM9801 eval board that I have, it seems 877 * to be impossible to talk to the management interface of the DM9801 878 * PHY (its MDIO pin is not connected to anything). Consequently, 879 * the driver has to just 'know' about the additional mode and deal 880 * with it itself. *sigh* 881 */ 882 static void 883 dc_miibus_mediainit(device_t dev) 884 { 885 struct dc_softc *sc; 886 struct mii_data *mii; 887 struct ifmedia *ifm; 888 int rev; 889 890 rev = pci_get_revid(dev); 891 892 sc = device_get_softc(dev); 893 mii = device_get_softc(sc->dc_miibus); 894 ifm = &mii->mii_media; 895 896 if (DC_IS_DAVICOM(sc) && rev >= DC_REVISION_DM9102A) 897 ifmedia_add(ifm, IFM_ETHER | IFM_HPNA_1, 0, NULL); 898 } 899 900 #define DC_BITS_512 9 901 #define DC_BITS_128 7 902 #define DC_BITS_64 6 903 904 static uint32_t 905 dc_mchash_le(struct dc_softc *sc, const uint8_t *addr) 906 { 907 uint32_t crc; 908 909 /* Compute CRC for the address value. */ 910 crc = ether_crc32_le(addr, ETHER_ADDR_LEN); 911 912 /* 913 * The hash table on the PNIC II and the MX98715AEC-C/D/E 914 * chips is only 128 bits wide. 915 */ 916 if (sc->dc_flags & DC_128BIT_HASH) 917 return (crc & ((1 << DC_BITS_128) - 1)); 918 919 /* The hash table on the MX98715BEC is only 64 bits wide. */ 920 if (sc->dc_flags & DC_64BIT_HASH) 921 return (crc & ((1 << DC_BITS_64) - 1)); 922 923 /* Xircom's hash filtering table is different (read: weird) */ 924 /* Xircom uses the LEAST significant bits */ 925 if (DC_IS_XIRCOM(sc)) { 926 if ((crc & 0x180) == 0x180) 927 return ((crc & 0x0F) + (crc & 0x70) * 3 + (14 << 4)); 928 else 929 return ((crc & 0x1F) + ((crc >> 1) & 0xF0) * 3 + 930 (12 << 4)); 931 } 932 933 return (crc & ((1 << DC_BITS_512) - 1)); 934 } 935 936 /* 937 * Calculate CRC of a multicast group address, return the lower 6 bits. 938 */ 939 static uint32_t 940 dc_mchash_be(const uint8_t *addr) 941 { 942 uint32_t crc; 943 944 /* Compute CRC for the address value. */ 945 crc = ether_crc32_be(addr, ETHER_ADDR_LEN); 946 947 /* Return the filter bit position. */ 948 return ((crc >> 26) & 0x0000003F); 949 } 950 951 /* 952 * 21143-style RX filter setup routine. Filter programming is done by 953 * downloading a special setup frame into the TX engine. 21143, Macronix, 954 * PNIC, PNIC II and Davicom chips are programmed this way. 955 * 956 * We always program the chip using 'hash perfect' mode, i.e. one perfect 957 * address (our node address) and a 512-bit hash filter for multicast 958 * frames. We also sneak the broadcast address into the hash filter since 959 * we need that too. 960 */ 961 static void 962 dc_setfilt_21143(struct dc_softc *sc) 963 { 964 uint16_t eaddr[(ETHER_ADDR_LEN+1)/2]; 965 struct dc_desc *sframe; 966 uint32_t h, *sp; 967 struct ifmultiaddr *ifma; 968 struct ifnet *ifp; 969 int i; 970 971 ifp = sc->dc_ifp; 972 973 i = sc->dc_cdata.dc_tx_prod; 974 DC_INC(sc->dc_cdata.dc_tx_prod, DC_TX_LIST_CNT); 975 sc->dc_cdata.dc_tx_cnt++; 976 sframe = &sc->dc_ldata.dc_tx_list[i]; 977 sp = sc->dc_cdata.dc_sbuf; 978 bzero(sp, DC_SFRAME_LEN); 979 980 sframe->dc_data = htole32(DC_ADDR_LO(sc->dc_saddr)); 981 sframe->dc_ctl = htole32(DC_SFRAME_LEN | DC_TXCTL_SETUP | 982 DC_TXCTL_TLINK | DC_FILTER_HASHPERF | DC_TXCTL_FINT); 983 984 sc->dc_cdata.dc_tx_chain[i] = (struct mbuf *)sc->dc_cdata.dc_sbuf; 985 986 /* If we want promiscuous mode, set the allframes bit. */ 987 if (ifp->if_flags & IFF_PROMISC) 988 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC); 989 else 990 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC); 991 992 if (ifp->if_flags & IFF_ALLMULTI) 993 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI); 994 else 995 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI); 996 997 if_maddr_rlock(ifp); 998 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 999 if (ifma->ifma_addr->sa_family != AF_LINK) 1000 continue; 1001 h = dc_mchash_le(sc, 1002 LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 1003 sp[h >> 4] |= htole32(1 << (h & 0xF)); 1004 } 1005 if_maddr_runlock(ifp); 1006 1007 if (ifp->if_flags & IFF_BROADCAST) { 1008 h = dc_mchash_le(sc, ifp->if_broadcastaddr); 1009 sp[h >> 4] |= htole32(1 << (h & 0xF)); 1010 } 1011 1012 /* Set our MAC address. */ 1013 bcopy(IF_LLADDR(sc->dc_ifp), eaddr, ETHER_ADDR_LEN); 1014 sp[39] = DC_SP_MAC(eaddr[0]); 1015 sp[40] = DC_SP_MAC(eaddr[1]); 1016 sp[41] = DC_SP_MAC(eaddr[2]); 1017 1018 sframe->dc_status = htole32(DC_TXSTAT_OWN); 1019 bus_dmamap_sync(sc->dc_tx_ltag, sc->dc_tx_lmap, BUS_DMASYNC_PREREAD | 1020 BUS_DMASYNC_PREWRITE); 1021 bus_dmamap_sync(sc->dc_stag, sc->dc_smap, BUS_DMASYNC_PREWRITE); 1022 CSR_WRITE_4(sc, DC_TXSTART, 0xFFFFFFFF); 1023 1024 /* 1025 * The PNIC takes an exceedingly long time to process its 1026 * setup frame; wait 10ms after posting the setup frame 1027 * before proceeding, just so it has time to swallow its 1028 * medicine. 1029 */ 1030 DELAY(10000); 1031 1032 sc->dc_wdog_timer = 5; 1033 } 1034 1035 static void 1036 dc_setfilt_admtek(struct dc_softc *sc) 1037 { 1038 uint8_t eaddr[ETHER_ADDR_LEN]; 1039 struct ifnet *ifp; 1040 struct ifmultiaddr *ifma; 1041 int h = 0; 1042 uint32_t hashes[2] = { 0, 0 }; 1043 1044 ifp = sc->dc_ifp; 1045 1046 /* Init our MAC address. */ 1047 bcopy(IF_LLADDR(sc->dc_ifp), eaddr, ETHER_ADDR_LEN); 1048 CSR_WRITE_4(sc, DC_AL_PAR0, eaddr[3] << 24 | eaddr[2] << 16 | 1049 eaddr[1] << 8 | eaddr[0]); 1050 CSR_WRITE_4(sc, DC_AL_PAR1, eaddr[5] << 8 | eaddr[4]); 1051 1052 /* If we want promiscuous mode, set the allframes bit. */ 1053 if (ifp->if_flags & IFF_PROMISC) 1054 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC); 1055 else 1056 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC); 1057 1058 if (ifp->if_flags & IFF_ALLMULTI) 1059 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI); 1060 else 1061 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI); 1062 1063 /* First, zot all the existing hash bits. */ 1064 CSR_WRITE_4(sc, DC_AL_MAR0, 0); 1065 CSR_WRITE_4(sc, DC_AL_MAR1, 0); 1066 1067 /* 1068 * If we're already in promisc or allmulti mode, we 1069 * don't have to bother programming the multicast filter. 1070 */ 1071 if (ifp->if_flags & (IFF_PROMISC | IFF_ALLMULTI)) 1072 return; 1073 1074 /* Now program new ones. */ 1075 if_maddr_rlock(ifp); 1076 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 1077 if (ifma->ifma_addr->sa_family != AF_LINK) 1078 continue; 1079 if (DC_IS_CENTAUR(sc)) 1080 h = dc_mchash_le(sc, 1081 LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 1082 else 1083 h = dc_mchash_be( 1084 LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 1085 if (h < 32) 1086 hashes[0] |= (1 << h); 1087 else 1088 hashes[1] |= (1 << (h - 32)); 1089 } 1090 if_maddr_runlock(ifp); 1091 1092 CSR_WRITE_4(sc, DC_AL_MAR0, hashes[0]); 1093 CSR_WRITE_4(sc, DC_AL_MAR1, hashes[1]); 1094 } 1095 1096 static void 1097 dc_setfilt_asix(struct dc_softc *sc) 1098 { 1099 uint32_t eaddr[(ETHER_ADDR_LEN+3)/4]; 1100 struct ifnet *ifp; 1101 struct ifmultiaddr *ifma; 1102 int h = 0; 1103 uint32_t hashes[2] = { 0, 0 }; 1104 1105 ifp = sc->dc_ifp; 1106 1107 /* Init our MAC address. */ 1108 bcopy(IF_LLADDR(sc->dc_ifp), eaddr, ETHER_ADDR_LEN); 1109 CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_PAR0); 1110 CSR_WRITE_4(sc, DC_AX_FILTDATA, eaddr[0]); 1111 CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_PAR1); 1112 CSR_WRITE_4(sc, DC_AX_FILTDATA, eaddr[1]); 1113 1114 /* If we want promiscuous mode, set the allframes bit. */ 1115 if (ifp->if_flags & IFF_PROMISC) 1116 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC); 1117 else 1118 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC); 1119 1120 if (ifp->if_flags & IFF_ALLMULTI) 1121 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI); 1122 else 1123 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI); 1124 1125 /* 1126 * The ASIX chip has a special bit to enable reception 1127 * of broadcast frames. 1128 */ 1129 if (ifp->if_flags & IFF_BROADCAST) 1130 DC_SETBIT(sc, DC_NETCFG, DC_AX_NETCFG_RX_BROAD); 1131 else 1132 DC_CLRBIT(sc, DC_NETCFG, DC_AX_NETCFG_RX_BROAD); 1133 1134 /* first, zot all the existing hash bits */ 1135 CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_MAR0); 1136 CSR_WRITE_4(sc, DC_AX_FILTDATA, 0); 1137 CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_MAR1); 1138 CSR_WRITE_4(sc, DC_AX_FILTDATA, 0); 1139 1140 /* 1141 * If we're already in promisc or allmulti mode, we 1142 * don't have to bother programming the multicast filter. 1143 */ 1144 if (ifp->if_flags & (IFF_PROMISC | IFF_ALLMULTI)) 1145 return; 1146 1147 /* now program new ones */ 1148 if_maddr_rlock(ifp); 1149 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 1150 if (ifma->ifma_addr->sa_family != AF_LINK) 1151 continue; 1152 h = dc_mchash_be(LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 1153 if (h < 32) 1154 hashes[0] |= (1 << h); 1155 else 1156 hashes[1] |= (1 << (h - 32)); 1157 } 1158 if_maddr_runlock(ifp); 1159 1160 CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_MAR0); 1161 CSR_WRITE_4(sc, DC_AX_FILTDATA, hashes[0]); 1162 CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_MAR1); 1163 CSR_WRITE_4(sc, DC_AX_FILTDATA, hashes[1]); 1164 } 1165 1166 static void 1167 dc_setfilt_uli(struct dc_softc *sc) 1168 { 1169 uint8_t eaddr[ETHER_ADDR_LEN]; 1170 struct ifnet *ifp; 1171 struct ifmultiaddr *ifma; 1172 struct dc_desc *sframe; 1173 uint32_t filter, *sp; 1174 uint8_t *ma; 1175 int i, mcnt; 1176 1177 ifp = sc->dc_ifp; 1178 1179 i = sc->dc_cdata.dc_tx_prod; 1180 DC_INC(sc->dc_cdata.dc_tx_prod, DC_TX_LIST_CNT); 1181 sc->dc_cdata.dc_tx_cnt++; 1182 sframe = &sc->dc_ldata.dc_tx_list[i]; 1183 sp = sc->dc_cdata.dc_sbuf; 1184 bzero(sp, DC_SFRAME_LEN); 1185 1186 sframe->dc_data = htole32(DC_ADDR_LO(sc->dc_saddr)); 1187 sframe->dc_ctl = htole32(DC_SFRAME_LEN | DC_TXCTL_SETUP | 1188 DC_TXCTL_TLINK | DC_FILTER_PERFECT | DC_TXCTL_FINT); 1189 1190 sc->dc_cdata.dc_tx_chain[i] = (struct mbuf *)sc->dc_cdata.dc_sbuf; 1191 1192 /* Set station address. */ 1193 bcopy(IF_LLADDR(sc->dc_ifp), eaddr, ETHER_ADDR_LEN); 1194 *sp++ = DC_SP_MAC(eaddr[1] << 8 | eaddr[0]); 1195 *sp++ = DC_SP_MAC(eaddr[3] << 8 | eaddr[2]); 1196 *sp++ = DC_SP_MAC(eaddr[5] << 8 | eaddr[4]); 1197 1198 /* Set broadcast address. */ 1199 *sp++ = DC_SP_MAC(0xFFFF); 1200 *sp++ = DC_SP_MAC(0xFFFF); 1201 *sp++ = DC_SP_MAC(0xFFFF); 1202 1203 /* Extract current filter configuration. */ 1204 filter = CSR_READ_4(sc, DC_NETCFG); 1205 filter &= ~(DC_NETCFG_RX_PROMISC | DC_NETCFG_RX_ALLMULTI); 1206 1207 /* Now build perfect filters. */ 1208 mcnt = 0; 1209 if_maddr_rlock(ifp); 1210 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 1211 if (ifma->ifma_addr->sa_family != AF_LINK) 1212 continue; 1213 if (mcnt >= DC_ULI_FILTER_NPERF) { 1214 filter |= DC_NETCFG_RX_ALLMULTI; 1215 break; 1216 } 1217 ma = LLADDR((struct sockaddr_dl *)ifma->ifma_addr); 1218 *sp++ = DC_SP_MAC(ma[1] << 8 | ma[0]); 1219 *sp++ = DC_SP_MAC(ma[3] << 8 | ma[2]); 1220 *sp++ = DC_SP_MAC(ma[5] << 8 | ma[4]); 1221 mcnt++; 1222 } 1223 if_maddr_runlock(ifp); 1224 1225 for (; mcnt < DC_ULI_FILTER_NPERF; mcnt++) { 1226 *sp++ = DC_SP_MAC(0xFFFF); 1227 *sp++ = DC_SP_MAC(0xFFFF); 1228 *sp++ = DC_SP_MAC(0xFFFF); 1229 } 1230 1231 if (filter & (DC_NETCFG_TX_ON | DC_NETCFG_RX_ON)) 1232 CSR_WRITE_4(sc, DC_NETCFG, 1233 filter & ~(DC_NETCFG_TX_ON | DC_NETCFG_RX_ON)); 1234 if (ifp->if_flags & IFF_PROMISC) 1235 filter |= DC_NETCFG_RX_PROMISC | DC_NETCFG_RX_ALLMULTI; 1236 if (ifp->if_flags & IFF_ALLMULTI) 1237 filter |= DC_NETCFG_RX_ALLMULTI; 1238 CSR_WRITE_4(sc, DC_NETCFG, 1239 filter & ~(DC_NETCFG_TX_ON | DC_NETCFG_RX_ON)); 1240 if (filter & (DC_NETCFG_TX_ON | DC_NETCFG_RX_ON)) 1241 CSR_WRITE_4(sc, DC_NETCFG, filter); 1242 1243 sframe->dc_status = htole32(DC_TXSTAT_OWN); 1244 bus_dmamap_sync(sc->dc_tx_ltag, sc->dc_tx_lmap, BUS_DMASYNC_PREREAD | 1245 BUS_DMASYNC_PREWRITE); 1246 bus_dmamap_sync(sc->dc_stag, sc->dc_smap, BUS_DMASYNC_PREWRITE); 1247 CSR_WRITE_4(sc, DC_TXSTART, 0xFFFFFFFF); 1248 1249 /* 1250 * Wait some time... 1251 */ 1252 DELAY(1000); 1253 1254 sc->dc_wdog_timer = 5; 1255 } 1256 1257 static void 1258 dc_setfilt_xircom(struct dc_softc *sc) 1259 { 1260 uint16_t eaddr[(ETHER_ADDR_LEN+1)/2]; 1261 struct ifnet *ifp; 1262 struct ifmultiaddr *ifma; 1263 struct dc_desc *sframe; 1264 uint32_t h, *sp; 1265 int i; 1266 1267 ifp = sc->dc_ifp; 1268 DC_CLRBIT(sc, DC_NETCFG, (DC_NETCFG_TX_ON | DC_NETCFG_RX_ON)); 1269 1270 i = sc->dc_cdata.dc_tx_prod; 1271 DC_INC(sc->dc_cdata.dc_tx_prod, DC_TX_LIST_CNT); 1272 sc->dc_cdata.dc_tx_cnt++; 1273 sframe = &sc->dc_ldata.dc_tx_list[i]; 1274 sp = sc->dc_cdata.dc_sbuf; 1275 bzero(sp, DC_SFRAME_LEN); 1276 1277 sframe->dc_data = htole32(DC_ADDR_LO(sc->dc_saddr)); 1278 sframe->dc_ctl = htole32(DC_SFRAME_LEN | DC_TXCTL_SETUP | 1279 DC_TXCTL_TLINK | DC_FILTER_HASHPERF | DC_TXCTL_FINT); 1280 1281 sc->dc_cdata.dc_tx_chain[i] = (struct mbuf *)sc->dc_cdata.dc_sbuf; 1282 1283 /* If we want promiscuous mode, set the allframes bit. */ 1284 if (ifp->if_flags & IFF_PROMISC) 1285 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC); 1286 else 1287 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC); 1288 1289 if (ifp->if_flags & IFF_ALLMULTI) 1290 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI); 1291 else 1292 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI); 1293 1294 if_maddr_rlock(ifp); 1295 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 1296 if (ifma->ifma_addr->sa_family != AF_LINK) 1297 continue; 1298 h = dc_mchash_le(sc, 1299 LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 1300 sp[h >> 4] |= htole32(1 << (h & 0xF)); 1301 } 1302 if_maddr_runlock(ifp); 1303 1304 if (ifp->if_flags & IFF_BROADCAST) { 1305 h = dc_mchash_le(sc, ifp->if_broadcastaddr); 1306 sp[h >> 4] |= htole32(1 << (h & 0xF)); 1307 } 1308 1309 /* Set our MAC address. */ 1310 bcopy(IF_LLADDR(sc->dc_ifp), eaddr, ETHER_ADDR_LEN); 1311 sp[0] = DC_SP_MAC(eaddr[0]); 1312 sp[1] = DC_SP_MAC(eaddr[1]); 1313 sp[2] = DC_SP_MAC(eaddr[2]); 1314 1315 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_TX_ON); 1316 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_ON); 1317 sframe->dc_status = htole32(DC_TXSTAT_OWN); 1318 bus_dmamap_sync(sc->dc_tx_ltag, sc->dc_tx_lmap, BUS_DMASYNC_PREREAD | 1319 BUS_DMASYNC_PREWRITE); 1320 bus_dmamap_sync(sc->dc_stag, sc->dc_smap, BUS_DMASYNC_PREWRITE); 1321 CSR_WRITE_4(sc, DC_TXSTART, 0xFFFFFFFF); 1322 1323 /* 1324 * Wait some time... 1325 */ 1326 DELAY(1000); 1327 1328 sc->dc_wdog_timer = 5; 1329 } 1330 1331 static void 1332 dc_setfilt(struct dc_softc *sc) 1333 { 1334 1335 if (DC_IS_INTEL(sc) || DC_IS_MACRONIX(sc) || DC_IS_PNIC(sc) || 1336 DC_IS_PNICII(sc) || DC_IS_DAVICOM(sc) || DC_IS_CONEXANT(sc)) 1337 dc_setfilt_21143(sc); 1338 1339 if (DC_IS_ASIX(sc)) 1340 dc_setfilt_asix(sc); 1341 1342 if (DC_IS_ADMTEK(sc)) 1343 dc_setfilt_admtek(sc); 1344 1345 if (DC_IS_ULI(sc)) 1346 dc_setfilt_uli(sc); 1347 1348 if (DC_IS_XIRCOM(sc)) 1349 dc_setfilt_xircom(sc); 1350 } 1351 1352 static void 1353 dc_netcfg_wait(struct dc_softc *sc) 1354 { 1355 uint32_t isr; 1356 int i; 1357 1358 for (i = 0; i < DC_TIMEOUT; i++) { 1359 isr = CSR_READ_4(sc, DC_ISR); 1360 if (isr & DC_ISR_TX_IDLE && 1361 ((isr & DC_ISR_RX_STATE) == DC_RXSTATE_STOPPED || 1362 (isr & DC_ISR_RX_STATE) == DC_RXSTATE_WAIT)) 1363 break; 1364 DELAY(10); 1365 } 1366 if (i == DC_TIMEOUT && bus_child_present(sc->dc_dev)) { 1367 if (!(isr & DC_ISR_TX_IDLE) && !DC_IS_ASIX(sc)) 1368 device_printf(sc->dc_dev, 1369 "%s: failed to force tx to idle state\n", __func__); 1370 if (!((isr & DC_ISR_RX_STATE) == DC_RXSTATE_STOPPED || 1371 (isr & DC_ISR_RX_STATE) == DC_RXSTATE_WAIT) && 1372 !DC_HAS_BROKEN_RXSTATE(sc)) 1373 device_printf(sc->dc_dev, 1374 "%s: failed to force rx to idle state\n", __func__); 1375 } 1376 } 1377 1378 /* 1379 * In order to fiddle with the 'full-duplex' and '100Mbps' bits in 1380 * the netconfig register, we first have to put the transmit and/or 1381 * receive logic in the idle state. 1382 */ 1383 static void 1384 dc_setcfg(struct dc_softc *sc, int media) 1385 { 1386 int restart = 0, watchdogreg; 1387 1388 if (IFM_SUBTYPE(media) == IFM_NONE) 1389 return; 1390 1391 if (CSR_READ_4(sc, DC_NETCFG) & (DC_NETCFG_TX_ON | DC_NETCFG_RX_ON)) { 1392 restart = 1; 1393 DC_CLRBIT(sc, DC_NETCFG, (DC_NETCFG_TX_ON | DC_NETCFG_RX_ON)); 1394 dc_netcfg_wait(sc); 1395 } 1396 1397 if (IFM_SUBTYPE(media) == IFM_100_TX) { 1398 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_SPEEDSEL); 1399 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_HEARTBEAT); 1400 if (sc->dc_pmode == DC_PMODE_MII) { 1401 if (DC_IS_INTEL(sc)) { 1402 /* There's a write enable bit here that reads as 1. */ 1403 watchdogreg = CSR_READ_4(sc, DC_WATCHDOG); 1404 watchdogreg &= ~DC_WDOG_CTLWREN; 1405 watchdogreg |= DC_WDOG_JABBERDIS; 1406 CSR_WRITE_4(sc, DC_WATCHDOG, watchdogreg); 1407 } else { 1408 DC_SETBIT(sc, DC_WATCHDOG, DC_WDOG_JABBERDIS); 1409 } 1410 DC_CLRBIT(sc, DC_NETCFG, (DC_NETCFG_PCS | 1411 DC_NETCFG_PORTSEL | DC_NETCFG_SCRAMBLER)); 1412 if (sc->dc_type == DC_TYPE_98713) 1413 DC_SETBIT(sc, DC_NETCFG, (DC_NETCFG_PCS | 1414 DC_NETCFG_SCRAMBLER)); 1415 if (!DC_IS_DAVICOM(sc)) 1416 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL); 1417 DC_CLRBIT(sc, DC_10BTCTRL, 0xFFFF); 1418 } else { 1419 if (DC_IS_PNIC(sc)) { 1420 DC_PN_GPIO_SETBIT(sc, DC_PN_GPIO_SPEEDSEL); 1421 DC_PN_GPIO_SETBIT(sc, DC_PN_GPIO_100TX_LOOP); 1422 DC_SETBIT(sc, DC_PN_NWAY, DC_PN_NWAY_SPEEDSEL); 1423 } 1424 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL); 1425 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PCS); 1426 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_SCRAMBLER); 1427 } 1428 } 1429 1430 if (IFM_SUBTYPE(media) == IFM_10_T) { 1431 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_SPEEDSEL); 1432 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_HEARTBEAT); 1433 if (sc->dc_pmode == DC_PMODE_MII) { 1434 /* There's a write enable bit here that reads as 1. */ 1435 if (DC_IS_INTEL(sc)) { 1436 watchdogreg = CSR_READ_4(sc, DC_WATCHDOG); 1437 watchdogreg &= ~DC_WDOG_CTLWREN; 1438 watchdogreg |= DC_WDOG_JABBERDIS; 1439 CSR_WRITE_4(sc, DC_WATCHDOG, watchdogreg); 1440 } else { 1441 DC_SETBIT(sc, DC_WATCHDOG, DC_WDOG_JABBERDIS); 1442 } 1443 DC_CLRBIT(sc, DC_NETCFG, (DC_NETCFG_PCS | 1444 DC_NETCFG_PORTSEL | DC_NETCFG_SCRAMBLER)); 1445 if (sc->dc_type == DC_TYPE_98713) 1446 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PCS); 1447 if (!DC_IS_DAVICOM(sc)) 1448 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL); 1449 DC_CLRBIT(sc, DC_10BTCTRL, 0xFFFF); 1450 } else { 1451 if (DC_IS_PNIC(sc)) { 1452 DC_PN_GPIO_CLRBIT(sc, DC_PN_GPIO_SPEEDSEL); 1453 DC_PN_GPIO_SETBIT(sc, DC_PN_GPIO_100TX_LOOP); 1454 DC_CLRBIT(sc, DC_PN_NWAY, DC_PN_NWAY_SPEEDSEL); 1455 } 1456 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL); 1457 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_PCS); 1458 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_SCRAMBLER); 1459 if (DC_IS_INTEL(sc)) { 1460 DC_CLRBIT(sc, DC_SIARESET, DC_SIA_RESET); 1461 DC_CLRBIT(sc, DC_10BTCTRL, 0xFFFF); 1462 if ((media & IFM_GMASK) == IFM_FDX) 1463 DC_SETBIT(sc, DC_10BTCTRL, 0x7F3D); 1464 else 1465 DC_SETBIT(sc, DC_10BTCTRL, 0x7F3F); 1466 DC_SETBIT(sc, DC_SIARESET, DC_SIA_RESET); 1467 DC_CLRBIT(sc, DC_10BTCTRL, 1468 DC_TCTL_AUTONEGENBL); 1469 DELAY(20000); 1470 } 1471 } 1472 } 1473 1474 /* 1475 * If this is a Davicom DM9102A card with a DM9801 HomePNA 1476 * PHY and we want HomePNA mode, set the portsel bit to turn 1477 * on the external MII port. 1478 */ 1479 if (DC_IS_DAVICOM(sc)) { 1480 if (IFM_SUBTYPE(media) == IFM_HPNA_1) { 1481 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL); 1482 sc->dc_link = 1; 1483 } else { 1484 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL); 1485 } 1486 } 1487 1488 if ((media & IFM_GMASK) == IFM_FDX) { 1489 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_FULLDUPLEX); 1490 if (sc->dc_pmode == DC_PMODE_SYM && DC_IS_PNIC(sc)) 1491 DC_SETBIT(sc, DC_PN_NWAY, DC_PN_NWAY_DUPLEX); 1492 } else { 1493 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_FULLDUPLEX); 1494 if (sc->dc_pmode == DC_PMODE_SYM && DC_IS_PNIC(sc)) 1495 DC_CLRBIT(sc, DC_PN_NWAY, DC_PN_NWAY_DUPLEX); 1496 } 1497 1498 if (restart) 1499 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_TX_ON | DC_NETCFG_RX_ON); 1500 } 1501 1502 static void 1503 dc_reset(struct dc_softc *sc) 1504 { 1505 int i; 1506 1507 DC_SETBIT(sc, DC_BUSCTL, DC_BUSCTL_RESET); 1508 1509 for (i = 0; i < DC_TIMEOUT; i++) { 1510 DELAY(10); 1511 if (!(CSR_READ_4(sc, DC_BUSCTL) & DC_BUSCTL_RESET)) 1512 break; 1513 } 1514 1515 if (DC_IS_ASIX(sc) || DC_IS_ADMTEK(sc) || DC_IS_CONEXANT(sc) || 1516 DC_IS_XIRCOM(sc) || DC_IS_INTEL(sc) || DC_IS_ULI(sc)) { 1517 DELAY(10000); 1518 DC_CLRBIT(sc, DC_BUSCTL, DC_BUSCTL_RESET); 1519 i = 0; 1520 } 1521 1522 if (i == DC_TIMEOUT) 1523 device_printf(sc->dc_dev, "reset never completed!\n"); 1524 1525 /* Wait a little while for the chip to get its brains in order. */ 1526 DELAY(1000); 1527 1528 CSR_WRITE_4(sc, DC_IMR, 0x00000000); 1529 CSR_WRITE_4(sc, DC_BUSCTL, 0x00000000); 1530 CSR_WRITE_4(sc, DC_NETCFG, 0x00000000); 1531 1532 /* 1533 * Bring the SIA out of reset. In some cases, it looks 1534 * like failing to unreset the SIA soon enough gets it 1535 * into a state where it will never come out of reset 1536 * until we reset the whole chip again. 1537 */ 1538 if (DC_IS_INTEL(sc)) { 1539 DC_SETBIT(sc, DC_SIARESET, DC_SIA_RESET); 1540 CSR_WRITE_4(sc, DC_10BTCTRL, 0xFFFFFFFF); 1541 CSR_WRITE_4(sc, DC_WATCHDOG, 0); 1542 } 1543 } 1544 1545 static const struct dc_type * 1546 dc_devtype(device_t dev) 1547 { 1548 const struct dc_type *t; 1549 uint32_t devid; 1550 uint8_t rev; 1551 1552 t = dc_devs; 1553 devid = pci_get_devid(dev); 1554 rev = pci_get_revid(dev); 1555 1556 while (t->dc_name != NULL) { 1557 if (devid == t->dc_devid && rev >= t->dc_minrev) 1558 return (t); 1559 t++; 1560 } 1561 1562 return (NULL); 1563 } 1564 1565 /* 1566 * Probe for a 21143 or clone chip. Check the PCI vendor and device 1567 * IDs against our list and return a device name if we find a match. 1568 * We do a little bit of extra work to identify the exact type of 1569 * chip. The MX98713 and MX98713A have the same PCI vendor/device ID, 1570 * but different revision IDs. The same is true for 98715/98715A 1571 * chips and the 98725, as well as the ASIX and ADMtek chips. In some 1572 * cases, the exact chip revision affects driver behavior. 1573 */ 1574 static int 1575 dc_probe(device_t dev) 1576 { 1577 const struct dc_type *t; 1578 1579 t = dc_devtype(dev); 1580 1581 if (t != NULL) { 1582 device_set_desc(dev, t->dc_name); 1583 return (BUS_PROBE_DEFAULT); 1584 } 1585 1586 return (ENXIO); 1587 } 1588 1589 static void 1590 dc_apply_fixup(struct dc_softc *sc, int media) 1591 { 1592 struct dc_mediainfo *m; 1593 uint8_t *p; 1594 int i; 1595 uint32_t reg; 1596 1597 m = sc->dc_mi; 1598 1599 while (m != NULL) { 1600 if (m->dc_media == media) 1601 break; 1602 m = m->dc_next; 1603 } 1604 1605 if (m == NULL) 1606 return; 1607 1608 for (i = 0, p = m->dc_reset_ptr; i < m->dc_reset_len; i++, p += 2) { 1609 reg = (p[0] | (p[1] << 8)) << 16; 1610 CSR_WRITE_4(sc, DC_WATCHDOG, reg); 1611 } 1612 1613 for (i = 0, p = m->dc_gp_ptr; i < m->dc_gp_len; i++, p += 2) { 1614 reg = (p[0] | (p[1] << 8)) << 16; 1615 CSR_WRITE_4(sc, DC_WATCHDOG, reg); 1616 } 1617 } 1618 1619 static int 1620 dc_decode_leaf_sia(struct dc_softc *sc, struct dc_eblock_sia *l) 1621 { 1622 struct dc_mediainfo *m; 1623 1624 m = malloc(sizeof(struct dc_mediainfo), M_DEVBUF, M_NOWAIT | M_ZERO); 1625 if (m == NULL) { 1626 device_printf(sc->dc_dev, "Could not allocate mediainfo\n"); 1627 return (ENOMEM); 1628 } 1629 switch (l->dc_sia_code & ~DC_SIA_CODE_EXT) { 1630 case DC_SIA_CODE_10BT: 1631 m->dc_media = IFM_10_T; 1632 break; 1633 case DC_SIA_CODE_10BT_FDX: 1634 m->dc_media = IFM_10_T | IFM_FDX; 1635 break; 1636 case DC_SIA_CODE_10B2: 1637 m->dc_media = IFM_10_2; 1638 break; 1639 case DC_SIA_CODE_10B5: 1640 m->dc_media = IFM_10_5; 1641 break; 1642 default: 1643 break; 1644 } 1645 1646 /* 1647 * We need to ignore CSR13, CSR14, CSR15 for SIA mode. 1648 * Things apparently already work for cards that do 1649 * supply Media Specific Data. 1650 */ 1651 if (l->dc_sia_code & DC_SIA_CODE_EXT) { 1652 m->dc_gp_len = 2; 1653 m->dc_gp_ptr = 1654 (uint8_t *)&l->dc_un.dc_sia_ext.dc_sia_gpio_ctl; 1655 } else { 1656 m->dc_gp_len = 2; 1657 m->dc_gp_ptr = 1658 (uint8_t *)&l->dc_un.dc_sia_noext.dc_sia_gpio_ctl; 1659 } 1660 1661 m->dc_next = sc->dc_mi; 1662 sc->dc_mi = m; 1663 1664 sc->dc_pmode = DC_PMODE_SIA; 1665 return (0); 1666 } 1667 1668 static int 1669 dc_decode_leaf_sym(struct dc_softc *sc, struct dc_eblock_sym *l) 1670 { 1671 struct dc_mediainfo *m; 1672 1673 m = malloc(sizeof(struct dc_mediainfo), M_DEVBUF, M_NOWAIT | M_ZERO); 1674 if (m == NULL) { 1675 device_printf(sc->dc_dev, "Could not allocate mediainfo\n"); 1676 return (ENOMEM); 1677 } 1678 if (l->dc_sym_code == DC_SYM_CODE_100BT) 1679 m->dc_media = IFM_100_TX; 1680 1681 if (l->dc_sym_code == DC_SYM_CODE_100BT_FDX) 1682 m->dc_media = IFM_100_TX | IFM_FDX; 1683 1684 m->dc_gp_len = 2; 1685 m->dc_gp_ptr = (uint8_t *)&l->dc_sym_gpio_ctl; 1686 1687 m->dc_next = sc->dc_mi; 1688 sc->dc_mi = m; 1689 1690 sc->dc_pmode = DC_PMODE_SYM; 1691 return (0); 1692 } 1693 1694 static int 1695 dc_decode_leaf_mii(struct dc_softc *sc, struct dc_eblock_mii *l) 1696 { 1697 struct dc_mediainfo *m; 1698 uint8_t *p; 1699 1700 m = malloc(sizeof(struct dc_mediainfo), M_DEVBUF, M_NOWAIT | M_ZERO); 1701 if (m == NULL) { 1702 device_printf(sc->dc_dev, "Could not allocate mediainfo\n"); 1703 return (ENOMEM); 1704 } 1705 /* We abuse IFM_AUTO to represent MII. */ 1706 m->dc_media = IFM_AUTO; 1707 m->dc_gp_len = l->dc_gpr_len; 1708 1709 p = (uint8_t *)l; 1710 p += sizeof(struct dc_eblock_mii); 1711 m->dc_gp_ptr = p; 1712 p += 2 * l->dc_gpr_len; 1713 m->dc_reset_len = *p; 1714 p++; 1715 m->dc_reset_ptr = p; 1716 1717 m->dc_next = sc->dc_mi; 1718 sc->dc_mi = m; 1719 return (0); 1720 } 1721 1722 static int 1723 dc_read_srom(struct dc_softc *sc, int bits) 1724 { 1725 int size; 1726 1727 size = DC_ROM_SIZE(bits); 1728 sc->dc_srom = malloc(size, M_DEVBUF, M_NOWAIT | M_ZERO); 1729 if (sc->dc_srom == NULL) { 1730 device_printf(sc->dc_dev, "Could not allocate SROM buffer\n"); 1731 return (ENOMEM); 1732 } 1733 dc_read_eeprom(sc, (caddr_t)sc->dc_srom, 0, (size / 2), 0); 1734 return (0); 1735 } 1736 1737 static int 1738 dc_parse_21143_srom(struct dc_softc *sc) 1739 { 1740 struct dc_leaf_hdr *lhdr; 1741 struct dc_eblock_hdr *hdr; 1742 int error, have_mii, i, loff; 1743 char *ptr; 1744 1745 have_mii = 0; 1746 loff = sc->dc_srom[27]; 1747 lhdr = (struct dc_leaf_hdr *)&(sc->dc_srom[loff]); 1748 1749 ptr = (char *)lhdr; 1750 ptr += sizeof(struct dc_leaf_hdr) - 1; 1751 /* 1752 * Look if we got a MII media block. 1753 */ 1754 for (i = 0; i < lhdr->dc_mcnt; i++) { 1755 hdr = (struct dc_eblock_hdr *)ptr; 1756 if (hdr->dc_type == DC_EBLOCK_MII) 1757 have_mii++; 1758 1759 ptr += (hdr->dc_len & 0x7F); 1760 ptr++; 1761 } 1762 1763 /* 1764 * Do the same thing again. Only use SIA and SYM media 1765 * blocks if no MII media block is available. 1766 */ 1767 ptr = (char *)lhdr; 1768 ptr += sizeof(struct dc_leaf_hdr) - 1; 1769 error = 0; 1770 for (i = 0; i < lhdr->dc_mcnt; i++) { 1771 hdr = (struct dc_eblock_hdr *)ptr; 1772 switch (hdr->dc_type) { 1773 case DC_EBLOCK_MII: 1774 error = dc_decode_leaf_mii(sc, (struct dc_eblock_mii *)hdr); 1775 break; 1776 case DC_EBLOCK_SIA: 1777 if (! have_mii) 1778 error = dc_decode_leaf_sia(sc, 1779 (struct dc_eblock_sia *)hdr); 1780 break; 1781 case DC_EBLOCK_SYM: 1782 if (! have_mii) 1783 error = dc_decode_leaf_sym(sc, 1784 (struct dc_eblock_sym *)hdr); 1785 break; 1786 default: 1787 /* Don't care. Yet. */ 1788 break; 1789 } 1790 ptr += (hdr->dc_len & 0x7F); 1791 ptr++; 1792 } 1793 return (error); 1794 } 1795 1796 static void 1797 dc_dma_map_addr(void *arg, bus_dma_segment_t *segs, int nseg, int error) 1798 { 1799 bus_addr_t *paddr; 1800 1801 KASSERT(nseg == 1, 1802 ("%s: wrong number of segments (%d)", __func__, nseg)); 1803 paddr = arg; 1804 *paddr = segs->ds_addr; 1805 } 1806 1807 static int 1808 dc_dma_alloc(struct dc_softc *sc) 1809 { 1810 int error, i; 1811 1812 error = bus_dma_tag_create(bus_get_dma_tag(sc->dc_dev), 1, 0, 1813 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL, 1814 BUS_SPACE_MAXSIZE_32BIT, 0, BUS_SPACE_MAXSIZE_32BIT, 0, 1815 NULL, NULL, &sc->dc_ptag); 1816 if (error) { 1817 device_printf(sc->dc_dev, 1818 "failed to allocate parent DMA tag\n"); 1819 goto fail; 1820 } 1821 1822 /* Allocate a busdma tag and DMA safe memory for TX/RX descriptors. */ 1823 error = bus_dma_tag_create(sc->dc_ptag, DC_LIST_ALIGN, 0, 1824 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL, DC_RX_LIST_SZ, 1, 1825 DC_RX_LIST_SZ, 0, NULL, NULL, &sc->dc_rx_ltag); 1826 if (error) { 1827 device_printf(sc->dc_dev, "failed to create RX list DMA tag\n"); 1828 goto fail; 1829 } 1830 1831 error = bus_dma_tag_create(sc->dc_ptag, DC_LIST_ALIGN, 0, 1832 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL, DC_TX_LIST_SZ, 1, 1833 DC_TX_LIST_SZ, 0, NULL, NULL, &sc->dc_tx_ltag); 1834 if (error) { 1835 device_printf(sc->dc_dev, "failed to create TX list DMA tag\n"); 1836 goto fail; 1837 } 1838 1839 /* RX descriptor list. */ 1840 error = bus_dmamem_alloc(sc->dc_rx_ltag, 1841 (void **)&sc->dc_ldata.dc_rx_list, BUS_DMA_NOWAIT | 1842 BUS_DMA_ZERO | BUS_DMA_COHERENT, &sc->dc_rx_lmap); 1843 if (error) { 1844 device_printf(sc->dc_dev, 1845 "failed to allocate DMA'able memory for RX list\n"); 1846 goto fail; 1847 } 1848 error = bus_dmamap_load(sc->dc_rx_ltag, sc->dc_rx_lmap, 1849 sc->dc_ldata.dc_rx_list, DC_RX_LIST_SZ, dc_dma_map_addr, 1850 &sc->dc_ldata.dc_rx_list_paddr, BUS_DMA_NOWAIT); 1851 if (error) { 1852 device_printf(sc->dc_dev, 1853 "failed to load DMA'able memory for RX list\n"); 1854 goto fail; 1855 } 1856 /* TX descriptor list. */ 1857 error = bus_dmamem_alloc(sc->dc_tx_ltag, 1858 (void **)&sc->dc_ldata.dc_tx_list, BUS_DMA_NOWAIT | 1859 BUS_DMA_ZERO | BUS_DMA_COHERENT, &sc->dc_tx_lmap); 1860 if (error) { 1861 device_printf(sc->dc_dev, 1862 "failed to allocate DMA'able memory for TX list\n"); 1863 goto fail; 1864 } 1865 error = bus_dmamap_load(sc->dc_tx_ltag, sc->dc_tx_lmap, 1866 sc->dc_ldata.dc_tx_list, DC_TX_LIST_SZ, dc_dma_map_addr, 1867 &sc->dc_ldata.dc_tx_list_paddr, BUS_DMA_NOWAIT); 1868 if (error) { 1869 device_printf(sc->dc_dev, 1870 "cannot load DMA'able memory for TX list\n"); 1871 goto fail; 1872 } 1873 1874 /* 1875 * Allocate a busdma tag and DMA safe memory for the multicast 1876 * setup frame. 1877 */ 1878 error = bus_dma_tag_create(sc->dc_ptag, DC_LIST_ALIGN, 0, 1879 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL, 1880 DC_SFRAME_LEN + DC_MIN_FRAMELEN, 1, DC_SFRAME_LEN + DC_MIN_FRAMELEN, 1881 0, NULL, NULL, &sc->dc_stag); 1882 if (error) { 1883 device_printf(sc->dc_dev, 1884 "failed to create DMA tag for setup frame\n"); 1885 goto fail; 1886 } 1887 error = bus_dmamem_alloc(sc->dc_stag, (void **)&sc->dc_cdata.dc_sbuf, 1888 BUS_DMA_NOWAIT, &sc->dc_smap); 1889 if (error) { 1890 device_printf(sc->dc_dev, 1891 "failed to allocate DMA'able memory for setup frame\n"); 1892 goto fail; 1893 } 1894 error = bus_dmamap_load(sc->dc_stag, sc->dc_smap, sc->dc_cdata.dc_sbuf, 1895 DC_SFRAME_LEN, dc_dma_map_addr, &sc->dc_saddr, BUS_DMA_NOWAIT); 1896 if (error) { 1897 device_printf(sc->dc_dev, 1898 "cannot load DMA'able memory for setup frame\n"); 1899 goto fail; 1900 } 1901 1902 /* Allocate a busdma tag for RX mbufs. */ 1903 error = bus_dma_tag_create(sc->dc_ptag, DC_RXBUF_ALIGN, 0, 1904 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL, 1905 MCLBYTES, 1, MCLBYTES, 0, NULL, NULL, &sc->dc_rx_mtag); 1906 if (error) { 1907 device_printf(sc->dc_dev, "failed to create RX mbuf tag\n"); 1908 goto fail; 1909 } 1910 1911 /* Allocate a busdma tag for TX mbufs. */ 1912 error = bus_dma_tag_create(sc->dc_ptag, 1, 0, 1913 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL, 1914 MCLBYTES * DC_MAXFRAGS, DC_MAXFRAGS, MCLBYTES, 1915 0, NULL, NULL, &sc->dc_tx_mtag); 1916 if (error) { 1917 device_printf(sc->dc_dev, "failed to create TX mbuf tag\n"); 1918 goto fail; 1919 } 1920 1921 /* Create the TX/RX busdma maps. */ 1922 for (i = 0; i < DC_TX_LIST_CNT; i++) { 1923 error = bus_dmamap_create(sc->dc_tx_mtag, 0, 1924 &sc->dc_cdata.dc_tx_map[i]); 1925 if (error) { 1926 device_printf(sc->dc_dev, 1927 "failed to create TX mbuf dmamap\n"); 1928 goto fail; 1929 } 1930 } 1931 for (i = 0; i < DC_RX_LIST_CNT; i++) { 1932 error = bus_dmamap_create(sc->dc_rx_mtag, 0, 1933 &sc->dc_cdata.dc_rx_map[i]); 1934 if (error) { 1935 device_printf(sc->dc_dev, 1936 "failed to create RX mbuf dmamap\n"); 1937 goto fail; 1938 } 1939 } 1940 error = bus_dmamap_create(sc->dc_rx_mtag, 0, &sc->dc_sparemap); 1941 if (error) { 1942 device_printf(sc->dc_dev, 1943 "failed to create spare RX mbuf dmamap\n"); 1944 goto fail; 1945 } 1946 1947 fail: 1948 return (error); 1949 } 1950 1951 static void 1952 dc_dma_free(struct dc_softc *sc) 1953 { 1954 int i; 1955 1956 /* RX buffers. */ 1957 if (sc->dc_rx_mtag != NULL) { 1958 for (i = 0; i < DC_RX_LIST_CNT; i++) { 1959 if (sc->dc_cdata.dc_rx_map[i] != NULL) 1960 bus_dmamap_destroy(sc->dc_rx_mtag, 1961 sc->dc_cdata.dc_rx_map[i]); 1962 } 1963 if (sc->dc_sparemap != NULL) 1964 bus_dmamap_destroy(sc->dc_rx_mtag, sc->dc_sparemap); 1965 bus_dma_tag_destroy(sc->dc_rx_mtag); 1966 } 1967 1968 /* TX buffers. */ 1969 if (sc->dc_rx_mtag != NULL) { 1970 for (i = 0; i < DC_TX_LIST_CNT; i++) { 1971 if (sc->dc_cdata.dc_tx_map[i] != NULL) 1972 bus_dmamap_destroy(sc->dc_tx_mtag, 1973 sc->dc_cdata.dc_tx_map[i]); 1974 } 1975 bus_dma_tag_destroy(sc->dc_tx_mtag); 1976 } 1977 1978 /* RX descriptor list. */ 1979 if (sc->dc_rx_ltag) { 1980 if (sc->dc_ldata.dc_rx_list_paddr != 0) 1981 bus_dmamap_unload(sc->dc_rx_ltag, sc->dc_rx_lmap); 1982 if (sc->dc_ldata.dc_rx_list != NULL) 1983 bus_dmamem_free(sc->dc_rx_ltag, sc->dc_ldata.dc_rx_list, 1984 sc->dc_rx_lmap); 1985 bus_dma_tag_destroy(sc->dc_rx_ltag); 1986 } 1987 1988 /* TX descriptor list. */ 1989 if (sc->dc_tx_ltag) { 1990 if (sc->dc_ldata.dc_tx_list_paddr != 0) 1991 bus_dmamap_unload(sc->dc_tx_ltag, sc->dc_tx_lmap); 1992 if (sc->dc_ldata.dc_tx_list != NULL) 1993 bus_dmamem_free(sc->dc_tx_ltag, sc->dc_ldata.dc_tx_list, 1994 sc->dc_tx_lmap); 1995 bus_dma_tag_destroy(sc->dc_tx_ltag); 1996 } 1997 1998 /* multicast setup frame. */ 1999 if (sc->dc_stag) { 2000 if (sc->dc_saddr != 0) 2001 bus_dmamap_unload(sc->dc_stag, sc->dc_smap); 2002 if (sc->dc_cdata.dc_sbuf != NULL) 2003 bus_dmamem_free(sc->dc_stag, sc->dc_cdata.dc_sbuf, 2004 sc->dc_smap); 2005 bus_dma_tag_destroy(sc->dc_stag); 2006 } 2007 } 2008 2009 /* 2010 * Attach the interface. Allocate softc structures, do ifmedia 2011 * setup and ethernet/BPF attach. 2012 */ 2013 static int 2014 dc_attach(device_t dev) 2015 { 2016 uint32_t eaddr[(ETHER_ADDR_LEN+3)/4]; 2017 uint32_t command; 2018 struct dc_softc *sc; 2019 struct ifnet *ifp; 2020 struct dc_mediainfo *m; 2021 uint32_t reg, revision; 2022 uint16_t *srom; 2023 int error, mac_offset, n, phy, rid, tmp; 2024 uint8_t *mac; 2025 2026 sc = device_get_softc(dev); 2027 sc->dc_dev = dev; 2028 2029 mtx_init(&sc->dc_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 2030 MTX_DEF); 2031 2032 /* 2033 * Map control/status registers. 2034 */ 2035 pci_enable_busmaster(dev); 2036 2037 rid = DC_RID; 2038 sc->dc_res = bus_alloc_resource_any(dev, DC_RES, &rid, RF_ACTIVE); 2039 2040 if (sc->dc_res == NULL) { 2041 device_printf(dev, "couldn't map ports/memory\n"); 2042 error = ENXIO; 2043 goto fail; 2044 } 2045 2046 sc->dc_btag = rman_get_bustag(sc->dc_res); 2047 sc->dc_bhandle = rman_get_bushandle(sc->dc_res); 2048 2049 /* Allocate interrupt. */ 2050 rid = 0; 2051 sc->dc_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 2052 RF_SHAREABLE | RF_ACTIVE); 2053 2054 if (sc->dc_irq == NULL) { 2055 device_printf(dev, "couldn't map interrupt\n"); 2056 error = ENXIO; 2057 goto fail; 2058 } 2059 2060 /* Need this info to decide on a chip type. */ 2061 sc->dc_info = dc_devtype(dev); 2062 revision = pci_get_revid(dev); 2063 2064 error = 0; 2065 /* Get the eeprom width, but PNIC and XIRCOM have diff eeprom */ 2066 if (sc->dc_info->dc_devid != 2067 DC_DEVID(DC_VENDORID_LO, DC_DEVICEID_82C168) && 2068 sc->dc_info->dc_devid != 2069 DC_DEVID(DC_VENDORID_XIRCOM, DC_DEVICEID_X3201)) 2070 dc_eeprom_width(sc); 2071 2072 switch (sc->dc_info->dc_devid) { 2073 case DC_DEVID(DC_VENDORID_DEC, DC_DEVICEID_21143): 2074 sc->dc_type = DC_TYPE_21143; 2075 sc->dc_flags |= DC_TX_POLL | DC_TX_USE_TX_INTR; 2076 sc->dc_flags |= DC_REDUCED_MII_POLL; 2077 /* Save EEPROM contents so we can parse them later. */ 2078 error = dc_read_srom(sc, sc->dc_romwidth); 2079 if (error != 0) 2080 goto fail; 2081 break; 2082 case DC_DEVID(DC_VENDORID_DAVICOM, DC_DEVICEID_DM9009): 2083 case DC_DEVID(DC_VENDORID_DAVICOM, DC_DEVICEID_DM9100): 2084 case DC_DEVID(DC_VENDORID_DAVICOM, DC_DEVICEID_DM9102): 2085 sc->dc_type = DC_TYPE_DM9102; 2086 sc->dc_flags |= DC_TX_COALESCE | DC_TX_INTR_ALWAYS; 2087 sc->dc_flags |= DC_REDUCED_MII_POLL | DC_TX_STORENFWD; 2088 sc->dc_flags |= DC_TX_ALIGN; 2089 sc->dc_pmode = DC_PMODE_MII; 2090 2091 /* Increase the latency timer value. */ 2092 pci_write_config(dev, PCIR_LATTIMER, 0x80, 1); 2093 break; 2094 case DC_DEVID(DC_VENDORID_ADMTEK, DC_DEVICEID_AL981): 2095 sc->dc_type = DC_TYPE_AL981; 2096 sc->dc_flags |= DC_TX_USE_TX_INTR; 2097 sc->dc_flags |= DC_TX_ADMTEK_WAR; 2098 sc->dc_pmode = DC_PMODE_MII; 2099 error = dc_read_srom(sc, sc->dc_romwidth); 2100 if (error != 0) 2101 goto fail; 2102 break; 2103 case DC_DEVID(DC_VENDORID_ADMTEK, DC_DEVICEID_AN983): 2104 case DC_DEVID(DC_VENDORID_ADMTEK, DC_DEVICEID_AN985): 2105 case DC_DEVID(DC_VENDORID_ADMTEK, DC_DEVICEID_ADM9511): 2106 case DC_DEVID(DC_VENDORID_ADMTEK, DC_DEVICEID_ADM9513): 2107 case DC_DEVID(DC_VENDORID_DLINK, DC_DEVICEID_DRP32TXD): 2108 case DC_DEVID(DC_VENDORID_ABOCOM, DC_DEVICEID_FE2500): 2109 case DC_DEVID(DC_VENDORID_ABOCOM, DC_DEVICEID_FE2500MX): 2110 case DC_DEVID(DC_VENDORID_ACCTON, DC_DEVICEID_EN2242): 2111 case DC_DEVID(DC_VENDORID_HAWKING, DC_DEVICEID_HAWKING_PN672TX): 2112 case DC_DEVID(DC_VENDORID_PLANEX, DC_DEVICEID_FNW3602T): 2113 case DC_DEVID(DC_VENDORID_3COM, DC_DEVICEID_3CSOHOB): 2114 case DC_DEVID(DC_VENDORID_MICROSOFT, DC_DEVICEID_MSMN120): 2115 case DC_DEVID(DC_VENDORID_MICROSOFT, DC_DEVICEID_MSMN130): 2116 case DC_DEVID(DC_VENDORID_LINKSYS, DC_DEVICEID_PCMPC200_AB08): 2117 case DC_DEVID(DC_VENDORID_LINKSYS, DC_DEVICEID_PCMPC200_AB09): 2118 sc->dc_type = DC_TYPE_AN983; 2119 sc->dc_flags |= DC_64BIT_HASH; 2120 sc->dc_flags |= DC_TX_USE_TX_INTR; 2121 sc->dc_flags |= DC_TX_ADMTEK_WAR; 2122 sc->dc_pmode = DC_PMODE_MII; 2123 /* Don't read SROM for - auto-loaded on reset */ 2124 break; 2125 case DC_DEVID(DC_VENDORID_MX, DC_DEVICEID_98713): 2126 case DC_DEVID(DC_VENDORID_CP, DC_DEVICEID_98713_CP): 2127 if (revision < DC_REVISION_98713A) { 2128 sc->dc_type = DC_TYPE_98713; 2129 } 2130 if (revision >= DC_REVISION_98713A) { 2131 sc->dc_type = DC_TYPE_98713A; 2132 sc->dc_flags |= DC_21143_NWAY; 2133 } 2134 sc->dc_flags |= DC_REDUCED_MII_POLL; 2135 sc->dc_flags |= DC_TX_POLL | DC_TX_USE_TX_INTR; 2136 break; 2137 case DC_DEVID(DC_VENDORID_MX, DC_DEVICEID_987x5): 2138 case DC_DEVID(DC_VENDORID_ACCTON, DC_DEVICEID_EN1217): 2139 /* 2140 * Macronix MX98715AEC-C/D/E parts have only a 2141 * 128-bit hash table. We need to deal with these 2142 * in the same manner as the PNIC II so that we 2143 * get the right number of bits out of the 2144 * CRC routine. 2145 */ 2146 if (revision >= DC_REVISION_98715AEC_C && 2147 revision < DC_REVISION_98725) 2148 sc->dc_flags |= DC_128BIT_HASH; 2149 sc->dc_type = DC_TYPE_987x5; 2150 sc->dc_flags |= DC_TX_POLL | DC_TX_USE_TX_INTR; 2151 sc->dc_flags |= DC_REDUCED_MII_POLL | DC_21143_NWAY; 2152 break; 2153 case DC_DEVID(DC_VENDORID_MX, DC_DEVICEID_98727): 2154 sc->dc_type = DC_TYPE_987x5; 2155 sc->dc_flags |= DC_TX_POLL | DC_TX_USE_TX_INTR; 2156 sc->dc_flags |= DC_REDUCED_MII_POLL | DC_21143_NWAY; 2157 break; 2158 case DC_DEVID(DC_VENDORID_LO, DC_DEVICEID_82C115): 2159 sc->dc_type = DC_TYPE_PNICII; 2160 sc->dc_flags |= DC_TX_POLL | DC_TX_USE_TX_INTR | DC_128BIT_HASH; 2161 sc->dc_flags |= DC_REDUCED_MII_POLL | DC_21143_NWAY; 2162 break; 2163 case DC_DEVID(DC_VENDORID_LO, DC_DEVICEID_82C168): 2164 sc->dc_type = DC_TYPE_PNIC; 2165 sc->dc_flags |= DC_TX_STORENFWD | DC_TX_INTR_ALWAYS; 2166 sc->dc_flags |= DC_PNIC_RX_BUG_WAR; 2167 sc->dc_pnic_rx_buf = malloc(DC_RXLEN * 5, M_DEVBUF, M_NOWAIT); 2168 if (sc->dc_pnic_rx_buf == NULL) { 2169 device_printf(sc->dc_dev, 2170 "Could not allocate PNIC RX buffer\n"); 2171 error = ENOMEM; 2172 goto fail; 2173 } 2174 if (revision < DC_REVISION_82C169) 2175 sc->dc_pmode = DC_PMODE_SYM; 2176 break; 2177 case DC_DEVID(DC_VENDORID_ASIX, DC_DEVICEID_AX88140A): 2178 sc->dc_type = DC_TYPE_ASIX; 2179 sc->dc_flags |= DC_TX_USE_TX_INTR | DC_TX_INTR_FIRSTFRAG; 2180 sc->dc_flags |= DC_REDUCED_MII_POLL; 2181 sc->dc_pmode = DC_PMODE_MII; 2182 break; 2183 case DC_DEVID(DC_VENDORID_XIRCOM, DC_DEVICEID_X3201): 2184 sc->dc_type = DC_TYPE_XIRCOM; 2185 sc->dc_flags |= DC_TX_INTR_ALWAYS | DC_TX_COALESCE | 2186 DC_TX_ALIGN; 2187 /* 2188 * We don't actually need to coalesce, but we're doing 2189 * it to obtain a double word aligned buffer. 2190 * The DC_TX_COALESCE flag is required. 2191 */ 2192 sc->dc_pmode = DC_PMODE_MII; 2193 break; 2194 case DC_DEVID(DC_VENDORID_CONEXANT, DC_DEVICEID_RS7112): 2195 sc->dc_type = DC_TYPE_CONEXANT; 2196 sc->dc_flags |= DC_TX_INTR_ALWAYS; 2197 sc->dc_flags |= DC_REDUCED_MII_POLL; 2198 sc->dc_pmode = DC_PMODE_MII; 2199 error = dc_read_srom(sc, sc->dc_romwidth); 2200 if (error != 0) 2201 goto fail; 2202 break; 2203 case DC_DEVID(DC_VENDORID_ULI, DC_DEVICEID_M5261): 2204 case DC_DEVID(DC_VENDORID_ULI, DC_DEVICEID_M5263): 2205 if (sc->dc_info->dc_devid == 2206 DC_DEVID(DC_VENDORID_ULI, DC_DEVICEID_M5261)) 2207 sc->dc_type = DC_TYPE_ULI_M5261; 2208 else 2209 sc->dc_type = DC_TYPE_ULI_M5263; 2210 /* TX buffers should be aligned on 4 byte boundary. */ 2211 sc->dc_flags |= DC_TX_INTR_ALWAYS | DC_TX_COALESCE | 2212 DC_TX_ALIGN; 2213 sc->dc_pmode = DC_PMODE_MII; 2214 error = dc_read_srom(sc, sc->dc_romwidth); 2215 if (error != 0) 2216 goto fail; 2217 break; 2218 default: 2219 device_printf(dev, "unknown device: %x\n", 2220 sc->dc_info->dc_devid); 2221 break; 2222 } 2223 2224 /* Save the cache line size. */ 2225 if (DC_IS_DAVICOM(sc)) 2226 sc->dc_cachesize = 0; 2227 else 2228 sc->dc_cachesize = pci_get_cachelnsz(dev); 2229 2230 /* Reset the adapter. */ 2231 dc_reset(sc); 2232 2233 /* Take 21143 out of snooze mode */ 2234 if (DC_IS_INTEL(sc) || DC_IS_XIRCOM(sc)) { 2235 command = pci_read_config(dev, DC_PCI_CFDD, 4); 2236 command &= ~(DC_CFDD_SNOOZE_MODE | DC_CFDD_SLEEP_MODE); 2237 pci_write_config(dev, DC_PCI_CFDD, command, 4); 2238 } 2239 2240 /* 2241 * Try to learn something about the supported media. 2242 * We know that ASIX and ADMtek and Davicom devices 2243 * will *always* be using MII media, so that's a no-brainer. 2244 * The tricky ones are the Macronix/PNIC II and the 2245 * Intel 21143. 2246 */ 2247 if (DC_IS_INTEL(sc)) { 2248 error = dc_parse_21143_srom(sc); 2249 if (error != 0) 2250 goto fail; 2251 } else if (DC_IS_MACRONIX(sc) || DC_IS_PNICII(sc)) { 2252 if (sc->dc_type == DC_TYPE_98713) 2253 sc->dc_pmode = DC_PMODE_MII; 2254 else 2255 sc->dc_pmode = DC_PMODE_SYM; 2256 } else if (!sc->dc_pmode) 2257 sc->dc_pmode = DC_PMODE_MII; 2258 2259 /* 2260 * Get station address from the EEPROM. 2261 */ 2262 switch(sc->dc_type) { 2263 case DC_TYPE_98713: 2264 case DC_TYPE_98713A: 2265 case DC_TYPE_987x5: 2266 case DC_TYPE_PNICII: 2267 dc_read_eeprom(sc, (caddr_t)&mac_offset, 2268 (DC_EE_NODEADDR_OFFSET / 2), 1, 0); 2269 dc_read_eeprom(sc, (caddr_t)&eaddr, (mac_offset / 2), 3, 0); 2270 break; 2271 case DC_TYPE_PNIC: 2272 dc_read_eeprom(sc, (caddr_t)&eaddr, 0, 3, 1); 2273 break; 2274 case DC_TYPE_DM9102: 2275 dc_read_eeprom(sc, (caddr_t)&eaddr, DC_EE_NODEADDR, 3, 0); 2276 #ifdef __sparc64__ 2277 /* 2278 * If this is an onboard dc(4) the station address read from 2279 * the EEPROM is all zero and we have to get it from the FCode. 2280 */ 2281 if (eaddr[0] == 0 && (eaddr[1] & ~0xffff) == 0) 2282 OF_getetheraddr(dev, (caddr_t)&eaddr); 2283 #endif 2284 break; 2285 case DC_TYPE_21143: 2286 case DC_TYPE_ASIX: 2287 dc_read_eeprom(sc, (caddr_t)&eaddr, DC_EE_NODEADDR, 3, 0); 2288 break; 2289 case DC_TYPE_AL981: 2290 case DC_TYPE_AN983: 2291 reg = CSR_READ_4(sc, DC_AL_PAR0); 2292 mac = (uint8_t *)&eaddr[0]; 2293 mac[0] = (reg >> 0) & 0xff; 2294 mac[1] = (reg >> 8) & 0xff; 2295 mac[2] = (reg >> 16) & 0xff; 2296 mac[3] = (reg >> 24) & 0xff; 2297 reg = CSR_READ_4(sc, DC_AL_PAR1); 2298 mac[4] = (reg >> 0) & 0xff; 2299 mac[5] = (reg >> 8) & 0xff; 2300 break; 2301 case DC_TYPE_CONEXANT: 2302 bcopy(sc->dc_srom + DC_CONEXANT_EE_NODEADDR, &eaddr, 2303 ETHER_ADDR_LEN); 2304 break; 2305 case DC_TYPE_XIRCOM: 2306 /* The MAC comes from the CIS. */ 2307 mac = pci_get_ether(dev); 2308 if (!mac) { 2309 device_printf(dev, "No station address in CIS!\n"); 2310 error = ENXIO; 2311 goto fail; 2312 } 2313 bcopy(mac, eaddr, ETHER_ADDR_LEN); 2314 break; 2315 case DC_TYPE_ULI_M5261: 2316 case DC_TYPE_ULI_M5263: 2317 srom = (uint16_t *)sc->dc_srom; 2318 if (srom == NULL || *srom == 0xFFFF || *srom == 0) { 2319 /* 2320 * No valid SROM present, read station address 2321 * from ID Table. 2322 */ 2323 device_printf(dev, 2324 "Reading station address from ID Table.\n"); 2325 CSR_WRITE_4(sc, DC_BUSCTL, 0x10000); 2326 CSR_WRITE_4(sc, DC_SIARESET, 0x01C0); 2327 CSR_WRITE_4(sc, DC_10BTCTRL, 0x0000); 2328 CSR_WRITE_4(sc, DC_10BTCTRL, 0x0010); 2329 CSR_WRITE_4(sc, DC_10BTCTRL, 0x0000); 2330 CSR_WRITE_4(sc, DC_SIARESET, 0x0000); 2331 CSR_WRITE_4(sc, DC_SIARESET, 0x01B0); 2332 mac = (uint8_t *)eaddr; 2333 for (n = 0; n < ETHER_ADDR_LEN; n++) 2334 mac[n] = (uint8_t)CSR_READ_4(sc, DC_10BTCTRL); 2335 CSR_WRITE_4(sc, DC_SIARESET, 0x0000); 2336 CSR_WRITE_4(sc, DC_BUSCTL, 0x0000); 2337 DELAY(10); 2338 } else 2339 dc_read_eeprom(sc, (caddr_t)&eaddr, DC_EE_NODEADDR, 3, 2340 0); 2341 break; 2342 default: 2343 dc_read_eeprom(sc, (caddr_t)&eaddr, DC_EE_NODEADDR, 3, 0); 2344 break; 2345 } 2346 2347 bcopy(eaddr, sc->dc_eaddr, sizeof(eaddr)); 2348 /* 2349 * If we still have invalid station address, see whether we can 2350 * find station address for chip 0. Some multi-port controllers 2351 * just store station address for chip 0 if they have a shared 2352 * SROM. 2353 */ 2354 if ((sc->dc_eaddr[0] == 0 && (sc->dc_eaddr[1] & ~0xffff) == 0) || 2355 (sc->dc_eaddr[0] == 0xffffffff && 2356 (sc->dc_eaddr[1] & 0xffff) == 0xffff)) { 2357 error = dc_check_multiport(sc); 2358 if (error == 0) { 2359 bcopy(sc->dc_eaddr, eaddr, sizeof(eaddr)); 2360 /* Extract media information. */ 2361 if (DC_IS_INTEL(sc) && sc->dc_srom != NULL) { 2362 while (sc->dc_mi != NULL) { 2363 m = sc->dc_mi->dc_next; 2364 free(sc->dc_mi, M_DEVBUF); 2365 sc->dc_mi = m; 2366 } 2367 error = dc_parse_21143_srom(sc); 2368 if (error != 0) 2369 goto fail; 2370 } 2371 } else if (error == ENOMEM) 2372 goto fail; 2373 else 2374 error = 0; 2375 } 2376 2377 if ((error = dc_dma_alloc(sc)) != 0) 2378 goto fail; 2379 2380 ifp = sc->dc_ifp = if_alloc(IFT_ETHER); 2381 if (ifp == NULL) { 2382 device_printf(dev, "can not if_alloc()\n"); 2383 error = ENOSPC; 2384 goto fail; 2385 } 2386 ifp->if_softc = sc; 2387 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 2388 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 2389 ifp->if_ioctl = dc_ioctl; 2390 ifp->if_start = dc_start; 2391 ifp->if_init = dc_init; 2392 IFQ_SET_MAXLEN(&ifp->if_snd, DC_TX_LIST_CNT - 1); 2393 ifp->if_snd.ifq_drv_maxlen = DC_TX_LIST_CNT - 1; 2394 IFQ_SET_READY(&ifp->if_snd); 2395 2396 /* 2397 * Do MII setup. If this is a 21143, check for a PHY on the 2398 * MII bus after applying any necessary fixups to twiddle the 2399 * GPIO bits. If we don't end up finding a PHY, restore the 2400 * old selection (SIA only or SIA/SYM) and attach the dcphy 2401 * driver instead. 2402 */ 2403 tmp = 0; 2404 if (DC_IS_INTEL(sc)) { 2405 dc_apply_fixup(sc, IFM_AUTO); 2406 tmp = sc->dc_pmode; 2407 sc->dc_pmode = DC_PMODE_MII; 2408 } 2409 2410 /* 2411 * Setup General Purpose port mode and data so the tulip can talk 2412 * to the MII. This needs to be done before mii_attach so that 2413 * we can actually see them. 2414 */ 2415 if (DC_IS_XIRCOM(sc)) { 2416 CSR_WRITE_4(sc, DC_SIAGP, DC_SIAGP_WRITE_EN | DC_SIAGP_INT1_EN | 2417 DC_SIAGP_MD_GP2_OUTPUT | DC_SIAGP_MD_GP0_OUTPUT); 2418 DELAY(10); 2419 CSR_WRITE_4(sc, DC_SIAGP, DC_SIAGP_INT1_EN | 2420 DC_SIAGP_MD_GP2_OUTPUT | DC_SIAGP_MD_GP0_OUTPUT); 2421 DELAY(10); 2422 } 2423 2424 phy = MII_PHY_ANY; 2425 /* 2426 * Note: both the AL981 and AN983 have internal PHYs, however the 2427 * AL981 provides direct access to the PHY registers while the AN983 2428 * uses a serial MII interface. The AN983's MII interface is also 2429 * buggy in that you can read from any MII address (0 to 31), but 2430 * only address 1 behaves normally. To deal with both cases, we 2431 * pretend that the PHY is at MII address 1. 2432 */ 2433 if (DC_IS_ADMTEK(sc)) 2434 phy = DC_ADMTEK_PHYADDR; 2435 2436 /* 2437 * Note: the ukphy probes of the RS7112 report a PHY at MII address 2438 * 0 (possibly HomePNA?) and 1 (ethernet) so we only respond to the 2439 * correct one. 2440 */ 2441 if (DC_IS_CONEXANT(sc)) 2442 phy = DC_CONEXANT_PHYADDR; 2443 2444 error = mii_attach(dev, &sc->dc_miibus, ifp, dc_ifmedia_upd, 2445 dc_ifmedia_sts, BMSR_DEFCAPMASK, phy, MII_OFFSET_ANY, 0); 2446 2447 if (error && DC_IS_INTEL(sc)) { 2448 sc->dc_pmode = tmp; 2449 if (sc->dc_pmode != DC_PMODE_SIA) 2450 sc->dc_pmode = DC_PMODE_SYM; 2451 sc->dc_flags |= DC_21143_NWAY; 2452 /* 2453 * For non-MII cards, we need to have the 21143 2454 * drive the LEDs. Except there are some systems 2455 * like the NEC VersaPro NoteBook PC which have no 2456 * LEDs, and twiddling these bits has adverse effects 2457 * on them. (I.e. you suddenly can't get a link.) 2458 */ 2459 if (!(pci_get_subvendor(dev) == 0x1033 && 2460 pci_get_subdevice(dev) == 0x8028)) 2461 sc->dc_flags |= DC_TULIP_LEDS; 2462 error = mii_attach(dev, &sc->dc_miibus, ifp, dc_ifmedia_upd, 2463 dc_ifmedia_sts, BMSR_DEFCAPMASK, MII_PHY_ANY, 2464 MII_OFFSET_ANY, 0); 2465 } 2466 2467 if (error) { 2468 device_printf(dev, "attaching PHYs failed\n"); 2469 goto fail; 2470 } 2471 2472 if (DC_IS_ADMTEK(sc)) { 2473 /* 2474 * Set automatic TX underrun recovery for the ADMtek chips 2475 */ 2476 DC_SETBIT(sc, DC_AL_CR, DC_AL_CR_ATUR); 2477 } 2478 2479 /* 2480 * Tell the upper layer(s) we support long frames. 2481 */ 2482 ifp->if_hdrlen = sizeof(struct ether_vlan_header); 2483 ifp->if_capabilities |= IFCAP_VLAN_MTU; 2484 ifp->if_capenable = ifp->if_capabilities; 2485 #ifdef DEVICE_POLLING 2486 ifp->if_capabilities |= IFCAP_POLLING; 2487 #endif 2488 2489 callout_init_mtx(&sc->dc_stat_ch, &sc->dc_mtx, 0); 2490 callout_init_mtx(&sc->dc_wdog_ch, &sc->dc_mtx, 0); 2491 2492 /* 2493 * Call MI attach routine. 2494 */ 2495 ether_ifattach(ifp, (caddr_t)eaddr); 2496 2497 /* Hook interrupt last to avoid having to lock softc */ 2498 error = bus_setup_intr(dev, sc->dc_irq, INTR_TYPE_NET | INTR_MPSAFE, 2499 NULL, dc_intr, sc, &sc->dc_intrhand); 2500 2501 if (error) { 2502 device_printf(dev, "couldn't set up irq\n"); 2503 ether_ifdetach(ifp); 2504 goto fail; 2505 } 2506 2507 fail: 2508 if (error) 2509 dc_detach(dev); 2510 return (error); 2511 } 2512 2513 /* 2514 * Shutdown hardware and free up resources. This can be called any 2515 * time after the mutex has been initialized. It is called in both 2516 * the error case in attach and the normal detach case so it needs 2517 * to be careful about only freeing resources that have actually been 2518 * allocated. 2519 */ 2520 static int 2521 dc_detach(device_t dev) 2522 { 2523 struct dc_softc *sc; 2524 struct ifnet *ifp; 2525 struct dc_mediainfo *m; 2526 2527 sc = device_get_softc(dev); 2528 KASSERT(mtx_initialized(&sc->dc_mtx), ("dc mutex not initialized")); 2529 2530 ifp = sc->dc_ifp; 2531 2532 #ifdef DEVICE_POLLING 2533 if (ifp != NULL && ifp->if_capenable & IFCAP_POLLING) 2534 ether_poll_deregister(ifp); 2535 #endif 2536 2537 /* These should only be active if attach succeeded */ 2538 if (device_is_attached(dev)) { 2539 DC_LOCK(sc); 2540 dc_stop(sc); 2541 DC_UNLOCK(sc); 2542 callout_drain(&sc->dc_stat_ch); 2543 callout_drain(&sc->dc_wdog_ch); 2544 ether_ifdetach(ifp); 2545 } 2546 if (sc->dc_miibus) 2547 device_delete_child(dev, sc->dc_miibus); 2548 bus_generic_detach(dev); 2549 2550 if (sc->dc_intrhand) 2551 bus_teardown_intr(dev, sc->dc_irq, sc->dc_intrhand); 2552 if (sc->dc_irq) 2553 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->dc_irq); 2554 if (sc->dc_res) 2555 bus_release_resource(dev, DC_RES, DC_RID, sc->dc_res); 2556 2557 if (ifp != NULL) 2558 if_free(ifp); 2559 2560 dc_dma_free(sc); 2561 2562 free(sc->dc_pnic_rx_buf, M_DEVBUF); 2563 2564 while (sc->dc_mi != NULL) { 2565 m = sc->dc_mi->dc_next; 2566 free(sc->dc_mi, M_DEVBUF); 2567 sc->dc_mi = m; 2568 } 2569 free(sc->dc_srom, M_DEVBUF); 2570 2571 mtx_destroy(&sc->dc_mtx); 2572 2573 return (0); 2574 } 2575 2576 /* 2577 * Initialize the transmit descriptors. 2578 */ 2579 static int 2580 dc_list_tx_init(struct dc_softc *sc) 2581 { 2582 struct dc_chain_data *cd; 2583 struct dc_list_data *ld; 2584 int i, nexti; 2585 2586 cd = &sc->dc_cdata; 2587 ld = &sc->dc_ldata; 2588 for (i = 0; i < DC_TX_LIST_CNT; i++) { 2589 if (i == DC_TX_LIST_CNT - 1) 2590 nexti = 0; 2591 else 2592 nexti = i + 1; 2593 ld->dc_tx_list[i].dc_status = 0; 2594 ld->dc_tx_list[i].dc_ctl = 0; 2595 ld->dc_tx_list[i].dc_data = 0; 2596 ld->dc_tx_list[i].dc_next = htole32(DC_TXDESC(sc, nexti)); 2597 cd->dc_tx_chain[i] = NULL; 2598 } 2599 2600 cd->dc_tx_prod = cd->dc_tx_cons = cd->dc_tx_cnt = 0; 2601 cd->dc_tx_pkts = 0; 2602 bus_dmamap_sync(sc->dc_tx_ltag, sc->dc_tx_lmap, 2603 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2604 return (0); 2605 } 2606 2607 /* 2608 * Initialize the RX descriptors and allocate mbufs for them. Note that 2609 * we arrange the descriptors in a closed ring, so that the last descriptor 2610 * points back to the first. 2611 */ 2612 static int 2613 dc_list_rx_init(struct dc_softc *sc) 2614 { 2615 struct dc_chain_data *cd; 2616 struct dc_list_data *ld; 2617 int i, nexti; 2618 2619 cd = &sc->dc_cdata; 2620 ld = &sc->dc_ldata; 2621 2622 for (i = 0; i < DC_RX_LIST_CNT; i++) { 2623 if (dc_newbuf(sc, i) != 0) 2624 return (ENOBUFS); 2625 if (i == DC_RX_LIST_CNT - 1) 2626 nexti = 0; 2627 else 2628 nexti = i + 1; 2629 ld->dc_rx_list[i].dc_next = htole32(DC_RXDESC(sc, nexti)); 2630 } 2631 2632 cd->dc_rx_prod = 0; 2633 bus_dmamap_sync(sc->dc_rx_ltag, sc->dc_rx_lmap, 2634 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2635 return (0); 2636 } 2637 2638 /* 2639 * Initialize an RX descriptor and attach an MBUF cluster. 2640 */ 2641 static int 2642 dc_newbuf(struct dc_softc *sc, int i) 2643 { 2644 struct mbuf *m; 2645 bus_dmamap_t map; 2646 bus_dma_segment_t segs[1]; 2647 int error, nseg; 2648 2649 m = m_getcl(M_NOWAIT, MT_DATA, M_PKTHDR); 2650 if (m == NULL) 2651 return (ENOBUFS); 2652 m->m_len = m->m_pkthdr.len = MCLBYTES; 2653 m_adj(m, sizeof(u_int64_t)); 2654 2655 /* 2656 * If this is a PNIC chip, zero the buffer. This is part 2657 * of the workaround for the receive bug in the 82c168 and 2658 * 82c169 chips. 2659 */ 2660 if (sc->dc_flags & DC_PNIC_RX_BUG_WAR) 2661 bzero(mtod(m, char *), m->m_len); 2662 2663 error = bus_dmamap_load_mbuf_sg(sc->dc_rx_mtag, sc->dc_sparemap, 2664 m, segs, &nseg, 0); 2665 if (error) { 2666 m_freem(m); 2667 return (error); 2668 } 2669 KASSERT(nseg == 1, ("%s: wrong number of segments (%d)", __func__, 2670 nseg)); 2671 if (sc->dc_cdata.dc_rx_chain[i] != NULL) 2672 bus_dmamap_unload(sc->dc_rx_mtag, sc->dc_cdata.dc_rx_map[i]); 2673 2674 map = sc->dc_cdata.dc_rx_map[i]; 2675 sc->dc_cdata.dc_rx_map[i] = sc->dc_sparemap; 2676 sc->dc_sparemap = map; 2677 sc->dc_cdata.dc_rx_chain[i] = m; 2678 bus_dmamap_sync(sc->dc_rx_mtag, sc->dc_cdata.dc_rx_map[i], 2679 BUS_DMASYNC_PREREAD); 2680 2681 sc->dc_ldata.dc_rx_list[i].dc_ctl = htole32(DC_RXCTL_RLINK | DC_RXLEN); 2682 sc->dc_ldata.dc_rx_list[i].dc_data = 2683 htole32(DC_ADDR_LO(segs[0].ds_addr)); 2684 sc->dc_ldata.dc_rx_list[i].dc_status = htole32(DC_RXSTAT_OWN); 2685 bus_dmamap_sync(sc->dc_rx_ltag, sc->dc_rx_lmap, 2686 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2687 return (0); 2688 } 2689 2690 /* 2691 * Grrrrr. 2692 * The PNIC chip has a terrible bug in it that manifests itself during 2693 * periods of heavy activity. The exact mode of failure if difficult to 2694 * pinpoint: sometimes it only happens in promiscuous mode, sometimes it 2695 * will happen on slow machines. The bug is that sometimes instead of 2696 * uploading one complete frame during reception, it uploads what looks 2697 * like the entire contents of its FIFO memory. The frame we want is at 2698 * the end of the whole mess, but we never know exactly how much data has 2699 * been uploaded, so salvaging the frame is hard. 2700 * 2701 * There is only one way to do it reliably, and it's disgusting. 2702 * Here's what we know: 2703 * 2704 * - We know there will always be somewhere between one and three extra 2705 * descriptors uploaded. 2706 * 2707 * - We know the desired received frame will always be at the end of the 2708 * total data upload. 2709 * 2710 * - We know the size of the desired received frame because it will be 2711 * provided in the length field of the status word in the last descriptor. 2712 * 2713 * Here's what we do: 2714 * 2715 * - When we allocate buffers for the receive ring, we bzero() them. 2716 * This means that we know that the buffer contents should be all 2717 * zeros, except for data uploaded by the chip. 2718 * 2719 * - We also force the PNIC chip to upload frames that include the 2720 * ethernet CRC at the end. 2721 * 2722 * - We gather all of the bogus frame data into a single buffer. 2723 * 2724 * - We then position a pointer at the end of this buffer and scan 2725 * backwards until we encounter the first non-zero byte of data. 2726 * This is the end of the received frame. We know we will encounter 2727 * some data at the end of the frame because the CRC will always be 2728 * there, so even if the sender transmits a packet of all zeros, 2729 * we won't be fooled. 2730 * 2731 * - We know the size of the actual received frame, so we subtract 2732 * that value from the current pointer location. This brings us 2733 * to the start of the actual received packet. 2734 * 2735 * - We copy this into an mbuf and pass it on, along with the actual 2736 * frame length. 2737 * 2738 * The performance hit is tremendous, but it beats dropping frames all 2739 * the time. 2740 */ 2741 2742 #define DC_WHOLEFRAME (DC_RXSTAT_FIRSTFRAG | DC_RXSTAT_LASTFRAG) 2743 static void 2744 dc_pnic_rx_bug_war(struct dc_softc *sc, int idx) 2745 { 2746 struct dc_desc *cur_rx; 2747 struct dc_desc *c = NULL; 2748 struct mbuf *m = NULL; 2749 unsigned char *ptr; 2750 int i, total_len; 2751 uint32_t rxstat = 0; 2752 2753 i = sc->dc_pnic_rx_bug_save; 2754 cur_rx = &sc->dc_ldata.dc_rx_list[idx]; 2755 ptr = sc->dc_pnic_rx_buf; 2756 bzero(ptr, DC_RXLEN * 5); 2757 2758 /* Copy all the bytes from the bogus buffers. */ 2759 while (1) { 2760 c = &sc->dc_ldata.dc_rx_list[i]; 2761 rxstat = le32toh(c->dc_status); 2762 m = sc->dc_cdata.dc_rx_chain[i]; 2763 bcopy(mtod(m, char *), ptr, DC_RXLEN); 2764 ptr += DC_RXLEN; 2765 /* If this is the last buffer, break out. */ 2766 if (i == idx || rxstat & DC_RXSTAT_LASTFRAG) 2767 break; 2768 dc_discard_rxbuf(sc, i); 2769 DC_INC(i, DC_RX_LIST_CNT); 2770 } 2771 2772 /* Find the length of the actual receive frame. */ 2773 total_len = DC_RXBYTES(rxstat); 2774 2775 /* Scan backwards until we hit a non-zero byte. */ 2776 while (*ptr == 0x00) 2777 ptr--; 2778 2779 /* Round off. */ 2780 if ((uintptr_t)(ptr) & 0x3) 2781 ptr -= 1; 2782 2783 /* Now find the start of the frame. */ 2784 ptr -= total_len; 2785 if (ptr < sc->dc_pnic_rx_buf) 2786 ptr = sc->dc_pnic_rx_buf; 2787 2788 /* 2789 * Now copy the salvaged frame to the last mbuf and fake up 2790 * the status word to make it look like a successful 2791 * frame reception. 2792 */ 2793 bcopy(ptr, mtod(m, char *), total_len); 2794 cur_rx->dc_status = htole32(rxstat | DC_RXSTAT_FIRSTFRAG); 2795 } 2796 2797 /* 2798 * This routine searches the RX ring for dirty descriptors in the 2799 * event that the rxeof routine falls out of sync with the chip's 2800 * current descriptor pointer. This may happen sometimes as a result 2801 * of a "no RX buffer available" condition that happens when the chip 2802 * consumes all of the RX buffers before the driver has a chance to 2803 * process the RX ring. This routine may need to be called more than 2804 * once to bring the driver back in sync with the chip, however we 2805 * should still be getting RX DONE interrupts to drive the search 2806 * for new packets in the RX ring, so we should catch up eventually. 2807 */ 2808 static int 2809 dc_rx_resync(struct dc_softc *sc) 2810 { 2811 struct dc_desc *cur_rx; 2812 int i, pos; 2813 2814 pos = sc->dc_cdata.dc_rx_prod; 2815 2816 for (i = 0; i < DC_RX_LIST_CNT; i++) { 2817 cur_rx = &sc->dc_ldata.dc_rx_list[pos]; 2818 if (!(le32toh(cur_rx->dc_status) & DC_RXSTAT_OWN)) 2819 break; 2820 DC_INC(pos, DC_RX_LIST_CNT); 2821 } 2822 2823 /* If the ring really is empty, then just return. */ 2824 if (i == DC_RX_LIST_CNT) 2825 return (0); 2826 2827 /* We've fallen behing the chip: catch it. */ 2828 sc->dc_cdata.dc_rx_prod = pos; 2829 2830 return (EAGAIN); 2831 } 2832 2833 static void 2834 dc_discard_rxbuf(struct dc_softc *sc, int i) 2835 { 2836 struct mbuf *m; 2837 2838 if (sc->dc_flags & DC_PNIC_RX_BUG_WAR) { 2839 m = sc->dc_cdata.dc_rx_chain[i]; 2840 bzero(mtod(m, char *), m->m_len); 2841 } 2842 2843 sc->dc_ldata.dc_rx_list[i].dc_ctl = htole32(DC_RXCTL_RLINK | DC_RXLEN); 2844 sc->dc_ldata.dc_rx_list[i].dc_status = htole32(DC_RXSTAT_OWN); 2845 bus_dmamap_sync(sc->dc_rx_ltag, sc->dc_rx_lmap, BUS_DMASYNC_PREREAD | 2846 BUS_DMASYNC_PREWRITE); 2847 } 2848 2849 /* 2850 * A frame has been uploaded: pass the resulting mbuf chain up to 2851 * the higher level protocols. 2852 */ 2853 static int 2854 dc_rxeof(struct dc_softc *sc) 2855 { 2856 struct mbuf *m; 2857 struct ifnet *ifp; 2858 struct dc_desc *cur_rx; 2859 int i, total_len, rx_npkts; 2860 uint32_t rxstat; 2861 2862 DC_LOCK_ASSERT(sc); 2863 2864 ifp = sc->dc_ifp; 2865 rx_npkts = 0; 2866 2867 bus_dmamap_sync(sc->dc_rx_ltag, sc->dc_rx_lmap, BUS_DMASYNC_POSTREAD | 2868 BUS_DMASYNC_POSTWRITE); 2869 for (i = sc->dc_cdata.dc_rx_prod; 2870 (ifp->if_drv_flags & IFF_DRV_RUNNING) != 0; 2871 DC_INC(i, DC_RX_LIST_CNT)) { 2872 #ifdef DEVICE_POLLING 2873 if (ifp->if_capenable & IFCAP_POLLING) { 2874 if (sc->rxcycles <= 0) 2875 break; 2876 sc->rxcycles--; 2877 } 2878 #endif 2879 cur_rx = &sc->dc_ldata.dc_rx_list[i]; 2880 rxstat = le32toh(cur_rx->dc_status); 2881 if ((rxstat & DC_RXSTAT_OWN) != 0) 2882 break; 2883 m = sc->dc_cdata.dc_rx_chain[i]; 2884 bus_dmamap_sync(sc->dc_rx_mtag, sc->dc_cdata.dc_rx_map[i], 2885 BUS_DMASYNC_POSTREAD); 2886 total_len = DC_RXBYTES(rxstat); 2887 rx_npkts++; 2888 2889 if (sc->dc_flags & DC_PNIC_RX_BUG_WAR) { 2890 if ((rxstat & DC_WHOLEFRAME) != DC_WHOLEFRAME) { 2891 if (rxstat & DC_RXSTAT_FIRSTFRAG) 2892 sc->dc_pnic_rx_bug_save = i; 2893 if ((rxstat & DC_RXSTAT_LASTFRAG) == 0) 2894 continue; 2895 dc_pnic_rx_bug_war(sc, i); 2896 rxstat = le32toh(cur_rx->dc_status); 2897 total_len = DC_RXBYTES(rxstat); 2898 } 2899 } 2900 2901 /* 2902 * If an error occurs, update stats, clear the 2903 * status word and leave the mbuf cluster in place: 2904 * it should simply get re-used next time this descriptor 2905 * comes up in the ring. However, don't report long 2906 * frames as errors since they could be vlans. 2907 */ 2908 if ((rxstat & DC_RXSTAT_RXERR)) { 2909 if (!(rxstat & DC_RXSTAT_GIANT) || 2910 (rxstat & (DC_RXSTAT_CRCERR | DC_RXSTAT_DRIBBLE | 2911 DC_RXSTAT_MIIERE | DC_RXSTAT_COLLSEEN | 2912 DC_RXSTAT_RUNT | DC_RXSTAT_DE))) { 2913 if_inc_counter(ifp, IFCOUNTER_IERRORS, 1); 2914 if (rxstat & DC_RXSTAT_COLLSEEN) 2915 if_inc_counter(ifp, IFCOUNTER_COLLISIONS, 1); 2916 dc_discard_rxbuf(sc, i); 2917 if (rxstat & DC_RXSTAT_CRCERR) 2918 continue; 2919 else { 2920 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 2921 dc_init_locked(sc); 2922 return (rx_npkts); 2923 } 2924 } 2925 } 2926 2927 /* No errors; receive the packet. */ 2928 total_len -= ETHER_CRC_LEN; 2929 #ifdef __NO_STRICT_ALIGNMENT 2930 /* 2931 * On architectures without alignment problems we try to 2932 * allocate a new buffer for the receive ring, and pass up 2933 * the one where the packet is already, saving the expensive 2934 * copy done in m_devget(). 2935 * If we are on an architecture with alignment problems, or 2936 * if the allocation fails, then use m_devget and leave the 2937 * existing buffer in the receive ring. 2938 */ 2939 if (dc_newbuf(sc, i) != 0) { 2940 dc_discard_rxbuf(sc, i); 2941 if_inc_counter(ifp, IFCOUNTER_IQDROPS, 1); 2942 continue; 2943 } 2944 m->m_pkthdr.rcvif = ifp; 2945 m->m_pkthdr.len = m->m_len = total_len; 2946 #else 2947 { 2948 struct mbuf *m0; 2949 2950 m0 = m_devget(mtod(m, char *), total_len, 2951 ETHER_ALIGN, ifp, NULL); 2952 dc_discard_rxbuf(sc, i); 2953 if (m0 == NULL) { 2954 if_inc_counter(ifp, IFCOUNTER_IQDROPS, 1); 2955 continue; 2956 } 2957 m = m0; 2958 } 2959 #endif 2960 2961 if_inc_counter(ifp, IFCOUNTER_IPACKETS, 1); 2962 DC_UNLOCK(sc); 2963 (*ifp->if_input)(ifp, m); 2964 DC_LOCK(sc); 2965 } 2966 2967 sc->dc_cdata.dc_rx_prod = i; 2968 return (rx_npkts); 2969 } 2970 2971 /* 2972 * A frame was downloaded to the chip. It's safe for us to clean up 2973 * the list buffers. 2974 */ 2975 static void 2976 dc_txeof(struct dc_softc *sc) 2977 { 2978 struct dc_desc *cur_tx; 2979 struct ifnet *ifp; 2980 int idx, setup; 2981 uint32_t ctl, txstat; 2982 2983 if (sc->dc_cdata.dc_tx_cnt == 0) 2984 return; 2985 2986 ifp = sc->dc_ifp; 2987 2988 /* 2989 * Go through our tx list and free mbufs for those 2990 * frames that have been transmitted. 2991 */ 2992 bus_dmamap_sync(sc->dc_tx_ltag, sc->dc_tx_lmap, BUS_DMASYNC_POSTREAD | 2993 BUS_DMASYNC_POSTWRITE); 2994 setup = 0; 2995 for (idx = sc->dc_cdata.dc_tx_cons; idx != sc->dc_cdata.dc_tx_prod; 2996 DC_INC(idx, DC_TX_LIST_CNT), sc->dc_cdata.dc_tx_cnt--) { 2997 cur_tx = &sc->dc_ldata.dc_tx_list[idx]; 2998 txstat = le32toh(cur_tx->dc_status); 2999 ctl = le32toh(cur_tx->dc_ctl); 3000 3001 if (txstat & DC_TXSTAT_OWN) 3002 break; 3003 3004 if (sc->dc_cdata.dc_tx_chain[idx] == NULL) 3005 continue; 3006 3007 if (ctl & DC_TXCTL_SETUP) { 3008 cur_tx->dc_ctl = htole32(ctl & ~DC_TXCTL_SETUP); 3009 setup++; 3010 bus_dmamap_sync(sc->dc_stag, sc->dc_smap, 3011 BUS_DMASYNC_POSTWRITE); 3012 /* 3013 * Yes, the PNIC is so brain damaged 3014 * that it will sometimes generate a TX 3015 * underrun error while DMAing the RX 3016 * filter setup frame. If we detect this, 3017 * we have to send the setup frame again, 3018 * or else the filter won't be programmed 3019 * correctly. 3020 */ 3021 if (DC_IS_PNIC(sc)) { 3022 if (txstat & DC_TXSTAT_ERRSUM) 3023 dc_setfilt(sc); 3024 } 3025 sc->dc_cdata.dc_tx_chain[idx] = NULL; 3026 continue; 3027 } 3028 3029 if (DC_IS_XIRCOM(sc) || DC_IS_CONEXANT(sc)) { 3030 /* 3031 * XXX: Why does my Xircom taunt me so? 3032 * For some reason it likes setting the CARRLOST flag 3033 * even when the carrier is there. wtf?!? 3034 * Who knows, but Conexant chips have the 3035 * same problem. Maybe they took lessons 3036 * from Xircom. 3037 */ 3038 if (/*sc->dc_type == DC_TYPE_21143 &&*/ 3039 sc->dc_pmode == DC_PMODE_MII && 3040 ((txstat & 0xFFFF) & ~(DC_TXSTAT_ERRSUM | 3041 DC_TXSTAT_NOCARRIER))) 3042 txstat &= ~DC_TXSTAT_ERRSUM; 3043 } else { 3044 if (/*sc->dc_type == DC_TYPE_21143 &&*/ 3045 sc->dc_pmode == DC_PMODE_MII && 3046 ((txstat & 0xFFFF) & ~(DC_TXSTAT_ERRSUM | 3047 DC_TXSTAT_NOCARRIER | DC_TXSTAT_CARRLOST))) 3048 txstat &= ~DC_TXSTAT_ERRSUM; 3049 } 3050 3051 if (txstat & DC_TXSTAT_ERRSUM) { 3052 if_inc_counter(ifp, IFCOUNTER_OERRORS, 1); 3053 if (txstat & DC_TXSTAT_EXCESSCOLL) 3054 if_inc_counter(ifp, IFCOUNTER_COLLISIONS, 1); 3055 if (txstat & DC_TXSTAT_LATECOLL) 3056 if_inc_counter(ifp, IFCOUNTER_COLLISIONS, 1); 3057 if (!(txstat & DC_TXSTAT_UNDERRUN)) { 3058 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 3059 dc_init_locked(sc); 3060 return; 3061 } 3062 } else 3063 if_inc_counter(ifp, IFCOUNTER_OPACKETS, 1); 3064 if_inc_counter(ifp, IFCOUNTER_COLLISIONS, (txstat & DC_TXSTAT_COLLCNT) >> 3); 3065 3066 bus_dmamap_sync(sc->dc_tx_mtag, sc->dc_cdata.dc_tx_map[idx], 3067 BUS_DMASYNC_POSTWRITE); 3068 bus_dmamap_unload(sc->dc_tx_mtag, sc->dc_cdata.dc_tx_map[idx]); 3069 m_freem(sc->dc_cdata.dc_tx_chain[idx]); 3070 sc->dc_cdata.dc_tx_chain[idx] = NULL; 3071 } 3072 sc->dc_cdata.dc_tx_cons = idx; 3073 3074 if (sc->dc_cdata.dc_tx_cnt <= DC_TX_LIST_CNT - DC_TX_LIST_RSVD) { 3075 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 3076 if (sc->dc_cdata.dc_tx_cnt == 0) 3077 sc->dc_wdog_timer = 0; 3078 } 3079 if (setup > 0) 3080 bus_dmamap_sync(sc->dc_tx_ltag, sc->dc_tx_lmap, 3081 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 3082 } 3083 3084 static void 3085 dc_tick(void *xsc) 3086 { 3087 struct dc_softc *sc; 3088 struct mii_data *mii; 3089 struct ifnet *ifp; 3090 uint32_t r; 3091 3092 sc = xsc; 3093 DC_LOCK_ASSERT(sc); 3094 ifp = sc->dc_ifp; 3095 mii = device_get_softc(sc->dc_miibus); 3096 3097 /* 3098 * Reclaim transmitted frames for controllers that do 3099 * not generate TX completion interrupt for every frame. 3100 */ 3101 if (sc->dc_flags & DC_TX_USE_TX_INTR) 3102 dc_txeof(sc); 3103 3104 if (sc->dc_flags & DC_REDUCED_MII_POLL) { 3105 if (sc->dc_flags & DC_21143_NWAY) { 3106 r = CSR_READ_4(sc, DC_10BTSTAT); 3107 if (IFM_SUBTYPE(mii->mii_media_active) == 3108 IFM_100_TX && (r & DC_TSTAT_LS100)) { 3109 sc->dc_link = 0; 3110 mii_mediachg(mii); 3111 } 3112 if (IFM_SUBTYPE(mii->mii_media_active) == 3113 IFM_10_T && (r & DC_TSTAT_LS10)) { 3114 sc->dc_link = 0; 3115 mii_mediachg(mii); 3116 } 3117 if (sc->dc_link == 0) 3118 mii_tick(mii); 3119 } else { 3120 /* 3121 * For NICs which never report DC_RXSTATE_WAIT, we 3122 * have to bite the bullet... 3123 */ 3124 if ((DC_HAS_BROKEN_RXSTATE(sc) || (CSR_READ_4(sc, 3125 DC_ISR) & DC_ISR_RX_STATE) == DC_RXSTATE_WAIT) && 3126 sc->dc_cdata.dc_tx_cnt == 0) 3127 mii_tick(mii); 3128 } 3129 } else 3130 mii_tick(mii); 3131 3132 /* 3133 * When the init routine completes, we expect to be able to send 3134 * packets right away, and in fact the network code will send a 3135 * gratuitous ARP the moment the init routine marks the interface 3136 * as running. However, even though the MAC may have been initialized, 3137 * there may be a delay of a few seconds before the PHY completes 3138 * autonegotiation and the link is brought up. Any transmissions 3139 * made during that delay will be lost. Dealing with this is tricky: 3140 * we can't just pause in the init routine while waiting for the 3141 * PHY to come ready since that would bring the whole system to 3142 * a screeching halt for several seconds. 3143 * 3144 * What we do here is prevent the TX start routine from sending 3145 * any packets until a link has been established. After the 3146 * interface has been initialized, the tick routine will poll 3147 * the state of the PHY until the IFM_ACTIVE flag is set. Until 3148 * that time, packets will stay in the send queue, and once the 3149 * link comes up, they will be flushed out to the wire. 3150 */ 3151 if (sc->dc_link != 0 && !IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 3152 dc_start_locked(ifp); 3153 3154 if (sc->dc_flags & DC_21143_NWAY && !sc->dc_link) 3155 callout_reset(&sc->dc_stat_ch, hz/10, dc_tick, sc); 3156 else 3157 callout_reset(&sc->dc_stat_ch, hz, dc_tick, sc); 3158 } 3159 3160 /* 3161 * A transmit underrun has occurred. Back off the transmit threshold, 3162 * or switch to store and forward mode if we have to. 3163 */ 3164 static void 3165 dc_tx_underrun(struct dc_softc *sc) 3166 { 3167 uint32_t netcfg, isr; 3168 int i, reinit; 3169 3170 reinit = 0; 3171 netcfg = CSR_READ_4(sc, DC_NETCFG); 3172 device_printf(sc->dc_dev, "TX underrun -- "); 3173 if ((sc->dc_flags & DC_TX_STORENFWD) == 0) { 3174 if (sc->dc_txthresh + DC_TXTHRESH_INC > DC_TXTHRESH_MAX) { 3175 printf("using store and forward mode\n"); 3176 netcfg |= DC_NETCFG_STORENFWD; 3177 } else { 3178 printf("increasing TX threshold\n"); 3179 sc->dc_txthresh += DC_TXTHRESH_INC; 3180 netcfg &= ~DC_NETCFG_TX_THRESH; 3181 netcfg |= sc->dc_txthresh; 3182 } 3183 3184 if (DC_IS_INTEL(sc)) { 3185 /* 3186 * The real 21143 requires that the transmitter be idle 3187 * in order to change the transmit threshold or store 3188 * and forward state. 3189 */ 3190 CSR_WRITE_4(sc, DC_NETCFG, netcfg & ~DC_NETCFG_TX_ON); 3191 3192 for (i = 0; i < DC_TIMEOUT; i++) { 3193 isr = CSR_READ_4(sc, DC_ISR); 3194 if (isr & DC_ISR_TX_IDLE) 3195 break; 3196 DELAY(10); 3197 } 3198 if (i == DC_TIMEOUT) { 3199 device_printf(sc->dc_dev, 3200 "%s: failed to force tx to idle state\n", 3201 __func__); 3202 reinit++; 3203 } 3204 } 3205 } else { 3206 printf("resetting\n"); 3207 reinit++; 3208 } 3209 3210 if (reinit == 0) { 3211 CSR_WRITE_4(sc, DC_NETCFG, netcfg); 3212 if (DC_IS_INTEL(sc)) 3213 CSR_WRITE_4(sc, DC_NETCFG, netcfg | DC_NETCFG_TX_ON); 3214 } else { 3215 sc->dc_ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 3216 dc_init_locked(sc); 3217 } 3218 } 3219 3220 #ifdef DEVICE_POLLING 3221 static poll_handler_t dc_poll; 3222 3223 static int 3224 dc_poll(struct ifnet *ifp, enum poll_cmd cmd, int count) 3225 { 3226 struct dc_softc *sc = ifp->if_softc; 3227 int rx_npkts = 0; 3228 3229 DC_LOCK(sc); 3230 3231 if (!(ifp->if_drv_flags & IFF_DRV_RUNNING)) { 3232 DC_UNLOCK(sc); 3233 return (rx_npkts); 3234 } 3235 3236 sc->rxcycles = count; 3237 rx_npkts = dc_rxeof(sc); 3238 dc_txeof(sc); 3239 if (!IFQ_IS_EMPTY(&ifp->if_snd) && 3240 !(ifp->if_drv_flags & IFF_DRV_OACTIVE)) 3241 dc_start_locked(ifp); 3242 3243 if (cmd == POLL_AND_CHECK_STATUS) { /* also check status register */ 3244 uint32_t status; 3245 3246 status = CSR_READ_4(sc, DC_ISR); 3247 status &= (DC_ISR_RX_WATDOGTIMEO | DC_ISR_RX_NOBUF | 3248 DC_ISR_TX_NOBUF | DC_ISR_TX_IDLE | DC_ISR_TX_UNDERRUN | 3249 DC_ISR_BUS_ERR); 3250 if (!status) { 3251 DC_UNLOCK(sc); 3252 return (rx_npkts); 3253 } 3254 /* ack what we have */ 3255 CSR_WRITE_4(sc, DC_ISR, status); 3256 3257 if (status & (DC_ISR_RX_WATDOGTIMEO | DC_ISR_RX_NOBUF)) { 3258 uint32_t r = CSR_READ_4(sc, DC_FRAMESDISCARDED); 3259 if_inc_counter(ifp, IFCOUNTER_IERRORS, (r & 0xffff) + ((r >> 17) & 0x7ff)); 3260 3261 if (dc_rx_resync(sc)) 3262 dc_rxeof(sc); 3263 } 3264 /* restart transmit unit if necessary */ 3265 if (status & DC_ISR_TX_IDLE && sc->dc_cdata.dc_tx_cnt) 3266 CSR_WRITE_4(sc, DC_TXSTART, 0xFFFFFFFF); 3267 3268 if (status & DC_ISR_TX_UNDERRUN) 3269 dc_tx_underrun(sc); 3270 3271 if (status & DC_ISR_BUS_ERR) { 3272 if_printf(ifp, "%s: bus error\n", __func__); 3273 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 3274 dc_init_locked(sc); 3275 } 3276 } 3277 DC_UNLOCK(sc); 3278 return (rx_npkts); 3279 } 3280 #endif /* DEVICE_POLLING */ 3281 3282 static void 3283 dc_intr(void *arg) 3284 { 3285 struct dc_softc *sc; 3286 struct ifnet *ifp; 3287 uint32_t r, status; 3288 int n; 3289 3290 sc = arg; 3291 3292 if (sc->suspended) 3293 return; 3294 3295 DC_LOCK(sc); 3296 status = CSR_READ_4(sc, DC_ISR); 3297 if (status == 0xFFFFFFFF || (status & DC_INTRS) == 0) { 3298 DC_UNLOCK(sc); 3299 return; 3300 } 3301 ifp = sc->dc_ifp; 3302 #ifdef DEVICE_POLLING 3303 if (ifp->if_capenable & IFCAP_POLLING) { 3304 DC_UNLOCK(sc); 3305 return; 3306 } 3307 #endif 3308 /* Disable interrupts. */ 3309 CSR_WRITE_4(sc, DC_IMR, 0x00000000); 3310 3311 for (n = 16; n > 0; n--) { 3312 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) 3313 break; 3314 /* Ack interrupts. */ 3315 CSR_WRITE_4(sc, DC_ISR, status); 3316 3317 if (status & DC_ISR_RX_OK) { 3318 if (dc_rxeof(sc) == 0) { 3319 while (dc_rx_resync(sc)) 3320 dc_rxeof(sc); 3321 } 3322 } 3323 3324 if (status & (DC_ISR_TX_OK | DC_ISR_TX_NOBUF)) 3325 dc_txeof(sc); 3326 3327 if (status & DC_ISR_TX_IDLE) { 3328 dc_txeof(sc); 3329 if (sc->dc_cdata.dc_tx_cnt) { 3330 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_TX_ON); 3331 CSR_WRITE_4(sc, DC_TXSTART, 0xFFFFFFFF); 3332 } 3333 } 3334 3335 if (status & DC_ISR_TX_UNDERRUN) 3336 dc_tx_underrun(sc); 3337 3338 if ((status & DC_ISR_RX_WATDOGTIMEO) 3339 || (status & DC_ISR_RX_NOBUF)) { 3340 r = CSR_READ_4(sc, DC_FRAMESDISCARDED); 3341 if_inc_counter(ifp, IFCOUNTER_IERRORS, (r & 0xffff) + ((r >> 17) & 0x7ff)); 3342 if (dc_rxeof(sc) == 0) { 3343 while (dc_rx_resync(sc)) 3344 dc_rxeof(sc); 3345 } 3346 } 3347 3348 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 3349 dc_start_locked(ifp); 3350 3351 if (status & DC_ISR_BUS_ERR) { 3352 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 3353 dc_init_locked(sc); 3354 DC_UNLOCK(sc); 3355 return; 3356 } 3357 status = CSR_READ_4(sc, DC_ISR); 3358 if (status == 0xFFFFFFFF || (status & DC_INTRS) == 0) 3359 break; 3360 } 3361 3362 /* Re-enable interrupts. */ 3363 if (ifp->if_drv_flags & IFF_DRV_RUNNING) 3364 CSR_WRITE_4(sc, DC_IMR, DC_INTRS); 3365 3366 DC_UNLOCK(sc); 3367 } 3368 3369 /* 3370 * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data 3371 * pointers to the fragment pointers. 3372 */ 3373 static int 3374 dc_encap(struct dc_softc *sc, struct mbuf **m_head) 3375 { 3376 bus_dma_segment_t segs[DC_MAXFRAGS]; 3377 bus_dmamap_t map; 3378 struct dc_desc *f; 3379 struct mbuf *m; 3380 int cur, defragged, error, first, frag, i, idx, nseg; 3381 3382 m = NULL; 3383 defragged = 0; 3384 if (sc->dc_flags & DC_TX_COALESCE && 3385 ((*m_head)->m_next != NULL || sc->dc_flags & DC_TX_ALIGN)) { 3386 m = m_defrag(*m_head, M_NOWAIT); 3387 defragged = 1; 3388 } else { 3389 /* 3390 * Count the number of frags in this chain to see if we 3391 * need to m_collapse. Since the descriptor list is shared 3392 * by all packets, we'll m_collapse long chains so that they 3393 * do not use up the entire list, even if they would fit. 3394 */ 3395 i = 0; 3396 for (m = *m_head; m != NULL; m = m->m_next) 3397 i++; 3398 if (i > DC_TX_LIST_CNT / 4 || 3399 DC_TX_LIST_CNT - i + sc->dc_cdata.dc_tx_cnt <= 3400 DC_TX_LIST_RSVD) { 3401 m = m_collapse(*m_head, M_NOWAIT, DC_MAXFRAGS); 3402 defragged = 1; 3403 } 3404 } 3405 if (defragged != 0) { 3406 if (m == NULL) { 3407 m_freem(*m_head); 3408 *m_head = NULL; 3409 return (ENOBUFS); 3410 } 3411 *m_head = m; 3412 } 3413 3414 idx = sc->dc_cdata.dc_tx_prod; 3415 error = bus_dmamap_load_mbuf_sg(sc->dc_tx_mtag, 3416 sc->dc_cdata.dc_tx_map[idx], *m_head, segs, &nseg, 0); 3417 if (error == EFBIG) { 3418 if (defragged != 0 || (m = m_collapse(*m_head, M_NOWAIT, 3419 DC_MAXFRAGS)) == NULL) { 3420 m_freem(*m_head); 3421 *m_head = NULL; 3422 return (defragged != 0 ? error : ENOBUFS); 3423 } 3424 *m_head = m; 3425 error = bus_dmamap_load_mbuf_sg(sc->dc_tx_mtag, 3426 sc->dc_cdata.dc_tx_map[idx], *m_head, segs, &nseg, 0); 3427 if (error != 0) { 3428 m_freem(*m_head); 3429 *m_head = NULL; 3430 return (error); 3431 } 3432 } else if (error != 0) 3433 return (error); 3434 KASSERT(nseg <= DC_MAXFRAGS, 3435 ("%s: wrong number of segments (%d)", __func__, nseg)); 3436 if (nseg == 0) { 3437 m_freem(*m_head); 3438 *m_head = NULL; 3439 return (EIO); 3440 } 3441 3442 /* Check descriptor overruns. */ 3443 if (sc->dc_cdata.dc_tx_cnt + nseg > DC_TX_LIST_CNT - DC_TX_LIST_RSVD) { 3444 bus_dmamap_unload(sc->dc_tx_mtag, sc->dc_cdata.dc_tx_map[idx]); 3445 return (ENOBUFS); 3446 } 3447 bus_dmamap_sync(sc->dc_tx_mtag, sc->dc_cdata.dc_tx_map[idx], 3448 BUS_DMASYNC_PREWRITE); 3449 3450 first = cur = frag = sc->dc_cdata.dc_tx_prod; 3451 for (i = 0; i < nseg; i++) { 3452 if ((sc->dc_flags & DC_TX_ADMTEK_WAR) && 3453 (frag == (DC_TX_LIST_CNT - 1)) && 3454 (first != sc->dc_cdata.dc_tx_first)) { 3455 bus_dmamap_unload(sc->dc_tx_mtag, 3456 sc->dc_cdata.dc_tx_map[first]); 3457 m_freem(*m_head); 3458 *m_head = NULL; 3459 return (ENOBUFS); 3460 } 3461 3462 f = &sc->dc_ldata.dc_tx_list[frag]; 3463 f->dc_ctl = htole32(DC_TXCTL_TLINK | segs[i].ds_len); 3464 if (i == 0) { 3465 f->dc_status = 0; 3466 f->dc_ctl |= htole32(DC_TXCTL_FIRSTFRAG); 3467 } else 3468 f->dc_status = htole32(DC_TXSTAT_OWN); 3469 f->dc_data = htole32(DC_ADDR_LO(segs[i].ds_addr)); 3470 cur = frag; 3471 DC_INC(frag, DC_TX_LIST_CNT); 3472 } 3473 3474 sc->dc_cdata.dc_tx_prod = frag; 3475 sc->dc_cdata.dc_tx_cnt += nseg; 3476 sc->dc_cdata.dc_tx_chain[cur] = *m_head; 3477 sc->dc_ldata.dc_tx_list[cur].dc_ctl |= htole32(DC_TXCTL_LASTFRAG); 3478 if (sc->dc_flags & DC_TX_INTR_FIRSTFRAG) 3479 sc->dc_ldata.dc_tx_list[first].dc_ctl |= 3480 htole32(DC_TXCTL_FINT); 3481 if (sc->dc_flags & DC_TX_INTR_ALWAYS) 3482 sc->dc_ldata.dc_tx_list[cur].dc_ctl |= htole32(DC_TXCTL_FINT); 3483 if (sc->dc_flags & DC_TX_USE_TX_INTR && 3484 ++sc->dc_cdata.dc_tx_pkts >= 8) { 3485 sc->dc_cdata.dc_tx_pkts = 0; 3486 sc->dc_ldata.dc_tx_list[cur].dc_ctl |= htole32(DC_TXCTL_FINT); 3487 } 3488 sc->dc_ldata.dc_tx_list[first].dc_status = htole32(DC_TXSTAT_OWN); 3489 3490 bus_dmamap_sync(sc->dc_tx_ltag, sc->dc_tx_lmap, 3491 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 3492 3493 /* 3494 * Swap the last and the first dmamaps to ensure the map for 3495 * this transmission is placed at the last descriptor. 3496 */ 3497 map = sc->dc_cdata.dc_tx_map[cur]; 3498 sc->dc_cdata.dc_tx_map[cur] = sc->dc_cdata.dc_tx_map[first]; 3499 sc->dc_cdata.dc_tx_map[first] = map; 3500 3501 return (0); 3502 } 3503 3504 static void 3505 dc_start(struct ifnet *ifp) 3506 { 3507 struct dc_softc *sc; 3508 3509 sc = ifp->if_softc; 3510 DC_LOCK(sc); 3511 dc_start_locked(ifp); 3512 DC_UNLOCK(sc); 3513 } 3514 3515 /* 3516 * Main transmit routine 3517 * To avoid having to do mbuf copies, we put pointers to the mbuf data 3518 * regions directly in the transmit lists. We also save a copy of the 3519 * pointers since the transmit list fragment pointers are physical 3520 * addresses. 3521 */ 3522 static void 3523 dc_start_locked(struct ifnet *ifp) 3524 { 3525 struct dc_softc *sc; 3526 struct mbuf *m_head; 3527 int queued; 3528 3529 sc = ifp->if_softc; 3530 3531 DC_LOCK_ASSERT(sc); 3532 3533 if ((ifp->if_drv_flags & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) != 3534 IFF_DRV_RUNNING || sc->dc_link == 0) 3535 return; 3536 3537 sc->dc_cdata.dc_tx_first = sc->dc_cdata.dc_tx_prod; 3538 3539 for (queued = 0; !IFQ_DRV_IS_EMPTY(&ifp->if_snd); ) { 3540 /* 3541 * If there's no way we can send any packets, return now. 3542 */ 3543 if (sc->dc_cdata.dc_tx_cnt > DC_TX_LIST_CNT - DC_TX_LIST_RSVD) { 3544 ifp->if_drv_flags |= IFF_DRV_OACTIVE; 3545 break; 3546 } 3547 IFQ_DRV_DEQUEUE(&ifp->if_snd, m_head); 3548 if (m_head == NULL) 3549 break; 3550 3551 if (dc_encap(sc, &m_head)) { 3552 if (m_head == NULL) 3553 break; 3554 IFQ_DRV_PREPEND(&ifp->if_snd, m_head); 3555 ifp->if_drv_flags |= IFF_DRV_OACTIVE; 3556 break; 3557 } 3558 3559 queued++; 3560 /* 3561 * If there's a BPF listener, bounce a copy of this frame 3562 * to him. 3563 */ 3564 BPF_MTAP(ifp, m_head); 3565 } 3566 3567 if (queued > 0) { 3568 /* Transmit */ 3569 if (!(sc->dc_flags & DC_TX_POLL)) 3570 CSR_WRITE_4(sc, DC_TXSTART, 0xFFFFFFFF); 3571 3572 /* 3573 * Set a timeout in case the chip goes out to lunch. 3574 */ 3575 sc->dc_wdog_timer = 5; 3576 } 3577 } 3578 3579 static void 3580 dc_init(void *xsc) 3581 { 3582 struct dc_softc *sc = xsc; 3583 3584 DC_LOCK(sc); 3585 dc_init_locked(sc); 3586 DC_UNLOCK(sc); 3587 } 3588 3589 static void 3590 dc_init_locked(struct dc_softc *sc) 3591 { 3592 struct ifnet *ifp = sc->dc_ifp; 3593 struct mii_data *mii; 3594 struct ifmedia *ifm; 3595 3596 DC_LOCK_ASSERT(sc); 3597 3598 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) 3599 return; 3600 3601 mii = device_get_softc(sc->dc_miibus); 3602 3603 /* 3604 * Cancel pending I/O and free all RX/TX buffers. 3605 */ 3606 dc_stop(sc); 3607 dc_reset(sc); 3608 if (DC_IS_INTEL(sc)) { 3609 ifm = &mii->mii_media; 3610 dc_apply_fixup(sc, ifm->ifm_media); 3611 } 3612 3613 /* 3614 * Set cache alignment and burst length. 3615 */ 3616 if (DC_IS_ASIX(sc) || DC_IS_DAVICOM(sc) || DC_IS_ULI(sc)) 3617 CSR_WRITE_4(sc, DC_BUSCTL, 0); 3618 else 3619 CSR_WRITE_4(sc, DC_BUSCTL, DC_BUSCTL_MRME | DC_BUSCTL_MRLE); 3620 /* 3621 * Evenly share the bus between receive and transmit process. 3622 */ 3623 if (DC_IS_INTEL(sc)) 3624 DC_SETBIT(sc, DC_BUSCTL, DC_BUSCTL_ARBITRATION); 3625 if (DC_IS_DAVICOM(sc) || DC_IS_INTEL(sc)) { 3626 DC_SETBIT(sc, DC_BUSCTL, DC_BURSTLEN_USECA); 3627 } else { 3628 DC_SETBIT(sc, DC_BUSCTL, DC_BURSTLEN_16LONG); 3629 } 3630 if (sc->dc_flags & DC_TX_POLL) 3631 DC_SETBIT(sc, DC_BUSCTL, DC_TXPOLL_1); 3632 switch(sc->dc_cachesize) { 3633 case 32: 3634 DC_SETBIT(sc, DC_BUSCTL, DC_CACHEALIGN_32LONG); 3635 break; 3636 case 16: 3637 DC_SETBIT(sc, DC_BUSCTL, DC_CACHEALIGN_16LONG); 3638 break; 3639 case 8: 3640 DC_SETBIT(sc, DC_BUSCTL, DC_CACHEALIGN_8LONG); 3641 break; 3642 case 0: 3643 default: 3644 DC_SETBIT(sc, DC_BUSCTL, DC_CACHEALIGN_NONE); 3645 break; 3646 } 3647 3648 if (sc->dc_flags & DC_TX_STORENFWD) 3649 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_STORENFWD); 3650 else { 3651 if (sc->dc_txthresh > DC_TXTHRESH_MAX) { 3652 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_STORENFWD); 3653 } else { 3654 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_STORENFWD); 3655 DC_SETBIT(sc, DC_NETCFG, sc->dc_txthresh); 3656 } 3657 } 3658 3659 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_NO_RXCRC); 3660 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_TX_BACKOFF); 3661 3662 if (DC_IS_MACRONIX(sc) || DC_IS_PNICII(sc)) { 3663 /* 3664 * The app notes for the 98713 and 98715A say that 3665 * in order to have the chips operate properly, a magic 3666 * number must be written to CSR16. Macronix does not 3667 * document the meaning of these bits so there's no way 3668 * to know exactly what they do. The 98713 has a magic 3669 * number all its own; the rest all use a different one. 3670 */ 3671 DC_CLRBIT(sc, DC_MX_MAGICPACKET, 0xFFFF0000); 3672 if (sc->dc_type == DC_TYPE_98713) 3673 DC_SETBIT(sc, DC_MX_MAGICPACKET, DC_MX_MAGIC_98713); 3674 else 3675 DC_SETBIT(sc, DC_MX_MAGICPACKET, DC_MX_MAGIC_98715); 3676 } 3677 3678 if (DC_IS_XIRCOM(sc)) { 3679 /* 3680 * setup General Purpose Port mode and data so the tulip 3681 * can talk to the MII. 3682 */ 3683 CSR_WRITE_4(sc, DC_SIAGP, DC_SIAGP_WRITE_EN | DC_SIAGP_INT1_EN | 3684 DC_SIAGP_MD_GP2_OUTPUT | DC_SIAGP_MD_GP0_OUTPUT); 3685 DELAY(10); 3686 CSR_WRITE_4(sc, DC_SIAGP, DC_SIAGP_INT1_EN | 3687 DC_SIAGP_MD_GP2_OUTPUT | DC_SIAGP_MD_GP0_OUTPUT); 3688 DELAY(10); 3689 } 3690 3691 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_TX_THRESH); 3692 DC_SETBIT(sc, DC_NETCFG, DC_TXTHRESH_MIN); 3693 3694 /* Init circular RX list. */ 3695 if (dc_list_rx_init(sc) == ENOBUFS) { 3696 device_printf(sc->dc_dev, 3697 "initialization failed: no memory for rx buffers\n"); 3698 dc_stop(sc); 3699 return; 3700 } 3701 3702 /* 3703 * Init TX descriptors. 3704 */ 3705 dc_list_tx_init(sc); 3706 3707 /* 3708 * Load the address of the RX list. 3709 */ 3710 CSR_WRITE_4(sc, DC_RXADDR, DC_RXDESC(sc, 0)); 3711 CSR_WRITE_4(sc, DC_TXADDR, DC_TXDESC(sc, 0)); 3712 3713 /* 3714 * Enable interrupts. 3715 */ 3716 #ifdef DEVICE_POLLING 3717 /* 3718 * ... but only if we are not polling, and make sure they are off in 3719 * the case of polling. Some cards (e.g. fxp) turn interrupts on 3720 * after a reset. 3721 */ 3722 if (ifp->if_capenable & IFCAP_POLLING) 3723 CSR_WRITE_4(sc, DC_IMR, 0x00000000); 3724 else 3725 #endif 3726 CSR_WRITE_4(sc, DC_IMR, DC_INTRS); 3727 CSR_WRITE_4(sc, DC_ISR, 0xFFFFFFFF); 3728 3729 /* Initialize TX jabber and RX watchdog timer. */ 3730 if (DC_IS_ULI(sc)) 3731 CSR_WRITE_4(sc, DC_WATCHDOG, DC_WDOG_JABBERCLK | 3732 DC_WDOG_HOSTUNJAB); 3733 3734 /* Enable transmitter. */ 3735 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_TX_ON); 3736 3737 /* 3738 * If this is an Intel 21143 and we're not using the 3739 * MII port, program the LED control pins so we get 3740 * link and activity indications. 3741 */ 3742 if (sc->dc_flags & DC_TULIP_LEDS) { 3743 CSR_WRITE_4(sc, DC_WATCHDOG, 3744 DC_WDOG_CTLWREN | DC_WDOG_LINK | DC_WDOG_ACTIVITY); 3745 CSR_WRITE_4(sc, DC_WATCHDOG, 0); 3746 } 3747 3748 /* 3749 * Load the RX/multicast filter. We do this sort of late 3750 * because the filter programming scheme on the 21143 and 3751 * some clones requires DMAing a setup frame via the TX 3752 * engine, and we need the transmitter enabled for that. 3753 */ 3754 dc_setfilt(sc); 3755 3756 /* Enable receiver. */ 3757 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_ON); 3758 CSR_WRITE_4(sc, DC_RXSTART, 0xFFFFFFFF); 3759 3760 ifp->if_drv_flags |= IFF_DRV_RUNNING; 3761 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 3762 3763 dc_ifmedia_upd_locked(sc); 3764 3765 /* Clear missed frames and overflow counter. */ 3766 CSR_READ_4(sc, DC_FRAMESDISCARDED); 3767 3768 /* Don't start the ticker if this is a homePNA link. */ 3769 if (IFM_SUBTYPE(mii->mii_media.ifm_media) == IFM_HPNA_1) 3770 sc->dc_link = 1; 3771 else { 3772 if (sc->dc_flags & DC_21143_NWAY) 3773 callout_reset(&sc->dc_stat_ch, hz/10, dc_tick, sc); 3774 else 3775 callout_reset(&sc->dc_stat_ch, hz, dc_tick, sc); 3776 } 3777 3778 sc->dc_wdog_timer = 0; 3779 callout_reset(&sc->dc_wdog_ch, hz, dc_watchdog, sc); 3780 } 3781 3782 /* 3783 * Set media options. 3784 */ 3785 static int 3786 dc_ifmedia_upd(struct ifnet *ifp) 3787 { 3788 struct dc_softc *sc; 3789 int error; 3790 3791 sc = ifp->if_softc; 3792 DC_LOCK(sc); 3793 error = dc_ifmedia_upd_locked(sc); 3794 DC_UNLOCK(sc); 3795 return (error); 3796 } 3797 3798 static int 3799 dc_ifmedia_upd_locked(struct dc_softc *sc) 3800 { 3801 struct mii_data *mii; 3802 struct ifmedia *ifm; 3803 int error; 3804 3805 DC_LOCK_ASSERT(sc); 3806 3807 sc->dc_link = 0; 3808 mii = device_get_softc(sc->dc_miibus); 3809 error = mii_mediachg(mii); 3810 if (error == 0) { 3811 ifm = &mii->mii_media; 3812 if (DC_IS_INTEL(sc)) 3813 dc_setcfg(sc, ifm->ifm_media); 3814 else if (DC_IS_DAVICOM(sc) && 3815 IFM_SUBTYPE(ifm->ifm_media) == IFM_HPNA_1) 3816 dc_setcfg(sc, ifm->ifm_media); 3817 } 3818 3819 return (error); 3820 } 3821 3822 /* 3823 * Report current media status. 3824 */ 3825 static void 3826 dc_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 3827 { 3828 struct dc_softc *sc; 3829 struct mii_data *mii; 3830 struct ifmedia *ifm; 3831 3832 sc = ifp->if_softc; 3833 mii = device_get_softc(sc->dc_miibus); 3834 DC_LOCK(sc); 3835 mii_pollstat(mii); 3836 ifm = &mii->mii_media; 3837 if (DC_IS_DAVICOM(sc)) { 3838 if (IFM_SUBTYPE(ifm->ifm_media) == IFM_HPNA_1) { 3839 ifmr->ifm_active = ifm->ifm_media; 3840 ifmr->ifm_status = 0; 3841 DC_UNLOCK(sc); 3842 return; 3843 } 3844 } 3845 ifmr->ifm_active = mii->mii_media_active; 3846 ifmr->ifm_status = mii->mii_media_status; 3847 DC_UNLOCK(sc); 3848 } 3849 3850 static int 3851 dc_ioctl(struct ifnet *ifp, u_long command, caddr_t data) 3852 { 3853 struct dc_softc *sc = ifp->if_softc; 3854 struct ifreq *ifr = (struct ifreq *)data; 3855 struct mii_data *mii; 3856 int error = 0; 3857 3858 switch (command) { 3859 case SIOCSIFFLAGS: 3860 DC_LOCK(sc); 3861 if (ifp->if_flags & IFF_UP) { 3862 int need_setfilt = (ifp->if_flags ^ sc->dc_if_flags) & 3863 (IFF_PROMISC | IFF_ALLMULTI); 3864 3865 if (ifp->if_drv_flags & IFF_DRV_RUNNING) { 3866 if (need_setfilt) 3867 dc_setfilt(sc); 3868 } else { 3869 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 3870 dc_init_locked(sc); 3871 } 3872 } else { 3873 if (ifp->if_drv_flags & IFF_DRV_RUNNING) 3874 dc_stop(sc); 3875 } 3876 sc->dc_if_flags = ifp->if_flags; 3877 DC_UNLOCK(sc); 3878 break; 3879 case SIOCADDMULTI: 3880 case SIOCDELMULTI: 3881 DC_LOCK(sc); 3882 if (ifp->if_drv_flags & IFF_DRV_RUNNING) 3883 dc_setfilt(sc); 3884 DC_UNLOCK(sc); 3885 break; 3886 case SIOCGIFMEDIA: 3887 case SIOCSIFMEDIA: 3888 mii = device_get_softc(sc->dc_miibus); 3889 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 3890 break; 3891 case SIOCSIFCAP: 3892 #ifdef DEVICE_POLLING 3893 if (ifr->ifr_reqcap & IFCAP_POLLING && 3894 !(ifp->if_capenable & IFCAP_POLLING)) { 3895 error = ether_poll_register(dc_poll, ifp); 3896 if (error) 3897 return(error); 3898 DC_LOCK(sc); 3899 /* Disable interrupts */ 3900 CSR_WRITE_4(sc, DC_IMR, 0x00000000); 3901 ifp->if_capenable |= IFCAP_POLLING; 3902 DC_UNLOCK(sc); 3903 return (error); 3904 } 3905 if (!(ifr->ifr_reqcap & IFCAP_POLLING) && 3906 ifp->if_capenable & IFCAP_POLLING) { 3907 error = ether_poll_deregister(ifp); 3908 /* Enable interrupts. */ 3909 DC_LOCK(sc); 3910 CSR_WRITE_4(sc, DC_IMR, DC_INTRS); 3911 ifp->if_capenable &= ~IFCAP_POLLING; 3912 DC_UNLOCK(sc); 3913 return (error); 3914 } 3915 #endif /* DEVICE_POLLING */ 3916 break; 3917 default: 3918 error = ether_ioctl(ifp, command, data); 3919 break; 3920 } 3921 3922 return (error); 3923 } 3924 3925 static void 3926 dc_watchdog(void *xsc) 3927 { 3928 struct dc_softc *sc = xsc; 3929 struct ifnet *ifp; 3930 3931 DC_LOCK_ASSERT(sc); 3932 3933 if (sc->dc_wdog_timer == 0 || --sc->dc_wdog_timer != 0) { 3934 callout_reset(&sc->dc_wdog_ch, hz, dc_watchdog, sc); 3935 return; 3936 } 3937 3938 ifp = sc->dc_ifp; 3939 if_inc_counter(ifp, IFCOUNTER_OERRORS, 1); 3940 device_printf(sc->dc_dev, "watchdog timeout\n"); 3941 3942 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 3943 dc_init_locked(sc); 3944 3945 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 3946 dc_start_locked(ifp); 3947 } 3948 3949 /* 3950 * Stop the adapter and free any mbufs allocated to the 3951 * RX and TX lists. 3952 */ 3953 static void 3954 dc_stop(struct dc_softc *sc) 3955 { 3956 struct ifnet *ifp; 3957 struct dc_list_data *ld; 3958 struct dc_chain_data *cd; 3959 int i; 3960 uint32_t ctl, netcfg; 3961 3962 DC_LOCK_ASSERT(sc); 3963 3964 ifp = sc->dc_ifp; 3965 ld = &sc->dc_ldata; 3966 cd = &sc->dc_cdata; 3967 3968 callout_stop(&sc->dc_stat_ch); 3969 callout_stop(&sc->dc_wdog_ch); 3970 sc->dc_wdog_timer = 0; 3971 sc->dc_link = 0; 3972 3973 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE); 3974 3975 netcfg = CSR_READ_4(sc, DC_NETCFG); 3976 if (netcfg & (DC_NETCFG_RX_ON | DC_NETCFG_TX_ON)) 3977 CSR_WRITE_4(sc, DC_NETCFG, 3978 netcfg & ~(DC_NETCFG_RX_ON | DC_NETCFG_TX_ON)); 3979 CSR_WRITE_4(sc, DC_IMR, 0x00000000); 3980 /* Wait the completion of TX/RX SM. */ 3981 if (netcfg & (DC_NETCFG_RX_ON | DC_NETCFG_TX_ON)) 3982 dc_netcfg_wait(sc); 3983 3984 CSR_WRITE_4(sc, DC_TXADDR, 0x00000000); 3985 CSR_WRITE_4(sc, DC_RXADDR, 0x00000000); 3986 3987 /* 3988 * Free data in the RX lists. 3989 */ 3990 for (i = 0; i < DC_RX_LIST_CNT; i++) { 3991 if (cd->dc_rx_chain[i] != NULL) { 3992 bus_dmamap_sync(sc->dc_rx_mtag, 3993 cd->dc_rx_map[i], BUS_DMASYNC_POSTREAD); 3994 bus_dmamap_unload(sc->dc_rx_mtag, 3995 cd->dc_rx_map[i]); 3996 m_freem(cd->dc_rx_chain[i]); 3997 cd->dc_rx_chain[i] = NULL; 3998 } 3999 } 4000 bzero(ld->dc_rx_list, DC_RX_LIST_SZ); 4001 bus_dmamap_sync(sc->dc_rx_ltag, sc->dc_rx_lmap, 4002 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 4003 4004 /* 4005 * Free the TX list buffers. 4006 */ 4007 for (i = 0; i < DC_TX_LIST_CNT; i++) { 4008 if (cd->dc_tx_chain[i] != NULL) { 4009 ctl = le32toh(ld->dc_tx_list[i].dc_ctl); 4010 if (ctl & DC_TXCTL_SETUP) { 4011 bus_dmamap_sync(sc->dc_stag, sc->dc_smap, 4012 BUS_DMASYNC_POSTWRITE); 4013 } else { 4014 bus_dmamap_sync(sc->dc_tx_mtag, 4015 cd->dc_tx_map[i], BUS_DMASYNC_POSTWRITE); 4016 bus_dmamap_unload(sc->dc_tx_mtag, 4017 cd->dc_tx_map[i]); 4018 m_freem(cd->dc_tx_chain[i]); 4019 } 4020 cd->dc_tx_chain[i] = NULL; 4021 } 4022 } 4023 bzero(ld->dc_tx_list, DC_TX_LIST_SZ); 4024 bus_dmamap_sync(sc->dc_tx_ltag, sc->dc_tx_lmap, 4025 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 4026 } 4027 4028 /* 4029 * Device suspend routine. Stop the interface and save some PCI 4030 * settings in case the BIOS doesn't restore them properly on 4031 * resume. 4032 */ 4033 static int 4034 dc_suspend(device_t dev) 4035 { 4036 struct dc_softc *sc; 4037 4038 sc = device_get_softc(dev); 4039 DC_LOCK(sc); 4040 dc_stop(sc); 4041 sc->suspended = 1; 4042 DC_UNLOCK(sc); 4043 4044 return (0); 4045 } 4046 4047 /* 4048 * Device resume routine. Restore some PCI settings in case the BIOS 4049 * doesn't, re-enable busmastering, and restart the interface if 4050 * appropriate. 4051 */ 4052 static int 4053 dc_resume(device_t dev) 4054 { 4055 struct dc_softc *sc; 4056 struct ifnet *ifp; 4057 4058 sc = device_get_softc(dev); 4059 ifp = sc->dc_ifp; 4060 4061 /* reinitialize interface if necessary */ 4062 DC_LOCK(sc); 4063 if (ifp->if_flags & IFF_UP) 4064 dc_init_locked(sc); 4065 4066 sc->suspended = 0; 4067 DC_UNLOCK(sc); 4068 4069 return (0); 4070 } 4071 4072 /* 4073 * Stop all chip I/O so that the kernel's probe routines don't 4074 * get confused by errant DMAs when rebooting. 4075 */ 4076 static int 4077 dc_shutdown(device_t dev) 4078 { 4079 struct dc_softc *sc; 4080 4081 sc = device_get_softc(dev); 4082 4083 DC_LOCK(sc); 4084 dc_stop(sc); 4085 DC_UNLOCK(sc); 4086 4087 return (0); 4088 } 4089 4090 static int 4091 dc_check_multiport(struct dc_softc *sc) 4092 { 4093 struct dc_softc *dsc; 4094 devclass_t dc; 4095 device_t child; 4096 uint8_t *eaddr; 4097 int unit; 4098 4099 dc = devclass_find("dc"); 4100 for (unit = 0; unit < devclass_get_maxunit(dc); unit++) { 4101 child = devclass_get_device(dc, unit); 4102 if (child == NULL) 4103 continue; 4104 if (child == sc->dc_dev) 4105 continue; 4106 if (device_get_parent(child) != device_get_parent(sc->dc_dev)) 4107 continue; 4108 if (unit > device_get_unit(sc->dc_dev)) 4109 continue; 4110 if (device_is_attached(child) == 0) 4111 continue; 4112 dsc = device_get_softc(child); 4113 device_printf(sc->dc_dev, 4114 "Using station address of %s as base\n", 4115 device_get_nameunit(child)); 4116 bcopy(dsc->dc_eaddr, sc->dc_eaddr, ETHER_ADDR_LEN); 4117 eaddr = (uint8_t *)sc->dc_eaddr; 4118 eaddr[5]++; 4119 /* Prepare SROM to parse again. */ 4120 if (DC_IS_INTEL(sc) && dsc->dc_srom != NULL && 4121 sc->dc_romwidth != 0) { 4122 free(sc->dc_srom, M_DEVBUF); 4123 sc->dc_romwidth = dsc->dc_romwidth; 4124 sc->dc_srom = malloc(DC_ROM_SIZE(sc->dc_romwidth), 4125 M_DEVBUF, M_NOWAIT); 4126 if (sc->dc_srom == NULL) { 4127 device_printf(sc->dc_dev, 4128 "Could not allocate SROM buffer\n"); 4129 return (ENOMEM); 4130 } 4131 bcopy(dsc->dc_srom, sc->dc_srom, 4132 DC_ROM_SIZE(sc->dc_romwidth)); 4133 } 4134 return (0); 4135 } 4136 return (ENOENT); 4137 } 4138