1 /*- 2 * Copyright (c) 1997, 1998, 1999 3 * Bill Paul <wpaul@ee.columbia.edu>. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 3. All advertising materials mentioning features or use of this software 14 * must display the following acknowledgement: 15 * This product includes software developed by Bill Paul. 16 * 4. Neither the name of the author nor the names of any co-contributors 17 * may be used to endorse or promote products derived from this software 18 * without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30 * THE POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33 #include <sys/cdefs.h> 34 __FBSDID("$FreeBSD$"); 35 36 /* 37 * DEC "tulip" clone ethernet driver. Supports the DEC/Intel 21143 38 * series chips and several workalikes including the following: 39 * 40 * Macronix 98713/98715/98725/98727/98732 PMAC (www.macronix.com) 41 * Macronix/Lite-On 82c115 PNIC II (www.macronix.com) 42 * Lite-On 82c168/82c169 PNIC (www.litecom.com) 43 * ASIX Electronics AX88140A (www.asix.com.tw) 44 * ASIX Electronics AX88141 (www.asix.com.tw) 45 * ADMtek AL981 (www.admtek.com.tw) 46 * ADMtek AN983 (www.admtek.com.tw) 47 * ADMtek CardBus AN985 (www.admtek.com.tw) 48 * Netgear FA511 (www.netgear.com) Appears to be rebadged ADMTek CardBus AN985 49 * Davicom DM9100, DM9102, DM9102A (www.davicom8.com) 50 * Accton EN1217 (www.accton.com) 51 * Xircom X3201 (www.xircom.com) 52 * Abocom FE2500 53 * Conexant LANfinity (www.conexant.com) 54 * 3Com OfficeConnect 10/100B 3CSOHO100B (www.3com.com) 55 * 56 * Datasheets for the 21143 are available at developer.intel.com. 57 * Datasheets for the clone parts can be found at their respective sites. 58 * (Except for the PNIC; see www.freebsd.org/~wpaul/PNIC/pnic.ps.gz.) 59 * The PNIC II is essentially a Macronix 98715A chip; the only difference 60 * worth noting is that its multicast hash table is only 128 bits wide 61 * instead of 512. 62 * 63 * Written by Bill Paul <wpaul@ee.columbia.edu> 64 * Electrical Engineering Department 65 * Columbia University, New York City 66 */ 67 /* 68 * The Intel 21143 is the successor to the DEC 21140. It is basically 69 * the same as the 21140 but with a few new features. The 21143 supports 70 * three kinds of media attachments: 71 * 72 * o MII port, for 10Mbps and 100Mbps support and NWAY 73 * autonegotiation provided by an external PHY. 74 * o SYM port, for symbol mode 100Mbps support. 75 * o 10baseT port. 76 * o AUI/BNC port. 77 * 78 * The 100Mbps SYM port and 10baseT port can be used together in 79 * combination with the internal NWAY support to create a 10/100 80 * autosensing configuration. 81 * 82 * Note that not all tulip workalikes are handled in this driver: we only 83 * deal with those which are relatively well behaved. The Winbond is 84 * handled separately due to its different register offsets and the 85 * special handling needed for its various bugs. The PNIC is handled 86 * here, but I'm not thrilled about it. 87 * 88 * All of the workalike chips use some form of MII transceiver support 89 * with the exception of the Macronix chips, which also have a SYM port. 90 * The ASIX AX88140A is also documented to have a SYM port, but all 91 * the cards I've seen use an MII transceiver, probably because the 92 * AX88140A doesn't support internal NWAY. 93 */ 94 95 #ifdef HAVE_KERNEL_OPTION_HEADERS 96 #include "opt_device_polling.h" 97 #endif 98 99 #include <sys/param.h> 100 #include <sys/endian.h> 101 #include <sys/systm.h> 102 #include <sys/sockio.h> 103 #include <sys/mbuf.h> 104 #include <sys/malloc.h> 105 #include <sys/kernel.h> 106 #include <sys/module.h> 107 #include <sys/socket.h> 108 109 #include <net/if.h> 110 #include <net/if_var.h> 111 #include <net/if_arp.h> 112 #include <net/ethernet.h> 113 #include <net/if_dl.h> 114 #include <net/if_media.h> 115 #include <net/if_types.h> 116 #include <net/if_vlan_var.h> 117 118 #include <net/bpf.h> 119 120 #include <machine/bus.h> 121 #include <machine/resource.h> 122 #include <sys/bus.h> 123 #include <sys/rman.h> 124 125 #include <dev/mii/mii.h> 126 #include <dev/mii/mii_bitbang.h> 127 #include <dev/mii/miivar.h> 128 129 #include <dev/pci/pcireg.h> 130 #include <dev/pci/pcivar.h> 131 132 #define DC_USEIOSPACE 133 134 #include <dev/dc/if_dcreg.h> 135 136 #ifdef __sparc64__ 137 #include <dev/ofw/openfirm.h> 138 #include <machine/ofw_machdep.h> 139 #endif 140 141 MODULE_DEPEND(dc, pci, 1, 1, 1); 142 MODULE_DEPEND(dc, ether, 1, 1, 1); 143 MODULE_DEPEND(dc, miibus, 1, 1, 1); 144 145 /* 146 * "device miibus" is required in kernel config. See GENERIC if you get 147 * errors here. 148 */ 149 #include "miibus_if.h" 150 151 /* 152 * Various supported device vendors/types and their names. 153 */ 154 static const struct dc_type dc_devs[] = { 155 { DC_DEVID(DC_VENDORID_DEC, DC_DEVICEID_21143), 0, 156 "Intel 21143 10/100BaseTX" }, 157 { DC_DEVID(DC_VENDORID_DAVICOM, DC_DEVICEID_DM9009), 0, 158 "Davicom DM9009 10/100BaseTX" }, 159 { DC_DEVID(DC_VENDORID_DAVICOM, DC_DEVICEID_DM9100), 0, 160 "Davicom DM9100 10/100BaseTX" }, 161 { DC_DEVID(DC_VENDORID_DAVICOM, DC_DEVICEID_DM9102), DC_REVISION_DM9102A, 162 "Davicom DM9102A 10/100BaseTX" }, 163 { DC_DEVID(DC_VENDORID_DAVICOM, DC_DEVICEID_DM9102), 0, 164 "Davicom DM9102 10/100BaseTX" }, 165 { DC_DEVID(DC_VENDORID_ADMTEK, DC_DEVICEID_AL981), 0, 166 "ADMtek AL981 10/100BaseTX" }, 167 { DC_DEVID(DC_VENDORID_ADMTEK, DC_DEVICEID_AN983), 0, 168 "ADMtek AN983 10/100BaseTX" }, 169 { DC_DEVID(DC_VENDORID_ADMTEK, DC_DEVICEID_AN985), 0, 170 "ADMtek AN985 CardBus 10/100BaseTX or clone" }, 171 { DC_DEVID(DC_VENDORID_ADMTEK, DC_DEVICEID_ADM9511), 0, 172 "ADMtek ADM9511 10/100BaseTX" }, 173 { DC_DEVID(DC_VENDORID_ADMTEK, DC_DEVICEID_ADM9513), 0, 174 "ADMtek ADM9513 10/100BaseTX" }, 175 { DC_DEVID(DC_VENDORID_ASIX, DC_DEVICEID_AX88140A), DC_REVISION_88141, 176 "ASIX AX88141 10/100BaseTX" }, 177 { DC_DEVID(DC_VENDORID_ASIX, DC_DEVICEID_AX88140A), 0, 178 "ASIX AX88140A 10/100BaseTX" }, 179 { DC_DEVID(DC_VENDORID_MX, DC_DEVICEID_98713), DC_REVISION_98713A, 180 "Macronix 98713A 10/100BaseTX" }, 181 { DC_DEVID(DC_VENDORID_MX, DC_DEVICEID_98713), 0, 182 "Macronix 98713 10/100BaseTX" }, 183 { DC_DEVID(DC_VENDORID_CP, DC_DEVICEID_98713_CP), DC_REVISION_98713A, 184 "Compex RL100-TX 10/100BaseTX" }, 185 { DC_DEVID(DC_VENDORID_CP, DC_DEVICEID_98713_CP), 0, 186 "Compex RL100-TX 10/100BaseTX" }, 187 { DC_DEVID(DC_VENDORID_MX, DC_DEVICEID_987x5), DC_REVISION_98725, 188 "Macronix 98725 10/100BaseTX" }, 189 { DC_DEVID(DC_VENDORID_MX, DC_DEVICEID_987x5), DC_REVISION_98715AEC_C, 190 "Macronix 98715AEC-C 10/100BaseTX" }, 191 { DC_DEVID(DC_VENDORID_MX, DC_DEVICEID_987x5), 0, 192 "Macronix 98715/98715A 10/100BaseTX" }, 193 { DC_DEVID(DC_VENDORID_MX, DC_DEVICEID_98727), 0, 194 "Macronix 98727/98732 10/100BaseTX" }, 195 { DC_DEVID(DC_VENDORID_LO, DC_DEVICEID_82C115), 0, 196 "LC82C115 PNIC II 10/100BaseTX" }, 197 { DC_DEVID(DC_VENDORID_LO, DC_DEVICEID_82C168), DC_REVISION_82C169, 198 "82c169 PNIC 10/100BaseTX" }, 199 { DC_DEVID(DC_VENDORID_LO, DC_DEVICEID_82C168), 0, 200 "82c168 PNIC 10/100BaseTX" }, 201 { DC_DEVID(DC_VENDORID_ACCTON, DC_DEVICEID_EN1217), 0, 202 "Accton EN1217 10/100BaseTX" }, 203 { DC_DEVID(DC_VENDORID_ACCTON, DC_DEVICEID_EN2242), 0, 204 "Accton EN2242 MiniPCI 10/100BaseTX" }, 205 { DC_DEVID(DC_VENDORID_XIRCOM, DC_DEVICEID_X3201), 0, 206 "Xircom X3201 10/100BaseTX" }, 207 { DC_DEVID(DC_VENDORID_DLINK, DC_DEVICEID_DRP32TXD), 0, 208 "Neteasy DRP-32TXD Cardbus 10/100" }, 209 { DC_DEVID(DC_VENDORID_ABOCOM, DC_DEVICEID_FE2500), 0, 210 "Abocom FE2500 10/100BaseTX" }, 211 { DC_DEVID(DC_VENDORID_ABOCOM, DC_DEVICEID_FE2500MX), 0, 212 "Abocom FE2500MX 10/100BaseTX" }, 213 { DC_DEVID(DC_VENDORID_CONEXANT, DC_DEVICEID_RS7112), 0, 214 "Conexant LANfinity MiniPCI 10/100BaseTX" }, 215 { DC_DEVID(DC_VENDORID_HAWKING, DC_DEVICEID_HAWKING_PN672TX), 0, 216 "Hawking CB102 CardBus 10/100" }, 217 { DC_DEVID(DC_VENDORID_PLANEX, DC_DEVICEID_FNW3602T), 0, 218 "PlaneX FNW-3602-T CardBus 10/100" }, 219 { DC_DEVID(DC_VENDORID_3COM, DC_DEVICEID_3CSOHOB), 0, 220 "3Com OfficeConnect 10/100B" }, 221 { DC_DEVID(DC_VENDORID_MICROSOFT, DC_DEVICEID_MSMN120), 0, 222 "Microsoft MN-120 CardBus 10/100" }, 223 { DC_DEVID(DC_VENDORID_MICROSOFT, DC_DEVICEID_MSMN130), 0, 224 "Microsoft MN-130 10/100" }, 225 { DC_DEVID(DC_VENDORID_LINKSYS, DC_DEVICEID_PCMPC200_AB08), 0, 226 "Linksys PCMPC200 CardBus 10/100" }, 227 { DC_DEVID(DC_VENDORID_LINKSYS, DC_DEVICEID_PCMPC200_AB09), 0, 228 "Linksys PCMPC200 CardBus 10/100" }, 229 { DC_DEVID(DC_VENDORID_ULI, DC_DEVICEID_M5261), 0, 230 "ULi M5261 FastEthernet" }, 231 { DC_DEVID(DC_VENDORID_ULI, DC_DEVICEID_M5263), 0, 232 "ULi M5263 FastEthernet" }, 233 { 0, 0, NULL } 234 }; 235 236 static int dc_probe(device_t); 237 static int dc_attach(device_t); 238 static int dc_detach(device_t); 239 static int dc_suspend(device_t); 240 static int dc_resume(device_t); 241 static const struct dc_type *dc_devtype(device_t); 242 static void dc_discard_rxbuf(struct dc_softc *, int); 243 static int dc_newbuf(struct dc_softc *, int); 244 static int dc_encap(struct dc_softc *, struct mbuf **); 245 static void dc_pnic_rx_bug_war(struct dc_softc *, int); 246 static int dc_rx_resync(struct dc_softc *); 247 static int dc_rxeof(struct dc_softc *); 248 static void dc_txeof(struct dc_softc *); 249 static void dc_tick(void *); 250 static void dc_tx_underrun(struct dc_softc *); 251 static void dc_intr(void *); 252 static void dc_start(struct ifnet *); 253 static void dc_start_locked(struct ifnet *); 254 static int dc_ioctl(struct ifnet *, u_long, caddr_t); 255 static void dc_init(void *); 256 static void dc_init_locked(struct dc_softc *); 257 static void dc_stop(struct dc_softc *); 258 static void dc_watchdog(void *); 259 static int dc_shutdown(device_t); 260 static int dc_ifmedia_upd(struct ifnet *); 261 static int dc_ifmedia_upd_locked(struct dc_softc *); 262 static void dc_ifmedia_sts(struct ifnet *, struct ifmediareq *); 263 264 static int dc_dma_alloc(struct dc_softc *); 265 static void dc_dma_free(struct dc_softc *); 266 static void dc_dma_map_addr(void *, bus_dma_segment_t *, int, int); 267 268 static void dc_delay(struct dc_softc *); 269 static void dc_eeprom_idle(struct dc_softc *); 270 static void dc_eeprom_putbyte(struct dc_softc *, int); 271 static void dc_eeprom_getword(struct dc_softc *, int, uint16_t *); 272 static void dc_eeprom_getword_pnic(struct dc_softc *, int, uint16_t *); 273 static void dc_eeprom_getword_xircom(struct dc_softc *, int, uint16_t *); 274 static void dc_eeprom_width(struct dc_softc *); 275 static void dc_read_eeprom(struct dc_softc *, caddr_t, int, int, int); 276 277 static int dc_miibus_readreg(device_t, int, int); 278 static int dc_miibus_writereg(device_t, int, int, int); 279 static void dc_miibus_statchg(device_t); 280 static void dc_miibus_mediainit(device_t); 281 282 static void dc_setcfg(struct dc_softc *, int); 283 static void dc_netcfg_wait(struct dc_softc *); 284 static uint32_t dc_mchash_le(struct dc_softc *, const uint8_t *); 285 static uint32_t dc_mchash_be(const uint8_t *); 286 static void dc_setfilt_21143(struct dc_softc *); 287 static void dc_setfilt_asix(struct dc_softc *); 288 static void dc_setfilt_admtek(struct dc_softc *); 289 static void dc_setfilt_uli(struct dc_softc *); 290 static void dc_setfilt_xircom(struct dc_softc *); 291 292 static void dc_setfilt(struct dc_softc *); 293 294 static void dc_reset(struct dc_softc *); 295 static int dc_list_rx_init(struct dc_softc *); 296 static int dc_list_tx_init(struct dc_softc *); 297 298 static int dc_read_srom(struct dc_softc *, int); 299 static int dc_parse_21143_srom(struct dc_softc *); 300 static int dc_decode_leaf_sia(struct dc_softc *, struct dc_eblock_sia *); 301 static int dc_decode_leaf_mii(struct dc_softc *, struct dc_eblock_mii *); 302 static int dc_decode_leaf_sym(struct dc_softc *, struct dc_eblock_sym *); 303 static void dc_apply_fixup(struct dc_softc *, int); 304 static int dc_check_multiport(struct dc_softc *); 305 306 /* 307 * MII bit-bang glue 308 */ 309 static uint32_t dc_mii_bitbang_read(device_t); 310 static void dc_mii_bitbang_write(device_t, uint32_t); 311 312 static const struct mii_bitbang_ops dc_mii_bitbang_ops = { 313 dc_mii_bitbang_read, 314 dc_mii_bitbang_write, 315 { 316 DC_SIO_MII_DATAOUT, /* MII_BIT_MDO */ 317 DC_SIO_MII_DATAIN, /* MII_BIT_MDI */ 318 DC_SIO_MII_CLK, /* MII_BIT_MDC */ 319 0, /* MII_BIT_DIR_HOST_PHY */ 320 DC_SIO_MII_DIR, /* MII_BIT_DIR_PHY_HOST */ 321 } 322 }; 323 324 #ifdef DC_USEIOSPACE 325 #define DC_RES SYS_RES_IOPORT 326 #define DC_RID DC_PCI_CFBIO 327 #else 328 #define DC_RES SYS_RES_MEMORY 329 #define DC_RID DC_PCI_CFBMA 330 #endif 331 332 static device_method_t dc_methods[] = { 333 /* Device interface */ 334 DEVMETHOD(device_probe, dc_probe), 335 DEVMETHOD(device_attach, dc_attach), 336 DEVMETHOD(device_detach, dc_detach), 337 DEVMETHOD(device_suspend, dc_suspend), 338 DEVMETHOD(device_resume, dc_resume), 339 DEVMETHOD(device_shutdown, dc_shutdown), 340 341 /* MII interface */ 342 DEVMETHOD(miibus_readreg, dc_miibus_readreg), 343 DEVMETHOD(miibus_writereg, dc_miibus_writereg), 344 DEVMETHOD(miibus_statchg, dc_miibus_statchg), 345 DEVMETHOD(miibus_mediainit, dc_miibus_mediainit), 346 347 DEVMETHOD_END 348 }; 349 350 static driver_t dc_driver = { 351 "dc", 352 dc_methods, 353 sizeof(struct dc_softc) 354 }; 355 356 static devclass_t dc_devclass; 357 358 DRIVER_MODULE_ORDERED(dc, pci, dc_driver, dc_devclass, NULL, NULL, 359 SI_ORDER_ANY); 360 DRIVER_MODULE(miibus, dc, miibus_driver, miibus_devclass, NULL, NULL); 361 362 #define DC_SETBIT(sc, reg, x) \ 363 CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) | (x)) 364 365 #define DC_CLRBIT(sc, reg, x) \ 366 CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) & ~(x)) 367 368 #define SIO_SET(x) DC_SETBIT(sc, DC_SIO, (x)) 369 #define SIO_CLR(x) DC_CLRBIT(sc, DC_SIO, (x)) 370 371 static void 372 dc_delay(struct dc_softc *sc) 373 { 374 int idx; 375 376 for (idx = (300 / 33) + 1; idx > 0; idx--) 377 CSR_READ_4(sc, DC_BUSCTL); 378 } 379 380 static void 381 dc_eeprom_width(struct dc_softc *sc) 382 { 383 int i; 384 385 /* Force EEPROM to idle state. */ 386 dc_eeprom_idle(sc); 387 388 /* Enter EEPROM access mode. */ 389 CSR_WRITE_4(sc, DC_SIO, DC_SIO_EESEL); 390 dc_delay(sc); 391 DC_SETBIT(sc, DC_SIO, DC_SIO_ROMCTL_READ); 392 dc_delay(sc); 393 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); 394 dc_delay(sc); 395 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CS); 396 dc_delay(sc); 397 398 for (i = 3; i--;) { 399 if (6 & (1 << i)) 400 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_DATAIN); 401 else 402 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_DATAIN); 403 dc_delay(sc); 404 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CLK); 405 dc_delay(sc); 406 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); 407 dc_delay(sc); 408 } 409 410 for (i = 1; i <= 12; i++) { 411 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CLK); 412 dc_delay(sc); 413 if (!(CSR_READ_4(sc, DC_SIO) & DC_SIO_EE_DATAOUT)) { 414 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); 415 dc_delay(sc); 416 break; 417 } 418 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); 419 dc_delay(sc); 420 } 421 422 /* Turn off EEPROM access mode. */ 423 dc_eeprom_idle(sc); 424 425 if (i < 4 || i > 12) 426 sc->dc_romwidth = 6; 427 else 428 sc->dc_romwidth = i; 429 430 /* Enter EEPROM access mode. */ 431 CSR_WRITE_4(sc, DC_SIO, DC_SIO_EESEL); 432 dc_delay(sc); 433 DC_SETBIT(sc, DC_SIO, DC_SIO_ROMCTL_READ); 434 dc_delay(sc); 435 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); 436 dc_delay(sc); 437 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CS); 438 dc_delay(sc); 439 440 /* Turn off EEPROM access mode. */ 441 dc_eeprom_idle(sc); 442 } 443 444 static void 445 dc_eeprom_idle(struct dc_softc *sc) 446 { 447 int i; 448 449 CSR_WRITE_4(sc, DC_SIO, DC_SIO_EESEL); 450 dc_delay(sc); 451 DC_SETBIT(sc, DC_SIO, DC_SIO_ROMCTL_READ); 452 dc_delay(sc); 453 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); 454 dc_delay(sc); 455 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CS); 456 dc_delay(sc); 457 458 for (i = 0; i < 25; i++) { 459 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); 460 dc_delay(sc); 461 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CLK); 462 dc_delay(sc); 463 } 464 465 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); 466 dc_delay(sc); 467 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CS); 468 dc_delay(sc); 469 CSR_WRITE_4(sc, DC_SIO, 0x00000000); 470 } 471 472 /* 473 * Send a read command and address to the EEPROM, check for ACK. 474 */ 475 static void 476 dc_eeprom_putbyte(struct dc_softc *sc, int addr) 477 { 478 int d, i; 479 480 d = DC_EECMD_READ >> 6; 481 for (i = 3; i--; ) { 482 if (d & (1 << i)) 483 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_DATAIN); 484 else 485 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_DATAIN); 486 dc_delay(sc); 487 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CLK); 488 dc_delay(sc); 489 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); 490 dc_delay(sc); 491 } 492 493 /* 494 * Feed in each bit and strobe the clock. 495 */ 496 for (i = sc->dc_romwidth; i--;) { 497 if (addr & (1 << i)) { 498 SIO_SET(DC_SIO_EE_DATAIN); 499 } else { 500 SIO_CLR(DC_SIO_EE_DATAIN); 501 } 502 dc_delay(sc); 503 SIO_SET(DC_SIO_EE_CLK); 504 dc_delay(sc); 505 SIO_CLR(DC_SIO_EE_CLK); 506 dc_delay(sc); 507 } 508 } 509 510 /* 511 * Read a word of data stored in the EEPROM at address 'addr.' 512 * The PNIC 82c168/82c169 has its own non-standard way to read 513 * the EEPROM. 514 */ 515 static void 516 dc_eeprom_getword_pnic(struct dc_softc *sc, int addr, uint16_t *dest) 517 { 518 int i; 519 uint32_t r; 520 521 CSR_WRITE_4(sc, DC_PN_SIOCTL, DC_PN_EEOPCODE_READ | addr); 522 523 for (i = 0; i < DC_TIMEOUT; i++) { 524 DELAY(1); 525 r = CSR_READ_4(sc, DC_SIO); 526 if (!(r & DC_PN_SIOCTL_BUSY)) { 527 *dest = (uint16_t)(r & 0xFFFF); 528 return; 529 } 530 } 531 } 532 533 /* 534 * Read a word of data stored in the EEPROM at address 'addr.' 535 * The Xircom X3201 has its own non-standard way to read 536 * the EEPROM, too. 537 */ 538 static void 539 dc_eeprom_getword_xircom(struct dc_softc *sc, int addr, uint16_t *dest) 540 { 541 542 SIO_SET(DC_SIO_ROMSEL | DC_SIO_ROMCTL_READ); 543 544 addr *= 2; 545 CSR_WRITE_4(sc, DC_ROM, addr | 0x160); 546 *dest = (uint16_t)CSR_READ_4(sc, DC_SIO) & 0xff; 547 addr += 1; 548 CSR_WRITE_4(sc, DC_ROM, addr | 0x160); 549 *dest |= ((uint16_t)CSR_READ_4(sc, DC_SIO) & 0xff) << 8; 550 551 SIO_CLR(DC_SIO_ROMSEL | DC_SIO_ROMCTL_READ); 552 } 553 554 /* 555 * Read a word of data stored in the EEPROM at address 'addr.' 556 */ 557 static void 558 dc_eeprom_getword(struct dc_softc *sc, int addr, uint16_t *dest) 559 { 560 int i; 561 uint16_t word = 0; 562 563 /* Force EEPROM to idle state. */ 564 dc_eeprom_idle(sc); 565 566 /* Enter EEPROM access mode. */ 567 CSR_WRITE_4(sc, DC_SIO, DC_SIO_EESEL); 568 dc_delay(sc); 569 DC_SETBIT(sc, DC_SIO, DC_SIO_ROMCTL_READ); 570 dc_delay(sc); 571 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); 572 dc_delay(sc); 573 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CS); 574 dc_delay(sc); 575 576 /* 577 * Send address of word we want to read. 578 */ 579 dc_eeprom_putbyte(sc, addr); 580 581 /* 582 * Start reading bits from EEPROM. 583 */ 584 for (i = 0x8000; i; i >>= 1) { 585 SIO_SET(DC_SIO_EE_CLK); 586 dc_delay(sc); 587 if (CSR_READ_4(sc, DC_SIO) & DC_SIO_EE_DATAOUT) 588 word |= i; 589 dc_delay(sc); 590 SIO_CLR(DC_SIO_EE_CLK); 591 dc_delay(sc); 592 } 593 594 /* Turn off EEPROM access mode. */ 595 dc_eeprom_idle(sc); 596 597 *dest = word; 598 } 599 600 /* 601 * Read a sequence of words from the EEPROM. 602 */ 603 static void 604 dc_read_eeprom(struct dc_softc *sc, caddr_t dest, int off, int cnt, int be) 605 { 606 int i; 607 uint16_t word = 0, *ptr; 608 609 for (i = 0; i < cnt; i++) { 610 if (DC_IS_PNIC(sc)) 611 dc_eeprom_getword_pnic(sc, off + i, &word); 612 else if (DC_IS_XIRCOM(sc)) 613 dc_eeprom_getword_xircom(sc, off + i, &word); 614 else 615 dc_eeprom_getword(sc, off + i, &word); 616 ptr = (uint16_t *)(dest + (i * 2)); 617 if (be) 618 *ptr = be16toh(word); 619 else 620 *ptr = le16toh(word); 621 } 622 } 623 624 /* 625 * Write the MII serial port for the MII bit-bang module. 626 */ 627 static void 628 dc_mii_bitbang_write(device_t dev, uint32_t val) 629 { 630 struct dc_softc *sc; 631 632 sc = device_get_softc(dev); 633 634 CSR_WRITE_4(sc, DC_SIO, val); 635 CSR_BARRIER_4(sc, DC_SIO, 636 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 637 } 638 639 /* 640 * Read the MII serial port for the MII bit-bang module. 641 */ 642 static uint32_t 643 dc_mii_bitbang_read(device_t dev) 644 { 645 struct dc_softc *sc; 646 uint32_t val; 647 648 sc = device_get_softc(dev); 649 650 val = CSR_READ_4(sc, DC_SIO); 651 CSR_BARRIER_4(sc, DC_SIO, 652 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 653 654 return (val); 655 } 656 657 static int 658 dc_miibus_readreg(device_t dev, int phy, int reg) 659 { 660 struct dc_softc *sc; 661 int i, rval, phy_reg = 0; 662 663 sc = device_get_softc(dev); 664 665 if (sc->dc_pmode != DC_PMODE_MII) { 666 if (phy == (MII_NPHY - 1)) { 667 switch (reg) { 668 case MII_BMSR: 669 /* 670 * Fake something to make the probe 671 * code think there's a PHY here. 672 */ 673 return (BMSR_MEDIAMASK); 674 break; 675 case MII_PHYIDR1: 676 if (DC_IS_PNIC(sc)) 677 return (DC_VENDORID_LO); 678 return (DC_VENDORID_DEC); 679 break; 680 case MII_PHYIDR2: 681 if (DC_IS_PNIC(sc)) 682 return (DC_DEVICEID_82C168); 683 return (DC_DEVICEID_21143); 684 break; 685 default: 686 return (0); 687 break; 688 } 689 } else 690 return (0); 691 } 692 693 if (DC_IS_PNIC(sc)) { 694 CSR_WRITE_4(sc, DC_PN_MII, DC_PN_MIIOPCODE_READ | 695 (phy << 23) | (reg << 18)); 696 for (i = 0; i < DC_TIMEOUT; i++) { 697 DELAY(1); 698 rval = CSR_READ_4(sc, DC_PN_MII); 699 if (!(rval & DC_PN_MII_BUSY)) { 700 rval &= 0xFFFF; 701 return (rval == 0xFFFF ? 0 : rval); 702 } 703 } 704 return (0); 705 } 706 707 if (sc->dc_type == DC_TYPE_ULI_M5263) { 708 CSR_WRITE_4(sc, DC_ROM, 709 ((phy << DC_ULI_PHY_ADDR_SHIFT) & DC_ULI_PHY_ADDR_MASK) | 710 ((reg << DC_ULI_PHY_REG_SHIFT) & DC_ULI_PHY_REG_MASK) | 711 DC_ULI_PHY_OP_READ); 712 for (i = 0; i < DC_TIMEOUT; i++) { 713 DELAY(1); 714 rval = CSR_READ_4(sc, DC_ROM); 715 if ((rval & DC_ULI_PHY_OP_DONE) != 0) { 716 return (rval & DC_ULI_PHY_DATA_MASK); 717 } 718 } 719 if (i == DC_TIMEOUT) 720 device_printf(dev, "phy read timed out\n"); 721 return (0); 722 } 723 724 if (DC_IS_COMET(sc)) { 725 switch (reg) { 726 case MII_BMCR: 727 phy_reg = DC_AL_BMCR; 728 break; 729 case MII_BMSR: 730 phy_reg = DC_AL_BMSR; 731 break; 732 case MII_PHYIDR1: 733 phy_reg = DC_AL_VENID; 734 break; 735 case MII_PHYIDR2: 736 phy_reg = DC_AL_DEVID; 737 break; 738 case MII_ANAR: 739 phy_reg = DC_AL_ANAR; 740 break; 741 case MII_ANLPAR: 742 phy_reg = DC_AL_LPAR; 743 break; 744 case MII_ANER: 745 phy_reg = DC_AL_ANER; 746 break; 747 default: 748 device_printf(dev, "phy_read: bad phy register %x\n", 749 reg); 750 return (0); 751 break; 752 } 753 754 rval = CSR_READ_4(sc, phy_reg) & 0x0000FFFF; 755 if (rval == 0xFFFF) 756 return (0); 757 return (rval); 758 } 759 760 if (sc->dc_type == DC_TYPE_98713) { 761 phy_reg = CSR_READ_4(sc, DC_NETCFG); 762 CSR_WRITE_4(sc, DC_NETCFG, phy_reg & ~DC_NETCFG_PORTSEL); 763 } 764 rval = mii_bitbang_readreg(dev, &dc_mii_bitbang_ops, phy, reg); 765 if (sc->dc_type == DC_TYPE_98713) 766 CSR_WRITE_4(sc, DC_NETCFG, phy_reg); 767 768 return (rval); 769 } 770 771 static int 772 dc_miibus_writereg(device_t dev, int phy, int reg, int data) 773 { 774 struct dc_softc *sc; 775 int i, phy_reg = 0; 776 777 sc = device_get_softc(dev); 778 779 if (DC_IS_PNIC(sc)) { 780 CSR_WRITE_4(sc, DC_PN_MII, DC_PN_MIIOPCODE_WRITE | 781 (phy << 23) | (reg << 10) | data); 782 for (i = 0; i < DC_TIMEOUT; i++) { 783 if (!(CSR_READ_4(sc, DC_PN_MII) & DC_PN_MII_BUSY)) 784 break; 785 } 786 return (0); 787 } 788 789 if (sc->dc_type == DC_TYPE_ULI_M5263) { 790 CSR_WRITE_4(sc, DC_ROM, 791 ((phy << DC_ULI_PHY_ADDR_SHIFT) & DC_ULI_PHY_ADDR_MASK) | 792 ((reg << DC_ULI_PHY_REG_SHIFT) & DC_ULI_PHY_REG_MASK) | 793 ((data << DC_ULI_PHY_DATA_SHIFT) & DC_ULI_PHY_DATA_MASK) | 794 DC_ULI_PHY_OP_WRITE); 795 DELAY(1); 796 return (0); 797 } 798 799 if (DC_IS_COMET(sc)) { 800 switch (reg) { 801 case MII_BMCR: 802 phy_reg = DC_AL_BMCR; 803 break; 804 case MII_BMSR: 805 phy_reg = DC_AL_BMSR; 806 break; 807 case MII_PHYIDR1: 808 phy_reg = DC_AL_VENID; 809 break; 810 case MII_PHYIDR2: 811 phy_reg = DC_AL_DEVID; 812 break; 813 case MII_ANAR: 814 phy_reg = DC_AL_ANAR; 815 break; 816 case MII_ANLPAR: 817 phy_reg = DC_AL_LPAR; 818 break; 819 case MII_ANER: 820 phy_reg = DC_AL_ANER; 821 break; 822 default: 823 device_printf(dev, "phy_write: bad phy register %x\n", 824 reg); 825 return (0); 826 break; 827 } 828 829 CSR_WRITE_4(sc, phy_reg, data); 830 return (0); 831 } 832 833 if (sc->dc_type == DC_TYPE_98713) { 834 phy_reg = CSR_READ_4(sc, DC_NETCFG); 835 CSR_WRITE_4(sc, DC_NETCFG, phy_reg & ~DC_NETCFG_PORTSEL); 836 } 837 mii_bitbang_writereg(dev, &dc_mii_bitbang_ops, phy, reg, data); 838 if (sc->dc_type == DC_TYPE_98713) 839 CSR_WRITE_4(sc, DC_NETCFG, phy_reg); 840 841 return (0); 842 } 843 844 static void 845 dc_miibus_statchg(device_t dev) 846 { 847 struct dc_softc *sc; 848 struct ifnet *ifp; 849 struct mii_data *mii; 850 struct ifmedia *ifm; 851 852 sc = device_get_softc(dev); 853 854 mii = device_get_softc(sc->dc_miibus); 855 ifp = sc->dc_ifp; 856 if (mii == NULL || ifp == NULL || 857 (ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) 858 return; 859 860 ifm = &mii->mii_media; 861 if (DC_IS_DAVICOM(sc) && IFM_SUBTYPE(ifm->ifm_media) == IFM_HPNA_1) { 862 dc_setcfg(sc, ifm->ifm_media); 863 return; 864 } else if (!DC_IS_ADMTEK(sc)) 865 dc_setcfg(sc, mii->mii_media_active); 866 867 sc->dc_link = 0; 868 if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) == 869 (IFM_ACTIVE | IFM_AVALID)) { 870 switch (IFM_SUBTYPE(mii->mii_media_active)) { 871 case IFM_10_T: 872 case IFM_100_TX: 873 sc->dc_link = 1; 874 break; 875 } 876 } 877 } 878 879 /* 880 * Special support for DM9102A cards with HomePNA PHYs. Note: 881 * with the Davicom DM9102A/DM9801 eval board that I have, it seems 882 * to be impossible to talk to the management interface of the DM9801 883 * PHY (its MDIO pin is not connected to anything). Consequently, 884 * the driver has to just 'know' about the additional mode and deal 885 * with it itself. *sigh* 886 */ 887 static void 888 dc_miibus_mediainit(device_t dev) 889 { 890 struct dc_softc *sc; 891 struct mii_data *mii; 892 struct ifmedia *ifm; 893 int rev; 894 895 rev = pci_get_revid(dev); 896 897 sc = device_get_softc(dev); 898 mii = device_get_softc(sc->dc_miibus); 899 ifm = &mii->mii_media; 900 901 if (DC_IS_DAVICOM(sc) && rev >= DC_REVISION_DM9102A) 902 ifmedia_add(ifm, IFM_ETHER | IFM_HPNA_1, 0, NULL); 903 } 904 905 #define DC_BITS_512 9 906 #define DC_BITS_128 7 907 #define DC_BITS_64 6 908 909 static uint32_t 910 dc_mchash_le(struct dc_softc *sc, const uint8_t *addr) 911 { 912 uint32_t crc; 913 914 /* Compute CRC for the address value. */ 915 crc = ether_crc32_le(addr, ETHER_ADDR_LEN); 916 917 /* 918 * The hash table on the PNIC II and the MX98715AEC-C/D/E 919 * chips is only 128 bits wide. 920 */ 921 if (sc->dc_flags & DC_128BIT_HASH) 922 return (crc & ((1 << DC_BITS_128) - 1)); 923 924 /* The hash table on the MX98715BEC is only 64 bits wide. */ 925 if (sc->dc_flags & DC_64BIT_HASH) 926 return (crc & ((1 << DC_BITS_64) - 1)); 927 928 /* Xircom's hash filtering table is different (read: weird) */ 929 /* Xircom uses the LEAST significant bits */ 930 if (DC_IS_XIRCOM(sc)) { 931 if ((crc & 0x180) == 0x180) 932 return ((crc & 0x0F) + (crc & 0x70) * 3 + (14 << 4)); 933 else 934 return ((crc & 0x1F) + ((crc >> 1) & 0xF0) * 3 + 935 (12 << 4)); 936 } 937 938 return (crc & ((1 << DC_BITS_512) - 1)); 939 } 940 941 /* 942 * Calculate CRC of a multicast group address, return the lower 6 bits. 943 */ 944 static uint32_t 945 dc_mchash_be(const uint8_t *addr) 946 { 947 uint32_t crc; 948 949 /* Compute CRC for the address value. */ 950 crc = ether_crc32_be(addr, ETHER_ADDR_LEN); 951 952 /* Return the filter bit position. */ 953 return ((crc >> 26) & 0x0000003F); 954 } 955 956 /* 957 * 21143-style RX filter setup routine. Filter programming is done by 958 * downloading a special setup frame into the TX engine. 21143, Macronix, 959 * PNIC, PNIC II and Davicom chips are programmed this way. 960 * 961 * We always program the chip using 'hash perfect' mode, i.e. one perfect 962 * address (our node address) and a 512-bit hash filter for multicast 963 * frames. We also sneak the broadcast address into the hash filter since 964 * we need that too. 965 */ 966 static void 967 dc_setfilt_21143(struct dc_softc *sc) 968 { 969 uint16_t eaddr[(ETHER_ADDR_LEN+1)/2]; 970 struct dc_desc *sframe; 971 uint32_t h, *sp; 972 struct ifmultiaddr *ifma; 973 struct ifnet *ifp; 974 int i; 975 976 ifp = sc->dc_ifp; 977 978 i = sc->dc_cdata.dc_tx_prod; 979 DC_INC(sc->dc_cdata.dc_tx_prod, DC_TX_LIST_CNT); 980 sc->dc_cdata.dc_tx_cnt++; 981 sframe = &sc->dc_ldata.dc_tx_list[i]; 982 sp = sc->dc_cdata.dc_sbuf; 983 bzero(sp, DC_SFRAME_LEN); 984 985 sframe->dc_data = htole32(DC_ADDR_LO(sc->dc_saddr)); 986 sframe->dc_ctl = htole32(DC_SFRAME_LEN | DC_TXCTL_SETUP | 987 DC_TXCTL_TLINK | DC_FILTER_HASHPERF | DC_TXCTL_FINT); 988 989 sc->dc_cdata.dc_tx_chain[i] = (struct mbuf *)sc->dc_cdata.dc_sbuf; 990 991 /* If we want promiscuous mode, set the allframes bit. */ 992 if (ifp->if_flags & IFF_PROMISC) 993 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC); 994 else 995 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC); 996 997 if (ifp->if_flags & IFF_ALLMULTI) 998 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI); 999 else 1000 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI); 1001 1002 if_maddr_rlock(ifp); 1003 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 1004 if (ifma->ifma_addr->sa_family != AF_LINK) 1005 continue; 1006 h = dc_mchash_le(sc, 1007 LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 1008 sp[h >> 4] |= htole32(1 << (h & 0xF)); 1009 } 1010 if_maddr_runlock(ifp); 1011 1012 if (ifp->if_flags & IFF_BROADCAST) { 1013 h = dc_mchash_le(sc, ifp->if_broadcastaddr); 1014 sp[h >> 4] |= htole32(1 << (h & 0xF)); 1015 } 1016 1017 /* Set our MAC address. */ 1018 bcopy(IF_LLADDR(sc->dc_ifp), eaddr, ETHER_ADDR_LEN); 1019 sp[39] = DC_SP_MAC(eaddr[0]); 1020 sp[40] = DC_SP_MAC(eaddr[1]); 1021 sp[41] = DC_SP_MAC(eaddr[2]); 1022 1023 sframe->dc_status = htole32(DC_TXSTAT_OWN); 1024 bus_dmamap_sync(sc->dc_tx_ltag, sc->dc_tx_lmap, BUS_DMASYNC_PREREAD | 1025 BUS_DMASYNC_PREWRITE); 1026 bus_dmamap_sync(sc->dc_stag, sc->dc_smap, BUS_DMASYNC_PREWRITE); 1027 CSR_WRITE_4(sc, DC_TXSTART, 0xFFFFFFFF); 1028 1029 /* 1030 * The PNIC takes an exceedingly long time to process its 1031 * setup frame; wait 10ms after posting the setup frame 1032 * before proceeding, just so it has time to swallow its 1033 * medicine. 1034 */ 1035 DELAY(10000); 1036 1037 sc->dc_wdog_timer = 5; 1038 } 1039 1040 static void 1041 dc_setfilt_admtek(struct dc_softc *sc) 1042 { 1043 uint8_t eaddr[ETHER_ADDR_LEN]; 1044 struct ifnet *ifp; 1045 struct ifmultiaddr *ifma; 1046 int h = 0; 1047 uint32_t hashes[2] = { 0, 0 }; 1048 1049 ifp = sc->dc_ifp; 1050 1051 /* Init our MAC address. */ 1052 bcopy(IF_LLADDR(sc->dc_ifp), eaddr, ETHER_ADDR_LEN); 1053 CSR_WRITE_4(sc, DC_AL_PAR0, eaddr[3] << 24 | eaddr[2] << 16 | 1054 eaddr[1] << 8 | eaddr[0]); 1055 CSR_WRITE_4(sc, DC_AL_PAR1, eaddr[5] << 8 | eaddr[4]); 1056 1057 /* If we want promiscuous mode, set the allframes bit. */ 1058 if (ifp->if_flags & IFF_PROMISC) 1059 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC); 1060 else 1061 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC); 1062 1063 if (ifp->if_flags & IFF_ALLMULTI) 1064 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI); 1065 else 1066 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI); 1067 1068 /* First, zot all the existing hash bits. */ 1069 CSR_WRITE_4(sc, DC_AL_MAR0, 0); 1070 CSR_WRITE_4(sc, DC_AL_MAR1, 0); 1071 1072 /* 1073 * If we're already in promisc or allmulti mode, we 1074 * don't have to bother programming the multicast filter. 1075 */ 1076 if (ifp->if_flags & (IFF_PROMISC | IFF_ALLMULTI)) 1077 return; 1078 1079 /* Now program new ones. */ 1080 if_maddr_rlock(ifp); 1081 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 1082 if (ifma->ifma_addr->sa_family != AF_LINK) 1083 continue; 1084 if (DC_IS_CENTAUR(sc)) 1085 h = dc_mchash_le(sc, 1086 LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 1087 else 1088 h = dc_mchash_be( 1089 LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 1090 if (h < 32) 1091 hashes[0] |= (1 << h); 1092 else 1093 hashes[1] |= (1 << (h - 32)); 1094 } 1095 if_maddr_runlock(ifp); 1096 1097 CSR_WRITE_4(sc, DC_AL_MAR0, hashes[0]); 1098 CSR_WRITE_4(sc, DC_AL_MAR1, hashes[1]); 1099 } 1100 1101 static void 1102 dc_setfilt_asix(struct dc_softc *sc) 1103 { 1104 uint32_t eaddr[(ETHER_ADDR_LEN+3)/4]; 1105 struct ifnet *ifp; 1106 struct ifmultiaddr *ifma; 1107 int h = 0; 1108 uint32_t hashes[2] = { 0, 0 }; 1109 1110 ifp = sc->dc_ifp; 1111 1112 /* Init our MAC address. */ 1113 bcopy(IF_LLADDR(sc->dc_ifp), eaddr, ETHER_ADDR_LEN); 1114 CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_PAR0); 1115 CSR_WRITE_4(sc, DC_AX_FILTDATA, eaddr[0]); 1116 CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_PAR1); 1117 CSR_WRITE_4(sc, DC_AX_FILTDATA, eaddr[1]); 1118 1119 /* If we want promiscuous mode, set the allframes bit. */ 1120 if (ifp->if_flags & IFF_PROMISC) 1121 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC); 1122 else 1123 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC); 1124 1125 if (ifp->if_flags & IFF_ALLMULTI) 1126 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI); 1127 else 1128 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI); 1129 1130 /* 1131 * The ASIX chip has a special bit to enable reception 1132 * of broadcast frames. 1133 */ 1134 if (ifp->if_flags & IFF_BROADCAST) 1135 DC_SETBIT(sc, DC_NETCFG, DC_AX_NETCFG_RX_BROAD); 1136 else 1137 DC_CLRBIT(sc, DC_NETCFG, DC_AX_NETCFG_RX_BROAD); 1138 1139 /* first, zot all the existing hash bits */ 1140 CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_MAR0); 1141 CSR_WRITE_4(sc, DC_AX_FILTDATA, 0); 1142 CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_MAR1); 1143 CSR_WRITE_4(sc, DC_AX_FILTDATA, 0); 1144 1145 /* 1146 * If we're already in promisc or allmulti mode, we 1147 * don't have to bother programming the multicast filter. 1148 */ 1149 if (ifp->if_flags & (IFF_PROMISC | IFF_ALLMULTI)) 1150 return; 1151 1152 /* now program new ones */ 1153 if_maddr_rlock(ifp); 1154 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 1155 if (ifma->ifma_addr->sa_family != AF_LINK) 1156 continue; 1157 h = dc_mchash_be(LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 1158 if (h < 32) 1159 hashes[0] |= (1 << h); 1160 else 1161 hashes[1] |= (1 << (h - 32)); 1162 } 1163 if_maddr_runlock(ifp); 1164 1165 CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_MAR0); 1166 CSR_WRITE_4(sc, DC_AX_FILTDATA, hashes[0]); 1167 CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_MAR1); 1168 CSR_WRITE_4(sc, DC_AX_FILTDATA, hashes[1]); 1169 } 1170 1171 static void 1172 dc_setfilt_uli(struct dc_softc *sc) 1173 { 1174 uint8_t eaddr[ETHER_ADDR_LEN]; 1175 struct ifnet *ifp; 1176 struct ifmultiaddr *ifma; 1177 struct dc_desc *sframe; 1178 uint32_t filter, *sp; 1179 uint8_t *ma; 1180 int i, mcnt; 1181 1182 ifp = sc->dc_ifp; 1183 1184 i = sc->dc_cdata.dc_tx_prod; 1185 DC_INC(sc->dc_cdata.dc_tx_prod, DC_TX_LIST_CNT); 1186 sc->dc_cdata.dc_tx_cnt++; 1187 sframe = &sc->dc_ldata.dc_tx_list[i]; 1188 sp = sc->dc_cdata.dc_sbuf; 1189 bzero(sp, DC_SFRAME_LEN); 1190 1191 sframe->dc_data = htole32(DC_ADDR_LO(sc->dc_saddr)); 1192 sframe->dc_ctl = htole32(DC_SFRAME_LEN | DC_TXCTL_SETUP | 1193 DC_TXCTL_TLINK | DC_FILTER_PERFECT | DC_TXCTL_FINT); 1194 1195 sc->dc_cdata.dc_tx_chain[i] = (struct mbuf *)sc->dc_cdata.dc_sbuf; 1196 1197 /* Set station address. */ 1198 bcopy(IF_LLADDR(sc->dc_ifp), eaddr, ETHER_ADDR_LEN); 1199 *sp++ = DC_SP_MAC(eaddr[1] << 8 | eaddr[0]); 1200 *sp++ = DC_SP_MAC(eaddr[3] << 8 | eaddr[2]); 1201 *sp++ = DC_SP_MAC(eaddr[5] << 8 | eaddr[4]); 1202 1203 /* Set broadcast address. */ 1204 *sp++ = DC_SP_MAC(0xFFFF); 1205 *sp++ = DC_SP_MAC(0xFFFF); 1206 *sp++ = DC_SP_MAC(0xFFFF); 1207 1208 /* Extract current filter configuration. */ 1209 filter = CSR_READ_4(sc, DC_NETCFG); 1210 filter &= ~(DC_NETCFG_RX_PROMISC | DC_NETCFG_RX_ALLMULTI); 1211 1212 /* Now build perfect filters. */ 1213 mcnt = 0; 1214 if_maddr_rlock(ifp); 1215 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 1216 if (ifma->ifma_addr->sa_family != AF_LINK) 1217 continue; 1218 if (mcnt >= DC_ULI_FILTER_NPERF) { 1219 filter |= DC_NETCFG_RX_ALLMULTI; 1220 break; 1221 } 1222 ma = LLADDR((struct sockaddr_dl *)ifma->ifma_addr); 1223 *sp++ = DC_SP_MAC(ma[1] << 8 | ma[0]); 1224 *sp++ = DC_SP_MAC(ma[3] << 8 | ma[2]); 1225 *sp++ = DC_SP_MAC(ma[5] << 8 | ma[4]); 1226 mcnt++; 1227 } 1228 if_maddr_runlock(ifp); 1229 1230 for (; mcnt < DC_ULI_FILTER_NPERF; mcnt++) { 1231 *sp++ = DC_SP_MAC(0xFFFF); 1232 *sp++ = DC_SP_MAC(0xFFFF); 1233 *sp++ = DC_SP_MAC(0xFFFF); 1234 } 1235 1236 if (filter & (DC_NETCFG_TX_ON | DC_NETCFG_RX_ON)) 1237 CSR_WRITE_4(sc, DC_NETCFG, 1238 filter & ~(DC_NETCFG_TX_ON | DC_NETCFG_RX_ON)); 1239 if (ifp->if_flags & IFF_PROMISC) 1240 filter |= DC_NETCFG_RX_PROMISC | DC_NETCFG_RX_ALLMULTI; 1241 if (ifp->if_flags & IFF_ALLMULTI) 1242 filter |= DC_NETCFG_RX_ALLMULTI; 1243 CSR_WRITE_4(sc, DC_NETCFG, 1244 filter & ~(DC_NETCFG_TX_ON | DC_NETCFG_RX_ON)); 1245 if (filter & (DC_NETCFG_TX_ON | DC_NETCFG_RX_ON)) 1246 CSR_WRITE_4(sc, DC_NETCFG, filter); 1247 1248 sframe->dc_status = htole32(DC_TXSTAT_OWN); 1249 bus_dmamap_sync(sc->dc_tx_ltag, sc->dc_tx_lmap, BUS_DMASYNC_PREREAD | 1250 BUS_DMASYNC_PREWRITE); 1251 bus_dmamap_sync(sc->dc_stag, sc->dc_smap, BUS_DMASYNC_PREWRITE); 1252 CSR_WRITE_4(sc, DC_TXSTART, 0xFFFFFFFF); 1253 1254 /* 1255 * Wait some time... 1256 */ 1257 DELAY(1000); 1258 1259 sc->dc_wdog_timer = 5; 1260 } 1261 1262 static void 1263 dc_setfilt_xircom(struct dc_softc *sc) 1264 { 1265 uint16_t eaddr[(ETHER_ADDR_LEN+1)/2]; 1266 struct ifnet *ifp; 1267 struct ifmultiaddr *ifma; 1268 struct dc_desc *sframe; 1269 uint32_t h, *sp; 1270 int i; 1271 1272 ifp = sc->dc_ifp; 1273 DC_CLRBIT(sc, DC_NETCFG, (DC_NETCFG_TX_ON | DC_NETCFG_RX_ON)); 1274 1275 i = sc->dc_cdata.dc_tx_prod; 1276 DC_INC(sc->dc_cdata.dc_tx_prod, DC_TX_LIST_CNT); 1277 sc->dc_cdata.dc_tx_cnt++; 1278 sframe = &sc->dc_ldata.dc_tx_list[i]; 1279 sp = sc->dc_cdata.dc_sbuf; 1280 bzero(sp, DC_SFRAME_LEN); 1281 1282 sframe->dc_data = htole32(DC_ADDR_LO(sc->dc_saddr)); 1283 sframe->dc_ctl = htole32(DC_SFRAME_LEN | DC_TXCTL_SETUP | 1284 DC_TXCTL_TLINK | DC_FILTER_HASHPERF | DC_TXCTL_FINT); 1285 1286 sc->dc_cdata.dc_tx_chain[i] = (struct mbuf *)sc->dc_cdata.dc_sbuf; 1287 1288 /* If we want promiscuous mode, set the allframes bit. */ 1289 if (ifp->if_flags & IFF_PROMISC) 1290 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC); 1291 else 1292 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC); 1293 1294 if (ifp->if_flags & IFF_ALLMULTI) 1295 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI); 1296 else 1297 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI); 1298 1299 if_maddr_rlock(ifp); 1300 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 1301 if (ifma->ifma_addr->sa_family != AF_LINK) 1302 continue; 1303 h = dc_mchash_le(sc, 1304 LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 1305 sp[h >> 4] |= htole32(1 << (h & 0xF)); 1306 } 1307 if_maddr_runlock(ifp); 1308 1309 if (ifp->if_flags & IFF_BROADCAST) { 1310 h = dc_mchash_le(sc, ifp->if_broadcastaddr); 1311 sp[h >> 4] |= htole32(1 << (h & 0xF)); 1312 } 1313 1314 /* Set our MAC address. */ 1315 bcopy(IF_LLADDR(sc->dc_ifp), eaddr, ETHER_ADDR_LEN); 1316 sp[0] = DC_SP_MAC(eaddr[0]); 1317 sp[1] = DC_SP_MAC(eaddr[1]); 1318 sp[2] = DC_SP_MAC(eaddr[2]); 1319 1320 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_TX_ON); 1321 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_ON); 1322 sframe->dc_status = htole32(DC_TXSTAT_OWN); 1323 bus_dmamap_sync(sc->dc_tx_ltag, sc->dc_tx_lmap, BUS_DMASYNC_PREREAD | 1324 BUS_DMASYNC_PREWRITE); 1325 bus_dmamap_sync(sc->dc_stag, sc->dc_smap, BUS_DMASYNC_PREWRITE); 1326 CSR_WRITE_4(sc, DC_TXSTART, 0xFFFFFFFF); 1327 1328 /* 1329 * Wait some time... 1330 */ 1331 DELAY(1000); 1332 1333 sc->dc_wdog_timer = 5; 1334 } 1335 1336 static void 1337 dc_setfilt(struct dc_softc *sc) 1338 { 1339 1340 if (DC_IS_INTEL(sc) || DC_IS_MACRONIX(sc) || DC_IS_PNIC(sc) || 1341 DC_IS_PNICII(sc) || DC_IS_DAVICOM(sc) || DC_IS_CONEXANT(sc)) 1342 dc_setfilt_21143(sc); 1343 1344 if (DC_IS_ASIX(sc)) 1345 dc_setfilt_asix(sc); 1346 1347 if (DC_IS_ADMTEK(sc)) 1348 dc_setfilt_admtek(sc); 1349 1350 if (DC_IS_ULI(sc)) 1351 dc_setfilt_uli(sc); 1352 1353 if (DC_IS_XIRCOM(sc)) 1354 dc_setfilt_xircom(sc); 1355 } 1356 1357 static void 1358 dc_netcfg_wait(struct dc_softc *sc) 1359 { 1360 uint32_t isr; 1361 int i; 1362 1363 for (i = 0; i < DC_TIMEOUT; i++) { 1364 isr = CSR_READ_4(sc, DC_ISR); 1365 if (isr & DC_ISR_TX_IDLE && 1366 ((isr & DC_ISR_RX_STATE) == DC_RXSTATE_STOPPED || 1367 (isr & DC_ISR_RX_STATE) == DC_RXSTATE_WAIT)) 1368 break; 1369 DELAY(10); 1370 } 1371 if (i == DC_TIMEOUT && bus_child_present(sc->dc_dev)) { 1372 if (!(isr & DC_ISR_TX_IDLE) && !DC_IS_ASIX(sc)) 1373 device_printf(sc->dc_dev, 1374 "%s: failed to force tx to idle state\n", __func__); 1375 if (!((isr & DC_ISR_RX_STATE) == DC_RXSTATE_STOPPED || 1376 (isr & DC_ISR_RX_STATE) == DC_RXSTATE_WAIT) && 1377 !DC_HAS_BROKEN_RXSTATE(sc)) 1378 device_printf(sc->dc_dev, 1379 "%s: failed to force rx to idle state\n", __func__); 1380 } 1381 } 1382 1383 /* 1384 * In order to fiddle with the 'full-duplex' and '100Mbps' bits in 1385 * the netconfig register, we first have to put the transmit and/or 1386 * receive logic in the idle state. 1387 */ 1388 static void 1389 dc_setcfg(struct dc_softc *sc, int media) 1390 { 1391 int restart = 0, watchdogreg; 1392 1393 if (IFM_SUBTYPE(media) == IFM_NONE) 1394 return; 1395 1396 if (CSR_READ_4(sc, DC_NETCFG) & (DC_NETCFG_TX_ON | DC_NETCFG_RX_ON)) { 1397 restart = 1; 1398 DC_CLRBIT(sc, DC_NETCFG, (DC_NETCFG_TX_ON | DC_NETCFG_RX_ON)); 1399 dc_netcfg_wait(sc); 1400 } 1401 1402 if (IFM_SUBTYPE(media) == IFM_100_TX) { 1403 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_SPEEDSEL); 1404 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_HEARTBEAT); 1405 if (sc->dc_pmode == DC_PMODE_MII) { 1406 if (DC_IS_INTEL(sc)) { 1407 /* There's a write enable bit here that reads as 1. */ 1408 watchdogreg = CSR_READ_4(sc, DC_WATCHDOG); 1409 watchdogreg &= ~DC_WDOG_CTLWREN; 1410 watchdogreg |= DC_WDOG_JABBERDIS; 1411 CSR_WRITE_4(sc, DC_WATCHDOG, watchdogreg); 1412 } else { 1413 DC_SETBIT(sc, DC_WATCHDOG, DC_WDOG_JABBERDIS); 1414 } 1415 DC_CLRBIT(sc, DC_NETCFG, (DC_NETCFG_PCS | 1416 DC_NETCFG_PORTSEL | DC_NETCFG_SCRAMBLER)); 1417 if (sc->dc_type == DC_TYPE_98713) 1418 DC_SETBIT(sc, DC_NETCFG, (DC_NETCFG_PCS | 1419 DC_NETCFG_SCRAMBLER)); 1420 if (!DC_IS_DAVICOM(sc)) 1421 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL); 1422 DC_CLRBIT(sc, DC_10BTCTRL, 0xFFFF); 1423 } else { 1424 if (DC_IS_PNIC(sc)) { 1425 DC_PN_GPIO_SETBIT(sc, DC_PN_GPIO_SPEEDSEL); 1426 DC_PN_GPIO_SETBIT(sc, DC_PN_GPIO_100TX_LOOP); 1427 DC_SETBIT(sc, DC_PN_NWAY, DC_PN_NWAY_SPEEDSEL); 1428 } 1429 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL); 1430 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PCS); 1431 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_SCRAMBLER); 1432 } 1433 } 1434 1435 if (IFM_SUBTYPE(media) == IFM_10_T) { 1436 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_SPEEDSEL); 1437 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_HEARTBEAT); 1438 if (sc->dc_pmode == DC_PMODE_MII) { 1439 /* There's a write enable bit here that reads as 1. */ 1440 if (DC_IS_INTEL(sc)) { 1441 watchdogreg = CSR_READ_4(sc, DC_WATCHDOG); 1442 watchdogreg &= ~DC_WDOG_CTLWREN; 1443 watchdogreg |= DC_WDOG_JABBERDIS; 1444 CSR_WRITE_4(sc, DC_WATCHDOG, watchdogreg); 1445 } else { 1446 DC_SETBIT(sc, DC_WATCHDOG, DC_WDOG_JABBERDIS); 1447 } 1448 DC_CLRBIT(sc, DC_NETCFG, (DC_NETCFG_PCS | 1449 DC_NETCFG_PORTSEL | DC_NETCFG_SCRAMBLER)); 1450 if (sc->dc_type == DC_TYPE_98713) 1451 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PCS); 1452 if (!DC_IS_DAVICOM(sc)) 1453 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL); 1454 DC_CLRBIT(sc, DC_10BTCTRL, 0xFFFF); 1455 } else { 1456 if (DC_IS_PNIC(sc)) { 1457 DC_PN_GPIO_CLRBIT(sc, DC_PN_GPIO_SPEEDSEL); 1458 DC_PN_GPIO_SETBIT(sc, DC_PN_GPIO_100TX_LOOP); 1459 DC_CLRBIT(sc, DC_PN_NWAY, DC_PN_NWAY_SPEEDSEL); 1460 } 1461 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL); 1462 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_PCS); 1463 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_SCRAMBLER); 1464 if (DC_IS_INTEL(sc)) { 1465 DC_CLRBIT(sc, DC_SIARESET, DC_SIA_RESET); 1466 DC_CLRBIT(sc, DC_10BTCTRL, 0xFFFF); 1467 if ((media & IFM_GMASK) == IFM_FDX) 1468 DC_SETBIT(sc, DC_10BTCTRL, 0x7F3D); 1469 else 1470 DC_SETBIT(sc, DC_10BTCTRL, 0x7F3F); 1471 DC_SETBIT(sc, DC_SIARESET, DC_SIA_RESET); 1472 DC_CLRBIT(sc, DC_10BTCTRL, 1473 DC_TCTL_AUTONEGENBL); 1474 DELAY(20000); 1475 } 1476 } 1477 } 1478 1479 /* 1480 * If this is a Davicom DM9102A card with a DM9801 HomePNA 1481 * PHY and we want HomePNA mode, set the portsel bit to turn 1482 * on the external MII port. 1483 */ 1484 if (DC_IS_DAVICOM(sc)) { 1485 if (IFM_SUBTYPE(media) == IFM_HPNA_1) { 1486 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL); 1487 sc->dc_link = 1; 1488 } else { 1489 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL); 1490 } 1491 } 1492 1493 if ((media & IFM_GMASK) == IFM_FDX) { 1494 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_FULLDUPLEX); 1495 if (sc->dc_pmode == DC_PMODE_SYM && DC_IS_PNIC(sc)) 1496 DC_SETBIT(sc, DC_PN_NWAY, DC_PN_NWAY_DUPLEX); 1497 } else { 1498 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_FULLDUPLEX); 1499 if (sc->dc_pmode == DC_PMODE_SYM && DC_IS_PNIC(sc)) 1500 DC_CLRBIT(sc, DC_PN_NWAY, DC_PN_NWAY_DUPLEX); 1501 } 1502 1503 if (restart) 1504 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_TX_ON | DC_NETCFG_RX_ON); 1505 } 1506 1507 static void 1508 dc_reset(struct dc_softc *sc) 1509 { 1510 int i; 1511 1512 DC_SETBIT(sc, DC_BUSCTL, DC_BUSCTL_RESET); 1513 1514 for (i = 0; i < DC_TIMEOUT; i++) { 1515 DELAY(10); 1516 if (!(CSR_READ_4(sc, DC_BUSCTL) & DC_BUSCTL_RESET)) 1517 break; 1518 } 1519 1520 if (DC_IS_ASIX(sc) || DC_IS_ADMTEK(sc) || DC_IS_CONEXANT(sc) || 1521 DC_IS_XIRCOM(sc) || DC_IS_INTEL(sc) || DC_IS_ULI(sc)) { 1522 DELAY(10000); 1523 DC_CLRBIT(sc, DC_BUSCTL, DC_BUSCTL_RESET); 1524 i = 0; 1525 } 1526 1527 if (i == DC_TIMEOUT) 1528 device_printf(sc->dc_dev, "reset never completed!\n"); 1529 1530 /* Wait a little while for the chip to get its brains in order. */ 1531 DELAY(1000); 1532 1533 CSR_WRITE_4(sc, DC_IMR, 0x00000000); 1534 CSR_WRITE_4(sc, DC_BUSCTL, 0x00000000); 1535 CSR_WRITE_4(sc, DC_NETCFG, 0x00000000); 1536 1537 /* 1538 * Bring the SIA out of reset. In some cases, it looks 1539 * like failing to unreset the SIA soon enough gets it 1540 * into a state where it will never come out of reset 1541 * until we reset the whole chip again. 1542 */ 1543 if (DC_IS_INTEL(sc)) { 1544 DC_SETBIT(sc, DC_SIARESET, DC_SIA_RESET); 1545 CSR_WRITE_4(sc, DC_10BTCTRL, 0xFFFFFFFF); 1546 CSR_WRITE_4(sc, DC_WATCHDOG, 0); 1547 } 1548 } 1549 1550 static const struct dc_type * 1551 dc_devtype(device_t dev) 1552 { 1553 const struct dc_type *t; 1554 uint32_t devid; 1555 uint8_t rev; 1556 1557 t = dc_devs; 1558 devid = pci_get_devid(dev); 1559 rev = pci_get_revid(dev); 1560 1561 while (t->dc_name != NULL) { 1562 if (devid == t->dc_devid && rev >= t->dc_minrev) 1563 return (t); 1564 t++; 1565 } 1566 1567 return (NULL); 1568 } 1569 1570 /* 1571 * Probe for a 21143 or clone chip. Check the PCI vendor and device 1572 * IDs against our list and return a device name if we find a match. 1573 * We do a little bit of extra work to identify the exact type of 1574 * chip. The MX98713 and MX98713A have the same PCI vendor/device ID, 1575 * but different revision IDs. The same is true for 98715/98715A 1576 * chips and the 98725, as well as the ASIX and ADMtek chips. In some 1577 * cases, the exact chip revision affects driver behavior. 1578 */ 1579 static int 1580 dc_probe(device_t dev) 1581 { 1582 const struct dc_type *t; 1583 1584 t = dc_devtype(dev); 1585 1586 if (t != NULL) { 1587 device_set_desc(dev, t->dc_name); 1588 return (BUS_PROBE_DEFAULT); 1589 } 1590 1591 return (ENXIO); 1592 } 1593 1594 static void 1595 dc_apply_fixup(struct dc_softc *sc, int media) 1596 { 1597 struct dc_mediainfo *m; 1598 uint8_t *p; 1599 int i; 1600 uint32_t reg; 1601 1602 m = sc->dc_mi; 1603 1604 while (m != NULL) { 1605 if (m->dc_media == media) 1606 break; 1607 m = m->dc_next; 1608 } 1609 1610 if (m == NULL) 1611 return; 1612 1613 for (i = 0, p = m->dc_reset_ptr; i < m->dc_reset_len; i++, p += 2) { 1614 reg = (p[0] | (p[1] << 8)) << 16; 1615 CSR_WRITE_4(sc, DC_WATCHDOG, reg); 1616 } 1617 1618 for (i = 0, p = m->dc_gp_ptr; i < m->dc_gp_len; i++, p += 2) { 1619 reg = (p[0] | (p[1] << 8)) << 16; 1620 CSR_WRITE_4(sc, DC_WATCHDOG, reg); 1621 } 1622 } 1623 1624 static int 1625 dc_decode_leaf_sia(struct dc_softc *sc, struct dc_eblock_sia *l) 1626 { 1627 struct dc_mediainfo *m; 1628 1629 m = malloc(sizeof(struct dc_mediainfo), M_DEVBUF, M_NOWAIT | M_ZERO); 1630 if (m == NULL) { 1631 device_printf(sc->dc_dev, "Could not allocate mediainfo\n"); 1632 return (ENOMEM); 1633 } 1634 switch (l->dc_sia_code & ~DC_SIA_CODE_EXT) { 1635 case DC_SIA_CODE_10BT: 1636 m->dc_media = IFM_10_T; 1637 break; 1638 case DC_SIA_CODE_10BT_FDX: 1639 m->dc_media = IFM_10_T | IFM_FDX; 1640 break; 1641 case DC_SIA_CODE_10B2: 1642 m->dc_media = IFM_10_2; 1643 break; 1644 case DC_SIA_CODE_10B5: 1645 m->dc_media = IFM_10_5; 1646 break; 1647 default: 1648 break; 1649 } 1650 1651 /* 1652 * We need to ignore CSR13, CSR14, CSR15 for SIA mode. 1653 * Things apparently already work for cards that do 1654 * supply Media Specific Data. 1655 */ 1656 if (l->dc_sia_code & DC_SIA_CODE_EXT) { 1657 m->dc_gp_len = 2; 1658 m->dc_gp_ptr = 1659 (uint8_t *)&l->dc_un.dc_sia_ext.dc_sia_gpio_ctl; 1660 } else { 1661 m->dc_gp_len = 2; 1662 m->dc_gp_ptr = 1663 (uint8_t *)&l->dc_un.dc_sia_noext.dc_sia_gpio_ctl; 1664 } 1665 1666 m->dc_next = sc->dc_mi; 1667 sc->dc_mi = m; 1668 1669 sc->dc_pmode = DC_PMODE_SIA; 1670 return (0); 1671 } 1672 1673 static int 1674 dc_decode_leaf_sym(struct dc_softc *sc, struct dc_eblock_sym *l) 1675 { 1676 struct dc_mediainfo *m; 1677 1678 m = malloc(sizeof(struct dc_mediainfo), M_DEVBUF, M_NOWAIT | M_ZERO); 1679 if (m == NULL) { 1680 device_printf(sc->dc_dev, "Could not allocate mediainfo\n"); 1681 return (ENOMEM); 1682 } 1683 if (l->dc_sym_code == DC_SYM_CODE_100BT) 1684 m->dc_media = IFM_100_TX; 1685 1686 if (l->dc_sym_code == DC_SYM_CODE_100BT_FDX) 1687 m->dc_media = IFM_100_TX | IFM_FDX; 1688 1689 m->dc_gp_len = 2; 1690 m->dc_gp_ptr = (uint8_t *)&l->dc_sym_gpio_ctl; 1691 1692 m->dc_next = sc->dc_mi; 1693 sc->dc_mi = m; 1694 1695 sc->dc_pmode = DC_PMODE_SYM; 1696 return (0); 1697 } 1698 1699 static int 1700 dc_decode_leaf_mii(struct dc_softc *sc, struct dc_eblock_mii *l) 1701 { 1702 struct dc_mediainfo *m; 1703 uint8_t *p; 1704 1705 m = malloc(sizeof(struct dc_mediainfo), M_DEVBUF, M_NOWAIT | M_ZERO); 1706 if (m == NULL) { 1707 device_printf(sc->dc_dev, "Could not allocate mediainfo\n"); 1708 return (ENOMEM); 1709 } 1710 /* We abuse IFM_AUTO to represent MII. */ 1711 m->dc_media = IFM_AUTO; 1712 m->dc_gp_len = l->dc_gpr_len; 1713 1714 p = (uint8_t *)l; 1715 p += sizeof(struct dc_eblock_mii); 1716 m->dc_gp_ptr = p; 1717 p += 2 * l->dc_gpr_len; 1718 m->dc_reset_len = *p; 1719 p++; 1720 m->dc_reset_ptr = p; 1721 1722 m->dc_next = sc->dc_mi; 1723 sc->dc_mi = m; 1724 return (0); 1725 } 1726 1727 static int 1728 dc_read_srom(struct dc_softc *sc, int bits) 1729 { 1730 int size; 1731 1732 size = DC_ROM_SIZE(bits); 1733 sc->dc_srom = malloc(size, M_DEVBUF, M_NOWAIT | M_ZERO); 1734 if (sc->dc_srom == NULL) { 1735 device_printf(sc->dc_dev, "Could not allocate SROM buffer\n"); 1736 return (ENOMEM); 1737 } 1738 dc_read_eeprom(sc, (caddr_t)sc->dc_srom, 0, (size / 2), 0); 1739 return (0); 1740 } 1741 1742 static int 1743 dc_parse_21143_srom(struct dc_softc *sc) 1744 { 1745 struct dc_leaf_hdr *lhdr; 1746 struct dc_eblock_hdr *hdr; 1747 int error, have_mii, i, loff; 1748 char *ptr; 1749 1750 have_mii = 0; 1751 loff = sc->dc_srom[27]; 1752 lhdr = (struct dc_leaf_hdr *)&(sc->dc_srom[loff]); 1753 1754 ptr = (char *)lhdr; 1755 ptr += sizeof(struct dc_leaf_hdr) - 1; 1756 /* 1757 * Look if we got a MII media block. 1758 */ 1759 for (i = 0; i < lhdr->dc_mcnt; i++) { 1760 hdr = (struct dc_eblock_hdr *)ptr; 1761 if (hdr->dc_type == DC_EBLOCK_MII) 1762 have_mii++; 1763 1764 ptr += (hdr->dc_len & 0x7F); 1765 ptr++; 1766 } 1767 1768 /* 1769 * Do the same thing again. Only use SIA and SYM media 1770 * blocks if no MII media block is available. 1771 */ 1772 ptr = (char *)lhdr; 1773 ptr += sizeof(struct dc_leaf_hdr) - 1; 1774 error = 0; 1775 for (i = 0; i < lhdr->dc_mcnt; i++) { 1776 hdr = (struct dc_eblock_hdr *)ptr; 1777 switch (hdr->dc_type) { 1778 case DC_EBLOCK_MII: 1779 error = dc_decode_leaf_mii(sc, (struct dc_eblock_mii *)hdr); 1780 break; 1781 case DC_EBLOCK_SIA: 1782 if (! have_mii) 1783 error = dc_decode_leaf_sia(sc, 1784 (struct dc_eblock_sia *)hdr); 1785 break; 1786 case DC_EBLOCK_SYM: 1787 if (! have_mii) 1788 error = dc_decode_leaf_sym(sc, 1789 (struct dc_eblock_sym *)hdr); 1790 break; 1791 default: 1792 /* Don't care. Yet. */ 1793 break; 1794 } 1795 ptr += (hdr->dc_len & 0x7F); 1796 ptr++; 1797 } 1798 return (error); 1799 } 1800 1801 static void 1802 dc_dma_map_addr(void *arg, bus_dma_segment_t *segs, int nseg, int error) 1803 { 1804 bus_addr_t *paddr; 1805 1806 KASSERT(nseg == 1, 1807 ("%s: wrong number of segments (%d)", __func__, nseg)); 1808 paddr = arg; 1809 *paddr = segs->ds_addr; 1810 } 1811 1812 static int 1813 dc_dma_alloc(struct dc_softc *sc) 1814 { 1815 int error, i; 1816 1817 error = bus_dma_tag_create(bus_get_dma_tag(sc->dc_dev), 1, 0, 1818 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL, 1819 BUS_SPACE_MAXSIZE_32BIT, 0, BUS_SPACE_MAXSIZE_32BIT, 0, 1820 NULL, NULL, &sc->dc_ptag); 1821 if (error) { 1822 device_printf(sc->dc_dev, 1823 "failed to allocate parent DMA tag\n"); 1824 goto fail; 1825 } 1826 1827 /* Allocate a busdma tag and DMA safe memory for TX/RX descriptors. */ 1828 error = bus_dma_tag_create(sc->dc_ptag, DC_LIST_ALIGN, 0, 1829 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL, DC_RX_LIST_SZ, 1, 1830 DC_RX_LIST_SZ, 0, NULL, NULL, &sc->dc_rx_ltag); 1831 if (error) { 1832 device_printf(sc->dc_dev, "failed to create RX list DMA tag\n"); 1833 goto fail; 1834 } 1835 1836 error = bus_dma_tag_create(sc->dc_ptag, DC_LIST_ALIGN, 0, 1837 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL, DC_TX_LIST_SZ, 1, 1838 DC_TX_LIST_SZ, 0, NULL, NULL, &sc->dc_tx_ltag); 1839 if (error) { 1840 device_printf(sc->dc_dev, "failed to create TX list DMA tag\n"); 1841 goto fail; 1842 } 1843 1844 /* RX descriptor list. */ 1845 error = bus_dmamem_alloc(sc->dc_rx_ltag, 1846 (void **)&sc->dc_ldata.dc_rx_list, BUS_DMA_NOWAIT | 1847 BUS_DMA_ZERO | BUS_DMA_COHERENT, &sc->dc_rx_lmap); 1848 if (error) { 1849 device_printf(sc->dc_dev, 1850 "failed to allocate DMA'able memory for RX list\n"); 1851 goto fail; 1852 } 1853 error = bus_dmamap_load(sc->dc_rx_ltag, sc->dc_rx_lmap, 1854 sc->dc_ldata.dc_rx_list, DC_RX_LIST_SZ, dc_dma_map_addr, 1855 &sc->dc_ldata.dc_rx_list_paddr, BUS_DMA_NOWAIT); 1856 if (error) { 1857 device_printf(sc->dc_dev, 1858 "failed to load DMA'able memory for RX list\n"); 1859 goto fail; 1860 } 1861 /* TX descriptor list. */ 1862 error = bus_dmamem_alloc(sc->dc_tx_ltag, 1863 (void **)&sc->dc_ldata.dc_tx_list, BUS_DMA_NOWAIT | 1864 BUS_DMA_ZERO | BUS_DMA_COHERENT, &sc->dc_tx_lmap); 1865 if (error) { 1866 device_printf(sc->dc_dev, 1867 "failed to allocate DMA'able memory for TX list\n"); 1868 goto fail; 1869 } 1870 error = bus_dmamap_load(sc->dc_tx_ltag, sc->dc_tx_lmap, 1871 sc->dc_ldata.dc_tx_list, DC_TX_LIST_SZ, dc_dma_map_addr, 1872 &sc->dc_ldata.dc_tx_list_paddr, BUS_DMA_NOWAIT); 1873 if (error) { 1874 device_printf(sc->dc_dev, 1875 "cannot load DMA'able memory for TX list\n"); 1876 goto fail; 1877 } 1878 1879 /* 1880 * Allocate a busdma tag and DMA safe memory for the multicast 1881 * setup frame. 1882 */ 1883 error = bus_dma_tag_create(sc->dc_ptag, DC_LIST_ALIGN, 0, 1884 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL, 1885 DC_SFRAME_LEN + DC_MIN_FRAMELEN, 1, DC_SFRAME_LEN + DC_MIN_FRAMELEN, 1886 0, NULL, NULL, &sc->dc_stag); 1887 if (error) { 1888 device_printf(sc->dc_dev, 1889 "failed to create DMA tag for setup frame\n"); 1890 goto fail; 1891 } 1892 error = bus_dmamem_alloc(sc->dc_stag, (void **)&sc->dc_cdata.dc_sbuf, 1893 BUS_DMA_NOWAIT, &sc->dc_smap); 1894 if (error) { 1895 device_printf(sc->dc_dev, 1896 "failed to allocate DMA'able memory for setup frame\n"); 1897 goto fail; 1898 } 1899 error = bus_dmamap_load(sc->dc_stag, sc->dc_smap, sc->dc_cdata.dc_sbuf, 1900 DC_SFRAME_LEN, dc_dma_map_addr, &sc->dc_saddr, BUS_DMA_NOWAIT); 1901 if (error) { 1902 device_printf(sc->dc_dev, 1903 "cannot load DMA'able memory for setup frame\n"); 1904 goto fail; 1905 } 1906 1907 /* Allocate a busdma tag for RX mbufs. */ 1908 error = bus_dma_tag_create(sc->dc_ptag, DC_RXBUF_ALIGN, 0, 1909 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL, 1910 MCLBYTES, 1, MCLBYTES, 0, NULL, NULL, &sc->dc_rx_mtag); 1911 if (error) { 1912 device_printf(sc->dc_dev, "failed to create RX mbuf tag\n"); 1913 goto fail; 1914 } 1915 1916 /* Allocate a busdma tag for TX mbufs. */ 1917 error = bus_dma_tag_create(sc->dc_ptag, 1, 0, 1918 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL, 1919 MCLBYTES * DC_MAXFRAGS, DC_MAXFRAGS, MCLBYTES, 1920 0, NULL, NULL, &sc->dc_tx_mtag); 1921 if (error) { 1922 device_printf(sc->dc_dev, "failed to create TX mbuf tag\n"); 1923 goto fail; 1924 } 1925 1926 /* Create the TX/RX busdma maps. */ 1927 for (i = 0; i < DC_TX_LIST_CNT; i++) { 1928 error = bus_dmamap_create(sc->dc_tx_mtag, 0, 1929 &sc->dc_cdata.dc_tx_map[i]); 1930 if (error) { 1931 device_printf(sc->dc_dev, 1932 "failed to create TX mbuf dmamap\n"); 1933 goto fail; 1934 } 1935 } 1936 for (i = 0; i < DC_RX_LIST_CNT; i++) { 1937 error = bus_dmamap_create(sc->dc_rx_mtag, 0, 1938 &sc->dc_cdata.dc_rx_map[i]); 1939 if (error) { 1940 device_printf(sc->dc_dev, 1941 "failed to create RX mbuf dmamap\n"); 1942 goto fail; 1943 } 1944 } 1945 error = bus_dmamap_create(sc->dc_rx_mtag, 0, &sc->dc_sparemap); 1946 if (error) { 1947 device_printf(sc->dc_dev, 1948 "failed to create spare RX mbuf dmamap\n"); 1949 goto fail; 1950 } 1951 1952 fail: 1953 return (error); 1954 } 1955 1956 static void 1957 dc_dma_free(struct dc_softc *sc) 1958 { 1959 int i; 1960 1961 /* RX buffers. */ 1962 if (sc->dc_rx_mtag != NULL) { 1963 for (i = 0; i < DC_RX_LIST_CNT; i++) { 1964 if (sc->dc_cdata.dc_rx_map[i] != NULL) 1965 bus_dmamap_destroy(sc->dc_rx_mtag, 1966 sc->dc_cdata.dc_rx_map[i]); 1967 } 1968 if (sc->dc_sparemap != NULL) 1969 bus_dmamap_destroy(sc->dc_rx_mtag, sc->dc_sparemap); 1970 bus_dma_tag_destroy(sc->dc_rx_mtag); 1971 } 1972 1973 /* TX buffers. */ 1974 if (sc->dc_rx_mtag != NULL) { 1975 for (i = 0; i < DC_TX_LIST_CNT; i++) { 1976 if (sc->dc_cdata.dc_tx_map[i] != NULL) 1977 bus_dmamap_destroy(sc->dc_tx_mtag, 1978 sc->dc_cdata.dc_tx_map[i]); 1979 } 1980 bus_dma_tag_destroy(sc->dc_tx_mtag); 1981 } 1982 1983 /* RX descriptor list. */ 1984 if (sc->dc_rx_ltag) { 1985 if (sc->dc_ldata.dc_rx_list_paddr != 0) 1986 bus_dmamap_unload(sc->dc_rx_ltag, sc->dc_rx_lmap); 1987 if (sc->dc_ldata.dc_rx_list != NULL) 1988 bus_dmamem_free(sc->dc_rx_ltag, sc->dc_ldata.dc_rx_list, 1989 sc->dc_rx_lmap); 1990 bus_dma_tag_destroy(sc->dc_rx_ltag); 1991 } 1992 1993 /* TX descriptor list. */ 1994 if (sc->dc_tx_ltag) { 1995 if (sc->dc_ldata.dc_tx_list_paddr != 0) 1996 bus_dmamap_unload(sc->dc_tx_ltag, sc->dc_tx_lmap); 1997 if (sc->dc_ldata.dc_tx_list != NULL) 1998 bus_dmamem_free(sc->dc_tx_ltag, sc->dc_ldata.dc_tx_list, 1999 sc->dc_tx_lmap); 2000 bus_dma_tag_destroy(sc->dc_tx_ltag); 2001 } 2002 2003 /* multicast setup frame. */ 2004 if (sc->dc_stag) { 2005 if (sc->dc_saddr != 0) 2006 bus_dmamap_unload(sc->dc_stag, sc->dc_smap); 2007 if (sc->dc_cdata.dc_sbuf != NULL) 2008 bus_dmamem_free(sc->dc_stag, sc->dc_cdata.dc_sbuf, 2009 sc->dc_smap); 2010 bus_dma_tag_destroy(sc->dc_stag); 2011 } 2012 } 2013 2014 /* 2015 * Attach the interface. Allocate softc structures, do ifmedia 2016 * setup and ethernet/BPF attach. 2017 */ 2018 static int 2019 dc_attach(device_t dev) 2020 { 2021 uint32_t eaddr[(ETHER_ADDR_LEN+3)/4]; 2022 uint32_t command; 2023 struct dc_softc *sc; 2024 struct ifnet *ifp; 2025 struct dc_mediainfo *m; 2026 uint32_t reg, revision; 2027 uint16_t *srom; 2028 int error, mac_offset, n, phy, rid, tmp; 2029 uint8_t *mac; 2030 2031 sc = device_get_softc(dev); 2032 sc->dc_dev = dev; 2033 2034 mtx_init(&sc->dc_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 2035 MTX_DEF); 2036 2037 /* 2038 * Map control/status registers. 2039 */ 2040 pci_enable_busmaster(dev); 2041 2042 rid = DC_RID; 2043 sc->dc_res = bus_alloc_resource_any(dev, DC_RES, &rid, RF_ACTIVE); 2044 2045 if (sc->dc_res == NULL) { 2046 device_printf(dev, "couldn't map ports/memory\n"); 2047 error = ENXIO; 2048 goto fail; 2049 } 2050 2051 sc->dc_btag = rman_get_bustag(sc->dc_res); 2052 sc->dc_bhandle = rman_get_bushandle(sc->dc_res); 2053 2054 /* Allocate interrupt. */ 2055 rid = 0; 2056 sc->dc_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 2057 RF_SHAREABLE | RF_ACTIVE); 2058 2059 if (sc->dc_irq == NULL) { 2060 device_printf(dev, "couldn't map interrupt\n"); 2061 error = ENXIO; 2062 goto fail; 2063 } 2064 2065 /* Need this info to decide on a chip type. */ 2066 sc->dc_info = dc_devtype(dev); 2067 revision = pci_get_revid(dev); 2068 2069 error = 0; 2070 /* Get the eeprom width, but PNIC and XIRCOM have diff eeprom */ 2071 if (sc->dc_info->dc_devid != 2072 DC_DEVID(DC_VENDORID_LO, DC_DEVICEID_82C168) && 2073 sc->dc_info->dc_devid != 2074 DC_DEVID(DC_VENDORID_XIRCOM, DC_DEVICEID_X3201)) 2075 dc_eeprom_width(sc); 2076 2077 switch (sc->dc_info->dc_devid) { 2078 case DC_DEVID(DC_VENDORID_DEC, DC_DEVICEID_21143): 2079 sc->dc_type = DC_TYPE_21143; 2080 sc->dc_flags |= DC_TX_POLL | DC_TX_USE_TX_INTR; 2081 sc->dc_flags |= DC_REDUCED_MII_POLL; 2082 /* Save EEPROM contents so we can parse them later. */ 2083 error = dc_read_srom(sc, sc->dc_romwidth); 2084 if (error != 0) 2085 goto fail; 2086 break; 2087 case DC_DEVID(DC_VENDORID_DAVICOM, DC_DEVICEID_DM9009): 2088 case DC_DEVID(DC_VENDORID_DAVICOM, DC_DEVICEID_DM9100): 2089 case DC_DEVID(DC_VENDORID_DAVICOM, DC_DEVICEID_DM9102): 2090 sc->dc_type = DC_TYPE_DM9102; 2091 sc->dc_flags |= DC_TX_COALESCE | DC_TX_INTR_ALWAYS; 2092 sc->dc_flags |= DC_REDUCED_MII_POLL | DC_TX_STORENFWD; 2093 sc->dc_flags |= DC_TX_ALIGN; 2094 sc->dc_pmode = DC_PMODE_MII; 2095 2096 /* Increase the latency timer value. */ 2097 pci_write_config(dev, PCIR_LATTIMER, 0x80, 1); 2098 break; 2099 case DC_DEVID(DC_VENDORID_ADMTEK, DC_DEVICEID_AL981): 2100 sc->dc_type = DC_TYPE_AL981; 2101 sc->dc_flags |= DC_TX_USE_TX_INTR; 2102 sc->dc_flags |= DC_TX_ADMTEK_WAR; 2103 sc->dc_pmode = DC_PMODE_MII; 2104 error = dc_read_srom(sc, sc->dc_romwidth); 2105 if (error != 0) 2106 goto fail; 2107 break; 2108 case DC_DEVID(DC_VENDORID_ADMTEK, DC_DEVICEID_AN983): 2109 case DC_DEVID(DC_VENDORID_ADMTEK, DC_DEVICEID_AN985): 2110 case DC_DEVID(DC_VENDORID_ADMTEK, DC_DEVICEID_ADM9511): 2111 case DC_DEVID(DC_VENDORID_ADMTEK, DC_DEVICEID_ADM9513): 2112 case DC_DEVID(DC_VENDORID_DLINK, DC_DEVICEID_DRP32TXD): 2113 case DC_DEVID(DC_VENDORID_ABOCOM, DC_DEVICEID_FE2500): 2114 case DC_DEVID(DC_VENDORID_ABOCOM, DC_DEVICEID_FE2500MX): 2115 case DC_DEVID(DC_VENDORID_ACCTON, DC_DEVICEID_EN2242): 2116 case DC_DEVID(DC_VENDORID_HAWKING, DC_DEVICEID_HAWKING_PN672TX): 2117 case DC_DEVID(DC_VENDORID_PLANEX, DC_DEVICEID_FNW3602T): 2118 case DC_DEVID(DC_VENDORID_3COM, DC_DEVICEID_3CSOHOB): 2119 case DC_DEVID(DC_VENDORID_MICROSOFT, DC_DEVICEID_MSMN120): 2120 case DC_DEVID(DC_VENDORID_MICROSOFT, DC_DEVICEID_MSMN130): 2121 case DC_DEVID(DC_VENDORID_LINKSYS, DC_DEVICEID_PCMPC200_AB08): 2122 case DC_DEVID(DC_VENDORID_LINKSYS, DC_DEVICEID_PCMPC200_AB09): 2123 sc->dc_type = DC_TYPE_AN983; 2124 sc->dc_flags |= DC_64BIT_HASH; 2125 sc->dc_flags |= DC_TX_USE_TX_INTR; 2126 sc->dc_flags |= DC_TX_ADMTEK_WAR; 2127 sc->dc_pmode = DC_PMODE_MII; 2128 /* Don't read SROM for - auto-loaded on reset */ 2129 break; 2130 case DC_DEVID(DC_VENDORID_MX, DC_DEVICEID_98713): 2131 case DC_DEVID(DC_VENDORID_CP, DC_DEVICEID_98713_CP): 2132 if (revision < DC_REVISION_98713A) { 2133 sc->dc_type = DC_TYPE_98713; 2134 } 2135 if (revision >= DC_REVISION_98713A) { 2136 sc->dc_type = DC_TYPE_98713A; 2137 sc->dc_flags |= DC_21143_NWAY; 2138 } 2139 sc->dc_flags |= DC_REDUCED_MII_POLL; 2140 sc->dc_flags |= DC_TX_POLL | DC_TX_USE_TX_INTR; 2141 break; 2142 case DC_DEVID(DC_VENDORID_MX, DC_DEVICEID_987x5): 2143 case DC_DEVID(DC_VENDORID_ACCTON, DC_DEVICEID_EN1217): 2144 /* 2145 * Macronix MX98715AEC-C/D/E parts have only a 2146 * 128-bit hash table. We need to deal with these 2147 * in the same manner as the PNIC II so that we 2148 * get the right number of bits out of the 2149 * CRC routine. 2150 */ 2151 if (revision >= DC_REVISION_98715AEC_C && 2152 revision < DC_REVISION_98725) 2153 sc->dc_flags |= DC_128BIT_HASH; 2154 sc->dc_type = DC_TYPE_987x5; 2155 sc->dc_flags |= DC_TX_POLL | DC_TX_USE_TX_INTR; 2156 sc->dc_flags |= DC_REDUCED_MII_POLL | DC_21143_NWAY; 2157 break; 2158 case DC_DEVID(DC_VENDORID_MX, DC_DEVICEID_98727): 2159 sc->dc_type = DC_TYPE_987x5; 2160 sc->dc_flags |= DC_TX_POLL | DC_TX_USE_TX_INTR; 2161 sc->dc_flags |= DC_REDUCED_MII_POLL | DC_21143_NWAY; 2162 break; 2163 case DC_DEVID(DC_VENDORID_LO, DC_DEVICEID_82C115): 2164 sc->dc_type = DC_TYPE_PNICII; 2165 sc->dc_flags |= DC_TX_POLL | DC_TX_USE_TX_INTR | DC_128BIT_HASH; 2166 sc->dc_flags |= DC_REDUCED_MII_POLL | DC_21143_NWAY; 2167 break; 2168 case DC_DEVID(DC_VENDORID_LO, DC_DEVICEID_82C168): 2169 sc->dc_type = DC_TYPE_PNIC; 2170 sc->dc_flags |= DC_TX_STORENFWD | DC_TX_INTR_ALWAYS; 2171 sc->dc_flags |= DC_PNIC_RX_BUG_WAR; 2172 sc->dc_pnic_rx_buf = malloc(DC_RXLEN * 5, M_DEVBUF, M_NOWAIT); 2173 if (sc->dc_pnic_rx_buf == NULL) { 2174 device_printf(sc->dc_dev, 2175 "Could not allocate PNIC RX buffer\n"); 2176 error = ENOMEM; 2177 goto fail; 2178 } 2179 if (revision < DC_REVISION_82C169) 2180 sc->dc_pmode = DC_PMODE_SYM; 2181 break; 2182 case DC_DEVID(DC_VENDORID_ASIX, DC_DEVICEID_AX88140A): 2183 sc->dc_type = DC_TYPE_ASIX; 2184 sc->dc_flags |= DC_TX_USE_TX_INTR | DC_TX_INTR_FIRSTFRAG; 2185 sc->dc_flags |= DC_REDUCED_MII_POLL; 2186 sc->dc_pmode = DC_PMODE_MII; 2187 break; 2188 case DC_DEVID(DC_VENDORID_XIRCOM, DC_DEVICEID_X3201): 2189 sc->dc_type = DC_TYPE_XIRCOM; 2190 sc->dc_flags |= DC_TX_INTR_ALWAYS | DC_TX_COALESCE | 2191 DC_TX_ALIGN; 2192 /* 2193 * We don't actually need to coalesce, but we're doing 2194 * it to obtain a double word aligned buffer. 2195 * The DC_TX_COALESCE flag is required. 2196 */ 2197 sc->dc_pmode = DC_PMODE_MII; 2198 break; 2199 case DC_DEVID(DC_VENDORID_CONEXANT, DC_DEVICEID_RS7112): 2200 sc->dc_type = DC_TYPE_CONEXANT; 2201 sc->dc_flags |= DC_TX_INTR_ALWAYS; 2202 sc->dc_flags |= DC_REDUCED_MII_POLL; 2203 sc->dc_pmode = DC_PMODE_MII; 2204 error = dc_read_srom(sc, sc->dc_romwidth); 2205 if (error != 0) 2206 goto fail; 2207 break; 2208 case DC_DEVID(DC_VENDORID_ULI, DC_DEVICEID_M5261): 2209 case DC_DEVID(DC_VENDORID_ULI, DC_DEVICEID_M5263): 2210 if (sc->dc_info->dc_devid == 2211 DC_DEVID(DC_VENDORID_ULI, DC_DEVICEID_M5261)) 2212 sc->dc_type = DC_TYPE_ULI_M5261; 2213 else 2214 sc->dc_type = DC_TYPE_ULI_M5263; 2215 /* TX buffers should be aligned on 4 byte boundary. */ 2216 sc->dc_flags |= DC_TX_INTR_ALWAYS | DC_TX_COALESCE | 2217 DC_TX_ALIGN; 2218 sc->dc_pmode = DC_PMODE_MII; 2219 error = dc_read_srom(sc, sc->dc_romwidth); 2220 if (error != 0) 2221 goto fail; 2222 break; 2223 default: 2224 device_printf(dev, "unknown device: %x\n", 2225 sc->dc_info->dc_devid); 2226 break; 2227 } 2228 2229 /* Save the cache line size. */ 2230 if (DC_IS_DAVICOM(sc)) 2231 sc->dc_cachesize = 0; 2232 else 2233 sc->dc_cachesize = pci_get_cachelnsz(dev); 2234 2235 /* Reset the adapter. */ 2236 dc_reset(sc); 2237 2238 /* Take 21143 out of snooze mode */ 2239 if (DC_IS_INTEL(sc) || DC_IS_XIRCOM(sc)) { 2240 command = pci_read_config(dev, DC_PCI_CFDD, 4); 2241 command &= ~(DC_CFDD_SNOOZE_MODE | DC_CFDD_SLEEP_MODE); 2242 pci_write_config(dev, DC_PCI_CFDD, command, 4); 2243 } 2244 2245 /* 2246 * Try to learn something about the supported media. 2247 * We know that ASIX and ADMtek and Davicom devices 2248 * will *always* be using MII media, so that's a no-brainer. 2249 * The tricky ones are the Macronix/PNIC II and the 2250 * Intel 21143. 2251 */ 2252 if (DC_IS_INTEL(sc)) { 2253 error = dc_parse_21143_srom(sc); 2254 if (error != 0) 2255 goto fail; 2256 } else if (DC_IS_MACRONIX(sc) || DC_IS_PNICII(sc)) { 2257 if (sc->dc_type == DC_TYPE_98713) 2258 sc->dc_pmode = DC_PMODE_MII; 2259 else 2260 sc->dc_pmode = DC_PMODE_SYM; 2261 } else if (!sc->dc_pmode) 2262 sc->dc_pmode = DC_PMODE_MII; 2263 2264 /* 2265 * Get station address from the EEPROM. 2266 */ 2267 switch(sc->dc_type) { 2268 case DC_TYPE_98713: 2269 case DC_TYPE_98713A: 2270 case DC_TYPE_987x5: 2271 case DC_TYPE_PNICII: 2272 dc_read_eeprom(sc, (caddr_t)&mac_offset, 2273 (DC_EE_NODEADDR_OFFSET / 2), 1, 0); 2274 dc_read_eeprom(sc, (caddr_t)&eaddr, (mac_offset / 2), 3, 0); 2275 break; 2276 case DC_TYPE_PNIC: 2277 dc_read_eeprom(sc, (caddr_t)&eaddr, 0, 3, 1); 2278 break; 2279 case DC_TYPE_DM9102: 2280 dc_read_eeprom(sc, (caddr_t)&eaddr, DC_EE_NODEADDR, 3, 0); 2281 #ifdef __sparc64__ 2282 /* 2283 * If this is an onboard dc(4) the station address read from 2284 * the EEPROM is all zero and we have to get it from the FCode. 2285 */ 2286 if (eaddr[0] == 0 && (eaddr[1] & ~0xffff) == 0) 2287 OF_getetheraddr(dev, (caddr_t)&eaddr); 2288 #endif 2289 break; 2290 case DC_TYPE_21143: 2291 case DC_TYPE_ASIX: 2292 dc_read_eeprom(sc, (caddr_t)&eaddr, DC_EE_NODEADDR, 3, 0); 2293 break; 2294 case DC_TYPE_AL981: 2295 case DC_TYPE_AN983: 2296 reg = CSR_READ_4(sc, DC_AL_PAR0); 2297 mac = (uint8_t *)&eaddr[0]; 2298 mac[0] = (reg >> 0) & 0xff; 2299 mac[1] = (reg >> 8) & 0xff; 2300 mac[2] = (reg >> 16) & 0xff; 2301 mac[3] = (reg >> 24) & 0xff; 2302 reg = CSR_READ_4(sc, DC_AL_PAR1); 2303 mac[4] = (reg >> 0) & 0xff; 2304 mac[5] = (reg >> 8) & 0xff; 2305 break; 2306 case DC_TYPE_CONEXANT: 2307 bcopy(sc->dc_srom + DC_CONEXANT_EE_NODEADDR, &eaddr, 2308 ETHER_ADDR_LEN); 2309 break; 2310 case DC_TYPE_XIRCOM: 2311 /* The MAC comes from the CIS. */ 2312 mac = pci_get_ether(dev); 2313 if (!mac) { 2314 device_printf(dev, "No station address in CIS!\n"); 2315 error = ENXIO; 2316 goto fail; 2317 } 2318 bcopy(mac, eaddr, ETHER_ADDR_LEN); 2319 break; 2320 case DC_TYPE_ULI_M5261: 2321 case DC_TYPE_ULI_M5263: 2322 srom = (uint16_t *)sc->dc_srom; 2323 if (srom == NULL || *srom == 0xFFFF || *srom == 0) { 2324 /* 2325 * No valid SROM present, read station address 2326 * from ID Table. 2327 */ 2328 device_printf(dev, 2329 "Reading station address from ID Table.\n"); 2330 CSR_WRITE_4(sc, DC_BUSCTL, 0x10000); 2331 CSR_WRITE_4(sc, DC_SIARESET, 0x01C0); 2332 CSR_WRITE_4(sc, DC_10BTCTRL, 0x0000); 2333 CSR_WRITE_4(sc, DC_10BTCTRL, 0x0010); 2334 CSR_WRITE_4(sc, DC_10BTCTRL, 0x0000); 2335 CSR_WRITE_4(sc, DC_SIARESET, 0x0000); 2336 CSR_WRITE_4(sc, DC_SIARESET, 0x01B0); 2337 mac = (uint8_t *)eaddr; 2338 for (n = 0; n < ETHER_ADDR_LEN; n++) 2339 mac[n] = (uint8_t)CSR_READ_4(sc, DC_10BTCTRL); 2340 CSR_WRITE_4(sc, DC_SIARESET, 0x0000); 2341 CSR_WRITE_4(sc, DC_BUSCTL, 0x0000); 2342 DELAY(10); 2343 } else 2344 dc_read_eeprom(sc, (caddr_t)&eaddr, DC_EE_NODEADDR, 3, 2345 0); 2346 break; 2347 default: 2348 dc_read_eeprom(sc, (caddr_t)&eaddr, DC_EE_NODEADDR, 3, 0); 2349 break; 2350 } 2351 2352 bcopy(eaddr, sc->dc_eaddr, sizeof(eaddr)); 2353 /* 2354 * If we still have invalid station address, see whether we can 2355 * find station address for chip 0. Some multi-port controllers 2356 * just store station address for chip 0 if they have a shared 2357 * SROM. 2358 */ 2359 if ((sc->dc_eaddr[0] == 0 && (sc->dc_eaddr[1] & ~0xffff) == 0) || 2360 (sc->dc_eaddr[0] == 0xffffffff && 2361 (sc->dc_eaddr[1] & 0xffff) == 0xffff)) { 2362 error = dc_check_multiport(sc); 2363 if (error == 0) { 2364 bcopy(sc->dc_eaddr, eaddr, sizeof(eaddr)); 2365 /* Extract media information. */ 2366 if (DC_IS_INTEL(sc) && sc->dc_srom != NULL) { 2367 while (sc->dc_mi != NULL) { 2368 m = sc->dc_mi->dc_next; 2369 free(sc->dc_mi, M_DEVBUF); 2370 sc->dc_mi = m; 2371 } 2372 error = dc_parse_21143_srom(sc); 2373 if (error != 0) 2374 goto fail; 2375 } 2376 } else if (error == ENOMEM) 2377 goto fail; 2378 else 2379 error = 0; 2380 } 2381 2382 if ((error = dc_dma_alloc(sc)) != 0) 2383 goto fail; 2384 2385 ifp = sc->dc_ifp = if_alloc(IFT_ETHER); 2386 if (ifp == NULL) { 2387 device_printf(dev, "can not if_alloc()\n"); 2388 error = ENOSPC; 2389 goto fail; 2390 } 2391 ifp->if_softc = sc; 2392 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 2393 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 2394 ifp->if_ioctl = dc_ioctl; 2395 ifp->if_start = dc_start; 2396 ifp->if_init = dc_init; 2397 IFQ_SET_MAXLEN(&ifp->if_snd, DC_TX_LIST_CNT - 1); 2398 ifp->if_snd.ifq_drv_maxlen = DC_TX_LIST_CNT - 1; 2399 IFQ_SET_READY(&ifp->if_snd); 2400 2401 /* 2402 * Do MII setup. If this is a 21143, check for a PHY on the 2403 * MII bus after applying any necessary fixups to twiddle the 2404 * GPIO bits. If we don't end up finding a PHY, restore the 2405 * old selection (SIA only or SIA/SYM) and attach the dcphy 2406 * driver instead. 2407 */ 2408 tmp = 0; 2409 if (DC_IS_INTEL(sc)) { 2410 dc_apply_fixup(sc, IFM_AUTO); 2411 tmp = sc->dc_pmode; 2412 sc->dc_pmode = DC_PMODE_MII; 2413 } 2414 2415 /* 2416 * Setup General Purpose port mode and data so the tulip can talk 2417 * to the MII. This needs to be done before mii_attach so that 2418 * we can actually see them. 2419 */ 2420 if (DC_IS_XIRCOM(sc)) { 2421 CSR_WRITE_4(sc, DC_SIAGP, DC_SIAGP_WRITE_EN | DC_SIAGP_INT1_EN | 2422 DC_SIAGP_MD_GP2_OUTPUT | DC_SIAGP_MD_GP0_OUTPUT); 2423 DELAY(10); 2424 CSR_WRITE_4(sc, DC_SIAGP, DC_SIAGP_INT1_EN | 2425 DC_SIAGP_MD_GP2_OUTPUT | DC_SIAGP_MD_GP0_OUTPUT); 2426 DELAY(10); 2427 } 2428 2429 phy = MII_PHY_ANY; 2430 /* 2431 * Note: both the AL981 and AN983 have internal PHYs, however the 2432 * AL981 provides direct access to the PHY registers while the AN983 2433 * uses a serial MII interface. The AN983's MII interface is also 2434 * buggy in that you can read from any MII address (0 to 31), but 2435 * only address 1 behaves normally. To deal with both cases, we 2436 * pretend that the PHY is at MII address 1. 2437 */ 2438 if (DC_IS_ADMTEK(sc)) 2439 phy = DC_ADMTEK_PHYADDR; 2440 2441 /* 2442 * Note: the ukphy probes of the RS7112 report a PHY at MII address 2443 * 0 (possibly HomePNA?) and 1 (ethernet) so we only respond to the 2444 * correct one. 2445 */ 2446 if (DC_IS_CONEXANT(sc)) 2447 phy = DC_CONEXANT_PHYADDR; 2448 2449 error = mii_attach(dev, &sc->dc_miibus, ifp, dc_ifmedia_upd, 2450 dc_ifmedia_sts, BMSR_DEFCAPMASK, phy, MII_OFFSET_ANY, 0); 2451 2452 if (error && DC_IS_INTEL(sc)) { 2453 sc->dc_pmode = tmp; 2454 if (sc->dc_pmode != DC_PMODE_SIA) 2455 sc->dc_pmode = DC_PMODE_SYM; 2456 sc->dc_flags |= DC_21143_NWAY; 2457 /* 2458 * For non-MII cards, we need to have the 21143 2459 * drive the LEDs. Except there are some systems 2460 * like the NEC VersaPro NoteBook PC which have no 2461 * LEDs, and twiddling these bits has adverse effects 2462 * on them. (I.e. you suddenly can't get a link.) 2463 */ 2464 if (!(pci_get_subvendor(dev) == 0x1033 && 2465 pci_get_subdevice(dev) == 0x8028)) 2466 sc->dc_flags |= DC_TULIP_LEDS; 2467 error = mii_attach(dev, &sc->dc_miibus, ifp, dc_ifmedia_upd, 2468 dc_ifmedia_sts, BMSR_DEFCAPMASK, MII_PHY_ANY, 2469 MII_OFFSET_ANY, 0); 2470 } 2471 2472 if (error) { 2473 device_printf(dev, "attaching PHYs failed\n"); 2474 goto fail; 2475 } 2476 2477 if (DC_IS_ADMTEK(sc)) { 2478 /* 2479 * Set automatic TX underrun recovery for the ADMtek chips 2480 */ 2481 DC_SETBIT(sc, DC_AL_CR, DC_AL_CR_ATUR); 2482 } 2483 2484 /* 2485 * Tell the upper layer(s) we support long frames. 2486 */ 2487 ifp->if_hdrlen = sizeof(struct ether_vlan_header); 2488 ifp->if_capabilities |= IFCAP_VLAN_MTU; 2489 ifp->if_capenable = ifp->if_capabilities; 2490 #ifdef DEVICE_POLLING 2491 ifp->if_capabilities |= IFCAP_POLLING; 2492 #endif 2493 2494 callout_init_mtx(&sc->dc_stat_ch, &sc->dc_mtx, 0); 2495 callout_init_mtx(&sc->dc_wdog_ch, &sc->dc_mtx, 0); 2496 2497 /* 2498 * Call MI attach routine. 2499 */ 2500 ether_ifattach(ifp, (caddr_t)eaddr); 2501 2502 /* Hook interrupt last to avoid having to lock softc */ 2503 error = bus_setup_intr(dev, sc->dc_irq, INTR_TYPE_NET | INTR_MPSAFE, 2504 NULL, dc_intr, sc, &sc->dc_intrhand); 2505 2506 if (error) { 2507 device_printf(dev, "couldn't set up irq\n"); 2508 ether_ifdetach(ifp); 2509 goto fail; 2510 } 2511 2512 fail: 2513 if (error) 2514 dc_detach(dev); 2515 return (error); 2516 } 2517 2518 /* 2519 * Shutdown hardware and free up resources. This can be called any 2520 * time after the mutex has been initialized. It is called in both 2521 * the error case in attach and the normal detach case so it needs 2522 * to be careful about only freeing resources that have actually been 2523 * allocated. 2524 */ 2525 static int 2526 dc_detach(device_t dev) 2527 { 2528 struct dc_softc *sc; 2529 struct ifnet *ifp; 2530 struct dc_mediainfo *m; 2531 2532 sc = device_get_softc(dev); 2533 KASSERT(mtx_initialized(&sc->dc_mtx), ("dc mutex not initialized")); 2534 2535 ifp = sc->dc_ifp; 2536 2537 #ifdef DEVICE_POLLING 2538 if (ifp != NULL && ifp->if_capenable & IFCAP_POLLING) 2539 ether_poll_deregister(ifp); 2540 #endif 2541 2542 /* These should only be active if attach succeeded */ 2543 if (device_is_attached(dev)) { 2544 DC_LOCK(sc); 2545 dc_stop(sc); 2546 DC_UNLOCK(sc); 2547 callout_drain(&sc->dc_stat_ch); 2548 callout_drain(&sc->dc_wdog_ch); 2549 ether_ifdetach(ifp); 2550 } 2551 if (sc->dc_miibus) 2552 device_delete_child(dev, sc->dc_miibus); 2553 bus_generic_detach(dev); 2554 2555 if (sc->dc_intrhand) 2556 bus_teardown_intr(dev, sc->dc_irq, sc->dc_intrhand); 2557 if (sc->dc_irq) 2558 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->dc_irq); 2559 if (sc->dc_res) 2560 bus_release_resource(dev, DC_RES, DC_RID, sc->dc_res); 2561 2562 if (ifp != NULL) 2563 if_free(ifp); 2564 2565 dc_dma_free(sc); 2566 2567 free(sc->dc_pnic_rx_buf, M_DEVBUF); 2568 2569 while (sc->dc_mi != NULL) { 2570 m = sc->dc_mi->dc_next; 2571 free(sc->dc_mi, M_DEVBUF); 2572 sc->dc_mi = m; 2573 } 2574 free(sc->dc_srom, M_DEVBUF); 2575 2576 mtx_destroy(&sc->dc_mtx); 2577 2578 return (0); 2579 } 2580 2581 /* 2582 * Initialize the transmit descriptors. 2583 */ 2584 static int 2585 dc_list_tx_init(struct dc_softc *sc) 2586 { 2587 struct dc_chain_data *cd; 2588 struct dc_list_data *ld; 2589 int i, nexti; 2590 2591 cd = &sc->dc_cdata; 2592 ld = &sc->dc_ldata; 2593 for (i = 0; i < DC_TX_LIST_CNT; i++) { 2594 if (i == DC_TX_LIST_CNT - 1) 2595 nexti = 0; 2596 else 2597 nexti = i + 1; 2598 ld->dc_tx_list[i].dc_status = 0; 2599 ld->dc_tx_list[i].dc_ctl = 0; 2600 ld->dc_tx_list[i].dc_data = 0; 2601 ld->dc_tx_list[i].dc_next = htole32(DC_TXDESC(sc, nexti)); 2602 cd->dc_tx_chain[i] = NULL; 2603 } 2604 2605 cd->dc_tx_prod = cd->dc_tx_cons = cd->dc_tx_cnt = 0; 2606 cd->dc_tx_pkts = 0; 2607 bus_dmamap_sync(sc->dc_tx_ltag, sc->dc_tx_lmap, 2608 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2609 return (0); 2610 } 2611 2612 /* 2613 * Initialize the RX descriptors and allocate mbufs for them. Note that 2614 * we arrange the descriptors in a closed ring, so that the last descriptor 2615 * points back to the first. 2616 */ 2617 static int 2618 dc_list_rx_init(struct dc_softc *sc) 2619 { 2620 struct dc_chain_data *cd; 2621 struct dc_list_data *ld; 2622 int i, nexti; 2623 2624 cd = &sc->dc_cdata; 2625 ld = &sc->dc_ldata; 2626 2627 for (i = 0; i < DC_RX_LIST_CNT; i++) { 2628 if (dc_newbuf(sc, i) != 0) 2629 return (ENOBUFS); 2630 if (i == DC_RX_LIST_CNT - 1) 2631 nexti = 0; 2632 else 2633 nexti = i + 1; 2634 ld->dc_rx_list[i].dc_next = htole32(DC_RXDESC(sc, nexti)); 2635 } 2636 2637 cd->dc_rx_prod = 0; 2638 bus_dmamap_sync(sc->dc_rx_ltag, sc->dc_rx_lmap, 2639 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2640 return (0); 2641 } 2642 2643 /* 2644 * Initialize an RX descriptor and attach an MBUF cluster. 2645 */ 2646 static int 2647 dc_newbuf(struct dc_softc *sc, int i) 2648 { 2649 struct mbuf *m; 2650 bus_dmamap_t map; 2651 bus_dma_segment_t segs[1]; 2652 int error, nseg; 2653 2654 m = m_getcl(M_NOWAIT, MT_DATA, M_PKTHDR); 2655 if (m == NULL) 2656 return (ENOBUFS); 2657 m->m_len = m->m_pkthdr.len = MCLBYTES; 2658 m_adj(m, sizeof(u_int64_t)); 2659 2660 /* 2661 * If this is a PNIC chip, zero the buffer. This is part 2662 * of the workaround for the receive bug in the 82c168 and 2663 * 82c169 chips. 2664 */ 2665 if (sc->dc_flags & DC_PNIC_RX_BUG_WAR) 2666 bzero(mtod(m, char *), m->m_len); 2667 2668 error = bus_dmamap_load_mbuf_sg(sc->dc_rx_mtag, sc->dc_sparemap, 2669 m, segs, &nseg, 0); 2670 if (error) { 2671 m_freem(m); 2672 return (error); 2673 } 2674 KASSERT(nseg == 1, ("%s: wrong number of segments (%d)", __func__, 2675 nseg)); 2676 if (sc->dc_cdata.dc_rx_chain[i] != NULL) 2677 bus_dmamap_unload(sc->dc_rx_mtag, sc->dc_cdata.dc_rx_map[i]); 2678 2679 map = sc->dc_cdata.dc_rx_map[i]; 2680 sc->dc_cdata.dc_rx_map[i] = sc->dc_sparemap; 2681 sc->dc_sparemap = map; 2682 sc->dc_cdata.dc_rx_chain[i] = m; 2683 bus_dmamap_sync(sc->dc_rx_mtag, sc->dc_cdata.dc_rx_map[i], 2684 BUS_DMASYNC_PREREAD); 2685 2686 sc->dc_ldata.dc_rx_list[i].dc_ctl = htole32(DC_RXCTL_RLINK | DC_RXLEN); 2687 sc->dc_ldata.dc_rx_list[i].dc_data = 2688 htole32(DC_ADDR_LO(segs[0].ds_addr)); 2689 sc->dc_ldata.dc_rx_list[i].dc_status = htole32(DC_RXSTAT_OWN); 2690 bus_dmamap_sync(sc->dc_rx_ltag, sc->dc_rx_lmap, 2691 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2692 return (0); 2693 } 2694 2695 /* 2696 * Grrrrr. 2697 * The PNIC chip has a terrible bug in it that manifests itself during 2698 * periods of heavy activity. The exact mode of failure if difficult to 2699 * pinpoint: sometimes it only happens in promiscuous mode, sometimes it 2700 * will happen on slow machines. The bug is that sometimes instead of 2701 * uploading one complete frame during reception, it uploads what looks 2702 * like the entire contents of its FIFO memory. The frame we want is at 2703 * the end of the whole mess, but we never know exactly how much data has 2704 * been uploaded, so salvaging the frame is hard. 2705 * 2706 * There is only one way to do it reliably, and it's disgusting. 2707 * Here's what we know: 2708 * 2709 * - We know there will always be somewhere between one and three extra 2710 * descriptors uploaded. 2711 * 2712 * - We know the desired received frame will always be at the end of the 2713 * total data upload. 2714 * 2715 * - We know the size of the desired received frame because it will be 2716 * provided in the length field of the status word in the last descriptor. 2717 * 2718 * Here's what we do: 2719 * 2720 * - When we allocate buffers for the receive ring, we bzero() them. 2721 * This means that we know that the buffer contents should be all 2722 * zeros, except for data uploaded by the chip. 2723 * 2724 * - We also force the PNIC chip to upload frames that include the 2725 * ethernet CRC at the end. 2726 * 2727 * - We gather all of the bogus frame data into a single buffer. 2728 * 2729 * - We then position a pointer at the end of this buffer and scan 2730 * backwards until we encounter the first non-zero byte of data. 2731 * This is the end of the received frame. We know we will encounter 2732 * some data at the end of the frame because the CRC will always be 2733 * there, so even if the sender transmits a packet of all zeros, 2734 * we won't be fooled. 2735 * 2736 * - We know the size of the actual received frame, so we subtract 2737 * that value from the current pointer location. This brings us 2738 * to the start of the actual received packet. 2739 * 2740 * - We copy this into an mbuf and pass it on, along with the actual 2741 * frame length. 2742 * 2743 * The performance hit is tremendous, but it beats dropping frames all 2744 * the time. 2745 */ 2746 2747 #define DC_WHOLEFRAME (DC_RXSTAT_FIRSTFRAG | DC_RXSTAT_LASTFRAG) 2748 static void 2749 dc_pnic_rx_bug_war(struct dc_softc *sc, int idx) 2750 { 2751 struct dc_desc *cur_rx; 2752 struct dc_desc *c = NULL; 2753 struct mbuf *m = NULL; 2754 unsigned char *ptr; 2755 int i, total_len; 2756 uint32_t rxstat = 0; 2757 2758 i = sc->dc_pnic_rx_bug_save; 2759 cur_rx = &sc->dc_ldata.dc_rx_list[idx]; 2760 ptr = sc->dc_pnic_rx_buf; 2761 bzero(ptr, DC_RXLEN * 5); 2762 2763 /* Copy all the bytes from the bogus buffers. */ 2764 while (1) { 2765 c = &sc->dc_ldata.dc_rx_list[i]; 2766 rxstat = le32toh(c->dc_status); 2767 m = sc->dc_cdata.dc_rx_chain[i]; 2768 bcopy(mtod(m, char *), ptr, DC_RXLEN); 2769 ptr += DC_RXLEN; 2770 /* If this is the last buffer, break out. */ 2771 if (i == idx || rxstat & DC_RXSTAT_LASTFRAG) 2772 break; 2773 dc_discard_rxbuf(sc, i); 2774 DC_INC(i, DC_RX_LIST_CNT); 2775 } 2776 2777 /* Find the length of the actual receive frame. */ 2778 total_len = DC_RXBYTES(rxstat); 2779 2780 /* Scan backwards until we hit a non-zero byte. */ 2781 while (*ptr == 0x00) 2782 ptr--; 2783 2784 /* Round off. */ 2785 if ((uintptr_t)(ptr) & 0x3) 2786 ptr -= 1; 2787 2788 /* Now find the start of the frame. */ 2789 ptr -= total_len; 2790 if (ptr < sc->dc_pnic_rx_buf) 2791 ptr = sc->dc_pnic_rx_buf; 2792 2793 /* 2794 * Now copy the salvaged frame to the last mbuf and fake up 2795 * the status word to make it look like a successful 2796 * frame reception. 2797 */ 2798 bcopy(ptr, mtod(m, char *), total_len); 2799 cur_rx->dc_status = htole32(rxstat | DC_RXSTAT_FIRSTFRAG); 2800 } 2801 2802 /* 2803 * This routine searches the RX ring for dirty descriptors in the 2804 * event that the rxeof routine falls out of sync with the chip's 2805 * current descriptor pointer. This may happen sometimes as a result 2806 * of a "no RX buffer available" condition that happens when the chip 2807 * consumes all of the RX buffers before the driver has a chance to 2808 * process the RX ring. This routine may need to be called more than 2809 * once to bring the driver back in sync with the chip, however we 2810 * should still be getting RX DONE interrupts to drive the search 2811 * for new packets in the RX ring, so we should catch up eventually. 2812 */ 2813 static int 2814 dc_rx_resync(struct dc_softc *sc) 2815 { 2816 struct dc_desc *cur_rx; 2817 int i, pos; 2818 2819 pos = sc->dc_cdata.dc_rx_prod; 2820 2821 for (i = 0; i < DC_RX_LIST_CNT; i++) { 2822 cur_rx = &sc->dc_ldata.dc_rx_list[pos]; 2823 if (!(le32toh(cur_rx->dc_status) & DC_RXSTAT_OWN)) 2824 break; 2825 DC_INC(pos, DC_RX_LIST_CNT); 2826 } 2827 2828 /* If the ring really is empty, then just return. */ 2829 if (i == DC_RX_LIST_CNT) 2830 return (0); 2831 2832 /* We've fallen behing the chip: catch it. */ 2833 sc->dc_cdata.dc_rx_prod = pos; 2834 2835 return (EAGAIN); 2836 } 2837 2838 static void 2839 dc_discard_rxbuf(struct dc_softc *sc, int i) 2840 { 2841 struct mbuf *m; 2842 2843 if (sc->dc_flags & DC_PNIC_RX_BUG_WAR) { 2844 m = sc->dc_cdata.dc_rx_chain[i]; 2845 bzero(mtod(m, char *), m->m_len); 2846 } 2847 2848 sc->dc_ldata.dc_rx_list[i].dc_ctl = htole32(DC_RXCTL_RLINK | DC_RXLEN); 2849 sc->dc_ldata.dc_rx_list[i].dc_status = htole32(DC_RXSTAT_OWN); 2850 bus_dmamap_sync(sc->dc_rx_ltag, sc->dc_rx_lmap, BUS_DMASYNC_PREREAD | 2851 BUS_DMASYNC_PREWRITE); 2852 } 2853 2854 /* 2855 * A frame has been uploaded: pass the resulting mbuf chain up to 2856 * the higher level protocols. 2857 */ 2858 static int 2859 dc_rxeof(struct dc_softc *sc) 2860 { 2861 struct mbuf *m; 2862 struct ifnet *ifp; 2863 struct dc_desc *cur_rx; 2864 int i, total_len, rx_npkts; 2865 uint32_t rxstat; 2866 2867 DC_LOCK_ASSERT(sc); 2868 2869 ifp = sc->dc_ifp; 2870 rx_npkts = 0; 2871 2872 bus_dmamap_sync(sc->dc_rx_ltag, sc->dc_rx_lmap, BUS_DMASYNC_POSTREAD | 2873 BUS_DMASYNC_POSTWRITE); 2874 for (i = sc->dc_cdata.dc_rx_prod; 2875 (ifp->if_drv_flags & IFF_DRV_RUNNING) != 0; 2876 DC_INC(i, DC_RX_LIST_CNT)) { 2877 #ifdef DEVICE_POLLING 2878 if (ifp->if_capenable & IFCAP_POLLING) { 2879 if (sc->rxcycles <= 0) 2880 break; 2881 sc->rxcycles--; 2882 } 2883 #endif 2884 cur_rx = &sc->dc_ldata.dc_rx_list[i]; 2885 rxstat = le32toh(cur_rx->dc_status); 2886 if ((rxstat & DC_RXSTAT_OWN) != 0) 2887 break; 2888 m = sc->dc_cdata.dc_rx_chain[i]; 2889 bus_dmamap_sync(sc->dc_rx_mtag, sc->dc_cdata.dc_rx_map[i], 2890 BUS_DMASYNC_POSTREAD); 2891 total_len = DC_RXBYTES(rxstat); 2892 rx_npkts++; 2893 2894 if (sc->dc_flags & DC_PNIC_RX_BUG_WAR) { 2895 if ((rxstat & DC_WHOLEFRAME) != DC_WHOLEFRAME) { 2896 if (rxstat & DC_RXSTAT_FIRSTFRAG) 2897 sc->dc_pnic_rx_bug_save = i; 2898 if ((rxstat & DC_RXSTAT_LASTFRAG) == 0) 2899 continue; 2900 dc_pnic_rx_bug_war(sc, i); 2901 rxstat = le32toh(cur_rx->dc_status); 2902 total_len = DC_RXBYTES(rxstat); 2903 } 2904 } 2905 2906 /* 2907 * If an error occurs, update stats, clear the 2908 * status word and leave the mbuf cluster in place: 2909 * it should simply get re-used next time this descriptor 2910 * comes up in the ring. However, don't report long 2911 * frames as errors since they could be vlans. 2912 */ 2913 if ((rxstat & DC_RXSTAT_RXERR)) { 2914 if (!(rxstat & DC_RXSTAT_GIANT) || 2915 (rxstat & (DC_RXSTAT_CRCERR | DC_RXSTAT_DRIBBLE | 2916 DC_RXSTAT_MIIERE | DC_RXSTAT_COLLSEEN | 2917 DC_RXSTAT_RUNT | DC_RXSTAT_DE))) { 2918 if_inc_counter(ifp, IFCOUNTER_IERRORS, 1); 2919 if (rxstat & DC_RXSTAT_COLLSEEN) 2920 if_inc_counter(ifp, IFCOUNTER_COLLISIONS, 1); 2921 dc_discard_rxbuf(sc, i); 2922 if (rxstat & DC_RXSTAT_CRCERR) 2923 continue; 2924 else { 2925 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 2926 dc_init_locked(sc); 2927 return (rx_npkts); 2928 } 2929 } 2930 } 2931 2932 /* No errors; receive the packet. */ 2933 total_len -= ETHER_CRC_LEN; 2934 #ifdef __NO_STRICT_ALIGNMENT 2935 /* 2936 * On architectures without alignment problems we try to 2937 * allocate a new buffer for the receive ring, and pass up 2938 * the one where the packet is already, saving the expensive 2939 * copy done in m_devget(). 2940 * If we are on an architecture with alignment problems, or 2941 * if the allocation fails, then use m_devget and leave the 2942 * existing buffer in the receive ring. 2943 */ 2944 if (dc_newbuf(sc, i) != 0) { 2945 dc_discard_rxbuf(sc, i); 2946 if_inc_counter(ifp, IFCOUNTER_IQDROPS, 1); 2947 continue; 2948 } 2949 m->m_pkthdr.rcvif = ifp; 2950 m->m_pkthdr.len = m->m_len = total_len; 2951 #else 2952 { 2953 struct mbuf *m0; 2954 2955 m0 = m_devget(mtod(m, char *), total_len, 2956 ETHER_ALIGN, ifp, NULL); 2957 dc_discard_rxbuf(sc, i); 2958 if (m0 == NULL) { 2959 if_inc_counter(ifp, IFCOUNTER_IQDROPS, 1); 2960 continue; 2961 } 2962 m = m0; 2963 } 2964 #endif 2965 2966 if_inc_counter(ifp, IFCOUNTER_IPACKETS, 1); 2967 DC_UNLOCK(sc); 2968 (*ifp->if_input)(ifp, m); 2969 DC_LOCK(sc); 2970 } 2971 2972 sc->dc_cdata.dc_rx_prod = i; 2973 return (rx_npkts); 2974 } 2975 2976 /* 2977 * A frame was downloaded to the chip. It's safe for us to clean up 2978 * the list buffers. 2979 */ 2980 static void 2981 dc_txeof(struct dc_softc *sc) 2982 { 2983 struct dc_desc *cur_tx; 2984 struct ifnet *ifp; 2985 int idx, setup; 2986 uint32_t ctl, txstat; 2987 2988 if (sc->dc_cdata.dc_tx_cnt == 0) 2989 return; 2990 2991 ifp = sc->dc_ifp; 2992 2993 /* 2994 * Go through our tx list and free mbufs for those 2995 * frames that have been transmitted. 2996 */ 2997 bus_dmamap_sync(sc->dc_tx_ltag, sc->dc_tx_lmap, BUS_DMASYNC_POSTREAD | 2998 BUS_DMASYNC_POSTWRITE); 2999 setup = 0; 3000 for (idx = sc->dc_cdata.dc_tx_cons; idx != sc->dc_cdata.dc_tx_prod; 3001 DC_INC(idx, DC_TX_LIST_CNT), sc->dc_cdata.dc_tx_cnt--) { 3002 cur_tx = &sc->dc_ldata.dc_tx_list[idx]; 3003 txstat = le32toh(cur_tx->dc_status); 3004 ctl = le32toh(cur_tx->dc_ctl); 3005 3006 if (txstat & DC_TXSTAT_OWN) 3007 break; 3008 3009 if (sc->dc_cdata.dc_tx_chain[idx] == NULL) 3010 continue; 3011 3012 if (ctl & DC_TXCTL_SETUP) { 3013 cur_tx->dc_ctl = htole32(ctl & ~DC_TXCTL_SETUP); 3014 setup++; 3015 bus_dmamap_sync(sc->dc_stag, sc->dc_smap, 3016 BUS_DMASYNC_POSTWRITE); 3017 /* 3018 * Yes, the PNIC is so brain damaged 3019 * that it will sometimes generate a TX 3020 * underrun error while DMAing the RX 3021 * filter setup frame. If we detect this, 3022 * we have to send the setup frame again, 3023 * or else the filter won't be programmed 3024 * correctly. 3025 */ 3026 if (DC_IS_PNIC(sc)) { 3027 if (txstat & DC_TXSTAT_ERRSUM) 3028 dc_setfilt(sc); 3029 } 3030 sc->dc_cdata.dc_tx_chain[idx] = NULL; 3031 continue; 3032 } 3033 3034 if (DC_IS_XIRCOM(sc) || DC_IS_CONEXANT(sc)) { 3035 /* 3036 * XXX: Why does my Xircom taunt me so? 3037 * For some reason it likes setting the CARRLOST flag 3038 * even when the carrier is there. wtf?!? 3039 * Who knows, but Conexant chips have the 3040 * same problem. Maybe they took lessons 3041 * from Xircom. 3042 */ 3043 if (/*sc->dc_type == DC_TYPE_21143 &&*/ 3044 sc->dc_pmode == DC_PMODE_MII && 3045 ((txstat & 0xFFFF) & ~(DC_TXSTAT_ERRSUM | 3046 DC_TXSTAT_NOCARRIER))) 3047 txstat &= ~DC_TXSTAT_ERRSUM; 3048 } else { 3049 if (/*sc->dc_type == DC_TYPE_21143 &&*/ 3050 sc->dc_pmode == DC_PMODE_MII && 3051 ((txstat & 0xFFFF) & ~(DC_TXSTAT_ERRSUM | 3052 DC_TXSTAT_NOCARRIER | DC_TXSTAT_CARRLOST))) 3053 txstat &= ~DC_TXSTAT_ERRSUM; 3054 } 3055 3056 if (txstat & DC_TXSTAT_ERRSUM) { 3057 if_inc_counter(ifp, IFCOUNTER_OERRORS, 1); 3058 if (txstat & DC_TXSTAT_EXCESSCOLL) 3059 if_inc_counter(ifp, IFCOUNTER_COLLISIONS, 1); 3060 if (txstat & DC_TXSTAT_LATECOLL) 3061 if_inc_counter(ifp, IFCOUNTER_COLLISIONS, 1); 3062 if (!(txstat & DC_TXSTAT_UNDERRUN)) { 3063 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 3064 dc_init_locked(sc); 3065 return; 3066 } 3067 } else 3068 if_inc_counter(ifp, IFCOUNTER_OPACKETS, 1); 3069 if_inc_counter(ifp, IFCOUNTER_COLLISIONS, (txstat & DC_TXSTAT_COLLCNT) >> 3); 3070 3071 bus_dmamap_sync(sc->dc_tx_mtag, sc->dc_cdata.dc_tx_map[idx], 3072 BUS_DMASYNC_POSTWRITE); 3073 bus_dmamap_unload(sc->dc_tx_mtag, sc->dc_cdata.dc_tx_map[idx]); 3074 m_freem(sc->dc_cdata.dc_tx_chain[idx]); 3075 sc->dc_cdata.dc_tx_chain[idx] = NULL; 3076 } 3077 sc->dc_cdata.dc_tx_cons = idx; 3078 3079 if (sc->dc_cdata.dc_tx_cnt <= DC_TX_LIST_CNT - DC_TX_LIST_RSVD) { 3080 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 3081 if (sc->dc_cdata.dc_tx_cnt == 0) 3082 sc->dc_wdog_timer = 0; 3083 } 3084 if (setup > 0) 3085 bus_dmamap_sync(sc->dc_tx_ltag, sc->dc_tx_lmap, 3086 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 3087 } 3088 3089 static void 3090 dc_tick(void *xsc) 3091 { 3092 struct dc_softc *sc; 3093 struct mii_data *mii; 3094 struct ifnet *ifp; 3095 uint32_t r; 3096 3097 sc = xsc; 3098 DC_LOCK_ASSERT(sc); 3099 ifp = sc->dc_ifp; 3100 mii = device_get_softc(sc->dc_miibus); 3101 3102 /* 3103 * Reclaim transmitted frames for controllers that do 3104 * not generate TX completion interrupt for every frame. 3105 */ 3106 if (sc->dc_flags & DC_TX_USE_TX_INTR) 3107 dc_txeof(sc); 3108 3109 if (sc->dc_flags & DC_REDUCED_MII_POLL) { 3110 if (sc->dc_flags & DC_21143_NWAY) { 3111 r = CSR_READ_4(sc, DC_10BTSTAT); 3112 if (IFM_SUBTYPE(mii->mii_media_active) == 3113 IFM_100_TX && (r & DC_TSTAT_LS100)) { 3114 sc->dc_link = 0; 3115 mii_mediachg(mii); 3116 } 3117 if (IFM_SUBTYPE(mii->mii_media_active) == 3118 IFM_10_T && (r & DC_TSTAT_LS10)) { 3119 sc->dc_link = 0; 3120 mii_mediachg(mii); 3121 } 3122 if (sc->dc_link == 0) 3123 mii_tick(mii); 3124 } else { 3125 /* 3126 * For NICs which never report DC_RXSTATE_WAIT, we 3127 * have to bite the bullet... 3128 */ 3129 if ((DC_HAS_BROKEN_RXSTATE(sc) || (CSR_READ_4(sc, 3130 DC_ISR) & DC_ISR_RX_STATE) == DC_RXSTATE_WAIT) && 3131 sc->dc_cdata.dc_tx_cnt == 0) 3132 mii_tick(mii); 3133 } 3134 } else 3135 mii_tick(mii); 3136 3137 /* 3138 * When the init routine completes, we expect to be able to send 3139 * packets right away, and in fact the network code will send a 3140 * gratuitous ARP the moment the init routine marks the interface 3141 * as running. However, even though the MAC may have been initialized, 3142 * there may be a delay of a few seconds before the PHY completes 3143 * autonegotiation and the link is brought up. Any transmissions 3144 * made during that delay will be lost. Dealing with this is tricky: 3145 * we can't just pause in the init routine while waiting for the 3146 * PHY to come ready since that would bring the whole system to 3147 * a screeching halt for several seconds. 3148 * 3149 * What we do here is prevent the TX start routine from sending 3150 * any packets until a link has been established. After the 3151 * interface has been initialized, the tick routine will poll 3152 * the state of the PHY until the IFM_ACTIVE flag is set. Until 3153 * that time, packets will stay in the send queue, and once the 3154 * link comes up, they will be flushed out to the wire. 3155 */ 3156 if (sc->dc_link != 0 && !IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 3157 dc_start_locked(ifp); 3158 3159 if (sc->dc_flags & DC_21143_NWAY && !sc->dc_link) 3160 callout_reset(&sc->dc_stat_ch, hz/10, dc_tick, sc); 3161 else 3162 callout_reset(&sc->dc_stat_ch, hz, dc_tick, sc); 3163 } 3164 3165 /* 3166 * A transmit underrun has occurred. Back off the transmit threshold, 3167 * or switch to store and forward mode if we have to. 3168 */ 3169 static void 3170 dc_tx_underrun(struct dc_softc *sc) 3171 { 3172 uint32_t netcfg, isr; 3173 int i, reinit; 3174 3175 reinit = 0; 3176 netcfg = CSR_READ_4(sc, DC_NETCFG); 3177 device_printf(sc->dc_dev, "TX underrun -- "); 3178 if ((sc->dc_flags & DC_TX_STORENFWD) == 0) { 3179 if (sc->dc_txthresh + DC_TXTHRESH_INC > DC_TXTHRESH_MAX) { 3180 printf("using store and forward mode\n"); 3181 netcfg |= DC_NETCFG_STORENFWD; 3182 } else { 3183 printf("increasing TX threshold\n"); 3184 sc->dc_txthresh += DC_TXTHRESH_INC; 3185 netcfg &= ~DC_NETCFG_TX_THRESH; 3186 netcfg |= sc->dc_txthresh; 3187 } 3188 3189 if (DC_IS_INTEL(sc)) { 3190 /* 3191 * The real 21143 requires that the transmitter be idle 3192 * in order to change the transmit threshold or store 3193 * and forward state. 3194 */ 3195 CSR_WRITE_4(sc, DC_NETCFG, netcfg & ~DC_NETCFG_TX_ON); 3196 3197 for (i = 0; i < DC_TIMEOUT; i++) { 3198 isr = CSR_READ_4(sc, DC_ISR); 3199 if (isr & DC_ISR_TX_IDLE) 3200 break; 3201 DELAY(10); 3202 } 3203 if (i == DC_TIMEOUT) { 3204 device_printf(sc->dc_dev, 3205 "%s: failed to force tx to idle state\n", 3206 __func__); 3207 reinit++; 3208 } 3209 } 3210 } else { 3211 printf("resetting\n"); 3212 reinit++; 3213 } 3214 3215 if (reinit == 0) { 3216 CSR_WRITE_4(sc, DC_NETCFG, netcfg); 3217 if (DC_IS_INTEL(sc)) 3218 CSR_WRITE_4(sc, DC_NETCFG, netcfg | DC_NETCFG_TX_ON); 3219 } else { 3220 sc->dc_ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 3221 dc_init_locked(sc); 3222 } 3223 } 3224 3225 #ifdef DEVICE_POLLING 3226 static poll_handler_t dc_poll; 3227 3228 static int 3229 dc_poll(struct ifnet *ifp, enum poll_cmd cmd, int count) 3230 { 3231 struct dc_softc *sc = ifp->if_softc; 3232 int rx_npkts = 0; 3233 3234 DC_LOCK(sc); 3235 3236 if (!(ifp->if_drv_flags & IFF_DRV_RUNNING)) { 3237 DC_UNLOCK(sc); 3238 return (rx_npkts); 3239 } 3240 3241 sc->rxcycles = count; 3242 rx_npkts = dc_rxeof(sc); 3243 dc_txeof(sc); 3244 if (!IFQ_IS_EMPTY(&ifp->if_snd) && 3245 !(ifp->if_drv_flags & IFF_DRV_OACTIVE)) 3246 dc_start_locked(ifp); 3247 3248 if (cmd == POLL_AND_CHECK_STATUS) { /* also check status register */ 3249 uint32_t status; 3250 3251 status = CSR_READ_4(sc, DC_ISR); 3252 status &= (DC_ISR_RX_WATDOGTIMEO | DC_ISR_RX_NOBUF | 3253 DC_ISR_TX_NOBUF | DC_ISR_TX_IDLE | DC_ISR_TX_UNDERRUN | 3254 DC_ISR_BUS_ERR); 3255 if (!status) { 3256 DC_UNLOCK(sc); 3257 return (rx_npkts); 3258 } 3259 /* ack what we have */ 3260 CSR_WRITE_4(sc, DC_ISR, status); 3261 3262 if (status & (DC_ISR_RX_WATDOGTIMEO | DC_ISR_RX_NOBUF)) { 3263 uint32_t r = CSR_READ_4(sc, DC_FRAMESDISCARDED); 3264 if_inc_counter(ifp, IFCOUNTER_IERRORS, (r & 0xffff) + ((r >> 17) & 0x7ff)); 3265 3266 if (dc_rx_resync(sc)) 3267 dc_rxeof(sc); 3268 } 3269 /* restart transmit unit if necessary */ 3270 if (status & DC_ISR_TX_IDLE && sc->dc_cdata.dc_tx_cnt) 3271 CSR_WRITE_4(sc, DC_TXSTART, 0xFFFFFFFF); 3272 3273 if (status & DC_ISR_TX_UNDERRUN) 3274 dc_tx_underrun(sc); 3275 3276 if (status & DC_ISR_BUS_ERR) { 3277 if_printf(ifp, "%s: bus error\n", __func__); 3278 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 3279 dc_init_locked(sc); 3280 } 3281 } 3282 DC_UNLOCK(sc); 3283 return (rx_npkts); 3284 } 3285 #endif /* DEVICE_POLLING */ 3286 3287 static void 3288 dc_intr(void *arg) 3289 { 3290 struct dc_softc *sc; 3291 struct ifnet *ifp; 3292 uint32_t r, status; 3293 int n; 3294 3295 sc = arg; 3296 3297 if (sc->suspended) 3298 return; 3299 3300 DC_LOCK(sc); 3301 status = CSR_READ_4(sc, DC_ISR); 3302 if (status == 0xFFFFFFFF || (status & DC_INTRS) == 0) { 3303 DC_UNLOCK(sc); 3304 return; 3305 } 3306 ifp = sc->dc_ifp; 3307 #ifdef DEVICE_POLLING 3308 if (ifp->if_capenable & IFCAP_POLLING) { 3309 DC_UNLOCK(sc); 3310 return; 3311 } 3312 #endif 3313 /* Disable interrupts. */ 3314 CSR_WRITE_4(sc, DC_IMR, 0x00000000); 3315 3316 for (n = 16; n > 0; n--) { 3317 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) 3318 break; 3319 /* Ack interrupts. */ 3320 CSR_WRITE_4(sc, DC_ISR, status); 3321 3322 if (status & DC_ISR_RX_OK) { 3323 if (dc_rxeof(sc) == 0) { 3324 while (dc_rx_resync(sc)) 3325 dc_rxeof(sc); 3326 } 3327 } 3328 3329 if (status & (DC_ISR_TX_OK | DC_ISR_TX_NOBUF)) 3330 dc_txeof(sc); 3331 3332 if (status & DC_ISR_TX_IDLE) { 3333 dc_txeof(sc); 3334 if (sc->dc_cdata.dc_tx_cnt) { 3335 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_TX_ON); 3336 CSR_WRITE_4(sc, DC_TXSTART, 0xFFFFFFFF); 3337 } 3338 } 3339 3340 if (status & DC_ISR_TX_UNDERRUN) 3341 dc_tx_underrun(sc); 3342 3343 if ((status & DC_ISR_RX_WATDOGTIMEO) 3344 || (status & DC_ISR_RX_NOBUF)) { 3345 r = CSR_READ_4(sc, DC_FRAMESDISCARDED); 3346 if_inc_counter(ifp, IFCOUNTER_IERRORS, (r & 0xffff) + ((r >> 17) & 0x7ff)); 3347 if (dc_rxeof(sc) == 0) { 3348 while (dc_rx_resync(sc)) 3349 dc_rxeof(sc); 3350 } 3351 } 3352 3353 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 3354 dc_start_locked(ifp); 3355 3356 if (status & DC_ISR_BUS_ERR) { 3357 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 3358 dc_init_locked(sc); 3359 DC_UNLOCK(sc); 3360 return; 3361 } 3362 status = CSR_READ_4(sc, DC_ISR); 3363 if (status == 0xFFFFFFFF || (status & DC_INTRS) == 0) 3364 break; 3365 } 3366 3367 /* Re-enable interrupts. */ 3368 if (ifp->if_drv_flags & IFF_DRV_RUNNING) 3369 CSR_WRITE_4(sc, DC_IMR, DC_INTRS); 3370 3371 DC_UNLOCK(sc); 3372 } 3373 3374 /* 3375 * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data 3376 * pointers to the fragment pointers. 3377 */ 3378 static int 3379 dc_encap(struct dc_softc *sc, struct mbuf **m_head) 3380 { 3381 bus_dma_segment_t segs[DC_MAXFRAGS]; 3382 bus_dmamap_t map; 3383 struct dc_desc *f; 3384 struct mbuf *m; 3385 int cur, defragged, error, first, frag, i, idx, nseg; 3386 3387 m = NULL; 3388 defragged = 0; 3389 if (sc->dc_flags & DC_TX_COALESCE && 3390 ((*m_head)->m_next != NULL || sc->dc_flags & DC_TX_ALIGN)) { 3391 m = m_defrag(*m_head, M_NOWAIT); 3392 defragged = 1; 3393 } else { 3394 /* 3395 * Count the number of frags in this chain to see if we 3396 * need to m_collapse. Since the descriptor list is shared 3397 * by all packets, we'll m_collapse long chains so that they 3398 * do not use up the entire list, even if they would fit. 3399 */ 3400 i = 0; 3401 for (m = *m_head; m != NULL; m = m->m_next) 3402 i++; 3403 if (i > DC_TX_LIST_CNT / 4 || 3404 DC_TX_LIST_CNT - i + sc->dc_cdata.dc_tx_cnt <= 3405 DC_TX_LIST_RSVD) { 3406 m = m_collapse(*m_head, M_NOWAIT, DC_MAXFRAGS); 3407 defragged = 1; 3408 } 3409 } 3410 if (defragged != 0) { 3411 if (m == NULL) { 3412 m_freem(*m_head); 3413 *m_head = NULL; 3414 return (ENOBUFS); 3415 } 3416 *m_head = m; 3417 } 3418 3419 idx = sc->dc_cdata.dc_tx_prod; 3420 error = bus_dmamap_load_mbuf_sg(sc->dc_tx_mtag, 3421 sc->dc_cdata.dc_tx_map[idx], *m_head, segs, &nseg, 0); 3422 if (error == EFBIG) { 3423 if (defragged != 0 || (m = m_collapse(*m_head, M_NOWAIT, 3424 DC_MAXFRAGS)) == NULL) { 3425 m_freem(*m_head); 3426 *m_head = NULL; 3427 return (defragged != 0 ? error : ENOBUFS); 3428 } 3429 *m_head = m; 3430 error = bus_dmamap_load_mbuf_sg(sc->dc_tx_mtag, 3431 sc->dc_cdata.dc_tx_map[idx], *m_head, segs, &nseg, 0); 3432 if (error != 0) { 3433 m_freem(*m_head); 3434 *m_head = NULL; 3435 return (error); 3436 } 3437 } else if (error != 0) 3438 return (error); 3439 KASSERT(nseg <= DC_MAXFRAGS, 3440 ("%s: wrong number of segments (%d)", __func__, nseg)); 3441 if (nseg == 0) { 3442 m_freem(*m_head); 3443 *m_head = NULL; 3444 return (EIO); 3445 } 3446 3447 /* Check descriptor overruns. */ 3448 if (sc->dc_cdata.dc_tx_cnt + nseg > DC_TX_LIST_CNT - DC_TX_LIST_RSVD) { 3449 bus_dmamap_unload(sc->dc_tx_mtag, sc->dc_cdata.dc_tx_map[idx]); 3450 return (ENOBUFS); 3451 } 3452 bus_dmamap_sync(sc->dc_tx_mtag, sc->dc_cdata.dc_tx_map[idx], 3453 BUS_DMASYNC_PREWRITE); 3454 3455 first = cur = frag = sc->dc_cdata.dc_tx_prod; 3456 for (i = 0; i < nseg; i++) { 3457 if ((sc->dc_flags & DC_TX_ADMTEK_WAR) && 3458 (frag == (DC_TX_LIST_CNT - 1)) && 3459 (first != sc->dc_cdata.dc_tx_first)) { 3460 bus_dmamap_unload(sc->dc_tx_mtag, 3461 sc->dc_cdata.dc_tx_map[first]); 3462 m_freem(*m_head); 3463 *m_head = NULL; 3464 return (ENOBUFS); 3465 } 3466 3467 f = &sc->dc_ldata.dc_tx_list[frag]; 3468 f->dc_ctl = htole32(DC_TXCTL_TLINK | segs[i].ds_len); 3469 if (i == 0) { 3470 f->dc_status = 0; 3471 f->dc_ctl |= htole32(DC_TXCTL_FIRSTFRAG); 3472 } else 3473 f->dc_status = htole32(DC_TXSTAT_OWN); 3474 f->dc_data = htole32(DC_ADDR_LO(segs[i].ds_addr)); 3475 cur = frag; 3476 DC_INC(frag, DC_TX_LIST_CNT); 3477 } 3478 3479 sc->dc_cdata.dc_tx_prod = frag; 3480 sc->dc_cdata.dc_tx_cnt += nseg; 3481 sc->dc_cdata.dc_tx_chain[cur] = *m_head; 3482 sc->dc_ldata.dc_tx_list[cur].dc_ctl |= htole32(DC_TXCTL_LASTFRAG); 3483 if (sc->dc_flags & DC_TX_INTR_FIRSTFRAG) 3484 sc->dc_ldata.dc_tx_list[first].dc_ctl |= 3485 htole32(DC_TXCTL_FINT); 3486 if (sc->dc_flags & DC_TX_INTR_ALWAYS) 3487 sc->dc_ldata.dc_tx_list[cur].dc_ctl |= htole32(DC_TXCTL_FINT); 3488 if (sc->dc_flags & DC_TX_USE_TX_INTR && 3489 ++sc->dc_cdata.dc_tx_pkts >= 8) { 3490 sc->dc_cdata.dc_tx_pkts = 0; 3491 sc->dc_ldata.dc_tx_list[cur].dc_ctl |= htole32(DC_TXCTL_FINT); 3492 } 3493 sc->dc_ldata.dc_tx_list[first].dc_status = htole32(DC_TXSTAT_OWN); 3494 3495 bus_dmamap_sync(sc->dc_tx_ltag, sc->dc_tx_lmap, 3496 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 3497 3498 /* 3499 * Swap the last and the first dmamaps to ensure the map for 3500 * this transmission is placed at the last descriptor. 3501 */ 3502 map = sc->dc_cdata.dc_tx_map[cur]; 3503 sc->dc_cdata.dc_tx_map[cur] = sc->dc_cdata.dc_tx_map[first]; 3504 sc->dc_cdata.dc_tx_map[first] = map; 3505 3506 return (0); 3507 } 3508 3509 static void 3510 dc_start(struct ifnet *ifp) 3511 { 3512 struct dc_softc *sc; 3513 3514 sc = ifp->if_softc; 3515 DC_LOCK(sc); 3516 dc_start_locked(ifp); 3517 DC_UNLOCK(sc); 3518 } 3519 3520 /* 3521 * Main transmit routine 3522 * To avoid having to do mbuf copies, we put pointers to the mbuf data 3523 * regions directly in the transmit lists. We also save a copy of the 3524 * pointers since the transmit list fragment pointers are physical 3525 * addresses. 3526 */ 3527 static void 3528 dc_start_locked(struct ifnet *ifp) 3529 { 3530 struct dc_softc *sc; 3531 struct mbuf *m_head; 3532 int queued; 3533 3534 sc = ifp->if_softc; 3535 3536 DC_LOCK_ASSERT(sc); 3537 3538 if ((ifp->if_drv_flags & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) != 3539 IFF_DRV_RUNNING || sc->dc_link == 0) 3540 return; 3541 3542 sc->dc_cdata.dc_tx_first = sc->dc_cdata.dc_tx_prod; 3543 3544 for (queued = 0; !IFQ_DRV_IS_EMPTY(&ifp->if_snd); ) { 3545 /* 3546 * If there's no way we can send any packets, return now. 3547 */ 3548 if (sc->dc_cdata.dc_tx_cnt > DC_TX_LIST_CNT - DC_TX_LIST_RSVD) { 3549 ifp->if_drv_flags |= IFF_DRV_OACTIVE; 3550 break; 3551 } 3552 IFQ_DRV_DEQUEUE(&ifp->if_snd, m_head); 3553 if (m_head == NULL) 3554 break; 3555 3556 if (dc_encap(sc, &m_head)) { 3557 if (m_head == NULL) 3558 break; 3559 IFQ_DRV_PREPEND(&ifp->if_snd, m_head); 3560 ifp->if_drv_flags |= IFF_DRV_OACTIVE; 3561 break; 3562 } 3563 3564 queued++; 3565 /* 3566 * If there's a BPF listener, bounce a copy of this frame 3567 * to him. 3568 */ 3569 BPF_MTAP(ifp, m_head); 3570 } 3571 3572 if (queued > 0) { 3573 /* Transmit */ 3574 if (!(sc->dc_flags & DC_TX_POLL)) 3575 CSR_WRITE_4(sc, DC_TXSTART, 0xFFFFFFFF); 3576 3577 /* 3578 * Set a timeout in case the chip goes out to lunch. 3579 */ 3580 sc->dc_wdog_timer = 5; 3581 } 3582 } 3583 3584 static void 3585 dc_init(void *xsc) 3586 { 3587 struct dc_softc *sc = xsc; 3588 3589 DC_LOCK(sc); 3590 dc_init_locked(sc); 3591 DC_UNLOCK(sc); 3592 } 3593 3594 static void 3595 dc_init_locked(struct dc_softc *sc) 3596 { 3597 struct ifnet *ifp = sc->dc_ifp; 3598 struct mii_data *mii; 3599 struct ifmedia *ifm; 3600 3601 DC_LOCK_ASSERT(sc); 3602 3603 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) 3604 return; 3605 3606 mii = device_get_softc(sc->dc_miibus); 3607 3608 /* 3609 * Cancel pending I/O and free all RX/TX buffers. 3610 */ 3611 dc_stop(sc); 3612 dc_reset(sc); 3613 if (DC_IS_INTEL(sc)) { 3614 ifm = &mii->mii_media; 3615 dc_apply_fixup(sc, ifm->ifm_media); 3616 } 3617 3618 /* 3619 * Set cache alignment and burst length. 3620 */ 3621 if (DC_IS_ASIX(sc) || DC_IS_DAVICOM(sc) || DC_IS_ULI(sc)) 3622 CSR_WRITE_4(sc, DC_BUSCTL, 0); 3623 else 3624 CSR_WRITE_4(sc, DC_BUSCTL, DC_BUSCTL_MRME | DC_BUSCTL_MRLE); 3625 /* 3626 * Evenly share the bus between receive and transmit process. 3627 */ 3628 if (DC_IS_INTEL(sc)) 3629 DC_SETBIT(sc, DC_BUSCTL, DC_BUSCTL_ARBITRATION); 3630 if (DC_IS_DAVICOM(sc) || DC_IS_INTEL(sc)) { 3631 DC_SETBIT(sc, DC_BUSCTL, DC_BURSTLEN_USECA); 3632 } else { 3633 DC_SETBIT(sc, DC_BUSCTL, DC_BURSTLEN_16LONG); 3634 } 3635 if (sc->dc_flags & DC_TX_POLL) 3636 DC_SETBIT(sc, DC_BUSCTL, DC_TXPOLL_1); 3637 switch(sc->dc_cachesize) { 3638 case 32: 3639 DC_SETBIT(sc, DC_BUSCTL, DC_CACHEALIGN_32LONG); 3640 break; 3641 case 16: 3642 DC_SETBIT(sc, DC_BUSCTL, DC_CACHEALIGN_16LONG); 3643 break; 3644 case 8: 3645 DC_SETBIT(sc, DC_BUSCTL, DC_CACHEALIGN_8LONG); 3646 break; 3647 case 0: 3648 default: 3649 DC_SETBIT(sc, DC_BUSCTL, DC_CACHEALIGN_NONE); 3650 break; 3651 } 3652 3653 if (sc->dc_flags & DC_TX_STORENFWD) 3654 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_STORENFWD); 3655 else { 3656 if (sc->dc_txthresh > DC_TXTHRESH_MAX) { 3657 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_STORENFWD); 3658 } else { 3659 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_STORENFWD); 3660 DC_SETBIT(sc, DC_NETCFG, sc->dc_txthresh); 3661 } 3662 } 3663 3664 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_NO_RXCRC); 3665 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_TX_BACKOFF); 3666 3667 if (DC_IS_MACRONIX(sc) || DC_IS_PNICII(sc)) { 3668 /* 3669 * The app notes for the 98713 and 98715A say that 3670 * in order to have the chips operate properly, a magic 3671 * number must be written to CSR16. Macronix does not 3672 * document the meaning of these bits so there's no way 3673 * to know exactly what they do. The 98713 has a magic 3674 * number all its own; the rest all use a different one. 3675 */ 3676 DC_CLRBIT(sc, DC_MX_MAGICPACKET, 0xFFFF0000); 3677 if (sc->dc_type == DC_TYPE_98713) 3678 DC_SETBIT(sc, DC_MX_MAGICPACKET, DC_MX_MAGIC_98713); 3679 else 3680 DC_SETBIT(sc, DC_MX_MAGICPACKET, DC_MX_MAGIC_98715); 3681 } 3682 3683 if (DC_IS_XIRCOM(sc)) { 3684 /* 3685 * setup General Purpose Port mode and data so the tulip 3686 * can talk to the MII. 3687 */ 3688 CSR_WRITE_4(sc, DC_SIAGP, DC_SIAGP_WRITE_EN | DC_SIAGP_INT1_EN | 3689 DC_SIAGP_MD_GP2_OUTPUT | DC_SIAGP_MD_GP0_OUTPUT); 3690 DELAY(10); 3691 CSR_WRITE_4(sc, DC_SIAGP, DC_SIAGP_INT1_EN | 3692 DC_SIAGP_MD_GP2_OUTPUT | DC_SIAGP_MD_GP0_OUTPUT); 3693 DELAY(10); 3694 } 3695 3696 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_TX_THRESH); 3697 DC_SETBIT(sc, DC_NETCFG, DC_TXTHRESH_MIN); 3698 3699 /* Init circular RX list. */ 3700 if (dc_list_rx_init(sc) == ENOBUFS) { 3701 device_printf(sc->dc_dev, 3702 "initialization failed: no memory for rx buffers\n"); 3703 dc_stop(sc); 3704 return; 3705 } 3706 3707 /* 3708 * Init TX descriptors. 3709 */ 3710 dc_list_tx_init(sc); 3711 3712 /* 3713 * Load the address of the RX list. 3714 */ 3715 CSR_WRITE_4(sc, DC_RXADDR, DC_RXDESC(sc, 0)); 3716 CSR_WRITE_4(sc, DC_TXADDR, DC_TXDESC(sc, 0)); 3717 3718 /* 3719 * Enable interrupts. 3720 */ 3721 #ifdef DEVICE_POLLING 3722 /* 3723 * ... but only if we are not polling, and make sure they are off in 3724 * the case of polling. Some cards (e.g. fxp) turn interrupts on 3725 * after a reset. 3726 */ 3727 if (ifp->if_capenable & IFCAP_POLLING) 3728 CSR_WRITE_4(sc, DC_IMR, 0x00000000); 3729 else 3730 #endif 3731 CSR_WRITE_4(sc, DC_IMR, DC_INTRS); 3732 CSR_WRITE_4(sc, DC_ISR, 0xFFFFFFFF); 3733 3734 /* Initialize TX jabber and RX watchdog timer. */ 3735 if (DC_IS_ULI(sc)) 3736 CSR_WRITE_4(sc, DC_WATCHDOG, DC_WDOG_JABBERCLK | 3737 DC_WDOG_HOSTUNJAB); 3738 3739 /* Enable transmitter. */ 3740 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_TX_ON); 3741 3742 /* 3743 * If this is an Intel 21143 and we're not using the 3744 * MII port, program the LED control pins so we get 3745 * link and activity indications. 3746 */ 3747 if (sc->dc_flags & DC_TULIP_LEDS) { 3748 CSR_WRITE_4(sc, DC_WATCHDOG, 3749 DC_WDOG_CTLWREN | DC_WDOG_LINK | DC_WDOG_ACTIVITY); 3750 CSR_WRITE_4(sc, DC_WATCHDOG, 0); 3751 } 3752 3753 /* 3754 * Load the RX/multicast filter. We do this sort of late 3755 * because the filter programming scheme on the 21143 and 3756 * some clones requires DMAing a setup frame via the TX 3757 * engine, and we need the transmitter enabled for that. 3758 */ 3759 dc_setfilt(sc); 3760 3761 /* Enable receiver. */ 3762 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_ON); 3763 CSR_WRITE_4(sc, DC_RXSTART, 0xFFFFFFFF); 3764 3765 ifp->if_drv_flags |= IFF_DRV_RUNNING; 3766 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 3767 3768 dc_ifmedia_upd_locked(sc); 3769 3770 /* Clear missed frames and overflow counter. */ 3771 CSR_READ_4(sc, DC_FRAMESDISCARDED); 3772 3773 /* Don't start the ticker if this is a homePNA link. */ 3774 if (IFM_SUBTYPE(mii->mii_media.ifm_media) == IFM_HPNA_1) 3775 sc->dc_link = 1; 3776 else { 3777 if (sc->dc_flags & DC_21143_NWAY) 3778 callout_reset(&sc->dc_stat_ch, hz/10, dc_tick, sc); 3779 else 3780 callout_reset(&sc->dc_stat_ch, hz, dc_tick, sc); 3781 } 3782 3783 sc->dc_wdog_timer = 0; 3784 callout_reset(&sc->dc_wdog_ch, hz, dc_watchdog, sc); 3785 } 3786 3787 /* 3788 * Set media options. 3789 */ 3790 static int 3791 dc_ifmedia_upd(struct ifnet *ifp) 3792 { 3793 struct dc_softc *sc; 3794 int error; 3795 3796 sc = ifp->if_softc; 3797 DC_LOCK(sc); 3798 error = dc_ifmedia_upd_locked(sc); 3799 DC_UNLOCK(sc); 3800 return (error); 3801 } 3802 3803 static int 3804 dc_ifmedia_upd_locked(struct dc_softc *sc) 3805 { 3806 struct mii_data *mii; 3807 struct ifmedia *ifm; 3808 int error; 3809 3810 DC_LOCK_ASSERT(sc); 3811 3812 sc->dc_link = 0; 3813 mii = device_get_softc(sc->dc_miibus); 3814 error = mii_mediachg(mii); 3815 if (error == 0) { 3816 ifm = &mii->mii_media; 3817 if (DC_IS_INTEL(sc)) 3818 dc_setcfg(sc, ifm->ifm_media); 3819 else if (DC_IS_DAVICOM(sc) && 3820 IFM_SUBTYPE(ifm->ifm_media) == IFM_HPNA_1) 3821 dc_setcfg(sc, ifm->ifm_media); 3822 } 3823 3824 return (error); 3825 } 3826 3827 /* 3828 * Report current media status. 3829 */ 3830 static void 3831 dc_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 3832 { 3833 struct dc_softc *sc; 3834 struct mii_data *mii; 3835 struct ifmedia *ifm; 3836 3837 sc = ifp->if_softc; 3838 mii = device_get_softc(sc->dc_miibus); 3839 DC_LOCK(sc); 3840 mii_pollstat(mii); 3841 ifm = &mii->mii_media; 3842 if (DC_IS_DAVICOM(sc)) { 3843 if (IFM_SUBTYPE(ifm->ifm_media) == IFM_HPNA_1) { 3844 ifmr->ifm_active = ifm->ifm_media; 3845 ifmr->ifm_status = 0; 3846 DC_UNLOCK(sc); 3847 return; 3848 } 3849 } 3850 ifmr->ifm_active = mii->mii_media_active; 3851 ifmr->ifm_status = mii->mii_media_status; 3852 DC_UNLOCK(sc); 3853 } 3854 3855 static int 3856 dc_ioctl(struct ifnet *ifp, u_long command, caddr_t data) 3857 { 3858 struct dc_softc *sc = ifp->if_softc; 3859 struct ifreq *ifr = (struct ifreq *)data; 3860 struct mii_data *mii; 3861 int error = 0; 3862 3863 switch (command) { 3864 case SIOCSIFFLAGS: 3865 DC_LOCK(sc); 3866 if (ifp->if_flags & IFF_UP) { 3867 int need_setfilt = (ifp->if_flags ^ sc->dc_if_flags) & 3868 (IFF_PROMISC | IFF_ALLMULTI); 3869 3870 if (ifp->if_drv_flags & IFF_DRV_RUNNING) { 3871 if (need_setfilt) 3872 dc_setfilt(sc); 3873 } else { 3874 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 3875 dc_init_locked(sc); 3876 } 3877 } else { 3878 if (ifp->if_drv_flags & IFF_DRV_RUNNING) 3879 dc_stop(sc); 3880 } 3881 sc->dc_if_flags = ifp->if_flags; 3882 DC_UNLOCK(sc); 3883 break; 3884 case SIOCADDMULTI: 3885 case SIOCDELMULTI: 3886 DC_LOCK(sc); 3887 if (ifp->if_drv_flags & IFF_DRV_RUNNING) 3888 dc_setfilt(sc); 3889 DC_UNLOCK(sc); 3890 break; 3891 case SIOCGIFMEDIA: 3892 case SIOCSIFMEDIA: 3893 mii = device_get_softc(sc->dc_miibus); 3894 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 3895 break; 3896 case SIOCSIFCAP: 3897 #ifdef DEVICE_POLLING 3898 if (ifr->ifr_reqcap & IFCAP_POLLING && 3899 !(ifp->if_capenable & IFCAP_POLLING)) { 3900 error = ether_poll_register(dc_poll, ifp); 3901 if (error) 3902 return(error); 3903 DC_LOCK(sc); 3904 /* Disable interrupts */ 3905 CSR_WRITE_4(sc, DC_IMR, 0x00000000); 3906 ifp->if_capenable |= IFCAP_POLLING; 3907 DC_UNLOCK(sc); 3908 return (error); 3909 } 3910 if (!(ifr->ifr_reqcap & IFCAP_POLLING) && 3911 ifp->if_capenable & IFCAP_POLLING) { 3912 error = ether_poll_deregister(ifp); 3913 /* Enable interrupts. */ 3914 DC_LOCK(sc); 3915 CSR_WRITE_4(sc, DC_IMR, DC_INTRS); 3916 ifp->if_capenable &= ~IFCAP_POLLING; 3917 DC_UNLOCK(sc); 3918 return (error); 3919 } 3920 #endif /* DEVICE_POLLING */ 3921 break; 3922 default: 3923 error = ether_ioctl(ifp, command, data); 3924 break; 3925 } 3926 3927 return (error); 3928 } 3929 3930 static void 3931 dc_watchdog(void *xsc) 3932 { 3933 struct dc_softc *sc = xsc; 3934 struct ifnet *ifp; 3935 3936 DC_LOCK_ASSERT(sc); 3937 3938 if (sc->dc_wdog_timer == 0 || --sc->dc_wdog_timer != 0) { 3939 callout_reset(&sc->dc_wdog_ch, hz, dc_watchdog, sc); 3940 return; 3941 } 3942 3943 ifp = sc->dc_ifp; 3944 if_inc_counter(ifp, IFCOUNTER_OERRORS, 1); 3945 device_printf(sc->dc_dev, "watchdog timeout\n"); 3946 3947 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 3948 dc_init_locked(sc); 3949 3950 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 3951 dc_start_locked(ifp); 3952 } 3953 3954 /* 3955 * Stop the adapter and free any mbufs allocated to the 3956 * RX and TX lists. 3957 */ 3958 static void 3959 dc_stop(struct dc_softc *sc) 3960 { 3961 struct ifnet *ifp; 3962 struct dc_list_data *ld; 3963 struct dc_chain_data *cd; 3964 int i; 3965 uint32_t ctl, netcfg; 3966 3967 DC_LOCK_ASSERT(sc); 3968 3969 ifp = sc->dc_ifp; 3970 ld = &sc->dc_ldata; 3971 cd = &sc->dc_cdata; 3972 3973 callout_stop(&sc->dc_stat_ch); 3974 callout_stop(&sc->dc_wdog_ch); 3975 sc->dc_wdog_timer = 0; 3976 sc->dc_link = 0; 3977 3978 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE); 3979 3980 netcfg = CSR_READ_4(sc, DC_NETCFG); 3981 if (netcfg & (DC_NETCFG_RX_ON | DC_NETCFG_TX_ON)) 3982 CSR_WRITE_4(sc, DC_NETCFG, 3983 netcfg & ~(DC_NETCFG_RX_ON | DC_NETCFG_TX_ON)); 3984 CSR_WRITE_4(sc, DC_IMR, 0x00000000); 3985 /* Wait the completion of TX/RX SM. */ 3986 if (netcfg & (DC_NETCFG_RX_ON | DC_NETCFG_TX_ON)) 3987 dc_netcfg_wait(sc); 3988 3989 CSR_WRITE_4(sc, DC_TXADDR, 0x00000000); 3990 CSR_WRITE_4(sc, DC_RXADDR, 0x00000000); 3991 3992 /* 3993 * Free data in the RX lists. 3994 */ 3995 for (i = 0; i < DC_RX_LIST_CNT; i++) { 3996 if (cd->dc_rx_chain[i] != NULL) { 3997 bus_dmamap_sync(sc->dc_rx_mtag, 3998 cd->dc_rx_map[i], BUS_DMASYNC_POSTREAD); 3999 bus_dmamap_unload(sc->dc_rx_mtag, 4000 cd->dc_rx_map[i]); 4001 m_freem(cd->dc_rx_chain[i]); 4002 cd->dc_rx_chain[i] = NULL; 4003 } 4004 } 4005 bzero(ld->dc_rx_list, DC_RX_LIST_SZ); 4006 bus_dmamap_sync(sc->dc_rx_ltag, sc->dc_rx_lmap, 4007 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 4008 4009 /* 4010 * Free the TX list buffers. 4011 */ 4012 for (i = 0; i < DC_TX_LIST_CNT; i++) { 4013 if (cd->dc_tx_chain[i] != NULL) { 4014 ctl = le32toh(ld->dc_tx_list[i].dc_ctl); 4015 if (ctl & DC_TXCTL_SETUP) { 4016 bus_dmamap_sync(sc->dc_stag, sc->dc_smap, 4017 BUS_DMASYNC_POSTWRITE); 4018 } else { 4019 bus_dmamap_sync(sc->dc_tx_mtag, 4020 cd->dc_tx_map[i], BUS_DMASYNC_POSTWRITE); 4021 bus_dmamap_unload(sc->dc_tx_mtag, 4022 cd->dc_tx_map[i]); 4023 m_freem(cd->dc_tx_chain[i]); 4024 } 4025 cd->dc_tx_chain[i] = NULL; 4026 } 4027 } 4028 bzero(ld->dc_tx_list, DC_TX_LIST_SZ); 4029 bus_dmamap_sync(sc->dc_tx_ltag, sc->dc_tx_lmap, 4030 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 4031 } 4032 4033 /* 4034 * Device suspend routine. Stop the interface and save some PCI 4035 * settings in case the BIOS doesn't restore them properly on 4036 * resume. 4037 */ 4038 static int 4039 dc_suspend(device_t dev) 4040 { 4041 struct dc_softc *sc; 4042 4043 sc = device_get_softc(dev); 4044 DC_LOCK(sc); 4045 dc_stop(sc); 4046 sc->suspended = 1; 4047 DC_UNLOCK(sc); 4048 4049 return (0); 4050 } 4051 4052 /* 4053 * Device resume routine. Restore some PCI settings in case the BIOS 4054 * doesn't, re-enable busmastering, and restart the interface if 4055 * appropriate. 4056 */ 4057 static int 4058 dc_resume(device_t dev) 4059 { 4060 struct dc_softc *sc; 4061 struct ifnet *ifp; 4062 4063 sc = device_get_softc(dev); 4064 ifp = sc->dc_ifp; 4065 4066 /* reinitialize interface if necessary */ 4067 DC_LOCK(sc); 4068 if (ifp->if_flags & IFF_UP) 4069 dc_init_locked(sc); 4070 4071 sc->suspended = 0; 4072 DC_UNLOCK(sc); 4073 4074 return (0); 4075 } 4076 4077 /* 4078 * Stop all chip I/O so that the kernel's probe routines don't 4079 * get confused by errant DMAs when rebooting. 4080 */ 4081 static int 4082 dc_shutdown(device_t dev) 4083 { 4084 struct dc_softc *sc; 4085 4086 sc = device_get_softc(dev); 4087 4088 DC_LOCK(sc); 4089 dc_stop(sc); 4090 DC_UNLOCK(sc); 4091 4092 return (0); 4093 } 4094 4095 static int 4096 dc_check_multiport(struct dc_softc *sc) 4097 { 4098 struct dc_softc *dsc; 4099 devclass_t dc; 4100 device_t child; 4101 uint8_t *eaddr; 4102 int unit; 4103 4104 dc = devclass_find("dc"); 4105 for (unit = 0; unit < devclass_get_maxunit(dc); unit++) { 4106 child = devclass_get_device(dc, unit); 4107 if (child == NULL) 4108 continue; 4109 if (child == sc->dc_dev) 4110 continue; 4111 if (device_get_parent(child) != device_get_parent(sc->dc_dev)) 4112 continue; 4113 if (unit > device_get_unit(sc->dc_dev)) 4114 continue; 4115 if (device_is_attached(child) == 0) 4116 continue; 4117 dsc = device_get_softc(child); 4118 device_printf(sc->dc_dev, 4119 "Using station address of %s as base\n", 4120 device_get_nameunit(child)); 4121 bcopy(dsc->dc_eaddr, sc->dc_eaddr, ETHER_ADDR_LEN); 4122 eaddr = (uint8_t *)sc->dc_eaddr; 4123 eaddr[5]++; 4124 /* Prepare SROM to parse again. */ 4125 if (DC_IS_INTEL(sc) && dsc->dc_srom != NULL && 4126 sc->dc_romwidth != 0) { 4127 free(sc->dc_srom, M_DEVBUF); 4128 sc->dc_romwidth = dsc->dc_romwidth; 4129 sc->dc_srom = malloc(DC_ROM_SIZE(sc->dc_romwidth), 4130 M_DEVBUF, M_NOWAIT); 4131 if (sc->dc_srom == NULL) { 4132 device_printf(sc->dc_dev, 4133 "Could not allocate SROM buffer\n"); 4134 return (ENOMEM); 4135 } 4136 bcopy(dsc->dc_srom, sc->dc_srom, 4137 DC_ROM_SIZE(sc->dc_romwidth)); 4138 } 4139 return (0); 4140 } 4141 return (ENOENT); 4142 } 4143