1 /* 2 * Copyright (c) 1997, 1998, 1999 3 * Bill Paul <wpaul@ee.columbia.edu>. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 3. All advertising materials mentioning features or use of this software 14 * must display the following acknowledgement: 15 * This product includes software developed by Bill Paul. 16 * 4. Neither the name of the author nor the names of any co-contributors 17 * may be used to endorse or promote products derived from this software 18 * without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30 * THE POSSIBILITY OF SUCH DAMAGE. 31 * 32 * $FreeBSD$ 33 */ 34 35 /* 36 * DEC "tulip" clone ethernet driver. Supports the DEC/Intel 21143 37 * series chips and several workalikes including the following: 38 * 39 * Macronix 98713/98715/98725/98727/98732 PMAC (www.macronix.com) 40 * Macronix/Lite-On 82c115 PNIC II (www.macronix.com) 41 * Lite-On 82c168/82c169 PNIC (www.litecom.com) 42 * ASIX Electronics AX88140A (www.asix.com.tw) 43 * ASIX Electronics AX88141 (www.asix.com.tw) 44 * ADMtek AL981 (www.admtek.com.tw) 45 * ADMtek AN985 (www.admtek.com.tw) 46 * Davicom DM9100, DM9102, DM9102A (www.davicom8.com) 47 * Accton EN1217 (www.accton.com) 48 * Xircom X3201 (www.xircom.com) 49 * Abocom FE2500 50 * Conexant LANfinity (www.conexant.com) 51 * 52 * Datasheets for the 21143 are available at developer.intel.com. 53 * Datasheets for the clone parts can be found at their respective sites. 54 * (Except for the PNIC; see www.freebsd.org/~wpaul/PNIC/pnic.ps.gz.) 55 * The PNIC II is essentially a Macronix 98715A chip; the only difference 56 * worth noting is that its multicast hash table is only 128 bits wide 57 * instead of 512. 58 * 59 * Written by Bill Paul <wpaul@ee.columbia.edu> 60 * Electrical Engineering Department 61 * Columbia University, New York City 62 */ 63 64 /* 65 * The Intel 21143 is the successor to the DEC 21140. It is basically 66 * the same as the 21140 but with a few new features. The 21143 supports 67 * three kinds of media attachments: 68 * 69 * o MII port, for 10Mbps and 100Mbps support and NWAY 70 * autonegotiation provided by an external PHY. 71 * o SYM port, for symbol mode 100Mbps support. 72 * o 10baseT port. 73 * o AUI/BNC port. 74 * 75 * The 100Mbps SYM port and 10baseT port can be used together in 76 * combination with the internal NWAY support to create a 10/100 77 * autosensing configuration. 78 * 79 * Note that not all tulip workalikes are handled in this driver: we only 80 * deal with those which are relatively well behaved. The Winbond is 81 * handled separately due to its different register offsets and the 82 * special handling needed for its various bugs. The PNIC is handled 83 * here, but I'm not thrilled about it. 84 * 85 * All of the workalike chips use some form of MII transceiver support 86 * with the exception of the Macronix chips, which also have a SYM port. 87 * The ASIX AX88140A is also documented to have a SYM port, but all 88 * the cards I've seen use an MII transceiver, probably because the 89 * AX88140A doesn't support internal NWAY. 90 */ 91 92 #include <sys/param.h> 93 #include <sys/systm.h> 94 #include <sys/sockio.h> 95 #include <sys/mbuf.h> 96 #include <sys/malloc.h> 97 #include <sys/kernel.h> 98 #include <sys/socket.h> 99 #include <sys/sysctl.h> 100 101 #include <net/if.h> 102 #include <net/if_arp.h> 103 #include <net/ethernet.h> 104 #include <net/if_dl.h> 105 #include <net/if_media.h> 106 #include <net/if_types.h> 107 #include <net/if_vlan_var.h> 108 109 #include <net/bpf.h> 110 111 #include <vm/vm.h> /* for vtophys */ 112 #include <vm/pmap.h> /* for vtophys */ 113 #include <machine/bus_pio.h> 114 #include <machine/bus_memio.h> 115 #include <machine/bus.h> 116 #include <machine/resource.h> 117 #include <sys/bus.h> 118 #include <sys/rman.h> 119 120 #include <dev/mii/mii.h> 121 #include <dev/mii/miivar.h> 122 123 #include <pci/pcireg.h> 124 #include <pci/pcivar.h> 125 126 #define DC_USEIOSPACE 127 #ifdef __alpha__ 128 #define SRM_MEDIA 129 #endif 130 131 #include <pci/if_dcreg.h> 132 133 MODULE_DEPEND(dc, miibus, 1, 1, 1); 134 135 /* "controller miibus0" required. See GENERIC if you get errors here. */ 136 #include "miibus_if.h" 137 138 #ifndef lint 139 static const char rcsid[] = 140 "$FreeBSD$"; 141 #endif 142 143 /* 144 * Various supported device vendors/types and their names. 145 */ 146 static struct dc_type dc_devs[] = { 147 { DC_VENDORID_DEC, DC_DEVICEID_21143, 148 "Intel 21143 10/100BaseTX" }, 149 { DC_VENDORID_DAVICOM, DC_DEVICEID_DM9100, 150 "Davicom DM9100 10/100BaseTX" }, 151 { DC_VENDORID_DAVICOM, DC_DEVICEID_DM9102, 152 "Davicom DM9102 10/100BaseTX" }, 153 { DC_VENDORID_DAVICOM, DC_DEVICEID_DM9102, 154 "Davicom DM9102A 10/100BaseTX" }, 155 { DC_VENDORID_ADMTEK, DC_DEVICEID_AL981, 156 "ADMtek AL981 10/100BaseTX" }, 157 { DC_VENDORID_ADMTEK, DC_DEVICEID_AN985, 158 "ADMtek AN985 10/100BaseTX" }, 159 { DC_VENDORID_ASIX, DC_DEVICEID_AX88140A, 160 "ASIX AX88140A 10/100BaseTX" }, 161 { DC_VENDORID_ASIX, DC_DEVICEID_AX88140A, 162 "ASIX AX88141 10/100BaseTX" }, 163 { DC_VENDORID_MX, DC_DEVICEID_98713, 164 "Macronix 98713 10/100BaseTX" }, 165 { DC_VENDORID_MX, DC_DEVICEID_98713, 166 "Macronix 98713A 10/100BaseTX" }, 167 { DC_VENDORID_CP, DC_DEVICEID_98713_CP, 168 "Compex RL100-TX 10/100BaseTX" }, 169 { DC_VENDORID_CP, DC_DEVICEID_98713_CP, 170 "Compex RL100-TX 10/100BaseTX" }, 171 { DC_VENDORID_MX, DC_DEVICEID_987x5, 172 "Macronix 98715/98715A 10/100BaseTX" }, 173 { DC_VENDORID_MX, DC_DEVICEID_987x5, 174 "Macronix 98715AEC-C 10/100BaseTX" }, 175 { DC_VENDORID_MX, DC_DEVICEID_987x5, 176 "Macronix 98725 10/100BaseTX" }, 177 { DC_VENDORID_MX, DC_DEVICEID_98727, 178 "Macronix 98727/98732 10/100BaseTX" }, 179 { DC_VENDORID_LO, DC_DEVICEID_82C115, 180 "LC82C115 PNIC II 10/100BaseTX" }, 181 { DC_VENDORID_LO, DC_DEVICEID_82C168, 182 "82c168 PNIC 10/100BaseTX" }, 183 { DC_VENDORID_LO, DC_DEVICEID_82C168, 184 "82c169 PNIC 10/100BaseTX" }, 185 { DC_VENDORID_ACCTON, DC_DEVICEID_EN1217, 186 "Accton EN1217 10/100BaseTX" }, 187 { DC_VENDORID_ACCTON, DC_DEVICEID_EN2242, 188 "Accton EN2242 MiniPCI 10/100BaseTX" }, 189 { DC_VENDORID_XIRCOM, DC_DEVICEID_X3201, 190 "Xircom X3201 10/100BaseTX" }, 191 { DC_VENDORID_ABOCOM, DC_DEVICEID_FE2500, 192 "Abocom FE2500 10/100BaseTX" }, 193 { DC_VENDORID_CONEXANT, DC_DEVICEID_RS7112, 194 "Conexant LANfinity MiniPCI 10/100BaseTX" }, 195 { 0, 0, NULL } 196 }; 197 198 static int dc_probe __P((device_t)); 199 static int dc_attach __P((device_t)); 200 static int dc_detach __P((device_t)); 201 static void dc_acpi __P((device_t)); 202 static struct dc_type *dc_devtype __P((device_t)); 203 static int dc_newbuf __P((struct dc_softc *, int, struct mbuf *)); 204 static int dc_encap __P((struct dc_softc *, struct mbuf *, 205 u_int32_t *)); 206 static int dc_coal __P((struct dc_softc *, struct mbuf **)); 207 static void dc_pnic_rx_bug_war __P((struct dc_softc *, int)); 208 static int dc_rx_resync __P((struct dc_softc *)); 209 static void dc_rxeof __P((struct dc_softc *)); 210 static void dc_txeof __P((struct dc_softc *)); 211 static void dc_tick __P((void *)); 212 static void dc_tx_underrun __P((struct dc_softc *)); 213 static void dc_intr __P((void *)); 214 static void dc_start __P((struct ifnet *)); 215 static int dc_ioctl __P((struct ifnet *, u_long, caddr_t)); 216 static void dc_init __P((void *)); 217 static void dc_stop __P((struct dc_softc *)); 218 static void dc_watchdog __P((struct ifnet *)); 219 static void dc_shutdown __P((device_t)); 220 static int dc_ifmedia_upd __P((struct ifnet *)); 221 static void dc_ifmedia_sts __P((struct ifnet *, struct ifmediareq *)); 222 223 static void dc_delay __P((struct dc_softc *)); 224 static void dc_eeprom_idle __P((struct dc_softc *)); 225 static void dc_eeprom_putbyte __P((struct dc_softc *, int)); 226 static void dc_eeprom_getword __P((struct dc_softc *, int, u_int16_t *)); 227 static void dc_eeprom_getword_pnic 228 __P((struct dc_softc *, int, u_int16_t *)); 229 static void dc_eeprom_getword_xircom 230 __P((struct dc_softc *, int, u_int16_t *)); 231 static void dc_read_eeprom __P((struct dc_softc *, caddr_t, int, 232 int, int)); 233 234 static void dc_mii_writebit __P((struct dc_softc *, int)); 235 static int dc_mii_readbit __P((struct dc_softc *)); 236 static void dc_mii_sync __P((struct dc_softc *)); 237 static void dc_mii_send __P((struct dc_softc *, u_int32_t, int)); 238 static int dc_mii_readreg __P((struct dc_softc *, struct dc_mii_frame *)); 239 static int dc_mii_writereg __P((struct dc_softc *, struct dc_mii_frame *)); 240 static int dc_miibus_readreg __P((device_t, int, int)); 241 static int dc_miibus_writereg __P((device_t, int, int, int)); 242 static void dc_miibus_statchg __P((device_t)); 243 static void dc_miibus_mediainit __P((device_t)); 244 245 static void dc_setcfg __P((struct dc_softc *, int)); 246 static u_int32_t dc_crc_le __P((struct dc_softc *, caddr_t)); 247 static u_int32_t dc_crc_be __P((caddr_t)); 248 static void dc_setfilt_21143 __P((struct dc_softc *)); 249 static void dc_setfilt_asix __P((struct dc_softc *)); 250 static void dc_setfilt_admtek __P((struct dc_softc *)); 251 static void dc_setfilt_xircom __P((struct dc_softc *)); 252 253 static void dc_setfilt __P((struct dc_softc *)); 254 255 static void dc_reset __P((struct dc_softc *)); 256 static int dc_list_rx_init __P((struct dc_softc *)); 257 static int dc_list_tx_init __P((struct dc_softc *)); 258 259 static void dc_parse_21143_srom __P((struct dc_softc *)); 260 static void dc_decode_leaf_sia __P((struct dc_softc *, 261 struct dc_eblock_sia *)); 262 static void dc_decode_leaf_mii __P((struct dc_softc *, 263 struct dc_eblock_mii *)); 264 static void dc_decode_leaf_sym __P((struct dc_softc *, 265 struct dc_eblock_sym *)); 266 static void dc_apply_fixup __P((struct dc_softc *, int)); 267 268 #ifdef DC_USEIOSPACE 269 #define DC_RES SYS_RES_IOPORT 270 #define DC_RID DC_PCI_CFBIO 271 #else 272 #define DC_RES SYS_RES_MEMORY 273 #define DC_RID DC_PCI_CFBMA 274 #endif 275 276 static device_method_t dc_methods[] = { 277 /* Device interface */ 278 DEVMETHOD(device_probe, dc_probe), 279 DEVMETHOD(device_attach, dc_attach), 280 DEVMETHOD(device_detach, dc_detach), 281 DEVMETHOD(device_shutdown, dc_shutdown), 282 283 /* bus interface */ 284 DEVMETHOD(bus_print_child, bus_generic_print_child), 285 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 286 287 /* MII interface */ 288 DEVMETHOD(miibus_readreg, dc_miibus_readreg), 289 DEVMETHOD(miibus_writereg, dc_miibus_writereg), 290 DEVMETHOD(miibus_statchg, dc_miibus_statchg), 291 DEVMETHOD(miibus_mediainit, dc_miibus_mediainit), 292 293 { 0, 0 } 294 }; 295 296 static driver_t dc_driver = { 297 "dc", 298 dc_methods, 299 sizeof(struct dc_softc) 300 }; 301 302 static devclass_t dc_devclass; 303 #ifdef __i386__ 304 static int dc_quick=1; 305 SYSCTL_INT(_hw, OID_AUTO, dc_quick, CTLFLAG_RW, 306 &dc_quick,0,"do not mdevget in dc driver"); 307 #endif 308 309 DRIVER_MODULE(if_dc, cardbus, dc_driver, dc_devclass, 0, 0); 310 DRIVER_MODULE(if_dc, pci, dc_driver, dc_devclass, 0, 0); 311 DRIVER_MODULE(miibus, dc, miibus_driver, miibus_devclass, 0, 0); 312 313 #define DC_SETBIT(sc, reg, x) \ 314 CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) | (x)) 315 316 #define DC_CLRBIT(sc, reg, x) \ 317 CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) & ~(x)) 318 319 #define SIO_SET(x) DC_SETBIT(sc, DC_SIO, (x)) 320 #define SIO_CLR(x) DC_CLRBIT(sc, DC_SIO, (x)) 321 322 #define IS_MPSAFE 0 323 324 static void dc_delay(sc) 325 struct dc_softc *sc; 326 { 327 int idx; 328 329 for (idx = (300 / 33) + 1; idx > 0; idx--) 330 CSR_READ_4(sc, DC_BUSCTL); 331 } 332 333 static void dc_eeprom_idle(sc) 334 struct dc_softc *sc; 335 { 336 register int i; 337 338 CSR_WRITE_4(sc, DC_SIO, DC_SIO_EESEL); 339 dc_delay(sc); 340 DC_SETBIT(sc, DC_SIO, DC_SIO_ROMCTL_READ); 341 dc_delay(sc); 342 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); 343 dc_delay(sc); 344 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CS); 345 dc_delay(sc); 346 347 for (i = 0; i < 25; i++) { 348 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); 349 dc_delay(sc); 350 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CLK); 351 dc_delay(sc); 352 } 353 354 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); 355 dc_delay(sc); 356 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CS); 357 dc_delay(sc); 358 CSR_WRITE_4(sc, DC_SIO, 0x00000000); 359 360 return; 361 } 362 363 /* 364 * Send a read command and address to the EEPROM, check for ACK. 365 */ 366 static void dc_eeprom_putbyte(sc, addr) 367 struct dc_softc *sc; 368 int addr; 369 { 370 register int d, i; 371 372 /* 373 * The AN985 has a 93C66 EEPROM on it instead of 374 * a 93C46. It uses a different bit sequence for 375 * specifying the "read" opcode. 376 */ 377 if (DC_IS_CENTAUR(sc) || DC_IS_CONEXANT(sc)) 378 d = addr | (DC_EECMD_READ << 2); 379 else 380 d = addr | DC_EECMD_READ; 381 382 /* 383 * Feed in each bit and strobe the clock. 384 */ 385 for (i = 0x400; i; i >>= 1) { 386 if (d & i) { 387 SIO_SET(DC_SIO_EE_DATAIN); 388 } else { 389 SIO_CLR(DC_SIO_EE_DATAIN); 390 } 391 dc_delay(sc); 392 SIO_SET(DC_SIO_EE_CLK); 393 dc_delay(sc); 394 SIO_CLR(DC_SIO_EE_CLK); 395 dc_delay(sc); 396 } 397 398 return; 399 } 400 401 /* 402 * Read a word of data stored in the EEPROM at address 'addr.' 403 * The PNIC 82c168/82c169 has its own non-standard way to read 404 * the EEPROM. 405 */ 406 static void dc_eeprom_getword_pnic(sc, addr, dest) 407 struct dc_softc *sc; 408 int addr; 409 u_int16_t *dest; 410 { 411 register int i; 412 u_int32_t r; 413 414 CSR_WRITE_4(sc, DC_PN_SIOCTL, DC_PN_EEOPCODE_READ|addr); 415 416 for (i = 0; i < DC_TIMEOUT; i++) { 417 DELAY(1); 418 r = CSR_READ_4(sc, DC_SIO); 419 if (!(r & DC_PN_SIOCTL_BUSY)) { 420 *dest = (u_int16_t)(r & 0xFFFF); 421 return; 422 } 423 } 424 425 return; 426 } 427 428 /* 429 * Read a word of data stored in the EEPROM at address 'addr.' 430 * The Xircom X3201 has its own non-standard way to read 431 * the EEPROM, too. 432 */ 433 static void dc_eeprom_getword_xircom(sc, addr, dest) 434 struct dc_softc *sc; 435 int addr; 436 u_int16_t *dest; 437 { 438 SIO_SET(DC_SIO_ROMSEL | DC_SIO_ROMCTL_READ); 439 440 addr *= 2; 441 CSR_WRITE_4(sc, DC_ROM, addr | 0x160); 442 *dest = (u_int16_t)CSR_READ_4(sc, DC_SIO)&0xff; 443 addr += 1; 444 CSR_WRITE_4(sc, DC_ROM, addr | 0x160); 445 *dest |= ((u_int16_t)CSR_READ_4(sc, DC_SIO)&0xff) << 8; 446 447 SIO_CLR(DC_SIO_ROMSEL | DC_SIO_ROMCTL_READ); 448 return; 449 } 450 451 /* 452 * Read a word of data stored in the EEPROM at address 'addr.' 453 */ 454 static void dc_eeprom_getword(sc, addr, dest) 455 struct dc_softc *sc; 456 int addr; 457 u_int16_t *dest; 458 { 459 register int i; 460 u_int16_t word = 0; 461 462 /* Force EEPROM to idle state. */ 463 dc_eeprom_idle(sc); 464 465 /* Enter EEPROM access mode. */ 466 CSR_WRITE_4(sc, DC_SIO, DC_SIO_EESEL); 467 dc_delay(sc); 468 DC_SETBIT(sc, DC_SIO, DC_SIO_ROMCTL_READ); 469 dc_delay(sc); 470 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); 471 dc_delay(sc); 472 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CS); 473 dc_delay(sc); 474 475 /* 476 * Send address of word we want to read. 477 */ 478 dc_eeprom_putbyte(sc, addr); 479 480 /* 481 * Start reading bits from EEPROM. 482 */ 483 for (i = 0x8000; i; i >>= 1) { 484 SIO_SET(DC_SIO_EE_CLK); 485 dc_delay(sc); 486 if (CSR_READ_4(sc, DC_SIO) & DC_SIO_EE_DATAOUT) 487 word |= i; 488 dc_delay(sc); 489 SIO_CLR(DC_SIO_EE_CLK); 490 dc_delay(sc); 491 } 492 493 /* Turn off EEPROM access mode. */ 494 dc_eeprom_idle(sc); 495 496 *dest = word; 497 498 return; 499 } 500 501 /* 502 * Read a sequence of words from the EEPROM. 503 */ 504 static void dc_read_eeprom(sc, dest, off, cnt, swap) 505 struct dc_softc *sc; 506 caddr_t dest; 507 int off; 508 int cnt; 509 int swap; 510 { 511 int i; 512 u_int16_t word = 0, *ptr; 513 514 for (i = 0; i < cnt; i++) { 515 if (DC_IS_PNIC(sc)) 516 dc_eeprom_getword_pnic(sc, off + i, &word); 517 else if (DC_IS_XIRCOM(sc)) 518 dc_eeprom_getword_xircom(sc, off + i, &word); 519 else 520 dc_eeprom_getword(sc, off + i, &word); 521 ptr = (u_int16_t *)(dest + (i * 2)); 522 if (swap) 523 *ptr = ntohs(word); 524 else 525 *ptr = word; 526 } 527 528 return; 529 } 530 531 /* 532 * The following two routines are taken from the Macronix 98713 533 * Application Notes pp.19-21. 534 */ 535 /* 536 * Write a bit to the MII bus. 537 */ 538 static void dc_mii_writebit(sc, bit) 539 struct dc_softc *sc; 540 int bit; 541 { 542 if (bit) 543 CSR_WRITE_4(sc, DC_SIO, 544 DC_SIO_ROMCTL_WRITE|DC_SIO_MII_DATAOUT); 545 else 546 CSR_WRITE_4(sc, DC_SIO, DC_SIO_ROMCTL_WRITE); 547 548 DC_SETBIT(sc, DC_SIO, DC_SIO_MII_CLK); 549 DC_CLRBIT(sc, DC_SIO, DC_SIO_MII_CLK); 550 551 return; 552 } 553 554 /* 555 * Read a bit from the MII bus. 556 */ 557 static int dc_mii_readbit(sc) 558 struct dc_softc *sc; 559 { 560 CSR_WRITE_4(sc, DC_SIO, DC_SIO_ROMCTL_READ|DC_SIO_MII_DIR); 561 CSR_READ_4(sc, DC_SIO); 562 DC_SETBIT(sc, DC_SIO, DC_SIO_MII_CLK); 563 DC_CLRBIT(sc, DC_SIO, DC_SIO_MII_CLK); 564 if (CSR_READ_4(sc, DC_SIO) & DC_SIO_MII_DATAIN) 565 return(1); 566 567 return(0); 568 } 569 570 /* 571 * Sync the PHYs by setting data bit and strobing the clock 32 times. 572 */ 573 static void dc_mii_sync(sc) 574 struct dc_softc *sc; 575 { 576 register int i; 577 578 CSR_WRITE_4(sc, DC_SIO, DC_SIO_ROMCTL_WRITE); 579 580 for (i = 0; i < 32; i++) 581 dc_mii_writebit(sc, 1); 582 583 return; 584 } 585 586 /* 587 * Clock a series of bits through the MII. 588 */ 589 static void dc_mii_send(sc, bits, cnt) 590 struct dc_softc *sc; 591 u_int32_t bits; 592 int cnt; 593 { 594 int i; 595 596 for (i = (0x1 << (cnt - 1)); i; i >>= 1) 597 dc_mii_writebit(sc, bits & i); 598 } 599 600 /* 601 * Read an PHY register through the MII. 602 */ 603 static int dc_mii_readreg(sc, frame) 604 struct dc_softc *sc; 605 struct dc_mii_frame *frame; 606 607 { 608 int i, ack; 609 610 DC_LOCK(sc); 611 612 /* 613 * Set up frame for RX. 614 */ 615 frame->mii_stdelim = DC_MII_STARTDELIM; 616 frame->mii_opcode = DC_MII_READOP; 617 frame->mii_turnaround = 0; 618 frame->mii_data = 0; 619 620 /* 621 * Sync the PHYs. 622 */ 623 dc_mii_sync(sc); 624 625 /* 626 * Send command/address info. 627 */ 628 dc_mii_send(sc, frame->mii_stdelim, 2); 629 dc_mii_send(sc, frame->mii_opcode, 2); 630 dc_mii_send(sc, frame->mii_phyaddr, 5); 631 dc_mii_send(sc, frame->mii_regaddr, 5); 632 633 #ifdef notdef 634 /* Idle bit */ 635 dc_mii_writebit(sc, 1); 636 dc_mii_writebit(sc, 0); 637 #endif 638 639 /* Check for ack */ 640 ack = dc_mii_readbit(sc); 641 642 /* 643 * Now try reading data bits. If the ack failed, we still 644 * need to clock through 16 cycles to keep the PHY(s) in sync. 645 */ 646 if (ack) { 647 for(i = 0; i < 16; i++) { 648 dc_mii_readbit(sc); 649 } 650 goto fail; 651 } 652 653 for (i = 0x8000; i; i >>= 1) { 654 if (!ack) { 655 if (dc_mii_readbit(sc)) 656 frame->mii_data |= i; 657 } 658 } 659 660 fail: 661 662 dc_mii_writebit(sc, 0); 663 dc_mii_writebit(sc, 0); 664 665 DC_UNLOCK(sc); 666 667 if (ack) 668 return(1); 669 return(0); 670 } 671 672 /* 673 * Write to a PHY register through the MII. 674 */ 675 static int dc_mii_writereg(sc, frame) 676 struct dc_softc *sc; 677 struct dc_mii_frame *frame; 678 679 { 680 DC_LOCK(sc); 681 /* 682 * Set up frame for TX. 683 */ 684 685 frame->mii_stdelim = DC_MII_STARTDELIM; 686 frame->mii_opcode = DC_MII_WRITEOP; 687 frame->mii_turnaround = DC_MII_TURNAROUND; 688 689 /* 690 * Sync the PHYs. 691 */ 692 dc_mii_sync(sc); 693 694 dc_mii_send(sc, frame->mii_stdelim, 2); 695 dc_mii_send(sc, frame->mii_opcode, 2); 696 dc_mii_send(sc, frame->mii_phyaddr, 5); 697 dc_mii_send(sc, frame->mii_regaddr, 5); 698 dc_mii_send(sc, frame->mii_turnaround, 2); 699 dc_mii_send(sc, frame->mii_data, 16); 700 701 /* Idle bit. */ 702 dc_mii_writebit(sc, 0); 703 dc_mii_writebit(sc, 0); 704 705 DC_UNLOCK(sc); 706 707 return(0); 708 } 709 710 static int dc_miibus_readreg(dev, phy, reg) 711 device_t dev; 712 int phy, reg; 713 { 714 struct dc_mii_frame frame; 715 struct dc_softc *sc; 716 int i, rval, phy_reg = 0; 717 718 sc = device_get_softc(dev); 719 bzero((char *)&frame, sizeof(frame)); 720 721 /* 722 * Note: both the AL981 and AN985 have internal PHYs, 723 * however the AL981 provides direct access to the PHY 724 * registers while the AN985 uses a serial MII interface. 725 * The AN985's MII interface is also buggy in that you 726 * can read from any MII address (0 to 31), but only address 1 727 * behaves normally. To deal with both cases, we pretend 728 * that the PHY is at MII address 1. 729 */ 730 if (DC_IS_ADMTEK(sc) && phy != DC_ADMTEK_PHYADDR) 731 return(0); 732 733 /* 734 * Note: the ukphy probes of the RS7112 report a PHY at 735 * MII address 0 (possibly HomePNA?) and 1 (ethernet) 736 * so we only respond to correct one. 737 */ 738 if (DC_IS_CONEXANT(sc) && phy != DC_CONEXANT_PHYADDR) 739 return(0); 740 741 if (sc->dc_pmode != DC_PMODE_MII) { 742 if (phy == (MII_NPHY - 1)) { 743 switch(reg) { 744 case MII_BMSR: 745 /* 746 * Fake something to make the probe 747 * code think there's a PHY here. 748 */ 749 return(BMSR_MEDIAMASK); 750 break; 751 case MII_PHYIDR1: 752 if (DC_IS_PNIC(sc)) 753 return(DC_VENDORID_LO); 754 return(DC_VENDORID_DEC); 755 break; 756 case MII_PHYIDR2: 757 if (DC_IS_PNIC(sc)) 758 return(DC_DEVICEID_82C168); 759 return(DC_DEVICEID_21143); 760 break; 761 default: 762 return(0); 763 break; 764 } 765 } else 766 return(0); 767 } 768 769 if (DC_IS_PNIC(sc)) { 770 CSR_WRITE_4(sc, DC_PN_MII, DC_PN_MIIOPCODE_READ | 771 (phy << 23) | (reg << 18)); 772 for (i = 0; i < DC_TIMEOUT; i++) { 773 DELAY(1); 774 rval = CSR_READ_4(sc, DC_PN_MII); 775 if (!(rval & DC_PN_MII_BUSY)) { 776 rval &= 0xFFFF; 777 return(rval == 0xFFFF ? 0 : rval); 778 } 779 } 780 return(0); 781 } 782 783 if (DC_IS_COMET(sc)) { 784 switch(reg) { 785 case MII_BMCR: 786 phy_reg = DC_AL_BMCR; 787 break; 788 case MII_BMSR: 789 phy_reg = DC_AL_BMSR; 790 break; 791 case MII_PHYIDR1: 792 phy_reg = DC_AL_VENID; 793 break; 794 case MII_PHYIDR2: 795 phy_reg = DC_AL_DEVID; 796 break; 797 case MII_ANAR: 798 phy_reg = DC_AL_ANAR; 799 break; 800 case MII_ANLPAR: 801 phy_reg = DC_AL_LPAR; 802 break; 803 case MII_ANER: 804 phy_reg = DC_AL_ANER; 805 break; 806 default: 807 printf("dc%d: phy_read: bad phy register %x\n", 808 sc->dc_unit, reg); 809 return(0); 810 break; 811 } 812 813 rval = CSR_READ_4(sc, phy_reg) & 0x0000FFFF; 814 815 if (rval == 0xFFFF) 816 return(0); 817 return(rval); 818 } 819 820 frame.mii_phyaddr = phy; 821 frame.mii_regaddr = reg; 822 if (sc->dc_type == DC_TYPE_98713) { 823 phy_reg = CSR_READ_4(sc, DC_NETCFG); 824 CSR_WRITE_4(sc, DC_NETCFG, phy_reg & ~DC_NETCFG_PORTSEL); 825 } 826 dc_mii_readreg(sc, &frame); 827 if (sc->dc_type == DC_TYPE_98713) 828 CSR_WRITE_4(sc, DC_NETCFG, phy_reg); 829 830 return(frame.mii_data); 831 } 832 833 static int dc_miibus_writereg(dev, phy, reg, data) 834 device_t dev; 835 int phy, reg, data; 836 { 837 struct dc_softc *sc; 838 struct dc_mii_frame frame; 839 int i, phy_reg = 0; 840 841 sc = device_get_softc(dev); 842 bzero((char *)&frame, sizeof(frame)); 843 844 if (DC_IS_ADMTEK(sc) && phy != DC_ADMTEK_PHYADDR) 845 return(0); 846 847 if (DC_IS_CONEXANT(sc) && phy != DC_CONEXANT_PHYADDR) 848 return(0); 849 850 if (DC_IS_PNIC(sc)) { 851 CSR_WRITE_4(sc, DC_PN_MII, DC_PN_MIIOPCODE_WRITE | 852 (phy << 23) | (reg << 10) | data); 853 for (i = 0; i < DC_TIMEOUT; i++) { 854 if (!(CSR_READ_4(sc, DC_PN_MII) & DC_PN_MII_BUSY)) 855 break; 856 } 857 return(0); 858 } 859 860 if (DC_IS_COMET(sc)) { 861 switch(reg) { 862 case MII_BMCR: 863 phy_reg = DC_AL_BMCR; 864 break; 865 case MII_BMSR: 866 phy_reg = DC_AL_BMSR; 867 break; 868 case MII_PHYIDR1: 869 phy_reg = DC_AL_VENID; 870 break; 871 case MII_PHYIDR2: 872 phy_reg = DC_AL_DEVID; 873 break; 874 case MII_ANAR: 875 phy_reg = DC_AL_ANAR; 876 break; 877 case MII_ANLPAR: 878 phy_reg = DC_AL_LPAR; 879 break; 880 case MII_ANER: 881 phy_reg = DC_AL_ANER; 882 break; 883 default: 884 printf("dc%d: phy_write: bad phy register %x\n", 885 sc->dc_unit, reg); 886 return(0); 887 break; 888 } 889 890 CSR_WRITE_4(sc, phy_reg, data); 891 return(0); 892 } 893 894 frame.mii_phyaddr = phy; 895 frame.mii_regaddr = reg; 896 frame.mii_data = data; 897 898 if (sc->dc_type == DC_TYPE_98713) { 899 phy_reg = CSR_READ_4(sc, DC_NETCFG); 900 CSR_WRITE_4(sc, DC_NETCFG, phy_reg & ~DC_NETCFG_PORTSEL); 901 } 902 dc_mii_writereg(sc, &frame); 903 if (sc->dc_type == DC_TYPE_98713) 904 CSR_WRITE_4(sc, DC_NETCFG, phy_reg); 905 906 return(0); 907 } 908 909 static void dc_miibus_statchg(dev) 910 device_t dev; 911 { 912 struct dc_softc *sc; 913 struct mii_data *mii; 914 struct ifmedia *ifm; 915 916 sc = device_get_softc(dev); 917 if (DC_IS_ADMTEK(sc)) 918 return; 919 920 mii = device_get_softc(sc->dc_miibus); 921 ifm = &mii->mii_media; 922 if (DC_IS_DAVICOM(sc) && 923 IFM_SUBTYPE(ifm->ifm_media) == IFM_homePNA) { 924 dc_setcfg(sc, ifm->ifm_media); 925 sc->dc_if_media = ifm->ifm_media; 926 } else { 927 dc_setcfg(sc, mii->mii_media_active); 928 sc->dc_if_media = mii->mii_media_active; 929 } 930 931 return; 932 } 933 934 /* 935 * Special support for DM9102A cards with HomePNA PHYs. Note: 936 * with the Davicom DM9102A/DM9801 eval board that I have, it seems 937 * to be impossible to talk to the management interface of the DM9801 938 * PHY (its MDIO pin is not connected to anything). Consequently, 939 * the driver has to just 'know' about the additional mode and deal 940 * with it itself. *sigh* 941 */ 942 static void dc_miibus_mediainit(dev) 943 device_t dev; 944 { 945 struct dc_softc *sc; 946 struct mii_data *mii; 947 struct ifmedia *ifm; 948 int rev; 949 950 rev = pci_read_config(dev, DC_PCI_CFRV, 4) & 0xFF; 951 952 sc = device_get_softc(dev); 953 mii = device_get_softc(sc->dc_miibus); 954 ifm = &mii->mii_media; 955 956 if (DC_IS_DAVICOM(sc) && rev >= DC_REVISION_DM9102A) 957 ifmedia_add(ifm, IFM_ETHER|IFM_homePNA, 0, NULL); 958 959 return; 960 } 961 962 #define DC_POLY 0xEDB88320 963 #define DC_BITS_512 9 964 #define DC_BITS_128 7 965 #define DC_BITS_64 6 966 967 static u_int32_t dc_crc_le(sc, addr) 968 struct dc_softc *sc; 969 caddr_t addr; 970 { 971 u_int32_t idx, bit, data, crc; 972 973 /* Compute CRC for the address value. */ 974 crc = 0xFFFFFFFF; /* initial value */ 975 976 for (idx = 0; idx < 6; idx++) { 977 for (data = *addr++, bit = 0; bit < 8; bit++, data >>= 1) 978 crc = (crc >> 1) ^ (((crc ^ data) & 1) ? DC_POLY : 0); 979 } 980 981 /* 982 * The hash table on the PNIC II and the MX98715AEC-C/D/E 983 * chips is only 128 bits wide. 984 */ 985 if (sc->dc_flags & DC_128BIT_HASH) 986 return (crc & ((1 << DC_BITS_128) - 1)); 987 988 /* The hash table on the MX98715BEC is only 64 bits wide. */ 989 if (sc->dc_flags & DC_64BIT_HASH) 990 return (crc & ((1 << DC_BITS_64) - 1)); 991 992 /* Xircom's hash filtering table is different (read: weird) */ 993 /* Xircom uses the LEAST significant bits */ 994 if (DC_IS_XIRCOM(sc)) { 995 if ((crc & 0x180) == 0x180) 996 return (crc & 0x0F) + (crc & 0x70)*3 + (14 << 4); 997 else 998 return (crc & 0x1F) + ((crc>>1) & 0xF0)*3 + (12 << 4); 999 } 1000 1001 return (crc & ((1 << DC_BITS_512) - 1)); 1002 } 1003 1004 /* 1005 * Calculate CRC of a multicast group address, return the lower 6 bits. 1006 */ 1007 static u_int32_t dc_crc_be(addr) 1008 caddr_t addr; 1009 { 1010 u_int32_t crc, carry; 1011 int i, j; 1012 u_int8_t c; 1013 1014 /* Compute CRC for the address value. */ 1015 crc = 0xFFFFFFFF; /* initial value */ 1016 1017 for (i = 0; i < 6; i++) { 1018 c = *(addr + i); 1019 for (j = 0; j < 8; j++) { 1020 carry = ((crc & 0x80000000) ? 1 : 0) ^ (c & 0x01); 1021 crc <<= 1; 1022 c >>= 1; 1023 if (carry) 1024 crc = (crc ^ 0x04c11db6) | carry; 1025 } 1026 } 1027 1028 /* return the filter bit position */ 1029 return((crc >> 26) & 0x0000003F); 1030 } 1031 1032 /* 1033 * 21143-style RX filter setup routine. Filter programming is done by 1034 * downloading a special setup frame into the TX engine. 21143, Macronix, 1035 * PNIC, PNIC II and Davicom chips are programmed this way. 1036 * 1037 * We always program the chip using 'hash perfect' mode, i.e. one perfect 1038 * address (our node address) and a 512-bit hash filter for multicast 1039 * frames. We also sneak the broadcast address into the hash filter since 1040 * we need that too. 1041 */ 1042 void dc_setfilt_21143(sc) 1043 struct dc_softc *sc; 1044 { 1045 struct dc_desc *sframe; 1046 u_int32_t h, *sp; 1047 struct ifmultiaddr *ifma; 1048 struct ifnet *ifp; 1049 int i; 1050 1051 ifp = &sc->arpcom.ac_if; 1052 1053 i = sc->dc_cdata.dc_tx_prod; 1054 DC_INC(sc->dc_cdata.dc_tx_prod, DC_TX_LIST_CNT); 1055 sc->dc_cdata.dc_tx_cnt++; 1056 sframe = &sc->dc_ldata->dc_tx_list[i]; 1057 sp = (u_int32_t *)&sc->dc_cdata.dc_sbuf; 1058 bzero((char *)sp, DC_SFRAME_LEN); 1059 1060 sframe->dc_data = vtophys(&sc->dc_cdata.dc_sbuf); 1061 sframe->dc_ctl = DC_SFRAME_LEN | DC_TXCTL_SETUP | DC_TXCTL_TLINK | 1062 DC_FILTER_HASHPERF | DC_TXCTL_FINT; 1063 1064 sc->dc_cdata.dc_tx_chain[i] = (struct mbuf *)&sc->dc_cdata.dc_sbuf; 1065 1066 /* If we want promiscuous mode, set the allframes bit. */ 1067 if (ifp->if_flags & IFF_PROMISC) 1068 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC); 1069 else 1070 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC); 1071 1072 if (ifp->if_flags & IFF_ALLMULTI) 1073 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI); 1074 else 1075 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI); 1076 1077 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 1078 if (ifma->ifma_addr->sa_family != AF_LINK) 1079 continue; 1080 h = dc_crc_le(sc, 1081 LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 1082 sp[h >> 4] |= 1 << (h & 0xF); 1083 } 1084 1085 if (ifp->if_flags & IFF_BROADCAST) { 1086 h = dc_crc_le(sc, (caddr_t)ðerbroadcastaddr); 1087 sp[h >> 4] |= 1 << (h & 0xF); 1088 } 1089 1090 /* Set our MAC address */ 1091 sp[39] = ((u_int16_t *)sc->arpcom.ac_enaddr)[0]; 1092 sp[40] = ((u_int16_t *)sc->arpcom.ac_enaddr)[1]; 1093 sp[41] = ((u_int16_t *)sc->arpcom.ac_enaddr)[2]; 1094 1095 sframe->dc_status = DC_TXSTAT_OWN; 1096 CSR_WRITE_4(sc, DC_TXSTART, 0xFFFFFFFF); 1097 1098 /* 1099 * The PNIC takes an exceedingly long time to process its 1100 * setup frame; wait 10ms after posting the setup frame 1101 * before proceeding, just so it has time to swallow its 1102 * medicine. 1103 */ 1104 DELAY(10000); 1105 1106 ifp->if_timer = 5; 1107 1108 return; 1109 } 1110 1111 void dc_setfilt_admtek(sc) 1112 struct dc_softc *sc; 1113 { 1114 struct ifnet *ifp; 1115 int h = 0; 1116 u_int32_t hashes[2] = { 0, 0 }; 1117 struct ifmultiaddr *ifma; 1118 1119 ifp = &sc->arpcom.ac_if; 1120 1121 /* Init our MAC address */ 1122 CSR_WRITE_4(sc, DC_AL_PAR0, *(u_int32_t *)(&sc->arpcom.ac_enaddr[0])); 1123 CSR_WRITE_4(sc, DC_AL_PAR1, *(u_int32_t *)(&sc->arpcom.ac_enaddr[4])); 1124 1125 /* If we want promiscuous mode, set the allframes bit. */ 1126 if (ifp->if_flags & IFF_PROMISC) 1127 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC); 1128 else 1129 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC); 1130 1131 if (ifp->if_flags & IFF_ALLMULTI) 1132 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI); 1133 else 1134 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI); 1135 1136 /* first, zot all the existing hash bits */ 1137 CSR_WRITE_4(sc, DC_AL_MAR0, 0); 1138 CSR_WRITE_4(sc, DC_AL_MAR1, 0); 1139 1140 /* 1141 * If we're already in promisc or allmulti mode, we 1142 * don't have to bother programming the multicast filter. 1143 */ 1144 if (ifp->if_flags & (IFF_PROMISC|IFF_ALLMULTI)) 1145 return; 1146 1147 /* now program new ones */ 1148 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 1149 if (ifma->ifma_addr->sa_family != AF_LINK) 1150 continue; 1151 h = dc_crc_be(LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 1152 if (h < 32) 1153 hashes[0] |= (1 << h); 1154 else 1155 hashes[1] |= (1 << (h - 32)); 1156 } 1157 1158 CSR_WRITE_4(sc, DC_AL_MAR0, hashes[0]); 1159 CSR_WRITE_4(sc, DC_AL_MAR1, hashes[1]); 1160 1161 return; 1162 } 1163 1164 void dc_setfilt_asix(sc) 1165 struct dc_softc *sc; 1166 { 1167 struct ifnet *ifp; 1168 int h = 0; 1169 u_int32_t hashes[2] = { 0, 0 }; 1170 struct ifmultiaddr *ifma; 1171 1172 ifp = &sc->arpcom.ac_if; 1173 1174 /* Init our MAC address */ 1175 CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_PAR0); 1176 CSR_WRITE_4(sc, DC_AX_FILTDATA, 1177 *(u_int32_t *)(&sc->arpcom.ac_enaddr[0])); 1178 CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_PAR1); 1179 CSR_WRITE_4(sc, DC_AX_FILTDATA, 1180 *(u_int32_t *)(&sc->arpcom.ac_enaddr[4])); 1181 1182 /* If we want promiscuous mode, set the allframes bit. */ 1183 if (ifp->if_flags & IFF_PROMISC) 1184 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC); 1185 else 1186 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC); 1187 1188 if (ifp->if_flags & IFF_ALLMULTI) 1189 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI); 1190 else 1191 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI); 1192 1193 /* 1194 * The ASIX chip has a special bit to enable reception 1195 * of broadcast frames. 1196 */ 1197 if (ifp->if_flags & IFF_BROADCAST) 1198 DC_SETBIT(sc, DC_NETCFG, DC_AX_NETCFG_RX_BROAD); 1199 else 1200 DC_CLRBIT(sc, DC_NETCFG, DC_AX_NETCFG_RX_BROAD); 1201 1202 /* first, zot all the existing hash bits */ 1203 CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_MAR0); 1204 CSR_WRITE_4(sc, DC_AX_FILTDATA, 0); 1205 CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_MAR1); 1206 CSR_WRITE_4(sc, DC_AX_FILTDATA, 0); 1207 1208 /* 1209 * If we're already in promisc or allmulti mode, we 1210 * don't have to bother programming the multicast filter. 1211 */ 1212 if (ifp->if_flags & (IFF_PROMISC|IFF_ALLMULTI)) 1213 return; 1214 1215 /* now program new ones */ 1216 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 1217 if (ifma->ifma_addr->sa_family != AF_LINK) 1218 continue; 1219 h = dc_crc_be(LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 1220 if (h < 32) 1221 hashes[0] |= (1 << h); 1222 else 1223 hashes[1] |= (1 << (h - 32)); 1224 } 1225 1226 CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_MAR0); 1227 CSR_WRITE_4(sc, DC_AX_FILTDATA, hashes[0]); 1228 CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_MAR1); 1229 CSR_WRITE_4(sc, DC_AX_FILTDATA, hashes[1]); 1230 1231 return; 1232 } 1233 1234 void dc_setfilt_xircom(sc) 1235 struct dc_softc *sc; 1236 { 1237 struct dc_desc *sframe; 1238 u_int32_t h, *sp; 1239 struct ifmultiaddr *ifma; 1240 struct ifnet *ifp; 1241 int i; 1242 1243 ifp = &sc->arpcom.ac_if; 1244 DC_CLRBIT(sc, DC_NETCFG, (DC_NETCFG_TX_ON|DC_NETCFG_RX_ON)); 1245 1246 i = sc->dc_cdata.dc_tx_prod; 1247 DC_INC(sc->dc_cdata.dc_tx_prod, DC_TX_LIST_CNT); 1248 sc->dc_cdata.dc_tx_cnt++; 1249 sframe = &sc->dc_ldata->dc_tx_list[i]; 1250 sp = (u_int32_t *)&sc->dc_cdata.dc_sbuf; 1251 bzero((char *)sp, DC_SFRAME_LEN); 1252 1253 sframe->dc_data = vtophys(&sc->dc_cdata.dc_sbuf); 1254 sframe->dc_ctl = DC_SFRAME_LEN | DC_TXCTL_SETUP | DC_TXCTL_TLINK | 1255 DC_FILTER_HASHPERF | DC_TXCTL_FINT; 1256 1257 sc->dc_cdata.dc_tx_chain[i] = (struct mbuf *)&sc->dc_cdata.dc_sbuf; 1258 1259 /* If we want promiscuous mode, set the allframes bit. */ 1260 if (ifp->if_flags & IFF_PROMISC) 1261 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC); 1262 else 1263 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC); 1264 1265 if (ifp->if_flags & IFF_ALLMULTI) 1266 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI); 1267 else 1268 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI); 1269 1270 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 1271 if (ifma->ifma_addr->sa_family != AF_LINK) 1272 continue; 1273 h = dc_crc_le(sc, 1274 LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 1275 sp[h >> 4] |= 1 << (h & 0xF); 1276 } 1277 1278 if (ifp->if_flags & IFF_BROADCAST) { 1279 h = dc_crc_le(sc, (caddr_t)ðerbroadcastaddr); 1280 sp[h >> 4] |= 1 << (h & 0xF); 1281 } 1282 1283 /* Set our MAC address */ 1284 sp[0] = ((u_int16_t *)sc->arpcom.ac_enaddr)[0]; 1285 sp[1] = ((u_int16_t *)sc->arpcom.ac_enaddr)[1]; 1286 sp[2] = ((u_int16_t *)sc->arpcom.ac_enaddr)[2]; 1287 1288 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_TX_ON); 1289 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_ON); 1290 ifp->if_flags |= IFF_RUNNING; 1291 sframe->dc_status = DC_TXSTAT_OWN; 1292 CSR_WRITE_4(sc, DC_TXSTART, 0xFFFFFFFF); 1293 1294 /* 1295 * wait some time... 1296 */ 1297 DELAY(1000); 1298 1299 ifp->if_timer = 5; 1300 1301 return; 1302 } 1303 1304 static void dc_setfilt(sc) 1305 struct dc_softc *sc; 1306 { 1307 if (DC_IS_INTEL(sc) || DC_IS_MACRONIX(sc) || DC_IS_PNIC(sc) || 1308 DC_IS_PNICII(sc) || DC_IS_DAVICOM(sc) || DC_IS_CONEXANT(sc)) 1309 dc_setfilt_21143(sc); 1310 1311 if (DC_IS_ASIX(sc)) 1312 dc_setfilt_asix(sc); 1313 1314 if (DC_IS_ADMTEK(sc)) 1315 dc_setfilt_admtek(sc); 1316 1317 if (DC_IS_XIRCOM(sc)) 1318 dc_setfilt_xircom(sc); 1319 1320 return; 1321 } 1322 1323 /* 1324 * In order to fiddle with the 1325 * 'full-duplex' and '100Mbps' bits in the netconfig register, we 1326 * first have to put the transmit and/or receive logic in the idle state. 1327 */ 1328 static void dc_setcfg(sc, media) 1329 struct dc_softc *sc; 1330 int media; 1331 { 1332 int i, restart = 0; 1333 u_int32_t isr; 1334 1335 if (IFM_SUBTYPE(media) == IFM_NONE) 1336 return; 1337 1338 if (CSR_READ_4(sc, DC_NETCFG) & (DC_NETCFG_TX_ON|DC_NETCFG_RX_ON)) { 1339 restart = 1; 1340 DC_CLRBIT(sc, DC_NETCFG, (DC_NETCFG_TX_ON|DC_NETCFG_RX_ON)); 1341 1342 for (i = 0; i < DC_TIMEOUT; i++) { 1343 isr = CSR_READ_4(sc, DC_ISR); 1344 if (isr & DC_ISR_TX_IDLE && 1345 (isr & DC_ISR_RX_STATE) == DC_RXSTATE_STOPPED) 1346 break; 1347 DELAY(10); 1348 } 1349 1350 if (i == DC_TIMEOUT) 1351 printf("dc%d: failed to force tx and " 1352 "rx to idle state\n", sc->dc_unit); 1353 } 1354 1355 if (IFM_SUBTYPE(media) == IFM_100_TX) { 1356 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_SPEEDSEL); 1357 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_HEARTBEAT); 1358 if (sc->dc_pmode == DC_PMODE_MII) { 1359 int watchdogreg; 1360 1361 if (DC_IS_INTEL(sc)) { 1362 /* there's a write enable bit here that reads as 1 */ 1363 watchdogreg = CSR_READ_4(sc, DC_WATCHDOG); 1364 watchdogreg &= ~DC_WDOG_CTLWREN; 1365 watchdogreg |= DC_WDOG_JABBERDIS; 1366 CSR_WRITE_4(sc, DC_WATCHDOG, watchdogreg); 1367 } else { 1368 DC_SETBIT(sc, DC_WATCHDOG, DC_WDOG_JABBERDIS); 1369 } 1370 DC_CLRBIT(sc, DC_NETCFG, (DC_NETCFG_PCS| 1371 DC_NETCFG_PORTSEL|DC_NETCFG_SCRAMBLER)); 1372 if (sc->dc_type == DC_TYPE_98713) 1373 DC_SETBIT(sc, DC_NETCFG, (DC_NETCFG_PCS| 1374 DC_NETCFG_SCRAMBLER)); 1375 if (!DC_IS_DAVICOM(sc)) 1376 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL); 1377 DC_CLRBIT(sc, DC_10BTCTRL, 0xFFFF); 1378 if (DC_IS_INTEL(sc)) 1379 dc_apply_fixup(sc, IFM_AUTO); 1380 } else { 1381 if (DC_IS_PNIC(sc)) { 1382 DC_PN_GPIO_SETBIT(sc, DC_PN_GPIO_SPEEDSEL); 1383 DC_PN_GPIO_SETBIT(sc, DC_PN_GPIO_100TX_LOOP); 1384 DC_SETBIT(sc, DC_PN_NWAY, DC_PN_NWAY_SPEEDSEL); 1385 } 1386 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL); 1387 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PCS); 1388 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_SCRAMBLER); 1389 if (DC_IS_INTEL(sc)) 1390 dc_apply_fixup(sc, 1391 (media & IFM_GMASK) == IFM_FDX ? 1392 IFM_100_TX|IFM_FDX : IFM_100_TX); 1393 } 1394 } 1395 1396 if (IFM_SUBTYPE(media) == IFM_10_T) { 1397 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_SPEEDSEL); 1398 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_HEARTBEAT); 1399 if (sc->dc_pmode == DC_PMODE_MII) { 1400 int watchdogreg; 1401 1402 /* there's a write enable bit here that reads as 1 */ 1403 if (DC_IS_INTEL(sc)) { 1404 watchdogreg = CSR_READ_4(sc, DC_WATCHDOG); 1405 watchdogreg &= ~DC_WDOG_CTLWREN; 1406 watchdogreg |= DC_WDOG_JABBERDIS; 1407 CSR_WRITE_4(sc, DC_WATCHDOG, watchdogreg); 1408 } else { 1409 DC_SETBIT(sc, DC_WATCHDOG, DC_WDOG_JABBERDIS); 1410 } 1411 DC_CLRBIT(sc, DC_NETCFG, (DC_NETCFG_PCS| 1412 DC_NETCFG_PORTSEL|DC_NETCFG_SCRAMBLER)); 1413 if (sc->dc_type == DC_TYPE_98713) 1414 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PCS); 1415 if (!DC_IS_DAVICOM(sc)) 1416 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL); 1417 DC_CLRBIT(sc, DC_10BTCTRL, 0xFFFF); 1418 if (DC_IS_INTEL(sc)) 1419 dc_apply_fixup(sc, IFM_AUTO); 1420 } else { 1421 if (DC_IS_PNIC(sc)) { 1422 DC_PN_GPIO_CLRBIT(sc, DC_PN_GPIO_SPEEDSEL); 1423 DC_PN_GPIO_SETBIT(sc, DC_PN_GPIO_100TX_LOOP); 1424 DC_CLRBIT(sc, DC_PN_NWAY, DC_PN_NWAY_SPEEDSEL); 1425 } 1426 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL); 1427 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_PCS); 1428 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_SCRAMBLER); 1429 if (DC_IS_INTEL(sc)) { 1430 DC_CLRBIT(sc, DC_SIARESET, DC_SIA_RESET); 1431 DC_CLRBIT(sc, DC_10BTCTRL, 0xFFFF); 1432 if ((media & IFM_GMASK) == IFM_FDX) 1433 DC_SETBIT(sc, DC_10BTCTRL, 0x7F3D); 1434 else 1435 DC_SETBIT(sc, DC_10BTCTRL, 0x7F3F); 1436 DC_SETBIT(sc, DC_SIARESET, DC_SIA_RESET); 1437 DC_CLRBIT(sc, DC_10BTCTRL, 1438 DC_TCTL_AUTONEGENBL); 1439 dc_apply_fixup(sc, 1440 (media & IFM_GMASK) == IFM_FDX ? 1441 IFM_10_T|IFM_FDX : IFM_10_T); 1442 DELAY(20000); 1443 } 1444 } 1445 } 1446 1447 /* 1448 * If this is a Davicom DM9102A card with a DM9801 HomePNA 1449 * PHY and we want HomePNA mode, set the portsel bit to turn 1450 * on the external MII port. 1451 */ 1452 if (DC_IS_DAVICOM(sc)) { 1453 if (IFM_SUBTYPE(media) == IFM_homePNA) { 1454 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL); 1455 sc->dc_link = 1; 1456 } else { 1457 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL); 1458 } 1459 } 1460 1461 if ((media & IFM_GMASK) == IFM_FDX) { 1462 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_FULLDUPLEX); 1463 if (sc->dc_pmode == DC_PMODE_SYM && DC_IS_PNIC(sc)) 1464 DC_SETBIT(sc, DC_PN_NWAY, DC_PN_NWAY_DUPLEX); 1465 } else { 1466 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_FULLDUPLEX); 1467 if (sc->dc_pmode == DC_PMODE_SYM && DC_IS_PNIC(sc)) 1468 DC_CLRBIT(sc, DC_PN_NWAY, DC_PN_NWAY_DUPLEX); 1469 } 1470 1471 if (restart) 1472 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_TX_ON|DC_NETCFG_RX_ON); 1473 1474 return; 1475 } 1476 1477 static void dc_reset(sc) 1478 struct dc_softc *sc; 1479 { 1480 register int i; 1481 1482 DC_SETBIT(sc, DC_BUSCTL, DC_BUSCTL_RESET); 1483 1484 for (i = 0; i < DC_TIMEOUT; i++) { 1485 DELAY(10); 1486 if (!(CSR_READ_4(sc, DC_BUSCTL) & DC_BUSCTL_RESET)) 1487 break; 1488 } 1489 1490 if (DC_IS_ASIX(sc) || DC_IS_ADMTEK(sc) || DC_IS_CONEXANT(sc) || 1491 DC_IS_XIRCOM(sc) || DC_IS_INTEL(sc)) { 1492 DELAY(10000); 1493 DC_CLRBIT(sc, DC_BUSCTL, DC_BUSCTL_RESET); 1494 i = 0; 1495 } 1496 1497 if (i == DC_TIMEOUT) 1498 printf("dc%d: reset never completed!\n", sc->dc_unit); 1499 1500 /* Wait a little while for the chip to get its brains in order. */ 1501 DELAY(1000); 1502 1503 CSR_WRITE_4(sc, DC_IMR, 0x00000000); 1504 CSR_WRITE_4(sc, DC_BUSCTL, 0x00000000); 1505 CSR_WRITE_4(sc, DC_NETCFG, 0x00000000); 1506 1507 /* 1508 * Bring the SIA out of reset. In some cases, it looks 1509 * like failing to unreset the SIA soon enough gets it 1510 * into a state where it will never come out of reset 1511 * until we reset the whole chip again. 1512 */ 1513 if (DC_IS_INTEL(sc)) { 1514 DC_SETBIT(sc, DC_SIARESET, DC_SIA_RESET); 1515 CSR_WRITE_4(sc, DC_10BTCTRL, 0); 1516 CSR_WRITE_4(sc, DC_WATCHDOG, 0); 1517 } 1518 1519 return; 1520 } 1521 1522 static struct dc_type *dc_devtype(dev) 1523 device_t dev; 1524 { 1525 struct dc_type *t; 1526 u_int32_t rev; 1527 1528 t = dc_devs; 1529 1530 while(t->dc_name != NULL) { 1531 if ((pci_get_vendor(dev) == t->dc_vid) && 1532 (pci_get_device(dev) == t->dc_did)) { 1533 /* Check the PCI revision */ 1534 rev = pci_read_config(dev, DC_PCI_CFRV, 4) & 0xFF; 1535 if (t->dc_did == DC_DEVICEID_98713 && 1536 rev >= DC_REVISION_98713A) 1537 t++; 1538 if (t->dc_did == DC_DEVICEID_98713_CP && 1539 rev >= DC_REVISION_98713A) 1540 t++; 1541 if (t->dc_did == DC_DEVICEID_987x5 && 1542 rev >= DC_REVISION_98715AEC_C) 1543 t++; 1544 if (t->dc_did == DC_DEVICEID_987x5 && 1545 rev >= DC_REVISION_98725) 1546 t++; 1547 if (t->dc_did == DC_DEVICEID_AX88140A && 1548 rev >= DC_REVISION_88141) 1549 t++; 1550 if (t->dc_did == DC_DEVICEID_82C168 && 1551 rev >= DC_REVISION_82C169) 1552 t++; 1553 if (t->dc_did == DC_DEVICEID_DM9102 && 1554 rev >= DC_REVISION_DM9102A) 1555 t++; 1556 return(t); 1557 } 1558 t++; 1559 } 1560 1561 return(NULL); 1562 } 1563 1564 /* 1565 * Probe for a 21143 or clone chip. Check the PCI vendor and device 1566 * IDs against our list and return a device name if we find a match. 1567 * We do a little bit of extra work to identify the exact type of 1568 * chip. The MX98713 and MX98713A have the same PCI vendor/device ID, 1569 * but different revision IDs. The same is true for 98715/98715A 1570 * chips and the 98725, as well as the ASIX and ADMtek chips. In some 1571 * cases, the exact chip revision affects driver behavior. 1572 */ 1573 static int dc_probe(dev) 1574 device_t dev; 1575 { 1576 struct dc_type *t; 1577 1578 t = dc_devtype(dev); 1579 1580 if (t != NULL) { 1581 device_set_desc(dev, t->dc_name); 1582 return(0); 1583 } 1584 1585 return(ENXIO); 1586 } 1587 1588 static void dc_acpi(dev) 1589 device_t dev; 1590 { 1591 int unit; 1592 1593 unit = device_get_unit(dev); 1594 1595 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) { 1596 u_int32_t iobase, membase, irq; 1597 1598 /* Save important PCI config data. */ 1599 iobase = pci_read_config(dev, DC_PCI_CFBIO, 4); 1600 membase = pci_read_config(dev, DC_PCI_CFBMA, 4); 1601 irq = pci_read_config(dev, DC_PCI_CFIT, 4); 1602 1603 /* Reset the power state. */ 1604 printf("dc%d: chip is in D%d power mode " 1605 "-- setting to D0\n", unit, 1606 pci_get_powerstate(dev)); 1607 pci_set_powerstate(dev, PCI_POWERSTATE_D0); 1608 1609 /* Restore PCI config data. */ 1610 pci_write_config(dev, DC_PCI_CFBIO, iobase, 4); 1611 pci_write_config(dev, DC_PCI_CFBMA, membase, 4); 1612 pci_write_config(dev, DC_PCI_CFIT, irq, 4); 1613 } 1614 1615 return; 1616 } 1617 1618 static void dc_apply_fixup(sc, media) 1619 struct dc_softc *sc; 1620 int media; 1621 { 1622 struct dc_mediainfo *m; 1623 u_int8_t *p; 1624 int i; 1625 u_int32_t reg; 1626 1627 m = sc->dc_mi; 1628 1629 while (m != NULL) { 1630 if (m->dc_media == media) 1631 break; 1632 m = m->dc_next; 1633 } 1634 1635 if (m == NULL) 1636 return; 1637 1638 for (i = 0, p = m->dc_reset_ptr; i < m->dc_reset_len; i++, p += 2) { 1639 reg = (p[0] | (p[1] << 8)) << 16; 1640 CSR_WRITE_4(sc, DC_WATCHDOG, reg); 1641 } 1642 1643 for (i = 0, p = m->dc_gp_ptr; i < m->dc_gp_len; i++, p += 2) { 1644 reg = (p[0] | (p[1] << 8)) << 16; 1645 CSR_WRITE_4(sc, DC_WATCHDOG, reg); 1646 } 1647 1648 return; 1649 } 1650 1651 static void dc_decode_leaf_sia(sc, l) 1652 struct dc_softc *sc; 1653 struct dc_eblock_sia *l; 1654 { 1655 struct dc_mediainfo *m; 1656 1657 m = malloc(sizeof(struct dc_mediainfo), M_DEVBUF, M_NOWAIT); 1658 bzero(m, sizeof(struct dc_mediainfo)); 1659 if (l->dc_sia_code == DC_SIA_CODE_10BT) 1660 m->dc_media = IFM_10_T; 1661 1662 if (l->dc_sia_code == DC_SIA_CODE_10BT_FDX) 1663 m->dc_media = IFM_10_T|IFM_FDX; 1664 1665 if (l->dc_sia_code == DC_SIA_CODE_10B2) 1666 m->dc_media = IFM_10_2; 1667 1668 if (l->dc_sia_code == DC_SIA_CODE_10B5) 1669 m->dc_media = IFM_10_5; 1670 1671 m->dc_gp_len = 2; 1672 m->dc_gp_ptr = (u_int8_t *)&l->dc_sia_gpio_ctl; 1673 1674 m->dc_next = sc->dc_mi; 1675 sc->dc_mi = m; 1676 1677 sc->dc_pmode = DC_PMODE_SIA; 1678 1679 return; 1680 } 1681 1682 static void dc_decode_leaf_sym(sc, l) 1683 struct dc_softc *sc; 1684 struct dc_eblock_sym *l; 1685 { 1686 struct dc_mediainfo *m; 1687 1688 m = malloc(sizeof(struct dc_mediainfo), M_DEVBUF, M_NOWAIT); 1689 bzero(m, sizeof(struct dc_mediainfo)); 1690 if (l->dc_sym_code == DC_SYM_CODE_100BT) 1691 m->dc_media = IFM_100_TX; 1692 1693 if (l->dc_sym_code == DC_SYM_CODE_100BT_FDX) 1694 m->dc_media = IFM_100_TX|IFM_FDX; 1695 1696 m->dc_gp_len = 2; 1697 m->dc_gp_ptr = (u_int8_t *)&l->dc_sym_gpio_ctl; 1698 1699 m->dc_next = sc->dc_mi; 1700 sc->dc_mi = m; 1701 1702 sc->dc_pmode = DC_PMODE_SYM; 1703 1704 return; 1705 } 1706 1707 static void dc_decode_leaf_mii(sc, l) 1708 struct dc_softc *sc; 1709 struct dc_eblock_mii *l; 1710 { 1711 u_int8_t *p; 1712 struct dc_mediainfo *m; 1713 1714 m = malloc(sizeof(struct dc_mediainfo), M_DEVBUF, M_NOWAIT); 1715 bzero(m, sizeof(struct dc_mediainfo)); 1716 /* We abuse IFM_AUTO to represent MII. */ 1717 m->dc_media = IFM_AUTO; 1718 m->dc_gp_len = l->dc_gpr_len; 1719 1720 p = (u_int8_t *)l; 1721 p += sizeof(struct dc_eblock_mii); 1722 m->dc_gp_ptr = p; 1723 p += 2 * l->dc_gpr_len; 1724 m->dc_reset_len = *p; 1725 p++; 1726 m->dc_reset_ptr = p; 1727 1728 m->dc_next = sc->dc_mi; 1729 sc->dc_mi = m; 1730 1731 return; 1732 } 1733 1734 static void dc_parse_21143_srom(sc) 1735 struct dc_softc *sc; 1736 { 1737 struct dc_leaf_hdr *lhdr; 1738 struct dc_eblock_hdr *hdr; 1739 int i, loff; 1740 char *ptr; 1741 1742 loff = sc->dc_srom[27]; 1743 lhdr = (struct dc_leaf_hdr *)&(sc->dc_srom[loff]); 1744 1745 ptr = (char *)lhdr; 1746 ptr += sizeof(struct dc_leaf_hdr) - 1; 1747 for (i = 0; i < lhdr->dc_mcnt; i++) { 1748 hdr = (struct dc_eblock_hdr *)ptr; 1749 switch(hdr->dc_type) { 1750 case DC_EBLOCK_MII: 1751 dc_decode_leaf_mii(sc, (struct dc_eblock_mii *)hdr); 1752 break; 1753 case DC_EBLOCK_SIA: 1754 dc_decode_leaf_sia(sc, (struct dc_eblock_sia *)hdr); 1755 break; 1756 case DC_EBLOCK_SYM: 1757 dc_decode_leaf_sym(sc, (struct dc_eblock_sym *)hdr); 1758 break; 1759 default: 1760 /* Don't care. Yet. */ 1761 break; 1762 } 1763 ptr += (hdr->dc_len & 0x7F); 1764 ptr++; 1765 } 1766 1767 return; 1768 } 1769 1770 /* 1771 * Attach the interface. Allocate softc structures, do ifmedia 1772 * setup and ethernet/BPF attach. 1773 */ 1774 static int dc_attach(dev) 1775 device_t dev; 1776 { 1777 int tmp = 0; 1778 u_char eaddr[ETHER_ADDR_LEN]; 1779 u_int32_t command; 1780 struct dc_softc *sc; 1781 struct ifnet *ifp; 1782 u_int32_t revision; 1783 int unit, error = 0, rid, mac_offset; 1784 1785 sc = device_get_softc(dev); 1786 unit = device_get_unit(dev); 1787 bzero(sc, sizeof(struct dc_softc)); 1788 1789 mtx_init(&sc->dc_mtx, device_get_nameunit(dev), MTX_DEF | MTX_RECURSE); 1790 DC_LOCK(sc); 1791 1792 /* 1793 * Handle power management nonsense. 1794 */ 1795 dc_acpi(dev); 1796 1797 /* 1798 * Map control/status registers. 1799 */ 1800 pci_enable_busmaster(dev); 1801 pci_enable_io(dev, SYS_RES_IOPORT); 1802 pci_enable_io(dev, SYS_RES_MEMORY); 1803 command = pci_read_config(dev, PCIR_COMMAND, 4); 1804 1805 #ifdef DC_USEIOSPACE 1806 if (!(command & PCIM_CMD_PORTEN)) { 1807 printf("dc%d: failed to enable I/O ports!\n", unit); 1808 error = ENXIO; 1809 goto fail; 1810 } 1811 #else 1812 if (!(command & PCIM_CMD_MEMEN)) { 1813 printf("dc%d: failed to enable memory mapping!\n", unit); 1814 error = ENXIO; 1815 goto fail; 1816 } 1817 #endif 1818 1819 rid = DC_RID; 1820 sc->dc_res = bus_alloc_resource(dev, DC_RES, &rid, 1821 0, ~0, 1, RF_ACTIVE); 1822 1823 if (sc->dc_res == NULL) { 1824 printf("dc%d: couldn't map ports/memory\n", unit); 1825 error = ENXIO; 1826 goto fail; 1827 } 1828 1829 sc->dc_btag = rman_get_bustag(sc->dc_res); 1830 sc->dc_bhandle = rman_get_bushandle(sc->dc_res); 1831 1832 /* Allocate interrupt */ 1833 rid = 0; 1834 sc->dc_irq = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, 0, ~0, 1, 1835 RF_SHAREABLE | RF_ACTIVE); 1836 1837 if (sc->dc_irq == NULL) { 1838 printf("dc%d: couldn't map interrupt\n", unit); 1839 bus_release_resource(dev, DC_RES, DC_RID, sc->dc_res); 1840 error = ENXIO; 1841 goto fail; 1842 } 1843 1844 error = bus_setup_intr(dev, sc->dc_irq, INTR_TYPE_NET | 1845 (IS_MPSAFE ? INTR_MPSAFE : 0), 1846 dc_intr, sc, &sc->dc_intrhand); 1847 1848 if (error) { 1849 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->dc_irq); 1850 bus_release_resource(dev, DC_RES, DC_RID, sc->dc_res); 1851 printf("dc%d: couldn't set up irq\n", unit); 1852 goto fail; 1853 } 1854 1855 /* Need this info to decide on a chip type. */ 1856 sc->dc_info = dc_devtype(dev); 1857 revision = pci_read_config(dev, DC_PCI_CFRV, 4) & 0x000000FF; 1858 1859 switch(sc->dc_info->dc_did) { 1860 case DC_DEVICEID_21143: 1861 sc->dc_type = DC_TYPE_21143; 1862 sc->dc_flags |= DC_TX_POLL|DC_TX_USE_TX_INTR; 1863 sc->dc_flags |= DC_REDUCED_MII_POLL; 1864 /* Save EEPROM contents so we can parse them later. */ 1865 dc_read_eeprom(sc, (caddr_t)&sc->dc_srom, 0, 512, 0); 1866 break; 1867 case DC_DEVICEID_DM9100: 1868 case DC_DEVICEID_DM9102: 1869 sc->dc_type = DC_TYPE_DM9102; 1870 sc->dc_flags |= DC_TX_COALESCE|DC_TX_INTR_ALWAYS; 1871 sc->dc_flags |= DC_REDUCED_MII_POLL|DC_TX_STORENFWD; 1872 sc->dc_pmode = DC_PMODE_MII; 1873 /* Increase the latency timer value. */ 1874 command = pci_read_config(dev, DC_PCI_CFLT, 4); 1875 command &= 0xFFFF00FF; 1876 command |= 0x00008000; 1877 pci_write_config(dev, DC_PCI_CFLT, command, 4); 1878 break; 1879 case DC_DEVICEID_AL981: 1880 sc->dc_type = DC_TYPE_AL981; 1881 sc->dc_flags |= DC_TX_USE_TX_INTR; 1882 sc->dc_flags |= DC_TX_ADMTEK_WAR; 1883 sc->dc_pmode = DC_PMODE_MII; 1884 break; 1885 case DC_DEVICEID_AN985: 1886 case DC_DEVICEID_FE2500: 1887 case DC_DEVICEID_EN2242: 1888 sc->dc_type = DC_TYPE_AN985; 1889 sc->dc_flags |= DC_TX_USE_TX_INTR; 1890 sc->dc_flags |= DC_TX_ADMTEK_WAR; 1891 sc->dc_pmode = DC_PMODE_MII; 1892 break; 1893 case DC_DEVICEID_98713: 1894 case DC_DEVICEID_98713_CP: 1895 if (revision < DC_REVISION_98713A) { 1896 sc->dc_type = DC_TYPE_98713; 1897 } 1898 if (revision >= DC_REVISION_98713A) { 1899 sc->dc_type = DC_TYPE_98713A; 1900 sc->dc_flags |= DC_21143_NWAY; 1901 } 1902 sc->dc_flags |= DC_REDUCED_MII_POLL; 1903 sc->dc_flags |= DC_TX_POLL|DC_TX_USE_TX_INTR; 1904 break; 1905 case DC_DEVICEID_987x5: 1906 case DC_DEVICEID_EN1217: 1907 /* 1908 * Macronix MX98715AEC-C/D/E parts have only a 1909 * 128-bit hash table. We need to deal with these 1910 * in the same manner as the PNIC II so that we 1911 * get the right number of bits out of the 1912 * CRC routine. 1913 */ 1914 if (revision >= DC_REVISION_98715AEC_C && 1915 revision < DC_REVISION_98725) 1916 sc->dc_flags |= DC_128BIT_HASH; 1917 sc->dc_type = DC_TYPE_987x5; 1918 sc->dc_flags |= DC_TX_POLL|DC_TX_USE_TX_INTR; 1919 sc->dc_flags |= DC_REDUCED_MII_POLL|DC_21143_NWAY; 1920 break; 1921 case DC_DEVICEID_98727: 1922 sc->dc_type = DC_TYPE_987x5; 1923 sc->dc_flags |= DC_TX_POLL|DC_TX_USE_TX_INTR; 1924 sc->dc_flags |= DC_REDUCED_MII_POLL|DC_21143_NWAY; 1925 break; 1926 case DC_DEVICEID_82C115: 1927 sc->dc_type = DC_TYPE_PNICII; 1928 sc->dc_flags |= DC_TX_POLL|DC_TX_USE_TX_INTR|DC_128BIT_HASH; 1929 sc->dc_flags |= DC_REDUCED_MII_POLL|DC_21143_NWAY; 1930 break; 1931 case DC_DEVICEID_82C168: 1932 sc->dc_type = DC_TYPE_PNIC; 1933 sc->dc_flags |= DC_TX_STORENFWD|DC_TX_INTR_ALWAYS; 1934 sc->dc_flags |= DC_PNIC_RX_BUG_WAR; 1935 sc->dc_pnic_rx_buf = malloc(DC_RXLEN * 5, M_DEVBUF, M_NOWAIT); 1936 if (revision < DC_REVISION_82C169) 1937 sc->dc_pmode = DC_PMODE_SYM; 1938 break; 1939 case DC_DEVICEID_AX88140A: 1940 sc->dc_type = DC_TYPE_ASIX; 1941 sc->dc_flags |= DC_TX_USE_TX_INTR|DC_TX_INTR_FIRSTFRAG; 1942 sc->dc_flags |= DC_REDUCED_MII_POLL; 1943 sc->dc_pmode = DC_PMODE_MII; 1944 break; 1945 case DC_DEVICEID_X3201: 1946 sc->dc_type = DC_TYPE_XIRCOM; 1947 sc->dc_flags |= DC_TX_INTR_ALWAYS | DC_TX_COALESCE | 1948 DC_TX_ALIGN; 1949 /* 1950 * We don't actually need to coalesce, but we're doing 1951 * it to obtain a double word aligned buffer. 1952 * The DC_TX_COALESCE flag is required. 1953 */ 1954 break; 1955 case DC_DEVICEID_RS7112: 1956 sc->dc_type = DC_TYPE_CONEXANT; 1957 sc->dc_flags |= DC_TX_INTR_ALWAYS; 1958 sc->dc_flags |= DC_REDUCED_MII_POLL; 1959 sc->dc_pmode = DC_PMODE_MII; 1960 dc_read_eeprom(sc, (caddr_t)&sc->dc_srom, 0, 256, 0); 1961 break; 1962 default: 1963 printf("dc%d: unknown device: %x\n", sc->dc_unit, 1964 sc->dc_info->dc_did); 1965 break; 1966 } 1967 1968 /* Save the cache line size. */ 1969 if (DC_IS_DAVICOM(sc)) 1970 sc->dc_cachesize = 0; 1971 else 1972 sc->dc_cachesize = pci_read_config(dev, 1973 DC_PCI_CFLT, 4) & 0xFF; 1974 1975 /* Reset the adapter. */ 1976 dc_reset(sc); 1977 1978 /* Take 21143 out of snooze mode */ 1979 if (DC_IS_INTEL(sc) || DC_IS_XIRCOM(sc)) { 1980 command = pci_read_config(dev, DC_PCI_CFDD, 4); 1981 command &= ~(DC_CFDD_SNOOZE_MODE|DC_CFDD_SLEEP_MODE); 1982 pci_write_config(dev, DC_PCI_CFDD, command, 4); 1983 } 1984 1985 /* 1986 * Try to learn something about the supported media. 1987 * We know that ASIX and ADMtek and Davicom devices 1988 * will *always* be using MII media, so that's a no-brainer. 1989 * The tricky ones are the Macronix/PNIC II and the 1990 * Intel 21143. 1991 */ 1992 if (DC_IS_INTEL(sc)) 1993 dc_parse_21143_srom(sc); 1994 else if (DC_IS_MACRONIX(sc) || DC_IS_PNICII(sc)) { 1995 if (sc->dc_type == DC_TYPE_98713) 1996 sc->dc_pmode = DC_PMODE_MII; 1997 else 1998 sc->dc_pmode = DC_PMODE_SYM; 1999 } else if (!sc->dc_pmode) 2000 sc->dc_pmode = DC_PMODE_MII; 2001 2002 /* 2003 * Get station address from the EEPROM. 2004 */ 2005 switch(sc->dc_type) { 2006 case DC_TYPE_98713: 2007 case DC_TYPE_98713A: 2008 case DC_TYPE_987x5: 2009 case DC_TYPE_PNICII: 2010 dc_read_eeprom(sc, (caddr_t)&mac_offset, 2011 (DC_EE_NODEADDR_OFFSET / 2), 1, 0); 2012 dc_read_eeprom(sc, (caddr_t)&eaddr, (mac_offset / 2), 3, 0); 2013 break; 2014 case DC_TYPE_PNIC: 2015 dc_read_eeprom(sc, (caddr_t)&eaddr, 0, 3, 1); 2016 break; 2017 case DC_TYPE_DM9102: 2018 case DC_TYPE_21143: 2019 case DC_TYPE_ASIX: 2020 dc_read_eeprom(sc, (caddr_t)&eaddr, DC_EE_NODEADDR, 3, 0); 2021 break; 2022 case DC_TYPE_AL981: 2023 case DC_TYPE_AN985: 2024 dc_read_eeprom(sc, (caddr_t)&eaddr, DC_AL_EE_NODEADDR, 3, 0); 2025 break; 2026 case DC_TYPE_CONEXANT: 2027 bcopy(sc->dc_srom + DC_CONEXANT_EE_NODEADDR, &eaddr, 6); 2028 break; 2029 case DC_TYPE_XIRCOM: 2030 dc_read_eeprom(sc, (caddr_t)&eaddr, 3, 3, 0); 2031 break; 2032 default: 2033 dc_read_eeprom(sc, (caddr_t)&eaddr, DC_EE_NODEADDR, 3, 0); 2034 break; 2035 } 2036 2037 /* 2038 * A 21143 or clone chip was detected. Inform the world. 2039 */ 2040 printf("dc%d: Ethernet address: %6D\n", unit, eaddr, ":"); 2041 2042 sc->dc_unit = unit; 2043 bcopy(eaddr, (char *)&sc->arpcom.ac_enaddr, ETHER_ADDR_LEN); 2044 2045 sc->dc_ldata = contigmalloc(sizeof(struct dc_list_data), M_DEVBUF, 2046 M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0); 2047 2048 if (sc->dc_ldata == NULL) { 2049 printf("dc%d: no memory for list buffers!\n", unit); 2050 bus_teardown_intr(dev, sc->dc_irq, sc->dc_intrhand); 2051 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->dc_irq); 2052 bus_release_resource(dev, DC_RES, DC_RID, sc->dc_res); 2053 error = ENXIO; 2054 goto fail; 2055 } 2056 2057 bzero(sc->dc_ldata, sizeof(struct dc_list_data)); 2058 2059 ifp = &sc->arpcom.ac_if; 2060 ifp->if_softc = sc; 2061 ifp->if_unit = unit; 2062 ifp->if_name = "dc"; 2063 /* XXX: bleah, MTU gets overwritten in ether_ifattach() */ 2064 ifp->if_mtu = ETHERMTU; 2065 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 2066 ifp->if_ioctl = dc_ioctl; 2067 ifp->if_output = ether_output; 2068 ifp->if_start = dc_start; 2069 ifp->if_watchdog = dc_watchdog; 2070 ifp->if_init = dc_init; 2071 ifp->if_baudrate = 10000000; 2072 ifp->if_snd.ifq_maxlen = DC_TX_LIST_CNT - 1; 2073 2074 /* 2075 * Do MII setup. If this is a 21143, check for a PHY on the 2076 * MII bus after applying any necessary fixups to twiddle the 2077 * GPIO bits. If we don't end up finding a PHY, restore the 2078 * old selection (SIA only or SIA/SYM) and attach the dcphy 2079 * driver instead. 2080 */ 2081 if (DC_IS_INTEL(sc)) { 2082 dc_apply_fixup(sc, IFM_AUTO); 2083 tmp = sc->dc_pmode; 2084 sc->dc_pmode = DC_PMODE_MII; 2085 } 2086 2087 error = mii_phy_probe(dev, &sc->dc_miibus, 2088 dc_ifmedia_upd, dc_ifmedia_sts); 2089 2090 if (error && DC_IS_INTEL(sc)) { 2091 sc->dc_pmode = tmp; 2092 if (sc->dc_pmode != DC_PMODE_SIA) 2093 sc->dc_pmode = DC_PMODE_SYM; 2094 sc->dc_flags |= DC_21143_NWAY; 2095 mii_phy_probe(dev, &sc->dc_miibus, 2096 dc_ifmedia_upd, dc_ifmedia_sts); 2097 /* 2098 * For non-MII cards, we need to have the 21143 2099 * drive the LEDs. Except there are some systems 2100 * like the NEC VersaPro NoteBook PC which have no 2101 * LEDs, and twiddling these bits has adverse effects 2102 * on them. (I.e. you suddenly can't get a link.) 2103 */ 2104 if (pci_read_config(dev, DC_PCI_CSID, 4) != 0x80281033) 2105 sc->dc_flags |= DC_TULIP_LEDS; 2106 error = 0; 2107 } 2108 2109 if (error) { 2110 printf("dc%d: MII without any PHY!\n", sc->dc_unit); 2111 bus_teardown_intr(dev, sc->dc_irq, sc->dc_intrhand); 2112 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->dc_irq); 2113 bus_release_resource(dev, DC_RES, DC_RID, sc->dc_res); 2114 error = ENXIO; 2115 goto fail; 2116 } 2117 2118 if (DC_IS_XIRCOM(sc)) { 2119 /* 2120 * setup General Purpose Port mode and data so the tulip 2121 * can talk to the MII. 2122 */ 2123 CSR_WRITE_4(sc, DC_SIAGP, DC_SIAGP_WRITE_EN | DC_SIAGP_INT1_EN | 2124 DC_SIAGP_MD_GP2_OUTPUT | DC_SIAGP_MD_GP0_OUTPUT); 2125 DELAY(10); 2126 CSR_WRITE_4(sc, DC_SIAGP, DC_SIAGP_INT1_EN | 2127 DC_SIAGP_MD_GP2_OUTPUT | DC_SIAGP_MD_GP0_OUTPUT); 2128 DELAY(10); 2129 } 2130 2131 /* 2132 * Call MI attach routine. 2133 */ 2134 ether_ifattach(ifp, ETHER_BPF_SUPPORTED); 2135 2136 /* 2137 * Tell the upper layer(s) we support long frames. 2138 */ 2139 ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header); 2140 2141 callout_init(&sc->dc_stat_ch, IS_MPSAFE); 2142 2143 #ifdef SRM_MEDIA 2144 sc->dc_srm_media = 0; 2145 2146 /* Remember the SRM console media setting */ 2147 if (DC_IS_INTEL(sc)) { 2148 command = pci_read_config(dev, DC_PCI_CFDD, 4); 2149 command &= ~(DC_CFDD_SNOOZE_MODE|DC_CFDD_SLEEP_MODE); 2150 switch ((command >> 8) & 0xff) { 2151 case 3: 2152 sc->dc_srm_media = IFM_10_T; 2153 break; 2154 case 4: 2155 sc->dc_srm_media = IFM_10_T | IFM_FDX; 2156 break; 2157 case 5: 2158 sc->dc_srm_media = IFM_100_TX; 2159 break; 2160 case 6: 2161 sc->dc_srm_media = IFM_100_TX | IFM_FDX; 2162 break; 2163 } 2164 if (sc->dc_srm_media) 2165 sc->dc_srm_media |= IFM_ACTIVE | IFM_ETHER; 2166 } 2167 #endif 2168 2169 DC_UNLOCK(sc); 2170 return(0); 2171 2172 fail: 2173 DC_UNLOCK(sc); 2174 mtx_destroy(&sc->dc_mtx); 2175 return(error); 2176 } 2177 2178 static int dc_detach(dev) 2179 device_t dev; 2180 { 2181 struct dc_softc *sc; 2182 struct ifnet *ifp; 2183 struct dc_mediainfo *m; 2184 2185 sc = device_get_softc(dev); 2186 2187 DC_LOCK(sc); 2188 2189 ifp = &sc->arpcom.ac_if; 2190 2191 dc_stop(sc); 2192 ether_ifdetach(ifp, ETHER_BPF_SUPPORTED); 2193 2194 bus_generic_detach(dev); 2195 device_delete_child(dev, sc->dc_miibus); 2196 2197 bus_teardown_intr(dev, sc->dc_irq, sc->dc_intrhand); 2198 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->dc_irq); 2199 bus_release_resource(dev, DC_RES, DC_RID, sc->dc_res); 2200 2201 contigfree(sc->dc_ldata, sizeof(struct dc_list_data), M_DEVBUF); 2202 if (sc->dc_pnic_rx_buf != NULL) 2203 free(sc->dc_pnic_rx_buf, M_DEVBUF); 2204 2205 while(sc->dc_mi != NULL) { 2206 m = sc->dc_mi->dc_next; 2207 free(sc->dc_mi, M_DEVBUF); 2208 sc->dc_mi = m; 2209 } 2210 2211 DC_UNLOCK(sc); 2212 mtx_destroy(&sc->dc_mtx); 2213 2214 return(0); 2215 } 2216 2217 /* 2218 * Initialize the transmit descriptors. 2219 */ 2220 static int dc_list_tx_init(sc) 2221 struct dc_softc *sc; 2222 { 2223 struct dc_chain_data *cd; 2224 struct dc_list_data *ld; 2225 int i, nexti; 2226 2227 cd = &sc->dc_cdata; 2228 ld = sc->dc_ldata; 2229 for (i = 0; i < DC_TX_LIST_CNT; i++) { 2230 nexti = (i == (DC_TX_LIST_CNT - 1)) ? 0 : i+1; 2231 ld->dc_tx_list[i].dc_next = vtophys(&ld->dc_tx_list[nexti]); 2232 cd->dc_tx_chain[i] = NULL; 2233 ld->dc_tx_list[i].dc_data = 0; 2234 ld->dc_tx_list[i].dc_ctl = 0; 2235 } 2236 2237 cd->dc_tx_prod = cd->dc_tx_cons = cd->dc_tx_cnt = 0; 2238 2239 return(0); 2240 } 2241 2242 2243 /* 2244 * Initialize the RX descriptors and allocate mbufs for them. Note that 2245 * we arrange the descriptors in a closed ring, so that the last descriptor 2246 * points back to the first. 2247 */ 2248 static int dc_list_rx_init(sc) 2249 struct dc_softc *sc; 2250 { 2251 struct dc_chain_data *cd; 2252 struct dc_list_data *ld; 2253 int i, nexti; 2254 2255 cd = &sc->dc_cdata; 2256 ld = sc->dc_ldata; 2257 2258 for (i = 0; i < DC_RX_LIST_CNT; i++) { 2259 if (dc_newbuf(sc, i, NULL) == ENOBUFS) 2260 return(ENOBUFS); 2261 nexti = (i == (DC_RX_LIST_CNT - 1)) ? 0 : i+1; 2262 ld->dc_rx_list[i].dc_next = vtophys(&ld->dc_rx_list[nexti]); 2263 } 2264 2265 cd->dc_rx_prod = 0; 2266 2267 return(0); 2268 } 2269 2270 /* 2271 * Initialize an RX descriptor and attach an MBUF cluster. 2272 */ 2273 static int dc_newbuf(sc, i, m) 2274 struct dc_softc *sc; 2275 int i; 2276 struct mbuf *m; 2277 { 2278 struct mbuf *m_new = NULL; 2279 struct dc_desc *c; 2280 2281 c = &sc->dc_ldata->dc_rx_list[i]; 2282 2283 if (m == NULL) { 2284 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 2285 if (m_new == NULL) 2286 return(ENOBUFS); 2287 2288 MCLGET(m_new, M_DONTWAIT); 2289 if (!(m_new->m_flags & M_EXT)) { 2290 m_freem(m_new); 2291 return(ENOBUFS); 2292 } 2293 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 2294 } else { 2295 m_new = m; 2296 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 2297 m_new->m_data = m_new->m_ext.ext_buf; 2298 } 2299 2300 m_adj(m_new, sizeof(u_int64_t)); 2301 2302 /* 2303 * If this is a PNIC chip, zero the buffer. This is part 2304 * of the workaround for the receive bug in the 82c168 and 2305 * 82c169 chips. 2306 */ 2307 if (sc->dc_flags & DC_PNIC_RX_BUG_WAR) 2308 bzero((char *)mtod(m_new, char *), m_new->m_len); 2309 2310 sc->dc_cdata.dc_rx_chain[i] = m_new; 2311 c->dc_data = vtophys(mtod(m_new, caddr_t)); 2312 c->dc_ctl = DC_RXCTL_RLINK | DC_RXLEN; 2313 c->dc_status = DC_RXSTAT_OWN; 2314 2315 return(0); 2316 } 2317 2318 /* 2319 * Grrrrr. 2320 * The PNIC chip has a terrible bug in it that manifests itself during 2321 * periods of heavy activity. The exact mode of failure if difficult to 2322 * pinpoint: sometimes it only happens in promiscuous mode, sometimes it 2323 * will happen on slow machines. The bug is that sometimes instead of 2324 * uploading one complete frame during reception, it uploads what looks 2325 * like the entire contents of its FIFO memory. The frame we want is at 2326 * the end of the whole mess, but we never know exactly how much data has 2327 * been uploaded, so salvaging the frame is hard. 2328 * 2329 * There is only one way to do it reliably, and it's disgusting. 2330 * Here's what we know: 2331 * 2332 * - We know there will always be somewhere between one and three extra 2333 * descriptors uploaded. 2334 * 2335 * - We know the desired received frame will always be at the end of the 2336 * total data upload. 2337 * 2338 * - We know the size of the desired received frame because it will be 2339 * provided in the length field of the status word in the last descriptor. 2340 * 2341 * Here's what we do: 2342 * 2343 * - When we allocate buffers for the receive ring, we bzero() them. 2344 * This means that we know that the buffer contents should be all 2345 * zeros, except for data uploaded by the chip. 2346 * 2347 * - We also force the PNIC chip to upload frames that include the 2348 * ethernet CRC at the end. 2349 * 2350 * - We gather all of the bogus frame data into a single buffer. 2351 * 2352 * - We then position a pointer at the end of this buffer and scan 2353 * backwards until we encounter the first non-zero byte of data. 2354 * This is the end of the received frame. We know we will encounter 2355 * some data at the end of the frame because the CRC will always be 2356 * there, so even if the sender transmits a packet of all zeros, 2357 * we won't be fooled. 2358 * 2359 * - We know the size of the actual received frame, so we subtract 2360 * that value from the current pointer location. This brings us 2361 * to the start of the actual received packet. 2362 * 2363 * - We copy this into an mbuf and pass it on, along with the actual 2364 * frame length. 2365 * 2366 * The performance hit is tremendous, but it beats dropping frames all 2367 * the time. 2368 */ 2369 2370 #define DC_WHOLEFRAME (DC_RXSTAT_FIRSTFRAG|DC_RXSTAT_LASTFRAG) 2371 static void dc_pnic_rx_bug_war(sc, idx) 2372 struct dc_softc *sc; 2373 int idx; 2374 { 2375 struct dc_desc *cur_rx; 2376 struct dc_desc *c = NULL; 2377 struct mbuf *m = NULL; 2378 unsigned char *ptr; 2379 int i, total_len; 2380 u_int32_t rxstat = 0; 2381 2382 i = sc->dc_pnic_rx_bug_save; 2383 cur_rx = &sc->dc_ldata->dc_rx_list[idx]; 2384 ptr = sc->dc_pnic_rx_buf; 2385 bzero(ptr, sizeof(DC_RXLEN * 5)); 2386 2387 /* Copy all the bytes from the bogus buffers. */ 2388 while (1) { 2389 c = &sc->dc_ldata->dc_rx_list[i]; 2390 rxstat = c->dc_status; 2391 m = sc->dc_cdata.dc_rx_chain[i]; 2392 bcopy(mtod(m, char *), ptr, DC_RXLEN); 2393 ptr += DC_RXLEN; 2394 /* If this is the last buffer, break out. */ 2395 if (i == idx || rxstat & DC_RXSTAT_LASTFRAG) 2396 break; 2397 dc_newbuf(sc, i, m); 2398 DC_INC(i, DC_RX_LIST_CNT); 2399 } 2400 2401 /* Find the length of the actual receive frame. */ 2402 total_len = DC_RXBYTES(rxstat); 2403 2404 /* Scan backwards until we hit a non-zero byte. */ 2405 while(*ptr == 0x00) 2406 ptr--; 2407 2408 /* Round off. */ 2409 if ((uintptr_t)(ptr) & 0x3) 2410 ptr -= 1; 2411 2412 /* Now find the start of the frame. */ 2413 ptr -= total_len; 2414 if (ptr < sc->dc_pnic_rx_buf) 2415 ptr = sc->dc_pnic_rx_buf; 2416 2417 /* 2418 * Now copy the salvaged frame to the last mbuf and fake up 2419 * the status word to make it look like a successful 2420 * frame reception. 2421 */ 2422 dc_newbuf(sc, i, m); 2423 bcopy(ptr, mtod(m, char *), total_len); 2424 cur_rx->dc_status = rxstat | DC_RXSTAT_FIRSTFRAG; 2425 2426 return; 2427 } 2428 2429 /* 2430 * This routine searches the RX ring for dirty descriptors in the 2431 * event that the rxeof routine falls out of sync with the chip's 2432 * current descriptor pointer. This may happen sometimes as a result 2433 * of a "no RX buffer available" condition that happens when the chip 2434 * consumes all of the RX buffers before the driver has a chance to 2435 * process the RX ring. This routine may need to be called more than 2436 * once to bring the driver back in sync with the chip, however we 2437 * should still be getting RX DONE interrupts to drive the search 2438 * for new packets in the RX ring, so we should catch up eventually. 2439 */ 2440 static int dc_rx_resync(sc) 2441 struct dc_softc *sc; 2442 { 2443 int i, pos; 2444 struct dc_desc *cur_rx; 2445 2446 pos = sc->dc_cdata.dc_rx_prod; 2447 2448 for (i = 0; i < DC_RX_LIST_CNT; i++) { 2449 cur_rx = &sc->dc_ldata->dc_rx_list[pos]; 2450 if (!(cur_rx->dc_status & DC_RXSTAT_OWN)) 2451 break; 2452 DC_INC(pos, DC_RX_LIST_CNT); 2453 } 2454 2455 /* If the ring really is empty, then just return. */ 2456 if (i == DC_RX_LIST_CNT) 2457 return(0); 2458 2459 /* We've fallen behing the chip: catch it. */ 2460 sc->dc_cdata.dc_rx_prod = pos; 2461 2462 return(EAGAIN); 2463 } 2464 2465 /* 2466 * A frame has been uploaded: pass the resulting mbuf chain up to 2467 * the higher level protocols. 2468 */ 2469 static void dc_rxeof(sc) 2470 struct dc_softc *sc; 2471 { 2472 struct ether_header *eh; 2473 struct mbuf *m; 2474 struct ifnet *ifp; 2475 struct dc_desc *cur_rx; 2476 int i, total_len = 0; 2477 u_int32_t rxstat; 2478 2479 ifp = &sc->arpcom.ac_if; 2480 i = sc->dc_cdata.dc_rx_prod; 2481 2482 while(!(sc->dc_ldata->dc_rx_list[i].dc_status & DC_RXSTAT_OWN)) { 2483 2484 #ifdef DEVICE_POLLING 2485 if (ifp->if_ipending & IFF_POLLING) { 2486 if (sc->rxcycles <= 0) 2487 break; 2488 sc->rxcycles--; 2489 } 2490 #endif /* DEVICE_POLLING */ 2491 cur_rx = &sc->dc_ldata->dc_rx_list[i]; 2492 rxstat = cur_rx->dc_status; 2493 m = sc->dc_cdata.dc_rx_chain[i]; 2494 total_len = DC_RXBYTES(rxstat); 2495 2496 if (sc->dc_flags & DC_PNIC_RX_BUG_WAR) { 2497 if ((rxstat & DC_WHOLEFRAME) != DC_WHOLEFRAME) { 2498 if (rxstat & DC_RXSTAT_FIRSTFRAG) 2499 sc->dc_pnic_rx_bug_save = i; 2500 if ((rxstat & DC_RXSTAT_LASTFRAG) == 0) { 2501 DC_INC(i, DC_RX_LIST_CNT); 2502 continue; 2503 } 2504 dc_pnic_rx_bug_war(sc, i); 2505 rxstat = cur_rx->dc_status; 2506 total_len = DC_RXBYTES(rxstat); 2507 } 2508 } 2509 2510 sc->dc_cdata.dc_rx_chain[i] = NULL; 2511 2512 /* 2513 * If an error occurs, update stats, clear the 2514 * status word and leave the mbuf cluster in place: 2515 * it should simply get re-used next time this descriptor 2516 * comes up in the ring. However, don't report long 2517 * frames as errors since they could be vlans 2518 */ 2519 if ((rxstat & DC_RXSTAT_RXERR)){ 2520 if (!(rxstat & DC_RXSTAT_GIANT) || 2521 (rxstat & (DC_RXSTAT_CRCERR | DC_RXSTAT_DRIBBLE | 2522 DC_RXSTAT_MIIERE | DC_RXSTAT_COLLSEEN | 2523 DC_RXSTAT_RUNT | DC_RXSTAT_DE))) { 2524 ifp->if_ierrors++; 2525 if (rxstat & DC_RXSTAT_COLLSEEN) 2526 ifp->if_collisions++; 2527 dc_newbuf(sc, i, m); 2528 if (rxstat & DC_RXSTAT_CRCERR) { 2529 DC_INC(i, DC_RX_LIST_CNT); 2530 continue; 2531 } else { 2532 dc_init(sc); 2533 return; 2534 } 2535 } 2536 } 2537 2538 /* No errors; receive the packet. */ 2539 total_len -= ETHER_CRC_LEN; 2540 #ifdef __i386__ 2541 /* 2542 * On the x86 we do not have alignment problems, so try to 2543 * allocate a new buffer for the receive ring, and pass up 2544 * the one where the packet is already, saving the expensive 2545 * copy done in m_devget(). 2546 * If we are on an architecture with alignment problems, or 2547 * if the allocation fails, then use m_devget and leave the 2548 * existing buffer in the receive ring. 2549 */ 2550 if (dc_quick && dc_newbuf(sc, i, NULL) == 0) { 2551 m->m_pkthdr.rcvif = ifp; 2552 m->m_pkthdr.len = m->m_len = total_len; 2553 DC_INC(i, DC_RX_LIST_CNT); 2554 } else 2555 #endif 2556 { 2557 struct mbuf *m0; 2558 2559 m0 = m_devget(mtod(m, char *), total_len, 2560 ETHER_ALIGN, ifp, NULL); 2561 dc_newbuf(sc, i, m); 2562 DC_INC(i, DC_RX_LIST_CNT); 2563 if (m0 == NULL) { 2564 ifp->if_ierrors++; 2565 continue; 2566 } 2567 m = m0; 2568 } 2569 2570 ifp->if_ipackets++; 2571 eh = mtod(m, struct ether_header *); 2572 2573 /* Remove header from mbuf and pass it on. */ 2574 m_adj(m, sizeof(struct ether_header)); 2575 ether_input(ifp, eh, m); 2576 } 2577 2578 sc->dc_cdata.dc_rx_prod = i; 2579 } 2580 2581 /* 2582 * A frame was downloaded to the chip. It's safe for us to clean up 2583 * the list buffers. 2584 */ 2585 2586 static void dc_txeof(sc) 2587 struct dc_softc *sc; 2588 { 2589 struct dc_desc *cur_tx = NULL; 2590 struct ifnet *ifp; 2591 int idx; 2592 2593 ifp = &sc->arpcom.ac_if; 2594 2595 /* Clear the timeout timer. */ 2596 ifp->if_timer = 0; 2597 2598 /* 2599 * Go through our tx list and free mbufs for those 2600 * frames that have been transmitted. 2601 */ 2602 idx = sc->dc_cdata.dc_tx_cons; 2603 while(idx != sc->dc_cdata.dc_tx_prod) { 2604 u_int32_t txstat; 2605 2606 cur_tx = &sc->dc_ldata->dc_tx_list[idx]; 2607 txstat = cur_tx->dc_status; 2608 2609 if (txstat & DC_TXSTAT_OWN) 2610 break; 2611 2612 if (!(cur_tx->dc_ctl & DC_TXCTL_LASTFRAG) || 2613 cur_tx->dc_ctl & DC_TXCTL_SETUP) { 2614 sc->dc_cdata.dc_tx_cnt--; 2615 if (cur_tx->dc_ctl & DC_TXCTL_SETUP) { 2616 /* 2617 * Yes, the PNIC is so brain damaged 2618 * that it will sometimes generate a TX 2619 * underrun error while DMAing the RX 2620 * filter setup frame. If we detect this, 2621 * we have to send the setup frame again, 2622 * or else the filter won't be programmed 2623 * correctly. 2624 */ 2625 if (DC_IS_PNIC(sc)) { 2626 if (txstat & DC_TXSTAT_ERRSUM) 2627 dc_setfilt(sc); 2628 } 2629 sc->dc_cdata.dc_tx_chain[idx] = NULL; 2630 } 2631 DC_INC(idx, DC_TX_LIST_CNT); 2632 continue; 2633 } 2634 2635 if (DC_IS_XIRCOM(sc) || DC_IS_CONEXANT(sc)) { 2636 /* 2637 * XXX: Why does my Xircom taunt me so? 2638 * For some reason it likes setting the CARRLOST flag 2639 * even when the carrier is there. wtf?!? 2640 * Who knows, but Conexant chips have the 2641 * same problem. Maybe they took lessons 2642 * from Xircom. 2643 */ 2644 if (/*sc->dc_type == DC_TYPE_21143 &&*/ 2645 sc->dc_pmode == DC_PMODE_MII && 2646 ((txstat & 0xFFFF) & ~(DC_TXSTAT_ERRSUM| 2647 DC_TXSTAT_NOCARRIER))) 2648 txstat &= ~DC_TXSTAT_ERRSUM; 2649 } else { 2650 if (/*sc->dc_type == DC_TYPE_21143 &&*/ 2651 sc->dc_pmode == DC_PMODE_MII && 2652 ((txstat & 0xFFFF) & ~(DC_TXSTAT_ERRSUM| 2653 DC_TXSTAT_NOCARRIER|DC_TXSTAT_CARRLOST))) 2654 txstat &= ~DC_TXSTAT_ERRSUM; 2655 } 2656 2657 if (txstat & DC_TXSTAT_ERRSUM) { 2658 ifp->if_oerrors++; 2659 if (txstat & DC_TXSTAT_EXCESSCOLL) 2660 ifp->if_collisions++; 2661 if (txstat & DC_TXSTAT_LATECOLL) 2662 ifp->if_collisions++; 2663 if (!(txstat & DC_TXSTAT_UNDERRUN)) { 2664 dc_init(sc); 2665 return; 2666 } 2667 } 2668 2669 ifp->if_collisions += (txstat & DC_TXSTAT_COLLCNT) >> 3; 2670 2671 ifp->if_opackets++; 2672 if (sc->dc_cdata.dc_tx_chain[idx] != NULL) { 2673 m_freem(sc->dc_cdata.dc_tx_chain[idx]); 2674 sc->dc_cdata.dc_tx_chain[idx] = NULL; 2675 } 2676 2677 sc->dc_cdata.dc_tx_cnt--; 2678 DC_INC(idx, DC_TX_LIST_CNT); 2679 } 2680 2681 sc->dc_cdata.dc_tx_cons = idx; 2682 if (cur_tx != NULL) 2683 ifp->if_flags &= ~IFF_OACTIVE; 2684 2685 return; 2686 } 2687 2688 static void dc_tick(xsc) 2689 void *xsc; 2690 { 2691 struct dc_softc *sc; 2692 struct mii_data *mii; 2693 struct ifnet *ifp; 2694 u_int32_t r; 2695 2696 sc = xsc; 2697 DC_LOCK(sc); 2698 ifp = &sc->arpcom.ac_if; 2699 mii = device_get_softc(sc->dc_miibus); 2700 2701 if (sc->dc_flags & DC_REDUCED_MII_POLL) { 2702 if (sc->dc_flags & DC_21143_NWAY) { 2703 r = CSR_READ_4(sc, DC_10BTSTAT); 2704 if (IFM_SUBTYPE(mii->mii_media_active) == 2705 IFM_100_TX && (r & DC_TSTAT_LS100)) { 2706 sc->dc_link = 0; 2707 mii_mediachg(mii); 2708 } 2709 if (IFM_SUBTYPE(mii->mii_media_active) == 2710 IFM_10_T && (r & DC_TSTAT_LS10)) { 2711 sc->dc_link = 0; 2712 mii_mediachg(mii); 2713 } 2714 if (sc->dc_link == 0) 2715 mii_tick(mii); 2716 } else { 2717 r = CSR_READ_4(sc, DC_ISR); 2718 if ((r & DC_ISR_RX_STATE) == DC_RXSTATE_WAIT && 2719 sc->dc_cdata.dc_tx_cnt == 0) 2720 mii_tick(mii); 2721 if (!(mii->mii_media_status & IFM_ACTIVE)) 2722 sc->dc_link = 0; 2723 } 2724 } else 2725 mii_tick(mii); 2726 2727 /* 2728 * When the init routine completes, we expect to be able to send 2729 * packets right away, and in fact the network code will send a 2730 * gratuitous ARP the moment the init routine marks the interface 2731 * as running. However, even though the MAC may have been initialized, 2732 * there may be a delay of a few seconds before the PHY completes 2733 * autonegotiation and the link is brought up. Any transmissions 2734 * made during that delay will be lost. Dealing with this is tricky: 2735 * we can't just pause in the init routine while waiting for the 2736 * PHY to come ready since that would bring the whole system to 2737 * a screeching halt for several seconds. 2738 * 2739 * What we do here is prevent the TX start routine from sending 2740 * any packets until a link has been established. After the 2741 * interface has been initialized, the tick routine will poll 2742 * the state of the PHY until the IFM_ACTIVE flag is set. Until 2743 * that time, packets will stay in the send queue, and once the 2744 * link comes up, they will be flushed out to the wire. 2745 */ 2746 if (!sc->dc_link && mii->mii_media_status & IFM_ACTIVE && 2747 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) { 2748 sc->dc_link++; 2749 if (ifp->if_snd.ifq_head != NULL) 2750 dc_start(ifp); 2751 } 2752 2753 if (sc->dc_flags & DC_21143_NWAY && !sc->dc_link) 2754 callout_reset(&sc->dc_stat_ch, hz/10, dc_tick, sc); 2755 else 2756 callout_reset(&sc->dc_stat_ch, hz, dc_tick, sc); 2757 2758 DC_UNLOCK(sc); 2759 2760 return; 2761 } 2762 2763 /* 2764 * A transmit underrun has occurred. Back off the transmit threshold, 2765 * or switch to store and forward mode if we have to. 2766 */ 2767 static void dc_tx_underrun(sc) 2768 struct dc_softc *sc; 2769 { 2770 u_int32_t isr; 2771 int i; 2772 2773 if (DC_IS_DAVICOM(sc)) 2774 dc_init(sc); 2775 2776 if (DC_IS_INTEL(sc)) { 2777 /* 2778 * The real 21143 requires that the transmitter be idle 2779 * in order to change the transmit threshold or store 2780 * and forward state. 2781 */ 2782 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_TX_ON); 2783 2784 for (i = 0; i < DC_TIMEOUT; i++) { 2785 isr = CSR_READ_4(sc, DC_ISR); 2786 if (isr & DC_ISR_TX_IDLE) 2787 break; 2788 DELAY(10); 2789 } 2790 if (i == DC_TIMEOUT) { 2791 printf("dc%d: failed to force tx to idle state\n", 2792 sc->dc_unit); 2793 dc_init(sc); 2794 } 2795 } 2796 2797 printf("dc%d: TX underrun -- ", sc->dc_unit); 2798 sc->dc_txthresh += DC_TXTHRESH_INC; 2799 if (sc->dc_txthresh > DC_TXTHRESH_MAX) { 2800 printf("using store and forward mode\n"); 2801 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_STORENFWD); 2802 } else { 2803 printf("increasing TX threshold\n"); 2804 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_TX_THRESH); 2805 DC_SETBIT(sc, DC_NETCFG, sc->dc_txthresh); 2806 } 2807 2808 if (DC_IS_INTEL(sc)) 2809 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_TX_ON); 2810 2811 return; 2812 } 2813 2814 #ifdef DEVICE_POLLING 2815 static poll_handler_t dc_poll; 2816 2817 static void 2818 dc_poll(struct ifnet *ifp, enum poll_cmd cmd, int count) 2819 { 2820 struct dc_softc *sc = ifp->if_softc; 2821 2822 if (cmd == POLL_DEREGISTER) { /* final call, enable interrupts */ 2823 /* Re-enable interrupts. */ 2824 CSR_WRITE_4(sc, DC_IMR, DC_INTRS); 2825 return; 2826 } 2827 sc->rxcycles = count; 2828 dc_rxeof(sc); 2829 dc_txeof(sc); 2830 if (ifp->if_snd.ifq_head != NULL && !(ifp->if_flags & IFF_OACTIVE)) 2831 dc_start(ifp); 2832 2833 if (cmd == POLL_AND_CHECK_STATUS) { /* also check status register */ 2834 u_int32_t status; 2835 2836 status = CSR_READ_4(sc, DC_ISR); 2837 status &= (DC_ISR_RX_WATDOGTIMEO|DC_ISR_RX_NOBUF| 2838 DC_ISR_TX_NOBUF|DC_ISR_TX_IDLE|DC_ISR_TX_UNDERRUN| 2839 DC_ISR_BUS_ERR); 2840 if (!status) 2841 return; 2842 /* ack what we have */ 2843 CSR_WRITE_4(sc, DC_ISR, status); 2844 2845 if (status & (DC_ISR_RX_WATDOGTIMEO|DC_ISR_RX_NOBUF)) { 2846 u_int32_t r = CSR_READ_4(sc, DC_FRAMESDISCARDED); 2847 ifp->if_ierrors += (r & 0xffff) + ((r >> 17) & 0x7ff); 2848 2849 if (dc_rx_resync(sc)) 2850 dc_rxeof(sc); 2851 } 2852 /* restart transmit unit if necessary */ 2853 if (status & DC_ISR_TX_IDLE && sc->dc_cdata.dc_tx_cnt) 2854 CSR_WRITE_4(sc, DC_TXSTART, 0xFFFFFFFF); 2855 2856 if (status & DC_ISR_TX_UNDERRUN) 2857 dc_tx_underrun(sc); 2858 2859 if (status & DC_ISR_BUS_ERR) { 2860 printf("dc_poll: dc%d bus error\n", sc->dc_unit); 2861 dc_reset(sc); 2862 dc_init(sc); 2863 } 2864 } 2865 } 2866 #endif /* DEVICE_POLLING */ 2867 2868 static void dc_intr(arg) 2869 void *arg; 2870 { 2871 struct dc_softc *sc; 2872 struct ifnet *ifp; 2873 u_int32_t status; 2874 2875 sc = arg; 2876 2877 if ((CSR_READ_4(sc, DC_ISR) & DC_INTRS) == 0) 2878 return; 2879 2880 DC_LOCK(sc); 2881 ifp = &sc->arpcom.ac_if; 2882 #ifdef DEVICE_POLLING 2883 if (ifp->if_ipending & IFF_POLLING) 2884 goto done; 2885 if (ether_poll_register(dc_poll, ifp)) { /* ok, disable interrupts */ 2886 CSR_WRITE_4(sc, DC_IMR, 0x00000000); 2887 goto done; 2888 } 2889 #endif /* DEVICE_POLLING */ 2890 2891 /* Suppress unwanted interrupts */ 2892 if (!(ifp->if_flags & IFF_UP)) { 2893 if (CSR_READ_4(sc, DC_ISR) & DC_INTRS) 2894 dc_stop(sc); 2895 DC_UNLOCK(sc); 2896 return; 2897 } 2898 2899 /* Disable interrupts. */ 2900 CSR_WRITE_4(sc, DC_IMR, 0x00000000); 2901 2902 while(((status = CSR_READ_4(sc, DC_ISR)) & DC_INTRS) 2903 && status != 0xFFFFFFFF) { 2904 2905 CSR_WRITE_4(sc, DC_ISR, status); 2906 2907 if (status & DC_ISR_RX_OK) { 2908 int curpkts; 2909 curpkts = ifp->if_ipackets; 2910 dc_rxeof(sc); 2911 if (curpkts == ifp->if_ipackets) { 2912 while(dc_rx_resync(sc)) 2913 dc_rxeof(sc); 2914 } 2915 } 2916 2917 if (status & (DC_ISR_TX_OK|DC_ISR_TX_NOBUF)) 2918 dc_txeof(sc); 2919 2920 if (status & DC_ISR_TX_IDLE) { 2921 dc_txeof(sc); 2922 if (sc->dc_cdata.dc_tx_cnt) { 2923 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_TX_ON); 2924 CSR_WRITE_4(sc, DC_TXSTART, 0xFFFFFFFF); 2925 } 2926 } 2927 2928 if (status & DC_ISR_TX_UNDERRUN) 2929 dc_tx_underrun(sc); 2930 2931 if ((status & DC_ISR_RX_WATDOGTIMEO) 2932 || (status & DC_ISR_RX_NOBUF)) { 2933 int curpkts; 2934 curpkts = ifp->if_ipackets; 2935 dc_rxeof(sc); 2936 if (curpkts == ifp->if_ipackets) { 2937 while(dc_rx_resync(sc)) 2938 dc_rxeof(sc); 2939 } 2940 } 2941 2942 if (status & DC_ISR_BUS_ERR) { 2943 dc_reset(sc); 2944 dc_init(sc); 2945 } 2946 } 2947 2948 /* Re-enable interrupts. */ 2949 CSR_WRITE_4(sc, DC_IMR, DC_INTRS); 2950 2951 if (ifp->if_snd.ifq_head != NULL) 2952 dc_start(ifp); 2953 2954 #ifdef DEVICE_POLLING 2955 done: 2956 #endif /* DEVICE_POLLING */ 2957 2958 DC_UNLOCK(sc); 2959 2960 return; 2961 } 2962 2963 /* 2964 * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data 2965 * pointers to the fragment pointers. 2966 */ 2967 static int dc_encap(sc, m_head, txidx) 2968 struct dc_softc *sc; 2969 struct mbuf *m_head; 2970 u_int32_t *txidx; 2971 { 2972 struct dc_desc *f = NULL; 2973 struct mbuf *m; 2974 int frag, cur, cnt = 0; 2975 2976 /* 2977 * Start packing the mbufs in this chain into 2978 * the fragment pointers. Stop when we run out 2979 * of fragments or hit the end of the mbuf chain. 2980 */ 2981 m = m_head; 2982 cur = frag = *txidx; 2983 2984 for (m = m_head; m != NULL; m = m->m_next) { 2985 if (m->m_len != 0) { 2986 if (sc->dc_flags & DC_TX_ADMTEK_WAR) { 2987 if (*txidx != sc->dc_cdata.dc_tx_prod && 2988 frag == (DC_TX_LIST_CNT - 1)) 2989 return(ENOBUFS); 2990 } 2991 if ((DC_TX_LIST_CNT - 2992 (sc->dc_cdata.dc_tx_cnt + cnt)) < 5) 2993 return(ENOBUFS); 2994 2995 f = &sc->dc_ldata->dc_tx_list[frag]; 2996 f->dc_ctl = DC_TXCTL_TLINK | m->m_len; 2997 if (cnt == 0) { 2998 f->dc_status = 0; 2999 f->dc_ctl |= DC_TXCTL_FIRSTFRAG; 3000 } else 3001 f->dc_status = DC_TXSTAT_OWN; 3002 f->dc_data = vtophys(mtod(m, vm_offset_t)); 3003 cur = frag; 3004 DC_INC(frag, DC_TX_LIST_CNT); 3005 cnt++; 3006 } 3007 } 3008 3009 if (m != NULL) 3010 return(ENOBUFS); 3011 3012 sc->dc_cdata.dc_tx_cnt += cnt; 3013 sc->dc_cdata.dc_tx_chain[cur] = m_head; 3014 sc->dc_ldata->dc_tx_list[cur].dc_ctl |= DC_TXCTL_LASTFRAG; 3015 if (sc->dc_flags & DC_TX_INTR_FIRSTFRAG) 3016 sc->dc_ldata->dc_tx_list[*txidx].dc_ctl |= DC_TXCTL_FINT; 3017 if (sc->dc_flags & DC_TX_INTR_ALWAYS) 3018 sc->dc_ldata->dc_tx_list[cur].dc_ctl |= DC_TXCTL_FINT; 3019 if (sc->dc_flags & DC_TX_USE_TX_INTR && sc->dc_cdata.dc_tx_cnt > 64) 3020 sc->dc_ldata->dc_tx_list[cur].dc_ctl |= DC_TXCTL_FINT; 3021 sc->dc_ldata->dc_tx_list[*txidx].dc_status = DC_TXSTAT_OWN; 3022 *txidx = frag; 3023 3024 return(0); 3025 } 3026 3027 /* 3028 * Coalesce an mbuf chain into a single mbuf cluster buffer. 3029 * Needed for some really badly behaved chips that just can't 3030 * do scatter/gather correctly. 3031 */ 3032 static int dc_coal(sc, m_head) 3033 struct dc_softc *sc; 3034 struct mbuf **m_head; 3035 { 3036 struct mbuf *m_new, *m; 3037 3038 m = *m_head; 3039 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 3040 if (m_new == NULL) 3041 return(ENOBUFS); 3042 if (m->m_pkthdr.len > MHLEN) { 3043 MCLGET(m_new, M_DONTWAIT); 3044 if (!(m_new->m_flags & M_EXT)) { 3045 m_freem(m_new); 3046 return(ENOBUFS); 3047 } 3048 } 3049 m_copydata(m, 0, m->m_pkthdr.len, mtod(m_new, caddr_t)); 3050 m_new->m_pkthdr.len = m_new->m_len = m->m_pkthdr.len; 3051 m_freem(m); 3052 *m_head = m_new; 3053 3054 return(0); 3055 } 3056 3057 /* 3058 * Main transmit routine. To avoid having to do mbuf copies, we put pointers 3059 * to the mbuf data regions directly in the transmit lists. We also save a 3060 * copy of the pointers since the transmit list fragment pointers are 3061 * physical addresses. 3062 */ 3063 3064 static void dc_start(ifp) 3065 struct ifnet *ifp; 3066 { 3067 struct dc_softc *sc; 3068 struct mbuf *m_head = NULL; 3069 int idx; 3070 3071 sc = ifp->if_softc; 3072 3073 DC_LOCK(sc); 3074 3075 if (!sc->dc_link && ifp->if_snd.ifq_len < 10) { 3076 DC_UNLOCK(sc); 3077 return; 3078 } 3079 3080 if (ifp->if_flags & IFF_OACTIVE) { 3081 DC_UNLOCK(sc); 3082 return; 3083 } 3084 3085 idx = sc->dc_cdata.dc_tx_prod; 3086 3087 while(sc->dc_cdata.dc_tx_chain[idx] == NULL) { 3088 IF_DEQUEUE(&ifp->if_snd, m_head); 3089 if (m_head == NULL) 3090 break; 3091 3092 if (sc->dc_flags & DC_TX_COALESCE && 3093 (m_head->m_next != NULL || 3094 sc->dc_flags & DC_TX_ALIGN)) { 3095 if (dc_coal(sc, &m_head)) { 3096 IF_PREPEND(&ifp->if_snd, m_head); 3097 ifp->if_flags |= IFF_OACTIVE; 3098 break; 3099 } 3100 } 3101 3102 if (dc_encap(sc, m_head, &idx)) { 3103 IF_PREPEND(&ifp->if_snd, m_head); 3104 ifp->if_flags |= IFF_OACTIVE; 3105 break; 3106 } 3107 3108 /* 3109 * If there's a BPF listener, bounce a copy of this frame 3110 * to him. 3111 */ 3112 if (ifp->if_bpf) 3113 bpf_mtap(ifp, m_head); 3114 3115 if (sc->dc_flags & DC_TX_ONE) { 3116 ifp->if_flags |= IFF_OACTIVE; 3117 break; 3118 } 3119 } 3120 3121 /* Transmit */ 3122 sc->dc_cdata.dc_tx_prod = idx; 3123 if (!(sc->dc_flags & DC_TX_POLL)) 3124 CSR_WRITE_4(sc, DC_TXSTART, 0xFFFFFFFF); 3125 3126 /* 3127 * Set a timeout in case the chip goes out to lunch. 3128 */ 3129 ifp->if_timer = 5; 3130 3131 DC_UNLOCK(sc); 3132 3133 return; 3134 } 3135 3136 static void dc_init(xsc) 3137 void *xsc; 3138 { 3139 struct dc_softc *sc = xsc; 3140 struct ifnet *ifp = &sc->arpcom.ac_if; 3141 struct mii_data *mii; 3142 3143 DC_LOCK(sc); 3144 3145 mii = device_get_softc(sc->dc_miibus); 3146 3147 /* 3148 * Cancel pending I/O and free all RX/TX buffers. 3149 */ 3150 dc_stop(sc); 3151 dc_reset(sc); 3152 3153 /* 3154 * Set cache alignment and burst length. 3155 */ 3156 if (DC_IS_ASIX(sc) || DC_IS_DAVICOM(sc)) 3157 CSR_WRITE_4(sc, DC_BUSCTL, 0); 3158 else 3159 CSR_WRITE_4(sc, DC_BUSCTL, DC_BUSCTL_MRME|DC_BUSCTL_MRLE); 3160 /* 3161 * Evenly share the bus between receive and transmit process. 3162 */ 3163 if (DC_IS_INTEL(sc)) 3164 DC_SETBIT(sc, DC_BUSCTL, DC_BUSCTL_ARBITRATION); 3165 if (DC_IS_DAVICOM(sc) || DC_IS_INTEL(sc)) { 3166 DC_SETBIT(sc, DC_BUSCTL, DC_BURSTLEN_USECA); 3167 } else { 3168 DC_SETBIT(sc, DC_BUSCTL, DC_BURSTLEN_16LONG); 3169 } 3170 if (sc->dc_flags & DC_TX_POLL) 3171 DC_SETBIT(sc, DC_BUSCTL, DC_TXPOLL_1); 3172 switch(sc->dc_cachesize) { 3173 case 32: 3174 DC_SETBIT(sc, DC_BUSCTL, DC_CACHEALIGN_32LONG); 3175 break; 3176 case 16: 3177 DC_SETBIT(sc, DC_BUSCTL, DC_CACHEALIGN_16LONG); 3178 break; 3179 case 8: 3180 DC_SETBIT(sc, DC_BUSCTL, DC_CACHEALIGN_8LONG); 3181 break; 3182 case 0: 3183 default: 3184 DC_SETBIT(sc, DC_BUSCTL, DC_CACHEALIGN_NONE); 3185 break; 3186 } 3187 3188 if (sc->dc_flags & DC_TX_STORENFWD) 3189 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_STORENFWD); 3190 else { 3191 if (sc->dc_txthresh > DC_TXTHRESH_MAX) { 3192 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_STORENFWD); 3193 } else { 3194 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_STORENFWD); 3195 DC_SETBIT(sc, DC_NETCFG, sc->dc_txthresh); 3196 } 3197 } 3198 3199 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_NO_RXCRC); 3200 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_TX_BACKOFF); 3201 3202 if (DC_IS_MACRONIX(sc) || DC_IS_PNICII(sc)) { 3203 /* 3204 * The app notes for the 98713 and 98715A say that 3205 * in order to have the chips operate properly, a magic 3206 * number must be written to CSR16. Macronix does not 3207 * document the meaning of these bits so there's no way 3208 * to know exactly what they do. The 98713 has a magic 3209 * number all its own; the rest all use a different one. 3210 */ 3211 DC_CLRBIT(sc, DC_MX_MAGICPACKET, 0xFFFF0000); 3212 if (sc->dc_type == DC_TYPE_98713) 3213 DC_SETBIT(sc, DC_MX_MAGICPACKET, DC_MX_MAGIC_98713); 3214 else 3215 DC_SETBIT(sc, DC_MX_MAGICPACKET, DC_MX_MAGIC_98715); 3216 } 3217 3218 if (DC_IS_XIRCOM(sc)) { 3219 /* 3220 * setup General Purpose Port mode and data so the tulip 3221 * can talk to the MII. 3222 */ 3223 CSR_WRITE_4(sc, DC_SIAGP, DC_SIAGP_WRITE_EN | DC_SIAGP_INT1_EN | 3224 DC_SIAGP_MD_GP2_OUTPUT | DC_SIAGP_MD_GP0_OUTPUT); 3225 DELAY(10); 3226 CSR_WRITE_4(sc, DC_SIAGP, DC_SIAGP_INT1_EN | 3227 DC_SIAGP_MD_GP2_OUTPUT | DC_SIAGP_MD_GP0_OUTPUT); 3228 DELAY(10); 3229 } 3230 3231 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_TX_THRESH); 3232 DC_SETBIT(sc, DC_NETCFG, DC_TXTHRESH_MIN); 3233 3234 /* Init circular RX list. */ 3235 if (dc_list_rx_init(sc) == ENOBUFS) { 3236 printf("dc%d: initialization failed: no " 3237 "memory for rx buffers\n", sc->dc_unit); 3238 dc_stop(sc); 3239 DC_UNLOCK(sc); 3240 return; 3241 } 3242 3243 /* 3244 * Init tx descriptors. 3245 */ 3246 dc_list_tx_init(sc); 3247 3248 /* 3249 * Load the address of the RX list. 3250 */ 3251 CSR_WRITE_4(sc, DC_RXADDR, vtophys(&sc->dc_ldata->dc_rx_list[0])); 3252 CSR_WRITE_4(sc, DC_TXADDR, vtophys(&sc->dc_ldata->dc_tx_list[0])); 3253 3254 /* 3255 * Enable interrupts. 3256 */ 3257 #ifdef DEVICE_POLLING 3258 /* 3259 * ... but only if we are not polling, and make sure they are off in 3260 * the case of polling. Some cards (e.g. fxp) turn interrupts on 3261 * after a reset. 3262 */ 3263 if (ifp->if_ipending & IFF_POLLING) 3264 CSR_WRITE_4(sc, DC_IMR, 0x00000000); 3265 else 3266 #endif 3267 CSR_WRITE_4(sc, DC_IMR, DC_INTRS); 3268 CSR_WRITE_4(sc, DC_ISR, 0xFFFFFFFF); 3269 3270 /* Enable transmitter. */ 3271 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_TX_ON); 3272 3273 /* 3274 * If this is an Intel 21143 and we're not using the 3275 * MII port, program the LED control pins so we get 3276 * link and activity indications. 3277 */ 3278 if (sc->dc_flags & DC_TULIP_LEDS) { 3279 CSR_WRITE_4(sc, DC_WATCHDOG, 3280 DC_WDOG_CTLWREN|DC_WDOG_LINK|DC_WDOG_ACTIVITY); 3281 CSR_WRITE_4(sc, DC_WATCHDOG, 0); 3282 } 3283 3284 /* 3285 * Load the RX/multicast filter. We do this sort of late 3286 * because the filter programming scheme on the 21143 and 3287 * some clones requires DMAing a setup frame via the TX 3288 * engine, and we need the transmitter enabled for that. 3289 */ 3290 dc_setfilt(sc); 3291 3292 /* Enable receiver. */ 3293 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_ON); 3294 CSR_WRITE_4(sc, DC_RXSTART, 0xFFFFFFFF); 3295 3296 mii_mediachg(mii); 3297 dc_setcfg(sc, sc->dc_if_media); 3298 3299 ifp->if_flags |= IFF_RUNNING; 3300 ifp->if_flags &= ~IFF_OACTIVE; 3301 3302 /* Don't start the ticker if this is a homePNA link. */ 3303 if (IFM_SUBTYPE(mii->mii_media.ifm_media) == IFM_homePNA) 3304 sc->dc_link = 1; 3305 else { 3306 if (sc->dc_flags & DC_21143_NWAY) 3307 callout_reset(&sc->dc_stat_ch, hz/10, dc_tick, sc); 3308 else 3309 callout_reset(&sc->dc_stat_ch, hz, dc_tick, sc); 3310 } 3311 3312 #ifdef SRM_MEDIA 3313 if(sc->dc_srm_media) { 3314 struct ifreq ifr; 3315 3316 ifr.ifr_media = sc->dc_srm_media; 3317 ifmedia_ioctl(ifp, &ifr, &mii->mii_media, SIOCSIFMEDIA); 3318 sc->dc_srm_media = 0; 3319 } 3320 #endif 3321 DC_UNLOCK(sc); 3322 return; 3323 } 3324 3325 /* 3326 * Set media options. 3327 */ 3328 static int dc_ifmedia_upd(ifp) 3329 struct ifnet *ifp; 3330 { 3331 struct dc_softc *sc; 3332 struct mii_data *mii; 3333 struct ifmedia *ifm; 3334 3335 sc = ifp->if_softc; 3336 mii = device_get_softc(sc->dc_miibus); 3337 mii_mediachg(mii); 3338 ifm = &mii->mii_media; 3339 3340 if (DC_IS_DAVICOM(sc) && 3341 IFM_SUBTYPE(ifm->ifm_media) == IFM_homePNA) 3342 dc_setcfg(sc, ifm->ifm_media); 3343 else 3344 sc->dc_link = 0; 3345 3346 return(0); 3347 } 3348 3349 /* 3350 * Report current media status. 3351 */ 3352 static void dc_ifmedia_sts(ifp, ifmr) 3353 struct ifnet *ifp; 3354 struct ifmediareq *ifmr; 3355 { 3356 struct dc_softc *sc; 3357 struct mii_data *mii; 3358 struct ifmedia *ifm; 3359 3360 sc = ifp->if_softc; 3361 mii = device_get_softc(sc->dc_miibus); 3362 mii_pollstat(mii); 3363 ifm = &mii->mii_media; 3364 if (DC_IS_DAVICOM(sc)) { 3365 if (IFM_SUBTYPE(ifm->ifm_media) == IFM_homePNA) { 3366 ifmr->ifm_active = ifm->ifm_media; 3367 ifmr->ifm_status = 0; 3368 return; 3369 } 3370 } 3371 ifmr->ifm_active = mii->mii_media_active; 3372 ifmr->ifm_status = mii->mii_media_status; 3373 3374 return; 3375 } 3376 3377 static int dc_ioctl(ifp, command, data) 3378 struct ifnet *ifp; 3379 u_long command; 3380 caddr_t data; 3381 { 3382 struct dc_softc *sc = ifp->if_softc; 3383 struct ifreq *ifr = (struct ifreq *) data; 3384 struct mii_data *mii; 3385 int error = 0; 3386 3387 DC_LOCK(sc); 3388 3389 switch(command) { 3390 case SIOCSIFADDR: 3391 case SIOCGIFADDR: 3392 case SIOCSIFMTU: 3393 error = ether_ioctl(ifp, command, data); 3394 break; 3395 case SIOCSIFFLAGS: 3396 if (ifp->if_flags & IFF_UP) { 3397 if (ifp->if_flags & IFF_RUNNING && 3398 ifp->if_flags & IFF_PROMISC && 3399 !(sc->dc_if_flags & IFF_PROMISC)) { 3400 dc_setfilt(sc); 3401 } else if (ifp->if_flags & IFF_RUNNING && 3402 !(ifp->if_flags & IFF_PROMISC) && 3403 sc->dc_if_flags & IFF_PROMISC) { 3404 dc_setfilt(sc); 3405 } else if (!(ifp->if_flags & IFF_RUNNING)) { 3406 sc->dc_txthresh = 0; 3407 dc_init(sc); 3408 } 3409 } else { 3410 if (ifp->if_flags & IFF_RUNNING) 3411 dc_stop(sc); 3412 } 3413 sc->dc_if_flags = ifp->if_flags; 3414 error = 0; 3415 break; 3416 case SIOCADDMULTI: 3417 case SIOCDELMULTI: 3418 dc_setfilt(sc); 3419 error = 0; 3420 break; 3421 case SIOCGIFMEDIA: 3422 case SIOCSIFMEDIA: 3423 mii = device_get_softc(sc->dc_miibus); 3424 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 3425 #ifdef SRM_MEDIA 3426 if (sc->dc_srm_media) 3427 sc->dc_srm_media = 0; 3428 #endif 3429 break; 3430 default: 3431 error = EINVAL; 3432 break; 3433 } 3434 3435 DC_UNLOCK(sc); 3436 3437 return(error); 3438 } 3439 3440 static void dc_watchdog(ifp) 3441 struct ifnet *ifp; 3442 { 3443 struct dc_softc *sc; 3444 3445 sc = ifp->if_softc; 3446 3447 DC_LOCK(sc); 3448 3449 ifp->if_oerrors++; 3450 printf("dc%d: watchdog timeout\n", sc->dc_unit); 3451 3452 dc_stop(sc); 3453 dc_reset(sc); 3454 dc_init(sc); 3455 3456 if (ifp->if_snd.ifq_head != NULL) 3457 dc_start(ifp); 3458 3459 DC_UNLOCK(sc); 3460 3461 return; 3462 } 3463 3464 /* 3465 * Stop the adapter and free any mbufs allocated to the 3466 * RX and TX lists. 3467 */ 3468 static void dc_stop(sc) 3469 struct dc_softc *sc; 3470 { 3471 register int i; 3472 struct ifnet *ifp; 3473 3474 DC_LOCK(sc); 3475 3476 ifp = &sc->arpcom.ac_if; 3477 ifp->if_timer = 0; 3478 3479 callout_stop(&sc->dc_stat_ch); 3480 3481 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 3482 #ifdef DEVICE_POLLING 3483 ether_poll_deregister(ifp); 3484 #endif 3485 3486 DC_CLRBIT(sc, DC_NETCFG, (DC_NETCFG_RX_ON|DC_NETCFG_TX_ON)); 3487 CSR_WRITE_4(sc, DC_IMR, 0x00000000); 3488 CSR_WRITE_4(sc, DC_TXADDR, 0x00000000); 3489 CSR_WRITE_4(sc, DC_RXADDR, 0x00000000); 3490 sc->dc_link = 0; 3491 3492 /* 3493 * Free data in the RX lists. 3494 */ 3495 for (i = 0; i < DC_RX_LIST_CNT; i++) { 3496 if (sc->dc_cdata.dc_rx_chain[i] != NULL) { 3497 m_freem(sc->dc_cdata.dc_rx_chain[i]); 3498 sc->dc_cdata.dc_rx_chain[i] = NULL; 3499 } 3500 } 3501 bzero((char *)&sc->dc_ldata->dc_rx_list, 3502 sizeof(sc->dc_ldata->dc_rx_list)); 3503 3504 /* 3505 * Free the TX list buffers. 3506 */ 3507 for (i = 0; i < DC_TX_LIST_CNT; i++) { 3508 if (sc->dc_cdata.dc_tx_chain[i] != NULL) { 3509 if (sc->dc_ldata->dc_tx_list[i].dc_ctl & 3510 DC_TXCTL_SETUP) { 3511 sc->dc_cdata.dc_tx_chain[i] = NULL; 3512 continue; 3513 } 3514 m_freem(sc->dc_cdata.dc_tx_chain[i]); 3515 sc->dc_cdata.dc_tx_chain[i] = NULL; 3516 } 3517 } 3518 3519 bzero((char *)&sc->dc_ldata->dc_tx_list, 3520 sizeof(sc->dc_ldata->dc_tx_list)); 3521 3522 DC_UNLOCK(sc); 3523 3524 return; 3525 } 3526 3527 /* 3528 * Stop all chip I/O so that the kernel's probe routines don't 3529 * get confused by errant DMAs when rebooting. 3530 */ 3531 static void dc_shutdown(dev) 3532 device_t dev; 3533 { 3534 struct dc_softc *sc; 3535 3536 sc = device_get_softc(dev); 3537 3538 dc_stop(sc); 3539 3540 return; 3541 } 3542