1 /* 2 * Copyright (c) 1997, 1998, 1999 3 * Bill Paul <wpaul@ee.columbia.edu>. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 3. All advertising materials mentioning features or use of this software 14 * must display the following acknowledgement: 15 * This product includes software developed by Bill Paul. 16 * 4. Neither the name of the author nor the names of any co-contributors 17 * may be used to endorse or promote products derived from this software 18 * without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30 * THE POSSIBILITY OF SUCH DAMAGE. 31 * 32 * $FreeBSD$ 33 */ 34 35 /* 36 * DEC "tulip" clone ethernet driver. Supports the DEC/Intel 21143 37 * series chips and several workalikes including the following: 38 * 39 * Macronix 98713/98715/98725 PMAC (www.macronix.com) 40 * Macronix/Lite-On 82c115 PNIC II (www.macronix.com) 41 * Lite-On 82c168/82c169 PNIC (www.litecom.com) 42 * ASIX Electronics AX88140A (www.asix.com.tw) 43 * ASIX Electronics AX88141 (www.asix.com.tw) 44 * ADMtek AL981 (www.admtek.com.tw) 45 * ADMtek AN985 (www.admtek.com.tw) 46 * Davicom DM9100, DM9102 (www.davicom8.com) 47 * 48 * Datasheets for the 21143 are available at developer.intel.com. 49 * Datasheets for the clone parts can be found at their respective sites. 50 * (Except for the PNIC; see www.freebsd.org/~wpaul/PNIC/pnic.ps.gz.) 51 * The PNIC II is essentially a Macronix 98715A chip; the only difference 52 * worth noting is that its multicast hash table is only 128 bits wide 53 * instead of 512. 54 * 55 * Written by Bill Paul <wpaul@ee.columbia.edu> 56 * Electrical Engineering Department 57 * Columbia University, New York City 58 */ 59 60 /* 61 * The Intel 21143 is the successor to the DEC 21140. It is basically 62 * the same as the 21140 but with a few new features. The 21143 supports 63 * three kinds of media attachments: 64 * 65 * o MII port, for 10Mbps and 100Mbps support and NWAY 66 * autonegotiation provided by an external PHY. 67 * o SYM port, for symbol mode 100Mbps support. 68 * o 10baseT port. 69 * o AUI/BNC port. 70 * 71 * The 100Mbps SYM port and 10baseT port can be used together in 72 * combination with the internal NWAY support to create a 10/100 73 * autosensing configuration. 74 * 75 * Knowing which media is available on a given card is tough: you're 76 * supposed to go slogging through the EEPROM looking for media 77 * description structures. Unfortunately, some card vendors that use 78 * the 21143 don't obey the DEC SROM spec correctly, which means that 79 * what you find in the EEPROM may not agree with reality. Fortunately, 80 * the 21143 provides us a way to get around this issue: lurking in 81 * PCI configuration space is the Configuration Wake-Up Command Register. 82 * This register is loaded with a value from the EEPROM when wake on LAN 83 * mode is enabled; this value tells us quite clearly what kind of media 84 * is attached to the NIC. The main purpose of this register is to tell 85 * the NIC what media to scan when in wake on LAN mode, however by 86 * forcibly enabling wake on LAN mode, we can use to learn what kind of 87 * media a given NIC has available and adapt ourselves accordingly. 88 * 89 * Of course, if the media description blocks in the EEPROM are bogus. 90 * what are the odds that the CWUC aren't bogus as well, right? Well, 91 * the CWUC value is more likely to be correct since wake on LAN mode 92 * won't work correctly without it, and wake on LAN is a big selling 93 * point these days. It's also harder to screw up a single byte than 94 * a whole media descriptor block. 95 * 96 * Note that not all tulip workalikes are handled in this driver: we only 97 * deal with those which are relatively well behaved. The Winbond is 98 * handled separately due to its different register offsets and the 99 * special handling needed for its various bugs. The PNIC is handled 100 * here, but I'm not thrilled about it. 101 * 102 * All of the workalike chips use some form of MII transceiver support 103 * with the exception of the Macronix chips, which also have a SYM port. 104 * The ASIX AX88140A is also documented to have a SYM port, but all 105 * the cards I've seen use an MII transceiver, probably because the 106 * AX88140A doesn't support internal NWAY. 107 */ 108 109 #include <sys/param.h> 110 #include <sys/systm.h> 111 #include <sys/sockio.h> 112 #include <sys/mbuf.h> 113 #include <sys/malloc.h> 114 #include <sys/kernel.h> 115 #include <sys/socket.h> 116 117 #include <net/if.h> 118 #include <net/if_arp.h> 119 #include <net/ethernet.h> 120 #include <net/if_dl.h> 121 #include <net/if_media.h> 122 123 #include <net/bpf.h> 124 125 #include <vm/vm.h> /* for vtophys */ 126 #include <vm/pmap.h> /* for vtophys */ 127 #include <machine/clock.h> /* for DELAY */ 128 #include <machine/bus_pio.h> 129 #include <machine/bus_memio.h> 130 #include <machine/bus.h> 131 #include <machine/resource.h> 132 #include <sys/bus.h> 133 #include <sys/rman.h> 134 135 #include <dev/mii/mii.h> 136 #include <dev/mii/miivar.h> 137 138 #include <pci/pcireg.h> 139 #include <pci/pcivar.h> 140 141 #define DC_USEIOSPACE 142 143 #include <pci/if_dcreg.h> 144 145 /* "controller miibus0" required. See GENERIC if you get errors here. */ 146 #include "miibus_if.h" 147 148 #ifndef lint 149 static const char rcsid[] = 150 "$FreeBSD$"; 151 #endif 152 153 /* 154 * Various supported device vendors/types and their names. 155 */ 156 static struct dc_type dc_devs[] = { 157 { DC_VENDORID_DEC, DC_DEVICEID_21143, 158 "Intel 21143 10/100BaseTX" }, 159 { DC_VENDORID_DAVICOM, DC_DEVICEID_DM9100, 160 "Davicom DM9100 10/100BaseTX" }, 161 { DC_VENDORID_DAVICOM, DC_DEVICEID_DM9102, 162 "Davicom DM9102 10/100BaseTX" }, 163 { DC_VENDORID_ADMTEK, DC_DEVICEID_AL981, 164 "ADMtek AL981 10/100BaseTX" }, 165 { DC_VENDORID_ADMTEK, DC_DEVICEID_AN985, 166 "ADMtek AN985 10/100BaseTX" }, 167 { DC_VENDORID_ASIX, DC_DEVICEID_AX88140A, 168 "ASIX AX88140A 10/100BaseTX" }, 169 { DC_VENDORID_ASIX, DC_DEVICEID_AX88140A, 170 "ASIX AX88141 10/100BaseTX" }, 171 { DC_VENDORID_MX, DC_DEVICEID_98713, 172 "Macronix 98713 10/100BaseTX" }, 173 { DC_VENDORID_MX, DC_DEVICEID_98713, 174 "Macronix 98713A 10/100BaseTX" }, 175 { DC_VENDORID_CP, DC_DEVICEID_98713_CP, 176 "Compex RL100-TX 10/100BaseTX" }, 177 { DC_VENDORID_CP, DC_DEVICEID_98713_CP, 178 "Compex RL100-TX 10/100BaseTX" }, 179 { DC_VENDORID_MX, DC_DEVICEID_987x5, 180 "Macronix 98715/98715A 10/100BaseTX" }, 181 { DC_VENDORID_MX, DC_DEVICEID_987x5, 182 "Macronix 98725 10/100BaseTX" }, 183 { DC_VENDORID_LO, DC_DEVICEID_82C115, 184 "LC82C115 PNIC II 10/100BaseTX" }, 185 { DC_VENDORID_LO, DC_DEVICEID_82C168, 186 "82c168 PNIC 10/100BaseTX" }, 187 { DC_VENDORID_LO, DC_DEVICEID_82C168, 188 "82c169 PNIC 10/100BaseTX" }, 189 { 0, 0, NULL } 190 }; 191 192 static int dc_probe __P((device_t)); 193 static int dc_attach __P((device_t)); 194 static int dc_detach __P((device_t)); 195 static void dc_acpi __P((device_t)); 196 static struct dc_type *dc_devtype __P((device_t)); 197 static int dc_newbuf __P((struct dc_softc *, int, struct mbuf *)); 198 static int dc_encap __P((struct dc_softc *, struct mbuf *, 199 u_int32_t *)); 200 static void dc_pnic_rx_bug_war __P((struct dc_softc *, int)); 201 static int dc_rx_resync __P((struct dc_softc *)); 202 static void dc_rxeof __P((struct dc_softc *)); 203 static void dc_txeof __P((struct dc_softc *)); 204 static void dc_tick __P((void *)); 205 static void dc_intr __P((void *)); 206 static void dc_start __P((struct ifnet *)); 207 static int dc_ioctl __P((struct ifnet *, u_long, caddr_t)); 208 static void dc_init __P((void *)); 209 static void dc_stop __P((struct dc_softc *)); 210 static void dc_watchdog __P((struct ifnet *)); 211 static void dc_shutdown __P((device_t)); 212 static int dc_ifmedia_upd __P((struct ifnet *)); 213 static void dc_ifmedia_sts __P((struct ifnet *, struct ifmediareq *)); 214 215 static void dc_delay __P((struct dc_softc *)); 216 static void dc_eeprom_idle __P((struct dc_softc *)); 217 static void dc_eeprom_putbyte __P((struct dc_softc *, int)); 218 static void dc_eeprom_getword __P((struct dc_softc *, int, u_int16_t *)); 219 static void dc_eeprom_getword_pnic 220 __P((struct dc_softc *, int, u_int16_t *)); 221 static void dc_read_eeprom __P((struct dc_softc *, caddr_t, int, 222 int, int)); 223 224 static void dc_mii_writebit __P((struct dc_softc *, int)); 225 static int dc_mii_readbit __P((struct dc_softc *)); 226 static void dc_mii_sync __P((struct dc_softc *)); 227 static void dc_mii_send __P((struct dc_softc *, u_int32_t, int)); 228 static int dc_mii_readreg __P((struct dc_softc *, struct dc_mii_frame *)); 229 static int dc_mii_writereg __P((struct dc_softc *, struct dc_mii_frame *)); 230 static int dc_miibus_readreg __P((device_t, int, int)); 231 static int dc_miibus_writereg __P((device_t, int, int, int)); 232 static void dc_miibus_statchg __P((device_t)); 233 234 static void dc_setcfg __P((struct dc_softc *, int)); 235 static u_int32_t dc_crc_le __P((struct dc_softc *, caddr_t)); 236 static u_int32_t dc_crc_be __P((caddr_t)); 237 static void dc_setfilt_21143 __P((struct dc_softc *)); 238 static void dc_setfilt_asix __P((struct dc_softc *)); 239 static void dc_setfilt_admtek __P((struct dc_softc *)); 240 241 static void dc_setfilt __P((struct dc_softc *)); 242 243 static void dc_reset __P((struct dc_softc *)); 244 static int dc_list_rx_init __P((struct dc_softc *)); 245 static int dc_list_tx_init __P((struct dc_softc *)); 246 247 #ifdef DC_USEIOSPACE 248 #define DC_RES SYS_RES_IOPORT 249 #define DC_RID DC_PCI_CFBIO 250 #else 251 #define DC_RES SYS_RES_MEMORY 252 #define DC_RID DC_PCI_CFBMA 253 #endif 254 255 static device_method_t dc_methods[] = { 256 /* Device interface */ 257 DEVMETHOD(device_probe, dc_probe), 258 DEVMETHOD(device_attach, dc_attach), 259 DEVMETHOD(device_detach, dc_detach), 260 DEVMETHOD(device_shutdown, dc_shutdown), 261 262 /* bus interface */ 263 DEVMETHOD(bus_print_child, bus_generic_print_child), 264 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 265 266 /* MII interface */ 267 DEVMETHOD(miibus_readreg, dc_miibus_readreg), 268 DEVMETHOD(miibus_writereg, dc_miibus_writereg), 269 DEVMETHOD(miibus_statchg, dc_miibus_statchg), 270 271 { 0, 0 } 272 }; 273 274 static driver_t dc_driver = { 275 "dc", 276 dc_methods, 277 sizeof(struct dc_softc) 278 }; 279 280 static devclass_t dc_devclass; 281 282 DRIVER_MODULE(if_dc, pci, dc_driver, dc_devclass, 0, 0); 283 DRIVER_MODULE(miibus, dc, miibus_driver, miibus_devclass, 0, 0); 284 285 #define DC_SETBIT(sc, reg, x) \ 286 CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) | (x)) 287 288 #define DC_CLRBIT(sc, reg, x) \ 289 CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) & ~(x)) 290 291 #define SIO_SET(x) DC_SETBIT(sc, DC_SIO, (x)) 292 #define SIO_CLR(x) DC_CLRBIT(sc, DC_SIO, (x)) 293 294 static void dc_delay(sc) 295 struct dc_softc *sc; 296 { 297 int idx; 298 299 for (idx = (300 / 33) + 1; idx > 0; idx--) 300 CSR_READ_4(sc, DC_BUSCTL); 301 } 302 303 static void dc_eeprom_idle(sc) 304 struct dc_softc *sc; 305 { 306 register int i; 307 308 CSR_WRITE_4(sc, DC_SIO, DC_SIO_EESEL); 309 dc_delay(sc); 310 DC_SETBIT(sc, DC_SIO, DC_SIO_ROMCTL_READ); 311 dc_delay(sc); 312 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); 313 dc_delay(sc); 314 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CS); 315 dc_delay(sc); 316 317 for (i = 0; i < 25; i++) { 318 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); 319 dc_delay(sc); 320 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CLK); 321 dc_delay(sc); 322 } 323 324 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); 325 dc_delay(sc); 326 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CS); 327 dc_delay(sc); 328 CSR_WRITE_4(sc, DC_SIO, 0x00000000); 329 330 return; 331 } 332 333 /* 334 * Send a read command and address to the EEPROM, check for ACK. 335 */ 336 static void dc_eeprom_putbyte(sc, addr) 337 struct dc_softc *sc; 338 int addr; 339 { 340 register int d, i; 341 342 /* 343 * The AN985 has a 93C66 EEPROM on it instead of 344 * a 93C46. It uses a different bit sequence for 345 * specifying the "read" opcode. 346 */ 347 if (DC_IS_CENTAUR(sc)) 348 d = addr | (DC_EECMD_READ << 2); 349 else 350 d = addr | DC_EECMD_READ; 351 352 /* 353 * Feed in each bit and strobe the clock. 354 */ 355 for (i = 0x400; i; i >>= 1) { 356 if (d & i) { 357 SIO_SET(DC_SIO_EE_DATAIN); 358 } else { 359 SIO_CLR(DC_SIO_EE_DATAIN); 360 } 361 dc_delay(sc); 362 SIO_SET(DC_SIO_EE_CLK); 363 dc_delay(sc); 364 SIO_CLR(DC_SIO_EE_CLK); 365 dc_delay(sc); 366 } 367 368 return; 369 } 370 371 /* 372 * Read a word of data stored in the EEPROM at address 'addr.' 373 * The PNIC 82c168/82c169 has its own non-standard way to read 374 * the EEPROM. 375 */ 376 static void dc_eeprom_getword_pnic(sc, addr, dest) 377 struct dc_softc *sc; 378 int addr; 379 u_int16_t *dest; 380 { 381 register int i; 382 u_int32_t r; 383 384 CSR_WRITE_4(sc, DC_PN_SIOCTL, DC_PN_EEOPCODE_READ|addr); 385 386 for (i = 0; i < DC_TIMEOUT; i++) { 387 DELAY(1); 388 r = CSR_READ_4(sc, DC_SIO); 389 if (!(r & DC_PN_SIOCTL_BUSY)) { 390 *dest = (u_int16_t)(r & 0xFFFF); 391 return; 392 } 393 } 394 395 return; 396 } 397 398 /* 399 * Read a word of data stored in the EEPROM at address 'addr.' 400 */ 401 static void dc_eeprom_getword(sc, addr, dest) 402 struct dc_softc *sc; 403 int addr; 404 u_int16_t *dest; 405 { 406 register int i; 407 u_int16_t word = 0; 408 409 /* Force EEPROM to idle state. */ 410 dc_eeprom_idle(sc); 411 412 /* Enter EEPROM access mode. */ 413 CSR_WRITE_4(sc, DC_SIO, DC_SIO_EESEL); 414 dc_delay(sc); 415 DC_SETBIT(sc, DC_SIO, DC_SIO_ROMCTL_READ); 416 dc_delay(sc); 417 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); 418 dc_delay(sc); 419 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CS); 420 dc_delay(sc); 421 422 /* 423 * Send address of word we want to read. 424 */ 425 dc_eeprom_putbyte(sc, addr); 426 427 /* 428 * Start reading bits from EEPROM. 429 */ 430 for (i = 0x8000; i; i >>= 1) { 431 SIO_SET(DC_SIO_EE_CLK); 432 dc_delay(sc); 433 if (CSR_READ_4(sc, DC_SIO) & DC_SIO_EE_DATAOUT) 434 word |= i; 435 dc_delay(sc); 436 SIO_CLR(DC_SIO_EE_CLK); 437 dc_delay(sc); 438 } 439 440 /* Turn off EEPROM access mode. */ 441 dc_eeprom_idle(sc); 442 443 *dest = word; 444 445 return; 446 } 447 448 /* 449 * Read a sequence of words from the EEPROM. 450 */ 451 static void dc_read_eeprom(sc, dest, off, cnt, swap) 452 struct dc_softc *sc; 453 caddr_t dest; 454 int off; 455 int cnt; 456 int swap; 457 { 458 int i; 459 u_int16_t word = 0, *ptr; 460 461 for (i = 0; i < cnt; i++) { 462 if (DC_IS_PNIC(sc)) 463 dc_eeprom_getword_pnic(sc, off + i, &word); 464 else 465 dc_eeprom_getword(sc, off + i, &word); 466 ptr = (u_int16_t *)(dest + (i * 2)); 467 if (swap) 468 *ptr = ntohs(word); 469 else 470 *ptr = word; 471 } 472 473 return; 474 } 475 476 /* 477 * The following two routines are taken from the Macronix 98713 478 * Application Notes pp.19-21. 479 */ 480 /* 481 * Write a bit to the MII bus. 482 */ 483 static void dc_mii_writebit(sc, bit) 484 struct dc_softc *sc; 485 int bit; 486 { 487 if (bit) 488 CSR_WRITE_4(sc, DC_SIO, 489 DC_SIO_ROMCTL_WRITE|DC_SIO_MII_DATAOUT); 490 else 491 CSR_WRITE_4(sc, DC_SIO, DC_SIO_ROMCTL_WRITE); 492 493 DC_SETBIT(sc, DC_SIO, DC_SIO_MII_CLK); 494 DC_CLRBIT(sc, DC_SIO, DC_SIO_MII_CLK); 495 496 return; 497 } 498 499 /* 500 * Read a bit from the MII bus. 501 */ 502 static int dc_mii_readbit(sc) 503 struct dc_softc *sc; 504 { 505 CSR_WRITE_4(sc, DC_SIO, DC_SIO_ROMCTL_READ|DC_SIO_MII_DIR); 506 CSR_READ_4(sc, DC_SIO); 507 DC_SETBIT(sc, DC_SIO, DC_SIO_MII_CLK); 508 DC_CLRBIT(sc, DC_SIO, DC_SIO_MII_CLK); 509 if (CSR_READ_4(sc, DC_SIO) & DC_SIO_MII_DATAIN) 510 return(1); 511 512 return(0); 513 } 514 515 /* 516 * Sync the PHYs by setting data bit and strobing the clock 32 times. 517 */ 518 static void dc_mii_sync(sc) 519 struct dc_softc *sc; 520 { 521 register int i; 522 523 CSR_WRITE_4(sc, DC_SIO, DC_SIO_ROMCTL_WRITE); 524 525 for (i = 0; i < 32; i++) 526 dc_mii_writebit(sc, 1); 527 528 return; 529 } 530 531 /* 532 * Clock a series of bits through the MII. 533 */ 534 static void dc_mii_send(sc, bits, cnt) 535 struct dc_softc *sc; 536 u_int32_t bits; 537 int cnt; 538 { 539 int i; 540 541 for (i = (0x1 << (cnt - 1)); i; i >>= 1) 542 dc_mii_writebit(sc, bits & i); 543 } 544 545 /* 546 * Read an PHY register through the MII. 547 */ 548 static int dc_mii_readreg(sc, frame) 549 struct dc_softc *sc; 550 struct dc_mii_frame *frame; 551 552 { 553 int i, ack, s; 554 555 s = splimp(); 556 557 /* 558 * Set up frame for RX. 559 */ 560 frame->mii_stdelim = DC_MII_STARTDELIM; 561 frame->mii_opcode = DC_MII_READOP; 562 frame->mii_turnaround = 0; 563 frame->mii_data = 0; 564 565 /* 566 * Sync the PHYs. 567 */ 568 dc_mii_sync(sc); 569 570 /* 571 * Send command/address info. 572 */ 573 dc_mii_send(sc, frame->mii_stdelim, 2); 574 dc_mii_send(sc, frame->mii_opcode, 2); 575 dc_mii_send(sc, frame->mii_phyaddr, 5); 576 dc_mii_send(sc, frame->mii_regaddr, 5); 577 578 #ifdef notdef 579 /* Idle bit */ 580 dc_mii_writebit(sc, 1); 581 dc_mii_writebit(sc, 0); 582 #endif 583 584 /* Check for ack */ 585 ack = dc_mii_readbit(sc); 586 587 /* 588 * Now try reading data bits. If the ack failed, we still 589 * need to clock through 16 cycles to keep the PHY(s) in sync. 590 */ 591 if (ack) { 592 for(i = 0; i < 16; i++) { 593 dc_mii_readbit(sc); 594 } 595 goto fail; 596 } 597 598 for (i = 0x8000; i; i >>= 1) { 599 if (!ack) { 600 if (dc_mii_readbit(sc)) 601 frame->mii_data |= i; 602 } 603 } 604 605 fail: 606 607 dc_mii_writebit(sc, 0); 608 dc_mii_writebit(sc, 0); 609 610 splx(s); 611 612 if (ack) 613 return(1); 614 return(0); 615 } 616 617 /* 618 * Write to a PHY register through the MII. 619 */ 620 static int dc_mii_writereg(sc, frame) 621 struct dc_softc *sc; 622 struct dc_mii_frame *frame; 623 624 { 625 int s; 626 627 s = splimp(); 628 /* 629 * Set up frame for TX. 630 */ 631 632 frame->mii_stdelim = DC_MII_STARTDELIM; 633 frame->mii_opcode = DC_MII_WRITEOP; 634 frame->mii_turnaround = DC_MII_TURNAROUND; 635 636 /* 637 * Sync the PHYs. 638 */ 639 dc_mii_sync(sc); 640 641 dc_mii_send(sc, frame->mii_stdelim, 2); 642 dc_mii_send(sc, frame->mii_opcode, 2); 643 dc_mii_send(sc, frame->mii_phyaddr, 5); 644 dc_mii_send(sc, frame->mii_regaddr, 5); 645 dc_mii_send(sc, frame->mii_turnaround, 2); 646 dc_mii_send(sc, frame->mii_data, 16); 647 648 /* Idle bit. */ 649 dc_mii_writebit(sc, 0); 650 dc_mii_writebit(sc, 0); 651 652 splx(s); 653 654 return(0); 655 } 656 657 static int dc_miibus_readreg(dev, phy, reg) 658 device_t dev; 659 int phy, reg; 660 { 661 struct dc_mii_frame frame; 662 struct dc_softc *sc; 663 int i, rval, phy_reg; 664 665 sc = device_get_softc(dev); 666 bzero((char *)&frame, sizeof(frame)); 667 668 /* 669 * Note: both the AL981 and AN985 have internal PHYs, 670 * however the AL981 provides direct access to the PHY 671 * registers while the AN985 uses a serial MII interface. 672 * The AN985's MII interface is also buggy in that you 673 * can read from any MII address (0 to 31), but only address 1 674 * behaves normally. To deal with both cases, we pretend 675 * that the PHY is at MII address 1. 676 */ 677 if (DC_IS_ADMTEK(sc) && phy != DC_ADMTEK_PHYADDR) 678 return(0); 679 680 if (sc->dc_pmode == DC_PMODE_SYM) { 681 if (phy == (MII_NPHY - 1)) { 682 switch(reg) { 683 case MII_BMSR: 684 /* 685 * Fake something to make the probe 686 * code think there's a PHY here. 687 */ 688 return(BMSR_MEDIAMASK); 689 break; 690 case MII_PHYIDR1: 691 if (DC_IS_PNIC(sc)) 692 return(DC_VENDORID_LO); 693 return(DC_VENDORID_DEC); 694 break; 695 case MII_PHYIDR2: 696 if (DC_IS_PNIC(sc)) 697 return(DC_DEVICEID_82C168); 698 return(DC_DEVICEID_21143); 699 break; 700 default: 701 return(0); 702 break; 703 } 704 } else 705 return(0); 706 } 707 708 if (DC_IS_PNIC(sc)) { 709 CSR_WRITE_4(sc, DC_PN_MII, DC_PN_MIIOPCODE_READ | 710 (phy << 23) | (reg << 18)); 711 for (i = 0; i < DC_TIMEOUT; i++) { 712 DELAY(1); 713 rval = CSR_READ_4(sc, DC_PN_MII); 714 if (!(rval & DC_PN_MII_BUSY)) { 715 rval &= 0xFFFF; 716 return(rval == 0xFFFF ? 0 : rval); 717 } 718 } 719 return(0); 720 } 721 722 if (DC_IS_COMET(sc)) { 723 switch(reg) { 724 case MII_BMCR: 725 phy_reg = DC_AL_BMCR; 726 break; 727 case MII_BMSR: 728 phy_reg = DC_AL_BMSR; 729 break; 730 case MII_PHYIDR1: 731 phy_reg = DC_AL_VENID; 732 break; 733 case MII_PHYIDR2: 734 phy_reg = DC_AL_DEVID; 735 break; 736 case MII_ANAR: 737 phy_reg = DC_AL_ANAR; 738 break; 739 case MII_ANLPAR: 740 phy_reg = DC_AL_LPAR; 741 break; 742 case MII_ANER: 743 phy_reg = DC_AL_ANER; 744 break; 745 default: 746 printf("dc%d: phy_read: bad phy register %x\n", 747 sc->dc_unit, reg); 748 return(0); 749 break; 750 } 751 752 rval = CSR_READ_4(sc, phy_reg) & 0x0000FFFF; 753 754 if (rval == 0xFFFF) 755 return(0); 756 return(rval); 757 } 758 759 frame.mii_phyaddr = phy; 760 frame.mii_regaddr = reg; 761 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL); 762 dc_mii_readreg(sc, &frame); 763 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL); 764 765 return(frame.mii_data); 766 } 767 768 static int dc_miibus_writereg(dev, phy, reg, data) 769 device_t dev; 770 int phy, reg, data; 771 { 772 struct dc_softc *sc; 773 struct dc_mii_frame frame; 774 int i, phy_reg; 775 776 sc = device_get_softc(dev); 777 bzero((char *)&frame, sizeof(frame)); 778 779 if (DC_IS_ADMTEK(sc) && phy != DC_ADMTEK_PHYADDR) 780 return(0); 781 782 if (DC_IS_PNIC(sc)) { 783 CSR_WRITE_4(sc, DC_PN_MII, DC_PN_MIIOPCODE_WRITE | 784 (phy << 23) | (reg << 10) | data); 785 for (i = 0; i < DC_TIMEOUT; i++) { 786 if (!(CSR_READ_4(sc, DC_PN_MII) & DC_PN_MII_BUSY)) 787 break; 788 } 789 return(0); 790 } 791 792 if (DC_IS_COMET(sc)) { 793 switch(reg) { 794 case MII_BMCR: 795 phy_reg = DC_AL_BMCR; 796 break; 797 case MII_BMSR: 798 phy_reg = DC_AL_BMSR; 799 break; 800 case MII_PHYIDR1: 801 phy_reg = DC_AL_VENID; 802 break; 803 case MII_PHYIDR2: 804 phy_reg = DC_AL_DEVID; 805 break; 806 case MII_ANAR: 807 phy_reg = DC_AL_ANAR; 808 break; 809 case MII_ANLPAR: 810 phy_reg = DC_AL_LPAR; 811 break; 812 case MII_ANER: 813 phy_reg = DC_AL_ANER; 814 break; 815 default: 816 printf("dc%d: phy_write: bad phy register %x\n", 817 sc->dc_unit, reg); 818 return(0); 819 break; 820 } 821 822 CSR_WRITE_4(sc, phy_reg, data); 823 return(0); 824 } 825 826 frame.mii_phyaddr = phy; 827 frame.mii_regaddr = reg; 828 frame.mii_data = data; 829 830 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL); 831 dc_mii_writereg(sc, &frame); 832 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL); 833 834 return(0); 835 } 836 837 static void dc_miibus_statchg(dev) 838 device_t dev; 839 { 840 struct dc_softc *sc; 841 struct mii_data *mii; 842 843 sc = device_get_softc(dev); 844 if (DC_IS_ADMTEK(sc)) 845 return; 846 mii = device_get_softc(sc->dc_miibus); 847 dc_setcfg(sc, mii->mii_media_active); 848 sc->dc_if_media = mii->mii_media_active; 849 850 return; 851 } 852 853 #define DC_POLY 0xEDB88320 854 #define DC_BITS 9 855 #define DC_BITS_PNIC_II 7 856 857 static u_int32_t dc_crc_le(sc, addr) 858 struct dc_softc *sc; 859 caddr_t addr; 860 { 861 u_int32_t idx, bit, data, crc; 862 863 /* Compute CRC for the address value. */ 864 crc = 0xFFFFFFFF; /* initial value */ 865 866 for (idx = 0; idx < 6; idx++) { 867 for (data = *addr++, bit = 0; bit < 8; bit++, data >>= 1) 868 crc = (crc >> 1) ^ (((crc ^ data) & 1) ? DC_POLY : 0); 869 } 870 871 /* The hash table on the PNIC II is only 128 bits wide. */ 872 if (DC_IS_PNICII(sc)) 873 return (crc & ((1 << DC_BITS_PNIC_II) - 1)); 874 875 return (crc & ((1 << DC_BITS) - 1)); 876 } 877 878 /* 879 * Calculate CRC of a multicast group address, return the lower 6 bits. 880 */ 881 static u_int32_t dc_crc_be(addr) 882 caddr_t addr; 883 { 884 u_int32_t crc, carry; 885 int i, j; 886 u_int8_t c; 887 888 /* Compute CRC for the address value. */ 889 crc = 0xFFFFFFFF; /* initial value */ 890 891 for (i = 0; i < 6; i++) { 892 c = *(addr + i); 893 for (j = 0; j < 8; j++) { 894 carry = ((crc & 0x80000000) ? 1 : 0) ^ (c & 0x01); 895 crc <<= 1; 896 c >>= 1; 897 if (carry) 898 crc = (crc ^ 0x04c11db6) | carry; 899 } 900 } 901 902 /* return the filter bit position */ 903 return((crc >> 26) & 0x0000003F); 904 } 905 906 /* 907 * 21143-style RX filter setup routine. Filter programming is done by 908 * downloading a special setup frame into the TX engine. 21143, Macronix, 909 * PNIC, PNIC II and Davicom chips are programmed this way. 910 * 911 * We always program the chip using 'hash perfect' mode, i.e. one perfect 912 * address (our node address) and a 512-bit hash filter for multicast 913 * frames. We also sneak the broadcast address into the hash filter since 914 * we need that too. 915 */ 916 void dc_setfilt_21143(sc) 917 struct dc_softc *sc; 918 { 919 struct dc_desc *sframe; 920 u_int32_t h, *sp; 921 struct ifmultiaddr *ifma; 922 struct ifnet *ifp; 923 int i; 924 925 ifp = &sc->arpcom.ac_if; 926 927 i = sc->dc_cdata.dc_tx_prod; 928 DC_INC(sc->dc_cdata.dc_tx_prod, DC_TX_LIST_CNT); 929 sc->dc_cdata.dc_tx_cnt++; 930 sframe = &sc->dc_ldata->dc_tx_list[i]; 931 sp = (u_int32_t *)&sc->dc_cdata.dc_sbuf; 932 bzero((char *)sp, DC_SFRAME_LEN); 933 934 sframe->dc_data = vtophys(&sc->dc_cdata.dc_sbuf); 935 sframe->dc_ctl = DC_SFRAME_LEN | DC_TXCTL_SETUP | DC_TXCTL_TLINK | 936 DC_FILTER_HASHPERF | DC_TXCTL_FINT; 937 938 sc->dc_cdata.dc_tx_chain[i] = (struct mbuf *)&sc->dc_cdata.dc_sbuf; 939 940 /* If we want promiscuous mode, set the allframes bit. */ 941 if (ifp->if_flags & IFF_PROMISC) 942 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC); 943 else 944 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC); 945 946 if (ifp->if_flags & IFF_ALLMULTI) 947 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI); 948 else 949 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI); 950 951 for (ifma = ifp->if_multiaddrs.lh_first; ifma != NULL; 952 ifma = ifma->ifma_link.le_next) { 953 if (ifma->ifma_addr->sa_family != AF_LINK) 954 continue; 955 h = dc_crc_le(sc, 956 LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 957 sp[h >> 4] |= 1 << (h & 0xF); 958 } 959 960 if (ifp->if_flags & IFF_BROADCAST) { 961 h = dc_crc_le(sc, (caddr_t)ðerbroadcastaddr); 962 sp[h >> 4] |= 1 << (h & 0xF); 963 } 964 965 /* Set our MAC address */ 966 sp[39] = ((u_int16_t *)sc->arpcom.ac_enaddr)[0]; 967 sp[40] = ((u_int16_t *)sc->arpcom.ac_enaddr)[1]; 968 sp[41] = ((u_int16_t *)sc->arpcom.ac_enaddr)[2]; 969 970 sframe->dc_status = DC_TXSTAT_OWN; 971 CSR_WRITE_4(sc, DC_TXSTART, 0xFFFFFFFF); 972 973 /* 974 * The PNIC takes an exceedingly long time to process its 975 * setup frame; wait 10ms after posting the setup frame 976 * before proceeding, just so it has time to swallow its 977 * medicine. 978 */ 979 DELAY(10000); 980 981 ifp->if_timer = 5; 982 983 return; 984 } 985 986 void dc_setfilt_admtek(sc) 987 struct dc_softc *sc; 988 { 989 struct ifnet *ifp; 990 int h = 0; 991 u_int32_t hashes[2] = { 0, 0 }; 992 struct ifmultiaddr *ifma; 993 994 ifp = &sc->arpcom.ac_if; 995 996 /* Init our MAC address */ 997 CSR_WRITE_4(sc, DC_AL_PAR0, *(u_int32_t *)(&sc->arpcom.ac_enaddr[0])); 998 CSR_WRITE_4(sc, DC_AL_PAR1, *(u_int32_t *)(&sc->arpcom.ac_enaddr[4])); 999 1000 /* If we want promiscuous mode, set the allframes bit. */ 1001 if (ifp->if_flags & IFF_PROMISC) 1002 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC); 1003 else 1004 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC); 1005 1006 if (ifp->if_flags & IFF_ALLMULTI) 1007 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI); 1008 else 1009 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI); 1010 1011 /* first, zot all the existing hash bits */ 1012 CSR_WRITE_4(sc, DC_AL_MAR0, 0); 1013 CSR_WRITE_4(sc, DC_AL_MAR1, 0); 1014 1015 /* 1016 * If we're already in promisc or allmulti mode, we 1017 * don't have to bother programming the multicast filter. 1018 */ 1019 if (ifp->if_flags & (IFF_PROMISC|IFF_ALLMULTI)) 1020 return; 1021 1022 /* now program new ones */ 1023 for (ifma = ifp->if_multiaddrs.lh_first; ifma != NULL; 1024 ifma = ifma->ifma_link.le_next) { 1025 if (ifma->ifma_addr->sa_family != AF_LINK) 1026 continue; 1027 h = dc_crc_be(LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 1028 if (h < 32) 1029 hashes[0] |= (1 << h); 1030 else 1031 hashes[1] |= (1 << (h - 32)); 1032 } 1033 1034 CSR_WRITE_4(sc, DC_AL_MAR0, hashes[0]); 1035 CSR_WRITE_4(sc, DC_AL_MAR1, hashes[1]); 1036 1037 return; 1038 } 1039 1040 void dc_setfilt_asix(sc) 1041 struct dc_softc *sc; 1042 { 1043 struct ifnet *ifp; 1044 int h = 0; 1045 u_int32_t hashes[2] = { 0, 0 }; 1046 struct ifmultiaddr *ifma; 1047 1048 ifp = &sc->arpcom.ac_if; 1049 1050 /* Init our MAC address */ 1051 CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_PAR0); 1052 CSR_WRITE_4(sc, DC_AX_FILTDATA, 1053 *(u_int32_t *)(&sc->arpcom.ac_enaddr[0])); 1054 CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_PAR1); 1055 CSR_WRITE_4(sc, DC_AX_FILTDATA, 1056 *(u_int32_t *)(&sc->arpcom.ac_enaddr[4])); 1057 1058 /* If we want promiscuous mode, set the allframes bit. */ 1059 if (ifp->if_flags & IFF_PROMISC) 1060 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC); 1061 else 1062 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC); 1063 1064 if (ifp->if_flags & IFF_ALLMULTI) 1065 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI); 1066 else 1067 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI); 1068 1069 /* 1070 * The ASIX chip has a special bit to enable reception 1071 * of broadcast frames. 1072 */ 1073 if (ifp->if_flags & IFF_BROADCAST) 1074 DC_SETBIT(sc, DC_NETCFG, DC_AX_NETCFG_RX_BROAD); 1075 else 1076 DC_CLRBIT(sc, DC_NETCFG, DC_AX_NETCFG_RX_BROAD); 1077 1078 /* first, zot all the existing hash bits */ 1079 CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_MAR0); 1080 CSR_WRITE_4(sc, DC_AX_FILTDATA, 0); 1081 CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_MAR1); 1082 CSR_WRITE_4(sc, DC_AX_FILTDATA, 0); 1083 1084 /* 1085 * If we're already in promisc or allmulti mode, we 1086 * don't have to bother programming the multicast filter. 1087 */ 1088 if (ifp->if_flags & (IFF_PROMISC|IFF_ALLMULTI)) 1089 return; 1090 1091 /* now program new ones */ 1092 for (ifma = ifp->if_multiaddrs.lh_first; ifma != NULL; 1093 ifma = ifma->ifma_link.le_next) { 1094 if (ifma->ifma_addr->sa_family != AF_LINK) 1095 continue; 1096 h = dc_crc_be(LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 1097 if (h < 32) 1098 hashes[0] |= (1 << h); 1099 else 1100 hashes[1] |= (1 << (h - 32)); 1101 } 1102 1103 CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_MAR0); 1104 CSR_WRITE_4(sc, DC_AX_FILTDATA, hashes[0]); 1105 CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_MAR1); 1106 CSR_WRITE_4(sc, DC_AX_FILTDATA, hashes[1]); 1107 1108 return; 1109 } 1110 1111 static void dc_setfilt(sc) 1112 struct dc_softc *sc; 1113 { 1114 if (DC_IS_INTEL(sc) || DC_IS_MACRONIX(sc) || DC_IS_PNIC(sc) || 1115 DC_IS_PNICII(sc) || DC_IS_DAVICOM(sc)) 1116 dc_setfilt_21143(sc); 1117 1118 if (DC_IS_ASIX(sc)) 1119 dc_setfilt_asix(sc); 1120 1121 if (DC_IS_ADMTEK(sc)) 1122 dc_setfilt_admtek(sc); 1123 1124 return; 1125 } 1126 1127 /* 1128 * In order to fiddle with the 1129 * 'full-duplex' and '100Mbps' bits in the netconfig register, we 1130 * first have to put the transmit and/or receive logic in the idle state. 1131 */ 1132 static void dc_setcfg(sc, media) 1133 struct dc_softc *sc; 1134 int media; 1135 { 1136 int i, restart = 0; 1137 u_int32_t isr; 1138 1139 if (IFM_SUBTYPE(media) == IFM_NONE) 1140 return; 1141 1142 if (CSR_READ_4(sc, DC_NETCFG) & (DC_NETCFG_TX_ON|DC_NETCFG_RX_ON)) { 1143 restart = 1; 1144 DC_CLRBIT(sc, DC_NETCFG, (DC_NETCFG_TX_ON|DC_NETCFG_RX_ON)); 1145 1146 for (i = 0; i < DC_TIMEOUT; i++) { 1147 DELAY(10); 1148 isr = CSR_READ_4(sc, DC_ISR); 1149 if (isr & DC_ISR_TX_IDLE || 1150 (isr & DC_ISR_RX_STATE) == DC_RXSTATE_STOPPED) 1151 break; 1152 } 1153 1154 if (i == DC_TIMEOUT) 1155 printf("dc%d: failed to force tx and " 1156 "rx to idle state\n", sc->dc_unit); 1157 1158 } 1159 1160 if (IFM_SUBTYPE(media) == IFM_100_TX) { 1161 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_SPEEDSEL); 1162 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_HEARTBEAT); 1163 if (sc->dc_pmode == DC_PMODE_MII) { 1164 DC_SETBIT(sc, DC_WATCHDOG, DC_WDOG_JABBERDIS); 1165 DC_CLRBIT(sc, DC_NETCFG, (DC_NETCFG_PCS| 1166 DC_NETCFG_PORTSEL|DC_NETCFG_SCRAMBLER)); 1167 if (sc->dc_type == DC_TYPE_98713) 1168 DC_SETBIT(sc, DC_NETCFG, (DC_NETCFG_PCS| 1169 DC_NETCFG_SCRAMBLER)); 1170 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL); 1171 DC_CLRBIT(sc, DC_10BTCTRL, 0xFFFF); 1172 } else { 1173 if (DC_IS_PNIC(sc)) { 1174 DC_PN_GPIO_SETBIT(sc, DC_PN_GPIO_SPEEDSEL); 1175 DC_PN_GPIO_SETBIT(sc, DC_PN_GPIO_100TX_LOOP); 1176 DC_SETBIT(sc, DC_PN_NWAY, DC_PN_NWAY_SPEEDSEL); 1177 } 1178 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL| 1179 DC_NETCFG_PCS|DC_NETCFG_SCRAMBLER); 1180 } 1181 } 1182 1183 if (IFM_SUBTYPE(media) == IFM_10_T) { 1184 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_SPEEDSEL); 1185 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_HEARTBEAT); 1186 if (sc->dc_pmode == DC_PMODE_MII) { 1187 DC_SETBIT(sc, DC_WATCHDOG, DC_WDOG_JABBERDIS); 1188 DC_CLRBIT(sc, DC_NETCFG, (DC_NETCFG_PCS| 1189 DC_NETCFG_PORTSEL|DC_NETCFG_SCRAMBLER)); 1190 if (sc->dc_type == DC_TYPE_98713) 1191 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PCS); 1192 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL); 1193 DC_CLRBIT(sc, DC_10BTCTRL, 0xFFFF); 1194 } else { 1195 if (DC_IS_PNIC(sc)) { 1196 DC_PN_GPIO_CLRBIT(sc, DC_PN_GPIO_SPEEDSEL); 1197 DC_PN_GPIO_SETBIT(sc, DC_PN_GPIO_100TX_LOOP); 1198 DC_CLRBIT(sc, DC_PN_NWAY, DC_PN_NWAY_SPEEDSEL); 1199 } 1200 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL); 1201 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_SCRAMBLER); 1202 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PCS); 1203 } 1204 } 1205 1206 if ((media & IFM_GMASK) == IFM_FDX) { 1207 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_FULLDUPLEX); 1208 if (sc->dc_pmode == DC_PMODE_SYM && DC_IS_PNIC(sc)) 1209 DC_SETBIT(sc, DC_PN_NWAY, DC_PN_NWAY_DUPLEX); 1210 } else { 1211 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_FULLDUPLEX); 1212 if (sc->dc_pmode == DC_PMODE_SYM && DC_IS_PNIC(sc)) 1213 DC_CLRBIT(sc, DC_PN_NWAY, DC_PN_NWAY_DUPLEX); 1214 } 1215 1216 if (restart) 1217 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_TX_ON|DC_NETCFG_RX_ON); 1218 1219 return; 1220 } 1221 1222 static void dc_reset(sc) 1223 struct dc_softc *sc; 1224 { 1225 register int i; 1226 1227 DC_SETBIT(sc, DC_BUSCTL, DC_BUSCTL_RESET); 1228 1229 for (i = 0; i < DC_TIMEOUT; i++) { 1230 DELAY(10); 1231 if (!(CSR_READ_4(sc, DC_BUSCTL) & DC_BUSCTL_RESET)) 1232 break; 1233 } 1234 1235 if (DC_IS_ASIX(sc) || DC_IS_ADMTEK(sc)) { 1236 DELAY(10000); 1237 DC_CLRBIT(sc, DC_BUSCTL, DC_BUSCTL_RESET); 1238 i = 0; 1239 } 1240 1241 if (i == DC_TIMEOUT) 1242 printf("dc%d: reset never completed!\n", sc->dc_unit); 1243 1244 /* Wait a little while for the chip to get its brains in order. */ 1245 DELAY(1000); 1246 1247 CSR_WRITE_4(sc, DC_IMR, 0x00000000); 1248 CSR_WRITE_4(sc, DC_BUSCTL, 0x00000000); 1249 CSR_WRITE_4(sc, DC_NETCFG, 0x00000000); 1250 1251 /* 1252 * Bring the SIA out of reset. In some cases, it looks 1253 * like failing to unreset the SIA soon enough gets it 1254 * into a state where it will never come out of reset 1255 * until we reset the whole chip again. 1256 */ 1257 if (DC_IS_INTEL(sc)) 1258 DC_SETBIT(sc, DC_SIARESET, DC_SIA_RESET); 1259 1260 return; 1261 } 1262 1263 static struct dc_type *dc_devtype(dev) 1264 device_t dev; 1265 { 1266 struct dc_type *t; 1267 u_int32_t rev; 1268 1269 t = dc_devs; 1270 1271 while(t->dc_name != NULL) { 1272 if ((pci_get_vendor(dev) == t->dc_vid) && 1273 (pci_get_device(dev) == t->dc_did)) { 1274 /* Check the PCI revision */ 1275 rev = pci_read_config(dev, DC_PCI_CFRV, 4) & 0xFF; 1276 if (t->dc_did == DC_DEVICEID_98713 && 1277 rev >= DC_REVISION_98713A) 1278 t++; 1279 if (t->dc_did == DC_DEVICEID_98713_CP && 1280 rev >= DC_REVISION_98713A) 1281 t++; 1282 if (t->dc_did == DC_DEVICEID_987x5 && 1283 rev >= DC_REVISION_98725) 1284 t++; 1285 if (t->dc_did == DC_DEVICEID_AX88140A && 1286 rev >= DC_REVISION_88141) 1287 t++; 1288 if (t->dc_did == DC_DEVICEID_82C168 && 1289 rev >= DC_REVISION_82C169) 1290 t++; 1291 return(t); 1292 } 1293 t++; 1294 } 1295 1296 return(NULL); 1297 } 1298 1299 /* 1300 * Probe for a 21143 or clone chip. Check the PCI vendor and device 1301 * IDs against our list and return a device name if we find a match. 1302 * We do a little bit of extra work to identify the exact type of 1303 * chip. The MX98713 and MX98713A have the same PCI vendor/device ID, 1304 * but different revision IDs. The same is true for 98715/98715A 1305 * chips and the 98725, as well as the ASIX and ADMtek chips. In some 1306 * cases, the exact chip revision affects driver behavior. 1307 */ 1308 static int dc_probe(dev) 1309 device_t dev; 1310 { 1311 struct dc_type *t; 1312 1313 t = dc_devtype(dev); 1314 1315 if (t != NULL) { 1316 device_set_desc(dev, t->dc_name); 1317 return(0); 1318 } 1319 1320 return(ENXIO); 1321 } 1322 1323 static void dc_acpi(dev) 1324 device_t dev; 1325 { 1326 u_int32_t r, cptr; 1327 int unit; 1328 1329 unit = device_get_unit(dev); 1330 1331 /* Find the location of the capabilities block */ 1332 cptr = pci_read_config(dev, DC_PCI_CCAP, 4) & 0xFF; 1333 1334 r = pci_read_config(dev, cptr, 4) & 0xFF; 1335 if (r == 0x01) { 1336 1337 r = pci_read_config(dev, cptr + 4, 4); 1338 if (r & DC_PSTATE_D3) { 1339 u_int32_t iobase, membase, irq; 1340 1341 /* Save important PCI config data. */ 1342 iobase = pci_read_config(dev, DC_PCI_CFBIO, 4); 1343 membase = pci_read_config(dev, DC_PCI_CFBMA, 4); 1344 irq = pci_read_config(dev, DC_PCI_CFIT, 4); 1345 1346 /* Reset the power state. */ 1347 printf("dc%d: chip is in D%d power mode " 1348 "-- setting to D0\n", unit, r & DC_PSTATE_D3); 1349 r &= 0xFFFFFFFC; 1350 pci_write_config(dev, cptr + 4, r, 4); 1351 1352 /* Restore PCI config data. */ 1353 pci_write_config(dev, DC_PCI_CFBIO, iobase, 4); 1354 pci_write_config(dev, DC_PCI_CFBMA, membase, 4); 1355 pci_write_config(dev, DC_PCI_CFIT, irq, 4); 1356 } 1357 } 1358 return; 1359 } 1360 1361 /* 1362 * Attach the interface. Allocate softc structures, do ifmedia 1363 * setup and ethernet/BPF attach. 1364 */ 1365 static int dc_attach(dev) 1366 device_t dev; 1367 { 1368 int s; 1369 u_char eaddr[ETHER_ADDR_LEN]; 1370 u_int32_t command; 1371 struct dc_softc *sc; 1372 struct ifnet *ifp; 1373 u_int32_t revision; 1374 int unit, error = 0, rid, mac_offset; 1375 1376 s = splimp(); 1377 1378 sc = device_get_softc(dev); 1379 unit = device_get_unit(dev); 1380 bzero(sc, sizeof(struct dc_softc)); 1381 1382 /* 1383 * Handle power management nonsense. 1384 */ 1385 dc_acpi(dev); 1386 1387 /* 1388 * Map control/status registers. 1389 */ 1390 command = pci_read_config(dev, PCI_COMMAND_STATUS_REG, 4); 1391 command |= (PCIM_CMD_PORTEN|PCIM_CMD_MEMEN|PCIM_CMD_BUSMASTEREN); 1392 pci_write_config(dev, PCI_COMMAND_STATUS_REG, command, 4); 1393 command = pci_read_config(dev, PCI_COMMAND_STATUS_REG, 4); 1394 1395 #ifdef DC_USEIOSPACE 1396 if (!(command & PCIM_CMD_PORTEN)) { 1397 printf("dc%d: failed to enable I/O ports!\n", unit); 1398 error = ENXIO; 1399 goto fail; 1400 } 1401 #else 1402 if (!(command & PCIM_CMD_MEMEN)) { 1403 printf("dc%d: failed to enable memory mapping!\n", unit); 1404 error = ENXIO; 1405 goto fail; 1406 } 1407 #endif 1408 1409 rid = DC_RID; 1410 sc->dc_res = bus_alloc_resource(dev, DC_RES, &rid, 1411 0, ~0, 1, RF_ACTIVE); 1412 1413 if (sc->dc_res == NULL) { 1414 printf("dc%d: couldn't map ports/memory\n", unit); 1415 error = ENXIO; 1416 goto fail; 1417 } 1418 1419 sc->dc_btag = rman_get_bustag(sc->dc_res); 1420 sc->dc_bhandle = rman_get_bushandle(sc->dc_res); 1421 1422 /* Allocate interrupt */ 1423 rid = 0; 1424 sc->dc_irq = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, 0, ~0, 1, 1425 RF_SHAREABLE | RF_ACTIVE); 1426 1427 if (sc->dc_irq == NULL) { 1428 printf("dc%d: couldn't map interrupt\n", unit); 1429 bus_release_resource(dev, DC_RES, DC_RID, sc->dc_res); 1430 error = ENXIO; 1431 goto fail; 1432 } 1433 1434 error = bus_setup_intr(dev, sc->dc_irq, INTR_TYPE_NET, 1435 dc_intr, sc, &sc->dc_intrhand); 1436 1437 if (error) { 1438 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->dc_irq); 1439 bus_release_resource(dev, DC_RES, DC_RID, sc->dc_res); 1440 printf("dc%d: couldn't set up irq\n", unit); 1441 goto fail; 1442 } 1443 1444 /* Need this info to decide on a chip type. */ 1445 sc->dc_info = dc_devtype(dev); 1446 revision = pci_read_config(dev, DC_PCI_CFRV, 4) & 0x000000FF; 1447 1448 switch(sc->dc_info->dc_did) { 1449 case DC_DEVICEID_21143: 1450 sc->dc_type = DC_TYPE_21143; 1451 sc->dc_flags |= DC_TX_POLL|DC_TX_USE_TX_INTR; 1452 sc->dc_flags |= DC_REDUCED_MII_POLL; 1453 break; 1454 case DC_DEVICEID_DM9100: 1455 case DC_DEVICEID_DM9102: 1456 sc->dc_type = DC_TYPE_DM9102; 1457 sc->dc_flags |= DC_TX_USE_TX_INTR; 1458 sc->dc_flags |= DC_REDUCED_MII_POLL; 1459 sc->dc_pmode = DC_PMODE_MII; 1460 break; 1461 case DC_DEVICEID_AL981: 1462 sc->dc_type = DC_TYPE_AL981; 1463 sc->dc_flags |= DC_TX_USE_TX_INTR; 1464 sc->dc_flags |= DC_TX_ADMTEK_WAR; 1465 sc->dc_pmode = DC_PMODE_MII; 1466 break; 1467 case DC_DEVICEID_AN985: 1468 sc->dc_type = DC_TYPE_AN985; 1469 sc->dc_flags |= DC_TX_USE_TX_INTR; 1470 sc->dc_flags |= DC_TX_ADMTEK_WAR; 1471 sc->dc_pmode = DC_PMODE_MII; 1472 break; 1473 case DC_DEVICEID_98713: 1474 case DC_DEVICEID_98713_CP: 1475 if (revision < DC_REVISION_98713A) { 1476 sc->dc_type = DC_TYPE_98713; 1477 sc->dc_flags |= DC_REDUCED_MII_POLL; 1478 } 1479 if (revision >= DC_REVISION_98713A) 1480 sc->dc_type = DC_TYPE_98713A; 1481 sc->dc_flags |= DC_TX_POLL|DC_TX_USE_TX_INTR; 1482 break; 1483 case DC_DEVICEID_987x5: 1484 sc->dc_type = DC_TYPE_987x5; 1485 sc->dc_flags |= DC_TX_POLL|DC_TX_USE_TX_INTR; 1486 break; 1487 case DC_DEVICEID_82C115: 1488 sc->dc_type = DC_TYPE_PNICII; 1489 sc->dc_flags |= DC_TX_POLL|DC_TX_USE_TX_INTR; 1490 break; 1491 case DC_DEVICEID_82C168: 1492 sc->dc_type = DC_TYPE_PNIC; 1493 sc->dc_flags |= DC_TX_STORENFWD|DC_TX_INTR_ALWAYS; 1494 sc->dc_flags |= DC_PNIC_RX_BUG_WAR; 1495 sc->dc_pnic_rx_buf = malloc(DC_RXLEN * 5, M_DEVBUF, M_NOWAIT); 1496 if (revision < DC_REVISION_82C169) 1497 sc->dc_pmode = DC_PMODE_SYM; 1498 break; 1499 case DC_DEVICEID_AX88140A: 1500 sc->dc_type = DC_TYPE_ASIX; 1501 sc->dc_flags |= DC_TX_USE_TX_INTR|DC_TX_INTR_FIRSTFRAG; 1502 sc->dc_flags |= DC_REDUCED_MII_POLL; 1503 sc->dc_pmode = DC_PMODE_MII; 1504 break; 1505 default: 1506 printf("dc%d: unknown device: %x\n", sc->dc_unit, 1507 sc->dc_info->dc_did); 1508 break; 1509 } 1510 1511 /* Save the cache line size. */ 1512 sc->dc_cachesize = pci_read_config(dev, DC_PCI_CFLT, 4) & 0xFF; 1513 1514 /* Reset the adapter. */ 1515 dc_reset(sc); 1516 1517 /* Take 21143 out of snooze mode */ 1518 if (DC_IS_INTEL(sc)) { 1519 command = pci_read_config(dev, DC_PCI_CFDD, 4); 1520 command &= ~(DC_CFDD_SNOOZE_MODE|DC_CFDD_SLEEP_MODE); 1521 pci_write_config(dev, DC_PCI_CFDD, command, 4); 1522 } 1523 1524 /* 1525 * Try to learn something about the supported media. 1526 * We know that ASIX and ADMtek and Davicom devices 1527 * will *always* be using MII media, so that's a no-brainer. 1528 * The tricky ones are the Macronix/PNIC II and the 1529 * Intel 21143. 1530 */ 1531 if (DC_IS_INTEL(sc)) { 1532 u_int32_t media, cwuc; 1533 cwuc = pci_read_config(dev, DC_PCI_CWUC, 4); 1534 cwuc |= DC_CWUC_FORCE_WUL; 1535 pci_write_config(dev, DC_PCI_CWUC, cwuc, 4); 1536 DELAY(10000); 1537 media = pci_read_config(dev, DC_PCI_CWUC, 4); 1538 cwuc &= ~DC_CWUC_FORCE_WUL; 1539 pci_write_config(dev, DC_PCI_CWUC, cwuc, 4); 1540 DELAY(10000); 1541 if (media & DC_CWUC_MII_ABILITY) 1542 sc->dc_pmode = DC_PMODE_MII; 1543 if (media & DC_CWUC_SYM_ABILITY) 1544 sc->dc_pmode = DC_PMODE_SYM; 1545 /* 1546 * If none of the bits are set, then this NIC 1547 * isn't meant to support 'wake up LAN' mode. 1548 * This is usually only the case on multiport 1549 * cards, and these cards almost always have 1550 * MII transceivers. 1551 */ 1552 if (media == 0) 1553 sc->dc_pmode = DC_PMODE_MII; 1554 } else if (DC_IS_MACRONIX(sc) || DC_IS_PNICII(sc)) { 1555 if (sc->dc_type == DC_TYPE_98713) 1556 sc->dc_pmode = DC_PMODE_MII; 1557 else 1558 sc->dc_pmode = DC_PMODE_SYM; 1559 } else if (!sc->dc_pmode) 1560 sc->dc_pmode = DC_PMODE_MII; 1561 1562 /* 1563 * Get station address from the EEPROM. 1564 */ 1565 switch(sc->dc_type) { 1566 case DC_TYPE_98713: 1567 case DC_TYPE_98713A: 1568 case DC_TYPE_987x5: 1569 case DC_TYPE_PNICII: 1570 dc_read_eeprom(sc, (caddr_t)&mac_offset, 1571 (DC_EE_NODEADDR_OFFSET / 2), 1, 0); 1572 dc_read_eeprom(sc, (caddr_t)&eaddr, (mac_offset / 2), 3, 0); 1573 break; 1574 case DC_TYPE_PNIC: 1575 dc_read_eeprom(sc, (caddr_t)&eaddr, 0, 3, 1); 1576 break; 1577 case DC_TYPE_DM9102: 1578 case DC_TYPE_21143: 1579 case DC_TYPE_ASIX: 1580 dc_read_eeprom(sc, (caddr_t)&eaddr, DC_EE_NODEADDR, 3, 0); 1581 break; 1582 case DC_TYPE_AL981: 1583 case DC_TYPE_AN985: 1584 dc_read_eeprom(sc, (caddr_t)&eaddr, DC_AL_EE_NODEADDR, 3, 0); 1585 break; 1586 default: 1587 dc_read_eeprom(sc, (caddr_t)&eaddr, DC_EE_NODEADDR, 3, 0); 1588 break; 1589 } 1590 1591 /* 1592 * A 21143 or clone chip was detected. Inform the world. 1593 */ 1594 printf("dc%d: Ethernet address: %6D\n", unit, eaddr, ":"); 1595 1596 sc->dc_unit = unit; 1597 bcopy(eaddr, (char *)&sc->arpcom.ac_enaddr, ETHER_ADDR_LEN); 1598 1599 sc->dc_ldata = contigmalloc(sizeof(struct dc_list_data), M_DEVBUF, 1600 M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0); 1601 1602 if (sc->dc_ldata == NULL) { 1603 printf("dc%d: no memory for list buffers!\n", unit); 1604 bus_teardown_intr(dev, sc->dc_irq, sc->dc_intrhand); 1605 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->dc_irq); 1606 bus_release_resource(dev, DC_RES, DC_RID, sc->dc_res); 1607 error = ENXIO; 1608 goto fail; 1609 } 1610 1611 bzero(sc->dc_ldata, sizeof(struct dc_list_data)); 1612 1613 ifp = &sc->arpcom.ac_if; 1614 ifp->if_softc = sc; 1615 ifp->if_unit = unit; 1616 ifp->if_name = "dc"; 1617 ifp->if_mtu = ETHERMTU; 1618 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 1619 ifp->if_ioctl = dc_ioctl; 1620 ifp->if_output = ether_output; 1621 ifp->if_start = dc_start; 1622 ifp->if_watchdog = dc_watchdog; 1623 ifp->if_init = dc_init; 1624 ifp->if_baudrate = 10000000; 1625 ifp->if_snd.ifq_maxlen = DC_TX_LIST_CNT - 1; 1626 1627 /* 1628 * Do MII setup. 1629 */ 1630 error = mii_phy_probe(dev, &sc->dc_miibus, 1631 dc_ifmedia_upd, dc_ifmedia_sts); 1632 1633 if (error && DC_IS_INTEL(sc)) { 1634 sc->dc_pmode = DC_PMODE_SYM; 1635 mii_phy_probe(dev, &sc->dc_miibus, 1636 dc_ifmedia_upd, dc_ifmedia_sts); 1637 error = 0; 1638 } 1639 1640 if (error) { 1641 printf("dc%d: MII without any PHY!\n", sc->dc_unit); 1642 bus_teardown_intr(dev, sc->dc_irq, sc->dc_intrhand); 1643 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->dc_irq); 1644 bus_release_resource(dev, DC_RES, DC_RID, sc->dc_res); 1645 error = ENXIO; 1646 goto fail; 1647 } 1648 1649 /* 1650 * Call MI attach routines. 1651 */ 1652 if_attach(ifp); 1653 ether_ifattach(ifp); 1654 callout_handle_init(&sc->dc_stat_ch); 1655 1656 bpfattach(ifp, DLT_EN10MB, sizeof(struct ether_header)); 1657 1658 fail: 1659 splx(s); 1660 1661 return(error); 1662 } 1663 1664 static int dc_detach(dev) 1665 device_t dev; 1666 { 1667 struct dc_softc *sc; 1668 struct ifnet *ifp; 1669 int s; 1670 1671 s = splimp(); 1672 1673 sc = device_get_softc(dev); 1674 ifp = &sc->arpcom.ac_if; 1675 1676 dc_stop(sc); 1677 if_detach(ifp); 1678 1679 bus_generic_detach(dev); 1680 device_delete_child(dev, sc->dc_miibus); 1681 1682 bus_teardown_intr(dev, sc->dc_irq, sc->dc_intrhand); 1683 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->dc_irq); 1684 bus_release_resource(dev, DC_RES, DC_RID, sc->dc_res); 1685 1686 contigfree(sc->dc_ldata, sizeof(struct dc_list_data), M_DEVBUF); 1687 if (sc->dc_pnic_rx_buf != NULL) 1688 free(sc->dc_pnic_rx_buf, M_DEVBUF); 1689 1690 splx(s); 1691 1692 return(0); 1693 } 1694 1695 /* 1696 * Initialize the transmit descriptors. 1697 */ 1698 static int dc_list_tx_init(sc) 1699 struct dc_softc *sc; 1700 { 1701 struct dc_chain_data *cd; 1702 struct dc_list_data *ld; 1703 int i; 1704 1705 cd = &sc->dc_cdata; 1706 ld = sc->dc_ldata; 1707 for (i = 0; i < DC_TX_LIST_CNT; i++) { 1708 if (i == (DC_TX_LIST_CNT - 1)) { 1709 ld->dc_tx_list[i].dc_next = 1710 vtophys(&ld->dc_tx_list[0]); 1711 } else { 1712 ld->dc_tx_list[i].dc_next = 1713 vtophys(&ld->dc_tx_list[i + 1]); 1714 } 1715 cd->dc_tx_chain[i] = NULL; 1716 ld->dc_tx_list[i].dc_data = 0; 1717 ld->dc_tx_list[i].dc_ctl = 0; 1718 } 1719 1720 cd->dc_tx_prod = cd->dc_tx_cons = cd->dc_tx_cnt = 0; 1721 1722 return(0); 1723 } 1724 1725 1726 /* 1727 * Initialize the RX descriptors and allocate mbufs for them. Note that 1728 * we arrange the descriptors in a closed ring, so that the last descriptor 1729 * points back to the first. 1730 */ 1731 static int dc_list_rx_init(sc) 1732 struct dc_softc *sc; 1733 { 1734 struct dc_chain_data *cd; 1735 struct dc_list_data *ld; 1736 int i; 1737 1738 cd = &sc->dc_cdata; 1739 ld = sc->dc_ldata; 1740 1741 for (i = 0; i < DC_RX_LIST_CNT; i++) { 1742 if (dc_newbuf(sc, i, NULL) == ENOBUFS) 1743 return(ENOBUFS); 1744 if (i == (DC_RX_LIST_CNT - 1)) { 1745 ld->dc_rx_list[i].dc_next = 1746 vtophys(&ld->dc_rx_list[0]); 1747 } else { 1748 ld->dc_rx_list[i].dc_next = 1749 vtophys(&ld->dc_rx_list[i + 1]); 1750 } 1751 } 1752 1753 cd->dc_rx_prod = 0; 1754 1755 return(0); 1756 } 1757 1758 /* 1759 * Initialize an RX descriptor and attach an MBUF cluster. 1760 */ 1761 static int dc_newbuf(sc, i, m) 1762 struct dc_softc *sc; 1763 int i; 1764 struct mbuf *m; 1765 { 1766 struct mbuf *m_new = NULL; 1767 struct dc_desc *c; 1768 1769 c = &sc->dc_ldata->dc_rx_list[i]; 1770 1771 if (m == NULL) { 1772 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 1773 if (m_new == NULL) { 1774 printf("dc%d: no memory for rx list " 1775 "-- packet dropped!\n", sc->dc_unit); 1776 return(ENOBUFS); 1777 } 1778 1779 MCLGET(m_new, M_DONTWAIT); 1780 if (!(m_new->m_flags & M_EXT)) { 1781 printf("dc%d: no memory for rx list " 1782 "-- packet dropped!\n", sc->dc_unit); 1783 m_freem(m_new); 1784 return(ENOBUFS); 1785 } 1786 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 1787 } else { 1788 m_new = m; 1789 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 1790 m_new->m_data = m_new->m_ext.ext_buf; 1791 } 1792 1793 m_adj(m_new, sizeof(u_int64_t)); 1794 1795 /* 1796 * If this is a PNIC chip, zero the buffer. This is part 1797 * of the workaround for the receive bug in the 82c168 and 1798 * 82c169 chips. 1799 */ 1800 if (sc->dc_flags & DC_PNIC_RX_BUG_WAR) 1801 bzero((char *)mtod(m_new, char *), m_new->m_len); 1802 1803 sc->dc_cdata.dc_rx_chain[i] = m_new; 1804 c->dc_data = vtophys(mtod(m_new, caddr_t)); 1805 c->dc_ctl = DC_RXCTL_RLINK | DC_RXLEN; 1806 c->dc_status = DC_RXSTAT_OWN; 1807 1808 return(0); 1809 } 1810 1811 /* 1812 * Grrrrr. 1813 * The PNIC chip has a terrible bug in it that manifests itself during 1814 * periods of heavy activity. The exact mode of failure if difficult to 1815 * pinpoint: sometimes it only happens in promiscuous mode, sometimes it 1816 * will happen on slow machines. The bug is that sometimes instead of 1817 * uploading one complete frame during reception, it uploads what looks 1818 * like the entire contents of its FIFO memory. The frame we want is at 1819 * the end of the whole mess, but we never know exactly how much data has 1820 * been uploaded, so salvaging the frame is hard. 1821 * 1822 * There is only one way to do it reliably, and it's disgusting. 1823 * Here's what we know: 1824 * 1825 * - We know there will always be somewhere between one and three extra 1826 * descriptors uploaded. 1827 * 1828 * - We know the desired received frame will always be at the end of the 1829 * total data upload. 1830 * 1831 * - We know the size of the desired received frame because it will be 1832 * provided in the length field of the status word in the last descriptor. 1833 * 1834 * Here's what we do: 1835 * 1836 * - When we allocate buffers for the receive ring, we bzero() them. 1837 * This means that we know that the buffer contents should be all 1838 * zeros, except for data uploaded by the chip. 1839 * 1840 * - We also force the PNIC chip to upload frames that include the 1841 * ethernet CRC at the end. 1842 * 1843 * - We gather all of the bogus frame data into a single buffer. 1844 * 1845 * - We then position a pointer at the end of this buffer and scan 1846 * backwards until we encounter the first non-zero byte of data. 1847 * This is the end of the received frame. We know we will encounter 1848 * some data at the end of the frame because the CRC will always be 1849 * there, so even if the sender transmits a packet of all zeros, 1850 * we won't be fooled. 1851 * 1852 * - We know the size of the actual received frame, so we subtract 1853 * that value from the current pointer location. This brings us 1854 * to the start of the actual received packet. 1855 * 1856 * - We copy this into an mbuf and pass it on, along with the actual 1857 * frame length. 1858 * 1859 * The performance hit is tremendous, but it beats dropping frames all 1860 * the time. 1861 */ 1862 1863 #define DC_WHOLEFRAME (DC_RXSTAT_FIRSTFRAG|DC_RXSTAT_LASTFRAG) 1864 static void dc_pnic_rx_bug_war(sc, idx) 1865 struct dc_softc *sc; 1866 int idx; 1867 { 1868 struct dc_desc *cur_rx; 1869 struct dc_desc *c = NULL; 1870 struct mbuf *m = NULL; 1871 unsigned char *ptr; 1872 int i, total_len; 1873 u_int32_t rxstat = 0; 1874 1875 i = sc->dc_pnic_rx_bug_save; 1876 cur_rx = &sc->dc_ldata->dc_rx_list[idx]; 1877 ptr = sc->dc_pnic_rx_buf; 1878 bzero(ptr, sizeof(DC_RXLEN * 5)); 1879 1880 /* Copy all the bytes from the bogus buffers. */ 1881 while (1) { 1882 c = &sc->dc_ldata->dc_rx_list[i]; 1883 rxstat = c->dc_status; 1884 m = sc->dc_cdata.dc_rx_chain[i]; 1885 bcopy(mtod(m, char *), ptr, DC_RXLEN); 1886 ptr += DC_RXLEN; 1887 /* If this is the last buffer, break out. */ 1888 if (i == idx || rxstat & DC_RXSTAT_LASTFRAG) 1889 break; 1890 dc_newbuf(sc, i, m); 1891 DC_INC(i, DC_RX_LIST_CNT); 1892 } 1893 1894 /* Find the length of the actual receive frame. */ 1895 total_len = DC_RXBYTES(rxstat); 1896 1897 /* Scan backwards until we hit a non-zero byte. */ 1898 while(*ptr == 0x00) 1899 ptr--; 1900 1901 /* Round off. */ 1902 if ((uintptr_t)(ptr) & 0x3) 1903 ptr -= 1; 1904 1905 /* Now find the start of the frame. */ 1906 ptr -= total_len; 1907 if (ptr < sc->dc_pnic_rx_buf) 1908 ptr = sc->dc_pnic_rx_buf; 1909 1910 /* 1911 * Now copy the salvaged frame to the last mbuf and fake up 1912 * the status word to make it look like a successful 1913 * frame reception. 1914 */ 1915 dc_newbuf(sc, i, m); 1916 bcopy(ptr, mtod(m, char *), total_len); 1917 cur_rx->dc_status = rxstat | DC_RXSTAT_FIRSTFRAG; 1918 1919 return; 1920 } 1921 1922 /* 1923 * This routine searches the RX ring for dirty descriptors in the 1924 * event that the rxeof routine falls out of sync with the chip's 1925 * current descriptor pointer. This may happen sometimes as a result 1926 * of a "no RX buffer available" condition that happens when the chip 1927 * consumes all of the RX buffers before the driver has a chance to 1928 * process the RX ring. This routine may need to be called more than 1929 * once to bring the driver back in sync with the chip, however we 1930 * should still be getting RX DONE interrupts to drive the search 1931 * for new packets in the RX ring, so we should catch up eventually. 1932 */ 1933 static int dc_rx_resync(sc) 1934 struct dc_softc *sc; 1935 { 1936 int i, pos; 1937 struct dc_desc *cur_rx; 1938 1939 pos = sc->dc_cdata.dc_rx_prod; 1940 1941 for (i = 0; i < DC_RX_LIST_CNT; i++) { 1942 cur_rx = &sc->dc_ldata->dc_rx_list[pos]; 1943 if (!(cur_rx->dc_status & DC_RXSTAT_OWN)) 1944 break; 1945 DC_INC(pos, DC_RX_LIST_CNT); 1946 } 1947 1948 /* If the ring really is empty, then just return. */ 1949 if (i == DC_RX_LIST_CNT) 1950 return(0); 1951 1952 /* We've fallen behing the chip: catch it. */ 1953 sc->dc_cdata.dc_rx_prod = pos; 1954 1955 return(EAGAIN); 1956 } 1957 1958 /* 1959 * A frame has been uploaded: pass the resulting mbuf chain up to 1960 * the higher level protocols. 1961 */ 1962 static void dc_rxeof(sc) 1963 struct dc_softc *sc; 1964 { 1965 struct ether_header *eh; 1966 struct mbuf *m; 1967 struct ifnet *ifp; 1968 struct dc_desc *cur_rx; 1969 int i, total_len = 0; 1970 u_int32_t rxstat; 1971 1972 ifp = &sc->arpcom.ac_if; 1973 i = sc->dc_cdata.dc_rx_prod; 1974 1975 while(!(sc->dc_ldata->dc_rx_list[i].dc_status & DC_RXSTAT_OWN)) { 1976 struct mbuf *m0 = NULL; 1977 1978 cur_rx = &sc->dc_ldata->dc_rx_list[i]; 1979 rxstat = cur_rx->dc_status; 1980 m = sc->dc_cdata.dc_rx_chain[i]; 1981 total_len = DC_RXBYTES(rxstat); 1982 1983 if (sc->dc_flags & DC_PNIC_RX_BUG_WAR) { 1984 if ((rxstat & DC_WHOLEFRAME) != DC_WHOLEFRAME) { 1985 if (rxstat & DC_RXSTAT_FIRSTFRAG) 1986 sc->dc_pnic_rx_bug_save = i; 1987 if ((rxstat & DC_RXSTAT_LASTFRAG) == 0) { 1988 DC_INC(i, DC_RX_LIST_CNT); 1989 continue; 1990 } 1991 dc_pnic_rx_bug_war(sc, i); 1992 rxstat = cur_rx->dc_status; 1993 total_len = DC_RXBYTES(rxstat); 1994 } 1995 } 1996 1997 sc->dc_cdata.dc_rx_chain[i] = NULL; 1998 1999 /* 2000 * If an error occurs, update stats, clear the 2001 * status word and leave the mbuf cluster in place: 2002 * it should simply get re-used next time this descriptor 2003 * comes up in the ring. 2004 */ 2005 if (rxstat & DC_RXSTAT_RXERR) { 2006 ifp->if_ierrors++; 2007 if (rxstat & DC_RXSTAT_COLLSEEN) 2008 ifp->if_collisions++; 2009 dc_newbuf(sc, i, m); 2010 if (rxstat & DC_RXSTAT_CRCERR) { 2011 DC_INC(i, DC_RX_LIST_CNT); 2012 continue; 2013 } else { 2014 dc_init(sc); 2015 return; 2016 } 2017 } 2018 2019 /* No errors; receive the packet. */ 2020 total_len -= ETHER_CRC_LEN; 2021 2022 m0 = m_devget(mtod(m, char *) - ETHER_ALIGN, 2023 total_len + ETHER_ALIGN, 0, ifp, NULL); 2024 dc_newbuf(sc, i, m); 2025 DC_INC(i, DC_RX_LIST_CNT); 2026 if (m0 == NULL) { 2027 ifp->if_ierrors++; 2028 continue; 2029 } 2030 m_adj(m0, ETHER_ALIGN); 2031 m = m0; 2032 2033 ifp->if_ipackets++; 2034 eh = mtod(m, struct ether_header *); 2035 2036 /* 2037 * Handle BPF listeners. Let the BPF user see the packet, but 2038 * don't pass it up to the ether_input() layer unless it's 2039 * a broadcast packet, multicast packet, matches our ethernet 2040 * address or the interface is in promiscuous mode. 2041 */ 2042 if (ifp->if_bpf) { 2043 bpf_mtap(ifp, m); 2044 if (ifp->if_flags & IFF_PROMISC && 2045 (bcmp(eh->ether_dhost, sc->arpcom.ac_enaddr, 2046 ETHER_ADDR_LEN) && 2047 (eh->ether_dhost[0] & 1) == 0)) { 2048 m_freem(m); 2049 continue; 2050 } 2051 } 2052 2053 /* Remove header from mbuf and pass it on. */ 2054 m_adj(m, sizeof(struct ether_header)); 2055 ether_input(ifp, eh, m); 2056 } 2057 2058 sc->dc_cdata.dc_rx_prod = i; 2059 2060 return; 2061 } 2062 2063 /* 2064 * A frame was downloaded to the chip. It's safe for us to clean up 2065 * the list buffers. 2066 */ 2067 2068 static void dc_txeof(sc) 2069 struct dc_softc *sc; 2070 { 2071 struct dc_desc *cur_tx = NULL; 2072 struct ifnet *ifp; 2073 int idx; 2074 2075 ifp = &sc->arpcom.ac_if; 2076 2077 /* Clear the timeout timer. */ 2078 ifp->if_timer = 0; 2079 2080 /* 2081 * Go through our tx list and free mbufs for those 2082 * frames that have been transmitted. 2083 */ 2084 idx = sc->dc_cdata.dc_tx_cons; 2085 while(idx != sc->dc_cdata.dc_tx_prod) { 2086 u_int32_t txstat; 2087 2088 cur_tx = &sc->dc_ldata->dc_tx_list[idx]; 2089 txstat = cur_tx->dc_status; 2090 2091 if (txstat & DC_TXSTAT_OWN) 2092 break; 2093 2094 if (!(cur_tx->dc_ctl & DC_TXCTL_LASTFRAG) || 2095 cur_tx->dc_ctl & DC_TXCTL_SETUP) { 2096 sc->dc_cdata.dc_tx_cnt--; 2097 if (cur_tx->dc_ctl & DC_TXCTL_SETUP) { 2098 /* 2099 * Yes, the PNIC is so brain damaged 2100 * that it will sometimes generate a TX 2101 * underrun error while DMAing the RX 2102 * filter setup frame. If we detect this, 2103 * we have to send the setup frame again, 2104 * or else the filter won't be programmed 2105 * correctly. 2106 */ 2107 if (DC_IS_PNIC(sc)) { 2108 if (txstat & DC_TXSTAT_ERRSUM) 2109 dc_setfilt(sc); 2110 } 2111 sc->dc_cdata.dc_tx_chain[idx] = NULL; 2112 } 2113 DC_INC(idx, DC_TX_LIST_CNT); 2114 continue; 2115 } 2116 2117 if (/*sc->dc_type == DC_TYPE_21143 &&*/ 2118 sc->dc_pmode == DC_PMODE_MII && 2119 ((txstat & 0xFFFF) & ~(DC_TXSTAT_ERRSUM| 2120 DC_TXSTAT_NOCARRIER|DC_TXSTAT_CARRLOST))) 2121 txstat &= ~DC_TXSTAT_ERRSUM; 2122 2123 if (txstat & DC_TXSTAT_ERRSUM) { 2124 ifp->if_oerrors++; 2125 if (txstat & DC_TXSTAT_EXCESSCOLL) 2126 ifp->if_collisions++; 2127 if (txstat & DC_TXSTAT_LATECOLL) 2128 ifp->if_collisions++; 2129 if (!(txstat & DC_TXSTAT_UNDERRUN)) { 2130 dc_init(sc); 2131 return; 2132 } 2133 } 2134 2135 ifp->if_collisions += (txstat & DC_TXSTAT_COLLCNT) >> 3; 2136 2137 ifp->if_opackets++; 2138 if (sc->dc_cdata.dc_tx_chain[idx] != NULL) { 2139 m_freem(sc->dc_cdata.dc_tx_chain[idx]); 2140 sc->dc_cdata.dc_tx_chain[idx] = NULL; 2141 } 2142 2143 sc->dc_cdata.dc_tx_cnt--; 2144 DC_INC(idx, DC_TX_LIST_CNT); 2145 } 2146 2147 sc->dc_cdata.dc_tx_cons = idx; 2148 if (cur_tx != NULL) 2149 ifp->if_flags &= ~IFF_OACTIVE; 2150 2151 return; 2152 } 2153 2154 static void dc_tick(xsc) 2155 void *xsc; 2156 { 2157 struct dc_softc *sc; 2158 struct mii_data *mii; 2159 struct ifnet *ifp; 2160 int s; 2161 u_int32_t r; 2162 2163 s = splimp(); 2164 2165 sc = xsc; 2166 ifp = &sc->arpcom.ac_if; 2167 mii = device_get_softc(sc->dc_miibus); 2168 2169 if (sc->dc_flags & DC_REDUCED_MII_POLL) { 2170 r = CSR_READ_4(sc, DC_ISR); 2171 if (DC_IS_INTEL(sc)) { 2172 if (r & DC_ISR_LINKFAIL) 2173 sc->dc_link = 0; 2174 if (sc->dc_link == 0) 2175 mii_tick(mii); 2176 } else { 2177 if ((r & DC_ISR_RX_STATE) == DC_RXSTATE_WAIT && 2178 sc->dc_cdata.dc_tx_prod == 0) 2179 mii_tick(mii); 2180 } 2181 } else 2182 mii_tick(mii); 2183 2184 /* 2185 * When the init routine completes, we expect to be able to send 2186 * packets right away, and in fact the network code will send a 2187 * gratuitous ARP the moment the init routine marks the interface 2188 * as running. However, even though the MAC may have been initialized, 2189 * there may be a delay of a few seconds before the PHY completes 2190 * autonegotiation and the link is brought up. Any transmissions 2191 * made during that delay will be lost. Dealing with this is tricky: 2192 * we can't just pause in the init routine while waiting for the 2193 * PHY to come ready since that would bring the whole system to 2194 * a screeching halt for several seconds. 2195 * 2196 * What we do here is prevent the TX start routine from sending 2197 * any packets until a link has been established. After the 2198 * interface has been initialized, the tick routine will poll 2199 * the state of the PHY until the IFM_ACTIVE flag is set. Until 2200 * that time, packets will stay in the send queue, and once the 2201 * link comes up, they will be flushed out to the wire. 2202 */ 2203 if (!sc->dc_link) { 2204 mii_pollstat(mii); 2205 if (mii->mii_media_status & IFM_ACTIVE && 2206 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) { 2207 sc->dc_link++; 2208 if (ifp->if_snd.ifq_head != NULL) 2209 dc_start(ifp); 2210 } 2211 } 2212 2213 sc->dc_stat_ch = timeout(dc_tick, sc, hz); 2214 2215 splx(s); 2216 2217 return; 2218 } 2219 2220 static void dc_intr(arg) 2221 void *arg; 2222 { 2223 struct dc_softc *sc; 2224 struct ifnet *ifp; 2225 u_int32_t status; 2226 2227 sc = arg; 2228 ifp = &sc->arpcom.ac_if; 2229 2230 /* Supress unwanted interrupts */ 2231 if (!(ifp->if_flags & IFF_UP)) { 2232 if (CSR_READ_4(sc, DC_ISR) & DC_INTRS) 2233 dc_stop(sc); 2234 return; 2235 } 2236 2237 /* Disable interrupts. */ 2238 CSR_WRITE_4(sc, DC_IMR, 0x00000000); 2239 2240 while((status = CSR_READ_4(sc, DC_ISR)) & DC_INTRS) { 2241 2242 CSR_WRITE_4(sc, DC_ISR, status); 2243 2244 if (status & DC_ISR_RX_OK) { 2245 int curpkts; 2246 curpkts = ifp->if_ipackets; 2247 dc_rxeof(sc); 2248 if (curpkts == ifp->if_ipackets) { 2249 while(dc_rx_resync(sc)) 2250 dc_rxeof(sc); 2251 } 2252 } 2253 2254 if (status & (DC_ISR_TX_OK|DC_ISR_TX_NOBUF)) 2255 dc_txeof(sc); 2256 2257 if (status & DC_ISR_TX_IDLE) { 2258 dc_txeof(sc); 2259 if (sc->dc_cdata.dc_tx_cnt) { 2260 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_TX_ON); 2261 CSR_WRITE_4(sc, DC_TXSTART, 0xFFFFFFFF); 2262 } 2263 } 2264 2265 if (status & DC_ISR_TX_UNDERRUN) { 2266 u_int32_t cfg; 2267 2268 printf("dc%d: TX underrun -- ", sc->dc_unit); 2269 if (DC_IS_DAVICOM(sc) || DC_IS_INTEL(sc)) 2270 dc_init(sc); 2271 cfg = CSR_READ_4(sc, DC_NETCFG); 2272 cfg &= ~DC_NETCFG_TX_THRESH; 2273 if (sc->dc_txthresh == DC_TXTHRESH_160BYTES) { 2274 printf("using store and forward mode\n"); 2275 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_STORENFWD); 2276 } else if (sc->dc_flags & DC_TX_STORENFWD) { 2277 printf("resetting\n"); 2278 } else { 2279 sc->dc_txthresh += 0x4000; 2280 printf("increasing TX threshold\n"); 2281 CSR_WRITE_4(sc, DC_NETCFG, cfg); 2282 DC_SETBIT(sc, DC_NETCFG, sc->dc_txthresh); 2283 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_STORENFWD); 2284 } 2285 } 2286 2287 if ((status & DC_ISR_RX_WATDOGTIMEO) 2288 || (status & DC_ISR_RX_NOBUF)) { 2289 int curpkts; 2290 curpkts = ifp->if_ipackets; 2291 dc_rxeof(sc); 2292 if (curpkts == ifp->if_ipackets) { 2293 while(dc_rx_resync(sc)) 2294 dc_rxeof(sc); 2295 } 2296 } 2297 2298 if (status & DC_ISR_BUS_ERR) { 2299 dc_reset(sc); 2300 dc_init(sc); 2301 } 2302 } 2303 2304 /* Re-enable interrupts. */ 2305 CSR_WRITE_4(sc, DC_IMR, DC_INTRS); 2306 2307 if (ifp->if_snd.ifq_head != NULL) 2308 dc_start(ifp); 2309 2310 return; 2311 } 2312 2313 /* 2314 * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data 2315 * pointers to the fragment pointers. 2316 */ 2317 static int dc_encap(sc, m_head, txidx) 2318 struct dc_softc *sc; 2319 struct mbuf *m_head; 2320 u_int32_t *txidx; 2321 { 2322 struct dc_desc *f = NULL; 2323 struct mbuf *m; 2324 int frag, cur, cnt = 0; 2325 2326 /* 2327 * Start packing the mbufs in this chain into 2328 * the fragment pointers. Stop when we run out 2329 * of fragments or hit the end of the mbuf chain. 2330 */ 2331 m = m_head; 2332 cur = frag = *txidx; 2333 2334 for (m = m_head; m != NULL; m = m->m_next) { 2335 if (m->m_len != 0) { 2336 if (sc->dc_flags & DC_TX_ADMTEK_WAR) { 2337 if (*txidx != sc->dc_cdata.dc_tx_prod && 2338 frag == (DC_TX_LIST_CNT - 1)) 2339 return(ENOBUFS); 2340 } 2341 if ((DC_TX_LIST_CNT - 2342 (sc->dc_cdata.dc_tx_cnt + cnt)) < 5) 2343 return(ENOBUFS); 2344 2345 f = &sc->dc_ldata->dc_tx_list[frag]; 2346 f->dc_ctl = DC_TXCTL_TLINK | m->m_len; 2347 if (cnt == 0) { 2348 f->dc_status = 0; 2349 f->dc_ctl |= DC_TXCTL_FIRSTFRAG; 2350 } else 2351 f->dc_status = DC_TXSTAT_OWN; 2352 f->dc_data = vtophys(mtod(m, vm_offset_t)); 2353 cur = frag; 2354 DC_INC(frag, DC_TX_LIST_CNT); 2355 cnt++; 2356 } 2357 } 2358 2359 if (m != NULL) 2360 return(ENOBUFS); 2361 2362 sc->dc_cdata.dc_tx_cnt += cnt; 2363 sc->dc_cdata.dc_tx_chain[cur] = m_head; 2364 sc->dc_ldata->dc_tx_list[cur].dc_ctl |= DC_TXCTL_LASTFRAG; 2365 if (sc->dc_flags & DC_TX_INTR_FIRSTFRAG) 2366 sc->dc_ldata->dc_tx_list[*txidx].dc_ctl |= DC_TXCTL_FINT; 2367 if (sc->dc_flags & DC_TX_INTR_ALWAYS) 2368 sc->dc_ldata->dc_tx_list[cur].dc_ctl |= DC_TXCTL_FINT; 2369 if (sc->dc_flags & DC_TX_USE_TX_INTR && sc->dc_cdata.dc_tx_cnt > 64) 2370 sc->dc_ldata->dc_tx_list[cur].dc_ctl |= DC_TXCTL_FINT; 2371 sc->dc_ldata->dc_tx_list[*txidx].dc_status = DC_TXSTAT_OWN; 2372 *txidx = frag; 2373 2374 return(0); 2375 } 2376 2377 /* 2378 * Main transmit routine. To avoid having to do mbuf copies, we put pointers 2379 * to the mbuf data regions directly in the transmit lists. We also save a 2380 * copy of the pointers since the transmit list fragment pointers are 2381 * physical addresses. 2382 */ 2383 2384 static void dc_start(ifp) 2385 struct ifnet *ifp; 2386 { 2387 struct dc_softc *sc; 2388 struct mbuf *m_head = NULL; 2389 int idx; 2390 2391 sc = ifp->if_softc; 2392 2393 if (!sc->dc_link) 2394 return; 2395 2396 if (ifp->if_flags & IFF_OACTIVE) 2397 return; 2398 2399 idx = sc->dc_cdata.dc_tx_prod; 2400 2401 while(sc->dc_cdata.dc_tx_chain[idx] == NULL) { 2402 IF_DEQUEUE(&ifp->if_snd, m_head); 2403 if (m_head == NULL) 2404 break; 2405 2406 if (dc_encap(sc, m_head, &idx)) { 2407 IF_PREPEND(&ifp->if_snd, m_head); 2408 ifp->if_flags |= IFF_OACTIVE; 2409 break; 2410 } 2411 2412 /* 2413 * If there's a BPF listener, bounce a copy of this frame 2414 * to him. 2415 */ 2416 if (ifp->if_bpf) 2417 bpf_mtap(ifp, m_head); 2418 } 2419 2420 /* Transmit */ 2421 sc->dc_cdata.dc_tx_prod = idx; 2422 if (!(sc->dc_flags & DC_TX_POLL)) 2423 CSR_WRITE_4(sc, DC_TXSTART, 0xFFFFFFFF); 2424 2425 /* 2426 * Set a timeout in case the chip goes out to lunch. 2427 */ 2428 ifp->if_timer = 5; 2429 2430 return; 2431 } 2432 2433 static void dc_init(xsc) 2434 void *xsc; 2435 { 2436 struct dc_softc *sc = xsc; 2437 struct ifnet *ifp = &sc->arpcom.ac_if; 2438 struct mii_data *mii; 2439 int s; 2440 2441 s = splimp(); 2442 2443 mii = device_get_softc(sc->dc_miibus); 2444 2445 /* 2446 * Cancel pending I/O and free all RX/TX buffers. 2447 */ 2448 dc_stop(sc); 2449 dc_reset(sc); 2450 2451 /* 2452 * Set cache alignment and burst length. 2453 */ 2454 if (DC_IS_ASIX(sc)) 2455 CSR_WRITE_4(sc, DC_BUSCTL, 0); 2456 else 2457 CSR_WRITE_4(sc, DC_BUSCTL, DC_BUSCTL_MRME|DC_BUSCTL_MRLE); 2458 if (DC_IS_DAVICOM(sc) || DC_IS_INTEL(sc)) { 2459 DC_SETBIT(sc, DC_BUSCTL, DC_BURSTLEN_USECA); 2460 } else { 2461 DC_SETBIT(sc, DC_BUSCTL, DC_BURSTLEN_16LONG); 2462 } 2463 if (sc->dc_flags & DC_TX_POLL) 2464 DC_SETBIT(sc, DC_BUSCTL, DC_TXPOLL_1); 2465 switch(sc->dc_cachesize) { 2466 case 32: 2467 DC_SETBIT(sc, DC_BUSCTL, DC_CACHEALIGN_32LONG); 2468 break; 2469 case 16: 2470 DC_SETBIT(sc, DC_BUSCTL, DC_CACHEALIGN_16LONG); 2471 break; 2472 case 8: 2473 DC_SETBIT(sc, DC_BUSCTL, DC_CACHEALIGN_8LONG); 2474 break; 2475 case 0: 2476 default: 2477 DC_SETBIT(sc, DC_BUSCTL, DC_CACHEALIGN_NONE); 2478 break; 2479 } 2480 2481 if (sc->dc_flags & DC_TX_STORENFWD) 2482 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_STORENFWD); 2483 else { 2484 if (sc->dc_txthresh == DC_TXTHRESH_160BYTES) { 2485 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_STORENFWD); 2486 } else { 2487 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_STORENFWD); 2488 DC_SETBIT(sc, DC_NETCFG, sc->dc_txthresh); 2489 } 2490 } 2491 2492 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_NO_RXCRC); 2493 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_TX_BACKOFF); 2494 2495 if (DC_IS_MACRONIX(sc) || DC_IS_PNICII(sc)) { 2496 /* 2497 * The app notes for the 98713 and 98715A say that 2498 * in order to have the chips operate properly, a magic 2499 * number must be written to CSR16. Macronix does not 2500 * document the meaning of these bits so there's no way 2501 * to know exactly what they do. The 98713 has a magic 2502 * number all its own; the rest all use a different one. 2503 */ 2504 DC_CLRBIT(sc, DC_MX_MAGICPACKET, 0xFFFF0000); 2505 if (sc->dc_type == DC_TYPE_98713) 2506 DC_SETBIT(sc, DC_MX_MAGICPACKET, DC_MX_MAGIC_98713); 2507 else 2508 DC_SETBIT(sc, DC_MX_MAGICPACKET, DC_MX_MAGIC_98715); 2509 } 2510 2511 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_TX_THRESH); 2512 DC_SETBIT(sc, DC_NETCFG, DC_TXTHRESH_72BYTES); 2513 2514 /* Init circular RX list. */ 2515 if (dc_list_rx_init(sc) == ENOBUFS) { 2516 printf("dc%d: initialization failed: no " 2517 "memory for rx buffers\n", sc->dc_unit); 2518 dc_stop(sc); 2519 (void)splx(s); 2520 return; 2521 } 2522 2523 /* 2524 * Init tx descriptors. 2525 */ 2526 dc_list_tx_init(sc); 2527 2528 /* 2529 * Load the address of the RX list. 2530 */ 2531 CSR_WRITE_4(sc, DC_RXADDR, vtophys(&sc->dc_ldata->dc_rx_list[0])); 2532 CSR_WRITE_4(sc, DC_TXADDR, vtophys(&sc->dc_ldata->dc_tx_list[0])); 2533 2534 /* 2535 * Enable interrupts. 2536 */ 2537 CSR_WRITE_4(sc, DC_IMR, DC_INTRS); 2538 CSR_WRITE_4(sc, DC_ISR, 0xFFFFFFFF); 2539 2540 /* Enable transmitter. */ 2541 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_TX_ON); 2542 2543 /* 2544 * Load the RX/multicast filter. We do this sort of late 2545 * because the filter programming scheme on the 21143 and 2546 * some clones requires DMAing a setup frame via the TX 2547 * engine, and we need the transmitter enabled for that. 2548 */ 2549 dc_setfilt(sc); 2550 2551 /* Enable receiver. */ 2552 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_ON); 2553 CSR_WRITE_4(sc, DC_RXSTART, 0xFFFFFFFF); 2554 2555 mii_mediachg(mii); 2556 dc_setcfg(sc, sc->dc_if_media); 2557 2558 ifp->if_flags |= IFF_RUNNING; 2559 ifp->if_flags &= ~IFF_OACTIVE; 2560 2561 (void)splx(s); 2562 2563 sc->dc_stat_ch = timeout(dc_tick, sc, hz); 2564 2565 return; 2566 } 2567 2568 /* 2569 * Set media options. 2570 */ 2571 static int dc_ifmedia_upd(ifp) 2572 struct ifnet *ifp; 2573 { 2574 struct dc_softc *sc; 2575 struct mii_data *mii; 2576 2577 sc = ifp->if_softc; 2578 mii = device_get_softc(sc->dc_miibus); 2579 mii_mediachg(mii); 2580 sc->dc_link = 0; 2581 2582 return(0); 2583 } 2584 2585 /* 2586 * Report current media status. 2587 */ 2588 static void dc_ifmedia_sts(ifp, ifmr) 2589 struct ifnet *ifp; 2590 struct ifmediareq *ifmr; 2591 { 2592 struct dc_softc *sc; 2593 struct mii_data *mii; 2594 2595 sc = ifp->if_softc; 2596 mii = device_get_softc(sc->dc_miibus); 2597 mii_pollstat(mii); 2598 ifmr->ifm_active = mii->mii_media_active; 2599 ifmr->ifm_status = mii->mii_media_status; 2600 2601 return; 2602 } 2603 2604 static int dc_ioctl(ifp, command, data) 2605 struct ifnet *ifp; 2606 u_long command; 2607 caddr_t data; 2608 { 2609 struct dc_softc *sc = ifp->if_softc; 2610 struct ifreq *ifr = (struct ifreq *) data; 2611 struct mii_data *mii; 2612 int s, error = 0; 2613 2614 s = splimp(); 2615 2616 switch(command) { 2617 case SIOCSIFADDR: 2618 case SIOCGIFADDR: 2619 case SIOCSIFMTU: 2620 error = ether_ioctl(ifp, command, data); 2621 break; 2622 case SIOCSIFFLAGS: 2623 if (ifp->if_flags & IFF_UP) { 2624 if (ifp->if_flags & IFF_RUNNING && 2625 ifp->if_flags & IFF_PROMISC && 2626 !(sc->dc_if_flags & IFF_PROMISC)) { 2627 dc_setfilt(sc); 2628 } else if (ifp->if_flags & IFF_RUNNING && 2629 !(ifp->if_flags & IFF_PROMISC) && 2630 sc->dc_if_flags & IFF_PROMISC) { 2631 dc_setfilt(sc); 2632 } else if (!(ifp->if_flags & IFF_RUNNING)) { 2633 sc->dc_txthresh = 0; 2634 dc_init(sc); 2635 } 2636 } else { 2637 if (ifp->if_flags & IFF_RUNNING) 2638 dc_stop(sc); 2639 } 2640 sc->dc_if_flags = ifp->if_flags; 2641 error = 0; 2642 break; 2643 case SIOCADDMULTI: 2644 case SIOCDELMULTI: 2645 dc_setfilt(sc); 2646 error = 0; 2647 break; 2648 case SIOCGIFMEDIA: 2649 case SIOCSIFMEDIA: 2650 mii = device_get_softc(sc->dc_miibus); 2651 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 2652 break; 2653 default: 2654 error = EINVAL; 2655 break; 2656 } 2657 2658 (void)splx(s); 2659 2660 return(error); 2661 } 2662 2663 static void dc_watchdog(ifp) 2664 struct ifnet *ifp; 2665 { 2666 struct dc_softc *sc; 2667 2668 sc = ifp->if_softc; 2669 2670 ifp->if_oerrors++; 2671 printf("dc%d: watchdog timeout\n", sc->dc_unit); 2672 2673 dc_stop(sc); 2674 dc_reset(sc); 2675 dc_init(sc); 2676 2677 if (ifp->if_snd.ifq_head != NULL) 2678 dc_start(ifp); 2679 2680 return; 2681 } 2682 2683 /* 2684 * Stop the adapter and free any mbufs allocated to the 2685 * RX and TX lists. 2686 */ 2687 static void dc_stop(sc) 2688 struct dc_softc *sc; 2689 { 2690 register int i; 2691 struct ifnet *ifp; 2692 2693 ifp = &sc->arpcom.ac_if; 2694 ifp->if_timer = 0; 2695 2696 untimeout(dc_tick, sc, sc->dc_stat_ch); 2697 2698 DC_CLRBIT(sc, DC_NETCFG, (DC_NETCFG_RX_ON|DC_NETCFG_TX_ON)); 2699 CSR_WRITE_4(sc, DC_IMR, 0x00000000); 2700 CSR_WRITE_4(sc, DC_TXADDR, 0x00000000); 2701 CSR_WRITE_4(sc, DC_RXADDR, 0x00000000); 2702 sc->dc_link = 0; 2703 2704 /* 2705 * Free data in the RX lists. 2706 */ 2707 for (i = 0; i < DC_RX_LIST_CNT; i++) { 2708 if (sc->dc_cdata.dc_rx_chain[i] != NULL) { 2709 m_freem(sc->dc_cdata.dc_rx_chain[i]); 2710 sc->dc_cdata.dc_rx_chain[i] = NULL; 2711 } 2712 } 2713 bzero((char *)&sc->dc_ldata->dc_rx_list, 2714 sizeof(sc->dc_ldata->dc_rx_list)); 2715 2716 /* 2717 * Free the TX list buffers. 2718 */ 2719 for (i = 0; i < DC_TX_LIST_CNT; i++) { 2720 if (sc->dc_cdata.dc_tx_chain[i] != NULL) { 2721 if (sc->dc_ldata->dc_tx_list[i].dc_ctl & 2722 DC_TXCTL_SETUP) { 2723 sc->dc_cdata.dc_tx_chain[i] = NULL; 2724 continue; 2725 } 2726 m_freem(sc->dc_cdata.dc_tx_chain[i]); 2727 sc->dc_cdata.dc_tx_chain[i] = NULL; 2728 } 2729 } 2730 2731 bzero((char *)&sc->dc_ldata->dc_tx_list, 2732 sizeof(sc->dc_ldata->dc_tx_list)); 2733 2734 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 2735 2736 return; 2737 } 2738 2739 /* 2740 * Stop all chip I/O so that the kernel's probe routines don't 2741 * get confused by errant DMAs when rebooting. 2742 */ 2743 static void dc_shutdown(dev) 2744 device_t dev; 2745 { 2746 struct dc_softc *sc; 2747 2748 sc = device_get_softc(dev); 2749 2750 dc_stop(sc); 2751 2752 return; 2753 } 2754