1 /* 2 * Copyright (c) 1997, 1998, 1999 3 * Bill Paul <wpaul@ee.columbia.edu>. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 3. All advertising materials mentioning features or use of this software 14 * must display the following acknowledgement: 15 * This product includes software developed by Bill Paul. 16 * 4. Neither the name of the author nor the names of any co-contributors 17 * may be used to endorse or promote products derived from this software 18 * without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30 * THE POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33 /* 34 * DEC "tulip" clone ethernet driver. Supports the DEC/Intel 21143 35 * series chips and several workalikes including the following: 36 * 37 * Macronix 98713/98715/98725/98727/98732 PMAC (www.macronix.com) 38 * Macronix/Lite-On 82c115 PNIC II (www.macronix.com) 39 * Lite-On 82c168/82c169 PNIC (www.litecom.com) 40 * ASIX Electronics AX88140A (www.asix.com.tw) 41 * ASIX Electronics AX88141 (www.asix.com.tw) 42 * ADMtek AL981 (www.admtek.com.tw) 43 * ADMtek AN985 (www.admtek.com.tw) 44 * Davicom DM9100, DM9102, DM9102A (www.davicom8.com) 45 * Accton EN1217 (www.accton.com) 46 * Xircom X3201 (www.xircom.com) 47 * Abocom FE2500 48 * Conexant LANfinity (www.conexant.com) 49 * 50 * Datasheets for the 21143 are available at developer.intel.com. 51 * Datasheets for the clone parts can be found at their respective sites. 52 * (Except for the PNIC; see www.freebsd.org/~wpaul/PNIC/pnic.ps.gz.) 53 * The PNIC II is essentially a Macronix 98715A chip; the only difference 54 * worth noting is that its multicast hash table is only 128 bits wide 55 * instead of 512. 56 * 57 * Written by Bill Paul <wpaul@ee.columbia.edu> 58 * Electrical Engineering Department 59 * Columbia University, New York City 60 */ 61 62 /* 63 * The Intel 21143 is the successor to the DEC 21140. It is basically 64 * the same as the 21140 but with a few new features. The 21143 supports 65 * three kinds of media attachments: 66 * 67 * o MII port, for 10Mbps and 100Mbps support and NWAY 68 * autonegotiation provided by an external PHY. 69 * o SYM port, for symbol mode 100Mbps support. 70 * o 10baseT port. 71 * o AUI/BNC port. 72 * 73 * The 100Mbps SYM port and 10baseT port can be used together in 74 * combination with the internal NWAY support to create a 10/100 75 * autosensing configuration. 76 * 77 * Note that not all tulip workalikes are handled in this driver: we only 78 * deal with those which are relatively well behaved. The Winbond is 79 * handled separately due to its different register offsets and the 80 * special handling needed for its various bugs. The PNIC is handled 81 * here, but I'm not thrilled about it. 82 * 83 * All of the workalike chips use some form of MII transceiver support 84 * with the exception of the Macronix chips, which also have a SYM port. 85 * The ASIX AX88140A is also documented to have a SYM port, but all 86 * the cards I've seen use an MII transceiver, probably because the 87 * AX88140A doesn't support internal NWAY. 88 */ 89 90 #include <sys/cdefs.h> 91 __FBSDID("$FreeBSD$"); 92 93 #include <sys/param.h> 94 #include <sys/systm.h> 95 #include <sys/sockio.h> 96 #include <sys/mbuf.h> 97 #include <sys/malloc.h> 98 #include <sys/kernel.h> 99 #include <sys/socket.h> 100 #include <sys/sysctl.h> 101 102 #include <net/if.h> 103 #include <net/if_arp.h> 104 #include <net/ethernet.h> 105 #include <net/if_dl.h> 106 #include <net/if_media.h> 107 #include <net/if_types.h> 108 #include <net/if_vlan_var.h> 109 110 #include <net/bpf.h> 111 112 #include <vm/vm.h> /* for vtophys */ 113 #include <vm/pmap.h> /* for vtophys */ 114 #include <machine/bus_pio.h> 115 #include <machine/bus_memio.h> 116 #include <machine/bus.h> 117 #include <machine/resource.h> 118 #include <sys/bus.h> 119 #include <sys/rman.h> 120 121 #include <dev/mii/mii.h> 122 #include <dev/mii/miivar.h> 123 124 #include <pci/pcireg.h> 125 #include <pci/pcivar.h> 126 127 #define DC_USEIOSPACE 128 #ifdef __alpha__ 129 #define SRM_MEDIA 130 #endif 131 132 #include <pci/if_dcreg.h> 133 134 MODULE_DEPEND(dc, pci, 1, 1, 1); 135 MODULE_DEPEND(dc, ether, 1, 1, 1); 136 MODULE_DEPEND(dc, miibus, 1, 1, 1); 137 138 /* "controller miibus0" required. See GENERIC if you get errors here. */ 139 #include "miibus_if.h" 140 141 /* 142 * Various supported device vendors/types and their names. 143 */ 144 static struct dc_type dc_devs[] = { 145 { DC_VENDORID_DEC, DC_DEVICEID_21143, 146 "Intel 21143 10/100BaseTX" }, 147 { DC_VENDORID_DAVICOM, DC_DEVICEID_DM9009, 148 "Davicom DM9009 10/100BaseTX" }, 149 { DC_VENDORID_DAVICOM, DC_DEVICEID_DM9100, 150 "Davicom DM9100 10/100BaseTX" }, 151 { DC_VENDORID_DAVICOM, DC_DEVICEID_DM9102, 152 "Davicom DM9102 10/100BaseTX" }, 153 { DC_VENDORID_DAVICOM, DC_DEVICEID_DM9102, 154 "Davicom DM9102A 10/100BaseTX" }, 155 { DC_VENDORID_ADMTEK, DC_DEVICEID_AL981, 156 "ADMtek AL981 10/100BaseTX" }, 157 { DC_VENDORID_ADMTEK, DC_DEVICEID_AN985, 158 "ADMtek AN985 10/100BaseTX" }, 159 { DC_VENDORID_ASIX, DC_DEVICEID_AX88140A, 160 "ASIX AX88140A 10/100BaseTX" }, 161 { DC_VENDORID_ASIX, DC_DEVICEID_AX88140A, 162 "ASIX AX88141 10/100BaseTX" }, 163 { DC_VENDORID_MX, DC_DEVICEID_98713, 164 "Macronix 98713 10/100BaseTX" }, 165 { DC_VENDORID_MX, DC_DEVICEID_98713, 166 "Macronix 98713A 10/100BaseTX" }, 167 { DC_VENDORID_CP, DC_DEVICEID_98713_CP, 168 "Compex RL100-TX 10/100BaseTX" }, 169 { DC_VENDORID_CP, DC_DEVICEID_98713_CP, 170 "Compex RL100-TX 10/100BaseTX" }, 171 { DC_VENDORID_MX, DC_DEVICEID_987x5, 172 "Macronix 98715/98715A 10/100BaseTX" }, 173 { DC_VENDORID_MX, DC_DEVICEID_987x5, 174 "Macronix 98715AEC-C 10/100BaseTX" }, 175 { DC_VENDORID_MX, DC_DEVICEID_987x5, 176 "Macronix 98725 10/100BaseTX" }, 177 { DC_VENDORID_MX, DC_DEVICEID_98727, 178 "Macronix 98727/98732 10/100BaseTX" }, 179 { DC_VENDORID_LO, DC_DEVICEID_82C115, 180 "LC82C115 PNIC II 10/100BaseTX" }, 181 { DC_VENDORID_LO, DC_DEVICEID_82C168, 182 "82c168 PNIC 10/100BaseTX" }, 183 { DC_VENDORID_LO, DC_DEVICEID_82C168, 184 "82c169 PNIC 10/100BaseTX" }, 185 { DC_VENDORID_ACCTON, DC_DEVICEID_EN1217, 186 "Accton EN1217 10/100BaseTX" }, 187 { DC_VENDORID_ACCTON, DC_DEVICEID_EN2242, 188 "Accton EN2242 MiniPCI 10/100BaseTX" }, 189 { DC_VENDORID_XIRCOM, DC_DEVICEID_X3201, 190 "Xircom X3201 10/100BaseTX" }, 191 { DC_VENDORID_ABOCOM, DC_DEVICEID_FE2500, 192 "Abocom FE2500 10/100BaseTX" }, 193 { DC_VENDORID_CONEXANT, DC_DEVICEID_RS7112, 194 "Conexant LANfinity MiniPCI 10/100BaseTX" }, 195 { DC_VENDORID_HAWKING, DC_DEVICEID_HAWKING_PN672TX, 196 "Hawking CB102 CardBus 10/100" }, 197 { DC_VENDORID_PLANEX, DC_DEVICEID_FNW3602T, 198 "PlaneX FNW-3602-T CardBus 10/100" }, 199 { 0, 0, NULL } 200 }; 201 202 static int dc_probe (device_t); 203 static int dc_attach (device_t); 204 static int dc_detach (device_t); 205 static int dc_suspend (device_t); 206 static int dc_resume (device_t); 207 static void dc_acpi (device_t); 208 static struct dc_type *dc_devtype (device_t); 209 static int dc_newbuf (struct dc_softc *, int, struct mbuf *); 210 static int dc_encap (struct dc_softc *, struct mbuf *, u_int32_t *); 211 static void dc_pnic_rx_bug_war (struct dc_softc *, int); 212 static int dc_rx_resync (struct dc_softc *); 213 static void dc_rxeof (struct dc_softc *); 214 static void dc_txeof (struct dc_softc *); 215 static void dc_tick (void *); 216 static void dc_tx_underrun (struct dc_softc *); 217 static void dc_intr (void *); 218 static void dc_start (struct ifnet *); 219 static int dc_ioctl (struct ifnet *, u_long, caddr_t); 220 static void dc_init (void *); 221 static void dc_stop (struct dc_softc *); 222 static void dc_watchdog (struct ifnet *); 223 static void dc_shutdown (device_t); 224 static int dc_ifmedia_upd (struct ifnet *); 225 static void dc_ifmedia_sts (struct ifnet *, struct ifmediareq *); 226 227 static void dc_delay (struct dc_softc *); 228 static void dc_eeprom_idle (struct dc_softc *); 229 static void dc_eeprom_putbyte (struct dc_softc *, int); 230 static void dc_eeprom_getword (struct dc_softc *, int, u_int16_t *); 231 static void dc_eeprom_getword_pnic 232 (struct dc_softc *, int, u_int16_t *); 233 static void dc_eeprom_getword_xircom 234 (struct dc_softc *, int, u_int16_t *); 235 static void dc_eeprom_width (struct dc_softc *); 236 static void dc_read_eeprom (struct dc_softc *, caddr_t, int, int, int); 237 238 static void dc_mii_writebit (struct dc_softc *, int); 239 static int dc_mii_readbit (struct dc_softc *); 240 static void dc_mii_sync (struct dc_softc *); 241 static void dc_mii_send (struct dc_softc *, u_int32_t, int); 242 static int dc_mii_readreg (struct dc_softc *, struct dc_mii_frame *); 243 static int dc_mii_writereg (struct dc_softc *, struct dc_mii_frame *); 244 static int dc_miibus_readreg (device_t, int, int); 245 static int dc_miibus_writereg (device_t, int, int, int); 246 static void dc_miibus_statchg (device_t); 247 static void dc_miibus_mediainit (device_t); 248 249 static void dc_setcfg (struct dc_softc *, int); 250 static u_int32_t dc_crc_le (struct dc_softc *, caddr_t); 251 static u_int32_t dc_crc_be (caddr_t); 252 static void dc_setfilt_21143 (struct dc_softc *); 253 static void dc_setfilt_asix (struct dc_softc *); 254 static void dc_setfilt_admtek (struct dc_softc *); 255 static void dc_setfilt_xircom (struct dc_softc *); 256 257 static void dc_setfilt (struct dc_softc *); 258 259 static void dc_reset (struct dc_softc *); 260 static int dc_list_rx_init (struct dc_softc *); 261 static int dc_list_tx_init (struct dc_softc *); 262 263 static void dc_read_srom (struct dc_softc *, int); 264 static void dc_parse_21143_srom (struct dc_softc *); 265 static void dc_decode_leaf_sia (struct dc_softc *, struct dc_eblock_sia *); 266 static void dc_decode_leaf_mii (struct dc_softc *, struct dc_eblock_mii *); 267 static void dc_decode_leaf_sym (struct dc_softc *, struct dc_eblock_sym *); 268 static void dc_apply_fixup (struct dc_softc *, int); 269 270 #ifdef DC_USEIOSPACE 271 #define DC_RES SYS_RES_IOPORT 272 #define DC_RID DC_PCI_CFBIO 273 #else 274 #define DC_RES SYS_RES_MEMORY 275 #define DC_RID DC_PCI_CFBMA 276 #endif 277 278 static device_method_t dc_methods[] = { 279 /* Device interface */ 280 DEVMETHOD(device_probe, dc_probe), 281 DEVMETHOD(device_attach, dc_attach), 282 DEVMETHOD(device_detach, dc_detach), 283 DEVMETHOD(device_suspend, dc_suspend), 284 DEVMETHOD(device_resume, dc_resume), 285 DEVMETHOD(device_shutdown, dc_shutdown), 286 287 /* bus interface */ 288 DEVMETHOD(bus_print_child, bus_generic_print_child), 289 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 290 291 /* MII interface */ 292 DEVMETHOD(miibus_readreg, dc_miibus_readreg), 293 DEVMETHOD(miibus_writereg, dc_miibus_writereg), 294 DEVMETHOD(miibus_statchg, dc_miibus_statchg), 295 DEVMETHOD(miibus_mediainit, dc_miibus_mediainit), 296 297 { 0, 0 } 298 }; 299 300 static driver_t dc_driver = { 301 "dc", 302 dc_methods, 303 sizeof(struct dc_softc) 304 }; 305 306 static devclass_t dc_devclass; 307 #ifdef __i386__ 308 static int dc_quick=1; 309 SYSCTL_INT(_hw, OID_AUTO, dc_quick, CTLFLAG_RW, 310 &dc_quick,0,"do not mdevget in dc driver"); 311 #endif 312 313 DRIVER_MODULE(dc, cardbus, dc_driver, dc_devclass, 0, 0); 314 DRIVER_MODULE(dc, pci, dc_driver, dc_devclass, 0, 0); 315 DRIVER_MODULE(miibus, dc, miibus_driver, miibus_devclass, 0, 0); 316 317 #define DC_SETBIT(sc, reg, x) \ 318 CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) | (x)) 319 320 #define DC_CLRBIT(sc, reg, x) \ 321 CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) & ~(x)) 322 323 #define SIO_SET(x) DC_SETBIT(sc, DC_SIO, (x)) 324 #define SIO_CLR(x) DC_CLRBIT(sc, DC_SIO, (x)) 325 326 #define IS_MPSAFE 0 327 328 static void 329 dc_delay(sc) 330 struct dc_softc *sc; 331 { 332 int idx; 333 334 for (idx = (300 / 33) + 1; idx > 0; idx--) 335 CSR_READ_4(sc, DC_BUSCTL); 336 } 337 338 static void 339 dc_eeprom_width(sc) 340 struct dc_softc *sc; 341 { 342 int i; 343 344 /* Force EEPROM to idle state. */ 345 dc_eeprom_idle(sc); 346 347 /* Enter EEPROM access mode. */ 348 CSR_WRITE_4(sc, DC_SIO, DC_SIO_EESEL); 349 dc_delay(sc); 350 DC_SETBIT(sc, DC_SIO, DC_SIO_ROMCTL_READ); 351 dc_delay(sc); 352 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); 353 dc_delay(sc); 354 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CS); 355 dc_delay(sc); 356 357 for (i = 3; i--;) { 358 if (6 & (1 << i)) 359 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_DATAIN); 360 else 361 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_DATAIN); 362 dc_delay(sc); 363 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CLK); 364 dc_delay(sc); 365 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); 366 dc_delay(sc); 367 } 368 369 for (i = 1; i <= 12; i++) { 370 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CLK); 371 dc_delay(sc); 372 if (!(CSR_READ_4(sc, DC_SIO) & DC_SIO_EE_DATAOUT)) { 373 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); 374 dc_delay(sc); 375 break; 376 } 377 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); 378 dc_delay(sc); 379 } 380 381 /* Turn off EEPROM access mode. */ 382 dc_eeprom_idle(sc); 383 384 if (i < 4 || i > 12) 385 sc->dc_romwidth = 6; 386 else 387 sc->dc_romwidth = i; 388 389 /* Enter EEPROM access mode. */ 390 CSR_WRITE_4(sc, DC_SIO, DC_SIO_EESEL); 391 dc_delay(sc); 392 DC_SETBIT(sc, DC_SIO, DC_SIO_ROMCTL_READ); 393 dc_delay(sc); 394 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); 395 dc_delay(sc); 396 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CS); 397 dc_delay(sc); 398 399 /* Turn off EEPROM access mode. */ 400 dc_eeprom_idle(sc); 401 } 402 403 static void 404 dc_eeprom_idle(sc) 405 struct dc_softc *sc; 406 { 407 register int i; 408 409 CSR_WRITE_4(sc, DC_SIO, DC_SIO_EESEL); 410 dc_delay(sc); 411 DC_SETBIT(sc, DC_SIO, DC_SIO_ROMCTL_READ); 412 dc_delay(sc); 413 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); 414 dc_delay(sc); 415 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CS); 416 dc_delay(sc); 417 418 for (i = 0; i < 25; i++) { 419 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); 420 dc_delay(sc); 421 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CLK); 422 dc_delay(sc); 423 } 424 425 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); 426 dc_delay(sc); 427 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CS); 428 dc_delay(sc); 429 CSR_WRITE_4(sc, DC_SIO, 0x00000000); 430 431 return; 432 } 433 434 /* 435 * Send a read command and address to the EEPROM, check for ACK. 436 */ 437 static void 438 dc_eeprom_putbyte(sc, addr) 439 struct dc_softc *sc; 440 int addr; 441 { 442 register int d, i; 443 444 d = DC_EECMD_READ >> 6; 445 for (i = 3; i--; ) { 446 if (d & (1 << i)) 447 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_DATAIN); 448 else 449 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_DATAIN); 450 dc_delay(sc); 451 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CLK); 452 dc_delay(sc); 453 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); 454 dc_delay(sc); 455 } 456 457 /* 458 * Feed in each bit and strobe the clock. 459 */ 460 for (i = sc->dc_romwidth; i--;) { 461 if (addr & (1 << i)) { 462 SIO_SET(DC_SIO_EE_DATAIN); 463 } else { 464 SIO_CLR(DC_SIO_EE_DATAIN); 465 } 466 dc_delay(sc); 467 SIO_SET(DC_SIO_EE_CLK); 468 dc_delay(sc); 469 SIO_CLR(DC_SIO_EE_CLK); 470 dc_delay(sc); 471 } 472 473 return; 474 } 475 476 /* 477 * Read a word of data stored in the EEPROM at address 'addr.' 478 * The PNIC 82c168/82c169 has its own non-standard way to read 479 * the EEPROM. 480 */ 481 static void 482 dc_eeprom_getword_pnic(sc, addr, dest) 483 struct dc_softc *sc; 484 int addr; 485 u_int16_t *dest; 486 { 487 register int i; 488 u_int32_t r; 489 490 CSR_WRITE_4(sc, DC_PN_SIOCTL, DC_PN_EEOPCODE_READ|addr); 491 492 for (i = 0; i < DC_TIMEOUT; i++) { 493 DELAY(1); 494 r = CSR_READ_4(sc, DC_SIO); 495 if (!(r & DC_PN_SIOCTL_BUSY)) { 496 *dest = (u_int16_t)(r & 0xFFFF); 497 return; 498 } 499 } 500 501 return; 502 } 503 504 /* 505 * Read a word of data stored in the EEPROM at address 'addr.' 506 * The Xircom X3201 has its own non-standard way to read 507 * the EEPROM, too. 508 */ 509 static void 510 dc_eeprom_getword_xircom(sc, addr, dest) 511 struct dc_softc *sc; 512 int addr; 513 u_int16_t *dest; 514 { 515 SIO_SET(DC_SIO_ROMSEL | DC_SIO_ROMCTL_READ); 516 517 addr *= 2; 518 CSR_WRITE_4(sc, DC_ROM, addr | 0x160); 519 *dest = (u_int16_t)CSR_READ_4(sc, DC_SIO)&0xff; 520 addr += 1; 521 CSR_WRITE_4(sc, DC_ROM, addr | 0x160); 522 *dest |= ((u_int16_t)CSR_READ_4(sc, DC_SIO)&0xff) << 8; 523 524 SIO_CLR(DC_SIO_ROMSEL | DC_SIO_ROMCTL_READ); 525 return; 526 } 527 528 /* 529 * Read a word of data stored in the EEPROM at address 'addr.' 530 */ 531 static void 532 dc_eeprom_getword(sc, addr, dest) 533 struct dc_softc *sc; 534 int addr; 535 u_int16_t *dest; 536 { 537 register int i; 538 u_int16_t word = 0; 539 540 /* Force EEPROM to idle state. */ 541 dc_eeprom_idle(sc); 542 543 /* Enter EEPROM access mode. */ 544 CSR_WRITE_4(sc, DC_SIO, DC_SIO_EESEL); 545 dc_delay(sc); 546 DC_SETBIT(sc, DC_SIO, DC_SIO_ROMCTL_READ); 547 dc_delay(sc); 548 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); 549 dc_delay(sc); 550 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CS); 551 dc_delay(sc); 552 553 /* 554 * Send address of word we want to read. 555 */ 556 dc_eeprom_putbyte(sc, addr); 557 558 /* 559 * Start reading bits from EEPROM. 560 */ 561 for (i = 0x8000; i; i >>= 1) { 562 SIO_SET(DC_SIO_EE_CLK); 563 dc_delay(sc); 564 if (CSR_READ_4(sc, DC_SIO) & DC_SIO_EE_DATAOUT) 565 word |= i; 566 dc_delay(sc); 567 SIO_CLR(DC_SIO_EE_CLK); 568 dc_delay(sc); 569 } 570 571 /* Turn off EEPROM access mode. */ 572 dc_eeprom_idle(sc); 573 574 *dest = word; 575 576 return; 577 } 578 579 /* 580 * Read a sequence of words from the EEPROM. 581 */ 582 static void 583 dc_read_eeprom(sc, dest, off, cnt, swap) 584 struct dc_softc *sc; 585 caddr_t dest; 586 int off; 587 int cnt; 588 int swap; 589 { 590 int i; 591 u_int16_t word = 0, *ptr; 592 593 for (i = 0; i < cnt; i++) { 594 if (DC_IS_PNIC(sc)) 595 dc_eeprom_getword_pnic(sc, off + i, &word); 596 else if (DC_IS_XIRCOM(sc)) 597 dc_eeprom_getword_xircom(sc, off + i, &word); 598 else 599 dc_eeprom_getword(sc, off + i, &word); 600 ptr = (u_int16_t *)(dest + (i * 2)); 601 if (swap) 602 *ptr = ntohs(word); 603 else 604 *ptr = word; 605 } 606 607 return; 608 } 609 610 /* 611 * The following two routines are taken from the Macronix 98713 612 * Application Notes pp.19-21. 613 */ 614 /* 615 * Write a bit to the MII bus. 616 */ 617 static void 618 dc_mii_writebit(sc, bit) 619 struct dc_softc *sc; 620 int bit; 621 { 622 if (bit) 623 CSR_WRITE_4(sc, DC_SIO, 624 DC_SIO_ROMCTL_WRITE|DC_SIO_MII_DATAOUT); 625 else 626 CSR_WRITE_4(sc, DC_SIO, DC_SIO_ROMCTL_WRITE); 627 628 DC_SETBIT(sc, DC_SIO, DC_SIO_MII_CLK); 629 DC_CLRBIT(sc, DC_SIO, DC_SIO_MII_CLK); 630 631 return; 632 } 633 634 /* 635 * Read a bit from the MII bus. 636 */ 637 static int 638 dc_mii_readbit(sc) 639 struct dc_softc *sc; 640 { 641 CSR_WRITE_4(sc, DC_SIO, DC_SIO_ROMCTL_READ|DC_SIO_MII_DIR); 642 CSR_READ_4(sc, DC_SIO); 643 DC_SETBIT(sc, DC_SIO, DC_SIO_MII_CLK); 644 DC_CLRBIT(sc, DC_SIO, DC_SIO_MII_CLK); 645 if (CSR_READ_4(sc, DC_SIO) & DC_SIO_MII_DATAIN) 646 return(1); 647 648 return(0); 649 } 650 651 /* 652 * Sync the PHYs by setting data bit and strobing the clock 32 times. 653 */ 654 static void 655 dc_mii_sync(sc) 656 struct dc_softc *sc; 657 { 658 register int i; 659 660 CSR_WRITE_4(sc, DC_SIO, DC_SIO_ROMCTL_WRITE); 661 662 for (i = 0; i < 32; i++) 663 dc_mii_writebit(sc, 1); 664 665 return; 666 } 667 668 /* 669 * Clock a series of bits through the MII. 670 */ 671 static void 672 dc_mii_send(sc, bits, cnt) 673 struct dc_softc *sc; 674 u_int32_t bits; 675 int cnt; 676 { 677 int i; 678 679 for (i = (0x1 << (cnt - 1)); i; i >>= 1) 680 dc_mii_writebit(sc, bits & i); 681 } 682 683 /* 684 * Read an PHY register through the MII. 685 */ 686 static int 687 dc_mii_readreg(sc, frame) 688 struct dc_softc *sc; 689 struct dc_mii_frame *frame; 690 691 { 692 int i, ack; 693 694 DC_LOCK(sc); 695 696 /* 697 * Set up frame for RX. 698 */ 699 frame->mii_stdelim = DC_MII_STARTDELIM; 700 frame->mii_opcode = DC_MII_READOP; 701 frame->mii_turnaround = 0; 702 frame->mii_data = 0; 703 704 /* 705 * Sync the PHYs. 706 */ 707 dc_mii_sync(sc); 708 709 /* 710 * Send command/address info. 711 */ 712 dc_mii_send(sc, frame->mii_stdelim, 2); 713 dc_mii_send(sc, frame->mii_opcode, 2); 714 dc_mii_send(sc, frame->mii_phyaddr, 5); 715 dc_mii_send(sc, frame->mii_regaddr, 5); 716 717 #ifdef notdef 718 /* Idle bit */ 719 dc_mii_writebit(sc, 1); 720 dc_mii_writebit(sc, 0); 721 #endif 722 723 /* Check for ack */ 724 ack = dc_mii_readbit(sc); 725 726 /* 727 * Now try reading data bits. If the ack failed, we still 728 * need to clock through 16 cycles to keep the PHY(s) in sync. 729 */ 730 if (ack) { 731 for(i = 0; i < 16; i++) { 732 dc_mii_readbit(sc); 733 } 734 goto fail; 735 } 736 737 for (i = 0x8000; i; i >>= 1) { 738 if (!ack) { 739 if (dc_mii_readbit(sc)) 740 frame->mii_data |= i; 741 } 742 } 743 744 fail: 745 746 dc_mii_writebit(sc, 0); 747 dc_mii_writebit(sc, 0); 748 749 DC_UNLOCK(sc); 750 751 if (ack) 752 return(1); 753 return(0); 754 } 755 756 /* 757 * Write to a PHY register through the MII. 758 */ 759 static int 760 dc_mii_writereg(sc, frame) 761 struct dc_softc *sc; 762 struct dc_mii_frame *frame; 763 764 { 765 DC_LOCK(sc); 766 /* 767 * Set up frame for TX. 768 */ 769 770 frame->mii_stdelim = DC_MII_STARTDELIM; 771 frame->mii_opcode = DC_MII_WRITEOP; 772 frame->mii_turnaround = DC_MII_TURNAROUND; 773 774 /* 775 * Sync the PHYs. 776 */ 777 dc_mii_sync(sc); 778 779 dc_mii_send(sc, frame->mii_stdelim, 2); 780 dc_mii_send(sc, frame->mii_opcode, 2); 781 dc_mii_send(sc, frame->mii_phyaddr, 5); 782 dc_mii_send(sc, frame->mii_regaddr, 5); 783 dc_mii_send(sc, frame->mii_turnaround, 2); 784 dc_mii_send(sc, frame->mii_data, 16); 785 786 /* Idle bit. */ 787 dc_mii_writebit(sc, 0); 788 dc_mii_writebit(sc, 0); 789 790 DC_UNLOCK(sc); 791 792 return(0); 793 } 794 795 static int 796 dc_miibus_readreg(dev, phy, reg) 797 device_t dev; 798 int phy, reg; 799 { 800 struct dc_mii_frame frame; 801 struct dc_softc *sc; 802 int i, rval, phy_reg = 0; 803 804 sc = device_get_softc(dev); 805 bzero((char *)&frame, sizeof(frame)); 806 807 /* 808 * Note: both the AL981 and AN985 have internal PHYs, 809 * however the AL981 provides direct access to the PHY 810 * registers while the AN985 uses a serial MII interface. 811 * The AN985's MII interface is also buggy in that you 812 * can read from any MII address (0 to 31), but only address 1 813 * behaves normally. To deal with both cases, we pretend 814 * that the PHY is at MII address 1. 815 */ 816 if (DC_IS_ADMTEK(sc) && phy != DC_ADMTEK_PHYADDR) 817 return(0); 818 819 /* 820 * Note: the ukphy probes of the RS7112 report a PHY at 821 * MII address 0 (possibly HomePNA?) and 1 (ethernet) 822 * so we only respond to correct one. 823 */ 824 if (DC_IS_CONEXANT(sc) && phy != DC_CONEXANT_PHYADDR) 825 return(0); 826 827 if (sc->dc_pmode != DC_PMODE_MII) { 828 if (phy == (MII_NPHY - 1)) { 829 switch(reg) { 830 case MII_BMSR: 831 /* 832 * Fake something to make the probe 833 * code think there's a PHY here. 834 */ 835 return(BMSR_MEDIAMASK); 836 break; 837 case MII_PHYIDR1: 838 if (DC_IS_PNIC(sc)) 839 return(DC_VENDORID_LO); 840 return(DC_VENDORID_DEC); 841 break; 842 case MII_PHYIDR2: 843 if (DC_IS_PNIC(sc)) 844 return(DC_DEVICEID_82C168); 845 return(DC_DEVICEID_21143); 846 break; 847 default: 848 return(0); 849 break; 850 } 851 } else 852 return(0); 853 } 854 855 if (DC_IS_PNIC(sc)) { 856 CSR_WRITE_4(sc, DC_PN_MII, DC_PN_MIIOPCODE_READ | 857 (phy << 23) | (reg << 18)); 858 for (i = 0; i < DC_TIMEOUT; i++) { 859 DELAY(1); 860 rval = CSR_READ_4(sc, DC_PN_MII); 861 if (!(rval & DC_PN_MII_BUSY)) { 862 rval &= 0xFFFF; 863 return(rval == 0xFFFF ? 0 : rval); 864 } 865 } 866 return(0); 867 } 868 869 if (DC_IS_COMET(sc)) { 870 switch(reg) { 871 case MII_BMCR: 872 phy_reg = DC_AL_BMCR; 873 break; 874 case MII_BMSR: 875 phy_reg = DC_AL_BMSR; 876 break; 877 case MII_PHYIDR1: 878 phy_reg = DC_AL_VENID; 879 break; 880 case MII_PHYIDR2: 881 phy_reg = DC_AL_DEVID; 882 break; 883 case MII_ANAR: 884 phy_reg = DC_AL_ANAR; 885 break; 886 case MII_ANLPAR: 887 phy_reg = DC_AL_LPAR; 888 break; 889 case MII_ANER: 890 phy_reg = DC_AL_ANER; 891 break; 892 default: 893 printf("dc%d: phy_read: bad phy register %x\n", 894 sc->dc_unit, reg); 895 return(0); 896 break; 897 } 898 899 rval = CSR_READ_4(sc, phy_reg) & 0x0000FFFF; 900 901 if (rval == 0xFFFF) 902 return(0); 903 return(rval); 904 } 905 906 frame.mii_phyaddr = phy; 907 frame.mii_regaddr = reg; 908 if (sc->dc_type == DC_TYPE_98713) { 909 phy_reg = CSR_READ_4(sc, DC_NETCFG); 910 CSR_WRITE_4(sc, DC_NETCFG, phy_reg & ~DC_NETCFG_PORTSEL); 911 } 912 dc_mii_readreg(sc, &frame); 913 if (sc->dc_type == DC_TYPE_98713) 914 CSR_WRITE_4(sc, DC_NETCFG, phy_reg); 915 916 return(frame.mii_data); 917 } 918 919 static int 920 dc_miibus_writereg(dev, phy, reg, data) 921 device_t dev; 922 int phy, reg, data; 923 { 924 struct dc_softc *sc; 925 struct dc_mii_frame frame; 926 int i, phy_reg = 0; 927 928 sc = device_get_softc(dev); 929 bzero((char *)&frame, sizeof(frame)); 930 931 if (DC_IS_ADMTEK(sc) && phy != DC_ADMTEK_PHYADDR) 932 return(0); 933 934 if (DC_IS_CONEXANT(sc) && phy != DC_CONEXANT_PHYADDR) 935 return(0); 936 937 if (DC_IS_PNIC(sc)) { 938 CSR_WRITE_4(sc, DC_PN_MII, DC_PN_MIIOPCODE_WRITE | 939 (phy << 23) | (reg << 10) | data); 940 for (i = 0; i < DC_TIMEOUT; i++) { 941 if (!(CSR_READ_4(sc, DC_PN_MII) & DC_PN_MII_BUSY)) 942 break; 943 } 944 return(0); 945 } 946 947 if (DC_IS_COMET(sc)) { 948 switch(reg) { 949 case MII_BMCR: 950 phy_reg = DC_AL_BMCR; 951 break; 952 case MII_BMSR: 953 phy_reg = DC_AL_BMSR; 954 break; 955 case MII_PHYIDR1: 956 phy_reg = DC_AL_VENID; 957 break; 958 case MII_PHYIDR2: 959 phy_reg = DC_AL_DEVID; 960 break; 961 case MII_ANAR: 962 phy_reg = DC_AL_ANAR; 963 break; 964 case MII_ANLPAR: 965 phy_reg = DC_AL_LPAR; 966 break; 967 case MII_ANER: 968 phy_reg = DC_AL_ANER; 969 break; 970 default: 971 printf("dc%d: phy_write: bad phy register %x\n", 972 sc->dc_unit, reg); 973 return(0); 974 break; 975 } 976 977 CSR_WRITE_4(sc, phy_reg, data); 978 return(0); 979 } 980 981 frame.mii_phyaddr = phy; 982 frame.mii_regaddr = reg; 983 frame.mii_data = data; 984 985 if (sc->dc_type == DC_TYPE_98713) { 986 phy_reg = CSR_READ_4(sc, DC_NETCFG); 987 CSR_WRITE_4(sc, DC_NETCFG, phy_reg & ~DC_NETCFG_PORTSEL); 988 } 989 dc_mii_writereg(sc, &frame); 990 if (sc->dc_type == DC_TYPE_98713) 991 CSR_WRITE_4(sc, DC_NETCFG, phy_reg); 992 993 return(0); 994 } 995 996 static void 997 dc_miibus_statchg(dev) 998 device_t dev; 999 { 1000 struct dc_softc *sc; 1001 struct mii_data *mii; 1002 struct ifmedia *ifm; 1003 1004 sc = device_get_softc(dev); 1005 if (DC_IS_ADMTEK(sc)) 1006 return; 1007 1008 mii = device_get_softc(sc->dc_miibus); 1009 ifm = &mii->mii_media; 1010 if (DC_IS_DAVICOM(sc) && 1011 IFM_SUBTYPE(ifm->ifm_media) == IFM_HPNA_1) { 1012 dc_setcfg(sc, ifm->ifm_media); 1013 sc->dc_if_media = ifm->ifm_media; 1014 } else { 1015 dc_setcfg(sc, mii->mii_media_active); 1016 sc->dc_if_media = mii->mii_media_active; 1017 } 1018 1019 return; 1020 } 1021 1022 /* 1023 * Special support for DM9102A cards with HomePNA PHYs. Note: 1024 * with the Davicom DM9102A/DM9801 eval board that I have, it seems 1025 * to be impossible to talk to the management interface of the DM9801 1026 * PHY (its MDIO pin is not connected to anything). Consequently, 1027 * the driver has to just 'know' about the additional mode and deal 1028 * with it itself. *sigh* 1029 */ 1030 static void 1031 dc_miibus_mediainit(dev) 1032 device_t dev; 1033 { 1034 struct dc_softc *sc; 1035 struct mii_data *mii; 1036 struct ifmedia *ifm; 1037 int rev; 1038 1039 rev = pci_read_config(dev, DC_PCI_CFRV, 4) & 0xFF; 1040 1041 sc = device_get_softc(dev); 1042 mii = device_get_softc(sc->dc_miibus); 1043 ifm = &mii->mii_media; 1044 1045 if (DC_IS_DAVICOM(sc) && rev >= DC_REVISION_DM9102A) 1046 ifmedia_add(ifm, IFM_ETHER|IFM_HPNA_1, 0, NULL); 1047 1048 return; 1049 } 1050 1051 #define DC_POLY 0xEDB88320 1052 #define DC_BITS_512 9 1053 #define DC_BITS_128 7 1054 #define DC_BITS_64 6 1055 1056 static u_int32_t 1057 dc_crc_le(sc, addr) 1058 struct dc_softc *sc; 1059 caddr_t addr; 1060 { 1061 u_int32_t idx, bit, data, crc; 1062 1063 /* Compute CRC for the address value. */ 1064 crc = 0xFFFFFFFF; /* initial value */ 1065 1066 for (idx = 0; idx < 6; idx++) { 1067 for (data = *addr++, bit = 0; bit < 8; bit++, data >>= 1) 1068 crc = (crc >> 1) ^ (((crc ^ data) & 1) ? DC_POLY : 0); 1069 } 1070 1071 /* 1072 * The hash table on the PNIC II and the MX98715AEC-C/D/E 1073 * chips is only 128 bits wide. 1074 */ 1075 if (sc->dc_flags & DC_128BIT_HASH) 1076 return (crc & ((1 << DC_BITS_128) - 1)); 1077 1078 /* The hash table on the MX98715BEC is only 64 bits wide. */ 1079 if (sc->dc_flags & DC_64BIT_HASH) 1080 return (crc & ((1 << DC_BITS_64) - 1)); 1081 1082 /* Xircom's hash filtering table is different (read: weird) */ 1083 /* Xircom uses the LEAST significant bits */ 1084 if (DC_IS_XIRCOM(sc)) { 1085 if ((crc & 0x180) == 0x180) 1086 return (crc & 0x0F) + (crc & 0x70)*3 + (14 << 4); 1087 else 1088 return (crc & 0x1F) + ((crc>>1) & 0xF0)*3 + (12 << 4); 1089 } 1090 1091 return (crc & ((1 << DC_BITS_512) - 1)); 1092 } 1093 1094 /* 1095 * Calculate CRC of a multicast group address, return the lower 6 bits. 1096 */ 1097 static u_int32_t 1098 dc_crc_be(addr) 1099 caddr_t addr; 1100 { 1101 u_int32_t crc, carry; 1102 int i, j; 1103 u_int8_t c; 1104 1105 /* Compute CRC for the address value. */ 1106 crc = 0xFFFFFFFF; /* initial value */ 1107 1108 for (i = 0; i < 6; i++) { 1109 c = *(addr + i); 1110 for (j = 0; j < 8; j++) { 1111 carry = ((crc & 0x80000000) ? 1 : 0) ^ (c & 0x01); 1112 crc <<= 1; 1113 c >>= 1; 1114 if (carry) 1115 crc = (crc ^ 0x04c11db6) | carry; 1116 } 1117 } 1118 1119 /* return the filter bit position */ 1120 return((crc >> 26) & 0x0000003F); 1121 } 1122 1123 /* 1124 * 21143-style RX filter setup routine. Filter programming is done by 1125 * downloading a special setup frame into the TX engine. 21143, Macronix, 1126 * PNIC, PNIC II and Davicom chips are programmed this way. 1127 * 1128 * We always program the chip using 'hash perfect' mode, i.e. one perfect 1129 * address (our node address) and a 512-bit hash filter for multicast 1130 * frames. We also sneak the broadcast address into the hash filter since 1131 * we need that too. 1132 */ 1133 static void 1134 dc_setfilt_21143(sc) 1135 struct dc_softc *sc; 1136 { 1137 struct dc_desc *sframe; 1138 u_int32_t h, *sp; 1139 struct ifmultiaddr *ifma; 1140 struct ifnet *ifp; 1141 int i; 1142 1143 ifp = &sc->arpcom.ac_if; 1144 1145 i = sc->dc_cdata.dc_tx_prod; 1146 DC_INC(sc->dc_cdata.dc_tx_prod, DC_TX_LIST_CNT); 1147 sc->dc_cdata.dc_tx_cnt++; 1148 sframe = &sc->dc_ldata->dc_tx_list[i]; 1149 sp = (u_int32_t *)&sc->dc_cdata.dc_sbuf; 1150 bzero((char *)sp, DC_SFRAME_LEN); 1151 1152 sframe->dc_data = vtophys(&sc->dc_cdata.dc_sbuf); 1153 sframe->dc_ctl = DC_SFRAME_LEN | DC_TXCTL_SETUP | DC_TXCTL_TLINK | 1154 DC_FILTER_HASHPERF | DC_TXCTL_FINT; 1155 1156 sc->dc_cdata.dc_tx_chain[i] = (struct mbuf *)&sc->dc_cdata.dc_sbuf; 1157 1158 /* If we want promiscuous mode, set the allframes bit. */ 1159 if (ifp->if_flags & IFF_PROMISC) 1160 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC); 1161 else 1162 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC); 1163 1164 if (ifp->if_flags & IFF_ALLMULTI) 1165 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI); 1166 else 1167 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI); 1168 1169 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 1170 if (ifma->ifma_addr->sa_family != AF_LINK) 1171 continue; 1172 h = dc_crc_le(sc, 1173 LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 1174 sp[h >> 4] |= 1 << (h & 0xF); 1175 } 1176 1177 if (ifp->if_flags & IFF_BROADCAST) { 1178 h = dc_crc_le(sc, (caddr_t)ifp->if_broadcastaddr); 1179 sp[h >> 4] |= 1 << (h & 0xF); 1180 } 1181 1182 /* Set our MAC address */ 1183 sp[39] = ((u_int16_t *)sc->arpcom.ac_enaddr)[0]; 1184 sp[40] = ((u_int16_t *)sc->arpcom.ac_enaddr)[1]; 1185 sp[41] = ((u_int16_t *)sc->arpcom.ac_enaddr)[2]; 1186 1187 sframe->dc_status = DC_TXSTAT_OWN; 1188 CSR_WRITE_4(sc, DC_TXSTART, 0xFFFFFFFF); 1189 1190 /* 1191 * The PNIC takes an exceedingly long time to process its 1192 * setup frame; wait 10ms after posting the setup frame 1193 * before proceeding, just so it has time to swallow its 1194 * medicine. 1195 */ 1196 DELAY(10000); 1197 1198 ifp->if_timer = 5; 1199 1200 return; 1201 } 1202 1203 static void 1204 dc_setfilt_admtek(sc) 1205 struct dc_softc *sc; 1206 { 1207 struct ifnet *ifp; 1208 int h = 0; 1209 u_int32_t hashes[2] = { 0, 0 }; 1210 struct ifmultiaddr *ifma; 1211 1212 ifp = &sc->arpcom.ac_if; 1213 1214 /* Init our MAC address */ 1215 CSR_WRITE_4(sc, DC_AL_PAR0, *(u_int32_t *)(&sc->arpcom.ac_enaddr[0])); 1216 CSR_WRITE_4(sc, DC_AL_PAR1, *(u_int32_t *)(&sc->arpcom.ac_enaddr[4])); 1217 1218 /* If we want promiscuous mode, set the allframes bit. */ 1219 if (ifp->if_flags & IFF_PROMISC) 1220 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC); 1221 else 1222 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC); 1223 1224 if (ifp->if_flags & IFF_ALLMULTI) 1225 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI); 1226 else 1227 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI); 1228 1229 /* first, zot all the existing hash bits */ 1230 CSR_WRITE_4(sc, DC_AL_MAR0, 0); 1231 CSR_WRITE_4(sc, DC_AL_MAR1, 0); 1232 1233 /* 1234 * If we're already in promisc or allmulti mode, we 1235 * don't have to bother programming the multicast filter. 1236 */ 1237 if (ifp->if_flags & (IFF_PROMISC|IFF_ALLMULTI)) 1238 return; 1239 1240 /* now program new ones */ 1241 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 1242 if (ifma->ifma_addr->sa_family != AF_LINK) 1243 continue; 1244 h = dc_crc_be(LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 1245 if (h < 32) 1246 hashes[0] |= (1 << h); 1247 else 1248 hashes[1] |= (1 << (h - 32)); 1249 } 1250 1251 CSR_WRITE_4(sc, DC_AL_MAR0, hashes[0]); 1252 CSR_WRITE_4(sc, DC_AL_MAR1, hashes[1]); 1253 1254 return; 1255 } 1256 1257 static void 1258 dc_setfilt_asix(sc) 1259 struct dc_softc *sc; 1260 { 1261 struct ifnet *ifp; 1262 int h = 0; 1263 u_int32_t hashes[2] = { 0, 0 }; 1264 struct ifmultiaddr *ifma; 1265 1266 ifp = &sc->arpcom.ac_if; 1267 1268 /* Init our MAC address */ 1269 CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_PAR0); 1270 CSR_WRITE_4(sc, DC_AX_FILTDATA, 1271 *(u_int32_t *)(&sc->arpcom.ac_enaddr[0])); 1272 CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_PAR1); 1273 CSR_WRITE_4(sc, DC_AX_FILTDATA, 1274 *(u_int32_t *)(&sc->arpcom.ac_enaddr[4])); 1275 1276 /* If we want promiscuous mode, set the allframes bit. */ 1277 if (ifp->if_flags & IFF_PROMISC) 1278 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC); 1279 else 1280 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC); 1281 1282 if (ifp->if_flags & IFF_ALLMULTI) 1283 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI); 1284 else 1285 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI); 1286 1287 /* 1288 * The ASIX chip has a special bit to enable reception 1289 * of broadcast frames. 1290 */ 1291 if (ifp->if_flags & IFF_BROADCAST) 1292 DC_SETBIT(sc, DC_NETCFG, DC_AX_NETCFG_RX_BROAD); 1293 else 1294 DC_CLRBIT(sc, DC_NETCFG, DC_AX_NETCFG_RX_BROAD); 1295 1296 /* first, zot all the existing hash bits */ 1297 CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_MAR0); 1298 CSR_WRITE_4(sc, DC_AX_FILTDATA, 0); 1299 CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_MAR1); 1300 CSR_WRITE_4(sc, DC_AX_FILTDATA, 0); 1301 1302 /* 1303 * If we're already in promisc or allmulti mode, we 1304 * don't have to bother programming the multicast filter. 1305 */ 1306 if (ifp->if_flags & (IFF_PROMISC|IFF_ALLMULTI)) 1307 return; 1308 1309 /* now program new ones */ 1310 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 1311 if (ifma->ifma_addr->sa_family != AF_LINK) 1312 continue; 1313 h = dc_crc_be(LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 1314 if (h < 32) 1315 hashes[0] |= (1 << h); 1316 else 1317 hashes[1] |= (1 << (h - 32)); 1318 } 1319 1320 CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_MAR0); 1321 CSR_WRITE_4(sc, DC_AX_FILTDATA, hashes[0]); 1322 CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_MAR1); 1323 CSR_WRITE_4(sc, DC_AX_FILTDATA, hashes[1]); 1324 1325 return; 1326 } 1327 1328 static void 1329 dc_setfilt_xircom(sc) 1330 struct dc_softc *sc; 1331 { 1332 struct dc_desc *sframe; 1333 u_int32_t h, *sp; 1334 struct ifmultiaddr *ifma; 1335 struct ifnet *ifp; 1336 int i; 1337 1338 ifp = &sc->arpcom.ac_if; 1339 DC_CLRBIT(sc, DC_NETCFG, (DC_NETCFG_TX_ON|DC_NETCFG_RX_ON)); 1340 1341 i = sc->dc_cdata.dc_tx_prod; 1342 DC_INC(sc->dc_cdata.dc_tx_prod, DC_TX_LIST_CNT); 1343 sc->dc_cdata.dc_tx_cnt++; 1344 sframe = &sc->dc_ldata->dc_tx_list[i]; 1345 sp = (u_int32_t *)&sc->dc_cdata.dc_sbuf; 1346 bzero((char *)sp, DC_SFRAME_LEN); 1347 1348 sframe->dc_data = vtophys(&sc->dc_cdata.dc_sbuf); 1349 sframe->dc_ctl = DC_SFRAME_LEN | DC_TXCTL_SETUP | DC_TXCTL_TLINK | 1350 DC_FILTER_HASHPERF | DC_TXCTL_FINT; 1351 1352 sc->dc_cdata.dc_tx_chain[i] = (struct mbuf *)&sc->dc_cdata.dc_sbuf; 1353 1354 /* If we want promiscuous mode, set the allframes bit. */ 1355 if (ifp->if_flags & IFF_PROMISC) 1356 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC); 1357 else 1358 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC); 1359 1360 if (ifp->if_flags & IFF_ALLMULTI) 1361 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI); 1362 else 1363 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI); 1364 1365 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 1366 if (ifma->ifma_addr->sa_family != AF_LINK) 1367 continue; 1368 h = dc_crc_le(sc, 1369 LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 1370 sp[h >> 4] |= 1 << (h & 0xF); 1371 } 1372 1373 if (ifp->if_flags & IFF_BROADCAST) { 1374 h = dc_crc_le(sc, (caddr_t)ifp->if_broadcastaddr); 1375 sp[h >> 4] |= 1 << (h & 0xF); 1376 } 1377 1378 /* Set our MAC address */ 1379 sp[0] = ((u_int16_t *)sc->arpcom.ac_enaddr)[0]; 1380 sp[1] = ((u_int16_t *)sc->arpcom.ac_enaddr)[1]; 1381 sp[2] = ((u_int16_t *)sc->arpcom.ac_enaddr)[2]; 1382 1383 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_TX_ON); 1384 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_ON); 1385 ifp->if_flags |= IFF_RUNNING; 1386 sframe->dc_status = DC_TXSTAT_OWN; 1387 CSR_WRITE_4(sc, DC_TXSTART, 0xFFFFFFFF); 1388 1389 /* 1390 * wait some time... 1391 */ 1392 DELAY(1000); 1393 1394 ifp->if_timer = 5; 1395 1396 return; 1397 } 1398 1399 static void 1400 dc_setfilt(sc) 1401 struct dc_softc *sc; 1402 { 1403 if (DC_IS_INTEL(sc) || DC_IS_MACRONIX(sc) || DC_IS_PNIC(sc) || 1404 DC_IS_PNICII(sc) || DC_IS_DAVICOM(sc) || DC_IS_CONEXANT(sc)) 1405 dc_setfilt_21143(sc); 1406 1407 if (DC_IS_ASIX(sc)) 1408 dc_setfilt_asix(sc); 1409 1410 if (DC_IS_ADMTEK(sc)) 1411 dc_setfilt_admtek(sc); 1412 1413 if (DC_IS_XIRCOM(sc)) 1414 dc_setfilt_xircom(sc); 1415 1416 return; 1417 } 1418 1419 /* 1420 * In order to fiddle with the 1421 * 'full-duplex' and '100Mbps' bits in the netconfig register, we 1422 * first have to put the transmit and/or receive logic in the idle state. 1423 */ 1424 static void 1425 dc_setcfg(sc, media) 1426 struct dc_softc *sc; 1427 int media; 1428 { 1429 int i, restart = 0; 1430 u_int32_t isr; 1431 1432 if (IFM_SUBTYPE(media) == IFM_NONE) 1433 return; 1434 1435 if (CSR_READ_4(sc, DC_NETCFG) & (DC_NETCFG_TX_ON|DC_NETCFG_RX_ON)) { 1436 restart = 1; 1437 DC_CLRBIT(sc, DC_NETCFG, (DC_NETCFG_TX_ON|DC_NETCFG_RX_ON)); 1438 1439 for (i = 0; i < DC_TIMEOUT; i++) { 1440 isr = CSR_READ_4(sc, DC_ISR); 1441 if (isr & DC_ISR_TX_IDLE && 1442 ((isr & DC_ISR_RX_STATE) == DC_RXSTATE_STOPPED || 1443 (isr & DC_ISR_RX_STATE) == DC_RXSTATE_WAIT)) 1444 break; 1445 DELAY(10); 1446 } 1447 1448 if (i == DC_TIMEOUT) 1449 printf("dc%d: failed to force tx and " 1450 "rx to idle state\n", sc->dc_unit); 1451 } 1452 1453 if (IFM_SUBTYPE(media) == IFM_100_TX) { 1454 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_SPEEDSEL); 1455 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_HEARTBEAT); 1456 if (sc->dc_pmode == DC_PMODE_MII) { 1457 int watchdogreg; 1458 1459 if (DC_IS_INTEL(sc)) { 1460 /* there's a write enable bit here that reads as 1 */ 1461 watchdogreg = CSR_READ_4(sc, DC_WATCHDOG); 1462 watchdogreg &= ~DC_WDOG_CTLWREN; 1463 watchdogreg |= DC_WDOG_JABBERDIS; 1464 CSR_WRITE_4(sc, DC_WATCHDOG, watchdogreg); 1465 } else { 1466 DC_SETBIT(sc, DC_WATCHDOG, DC_WDOG_JABBERDIS); 1467 } 1468 DC_CLRBIT(sc, DC_NETCFG, (DC_NETCFG_PCS| 1469 DC_NETCFG_PORTSEL|DC_NETCFG_SCRAMBLER)); 1470 if (sc->dc_type == DC_TYPE_98713) 1471 DC_SETBIT(sc, DC_NETCFG, (DC_NETCFG_PCS| 1472 DC_NETCFG_SCRAMBLER)); 1473 if (!DC_IS_DAVICOM(sc)) 1474 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL); 1475 DC_CLRBIT(sc, DC_10BTCTRL, 0xFFFF); 1476 if (DC_IS_INTEL(sc)) 1477 dc_apply_fixup(sc, IFM_AUTO); 1478 } else { 1479 if (DC_IS_PNIC(sc)) { 1480 DC_PN_GPIO_SETBIT(sc, DC_PN_GPIO_SPEEDSEL); 1481 DC_PN_GPIO_SETBIT(sc, DC_PN_GPIO_100TX_LOOP); 1482 DC_SETBIT(sc, DC_PN_NWAY, DC_PN_NWAY_SPEEDSEL); 1483 } 1484 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL); 1485 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PCS); 1486 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_SCRAMBLER); 1487 if (DC_IS_INTEL(sc)) 1488 dc_apply_fixup(sc, 1489 (media & IFM_GMASK) == IFM_FDX ? 1490 IFM_100_TX|IFM_FDX : IFM_100_TX); 1491 } 1492 } 1493 1494 if (IFM_SUBTYPE(media) == IFM_10_T) { 1495 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_SPEEDSEL); 1496 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_HEARTBEAT); 1497 if (sc->dc_pmode == DC_PMODE_MII) { 1498 int watchdogreg; 1499 1500 /* there's a write enable bit here that reads as 1 */ 1501 if (DC_IS_INTEL(sc)) { 1502 watchdogreg = CSR_READ_4(sc, DC_WATCHDOG); 1503 watchdogreg &= ~DC_WDOG_CTLWREN; 1504 watchdogreg |= DC_WDOG_JABBERDIS; 1505 CSR_WRITE_4(sc, DC_WATCHDOG, watchdogreg); 1506 } else { 1507 DC_SETBIT(sc, DC_WATCHDOG, DC_WDOG_JABBERDIS); 1508 } 1509 DC_CLRBIT(sc, DC_NETCFG, (DC_NETCFG_PCS| 1510 DC_NETCFG_PORTSEL|DC_NETCFG_SCRAMBLER)); 1511 if (sc->dc_type == DC_TYPE_98713) 1512 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PCS); 1513 if (!DC_IS_DAVICOM(sc)) 1514 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL); 1515 DC_CLRBIT(sc, DC_10BTCTRL, 0xFFFF); 1516 if (DC_IS_INTEL(sc)) 1517 dc_apply_fixup(sc, IFM_AUTO); 1518 } else { 1519 if (DC_IS_PNIC(sc)) { 1520 DC_PN_GPIO_CLRBIT(sc, DC_PN_GPIO_SPEEDSEL); 1521 DC_PN_GPIO_SETBIT(sc, DC_PN_GPIO_100TX_LOOP); 1522 DC_CLRBIT(sc, DC_PN_NWAY, DC_PN_NWAY_SPEEDSEL); 1523 } 1524 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL); 1525 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_PCS); 1526 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_SCRAMBLER); 1527 if (DC_IS_INTEL(sc)) { 1528 DC_CLRBIT(sc, DC_SIARESET, DC_SIA_RESET); 1529 DC_CLRBIT(sc, DC_10BTCTRL, 0xFFFF); 1530 if ((media & IFM_GMASK) == IFM_FDX) 1531 DC_SETBIT(sc, DC_10BTCTRL, 0x7F3D); 1532 else 1533 DC_SETBIT(sc, DC_10BTCTRL, 0x7F3F); 1534 DC_SETBIT(sc, DC_SIARESET, DC_SIA_RESET); 1535 DC_CLRBIT(sc, DC_10BTCTRL, 1536 DC_TCTL_AUTONEGENBL); 1537 dc_apply_fixup(sc, 1538 (media & IFM_GMASK) == IFM_FDX ? 1539 IFM_10_T|IFM_FDX : IFM_10_T); 1540 DELAY(20000); 1541 } 1542 } 1543 } 1544 1545 /* 1546 * If this is a Davicom DM9102A card with a DM9801 HomePNA 1547 * PHY and we want HomePNA mode, set the portsel bit to turn 1548 * on the external MII port. 1549 */ 1550 if (DC_IS_DAVICOM(sc)) { 1551 if (IFM_SUBTYPE(media) == IFM_HPNA_1) { 1552 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL); 1553 sc->dc_link = 1; 1554 } else { 1555 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL); 1556 } 1557 } 1558 1559 if ((media & IFM_GMASK) == IFM_FDX) { 1560 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_FULLDUPLEX); 1561 if (sc->dc_pmode == DC_PMODE_SYM && DC_IS_PNIC(sc)) 1562 DC_SETBIT(sc, DC_PN_NWAY, DC_PN_NWAY_DUPLEX); 1563 } else { 1564 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_FULLDUPLEX); 1565 if (sc->dc_pmode == DC_PMODE_SYM && DC_IS_PNIC(sc)) 1566 DC_CLRBIT(sc, DC_PN_NWAY, DC_PN_NWAY_DUPLEX); 1567 } 1568 1569 if (restart) 1570 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_TX_ON|DC_NETCFG_RX_ON); 1571 1572 return; 1573 } 1574 1575 static void 1576 dc_reset(sc) 1577 struct dc_softc *sc; 1578 { 1579 register int i; 1580 1581 DC_SETBIT(sc, DC_BUSCTL, DC_BUSCTL_RESET); 1582 1583 for (i = 0; i < DC_TIMEOUT; i++) { 1584 DELAY(10); 1585 if (!(CSR_READ_4(sc, DC_BUSCTL) & DC_BUSCTL_RESET)) 1586 break; 1587 } 1588 1589 if (DC_IS_ASIX(sc) || DC_IS_ADMTEK(sc) || DC_IS_CONEXANT(sc) || 1590 DC_IS_XIRCOM(sc) || DC_IS_INTEL(sc)) { 1591 DELAY(10000); 1592 DC_CLRBIT(sc, DC_BUSCTL, DC_BUSCTL_RESET); 1593 i = 0; 1594 } 1595 1596 if (i == DC_TIMEOUT) 1597 printf("dc%d: reset never completed!\n", sc->dc_unit); 1598 1599 /* Wait a little while for the chip to get its brains in order. */ 1600 DELAY(1000); 1601 1602 CSR_WRITE_4(sc, DC_IMR, 0x00000000); 1603 CSR_WRITE_4(sc, DC_BUSCTL, 0x00000000); 1604 CSR_WRITE_4(sc, DC_NETCFG, 0x00000000); 1605 1606 /* 1607 * Bring the SIA out of reset. In some cases, it looks 1608 * like failing to unreset the SIA soon enough gets it 1609 * into a state where it will never come out of reset 1610 * until we reset the whole chip again. 1611 */ 1612 if (DC_IS_INTEL(sc)) { 1613 DC_SETBIT(sc, DC_SIARESET, DC_SIA_RESET); 1614 CSR_WRITE_4(sc, DC_10BTCTRL, 0); 1615 CSR_WRITE_4(sc, DC_WATCHDOG, 0); 1616 } 1617 1618 return; 1619 } 1620 1621 static struct dc_type * 1622 dc_devtype(dev) 1623 device_t dev; 1624 { 1625 struct dc_type *t; 1626 u_int32_t rev; 1627 1628 t = dc_devs; 1629 1630 while(t->dc_name != NULL) { 1631 if ((pci_get_vendor(dev) == t->dc_vid) && 1632 (pci_get_device(dev) == t->dc_did)) { 1633 /* Check the PCI revision */ 1634 rev = pci_read_config(dev, DC_PCI_CFRV, 4) & 0xFF; 1635 if (t->dc_did == DC_DEVICEID_98713 && 1636 rev >= DC_REVISION_98713A) 1637 t++; 1638 if (t->dc_did == DC_DEVICEID_98713_CP && 1639 rev >= DC_REVISION_98713A) 1640 t++; 1641 if (t->dc_did == DC_DEVICEID_987x5 && 1642 rev >= DC_REVISION_98715AEC_C) 1643 t++; 1644 if (t->dc_did == DC_DEVICEID_987x5 && 1645 rev >= DC_REVISION_98725) 1646 t++; 1647 if (t->dc_did == DC_DEVICEID_AX88140A && 1648 rev >= DC_REVISION_88141) 1649 t++; 1650 if (t->dc_did == DC_DEVICEID_82C168 && 1651 rev >= DC_REVISION_82C169) 1652 t++; 1653 if (t->dc_did == DC_DEVICEID_DM9102 && 1654 rev >= DC_REVISION_DM9102A) 1655 t++; 1656 return(t); 1657 } 1658 t++; 1659 } 1660 1661 return(NULL); 1662 } 1663 1664 /* 1665 * Probe for a 21143 or clone chip. Check the PCI vendor and device 1666 * IDs against our list and return a device name if we find a match. 1667 * We do a little bit of extra work to identify the exact type of 1668 * chip. The MX98713 and MX98713A have the same PCI vendor/device ID, 1669 * but different revision IDs. The same is true for 98715/98715A 1670 * chips and the 98725, as well as the ASIX and ADMtek chips. In some 1671 * cases, the exact chip revision affects driver behavior. 1672 */ 1673 static int 1674 dc_probe(dev) 1675 device_t dev; 1676 { 1677 struct dc_type *t; 1678 1679 t = dc_devtype(dev); 1680 1681 if (t != NULL) { 1682 device_set_desc(dev, t->dc_name); 1683 return(0); 1684 } 1685 1686 return(ENXIO); 1687 } 1688 1689 static void 1690 dc_acpi(dev) 1691 device_t dev; 1692 { 1693 int unit; 1694 1695 unit = device_get_unit(dev); 1696 1697 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) { 1698 u_int32_t iobase, membase, irq; 1699 1700 /* Save important PCI config data. */ 1701 iobase = pci_read_config(dev, DC_PCI_CFBIO, 4); 1702 membase = pci_read_config(dev, DC_PCI_CFBMA, 4); 1703 irq = pci_read_config(dev, DC_PCI_CFIT, 4); 1704 1705 /* Reset the power state. */ 1706 printf("dc%d: chip is in D%d power mode " 1707 "-- setting to D0\n", unit, 1708 pci_get_powerstate(dev)); 1709 pci_set_powerstate(dev, PCI_POWERSTATE_D0); 1710 1711 /* Restore PCI config data. */ 1712 pci_write_config(dev, DC_PCI_CFBIO, iobase, 4); 1713 pci_write_config(dev, DC_PCI_CFBMA, membase, 4); 1714 pci_write_config(dev, DC_PCI_CFIT, irq, 4); 1715 } 1716 1717 return; 1718 } 1719 1720 static void 1721 dc_apply_fixup(sc, media) 1722 struct dc_softc *sc; 1723 int media; 1724 { 1725 struct dc_mediainfo *m; 1726 u_int8_t *p; 1727 int i; 1728 u_int32_t reg; 1729 1730 m = sc->dc_mi; 1731 1732 while (m != NULL) { 1733 if (m->dc_media == media) 1734 break; 1735 m = m->dc_next; 1736 } 1737 1738 if (m == NULL) 1739 return; 1740 1741 for (i = 0, p = m->dc_reset_ptr; i < m->dc_reset_len; i++, p += 2) { 1742 reg = (p[0] | (p[1] << 8)) << 16; 1743 CSR_WRITE_4(sc, DC_WATCHDOG, reg); 1744 } 1745 1746 for (i = 0, p = m->dc_gp_ptr; i < m->dc_gp_len; i++, p += 2) { 1747 reg = (p[0] | (p[1] << 8)) << 16; 1748 CSR_WRITE_4(sc, DC_WATCHDOG, reg); 1749 } 1750 1751 return; 1752 } 1753 1754 static void 1755 dc_decode_leaf_sia(sc, l) 1756 struct dc_softc *sc; 1757 struct dc_eblock_sia *l; 1758 { 1759 struct dc_mediainfo *m; 1760 1761 m = malloc(sizeof(struct dc_mediainfo), M_DEVBUF, M_NOWAIT); 1762 bzero(m, sizeof(struct dc_mediainfo)); 1763 if (l->dc_sia_code == DC_SIA_CODE_10BT) 1764 m->dc_media = IFM_10_T; 1765 1766 if (l->dc_sia_code == DC_SIA_CODE_10BT_FDX) 1767 m->dc_media = IFM_10_T|IFM_FDX; 1768 1769 if (l->dc_sia_code == DC_SIA_CODE_10B2) 1770 m->dc_media = IFM_10_2; 1771 1772 if (l->dc_sia_code == DC_SIA_CODE_10B5) 1773 m->dc_media = IFM_10_5; 1774 1775 m->dc_gp_len = 2; 1776 m->dc_gp_ptr = (u_int8_t *)&l->dc_sia_gpio_ctl; 1777 1778 m->dc_next = sc->dc_mi; 1779 sc->dc_mi = m; 1780 1781 sc->dc_pmode = DC_PMODE_SIA; 1782 1783 return; 1784 } 1785 1786 static void 1787 dc_decode_leaf_sym(sc, l) 1788 struct dc_softc *sc; 1789 struct dc_eblock_sym *l; 1790 { 1791 struct dc_mediainfo *m; 1792 1793 m = malloc(sizeof(struct dc_mediainfo), M_DEVBUF, M_NOWAIT); 1794 bzero(m, sizeof(struct dc_mediainfo)); 1795 if (l->dc_sym_code == DC_SYM_CODE_100BT) 1796 m->dc_media = IFM_100_TX; 1797 1798 if (l->dc_sym_code == DC_SYM_CODE_100BT_FDX) 1799 m->dc_media = IFM_100_TX|IFM_FDX; 1800 1801 m->dc_gp_len = 2; 1802 m->dc_gp_ptr = (u_int8_t *)&l->dc_sym_gpio_ctl; 1803 1804 m->dc_next = sc->dc_mi; 1805 sc->dc_mi = m; 1806 1807 sc->dc_pmode = DC_PMODE_SYM; 1808 1809 return; 1810 } 1811 1812 static void 1813 dc_decode_leaf_mii(sc, l) 1814 struct dc_softc *sc; 1815 struct dc_eblock_mii *l; 1816 { 1817 u_int8_t *p; 1818 struct dc_mediainfo *m; 1819 1820 m = malloc(sizeof(struct dc_mediainfo), M_DEVBUF, M_NOWAIT); 1821 bzero(m, sizeof(struct dc_mediainfo)); 1822 /* We abuse IFM_AUTO to represent MII. */ 1823 m->dc_media = IFM_AUTO; 1824 m->dc_gp_len = l->dc_gpr_len; 1825 1826 p = (u_int8_t *)l; 1827 p += sizeof(struct dc_eblock_mii); 1828 m->dc_gp_ptr = p; 1829 p += 2 * l->dc_gpr_len; 1830 m->dc_reset_len = *p; 1831 p++; 1832 m->dc_reset_ptr = p; 1833 1834 m->dc_next = sc->dc_mi; 1835 sc->dc_mi = m; 1836 1837 return; 1838 } 1839 1840 static void 1841 dc_read_srom(sc, bits) 1842 struct dc_softc *sc; 1843 int bits; 1844 { 1845 int size; 1846 1847 size = 2 << bits; 1848 sc->dc_srom = malloc(size, M_DEVBUF, M_NOWAIT); 1849 dc_read_eeprom(sc, (caddr_t)sc->dc_srom, 0, (size / 2), 0); 1850 } 1851 1852 static void 1853 dc_parse_21143_srom(sc) 1854 struct dc_softc *sc; 1855 { 1856 struct dc_leaf_hdr *lhdr; 1857 struct dc_eblock_hdr *hdr; 1858 int i, loff; 1859 char *ptr; 1860 1861 loff = sc->dc_srom[27]; 1862 lhdr = (struct dc_leaf_hdr *)&(sc->dc_srom[loff]); 1863 1864 ptr = (char *)lhdr; 1865 ptr += sizeof(struct dc_leaf_hdr) - 1; 1866 for (i = 0; i < lhdr->dc_mcnt; i++) { 1867 hdr = (struct dc_eblock_hdr *)ptr; 1868 switch(hdr->dc_type) { 1869 case DC_EBLOCK_MII: 1870 dc_decode_leaf_mii(sc, (struct dc_eblock_mii *)hdr); 1871 break; 1872 case DC_EBLOCK_SIA: 1873 dc_decode_leaf_sia(sc, (struct dc_eblock_sia *)hdr); 1874 break; 1875 case DC_EBLOCK_SYM: 1876 dc_decode_leaf_sym(sc, (struct dc_eblock_sym *)hdr); 1877 break; 1878 default: 1879 /* Don't care. Yet. */ 1880 break; 1881 } 1882 ptr += (hdr->dc_len & 0x7F); 1883 ptr++; 1884 } 1885 1886 return; 1887 } 1888 1889 /* 1890 * Attach the interface. Allocate softc structures, do ifmedia 1891 * setup and ethernet/BPF attach. 1892 */ 1893 static int 1894 dc_attach(dev) 1895 device_t dev; 1896 { 1897 int tmp = 0; 1898 u_char eaddr[ETHER_ADDR_LEN]; 1899 u_int32_t command; 1900 struct dc_softc *sc; 1901 struct ifnet *ifp; 1902 u_int32_t revision; 1903 int unit, error = 0, rid, mac_offset; 1904 u_int8_t *mac; 1905 1906 sc = device_get_softc(dev); 1907 unit = device_get_unit(dev); 1908 1909 mtx_init(&sc->dc_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 1910 MTX_DEF | MTX_RECURSE); 1911 1912 /* 1913 * Handle power management nonsense. 1914 */ 1915 dc_acpi(dev); 1916 1917 /* 1918 * Map control/status registers. 1919 */ 1920 pci_enable_busmaster(dev); 1921 1922 rid = DC_RID; 1923 sc->dc_res = bus_alloc_resource(dev, DC_RES, &rid, 1924 0, ~0, 1, RF_ACTIVE); 1925 1926 if (sc->dc_res == NULL) { 1927 printf("dc%d: couldn't map ports/memory\n", unit); 1928 error = ENXIO; 1929 goto fail; 1930 } 1931 1932 sc->dc_btag = rman_get_bustag(sc->dc_res); 1933 sc->dc_bhandle = rman_get_bushandle(sc->dc_res); 1934 1935 /* Allocate interrupt */ 1936 rid = 0; 1937 sc->dc_irq = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, 0, ~0, 1, 1938 RF_SHAREABLE | RF_ACTIVE); 1939 1940 if (sc->dc_irq == NULL) { 1941 printf("dc%d: couldn't map interrupt\n", unit); 1942 error = ENXIO; 1943 goto fail; 1944 } 1945 1946 /* Need this info to decide on a chip type. */ 1947 sc->dc_info = dc_devtype(dev); 1948 revision = pci_read_config(dev, DC_PCI_CFRV, 4) & 0x000000FF; 1949 1950 /* Get the eeprom width, but PNIC and XIRCOM have diff eeprom */ 1951 if (sc->dc_info->dc_did != DC_DEVICEID_82C168 && 1952 sc->dc_info->dc_did != DC_DEVICEID_X3201) 1953 dc_eeprom_width(sc); 1954 1955 switch(sc->dc_info->dc_did) { 1956 case DC_DEVICEID_21143: 1957 sc->dc_type = DC_TYPE_21143; 1958 sc->dc_flags |= DC_TX_POLL|DC_TX_USE_TX_INTR; 1959 sc->dc_flags |= DC_REDUCED_MII_POLL; 1960 /* Save EEPROM contents so we can parse them later. */ 1961 dc_read_srom(sc, sc->dc_romwidth); 1962 break; 1963 case DC_DEVICEID_DM9009: 1964 case DC_DEVICEID_DM9100: 1965 case DC_DEVICEID_DM9102: 1966 sc->dc_type = DC_TYPE_DM9102; 1967 sc->dc_flags |= DC_TX_COALESCE|DC_TX_INTR_ALWAYS; 1968 sc->dc_flags |= DC_REDUCED_MII_POLL|DC_TX_STORENFWD; 1969 sc->dc_pmode = DC_PMODE_MII; 1970 /* Increase the latency timer value. */ 1971 command = pci_read_config(dev, DC_PCI_CFLT, 4); 1972 command &= 0xFFFF00FF; 1973 command |= 0x00008000; 1974 pci_write_config(dev, DC_PCI_CFLT, command, 4); 1975 break; 1976 case DC_DEVICEID_AL981: 1977 sc->dc_type = DC_TYPE_AL981; 1978 sc->dc_flags |= DC_TX_USE_TX_INTR; 1979 sc->dc_flags |= DC_TX_ADMTEK_WAR; 1980 sc->dc_pmode = DC_PMODE_MII; 1981 dc_read_srom(sc, sc->dc_romwidth); 1982 break; 1983 case DC_DEVICEID_AN985: 1984 case DC_DEVICEID_FE2500: 1985 case DC_DEVICEID_EN2242: 1986 case DC_DEVICEID_HAWKING_PN672TX: 1987 sc->dc_type = DC_TYPE_AN985; 1988 sc->dc_flags |= DC_TX_USE_TX_INTR; 1989 sc->dc_flags |= DC_TX_ADMTEK_WAR; 1990 sc->dc_pmode = DC_PMODE_MII; 1991 dc_read_srom(sc, sc->dc_romwidth); 1992 break; 1993 case DC_DEVICEID_98713: 1994 case DC_DEVICEID_98713_CP: 1995 if (revision < DC_REVISION_98713A) { 1996 sc->dc_type = DC_TYPE_98713; 1997 } 1998 if (revision >= DC_REVISION_98713A) { 1999 sc->dc_type = DC_TYPE_98713A; 2000 sc->dc_flags |= DC_21143_NWAY; 2001 } 2002 sc->dc_flags |= DC_REDUCED_MII_POLL; 2003 sc->dc_flags |= DC_TX_POLL|DC_TX_USE_TX_INTR; 2004 break; 2005 case DC_DEVICEID_987x5: 2006 case DC_DEVICEID_EN1217: 2007 /* 2008 * Macronix MX98715AEC-C/D/E parts have only a 2009 * 128-bit hash table. We need to deal with these 2010 * in the same manner as the PNIC II so that we 2011 * get the right number of bits out of the 2012 * CRC routine. 2013 */ 2014 if (revision >= DC_REVISION_98715AEC_C && 2015 revision < DC_REVISION_98725) 2016 sc->dc_flags |= DC_128BIT_HASH; 2017 sc->dc_type = DC_TYPE_987x5; 2018 sc->dc_flags |= DC_TX_POLL|DC_TX_USE_TX_INTR; 2019 sc->dc_flags |= DC_REDUCED_MII_POLL|DC_21143_NWAY; 2020 break; 2021 case DC_DEVICEID_98727: 2022 sc->dc_type = DC_TYPE_987x5; 2023 sc->dc_flags |= DC_TX_POLL|DC_TX_USE_TX_INTR; 2024 sc->dc_flags |= DC_REDUCED_MII_POLL|DC_21143_NWAY; 2025 break; 2026 case DC_DEVICEID_82C115: 2027 sc->dc_type = DC_TYPE_PNICII; 2028 sc->dc_flags |= DC_TX_POLL|DC_TX_USE_TX_INTR|DC_128BIT_HASH; 2029 sc->dc_flags |= DC_REDUCED_MII_POLL|DC_21143_NWAY; 2030 break; 2031 case DC_DEVICEID_82C168: 2032 sc->dc_type = DC_TYPE_PNIC; 2033 sc->dc_flags |= DC_TX_STORENFWD|DC_TX_INTR_ALWAYS; 2034 sc->dc_flags |= DC_PNIC_RX_BUG_WAR; 2035 sc->dc_pnic_rx_buf = malloc(DC_RXLEN * 5, M_DEVBUF, M_NOWAIT); 2036 if (revision < DC_REVISION_82C169) 2037 sc->dc_pmode = DC_PMODE_SYM; 2038 break; 2039 case DC_DEVICEID_AX88140A: 2040 sc->dc_type = DC_TYPE_ASIX; 2041 sc->dc_flags |= DC_TX_USE_TX_INTR|DC_TX_INTR_FIRSTFRAG; 2042 sc->dc_flags |= DC_REDUCED_MII_POLL; 2043 sc->dc_pmode = DC_PMODE_MII; 2044 break; 2045 case DC_DEVICEID_X3201: 2046 sc->dc_type = DC_TYPE_XIRCOM; 2047 sc->dc_flags |= DC_TX_INTR_ALWAYS | DC_TX_COALESCE | 2048 DC_TX_ALIGN; 2049 /* 2050 * We don't actually need to coalesce, but we're doing 2051 * it to obtain a double word aligned buffer. 2052 * The DC_TX_COALESCE flag is required. 2053 */ 2054 sc->dc_pmode = DC_PMODE_MII; 2055 break; 2056 case DC_DEVICEID_RS7112: 2057 sc->dc_type = DC_TYPE_CONEXANT; 2058 sc->dc_flags |= DC_TX_INTR_ALWAYS; 2059 sc->dc_flags |= DC_REDUCED_MII_POLL; 2060 sc->dc_pmode = DC_PMODE_MII; 2061 dc_read_srom(sc, sc->dc_romwidth); 2062 break; 2063 default: 2064 printf("dc%d: unknown device: %x\n", sc->dc_unit, 2065 sc->dc_info->dc_did); 2066 break; 2067 } 2068 2069 /* Save the cache line size. */ 2070 if (DC_IS_DAVICOM(sc)) 2071 sc->dc_cachesize = 0; 2072 else 2073 sc->dc_cachesize = pci_read_config(dev, 2074 DC_PCI_CFLT, 4) & 0xFF; 2075 2076 /* Reset the adapter. */ 2077 dc_reset(sc); 2078 2079 /* Take 21143 out of snooze mode */ 2080 if (DC_IS_INTEL(sc) || DC_IS_XIRCOM(sc)) { 2081 command = pci_read_config(dev, DC_PCI_CFDD, 4); 2082 command &= ~(DC_CFDD_SNOOZE_MODE|DC_CFDD_SLEEP_MODE); 2083 pci_write_config(dev, DC_PCI_CFDD, command, 4); 2084 } 2085 2086 /* 2087 * Try to learn something about the supported media. 2088 * We know that ASIX and ADMtek and Davicom devices 2089 * will *always* be using MII media, so that's a no-brainer. 2090 * The tricky ones are the Macronix/PNIC II and the 2091 * Intel 21143. 2092 */ 2093 if (DC_IS_INTEL(sc)) 2094 dc_parse_21143_srom(sc); 2095 else if (DC_IS_MACRONIX(sc) || DC_IS_PNICII(sc)) { 2096 if (sc->dc_type == DC_TYPE_98713) 2097 sc->dc_pmode = DC_PMODE_MII; 2098 else 2099 sc->dc_pmode = DC_PMODE_SYM; 2100 } else if (!sc->dc_pmode) 2101 sc->dc_pmode = DC_PMODE_MII; 2102 2103 /* 2104 * Get station address from the EEPROM. 2105 */ 2106 switch(sc->dc_type) { 2107 case DC_TYPE_98713: 2108 case DC_TYPE_98713A: 2109 case DC_TYPE_987x5: 2110 case DC_TYPE_PNICII: 2111 dc_read_eeprom(sc, (caddr_t)&mac_offset, 2112 (DC_EE_NODEADDR_OFFSET / 2), 1, 0); 2113 dc_read_eeprom(sc, (caddr_t)&eaddr, (mac_offset / 2), 3, 0); 2114 break; 2115 case DC_TYPE_PNIC: 2116 dc_read_eeprom(sc, (caddr_t)&eaddr, 0, 3, 1); 2117 break; 2118 case DC_TYPE_DM9102: 2119 case DC_TYPE_21143: 2120 case DC_TYPE_ASIX: 2121 dc_read_eeprom(sc, (caddr_t)&eaddr, DC_EE_NODEADDR, 3, 0); 2122 break; 2123 case DC_TYPE_AL981: 2124 case DC_TYPE_AN985: 2125 bcopy(&sc->dc_srom[DC_AL_EE_NODEADDR], (caddr_t)&eaddr, 2126 ETHER_ADDR_LEN); 2127 dc_read_eeprom(sc, (caddr_t)&eaddr, DC_AL_EE_NODEADDR, 3, 0); 2128 break; 2129 case DC_TYPE_CONEXANT: 2130 bcopy(sc->dc_srom + DC_CONEXANT_EE_NODEADDR, &eaddr, 6); 2131 break; 2132 case DC_TYPE_XIRCOM: 2133 /* The MAC comes from the CIS */ 2134 mac = pci_get_ether(dev); 2135 if (!mac) { 2136 device_printf(dev, "No station address in CIS!\n"); 2137 error = ENXIO; 2138 goto fail; 2139 } 2140 bcopy(mac, eaddr, ETHER_ADDR_LEN); 2141 break; 2142 default: 2143 dc_read_eeprom(sc, (caddr_t)&eaddr, DC_EE_NODEADDR, 3, 0); 2144 break; 2145 } 2146 2147 /* 2148 * A 21143 or clone chip was detected. Inform the world. 2149 */ 2150 printf("dc%d: Ethernet address: %6D\n", unit, eaddr, ":"); 2151 2152 sc->dc_unit = unit; 2153 bcopy(eaddr, (char *)&sc->arpcom.ac_enaddr, ETHER_ADDR_LEN); 2154 2155 sc->dc_ldata = contigmalloc(sizeof(struct dc_list_data), M_DEVBUF, 2156 M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0); 2157 2158 if (sc->dc_ldata == NULL) { 2159 printf("dc%d: no memory for list buffers!\n", unit); 2160 error = ENXIO; 2161 goto fail; 2162 } 2163 2164 bzero(sc->dc_ldata, sizeof(struct dc_list_data)); 2165 2166 ifp = &sc->arpcom.ac_if; 2167 ifp->if_softc = sc; 2168 ifp->if_unit = unit; 2169 ifp->if_name = "dc"; 2170 /* XXX: bleah, MTU gets overwritten in ether_ifattach() */ 2171 ifp->if_mtu = ETHERMTU; 2172 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 2173 ifp->if_ioctl = dc_ioctl; 2174 ifp->if_output = ether_output; 2175 ifp->if_start = dc_start; 2176 ifp->if_watchdog = dc_watchdog; 2177 ifp->if_init = dc_init; 2178 ifp->if_baudrate = 10000000; 2179 ifp->if_snd.ifq_maxlen = DC_TX_LIST_CNT - 1; 2180 2181 /* 2182 * Do MII setup. If this is a 21143, check for a PHY on the 2183 * MII bus after applying any necessary fixups to twiddle the 2184 * GPIO bits. If we don't end up finding a PHY, restore the 2185 * old selection (SIA only or SIA/SYM) and attach the dcphy 2186 * driver instead. 2187 */ 2188 if (DC_IS_INTEL(sc)) { 2189 dc_apply_fixup(sc, IFM_AUTO); 2190 tmp = sc->dc_pmode; 2191 sc->dc_pmode = DC_PMODE_MII; 2192 } 2193 2194 error = mii_phy_probe(dev, &sc->dc_miibus, 2195 dc_ifmedia_upd, dc_ifmedia_sts); 2196 2197 if (error && DC_IS_INTEL(sc)) { 2198 sc->dc_pmode = tmp; 2199 if (sc->dc_pmode != DC_PMODE_SIA) 2200 sc->dc_pmode = DC_PMODE_SYM; 2201 sc->dc_flags |= DC_21143_NWAY; 2202 mii_phy_probe(dev, &sc->dc_miibus, 2203 dc_ifmedia_upd, dc_ifmedia_sts); 2204 /* 2205 * For non-MII cards, we need to have the 21143 2206 * drive the LEDs. Except there are some systems 2207 * like the NEC VersaPro NoteBook PC which have no 2208 * LEDs, and twiddling these bits has adverse effects 2209 * on them. (I.e. you suddenly can't get a link.) 2210 */ 2211 if (pci_read_config(dev, DC_PCI_CSID, 4) != 0x80281033) 2212 sc->dc_flags |= DC_TULIP_LEDS; 2213 error = 0; 2214 } 2215 2216 if (error) { 2217 printf("dc%d: MII without any PHY!\n", sc->dc_unit); 2218 goto fail; 2219 } 2220 2221 if (DC_IS_XIRCOM(sc)) { 2222 /* 2223 * setup General Purpose Port mode and data so the tulip 2224 * can talk to the MII. 2225 */ 2226 CSR_WRITE_4(sc, DC_SIAGP, DC_SIAGP_WRITE_EN | DC_SIAGP_INT1_EN | 2227 DC_SIAGP_MD_GP2_OUTPUT | DC_SIAGP_MD_GP0_OUTPUT); 2228 DELAY(10); 2229 CSR_WRITE_4(sc, DC_SIAGP, DC_SIAGP_INT1_EN | 2230 DC_SIAGP_MD_GP2_OUTPUT | DC_SIAGP_MD_GP0_OUTPUT); 2231 DELAY(10); 2232 } 2233 2234 if (DC_IS_ADMTEK(sc)) { 2235 /* 2236 * Set automatic TX underrun recovery for the ADMtek chips 2237 */ 2238 DC_SETBIT(sc, DC_AL_CR, DC_AL_CR_ATUR); 2239 } 2240 2241 /* 2242 * Tell the upper layer(s) we support long frames. 2243 */ 2244 ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header); 2245 ifp->if_capabilities |= IFCAP_VLAN_MTU; 2246 2247 callout_init(&sc->dc_stat_ch, IS_MPSAFE); 2248 2249 #ifdef SRM_MEDIA 2250 sc->dc_srm_media = 0; 2251 2252 /* Remember the SRM console media setting */ 2253 if (DC_IS_INTEL(sc)) { 2254 command = pci_read_config(dev, DC_PCI_CFDD, 4); 2255 command &= ~(DC_CFDD_SNOOZE_MODE|DC_CFDD_SLEEP_MODE); 2256 switch ((command >> 8) & 0xff) { 2257 case 3: 2258 sc->dc_srm_media = IFM_10_T; 2259 break; 2260 case 4: 2261 sc->dc_srm_media = IFM_10_T | IFM_FDX; 2262 break; 2263 case 5: 2264 sc->dc_srm_media = IFM_100_TX; 2265 break; 2266 case 6: 2267 sc->dc_srm_media = IFM_100_TX | IFM_FDX; 2268 break; 2269 } 2270 if (sc->dc_srm_media) 2271 sc->dc_srm_media |= IFM_ACTIVE | IFM_ETHER; 2272 } 2273 #endif 2274 2275 /* 2276 * Call MI attach routine. 2277 */ 2278 ether_ifattach(ifp, eaddr); 2279 2280 /* Hook interrupt last to avoid having to lock softc */ 2281 error = bus_setup_intr(dev, sc->dc_irq, INTR_TYPE_NET | 2282 (IS_MPSAFE ? INTR_MPSAFE : 0), 2283 dc_intr, sc, &sc->dc_intrhand); 2284 2285 if (error) { 2286 printf("dc%d: couldn't set up irq\n", unit); 2287 ether_ifdetach(ifp); 2288 goto fail; 2289 } 2290 2291 fail: 2292 if (error) 2293 dc_detach(dev); 2294 return (error); 2295 } 2296 2297 /* 2298 * Shutdown hardware and free up resources. This can be called any 2299 * time after the mutex has been initialized. It is called in both 2300 * the error case in attach and the normal detach case so it needs 2301 * to be careful about only freeing resources that have actually been 2302 * allocated. 2303 */ 2304 static int 2305 dc_detach(dev) 2306 device_t dev; 2307 { 2308 struct dc_softc *sc; 2309 struct ifnet *ifp; 2310 struct dc_mediainfo *m; 2311 2312 sc = device_get_softc(dev); 2313 KASSERT(mtx_initialized(&sc->dc_mtx), ("dc mutex not initialized")); 2314 DC_LOCK(sc); 2315 2316 ifp = &sc->arpcom.ac_if; 2317 2318 /* These should only be active if attach succeeded */ 2319 if (device_is_attached(dev)) { 2320 dc_stop(sc); 2321 ether_ifdetach(ifp); 2322 } 2323 if (sc->dc_miibus) 2324 device_delete_child(dev, sc->dc_miibus); 2325 bus_generic_detach(dev); 2326 2327 if (sc->dc_intrhand) 2328 bus_teardown_intr(dev, sc->dc_irq, sc->dc_intrhand); 2329 if (sc->dc_irq) 2330 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->dc_irq); 2331 if (sc->dc_res) 2332 bus_release_resource(dev, DC_RES, DC_RID, sc->dc_res); 2333 2334 if (sc->dc_ldata) 2335 contigfree(sc->dc_ldata, sizeof(struct dc_list_data), M_DEVBUF); 2336 free(sc->dc_pnic_rx_buf, M_DEVBUF); 2337 2338 while(sc->dc_mi != NULL) { 2339 m = sc->dc_mi->dc_next; 2340 free(sc->dc_mi, M_DEVBUF); 2341 sc->dc_mi = m; 2342 } 2343 free(sc->dc_srom, M_DEVBUF); 2344 2345 DC_UNLOCK(sc); 2346 mtx_destroy(&sc->dc_mtx); 2347 2348 return(0); 2349 } 2350 2351 /* 2352 * Initialize the transmit descriptors. 2353 */ 2354 static int 2355 dc_list_tx_init(sc) 2356 struct dc_softc *sc; 2357 { 2358 struct dc_chain_data *cd; 2359 struct dc_list_data *ld; 2360 int i, nexti; 2361 2362 cd = &sc->dc_cdata; 2363 ld = sc->dc_ldata; 2364 for (i = 0; i < DC_TX_LIST_CNT; i++) { 2365 nexti = (i == (DC_TX_LIST_CNT - 1)) ? 0 : i+1; 2366 ld->dc_tx_list[i].dc_next = vtophys(&ld->dc_tx_list[nexti]); 2367 cd->dc_tx_chain[i] = NULL; 2368 ld->dc_tx_list[i].dc_data = 0; 2369 ld->dc_tx_list[i].dc_ctl = 0; 2370 } 2371 2372 cd->dc_tx_prod = cd->dc_tx_cons = cd->dc_tx_cnt = 0; 2373 2374 return(0); 2375 } 2376 2377 2378 /* 2379 * Initialize the RX descriptors and allocate mbufs for them. Note that 2380 * we arrange the descriptors in a closed ring, so that the last descriptor 2381 * points back to the first. 2382 */ 2383 static int 2384 dc_list_rx_init(sc) 2385 struct dc_softc *sc; 2386 { 2387 struct dc_chain_data *cd; 2388 struct dc_list_data *ld; 2389 int i, nexti; 2390 2391 cd = &sc->dc_cdata; 2392 ld = sc->dc_ldata; 2393 2394 for (i = 0; i < DC_RX_LIST_CNT; i++) { 2395 if (dc_newbuf(sc, i, NULL) == ENOBUFS) 2396 return(ENOBUFS); 2397 nexti = (i == (DC_RX_LIST_CNT - 1)) ? 0 : i+1; 2398 ld->dc_rx_list[i].dc_next = vtophys(&ld->dc_rx_list[nexti]); 2399 } 2400 2401 cd->dc_rx_prod = 0; 2402 2403 return(0); 2404 } 2405 2406 /* 2407 * Initialize an RX descriptor and attach an MBUF cluster. 2408 */ 2409 static int 2410 dc_newbuf(sc, i, m) 2411 struct dc_softc *sc; 2412 int i; 2413 struct mbuf *m; 2414 { 2415 struct mbuf *m_new = NULL; 2416 struct dc_desc *c; 2417 2418 c = &sc->dc_ldata->dc_rx_list[i]; 2419 2420 if (m == NULL) { 2421 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 2422 if (m_new == NULL) 2423 return(ENOBUFS); 2424 2425 MCLGET(m_new, M_DONTWAIT); 2426 if (!(m_new->m_flags & M_EXT)) { 2427 m_freem(m_new); 2428 return(ENOBUFS); 2429 } 2430 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 2431 } else { 2432 m_new = m; 2433 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 2434 m_new->m_data = m_new->m_ext.ext_buf; 2435 } 2436 2437 m_adj(m_new, sizeof(u_int64_t)); 2438 2439 /* 2440 * If this is a PNIC chip, zero the buffer. This is part 2441 * of the workaround for the receive bug in the 82c168 and 2442 * 82c169 chips. 2443 */ 2444 if (sc->dc_flags & DC_PNIC_RX_BUG_WAR) 2445 bzero((char *)mtod(m_new, char *), m_new->m_len); 2446 2447 sc->dc_cdata.dc_rx_chain[i] = m_new; 2448 c->dc_data = vtophys(mtod(m_new, caddr_t)); 2449 c->dc_ctl = DC_RXCTL_RLINK | DC_RXLEN; 2450 c->dc_status = DC_RXSTAT_OWN; 2451 2452 return(0); 2453 } 2454 2455 /* 2456 * Grrrrr. 2457 * The PNIC chip has a terrible bug in it that manifests itself during 2458 * periods of heavy activity. The exact mode of failure if difficult to 2459 * pinpoint: sometimes it only happens in promiscuous mode, sometimes it 2460 * will happen on slow machines. The bug is that sometimes instead of 2461 * uploading one complete frame during reception, it uploads what looks 2462 * like the entire contents of its FIFO memory. The frame we want is at 2463 * the end of the whole mess, but we never know exactly how much data has 2464 * been uploaded, so salvaging the frame is hard. 2465 * 2466 * There is only one way to do it reliably, and it's disgusting. 2467 * Here's what we know: 2468 * 2469 * - We know there will always be somewhere between one and three extra 2470 * descriptors uploaded. 2471 * 2472 * - We know the desired received frame will always be at the end of the 2473 * total data upload. 2474 * 2475 * - We know the size of the desired received frame because it will be 2476 * provided in the length field of the status word in the last descriptor. 2477 * 2478 * Here's what we do: 2479 * 2480 * - When we allocate buffers for the receive ring, we bzero() them. 2481 * This means that we know that the buffer contents should be all 2482 * zeros, except for data uploaded by the chip. 2483 * 2484 * - We also force the PNIC chip to upload frames that include the 2485 * ethernet CRC at the end. 2486 * 2487 * - We gather all of the bogus frame data into a single buffer. 2488 * 2489 * - We then position a pointer at the end of this buffer and scan 2490 * backwards until we encounter the first non-zero byte of data. 2491 * This is the end of the received frame. We know we will encounter 2492 * some data at the end of the frame because the CRC will always be 2493 * there, so even if the sender transmits a packet of all zeros, 2494 * we won't be fooled. 2495 * 2496 * - We know the size of the actual received frame, so we subtract 2497 * that value from the current pointer location. This brings us 2498 * to the start of the actual received packet. 2499 * 2500 * - We copy this into an mbuf and pass it on, along with the actual 2501 * frame length. 2502 * 2503 * The performance hit is tremendous, but it beats dropping frames all 2504 * the time. 2505 */ 2506 2507 #define DC_WHOLEFRAME (DC_RXSTAT_FIRSTFRAG|DC_RXSTAT_LASTFRAG) 2508 static void 2509 dc_pnic_rx_bug_war(sc, idx) 2510 struct dc_softc *sc; 2511 int idx; 2512 { 2513 struct dc_desc *cur_rx; 2514 struct dc_desc *c = NULL; 2515 struct mbuf *m = NULL; 2516 unsigned char *ptr; 2517 int i, total_len; 2518 u_int32_t rxstat = 0; 2519 2520 i = sc->dc_pnic_rx_bug_save; 2521 cur_rx = &sc->dc_ldata->dc_rx_list[idx]; 2522 ptr = sc->dc_pnic_rx_buf; 2523 bzero(ptr, sizeof(DC_RXLEN * 5)); 2524 2525 /* Copy all the bytes from the bogus buffers. */ 2526 while (1) { 2527 c = &sc->dc_ldata->dc_rx_list[i]; 2528 rxstat = c->dc_status; 2529 m = sc->dc_cdata.dc_rx_chain[i]; 2530 bcopy(mtod(m, char *), ptr, DC_RXLEN); 2531 ptr += DC_RXLEN; 2532 /* If this is the last buffer, break out. */ 2533 if (i == idx || rxstat & DC_RXSTAT_LASTFRAG) 2534 break; 2535 dc_newbuf(sc, i, m); 2536 DC_INC(i, DC_RX_LIST_CNT); 2537 } 2538 2539 /* Find the length of the actual receive frame. */ 2540 total_len = DC_RXBYTES(rxstat); 2541 2542 /* Scan backwards until we hit a non-zero byte. */ 2543 while(*ptr == 0x00) 2544 ptr--; 2545 2546 /* Round off. */ 2547 if ((uintptr_t)(ptr) & 0x3) 2548 ptr -= 1; 2549 2550 /* Now find the start of the frame. */ 2551 ptr -= total_len; 2552 if (ptr < sc->dc_pnic_rx_buf) 2553 ptr = sc->dc_pnic_rx_buf; 2554 2555 /* 2556 * Now copy the salvaged frame to the last mbuf and fake up 2557 * the status word to make it look like a successful 2558 * frame reception. 2559 */ 2560 dc_newbuf(sc, i, m); 2561 bcopy(ptr, mtod(m, char *), total_len); 2562 cur_rx->dc_status = rxstat | DC_RXSTAT_FIRSTFRAG; 2563 2564 return; 2565 } 2566 2567 /* 2568 * This routine searches the RX ring for dirty descriptors in the 2569 * event that the rxeof routine falls out of sync with the chip's 2570 * current descriptor pointer. This may happen sometimes as a result 2571 * of a "no RX buffer available" condition that happens when the chip 2572 * consumes all of the RX buffers before the driver has a chance to 2573 * process the RX ring. This routine may need to be called more than 2574 * once to bring the driver back in sync with the chip, however we 2575 * should still be getting RX DONE interrupts to drive the search 2576 * for new packets in the RX ring, so we should catch up eventually. 2577 */ 2578 static int 2579 dc_rx_resync(sc) 2580 struct dc_softc *sc; 2581 { 2582 int i, pos; 2583 struct dc_desc *cur_rx; 2584 2585 pos = sc->dc_cdata.dc_rx_prod; 2586 2587 for (i = 0; i < DC_RX_LIST_CNT; i++) { 2588 cur_rx = &sc->dc_ldata->dc_rx_list[pos]; 2589 if (!(cur_rx->dc_status & DC_RXSTAT_OWN)) 2590 break; 2591 DC_INC(pos, DC_RX_LIST_CNT); 2592 } 2593 2594 /* If the ring really is empty, then just return. */ 2595 if (i == DC_RX_LIST_CNT) 2596 return(0); 2597 2598 /* We've fallen behing the chip: catch it. */ 2599 sc->dc_cdata.dc_rx_prod = pos; 2600 2601 return(EAGAIN); 2602 } 2603 2604 /* 2605 * A frame has been uploaded: pass the resulting mbuf chain up to 2606 * the higher level protocols. 2607 */ 2608 static void 2609 dc_rxeof(sc) 2610 struct dc_softc *sc; 2611 { 2612 struct mbuf *m; 2613 struct ifnet *ifp; 2614 struct dc_desc *cur_rx; 2615 int i, total_len = 0; 2616 u_int32_t rxstat; 2617 2618 ifp = &sc->arpcom.ac_if; 2619 i = sc->dc_cdata.dc_rx_prod; 2620 2621 while(!(sc->dc_ldata->dc_rx_list[i].dc_status & DC_RXSTAT_OWN)) { 2622 2623 #ifdef DEVICE_POLLING 2624 if (ifp->if_flags & IFF_POLLING) { 2625 if (sc->rxcycles <= 0) 2626 break; 2627 sc->rxcycles--; 2628 } 2629 #endif /* DEVICE_POLLING */ 2630 cur_rx = &sc->dc_ldata->dc_rx_list[i]; 2631 rxstat = cur_rx->dc_status; 2632 m = sc->dc_cdata.dc_rx_chain[i]; 2633 total_len = DC_RXBYTES(rxstat); 2634 2635 if (sc->dc_flags & DC_PNIC_RX_BUG_WAR) { 2636 if ((rxstat & DC_WHOLEFRAME) != DC_WHOLEFRAME) { 2637 if (rxstat & DC_RXSTAT_FIRSTFRAG) 2638 sc->dc_pnic_rx_bug_save = i; 2639 if ((rxstat & DC_RXSTAT_LASTFRAG) == 0) { 2640 DC_INC(i, DC_RX_LIST_CNT); 2641 continue; 2642 } 2643 dc_pnic_rx_bug_war(sc, i); 2644 rxstat = cur_rx->dc_status; 2645 total_len = DC_RXBYTES(rxstat); 2646 } 2647 } 2648 2649 sc->dc_cdata.dc_rx_chain[i] = NULL; 2650 2651 /* 2652 * If an error occurs, update stats, clear the 2653 * status word and leave the mbuf cluster in place: 2654 * it should simply get re-used next time this descriptor 2655 * comes up in the ring. However, don't report long 2656 * frames as errors since they could be vlans 2657 */ 2658 if ((rxstat & DC_RXSTAT_RXERR)){ 2659 if (!(rxstat & DC_RXSTAT_GIANT) || 2660 (rxstat & (DC_RXSTAT_CRCERR | DC_RXSTAT_DRIBBLE | 2661 DC_RXSTAT_MIIERE | DC_RXSTAT_COLLSEEN | 2662 DC_RXSTAT_RUNT | DC_RXSTAT_DE))) { 2663 ifp->if_ierrors++; 2664 if (rxstat & DC_RXSTAT_COLLSEEN) 2665 ifp->if_collisions++; 2666 dc_newbuf(sc, i, m); 2667 if (rxstat & DC_RXSTAT_CRCERR) { 2668 DC_INC(i, DC_RX_LIST_CNT); 2669 continue; 2670 } else { 2671 dc_init(sc); 2672 return; 2673 } 2674 } 2675 } 2676 2677 /* No errors; receive the packet. */ 2678 total_len -= ETHER_CRC_LEN; 2679 #ifdef __i386__ 2680 /* 2681 * On the x86 we do not have alignment problems, so try to 2682 * allocate a new buffer for the receive ring, and pass up 2683 * the one where the packet is already, saving the expensive 2684 * copy done in m_devget(). 2685 * If we are on an architecture with alignment problems, or 2686 * if the allocation fails, then use m_devget and leave the 2687 * existing buffer in the receive ring. 2688 */ 2689 if (dc_quick && dc_newbuf(sc, i, NULL) == 0) { 2690 m->m_pkthdr.rcvif = ifp; 2691 m->m_pkthdr.len = m->m_len = total_len; 2692 DC_INC(i, DC_RX_LIST_CNT); 2693 } else 2694 #endif 2695 { 2696 struct mbuf *m0; 2697 2698 m0 = m_devget(mtod(m, char *), total_len, 2699 ETHER_ALIGN, ifp, NULL); 2700 dc_newbuf(sc, i, m); 2701 DC_INC(i, DC_RX_LIST_CNT); 2702 if (m0 == NULL) { 2703 ifp->if_ierrors++; 2704 continue; 2705 } 2706 m = m0; 2707 } 2708 2709 ifp->if_ipackets++; 2710 (*ifp->if_input)(ifp, m); 2711 } 2712 2713 sc->dc_cdata.dc_rx_prod = i; 2714 } 2715 2716 /* 2717 * A frame was downloaded to the chip. It's safe for us to clean up 2718 * the list buffers. 2719 */ 2720 2721 static void 2722 dc_txeof(sc) 2723 struct dc_softc *sc; 2724 { 2725 struct dc_desc *cur_tx = NULL; 2726 struct ifnet *ifp; 2727 int idx; 2728 2729 ifp = &sc->arpcom.ac_if; 2730 2731 /* 2732 * Go through our tx list and free mbufs for those 2733 * frames that have been transmitted. 2734 */ 2735 idx = sc->dc_cdata.dc_tx_cons; 2736 while(idx != sc->dc_cdata.dc_tx_prod) { 2737 u_int32_t txstat; 2738 2739 cur_tx = &sc->dc_ldata->dc_tx_list[idx]; 2740 txstat = cur_tx->dc_status; 2741 2742 if (txstat & DC_TXSTAT_OWN) 2743 break; 2744 2745 if (!(cur_tx->dc_ctl & DC_TXCTL_LASTFRAG) || 2746 cur_tx->dc_ctl & DC_TXCTL_SETUP) { 2747 if (cur_tx->dc_ctl & DC_TXCTL_SETUP) { 2748 /* 2749 * Yes, the PNIC is so brain damaged 2750 * that it will sometimes generate a TX 2751 * underrun error while DMAing the RX 2752 * filter setup frame. If we detect this, 2753 * we have to send the setup frame again, 2754 * or else the filter won't be programmed 2755 * correctly. 2756 */ 2757 if (DC_IS_PNIC(sc)) { 2758 if (txstat & DC_TXSTAT_ERRSUM) 2759 dc_setfilt(sc); 2760 } 2761 sc->dc_cdata.dc_tx_chain[idx] = NULL; 2762 } 2763 sc->dc_cdata.dc_tx_cnt--; 2764 DC_INC(idx, DC_TX_LIST_CNT); 2765 continue; 2766 } 2767 2768 if (DC_IS_XIRCOM(sc) || DC_IS_CONEXANT(sc)) { 2769 /* 2770 * XXX: Why does my Xircom taunt me so? 2771 * For some reason it likes setting the CARRLOST flag 2772 * even when the carrier is there. wtf?!? 2773 * Who knows, but Conexant chips have the 2774 * same problem. Maybe they took lessons 2775 * from Xircom. 2776 */ 2777 if (/*sc->dc_type == DC_TYPE_21143 &&*/ 2778 sc->dc_pmode == DC_PMODE_MII && 2779 ((txstat & 0xFFFF) & ~(DC_TXSTAT_ERRSUM| 2780 DC_TXSTAT_NOCARRIER))) 2781 txstat &= ~DC_TXSTAT_ERRSUM; 2782 } else { 2783 if (/*sc->dc_type == DC_TYPE_21143 &&*/ 2784 sc->dc_pmode == DC_PMODE_MII && 2785 ((txstat & 0xFFFF) & ~(DC_TXSTAT_ERRSUM| 2786 DC_TXSTAT_NOCARRIER|DC_TXSTAT_CARRLOST))) 2787 txstat &= ~DC_TXSTAT_ERRSUM; 2788 } 2789 2790 if (txstat & DC_TXSTAT_ERRSUM) { 2791 ifp->if_oerrors++; 2792 if (txstat & DC_TXSTAT_EXCESSCOLL) 2793 ifp->if_collisions++; 2794 if (txstat & DC_TXSTAT_LATECOLL) 2795 ifp->if_collisions++; 2796 if (!(txstat & DC_TXSTAT_UNDERRUN)) { 2797 dc_init(sc); 2798 return; 2799 } 2800 } 2801 2802 ifp->if_collisions += (txstat & DC_TXSTAT_COLLCNT) >> 3; 2803 2804 ifp->if_opackets++; 2805 if (sc->dc_cdata.dc_tx_chain[idx] != NULL) { 2806 m_freem(sc->dc_cdata.dc_tx_chain[idx]); 2807 sc->dc_cdata.dc_tx_chain[idx] = NULL; 2808 } 2809 2810 sc->dc_cdata.dc_tx_cnt--; 2811 DC_INC(idx, DC_TX_LIST_CNT); 2812 } 2813 2814 if (idx != sc->dc_cdata.dc_tx_cons) { 2815 /* some buffers have been freed */ 2816 sc->dc_cdata.dc_tx_cons = idx; 2817 ifp->if_flags &= ~IFF_OACTIVE; 2818 } 2819 ifp->if_timer = (sc->dc_cdata.dc_tx_cnt == 0) ? 0 : 5; 2820 2821 return; 2822 } 2823 2824 static void 2825 dc_tick(xsc) 2826 void *xsc; 2827 { 2828 struct dc_softc *sc; 2829 struct mii_data *mii; 2830 struct ifnet *ifp; 2831 u_int32_t r; 2832 2833 sc = xsc; 2834 DC_LOCK(sc); 2835 ifp = &sc->arpcom.ac_if; 2836 mii = device_get_softc(sc->dc_miibus); 2837 2838 if (sc->dc_flags & DC_REDUCED_MII_POLL) { 2839 if (sc->dc_flags & DC_21143_NWAY) { 2840 r = CSR_READ_4(sc, DC_10BTSTAT); 2841 if (IFM_SUBTYPE(mii->mii_media_active) == 2842 IFM_100_TX && (r & DC_TSTAT_LS100)) { 2843 sc->dc_link = 0; 2844 mii_mediachg(mii); 2845 } 2846 if (IFM_SUBTYPE(mii->mii_media_active) == 2847 IFM_10_T && (r & DC_TSTAT_LS10)) { 2848 sc->dc_link = 0; 2849 mii_mediachg(mii); 2850 } 2851 if (sc->dc_link == 0) 2852 mii_tick(mii); 2853 } else { 2854 r = CSR_READ_4(sc, DC_ISR); 2855 if ((r & DC_ISR_RX_STATE) == DC_RXSTATE_WAIT && 2856 sc->dc_cdata.dc_tx_cnt == 0) { 2857 mii_tick(mii); 2858 if (!(mii->mii_media_status & IFM_ACTIVE)) 2859 sc->dc_link = 0; 2860 } 2861 } 2862 } else 2863 mii_tick(mii); 2864 2865 /* 2866 * When the init routine completes, we expect to be able to send 2867 * packets right away, and in fact the network code will send a 2868 * gratuitous ARP the moment the init routine marks the interface 2869 * as running. However, even though the MAC may have been initialized, 2870 * there may be a delay of a few seconds before the PHY completes 2871 * autonegotiation and the link is brought up. Any transmissions 2872 * made during that delay will be lost. Dealing with this is tricky: 2873 * we can't just pause in the init routine while waiting for the 2874 * PHY to come ready since that would bring the whole system to 2875 * a screeching halt for several seconds. 2876 * 2877 * What we do here is prevent the TX start routine from sending 2878 * any packets until a link has been established. After the 2879 * interface has been initialized, the tick routine will poll 2880 * the state of the PHY until the IFM_ACTIVE flag is set. Until 2881 * that time, packets will stay in the send queue, and once the 2882 * link comes up, they will be flushed out to the wire. 2883 */ 2884 if (!sc->dc_link && mii->mii_media_status & IFM_ACTIVE && 2885 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) { 2886 sc->dc_link++; 2887 if (ifp->if_snd.ifq_head != NULL) 2888 dc_start(ifp); 2889 } 2890 2891 if (sc->dc_flags & DC_21143_NWAY && !sc->dc_link) 2892 callout_reset(&sc->dc_stat_ch, hz/10, dc_tick, sc); 2893 else 2894 callout_reset(&sc->dc_stat_ch, hz, dc_tick, sc); 2895 2896 DC_UNLOCK(sc); 2897 2898 return; 2899 } 2900 2901 /* 2902 * A transmit underrun has occurred. Back off the transmit threshold, 2903 * or switch to store and forward mode if we have to. 2904 */ 2905 static void 2906 dc_tx_underrun(sc) 2907 struct dc_softc *sc; 2908 { 2909 u_int32_t isr; 2910 int i; 2911 2912 if (DC_IS_DAVICOM(sc)) 2913 dc_init(sc); 2914 2915 if (DC_IS_INTEL(sc)) { 2916 /* 2917 * The real 21143 requires that the transmitter be idle 2918 * in order to change the transmit threshold or store 2919 * and forward state. 2920 */ 2921 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_TX_ON); 2922 2923 for (i = 0; i < DC_TIMEOUT; i++) { 2924 isr = CSR_READ_4(sc, DC_ISR); 2925 if (isr & DC_ISR_TX_IDLE) 2926 break; 2927 DELAY(10); 2928 } 2929 if (i == DC_TIMEOUT) { 2930 printf("dc%d: failed to force tx to idle state\n", 2931 sc->dc_unit); 2932 dc_init(sc); 2933 } 2934 } 2935 2936 printf("dc%d: TX underrun -- ", sc->dc_unit); 2937 sc->dc_txthresh += DC_TXTHRESH_INC; 2938 if (sc->dc_txthresh > DC_TXTHRESH_MAX) { 2939 printf("using store and forward mode\n"); 2940 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_STORENFWD); 2941 } else { 2942 printf("increasing TX threshold\n"); 2943 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_TX_THRESH); 2944 DC_SETBIT(sc, DC_NETCFG, sc->dc_txthresh); 2945 } 2946 2947 if (DC_IS_INTEL(sc)) 2948 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_TX_ON); 2949 2950 return; 2951 } 2952 2953 #ifdef DEVICE_POLLING 2954 static poll_handler_t dc_poll; 2955 2956 static void 2957 dc_poll(struct ifnet *ifp, enum poll_cmd cmd, int count) 2958 { 2959 struct dc_softc *sc = ifp->if_softc; 2960 2961 if (cmd == POLL_DEREGISTER) { /* final call, enable interrupts */ 2962 /* Re-enable interrupts. */ 2963 CSR_WRITE_4(sc, DC_IMR, DC_INTRS); 2964 return; 2965 } 2966 sc->rxcycles = count; 2967 dc_rxeof(sc); 2968 dc_txeof(sc); 2969 if (ifp->if_snd.ifq_head != NULL && !(ifp->if_flags & IFF_OACTIVE)) 2970 dc_start(ifp); 2971 2972 if (cmd == POLL_AND_CHECK_STATUS) { /* also check status register */ 2973 u_int32_t status; 2974 2975 status = CSR_READ_4(sc, DC_ISR); 2976 status &= (DC_ISR_RX_WATDOGTIMEO|DC_ISR_RX_NOBUF| 2977 DC_ISR_TX_NOBUF|DC_ISR_TX_IDLE|DC_ISR_TX_UNDERRUN| 2978 DC_ISR_BUS_ERR); 2979 if (!status) 2980 return; 2981 /* ack what we have */ 2982 CSR_WRITE_4(sc, DC_ISR, status); 2983 2984 if (status & (DC_ISR_RX_WATDOGTIMEO|DC_ISR_RX_NOBUF)) { 2985 u_int32_t r = CSR_READ_4(sc, DC_FRAMESDISCARDED); 2986 ifp->if_ierrors += (r & 0xffff) + ((r >> 17) & 0x7ff); 2987 2988 if (dc_rx_resync(sc)) 2989 dc_rxeof(sc); 2990 } 2991 /* restart transmit unit if necessary */ 2992 if (status & DC_ISR_TX_IDLE && sc->dc_cdata.dc_tx_cnt) 2993 CSR_WRITE_4(sc, DC_TXSTART, 0xFFFFFFFF); 2994 2995 if (status & DC_ISR_TX_UNDERRUN) 2996 dc_tx_underrun(sc); 2997 2998 if (status & DC_ISR_BUS_ERR) { 2999 printf("dc_poll: dc%d bus error\n", sc->dc_unit); 3000 dc_reset(sc); 3001 dc_init(sc); 3002 } 3003 } 3004 } 3005 #endif /* DEVICE_POLLING */ 3006 3007 static void 3008 dc_intr(arg) 3009 void *arg; 3010 { 3011 struct dc_softc *sc; 3012 struct ifnet *ifp; 3013 u_int32_t status; 3014 3015 sc = arg; 3016 3017 if (sc->suspended) { 3018 return; 3019 } 3020 3021 if ((CSR_READ_4(sc, DC_ISR) & DC_INTRS) == 0) 3022 return; 3023 3024 DC_LOCK(sc); 3025 ifp = &sc->arpcom.ac_if; 3026 #ifdef DEVICE_POLLING 3027 if (ifp->if_flags & IFF_POLLING) 3028 goto done; 3029 if (ether_poll_register(dc_poll, ifp)) { /* ok, disable interrupts */ 3030 CSR_WRITE_4(sc, DC_IMR, 0x00000000); 3031 goto done; 3032 } 3033 #endif /* DEVICE_POLLING */ 3034 3035 /* Suppress unwanted interrupts */ 3036 if (!(ifp->if_flags & IFF_UP)) { 3037 if (CSR_READ_4(sc, DC_ISR) & DC_INTRS) 3038 dc_stop(sc); 3039 DC_UNLOCK(sc); 3040 return; 3041 } 3042 3043 /* Disable interrupts. */ 3044 CSR_WRITE_4(sc, DC_IMR, 0x00000000); 3045 3046 while(((status = CSR_READ_4(sc, DC_ISR)) & DC_INTRS) 3047 && status != 0xFFFFFFFF) { 3048 3049 CSR_WRITE_4(sc, DC_ISR, status); 3050 3051 if (status & DC_ISR_RX_OK) { 3052 int curpkts; 3053 curpkts = ifp->if_ipackets; 3054 dc_rxeof(sc); 3055 if (curpkts == ifp->if_ipackets) { 3056 while(dc_rx_resync(sc)) 3057 dc_rxeof(sc); 3058 } 3059 } 3060 3061 if (status & (DC_ISR_TX_OK|DC_ISR_TX_NOBUF)) 3062 dc_txeof(sc); 3063 3064 if (status & DC_ISR_TX_IDLE) { 3065 dc_txeof(sc); 3066 if (sc->dc_cdata.dc_tx_cnt) { 3067 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_TX_ON); 3068 CSR_WRITE_4(sc, DC_TXSTART, 0xFFFFFFFF); 3069 } 3070 } 3071 3072 if (status & DC_ISR_TX_UNDERRUN) 3073 dc_tx_underrun(sc); 3074 3075 if ((status & DC_ISR_RX_WATDOGTIMEO) 3076 || (status & DC_ISR_RX_NOBUF)) { 3077 int curpkts; 3078 curpkts = ifp->if_ipackets; 3079 dc_rxeof(sc); 3080 if (curpkts == ifp->if_ipackets) { 3081 while(dc_rx_resync(sc)) 3082 dc_rxeof(sc); 3083 } 3084 } 3085 3086 if (status & DC_ISR_BUS_ERR) { 3087 dc_reset(sc); 3088 dc_init(sc); 3089 } 3090 } 3091 3092 /* Re-enable interrupts. */ 3093 CSR_WRITE_4(sc, DC_IMR, DC_INTRS); 3094 3095 if (ifp->if_snd.ifq_head != NULL) 3096 dc_start(ifp); 3097 3098 #ifdef DEVICE_POLLING 3099 done: 3100 #endif /* DEVICE_POLLING */ 3101 3102 DC_UNLOCK(sc); 3103 3104 return; 3105 } 3106 3107 /* 3108 * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data 3109 * pointers to the fragment pointers. 3110 */ 3111 static int 3112 dc_encap(sc, m_head, txidx) 3113 struct dc_softc *sc; 3114 struct mbuf *m_head; 3115 u_int32_t *txidx; 3116 { 3117 struct dc_desc *f = NULL; 3118 struct mbuf *m; 3119 int frag, cur, cnt = 0, chainlen = 0; 3120 3121 /* 3122 * If there's no way we can send any packets, return now. 3123 */ 3124 if (DC_TX_LIST_CNT - sc->dc_cdata.dc_tx_cnt < 6) 3125 return (ENOBUFS); 3126 3127 /* 3128 * Count the number of frags in this chain to see if 3129 * we need to m_defrag. Since the descriptor list is shared 3130 * by all packets, we'll m_defrag long chains so that they 3131 * do not use up the entire list, even if they would fit. 3132 */ 3133 3134 for (m = m_head; m != NULL; m = m->m_next) 3135 chainlen++; 3136 3137 if ((chainlen > DC_TX_LIST_CNT / 4) || 3138 ((DC_TX_LIST_CNT - (chainlen + sc->dc_cdata.dc_tx_cnt)) < 6)) { 3139 m = m_defrag(m_head, M_DONTWAIT); 3140 if (m == NULL) 3141 return (ENOBUFS); 3142 m_head = m; 3143 } 3144 3145 /* 3146 * Start packing the mbufs in this chain into 3147 * the fragment pointers. Stop when we run out 3148 * of fragments or hit the end of the mbuf chain. 3149 */ 3150 m = m_head; 3151 cur = frag = *txidx; 3152 3153 for (m = m_head; m != NULL; m = m->m_next) { 3154 if (m->m_len != 0) { 3155 if (sc->dc_flags & DC_TX_ADMTEK_WAR) { 3156 if (*txidx != sc->dc_cdata.dc_tx_prod && 3157 frag == (DC_TX_LIST_CNT - 1)) 3158 return(ENOBUFS); 3159 } 3160 if ((DC_TX_LIST_CNT - 3161 (sc->dc_cdata.dc_tx_cnt + cnt)) < 5) 3162 return(ENOBUFS); 3163 3164 f = &sc->dc_ldata->dc_tx_list[frag]; 3165 f->dc_ctl = DC_TXCTL_TLINK | m->m_len; 3166 if (cnt == 0) { 3167 f->dc_status = 0; 3168 f->dc_ctl |= DC_TXCTL_FIRSTFRAG; 3169 } else 3170 f->dc_status = DC_TXSTAT_OWN; 3171 f->dc_data = vtophys(mtod(m, vm_offset_t)); 3172 cur = frag; 3173 DC_INC(frag, DC_TX_LIST_CNT); 3174 cnt++; 3175 } 3176 } 3177 3178 if (m != NULL) 3179 return(ENOBUFS); 3180 3181 sc->dc_cdata.dc_tx_cnt += cnt; 3182 sc->dc_cdata.dc_tx_chain[cur] = m_head; 3183 sc->dc_ldata->dc_tx_list[cur].dc_ctl |= DC_TXCTL_LASTFRAG; 3184 if (sc->dc_flags & DC_TX_INTR_FIRSTFRAG) 3185 sc->dc_ldata->dc_tx_list[*txidx].dc_ctl |= DC_TXCTL_FINT; 3186 if (sc->dc_flags & DC_TX_INTR_ALWAYS) 3187 sc->dc_ldata->dc_tx_list[cur].dc_ctl |= DC_TXCTL_FINT; 3188 if (sc->dc_flags & DC_TX_USE_TX_INTR && sc->dc_cdata.dc_tx_cnt > 64) 3189 sc->dc_ldata->dc_tx_list[cur].dc_ctl |= DC_TXCTL_FINT; 3190 sc->dc_ldata->dc_tx_list[*txidx].dc_status = DC_TXSTAT_OWN; 3191 *txidx = frag; 3192 3193 return(0); 3194 } 3195 3196 /* 3197 * Main transmit routine. To avoid having to do mbuf copies, we put pointers 3198 * to the mbuf data regions directly in the transmit lists. We also save a 3199 * copy of the pointers since the transmit list fragment pointers are 3200 * physical addresses. 3201 */ 3202 3203 static void 3204 dc_start(ifp) 3205 struct ifnet *ifp; 3206 { 3207 struct dc_softc *sc; 3208 struct mbuf *m_head = NULL, *m; 3209 int idx; 3210 3211 sc = ifp->if_softc; 3212 3213 DC_LOCK(sc); 3214 3215 if (!sc->dc_link && ifp->if_snd.ifq_len < 10) { 3216 DC_UNLOCK(sc); 3217 return; 3218 } 3219 3220 if (ifp->if_flags & IFF_OACTIVE) { 3221 DC_UNLOCK(sc); 3222 return; 3223 } 3224 3225 idx = sc->dc_cdata.dc_tx_prod; 3226 3227 while(sc->dc_cdata.dc_tx_chain[idx] == NULL) { 3228 IF_DEQUEUE(&ifp->if_snd, m_head); 3229 if (m_head == NULL) 3230 break; 3231 3232 if (sc->dc_flags & DC_TX_COALESCE && 3233 (m_head->m_next != NULL || 3234 sc->dc_flags & DC_TX_ALIGN)) { 3235 m = m_defrag(m_head, M_DONTWAIT); 3236 if (m == NULL) { 3237 IF_PREPEND(&ifp->if_snd, m_head); 3238 ifp->if_flags |= IFF_OACTIVE; 3239 break; 3240 } else { 3241 m_head = m; 3242 } 3243 } 3244 3245 if (dc_encap(sc, m_head, &idx)) { 3246 IF_PREPEND(&ifp->if_snd, m_head); 3247 ifp->if_flags |= IFF_OACTIVE; 3248 break; 3249 } 3250 3251 /* 3252 * If there's a BPF listener, bounce a copy of this frame 3253 * to him. 3254 */ 3255 BPF_MTAP(ifp, m_head); 3256 3257 if (sc->dc_flags & DC_TX_ONE) { 3258 ifp->if_flags |= IFF_OACTIVE; 3259 break; 3260 } 3261 } 3262 3263 /* Transmit */ 3264 sc->dc_cdata.dc_tx_prod = idx; 3265 if (!(sc->dc_flags & DC_TX_POLL)) 3266 CSR_WRITE_4(sc, DC_TXSTART, 0xFFFFFFFF); 3267 3268 /* 3269 * Set a timeout in case the chip goes out to lunch. 3270 */ 3271 ifp->if_timer = 5; 3272 3273 DC_UNLOCK(sc); 3274 3275 return; 3276 } 3277 3278 static void 3279 dc_init(xsc) 3280 void *xsc; 3281 { 3282 struct dc_softc *sc = xsc; 3283 struct ifnet *ifp = &sc->arpcom.ac_if; 3284 struct mii_data *mii; 3285 3286 DC_LOCK(sc); 3287 3288 mii = device_get_softc(sc->dc_miibus); 3289 3290 /* 3291 * Cancel pending I/O and free all RX/TX buffers. 3292 */ 3293 dc_stop(sc); 3294 dc_reset(sc); 3295 3296 /* 3297 * Set cache alignment and burst length. 3298 */ 3299 if (DC_IS_ASIX(sc) || DC_IS_DAVICOM(sc)) 3300 CSR_WRITE_4(sc, DC_BUSCTL, 0); 3301 else 3302 CSR_WRITE_4(sc, DC_BUSCTL, DC_BUSCTL_MRME|DC_BUSCTL_MRLE); 3303 /* 3304 * Evenly share the bus between receive and transmit process. 3305 */ 3306 if (DC_IS_INTEL(sc)) 3307 DC_SETBIT(sc, DC_BUSCTL, DC_BUSCTL_ARBITRATION); 3308 if (DC_IS_DAVICOM(sc) || DC_IS_INTEL(sc)) { 3309 DC_SETBIT(sc, DC_BUSCTL, DC_BURSTLEN_USECA); 3310 } else { 3311 DC_SETBIT(sc, DC_BUSCTL, DC_BURSTLEN_16LONG); 3312 } 3313 if (sc->dc_flags & DC_TX_POLL) 3314 DC_SETBIT(sc, DC_BUSCTL, DC_TXPOLL_1); 3315 switch(sc->dc_cachesize) { 3316 case 32: 3317 DC_SETBIT(sc, DC_BUSCTL, DC_CACHEALIGN_32LONG); 3318 break; 3319 case 16: 3320 DC_SETBIT(sc, DC_BUSCTL, DC_CACHEALIGN_16LONG); 3321 break; 3322 case 8: 3323 DC_SETBIT(sc, DC_BUSCTL, DC_CACHEALIGN_8LONG); 3324 break; 3325 case 0: 3326 default: 3327 DC_SETBIT(sc, DC_BUSCTL, DC_CACHEALIGN_NONE); 3328 break; 3329 } 3330 3331 if (sc->dc_flags & DC_TX_STORENFWD) 3332 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_STORENFWD); 3333 else { 3334 if (sc->dc_txthresh > DC_TXTHRESH_MAX) { 3335 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_STORENFWD); 3336 } else { 3337 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_STORENFWD); 3338 DC_SETBIT(sc, DC_NETCFG, sc->dc_txthresh); 3339 } 3340 } 3341 3342 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_NO_RXCRC); 3343 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_TX_BACKOFF); 3344 3345 if (DC_IS_MACRONIX(sc) || DC_IS_PNICII(sc)) { 3346 /* 3347 * The app notes for the 98713 and 98715A say that 3348 * in order to have the chips operate properly, a magic 3349 * number must be written to CSR16. Macronix does not 3350 * document the meaning of these bits so there's no way 3351 * to know exactly what they do. The 98713 has a magic 3352 * number all its own; the rest all use a different one. 3353 */ 3354 DC_CLRBIT(sc, DC_MX_MAGICPACKET, 0xFFFF0000); 3355 if (sc->dc_type == DC_TYPE_98713) 3356 DC_SETBIT(sc, DC_MX_MAGICPACKET, DC_MX_MAGIC_98713); 3357 else 3358 DC_SETBIT(sc, DC_MX_MAGICPACKET, DC_MX_MAGIC_98715); 3359 } 3360 3361 if (DC_IS_XIRCOM(sc)) { 3362 /* 3363 * setup General Purpose Port mode and data so the tulip 3364 * can talk to the MII. 3365 */ 3366 CSR_WRITE_4(sc, DC_SIAGP, DC_SIAGP_WRITE_EN | DC_SIAGP_INT1_EN | 3367 DC_SIAGP_MD_GP2_OUTPUT | DC_SIAGP_MD_GP0_OUTPUT); 3368 DELAY(10); 3369 CSR_WRITE_4(sc, DC_SIAGP, DC_SIAGP_INT1_EN | 3370 DC_SIAGP_MD_GP2_OUTPUT | DC_SIAGP_MD_GP0_OUTPUT); 3371 DELAY(10); 3372 } 3373 3374 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_TX_THRESH); 3375 DC_SETBIT(sc, DC_NETCFG, DC_TXTHRESH_MIN); 3376 3377 /* Init circular RX list. */ 3378 if (dc_list_rx_init(sc) == ENOBUFS) { 3379 printf("dc%d: initialization failed: no " 3380 "memory for rx buffers\n", sc->dc_unit); 3381 dc_stop(sc); 3382 DC_UNLOCK(sc); 3383 return; 3384 } 3385 3386 /* 3387 * Init tx descriptors. 3388 */ 3389 dc_list_tx_init(sc); 3390 3391 /* 3392 * Load the address of the RX list. 3393 */ 3394 CSR_WRITE_4(sc, DC_RXADDR, vtophys(&sc->dc_ldata->dc_rx_list[0])); 3395 CSR_WRITE_4(sc, DC_TXADDR, vtophys(&sc->dc_ldata->dc_tx_list[0])); 3396 3397 /* 3398 * Enable interrupts. 3399 */ 3400 #ifdef DEVICE_POLLING 3401 /* 3402 * ... but only if we are not polling, and make sure they are off in 3403 * the case of polling. Some cards (e.g. fxp) turn interrupts on 3404 * after a reset. 3405 */ 3406 if (ifp->if_flags & IFF_POLLING) 3407 CSR_WRITE_4(sc, DC_IMR, 0x00000000); 3408 else 3409 #endif 3410 CSR_WRITE_4(sc, DC_IMR, DC_INTRS); 3411 CSR_WRITE_4(sc, DC_ISR, 0xFFFFFFFF); 3412 3413 /* Enable transmitter. */ 3414 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_TX_ON); 3415 3416 /* 3417 * If this is an Intel 21143 and we're not using the 3418 * MII port, program the LED control pins so we get 3419 * link and activity indications. 3420 */ 3421 if (sc->dc_flags & DC_TULIP_LEDS) { 3422 CSR_WRITE_4(sc, DC_WATCHDOG, 3423 DC_WDOG_CTLWREN|DC_WDOG_LINK|DC_WDOG_ACTIVITY); 3424 CSR_WRITE_4(sc, DC_WATCHDOG, 0); 3425 } 3426 3427 /* 3428 * Load the RX/multicast filter. We do this sort of late 3429 * because the filter programming scheme on the 21143 and 3430 * some clones requires DMAing a setup frame via the TX 3431 * engine, and we need the transmitter enabled for that. 3432 */ 3433 dc_setfilt(sc); 3434 3435 /* Enable receiver. */ 3436 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_ON); 3437 CSR_WRITE_4(sc, DC_RXSTART, 0xFFFFFFFF); 3438 3439 mii_mediachg(mii); 3440 dc_setcfg(sc, sc->dc_if_media); 3441 3442 ifp->if_flags |= IFF_RUNNING; 3443 ifp->if_flags &= ~IFF_OACTIVE; 3444 3445 /* Don't start the ticker if this is a homePNA link. */ 3446 if (IFM_SUBTYPE(mii->mii_media.ifm_media) == IFM_HPNA_1) 3447 sc->dc_link = 1; 3448 else { 3449 if (sc->dc_flags & DC_21143_NWAY) 3450 callout_reset(&sc->dc_stat_ch, hz/10, dc_tick, sc); 3451 else 3452 callout_reset(&sc->dc_stat_ch, hz, dc_tick, sc); 3453 } 3454 3455 #ifdef SRM_MEDIA 3456 if(sc->dc_srm_media) { 3457 struct ifreq ifr; 3458 3459 ifr.ifr_media = sc->dc_srm_media; 3460 ifmedia_ioctl(ifp, &ifr, &mii->mii_media, SIOCSIFMEDIA); 3461 sc->dc_srm_media = 0; 3462 } 3463 #endif 3464 DC_UNLOCK(sc); 3465 return; 3466 } 3467 3468 /* 3469 * Set media options. 3470 */ 3471 static int 3472 dc_ifmedia_upd(ifp) 3473 struct ifnet *ifp; 3474 { 3475 struct dc_softc *sc; 3476 struct mii_data *mii; 3477 struct ifmedia *ifm; 3478 3479 sc = ifp->if_softc; 3480 mii = device_get_softc(sc->dc_miibus); 3481 mii_mediachg(mii); 3482 ifm = &mii->mii_media; 3483 3484 if (DC_IS_DAVICOM(sc) && 3485 IFM_SUBTYPE(ifm->ifm_media) == IFM_HPNA_1) 3486 dc_setcfg(sc, ifm->ifm_media); 3487 else 3488 sc->dc_link = 0; 3489 3490 return(0); 3491 } 3492 3493 /* 3494 * Report current media status. 3495 */ 3496 static void 3497 dc_ifmedia_sts(ifp, ifmr) 3498 struct ifnet *ifp; 3499 struct ifmediareq *ifmr; 3500 { 3501 struct dc_softc *sc; 3502 struct mii_data *mii; 3503 struct ifmedia *ifm; 3504 3505 sc = ifp->if_softc; 3506 mii = device_get_softc(sc->dc_miibus); 3507 mii_pollstat(mii); 3508 ifm = &mii->mii_media; 3509 if (DC_IS_DAVICOM(sc)) { 3510 if (IFM_SUBTYPE(ifm->ifm_media) == IFM_HPNA_1) { 3511 ifmr->ifm_active = ifm->ifm_media; 3512 ifmr->ifm_status = 0; 3513 return; 3514 } 3515 } 3516 ifmr->ifm_active = mii->mii_media_active; 3517 ifmr->ifm_status = mii->mii_media_status; 3518 3519 return; 3520 } 3521 3522 static int 3523 dc_ioctl(ifp, command, data) 3524 struct ifnet *ifp; 3525 u_long command; 3526 caddr_t data; 3527 { 3528 struct dc_softc *sc = ifp->if_softc; 3529 struct ifreq *ifr = (struct ifreq *) data; 3530 struct mii_data *mii; 3531 int error = 0; 3532 3533 DC_LOCK(sc); 3534 3535 switch(command) { 3536 case SIOCSIFFLAGS: 3537 if (ifp->if_flags & IFF_UP) { 3538 int need_setfilt = (ifp->if_flags ^ sc->dc_if_flags) & 3539 (IFF_PROMISC | IFF_ALLMULTI); 3540 3541 if (ifp->if_flags & IFF_RUNNING) { 3542 if (need_setfilt) 3543 dc_setfilt(sc); 3544 } else { 3545 sc->dc_txthresh = 0; 3546 dc_init(sc); 3547 } 3548 } else { 3549 if (ifp->if_flags & IFF_RUNNING) 3550 dc_stop(sc); 3551 } 3552 sc->dc_if_flags = ifp->if_flags; 3553 error = 0; 3554 break; 3555 case SIOCADDMULTI: 3556 case SIOCDELMULTI: 3557 dc_setfilt(sc); 3558 error = 0; 3559 break; 3560 case SIOCGIFMEDIA: 3561 case SIOCSIFMEDIA: 3562 mii = device_get_softc(sc->dc_miibus); 3563 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 3564 #ifdef SRM_MEDIA 3565 if (sc->dc_srm_media) 3566 sc->dc_srm_media = 0; 3567 #endif 3568 break; 3569 default: 3570 error = ether_ioctl(ifp, command, data); 3571 break; 3572 } 3573 3574 DC_UNLOCK(sc); 3575 3576 return(error); 3577 } 3578 3579 static void 3580 dc_watchdog(ifp) 3581 struct ifnet *ifp; 3582 { 3583 struct dc_softc *sc; 3584 3585 sc = ifp->if_softc; 3586 3587 DC_LOCK(sc); 3588 3589 ifp->if_oerrors++; 3590 printf("dc%d: watchdog timeout\n", sc->dc_unit); 3591 3592 dc_stop(sc); 3593 dc_reset(sc); 3594 dc_init(sc); 3595 3596 if (ifp->if_snd.ifq_head != NULL) 3597 dc_start(ifp); 3598 3599 DC_UNLOCK(sc); 3600 3601 return; 3602 } 3603 3604 /* 3605 * Stop the adapter and free any mbufs allocated to the 3606 * RX and TX lists. 3607 */ 3608 static void 3609 dc_stop(sc) 3610 struct dc_softc *sc; 3611 { 3612 register int i; 3613 struct ifnet *ifp; 3614 3615 DC_LOCK(sc); 3616 3617 ifp = &sc->arpcom.ac_if; 3618 ifp->if_timer = 0; 3619 3620 callout_stop(&sc->dc_stat_ch); 3621 3622 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 3623 #ifdef DEVICE_POLLING 3624 ether_poll_deregister(ifp); 3625 #endif 3626 3627 DC_CLRBIT(sc, DC_NETCFG, (DC_NETCFG_RX_ON|DC_NETCFG_TX_ON)); 3628 CSR_WRITE_4(sc, DC_IMR, 0x00000000); 3629 CSR_WRITE_4(sc, DC_TXADDR, 0x00000000); 3630 CSR_WRITE_4(sc, DC_RXADDR, 0x00000000); 3631 sc->dc_link = 0; 3632 3633 /* 3634 * Free data in the RX lists. 3635 */ 3636 for (i = 0; i < DC_RX_LIST_CNT; i++) { 3637 if (sc->dc_cdata.dc_rx_chain[i] != NULL) { 3638 m_freem(sc->dc_cdata.dc_rx_chain[i]); 3639 sc->dc_cdata.dc_rx_chain[i] = NULL; 3640 } 3641 } 3642 bzero((char *)&sc->dc_ldata->dc_rx_list, 3643 sizeof(sc->dc_ldata->dc_rx_list)); 3644 3645 /* 3646 * Free the TX list buffers. 3647 */ 3648 for (i = 0; i < DC_TX_LIST_CNT; i++) { 3649 if (sc->dc_cdata.dc_tx_chain[i] != NULL) { 3650 if (sc->dc_ldata->dc_tx_list[i].dc_ctl & 3651 DC_TXCTL_SETUP) { 3652 sc->dc_cdata.dc_tx_chain[i] = NULL; 3653 continue; 3654 } 3655 m_freem(sc->dc_cdata.dc_tx_chain[i]); 3656 sc->dc_cdata.dc_tx_chain[i] = NULL; 3657 } 3658 } 3659 3660 bzero((char *)&sc->dc_ldata->dc_tx_list, 3661 sizeof(sc->dc_ldata->dc_tx_list)); 3662 3663 DC_UNLOCK(sc); 3664 3665 return; 3666 } 3667 3668 /* 3669 * Device suspend routine. Stop the interface and save some PCI 3670 * settings in case the BIOS doesn't restore them properly on 3671 * resume. 3672 */ 3673 static int 3674 dc_suspend(dev) 3675 device_t dev; 3676 { 3677 register int i; 3678 int s; 3679 struct dc_softc *sc; 3680 3681 s = splimp(); 3682 3683 sc = device_get_softc(dev); 3684 3685 dc_stop(sc); 3686 3687 for (i = 0; i < 5; i++) 3688 sc->saved_maps[i] = pci_read_config(dev, PCIR_MAPS + i * 4, 4); 3689 sc->saved_biosaddr = pci_read_config(dev, PCIR_BIOS, 4); 3690 sc->saved_intline = pci_read_config(dev, PCIR_INTLINE, 1); 3691 sc->saved_cachelnsz = pci_read_config(dev, PCIR_CACHELNSZ, 1); 3692 sc->saved_lattimer = pci_read_config(dev, PCIR_LATTIMER, 1); 3693 3694 sc->suspended = 1; 3695 3696 splx(s); 3697 return (0); 3698 } 3699 3700 /* 3701 * Device resume routine. Restore some PCI settings in case the BIOS 3702 * doesn't, re-enable busmastering, and restart the interface if 3703 * appropriate. 3704 */ 3705 static int 3706 dc_resume(dev) 3707 device_t dev; 3708 { 3709 register int i; 3710 int s; 3711 struct dc_softc *sc; 3712 struct ifnet *ifp; 3713 3714 s = splimp(); 3715 3716 sc = device_get_softc(dev); 3717 ifp = &sc->arpcom.ac_if; 3718 3719 dc_acpi(dev); 3720 3721 /* better way to do this? */ 3722 for (i = 0; i < 5; i++) 3723 pci_write_config(dev, PCIR_MAPS + i * 4, sc->saved_maps[i], 4); 3724 pci_write_config(dev, PCIR_BIOS, sc->saved_biosaddr, 4); 3725 pci_write_config(dev, PCIR_INTLINE, sc->saved_intline, 1); 3726 pci_write_config(dev, PCIR_CACHELNSZ, sc->saved_cachelnsz, 1); 3727 pci_write_config(dev, PCIR_LATTIMER, sc->saved_lattimer, 1); 3728 3729 /* reenable busmastering */ 3730 pci_enable_busmaster(dev); 3731 pci_enable_io(dev, DC_RES); 3732 3733 /* reinitialize interface if necessary */ 3734 if (ifp->if_flags & IFF_UP) 3735 dc_init(sc); 3736 3737 sc->suspended = 0; 3738 3739 splx(s); 3740 return (0); 3741 } 3742 3743 /* 3744 * Stop all chip I/O so that the kernel's probe routines don't 3745 * get confused by errant DMAs when rebooting. 3746 */ 3747 static void 3748 dc_shutdown(dev) 3749 device_t dev; 3750 { 3751 struct dc_softc *sc; 3752 3753 sc = device_get_softc(dev); 3754 3755 dc_stop(sc); 3756 3757 return; 3758 } 3759