1 /*- 2 * Copyright (c) 1997, 1998, 1999 3 * Bill Paul <wpaul@ee.columbia.edu>. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 3. All advertising materials mentioning features or use of this software 14 * must display the following acknowledgement: 15 * This product includes software developed by Bill Paul. 16 * 4. Neither the name of the author nor the names of any co-contributors 17 * may be used to endorse or promote products derived from this software 18 * without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30 * THE POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33 #include <sys/cdefs.h> 34 __FBSDID("$FreeBSD$"); 35 36 /* 37 * DEC "tulip" clone ethernet driver. Supports the DEC/Intel 21143 38 * series chips and several workalikes including the following: 39 * 40 * Macronix 98713/98715/98725/98727/98732 PMAC (www.macronix.com) 41 * Macronix/Lite-On 82c115 PNIC II (www.macronix.com) 42 * Lite-On 82c168/82c169 PNIC (www.litecom.com) 43 * ASIX Electronics AX88140A (www.asix.com.tw) 44 * ASIX Electronics AX88141 (www.asix.com.tw) 45 * ADMtek AL981 (www.admtek.com.tw) 46 * ADMtek AN985 (www.admtek.com.tw) 47 * Netgear FA511 (www.netgear.com) Appears to be rebadged ADMTek AN985 48 * Davicom DM9100, DM9102, DM9102A (www.davicom8.com) 49 * Accton EN1217 (www.accton.com) 50 * Xircom X3201 (www.xircom.com) 51 * Abocom FE2500 52 * Conexant LANfinity (www.conexant.com) 53 * 3Com OfficeConnect 10/100B 3CSOHO100B (www.3com.com) 54 * 55 * Datasheets for the 21143 are available at developer.intel.com. 56 * Datasheets for the clone parts can be found at their respective sites. 57 * (Except for the PNIC; see www.freebsd.org/~wpaul/PNIC/pnic.ps.gz.) 58 * The PNIC II is essentially a Macronix 98715A chip; the only difference 59 * worth noting is that its multicast hash table is only 128 bits wide 60 * instead of 512. 61 * 62 * Written by Bill Paul <wpaul@ee.columbia.edu> 63 * Electrical Engineering Department 64 * Columbia University, New York City 65 */ 66 /* 67 * The Intel 21143 is the successor to the DEC 21140. It is basically 68 * the same as the 21140 but with a few new features. The 21143 supports 69 * three kinds of media attachments: 70 * 71 * o MII port, for 10Mbps and 100Mbps support and NWAY 72 * autonegotiation provided by an external PHY. 73 * o SYM port, for symbol mode 100Mbps support. 74 * o 10baseT port. 75 * o AUI/BNC port. 76 * 77 * The 100Mbps SYM port and 10baseT port can be used together in 78 * combination with the internal NWAY support to create a 10/100 79 * autosensing configuration. 80 * 81 * Note that not all tulip workalikes are handled in this driver: we only 82 * deal with those which are relatively well behaved. The Winbond is 83 * handled separately due to its different register offsets and the 84 * special handling needed for its various bugs. The PNIC is handled 85 * here, but I'm not thrilled about it. 86 * 87 * All of the workalike chips use some form of MII transceiver support 88 * with the exception of the Macronix chips, which also have a SYM port. 89 * The ASIX AX88140A is also documented to have a SYM port, but all 90 * the cards I've seen use an MII transceiver, probably because the 91 * AX88140A doesn't support internal NWAY. 92 */ 93 94 #include <sys/param.h> 95 #include <sys/endian.h> 96 #include <sys/systm.h> 97 #include <sys/sockio.h> 98 #include <sys/mbuf.h> 99 #include <sys/malloc.h> 100 #include <sys/kernel.h> 101 #include <sys/module.h> 102 #include <sys/socket.h> 103 #include <sys/sysctl.h> 104 105 #include <net/if.h> 106 #include <net/if_arp.h> 107 #include <net/ethernet.h> 108 #include <net/if_dl.h> 109 #include <net/if_media.h> 110 #include <net/if_types.h> 111 #include <net/if_vlan_var.h> 112 113 #include <net/bpf.h> 114 115 #include <machine/bus.h> 116 #include <machine/resource.h> 117 #include <sys/bus.h> 118 #include <sys/rman.h> 119 120 #include <dev/mii/mii.h> 121 #include <dev/mii/miivar.h> 122 123 #include <dev/pci/pcireg.h> 124 #include <dev/pci/pcivar.h> 125 126 #define DC_USEIOSPACE 127 #ifdef __alpha__ 128 #define SRM_MEDIA 129 #endif 130 131 #include <pci/if_dcreg.h> 132 133 #ifdef __sparc64__ 134 #include <dev/ofw/openfirm.h> 135 #include <machine/ofw_machdep.h> 136 #endif 137 138 MODULE_DEPEND(dc, pci, 1, 1, 1); 139 MODULE_DEPEND(dc, ether, 1, 1, 1); 140 MODULE_DEPEND(dc, miibus, 1, 1, 1); 141 142 /* "controller miibus0" required. See GENERIC if you get errors here. */ 143 #include "miibus_if.h" 144 145 /* 146 * Various supported device vendors/types and their names. 147 */ 148 static struct dc_type dc_devs[] = { 149 { DC_VENDORID_DEC, DC_DEVICEID_21143, 150 "Intel 21143 10/100BaseTX" }, 151 { DC_VENDORID_DAVICOM, DC_DEVICEID_DM9009, 152 "Davicom DM9009 10/100BaseTX" }, 153 { DC_VENDORID_DAVICOM, DC_DEVICEID_DM9100, 154 "Davicom DM9100 10/100BaseTX" }, 155 { DC_VENDORID_DAVICOM, DC_DEVICEID_DM9102, 156 "Davicom DM9102 10/100BaseTX" }, 157 { DC_VENDORID_DAVICOM, DC_DEVICEID_DM9102, 158 "Davicom DM9102A 10/100BaseTX" }, 159 { DC_VENDORID_ADMTEK, DC_DEVICEID_AL981, 160 "ADMtek AL981 10/100BaseTX" }, 161 { DC_VENDORID_ADMTEK, DC_DEVICEID_AN985, 162 "ADMtek AN985 10/100BaseTX" }, 163 { DC_VENDORID_ADMTEK, DC_DEVICEID_ADM9511, 164 "ADMtek ADM9511 10/100BaseTX" }, 165 { DC_VENDORID_ADMTEK, DC_DEVICEID_ADM9513, 166 "ADMtek ADM9513 10/100BaseTX" }, 167 { DC_VENDORID_ADMTEK, DC_DEVICEID_FA511, 168 "Netgear FA511 10/100BaseTX" }, 169 { DC_VENDORID_ASIX, DC_DEVICEID_AX88140A, 170 "ASIX AX88140A 10/100BaseTX" }, 171 { DC_VENDORID_ASIX, DC_DEVICEID_AX88140A, 172 "ASIX AX88141 10/100BaseTX" }, 173 { DC_VENDORID_MX, DC_DEVICEID_98713, 174 "Macronix 98713 10/100BaseTX" }, 175 { DC_VENDORID_MX, DC_DEVICEID_98713, 176 "Macronix 98713A 10/100BaseTX" }, 177 { DC_VENDORID_CP, DC_DEVICEID_98713_CP, 178 "Compex RL100-TX 10/100BaseTX" }, 179 { DC_VENDORID_CP, DC_DEVICEID_98713_CP, 180 "Compex RL100-TX 10/100BaseTX" }, 181 { DC_VENDORID_MX, DC_DEVICEID_987x5, 182 "Macronix 98715/98715A 10/100BaseTX" }, 183 { DC_VENDORID_MX, DC_DEVICEID_987x5, 184 "Macronix 98715AEC-C 10/100BaseTX" }, 185 { DC_VENDORID_MX, DC_DEVICEID_987x5, 186 "Macronix 98725 10/100BaseTX" }, 187 { DC_VENDORID_MX, DC_DEVICEID_98727, 188 "Macronix 98727/98732 10/100BaseTX" }, 189 { DC_VENDORID_LO, DC_DEVICEID_82C115, 190 "LC82C115 PNIC II 10/100BaseTX" }, 191 { DC_VENDORID_LO, DC_DEVICEID_82C168, 192 "82c168 PNIC 10/100BaseTX" }, 193 { DC_VENDORID_LO, DC_DEVICEID_82C168, 194 "82c169 PNIC 10/100BaseTX" }, 195 { DC_VENDORID_ACCTON, DC_DEVICEID_EN1217, 196 "Accton EN1217 10/100BaseTX" }, 197 { DC_VENDORID_ACCTON, DC_DEVICEID_EN2242, 198 "Accton EN2242 MiniPCI 10/100BaseTX" }, 199 { DC_VENDORID_XIRCOM, DC_DEVICEID_X3201, 200 "Xircom X3201 10/100BaseTX" }, 201 { DC_VENDORID_ABOCOM, DC_DEVICEID_FE2500, 202 "Abocom FE2500 10/100BaseTX" }, 203 { DC_VENDORID_ABOCOM, DC_DEVICEID_FE2500MX, 204 "Abocom FE2500MX 10/100BaseTX" }, 205 { DC_VENDORID_CONEXANT, DC_DEVICEID_RS7112, 206 "Conexant LANfinity MiniPCI 10/100BaseTX" }, 207 { DC_VENDORID_HAWKING, DC_DEVICEID_HAWKING_PN672TX, 208 "Hawking CB102 CardBus 10/100" }, 209 { DC_VENDORID_PLANEX, DC_DEVICEID_FNW3602T, 210 "PlaneX FNW-3602-T CardBus 10/100" }, 211 { DC_VENDORID_3COM, DC_DEVICEID_3CSOHOB, 212 "3Com OfficeConnect 10/100B" }, 213 { DC_VENDORID_MICROSOFT, DC_DEVICEID_MSMN120, 214 "Microsoft MN-120 CardBus 10/100" }, 215 { DC_VENDORID_MICROSOFT, DC_DEVICEID_MSMN130, 216 "Microsoft MN-130 10/100" }, 217 { DC_VENDORID_MICROSOFT, DC_DEVICEID_MSMN130_FAKE, 218 "Microsoft MN-130 10/100" }, 219 { 0, 0, NULL } 220 }; 221 222 static int dc_probe(device_t); 223 static int dc_attach(device_t); 224 static int dc_detach(device_t); 225 static int dc_suspend(device_t); 226 static int dc_resume(device_t); 227 static struct dc_type *dc_devtype(device_t); 228 static int dc_newbuf(struct dc_softc *, int, int); 229 static int dc_encap(struct dc_softc *, struct mbuf **); 230 static void dc_pnic_rx_bug_war(struct dc_softc *, int); 231 static int dc_rx_resync(struct dc_softc *); 232 static void dc_rxeof(struct dc_softc *); 233 static void dc_txeof(struct dc_softc *); 234 static void dc_tick(void *); 235 static void dc_tx_underrun(struct dc_softc *); 236 static void dc_intr(void *); 237 static void dc_start(struct ifnet *); 238 static int dc_ioctl(struct ifnet *, u_long, caddr_t); 239 static void dc_init(void *); 240 static void dc_stop(struct dc_softc *); 241 static void dc_watchdog(struct ifnet *); 242 static void dc_shutdown(device_t); 243 static int dc_ifmedia_upd(struct ifnet *); 244 static void dc_ifmedia_sts(struct ifnet *, struct ifmediareq *); 245 246 static void dc_delay(struct dc_softc *); 247 static void dc_eeprom_idle(struct dc_softc *); 248 static void dc_eeprom_putbyte(struct dc_softc *, int); 249 static void dc_eeprom_getword(struct dc_softc *, int, u_int16_t *); 250 static void dc_eeprom_getword_pnic(struct dc_softc *, int, u_int16_t *); 251 static void dc_eeprom_getword_xircom(struct dc_softc *, int, u_int16_t *); 252 static void dc_eeprom_width(struct dc_softc *); 253 static void dc_read_eeprom(struct dc_softc *, caddr_t, int, int, int); 254 255 static void dc_mii_writebit(struct dc_softc *, int); 256 static int dc_mii_readbit(struct dc_softc *); 257 static void dc_mii_sync(struct dc_softc *); 258 static void dc_mii_send(struct dc_softc *, u_int32_t, int); 259 static int dc_mii_readreg(struct dc_softc *, struct dc_mii_frame *); 260 static int dc_mii_writereg(struct dc_softc *, struct dc_mii_frame *); 261 static int dc_miibus_readreg(device_t, int, int); 262 static int dc_miibus_writereg(device_t, int, int, int); 263 static void dc_miibus_statchg(device_t); 264 static void dc_miibus_mediainit(device_t); 265 266 static void dc_setcfg(struct dc_softc *, int); 267 static uint32_t dc_mchash_le(struct dc_softc *, const uint8_t *); 268 static uint32_t dc_mchash_be(const uint8_t *); 269 static void dc_setfilt_21143(struct dc_softc *); 270 static void dc_setfilt_asix(struct dc_softc *); 271 static void dc_setfilt_admtek(struct dc_softc *); 272 static void dc_setfilt_xircom(struct dc_softc *); 273 274 static void dc_setfilt(struct dc_softc *); 275 276 static void dc_reset(struct dc_softc *); 277 static int dc_list_rx_init(struct dc_softc *); 278 static int dc_list_tx_init(struct dc_softc *); 279 280 static void dc_read_srom(struct dc_softc *, int); 281 static void dc_parse_21143_srom(struct dc_softc *); 282 static void dc_decode_leaf_sia(struct dc_softc *, struct dc_eblock_sia *); 283 static void dc_decode_leaf_mii(struct dc_softc *, struct dc_eblock_mii *); 284 static void dc_decode_leaf_sym(struct dc_softc *, struct dc_eblock_sym *); 285 static void dc_apply_fixup(struct dc_softc *, int); 286 287 static void dc_dma_map_txbuf(void *, bus_dma_segment_t *, int, bus_size_t, int); 288 static void dc_dma_map_rxbuf(void *, bus_dma_segment_t *, int, bus_size_t, int); 289 290 #ifdef DC_USEIOSPACE 291 #define DC_RES SYS_RES_IOPORT 292 #define DC_RID DC_PCI_CFBIO 293 #else 294 #define DC_RES SYS_RES_MEMORY 295 #define DC_RID DC_PCI_CFBMA 296 #endif 297 298 static device_method_t dc_methods[] = { 299 /* Device interface */ 300 DEVMETHOD(device_probe, dc_probe), 301 DEVMETHOD(device_attach, dc_attach), 302 DEVMETHOD(device_detach, dc_detach), 303 DEVMETHOD(device_suspend, dc_suspend), 304 DEVMETHOD(device_resume, dc_resume), 305 DEVMETHOD(device_shutdown, dc_shutdown), 306 307 /* bus interface */ 308 DEVMETHOD(bus_print_child, bus_generic_print_child), 309 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 310 311 /* MII interface */ 312 DEVMETHOD(miibus_readreg, dc_miibus_readreg), 313 DEVMETHOD(miibus_writereg, dc_miibus_writereg), 314 DEVMETHOD(miibus_statchg, dc_miibus_statchg), 315 DEVMETHOD(miibus_mediainit, dc_miibus_mediainit), 316 317 { 0, 0 } 318 }; 319 320 static driver_t dc_driver = { 321 "dc", 322 dc_methods, 323 sizeof(struct dc_softc) 324 }; 325 326 static devclass_t dc_devclass; 327 #ifdef __i386__ 328 static int dc_quick = 1; 329 SYSCTL_INT(_hw, OID_AUTO, dc_quick, CTLFLAG_RW, &dc_quick, 0, 330 "do not m_devget() in dc driver"); 331 #endif 332 333 DRIVER_MODULE(dc, cardbus, dc_driver, dc_devclass, 0, 0); 334 DRIVER_MODULE(dc, pci, dc_driver, dc_devclass, 0, 0); 335 DRIVER_MODULE(miibus, dc, miibus_driver, miibus_devclass, 0, 0); 336 337 #define DC_SETBIT(sc, reg, x) \ 338 CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) | (x)) 339 340 #define DC_CLRBIT(sc, reg, x) \ 341 CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) & ~(x)) 342 343 #define SIO_SET(x) DC_SETBIT(sc, DC_SIO, (x)) 344 #define SIO_CLR(x) DC_CLRBIT(sc, DC_SIO, (x)) 345 346 #define IS_MPSAFE 0 347 348 static void 349 dc_delay(struct dc_softc *sc) 350 { 351 int idx; 352 353 for (idx = (300 / 33) + 1; idx > 0; idx--) 354 CSR_READ_4(sc, DC_BUSCTL); 355 } 356 357 static void 358 dc_eeprom_width(struct dc_softc *sc) 359 { 360 int i; 361 362 /* Force EEPROM to idle state. */ 363 dc_eeprom_idle(sc); 364 365 /* Enter EEPROM access mode. */ 366 CSR_WRITE_4(sc, DC_SIO, DC_SIO_EESEL); 367 dc_delay(sc); 368 DC_SETBIT(sc, DC_SIO, DC_SIO_ROMCTL_READ); 369 dc_delay(sc); 370 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); 371 dc_delay(sc); 372 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CS); 373 dc_delay(sc); 374 375 for (i = 3; i--;) { 376 if (6 & (1 << i)) 377 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_DATAIN); 378 else 379 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_DATAIN); 380 dc_delay(sc); 381 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CLK); 382 dc_delay(sc); 383 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); 384 dc_delay(sc); 385 } 386 387 for (i = 1; i <= 12; i++) { 388 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CLK); 389 dc_delay(sc); 390 if (!(CSR_READ_4(sc, DC_SIO) & DC_SIO_EE_DATAOUT)) { 391 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); 392 dc_delay(sc); 393 break; 394 } 395 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); 396 dc_delay(sc); 397 } 398 399 /* Turn off EEPROM access mode. */ 400 dc_eeprom_idle(sc); 401 402 if (i < 4 || i > 12) 403 sc->dc_romwidth = 6; 404 else 405 sc->dc_romwidth = i; 406 407 /* Enter EEPROM access mode. */ 408 CSR_WRITE_4(sc, DC_SIO, DC_SIO_EESEL); 409 dc_delay(sc); 410 DC_SETBIT(sc, DC_SIO, DC_SIO_ROMCTL_READ); 411 dc_delay(sc); 412 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); 413 dc_delay(sc); 414 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CS); 415 dc_delay(sc); 416 417 /* Turn off EEPROM access mode. */ 418 dc_eeprom_idle(sc); 419 } 420 421 static void 422 dc_eeprom_idle(struct dc_softc *sc) 423 { 424 int i; 425 426 CSR_WRITE_4(sc, DC_SIO, DC_SIO_EESEL); 427 dc_delay(sc); 428 DC_SETBIT(sc, DC_SIO, DC_SIO_ROMCTL_READ); 429 dc_delay(sc); 430 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); 431 dc_delay(sc); 432 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CS); 433 dc_delay(sc); 434 435 for (i = 0; i < 25; i++) { 436 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); 437 dc_delay(sc); 438 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CLK); 439 dc_delay(sc); 440 } 441 442 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); 443 dc_delay(sc); 444 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CS); 445 dc_delay(sc); 446 CSR_WRITE_4(sc, DC_SIO, 0x00000000); 447 } 448 449 /* 450 * Send a read command and address to the EEPROM, check for ACK. 451 */ 452 static void 453 dc_eeprom_putbyte(struct dc_softc *sc, int addr) 454 { 455 int d, i; 456 457 d = DC_EECMD_READ >> 6; 458 for (i = 3; i--; ) { 459 if (d & (1 << i)) 460 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_DATAIN); 461 else 462 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_DATAIN); 463 dc_delay(sc); 464 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CLK); 465 dc_delay(sc); 466 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); 467 dc_delay(sc); 468 } 469 470 /* 471 * Feed in each bit and strobe the clock. 472 */ 473 for (i = sc->dc_romwidth; i--;) { 474 if (addr & (1 << i)) { 475 SIO_SET(DC_SIO_EE_DATAIN); 476 } else { 477 SIO_CLR(DC_SIO_EE_DATAIN); 478 } 479 dc_delay(sc); 480 SIO_SET(DC_SIO_EE_CLK); 481 dc_delay(sc); 482 SIO_CLR(DC_SIO_EE_CLK); 483 dc_delay(sc); 484 } 485 } 486 487 /* 488 * Read a word of data stored in the EEPROM at address 'addr.' 489 * The PNIC 82c168/82c169 has its own non-standard way to read 490 * the EEPROM. 491 */ 492 static void 493 dc_eeprom_getword_pnic(struct dc_softc *sc, int addr, u_int16_t *dest) 494 { 495 int i; 496 u_int32_t r; 497 498 CSR_WRITE_4(sc, DC_PN_SIOCTL, DC_PN_EEOPCODE_READ | addr); 499 500 for (i = 0; i < DC_TIMEOUT; i++) { 501 DELAY(1); 502 r = CSR_READ_4(sc, DC_SIO); 503 if (!(r & DC_PN_SIOCTL_BUSY)) { 504 *dest = (u_int16_t)(r & 0xFFFF); 505 return; 506 } 507 } 508 } 509 510 /* 511 * Read a word of data stored in the EEPROM at address 'addr.' 512 * The Xircom X3201 has its own non-standard way to read 513 * the EEPROM, too. 514 */ 515 static void 516 dc_eeprom_getword_xircom(struct dc_softc *sc, int addr, u_int16_t *dest) 517 { 518 519 SIO_SET(DC_SIO_ROMSEL | DC_SIO_ROMCTL_READ); 520 521 addr *= 2; 522 CSR_WRITE_4(sc, DC_ROM, addr | 0x160); 523 *dest = (u_int16_t)CSR_READ_4(sc, DC_SIO) & 0xff; 524 addr += 1; 525 CSR_WRITE_4(sc, DC_ROM, addr | 0x160); 526 *dest |= ((u_int16_t)CSR_READ_4(sc, DC_SIO) & 0xff) << 8; 527 528 SIO_CLR(DC_SIO_ROMSEL | DC_SIO_ROMCTL_READ); 529 } 530 531 /* 532 * Read a word of data stored in the EEPROM at address 'addr.' 533 */ 534 static void 535 dc_eeprom_getword(struct dc_softc *sc, int addr, u_int16_t *dest) 536 { 537 int i; 538 u_int16_t word = 0; 539 540 /* Force EEPROM to idle state. */ 541 dc_eeprom_idle(sc); 542 543 /* Enter EEPROM access mode. */ 544 CSR_WRITE_4(sc, DC_SIO, DC_SIO_EESEL); 545 dc_delay(sc); 546 DC_SETBIT(sc, DC_SIO, DC_SIO_ROMCTL_READ); 547 dc_delay(sc); 548 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); 549 dc_delay(sc); 550 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CS); 551 dc_delay(sc); 552 553 /* 554 * Send address of word we want to read. 555 */ 556 dc_eeprom_putbyte(sc, addr); 557 558 /* 559 * Start reading bits from EEPROM. 560 */ 561 for (i = 0x8000; i; i >>= 1) { 562 SIO_SET(DC_SIO_EE_CLK); 563 dc_delay(sc); 564 if (CSR_READ_4(sc, DC_SIO) & DC_SIO_EE_DATAOUT) 565 word |= i; 566 dc_delay(sc); 567 SIO_CLR(DC_SIO_EE_CLK); 568 dc_delay(sc); 569 } 570 571 /* Turn off EEPROM access mode. */ 572 dc_eeprom_idle(sc); 573 574 *dest = word; 575 } 576 577 /* 578 * Read a sequence of words from the EEPROM. 579 */ 580 static void 581 dc_read_eeprom(struct dc_softc *sc, caddr_t dest, int off, int cnt, int be) 582 { 583 int i; 584 u_int16_t word = 0, *ptr; 585 586 for (i = 0; i < cnt; i++) { 587 if (DC_IS_PNIC(sc)) 588 dc_eeprom_getword_pnic(sc, off + i, &word); 589 else if (DC_IS_XIRCOM(sc)) 590 dc_eeprom_getword_xircom(sc, off + i, &word); 591 else 592 dc_eeprom_getword(sc, off + i, &word); 593 ptr = (u_int16_t *)(dest + (i * 2)); 594 if (be) 595 *ptr = be16toh(word); 596 else 597 *ptr = le16toh(word); 598 } 599 } 600 601 /* 602 * The following two routines are taken from the Macronix 98713 603 * Application Notes pp.19-21. 604 */ 605 /* 606 * Write a bit to the MII bus. 607 */ 608 static void 609 dc_mii_writebit(struct dc_softc *sc, int bit) 610 { 611 612 if (bit) 613 CSR_WRITE_4(sc, DC_SIO, 614 DC_SIO_ROMCTL_WRITE | DC_SIO_MII_DATAOUT); 615 else 616 CSR_WRITE_4(sc, DC_SIO, DC_SIO_ROMCTL_WRITE); 617 618 DC_SETBIT(sc, DC_SIO, DC_SIO_MII_CLK); 619 DC_CLRBIT(sc, DC_SIO, DC_SIO_MII_CLK); 620 } 621 622 /* 623 * Read a bit from the MII bus. 624 */ 625 static int 626 dc_mii_readbit(struct dc_softc *sc) 627 { 628 629 CSR_WRITE_4(sc, DC_SIO, DC_SIO_ROMCTL_READ | DC_SIO_MII_DIR); 630 CSR_READ_4(sc, DC_SIO); 631 DC_SETBIT(sc, DC_SIO, DC_SIO_MII_CLK); 632 DC_CLRBIT(sc, DC_SIO, DC_SIO_MII_CLK); 633 if (CSR_READ_4(sc, DC_SIO) & DC_SIO_MII_DATAIN) 634 return (1); 635 636 return (0); 637 } 638 639 /* 640 * Sync the PHYs by setting data bit and strobing the clock 32 times. 641 */ 642 static void 643 dc_mii_sync(struct dc_softc *sc) 644 { 645 int i; 646 647 CSR_WRITE_4(sc, DC_SIO, DC_SIO_ROMCTL_WRITE); 648 649 for (i = 0; i < 32; i++) 650 dc_mii_writebit(sc, 1); 651 } 652 653 /* 654 * Clock a series of bits through the MII. 655 */ 656 static void 657 dc_mii_send(struct dc_softc *sc, u_int32_t bits, int cnt) 658 { 659 int i; 660 661 for (i = (0x1 << (cnt - 1)); i; i >>= 1) 662 dc_mii_writebit(sc, bits & i); 663 } 664 665 /* 666 * Read an PHY register through the MII. 667 */ 668 static int 669 dc_mii_readreg(struct dc_softc *sc, struct dc_mii_frame *frame) 670 { 671 int i, ack; 672 673 DC_LOCK(sc); 674 675 /* 676 * Set up frame for RX. 677 */ 678 frame->mii_stdelim = DC_MII_STARTDELIM; 679 frame->mii_opcode = DC_MII_READOP; 680 frame->mii_turnaround = 0; 681 frame->mii_data = 0; 682 683 /* 684 * Sync the PHYs. 685 */ 686 dc_mii_sync(sc); 687 688 /* 689 * Send command/address info. 690 */ 691 dc_mii_send(sc, frame->mii_stdelim, 2); 692 dc_mii_send(sc, frame->mii_opcode, 2); 693 dc_mii_send(sc, frame->mii_phyaddr, 5); 694 dc_mii_send(sc, frame->mii_regaddr, 5); 695 696 #ifdef notdef 697 /* Idle bit */ 698 dc_mii_writebit(sc, 1); 699 dc_mii_writebit(sc, 0); 700 #endif 701 702 /* Check for ack. */ 703 ack = dc_mii_readbit(sc); 704 705 /* 706 * Now try reading data bits. If the ack failed, we still 707 * need to clock through 16 cycles to keep the PHY(s) in sync. 708 */ 709 if (ack) { 710 for (i = 0; i < 16; i++) 711 dc_mii_readbit(sc); 712 goto fail; 713 } 714 715 for (i = 0x8000; i; i >>= 1) { 716 if (!ack) { 717 if (dc_mii_readbit(sc)) 718 frame->mii_data |= i; 719 } 720 } 721 722 fail: 723 724 dc_mii_writebit(sc, 0); 725 dc_mii_writebit(sc, 0); 726 727 DC_UNLOCK(sc); 728 729 if (ack) 730 return (1); 731 return (0); 732 } 733 734 /* 735 * Write to a PHY register through the MII. 736 */ 737 static int 738 dc_mii_writereg(struct dc_softc *sc, struct dc_mii_frame *frame) 739 { 740 741 DC_LOCK(sc); 742 /* 743 * Set up frame for TX. 744 */ 745 746 frame->mii_stdelim = DC_MII_STARTDELIM; 747 frame->mii_opcode = DC_MII_WRITEOP; 748 frame->mii_turnaround = DC_MII_TURNAROUND; 749 750 /* 751 * Sync the PHYs. 752 */ 753 dc_mii_sync(sc); 754 755 dc_mii_send(sc, frame->mii_stdelim, 2); 756 dc_mii_send(sc, frame->mii_opcode, 2); 757 dc_mii_send(sc, frame->mii_phyaddr, 5); 758 dc_mii_send(sc, frame->mii_regaddr, 5); 759 dc_mii_send(sc, frame->mii_turnaround, 2); 760 dc_mii_send(sc, frame->mii_data, 16); 761 762 /* Idle bit. */ 763 dc_mii_writebit(sc, 0); 764 dc_mii_writebit(sc, 0); 765 766 DC_UNLOCK(sc); 767 768 return (0); 769 } 770 771 static int 772 dc_miibus_readreg(device_t dev, int phy, int reg) 773 { 774 struct dc_mii_frame frame; 775 struct dc_softc *sc; 776 int i, rval, phy_reg = 0; 777 778 sc = device_get_softc(dev); 779 bzero(&frame, sizeof(frame)); 780 781 /* 782 * Note: both the AL981 and AN985 have internal PHYs, 783 * however the AL981 provides direct access to the PHY 784 * registers while the AN985 uses a serial MII interface. 785 * The AN985's MII interface is also buggy in that you 786 * can read from any MII address (0 to 31), but only address 1 787 * behaves normally. To deal with both cases, we pretend 788 * that the PHY is at MII address 1. 789 */ 790 if (DC_IS_ADMTEK(sc) && phy != DC_ADMTEK_PHYADDR) 791 return (0); 792 793 /* 794 * Note: the ukphy probes of the RS7112 report a PHY at 795 * MII address 0 (possibly HomePNA?) and 1 (ethernet) 796 * so we only respond to correct one. 797 */ 798 if (DC_IS_CONEXANT(sc) && phy != DC_CONEXANT_PHYADDR) 799 return (0); 800 801 if (sc->dc_pmode != DC_PMODE_MII) { 802 if (phy == (MII_NPHY - 1)) { 803 switch (reg) { 804 case MII_BMSR: 805 /* 806 * Fake something to make the probe 807 * code think there's a PHY here. 808 */ 809 return (BMSR_MEDIAMASK); 810 break; 811 case MII_PHYIDR1: 812 if (DC_IS_PNIC(sc)) 813 return (DC_VENDORID_LO); 814 return (DC_VENDORID_DEC); 815 break; 816 case MII_PHYIDR2: 817 if (DC_IS_PNIC(sc)) 818 return (DC_DEVICEID_82C168); 819 return (DC_DEVICEID_21143); 820 break; 821 default: 822 return (0); 823 break; 824 } 825 } else 826 return (0); 827 } 828 829 if (DC_IS_PNIC(sc)) { 830 CSR_WRITE_4(sc, DC_PN_MII, DC_PN_MIIOPCODE_READ | 831 (phy << 23) | (reg << 18)); 832 for (i = 0; i < DC_TIMEOUT; i++) { 833 DELAY(1); 834 rval = CSR_READ_4(sc, DC_PN_MII); 835 if (!(rval & DC_PN_MII_BUSY)) { 836 rval &= 0xFFFF; 837 return (rval == 0xFFFF ? 0 : rval); 838 } 839 } 840 return (0); 841 } 842 843 if (DC_IS_COMET(sc)) { 844 switch (reg) { 845 case MII_BMCR: 846 phy_reg = DC_AL_BMCR; 847 break; 848 case MII_BMSR: 849 phy_reg = DC_AL_BMSR; 850 break; 851 case MII_PHYIDR1: 852 phy_reg = DC_AL_VENID; 853 break; 854 case MII_PHYIDR2: 855 phy_reg = DC_AL_DEVID; 856 break; 857 case MII_ANAR: 858 phy_reg = DC_AL_ANAR; 859 break; 860 case MII_ANLPAR: 861 phy_reg = DC_AL_LPAR; 862 break; 863 case MII_ANER: 864 phy_reg = DC_AL_ANER; 865 break; 866 default: 867 device_printf(dev, "phy_read: bad phy register %x\n", 868 reg); 869 return (0); 870 break; 871 } 872 873 rval = CSR_READ_4(sc, phy_reg) & 0x0000FFFF; 874 875 if (rval == 0xFFFF) 876 return (0); 877 return (rval); 878 } 879 880 frame.mii_phyaddr = phy; 881 frame.mii_regaddr = reg; 882 if (sc->dc_type == DC_TYPE_98713) { 883 phy_reg = CSR_READ_4(sc, DC_NETCFG); 884 CSR_WRITE_4(sc, DC_NETCFG, phy_reg & ~DC_NETCFG_PORTSEL); 885 } 886 dc_mii_readreg(sc, &frame); 887 if (sc->dc_type == DC_TYPE_98713) 888 CSR_WRITE_4(sc, DC_NETCFG, phy_reg); 889 890 return (frame.mii_data); 891 } 892 893 static int 894 dc_miibus_writereg(device_t dev, int phy, int reg, int data) 895 { 896 struct dc_softc *sc; 897 struct dc_mii_frame frame; 898 int i, phy_reg = 0; 899 900 sc = device_get_softc(dev); 901 bzero(&frame, sizeof(frame)); 902 903 if (DC_IS_ADMTEK(sc) && phy != DC_ADMTEK_PHYADDR) 904 return (0); 905 906 if (DC_IS_CONEXANT(sc) && phy != DC_CONEXANT_PHYADDR) 907 return (0); 908 909 if (DC_IS_PNIC(sc)) { 910 CSR_WRITE_4(sc, DC_PN_MII, DC_PN_MIIOPCODE_WRITE | 911 (phy << 23) | (reg << 10) | data); 912 for (i = 0; i < DC_TIMEOUT; i++) { 913 if (!(CSR_READ_4(sc, DC_PN_MII) & DC_PN_MII_BUSY)) 914 break; 915 } 916 return (0); 917 } 918 919 if (DC_IS_COMET(sc)) { 920 switch (reg) { 921 case MII_BMCR: 922 phy_reg = DC_AL_BMCR; 923 break; 924 case MII_BMSR: 925 phy_reg = DC_AL_BMSR; 926 break; 927 case MII_PHYIDR1: 928 phy_reg = DC_AL_VENID; 929 break; 930 case MII_PHYIDR2: 931 phy_reg = DC_AL_DEVID; 932 break; 933 case MII_ANAR: 934 phy_reg = DC_AL_ANAR; 935 break; 936 case MII_ANLPAR: 937 phy_reg = DC_AL_LPAR; 938 break; 939 case MII_ANER: 940 phy_reg = DC_AL_ANER; 941 break; 942 default: 943 device_printf(dev, "phy_write: bad phy register %x\n", 944 reg); 945 return (0); 946 break; 947 } 948 949 CSR_WRITE_4(sc, phy_reg, data); 950 return (0); 951 } 952 953 frame.mii_phyaddr = phy; 954 frame.mii_regaddr = reg; 955 frame.mii_data = data; 956 957 if (sc->dc_type == DC_TYPE_98713) { 958 phy_reg = CSR_READ_4(sc, DC_NETCFG); 959 CSR_WRITE_4(sc, DC_NETCFG, phy_reg & ~DC_NETCFG_PORTSEL); 960 } 961 dc_mii_writereg(sc, &frame); 962 if (sc->dc_type == DC_TYPE_98713) 963 CSR_WRITE_4(sc, DC_NETCFG, phy_reg); 964 965 return (0); 966 } 967 968 static void 969 dc_miibus_statchg(device_t dev) 970 { 971 struct dc_softc *sc; 972 struct mii_data *mii; 973 struct ifmedia *ifm; 974 975 sc = device_get_softc(dev); 976 if (DC_IS_ADMTEK(sc)) 977 return; 978 979 mii = device_get_softc(sc->dc_miibus); 980 ifm = &mii->mii_media; 981 if (DC_IS_DAVICOM(sc) && 982 IFM_SUBTYPE(ifm->ifm_media) == IFM_HPNA_1) { 983 dc_setcfg(sc, ifm->ifm_media); 984 sc->dc_if_media = ifm->ifm_media; 985 } else { 986 dc_setcfg(sc, mii->mii_media_active); 987 sc->dc_if_media = mii->mii_media_active; 988 } 989 } 990 991 /* 992 * Special support for DM9102A cards with HomePNA PHYs. Note: 993 * with the Davicom DM9102A/DM9801 eval board that I have, it seems 994 * to be impossible to talk to the management interface of the DM9801 995 * PHY (its MDIO pin is not connected to anything). Consequently, 996 * the driver has to just 'know' about the additional mode and deal 997 * with it itself. *sigh* 998 */ 999 static void 1000 dc_miibus_mediainit(device_t dev) 1001 { 1002 struct dc_softc *sc; 1003 struct mii_data *mii; 1004 struct ifmedia *ifm; 1005 int rev; 1006 1007 rev = pci_read_config(dev, DC_PCI_CFRV, 4) & 0xFF; 1008 1009 sc = device_get_softc(dev); 1010 mii = device_get_softc(sc->dc_miibus); 1011 ifm = &mii->mii_media; 1012 1013 if (DC_IS_DAVICOM(sc) && rev >= DC_REVISION_DM9102A) 1014 ifmedia_add(ifm, IFM_ETHER | IFM_HPNA_1, 0, NULL); 1015 } 1016 1017 #define DC_BITS_512 9 1018 #define DC_BITS_128 7 1019 #define DC_BITS_64 6 1020 1021 static uint32_t 1022 dc_mchash_le(struct dc_softc *sc, const uint8_t *addr) 1023 { 1024 uint32_t crc; 1025 1026 /* Compute CRC for the address value. */ 1027 crc = ether_crc32_le(addr, ETHER_ADDR_LEN); 1028 1029 /* 1030 * The hash table on the PNIC II and the MX98715AEC-C/D/E 1031 * chips is only 128 bits wide. 1032 */ 1033 if (sc->dc_flags & DC_128BIT_HASH) 1034 return (crc & ((1 << DC_BITS_128) - 1)); 1035 1036 /* The hash table on the MX98715BEC is only 64 bits wide. */ 1037 if (sc->dc_flags & DC_64BIT_HASH) 1038 return (crc & ((1 << DC_BITS_64) - 1)); 1039 1040 /* Xircom's hash filtering table is different (read: weird) */ 1041 /* Xircom uses the LEAST significant bits */ 1042 if (DC_IS_XIRCOM(sc)) { 1043 if ((crc & 0x180) == 0x180) 1044 return ((crc & 0x0F) + (crc & 0x70) * 3 + (14 << 4)); 1045 else 1046 return ((crc & 0x1F) + ((crc >> 1) & 0xF0) * 3 + 1047 (12 << 4)); 1048 } 1049 1050 return (crc & ((1 << DC_BITS_512) - 1)); 1051 } 1052 1053 /* 1054 * Calculate CRC of a multicast group address, return the lower 6 bits. 1055 */ 1056 static uint32_t 1057 dc_mchash_be(const uint8_t *addr) 1058 { 1059 uint32_t crc; 1060 1061 /* Compute CRC for the address value. */ 1062 crc = ether_crc32_be(addr, ETHER_ADDR_LEN); 1063 1064 /* Return the filter bit position. */ 1065 return ((crc >> 26) & 0x0000003F); 1066 } 1067 1068 /* 1069 * 21143-style RX filter setup routine. Filter programming is done by 1070 * downloading a special setup frame into the TX engine. 21143, Macronix, 1071 * PNIC, PNIC II and Davicom chips are programmed this way. 1072 * 1073 * We always program the chip using 'hash perfect' mode, i.e. one perfect 1074 * address (our node address) and a 512-bit hash filter for multicast 1075 * frames. We also sneak the broadcast address into the hash filter since 1076 * we need that too. 1077 */ 1078 static void 1079 dc_setfilt_21143(struct dc_softc *sc) 1080 { 1081 struct dc_desc *sframe; 1082 u_int32_t h, *sp; 1083 struct ifmultiaddr *ifma; 1084 struct ifnet *ifp; 1085 int i; 1086 1087 ifp = sc->dc_ifp; 1088 1089 i = sc->dc_cdata.dc_tx_prod; 1090 DC_INC(sc->dc_cdata.dc_tx_prod, DC_TX_LIST_CNT); 1091 sc->dc_cdata.dc_tx_cnt++; 1092 sframe = &sc->dc_ldata->dc_tx_list[i]; 1093 sp = sc->dc_cdata.dc_sbuf; 1094 bzero(sp, DC_SFRAME_LEN); 1095 1096 sframe->dc_data = htole32(sc->dc_saddr); 1097 sframe->dc_ctl = htole32(DC_SFRAME_LEN | DC_TXCTL_SETUP | 1098 DC_TXCTL_TLINK | DC_FILTER_HASHPERF | DC_TXCTL_FINT); 1099 1100 sc->dc_cdata.dc_tx_chain[i] = (struct mbuf *)sc->dc_cdata.dc_sbuf; 1101 1102 /* If we want promiscuous mode, set the allframes bit. */ 1103 if (ifp->if_flags & IFF_PROMISC) 1104 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC); 1105 else 1106 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC); 1107 1108 if (ifp->if_flags & IFF_ALLMULTI) 1109 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI); 1110 else 1111 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI); 1112 1113 IF_ADDR_LOCK(ifp); 1114 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 1115 if (ifma->ifma_addr->sa_family != AF_LINK) 1116 continue; 1117 h = dc_mchash_le(sc, 1118 LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 1119 sp[h >> 4] |= htole32(1 << (h & 0xF)); 1120 } 1121 IF_ADDR_UNLOCK(ifp); 1122 1123 if (ifp->if_flags & IFF_BROADCAST) { 1124 h = dc_mchash_le(sc, ifp->if_broadcastaddr); 1125 sp[h >> 4] |= htole32(1 << (h & 0xF)); 1126 } 1127 1128 /* Set our MAC address */ 1129 sp[39] = DC_SP_MAC(((u_int16_t *)IFP2ENADDR(sc->dc_ifp))[0]); 1130 sp[40] = DC_SP_MAC(((u_int16_t *)IFP2ENADDR(sc->dc_ifp))[1]); 1131 sp[41] = DC_SP_MAC(((u_int16_t *)IFP2ENADDR(sc->dc_ifp))[2]); 1132 1133 sframe->dc_status = htole32(DC_TXSTAT_OWN); 1134 CSR_WRITE_4(sc, DC_TXSTART, 0xFFFFFFFF); 1135 1136 /* 1137 * The PNIC takes an exceedingly long time to process its 1138 * setup frame; wait 10ms after posting the setup frame 1139 * before proceeding, just so it has time to swallow its 1140 * medicine. 1141 */ 1142 DELAY(10000); 1143 1144 ifp->if_timer = 5; 1145 } 1146 1147 static void 1148 dc_setfilt_admtek(struct dc_softc *sc) 1149 { 1150 struct ifnet *ifp; 1151 struct ifmultiaddr *ifma; 1152 int h = 0; 1153 u_int32_t hashes[2] = { 0, 0 }; 1154 1155 ifp = sc->dc_ifp; 1156 1157 /* Init our MAC address. */ 1158 CSR_WRITE_4(sc, DC_AL_PAR0, *(u_int32_t *)(&IFP2ENADDR(sc->dc_ifp)[0])); 1159 CSR_WRITE_4(sc, DC_AL_PAR1, *(u_int32_t *)(&IFP2ENADDR(sc->dc_ifp)[4])); 1160 1161 /* If we want promiscuous mode, set the allframes bit. */ 1162 if (ifp->if_flags & IFF_PROMISC) 1163 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC); 1164 else 1165 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC); 1166 1167 if (ifp->if_flags & IFF_ALLMULTI) 1168 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI); 1169 else 1170 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI); 1171 1172 /* First, zot all the existing hash bits. */ 1173 CSR_WRITE_4(sc, DC_AL_MAR0, 0); 1174 CSR_WRITE_4(sc, DC_AL_MAR1, 0); 1175 1176 /* 1177 * If we're already in promisc or allmulti mode, we 1178 * don't have to bother programming the multicast filter. 1179 */ 1180 if (ifp->if_flags & (IFF_PROMISC | IFF_ALLMULTI)) 1181 return; 1182 1183 /* Now program new ones. */ 1184 IF_ADDR_LOCK(ifp); 1185 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 1186 if (ifma->ifma_addr->sa_family != AF_LINK) 1187 continue; 1188 if (DC_IS_CENTAUR(sc)) 1189 h = dc_mchash_le(sc, 1190 LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 1191 else 1192 h = dc_mchash_be( 1193 LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 1194 if (h < 32) 1195 hashes[0] |= (1 << h); 1196 else 1197 hashes[1] |= (1 << (h - 32)); 1198 } 1199 IF_ADDR_UNLOCK(ifp); 1200 1201 CSR_WRITE_4(sc, DC_AL_MAR0, hashes[0]); 1202 CSR_WRITE_4(sc, DC_AL_MAR1, hashes[1]); 1203 } 1204 1205 static void 1206 dc_setfilt_asix(struct dc_softc *sc) 1207 { 1208 struct ifnet *ifp; 1209 struct ifmultiaddr *ifma; 1210 int h = 0; 1211 u_int32_t hashes[2] = { 0, 0 }; 1212 1213 ifp = sc->dc_ifp; 1214 1215 /* Init our MAC address */ 1216 CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_PAR0); 1217 CSR_WRITE_4(sc, DC_AX_FILTDATA, 1218 *(u_int32_t *)(&IFP2ENADDR(sc->dc_ifp)[0])); 1219 CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_PAR1); 1220 CSR_WRITE_4(sc, DC_AX_FILTDATA, 1221 *(u_int32_t *)(&IFP2ENADDR(sc->dc_ifp)[4])); 1222 1223 /* If we want promiscuous mode, set the allframes bit. */ 1224 if (ifp->if_flags & IFF_PROMISC) 1225 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC); 1226 else 1227 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC); 1228 1229 if (ifp->if_flags & IFF_ALLMULTI) 1230 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI); 1231 else 1232 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI); 1233 1234 /* 1235 * The ASIX chip has a special bit to enable reception 1236 * of broadcast frames. 1237 */ 1238 if (ifp->if_flags & IFF_BROADCAST) 1239 DC_SETBIT(sc, DC_NETCFG, DC_AX_NETCFG_RX_BROAD); 1240 else 1241 DC_CLRBIT(sc, DC_NETCFG, DC_AX_NETCFG_RX_BROAD); 1242 1243 /* first, zot all the existing hash bits */ 1244 CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_MAR0); 1245 CSR_WRITE_4(sc, DC_AX_FILTDATA, 0); 1246 CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_MAR1); 1247 CSR_WRITE_4(sc, DC_AX_FILTDATA, 0); 1248 1249 /* 1250 * If we're already in promisc or allmulti mode, we 1251 * don't have to bother programming the multicast filter. 1252 */ 1253 if (ifp->if_flags & (IFF_PROMISC | IFF_ALLMULTI)) 1254 return; 1255 1256 /* now program new ones */ 1257 IF_ADDR_LOCK(ifp); 1258 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 1259 if (ifma->ifma_addr->sa_family != AF_LINK) 1260 continue; 1261 h = dc_mchash_be(LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 1262 if (h < 32) 1263 hashes[0] |= (1 << h); 1264 else 1265 hashes[1] |= (1 << (h - 32)); 1266 } 1267 IF_ADDR_UNLOCK(ifp); 1268 1269 CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_MAR0); 1270 CSR_WRITE_4(sc, DC_AX_FILTDATA, hashes[0]); 1271 CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_MAR1); 1272 CSR_WRITE_4(sc, DC_AX_FILTDATA, hashes[1]); 1273 } 1274 1275 static void 1276 dc_setfilt_xircom(struct dc_softc *sc) 1277 { 1278 struct ifnet *ifp; 1279 struct ifmultiaddr *ifma; 1280 struct dc_desc *sframe; 1281 u_int32_t h, *sp; 1282 int i; 1283 1284 ifp = sc->dc_ifp; 1285 DC_CLRBIT(sc, DC_NETCFG, (DC_NETCFG_TX_ON | DC_NETCFG_RX_ON)); 1286 1287 i = sc->dc_cdata.dc_tx_prod; 1288 DC_INC(sc->dc_cdata.dc_tx_prod, DC_TX_LIST_CNT); 1289 sc->dc_cdata.dc_tx_cnt++; 1290 sframe = &sc->dc_ldata->dc_tx_list[i]; 1291 sp = sc->dc_cdata.dc_sbuf; 1292 bzero(sp, DC_SFRAME_LEN); 1293 1294 sframe->dc_data = htole32(sc->dc_saddr); 1295 sframe->dc_ctl = htole32(DC_SFRAME_LEN | DC_TXCTL_SETUP | 1296 DC_TXCTL_TLINK | DC_FILTER_HASHPERF | DC_TXCTL_FINT); 1297 1298 sc->dc_cdata.dc_tx_chain[i] = (struct mbuf *)sc->dc_cdata.dc_sbuf; 1299 1300 /* If we want promiscuous mode, set the allframes bit. */ 1301 if (ifp->if_flags & IFF_PROMISC) 1302 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC); 1303 else 1304 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC); 1305 1306 if (ifp->if_flags & IFF_ALLMULTI) 1307 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI); 1308 else 1309 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI); 1310 1311 IF_ADDR_LOCK(ifp); 1312 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 1313 if (ifma->ifma_addr->sa_family != AF_LINK) 1314 continue; 1315 h = dc_mchash_le(sc, 1316 LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 1317 sp[h >> 4] |= htole32(1 << (h & 0xF)); 1318 } 1319 IF_ADDR_UNLOCK(ifp); 1320 1321 if (ifp->if_flags & IFF_BROADCAST) { 1322 h = dc_mchash_le(sc, ifp->if_broadcastaddr); 1323 sp[h >> 4] |= htole32(1 << (h & 0xF)); 1324 } 1325 1326 /* Set our MAC address */ 1327 sp[0] = DC_SP_MAC(((u_int16_t *)IFP2ENADDR(sc->dc_ifp))[0]); 1328 sp[1] = DC_SP_MAC(((u_int16_t *)IFP2ENADDR(sc->dc_ifp))[1]); 1329 sp[2] = DC_SP_MAC(((u_int16_t *)IFP2ENADDR(sc->dc_ifp))[2]); 1330 1331 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_TX_ON); 1332 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_ON); 1333 ifp->if_drv_flags |= IFF_DRV_RUNNING; 1334 sframe->dc_status = htole32(DC_TXSTAT_OWN); 1335 CSR_WRITE_4(sc, DC_TXSTART, 0xFFFFFFFF); 1336 1337 /* 1338 * Wait some time... 1339 */ 1340 DELAY(1000); 1341 1342 ifp->if_timer = 5; 1343 } 1344 1345 static void 1346 dc_setfilt(struct dc_softc *sc) 1347 { 1348 1349 if (DC_IS_INTEL(sc) || DC_IS_MACRONIX(sc) || DC_IS_PNIC(sc) || 1350 DC_IS_PNICII(sc) || DC_IS_DAVICOM(sc) || DC_IS_CONEXANT(sc)) 1351 dc_setfilt_21143(sc); 1352 1353 if (DC_IS_ASIX(sc)) 1354 dc_setfilt_asix(sc); 1355 1356 if (DC_IS_ADMTEK(sc)) 1357 dc_setfilt_admtek(sc); 1358 1359 if (DC_IS_XIRCOM(sc)) 1360 dc_setfilt_xircom(sc); 1361 } 1362 1363 /* 1364 * In order to fiddle with the 'full-duplex' and '100Mbps' bits in 1365 * the netconfig register, we first have to put the transmit and/or 1366 * receive logic in the idle state. 1367 */ 1368 static void 1369 dc_setcfg(struct dc_softc *sc, int media) 1370 { 1371 int i, restart = 0, watchdogreg; 1372 u_int32_t isr; 1373 1374 if (IFM_SUBTYPE(media) == IFM_NONE) 1375 return; 1376 1377 if (CSR_READ_4(sc, DC_NETCFG) & (DC_NETCFG_TX_ON | DC_NETCFG_RX_ON)) { 1378 restart = 1; 1379 DC_CLRBIT(sc, DC_NETCFG, (DC_NETCFG_TX_ON | DC_NETCFG_RX_ON)); 1380 1381 for (i = 0; i < DC_TIMEOUT; i++) { 1382 isr = CSR_READ_4(sc, DC_ISR); 1383 if (isr & DC_ISR_TX_IDLE && 1384 ((isr & DC_ISR_RX_STATE) == DC_RXSTATE_STOPPED || 1385 (isr & DC_ISR_RX_STATE) == DC_RXSTATE_WAIT)) 1386 break; 1387 DELAY(10); 1388 } 1389 1390 if (i == DC_TIMEOUT) 1391 if_printf(sc->dc_ifp, 1392 "failed to force tx and rx to idle state\n"); 1393 } 1394 1395 if (IFM_SUBTYPE(media) == IFM_100_TX) { 1396 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_SPEEDSEL); 1397 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_HEARTBEAT); 1398 if (sc->dc_pmode == DC_PMODE_MII) { 1399 if (DC_IS_INTEL(sc)) { 1400 /* There's a write enable bit here that reads as 1. */ 1401 watchdogreg = CSR_READ_4(sc, DC_WATCHDOG); 1402 watchdogreg &= ~DC_WDOG_CTLWREN; 1403 watchdogreg |= DC_WDOG_JABBERDIS; 1404 CSR_WRITE_4(sc, DC_WATCHDOG, watchdogreg); 1405 } else { 1406 DC_SETBIT(sc, DC_WATCHDOG, DC_WDOG_JABBERDIS); 1407 } 1408 DC_CLRBIT(sc, DC_NETCFG, (DC_NETCFG_PCS | 1409 DC_NETCFG_PORTSEL | DC_NETCFG_SCRAMBLER)); 1410 if (sc->dc_type == DC_TYPE_98713) 1411 DC_SETBIT(sc, DC_NETCFG, (DC_NETCFG_PCS | 1412 DC_NETCFG_SCRAMBLER)); 1413 if (!DC_IS_DAVICOM(sc)) 1414 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL); 1415 DC_CLRBIT(sc, DC_10BTCTRL, 0xFFFF); 1416 if (DC_IS_INTEL(sc)) 1417 dc_apply_fixup(sc, IFM_AUTO); 1418 } else { 1419 if (DC_IS_PNIC(sc)) { 1420 DC_PN_GPIO_SETBIT(sc, DC_PN_GPIO_SPEEDSEL); 1421 DC_PN_GPIO_SETBIT(sc, DC_PN_GPIO_100TX_LOOP); 1422 DC_SETBIT(sc, DC_PN_NWAY, DC_PN_NWAY_SPEEDSEL); 1423 } 1424 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL); 1425 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PCS); 1426 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_SCRAMBLER); 1427 if (DC_IS_INTEL(sc)) 1428 dc_apply_fixup(sc, 1429 (media & IFM_GMASK) == IFM_FDX ? 1430 IFM_100_TX | IFM_FDX : IFM_100_TX); 1431 } 1432 } 1433 1434 if (IFM_SUBTYPE(media) == IFM_10_T) { 1435 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_SPEEDSEL); 1436 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_HEARTBEAT); 1437 if (sc->dc_pmode == DC_PMODE_MII) { 1438 /* There's a write enable bit here that reads as 1. */ 1439 if (DC_IS_INTEL(sc)) { 1440 watchdogreg = CSR_READ_4(sc, DC_WATCHDOG); 1441 watchdogreg &= ~DC_WDOG_CTLWREN; 1442 watchdogreg |= DC_WDOG_JABBERDIS; 1443 CSR_WRITE_4(sc, DC_WATCHDOG, watchdogreg); 1444 } else { 1445 DC_SETBIT(sc, DC_WATCHDOG, DC_WDOG_JABBERDIS); 1446 } 1447 DC_CLRBIT(sc, DC_NETCFG, (DC_NETCFG_PCS | 1448 DC_NETCFG_PORTSEL | DC_NETCFG_SCRAMBLER)); 1449 if (sc->dc_type == DC_TYPE_98713) 1450 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PCS); 1451 if (!DC_IS_DAVICOM(sc)) 1452 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL); 1453 DC_CLRBIT(sc, DC_10BTCTRL, 0xFFFF); 1454 if (DC_IS_INTEL(sc)) 1455 dc_apply_fixup(sc, IFM_AUTO); 1456 } else { 1457 if (DC_IS_PNIC(sc)) { 1458 DC_PN_GPIO_CLRBIT(sc, DC_PN_GPIO_SPEEDSEL); 1459 DC_PN_GPIO_SETBIT(sc, DC_PN_GPIO_100TX_LOOP); 1460 DC_CLRBIT(sc, DC_PN_NWAY, DC_PN_NWAY_SPEEDSEL); 1461 } 1462 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL); 1463 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_PCS); 1464 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_SCRAMBLER); 1465 if (DC_IS_INTEL(sc)) { 1466 DC_CLRBIT(sc, DC_SIARESET, DC_SIA_RESET); 1467 DC_CLRBIT(sc, DC_10BTCTRL, 0xFFFF); 1468 if ((media & IFM_GMASK) == IFM_FDX) 1469 DC_SETBIT(sc, DC_10BTCTRL, 0x7F3D); 1470 else 1471 DC_SETBIT(sc, DC_10BTCTRL, 0x7F3F); 1472 DC_SETBIT(sc, DC_SIARESET, DC_SIA_RESET); 1473 DC_CLRBIT(sc, DC_10BTCTRL, 1474 DC_TCTL_AUTONEGENBL); 1475 dc_apply_fixup(sc, 1476 (media & IFM_GMASK) == IFM_FDX ? 1477 IFM_10_T | IFM_FDX : IFM_10_T); 1478 DELAY(20000); 1479 } 1480 } 1481 } 1482 1483 /* 1484 * If this is a Davicom DM9102A card with a DM9801 HomePNA 1485 * PHY and we want HomePNA mode, set the portsel bit to turn 1486 * on the external MII port. 1487 */ 1488 if (DC_IS_DAVICOM(sc)) { 1489 if (IFM_SUBTYPE(media) == IFM_HPNA_1) { 1490 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL); 1491 sc->dc_link = 1; 1492 } else { 1493 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL); 1494 } 1495 } 1496 1497 if ((media & IFM_GMASK) == IFM_FDX) { 1498 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_FULLDUPLEX); 1499 if (sc->dc_pmode == DC_PMODE_SYM && DC_IS_PNIC(sc)) 1500 DC_SETBIT(sc, DC_PN_NWAY, DC_PN_NWAY_DUPLEX); 1501 } else { 1502 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_FULLDUPLEX); 1503 if (sc->dc_pmode == DC_PMODE_SYM && DC_IS_PNIC(sc)) 1504 DC_CLRBIT(sc, DC_PN_NWAY, DC_PN_NWAY_DUPLEX); 1505 } 1506 1507 if (restart) 1508 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_TX_ON | DC_NETCFG_RX_ON); 1509 } 1510 1511 static void 1512 dc_reset(struct dc_softc *sc) 1513 { 1514 int i; 1515 1516 DC_SETBIT(sc, DC_BUSCTL, DC_BUSCTL_RESET); 1517 1518 for (i = 0; i < DC_TIMEOUT; i++) { 1519 DELAY(10); 1520 if (!(CSR_READ_4(sc, DC_BUSCTL) & DC_BUSCTL_RESET)) 1521 break; 1522 } 1523 1524 if (DC_IS_ASIX(sc) || DC_IS_ADMTEK(sc) || DC_IS_CONEXANT(sc) || 1525 DC_IS_XIRCOM(sc) || DC_IS_INTEL(sc)) { 1526 DELAY(10000); 1527 DC_CLRBIT(sc, DC_BUSCTL, DC_BUSCTL_RESET); 1528 i = 0; 1529 } 1530 1531 if (i == DC_TIMEOUT) 1532 if_printf(sc->dc_ifp, "reset never completed!\n"); 1533 1534 /* Wait a little while for the chip to get its brains in order. */ 1535 DELAY(1000); 1536 1537 CSR_WRITE_4(sc, DC_IMR, 0x00000000); 1538 CSR_WRITE_4(sc, DC_BUSCTL, 0x00000000); 1539 CSR_WRITE_4(sc, DC_NETCFG, 0x00000000); 1540 1541 /* 1542 * Bring the SIA out of reset. In some cases, it looks 1543 * like failing to unreset the SIA soon enough gets it 1544 * into a state where it will never come out of reset 1545 * until we reset the whole chip again. 1546 */ 1547 if (DC_IS_INTEL(sc)) { 1548 DC_SETBIT(sc, DC_SIARESET, DC_SIA_RESET); 1549 CSR_WRITE_4(sc, DC_10BTCTRL, 0); 1550 CSR_WRITE_4(sc, DC_WATCHDOG, 0); 1551 } 1552 } 1553 1554 static struct dc_type * 1555 dc_devtype(device_t dev) 1556 { 1557 struct dc_type *t; 1558 u_int32_t rev; 1559 1560 t = dc_devs; 1561 1562 while (t->dc_name != NULL) { 1563 if ((pci_get_vendor(dev) == t->dc_vid) && 1564 (pci_get_device(dev) == t->dc_did)) { 1565 /* Check the PCI revision */ 1566 rev = pci_read_config(dev, DC_PCI_CFRV, 4) & 0xFF; 1567 if (t->dc_did == DC_DEVICEID_98713 && 1568 rev >= DC_REVISION_98713A) 1569 t++; 1570 if (t->dc_did == DC_DEVICEID_98713_CP && 1571 rev >= DC_REVISION_98713A) 1572 t++; 1573 if (t->dc_did == DC_DEVICEID_987x5 && 1574 rev >= DC_REVISION_98715AEC_C) 1575 t++; 1576 if (t->dc_did == DC_DEVICEID_987x5 && 1577 rev >= DC_REVISION_98725) 1578 t++; 1579 if (t->dc_did == DC_DEVICEID_AX88140A && 1580 rev >= DC_REVISION_88141) 1581 t++; 1582 if (t->dc_did == DC_DEVICEID_82C168 && 1583 rev >= DC_REVISION_82C169) 1584 t++; 1585 if (t->dc_did == DC_DEVICEID_DM9102 && 1586 rev >= DC_REVISION_DM9102A) 1587 t++; 1588 /* 1589 * The Microsoft MN-130 has a device ID of 0x0002, 1590 * which happens to be the same as the PNIC 82c168. 1591 * To keep dc_attach() from getting confused, we 1592 * pretend its ID is something different. 1593 * XXX: ideally, dc_attach() should be checking 1594 * vendorid+deviceid together to avoid such 1595 * collisions. 1596 */ 1597 if (t->dc_vid == DC_VENDORID_MICROSOFT && 1598 t->dc_did == DC_DEVICEID_MSMN130) 1599 t++; 1600 return (t); 1601 } 1602 t++; 1603 } 1604 1605 return (NULL); 1606 } 1607 1608 /* 1609 * Probe for a 21143 or clone chip. Check the PCI vendor and device 1610 * IDs against our list and return a device name if we find a match. 1611 * We do a little bit of extra work to identify the exact type of 1612 * chip. The MX98713 and MX98713A have the same PCI vendor/device ID, 1613 * but different revision IDs. The same is true for 98715/98715A 1614 * chips and the 98725, as well as the ASIX and ADMtek chips. In some 1615 * cases, the exact chip revision affects driver behavior. 1616 */ 1617 static int 1618 dc_probe(device_t dev) 1619 { 1620 struct dc_type *t; 1621 1622 t = dc_devtype(dev); 1623 1624 if (t != NULL) { 1625 device_set_desc(dev, t->dc_name); 1626 return (BUS_PROBE_DEFAULT); 1627 } 1628 1629 return (ENXIO); 1630 } 1631 1632 static void 1633 dc_apply_fixup(struct dc_softc *sc, int media) 1634 { 1635 struct dc_mediainfo *m; 1636 u_int8_t *p; 1637 int i; 1638 u_int32_t reg; 1639 1640 m = sc->dc_mi; 1641 1642 while (m != NULL) { 1643 if (m->dc_media == media) 1644 break; 1645 m = m->dc_next; 1646 } 1647 1648 if (m == NULL) 1649 return; 1650 1651 for (i = 0, p = m->dc_reset_ptr; i < m->dc_reset_len; i++, p += 2) { 1652 reg = (p[0] | (p[1] << 8)) << 16; 1653 CSR_WRITE_4(sc, DC_WATCHDOG, reg); 1654 } 1655 1656 for (i = 0, p = m->dc_gp_ptr; i < m->dc_gp_len; i++, p += 2) { 1657 reg = (p[0] | (p[1] << 8)) << 16; 1658 CSR_WRITE_4(sc, DC_WATCHDOG, reg); 1659 } 1660 } 1661 1662 static void 1663 dc_decode_leaf_sia(struct dc_softc *sc, struct dc_eblock_sia *l) 1664 { 1665 struct dc_mediainfo *m; 1666 1667 m = malloc(sizeof(struct dc_mediainfo), M_DEVBUF, M_NOWAIT | M_ZERO); 1668 switch (l->dc_sia_code & ~DC_SIA_CODE_EXT) { 1669 case DC_SIA_CODE_10BT: 1670 m->dc_media = IFM_10_T; 1671 break; 1672 case DC_SIA_CODE_10BT_FDX: 1673 m->dc_media = IFM_10_T | IFM_FDX; 1674 break; 1675 case DC_SIA_CODE_10B2: 1676 m->dc_media = IFM_10_2; 1677 break; 1678 case DC_SIA_CODE_10B5: 1679 m->dc_media = IFM_10_5; 1680 break; 1681 default: 1682 break; 1683 } 1684 1685 /* 1686 * We need to ignore CSR13, CSR14, CSR15 for SIA mode. 1687 * Things apparently already work for cards that do 1688 * supply Media Specific Data. 1689 */ 1690 if (l->dc_sia_code & DC_SIA_CODE_EXT) { 1691 m->dc_gp_len = 2; 1692 m->dc_gp_ptr = 1693 (u_int8_t *)&l->dc_un.dc_sia_ext.dc_sia_gpio_ctl; 1694 } else { 1695 m->dc_gp_len = 2; 1696 m->dc_gp_ptr = 1697 (u_int8_t *)&l->dc_un.dc_sia_noext.dc_sia_gpio_ctl; 1698 } 1699 1700 m->dc_next = sc->dc_mi; 1701 sc->dc_mi = m; 1702 1703 sc->dc_pmode = DC_PMODE_SIA; 1704 } 1705 1706 static void 1707 dc_decode_leaf_sym(struct dc_softc *sc, struct dc_eblock_sym *l) 1708 { 1709 struct dc_mediainfo *m; 1710 1711 m = malloc(sizeof(struct dc_mediainfo), M_DEVBUF, M_NOWAIT | M_ZERO); 1712 if (l->dc_sym_code == DC_SYM_CODE_100BT) 1713 m->dc_media = IFM_100_TX; 1714 1715 if (l->dc_sym_code == DC_SYM_CODE_100BT_FDX) 1716 m->dc_media = IFM_100_TX | IFM_FDX; 1717 1718 m->dc_gp_len = 2; 1719 m->dc_gp_ptr = (u_int8_t *)&l->dc_sym_gpio_ctl; 1720 1721 m->dc_next = sc->dc_mi; 1722 sc->dc_mi = m; 1723 1724 sc->dc_pmode = DC_PMODE_SYM; 1725 } 1726 1727 static void 1728 dc_decode_leaf_mii(struct dc_softc *sc, struct dc_eblock_mii *l) 1729 { 1730 struct dc_mediainfo *m; 1731 u_int8_t *p; 1732 1733 m = malloc(sizeof(struct dc_mediainfo), M_DEVBUF, M_NOWAIT | M_ZERO); 1734 /* We abuse IFM_AUTO to represent MII. */ 1735 m->dc_media = IFM_AUTO; 1736 m->dc_gp_len = l->dc_gpr_len; 1737 1738 p = (u_int8_t *)l; 1739 p += sizeof(struct dc_eblock_mii); 1740 m->dc_gp_ptr = p; 1741 p += 2 * l->dc_gpr_len; 1742 m->dc_reset_len = *p; 1743 p++; 1744 m->dc_reset_ptr = p; 1745 1746 m->dc_next = sc->dc_mi; 1747 sc->dc_mi = m; 1748 } 1749 1750 static void 1751 dc_read_srom(struct dc_softc *sc, int bits) 1752 { 1753 int size; 1754 1755 size = 2 << bits; 1756 sc->dc_srom = malloc(size, M_DEVBUF, M_NOWAIT); 1757 dc_read_eeprom(sc, (caddr_t)sc->dc_srom, 0, (size / 2), 0); 1758 } 1759 1760 static void 1761 dc_parse_21143_srom(struct dc_softc *sc) 1762 { 1763 struct dc_leaf_hdr *lhdr; 1764 struct dc_eblock_hdr *hdr; 1765 int have_mii, i, loff; 1766 char *ptr; 1767 1768 have_mii = 0; 1769 loff = sc->dc_srom[27]; 1770 lhdr = (struct dc_leaf_hdr *)&(sc->dc_srom[loff]); 1771 1772 ptr = (char *)lhdr; 1773 ptr += sizeof(struct dc_leaf_hdr) - 1; 1774 /* 1775 * Look if we got a MII media block. 1776 */ 1777 for (i = 0; i < lhdr->dc_mcnt; i++) { 1778 hdr = (struct dc_eblock_hdr *)ptr; 1779 if (hdr->dc_type == DC_EBLOCK_MII) 1780 have_mii++; 1781 1782 ptr += (hdr->dc_len & 0x7F); 1783 ptr++; 1784 } 1785 1786 /* 1787 * Do the same thing again. Only use SIA and SYM media 1788 * blocks if no MII media block is available. 1789 */ 1790 ptr = (char *)lhdr; 1791 ptr += sizeof(struct dc_leaf_hdr) - 1; 1792 for (i = 0; i < lhdr->dc_mcnt; i++) { 1793 hdr = (struct dc_eblock_hdr *)ptr; 1794 switch (hdr->dc_type) { 1795 case DC_EBLOCK_MII: 1796 dc_decode_leaf_mii(sc, (struct dc_eblock_mii *)hdr); 1797 break; 1798 case DC_EBLOCK_SIA: 1799 if (! have_mii) 1800 dc_decode_leaf_sia(sc, 1801 (struct dc_eblock_sia *)hdr); 1802 break; 1803 case DC_EBLOCK_SYM: 1804 if (! have_mii) 1805 dc_decode_leaf_sym(sc, 1806 (struct dc_eblock_sym *)hdr); 1807 break; 1808 default: 1809 /* Don't care. Yet. */ 1810 break; 1811 } 1812 ptr += (hdr->dc_len & 0x7F); 1813 ptr++; 1814 } 1815 } 1816 1817 static void 1818 dc_dma_map_addr(void *arg, bus_dma_segment_t *segs, int nseg, int error) 1819 { 1820 u_int32_t *paddr; 1821 1822 KASSERT(nseg == 1, ("wrong number of segments, should be 1")); 1823 paddr = arg; 1824 *paddr = segs->ds_addr; 1825 } 1826 1827 /* 1828 * Attach the interface. Allocate softc structures, do ifmedia 1829 * setup and ethernet/BPF attach. 1830 */ 1831 static int 1832 dc_attach(device_t dev) 1833 { 1834 int tmp = 0; 1835 u_char eaddr[ETHER_ADDR_LEN]; 1836 u_int32_t command; 1837 struct dc_softc *sc; 1838 struct ifnet *ifp; 1839 u_int32_t revision; 1840 int error = 0, rid, mac_offset; 1841 int i; 1842 u_int8_t *mac; 1843 1844 sc = device_get_softc(dev); 1845 1846 mtx_init(&sc->dc_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 1847 MTX_DEF | MTX_RECURSE); 1848 1849 /* 1850 * Map control/status registers. 1851 */ 1852 pci_enable_busmaster(dev); 1853 1854 rid = DC_RID; 1855 sc->dc_res = bus_alloc_resource_any(dev, DC_RES, &rid, RF_ACTIVE); 1856 1857 if (sc->dc_res == NULL) { 1858 device_printf(dev, "couldn't map ports/memory\n"); 1859 error = ENXIO; 1860 goto fail; 1861 } 1862 1863 sc->dc_btag = rman_get_bustag(sc->dc_res); 1864 sc->dc_bhandle = rman_get_bushandle(sc->dc_res); 1865 1866 /* Allocate interrupt. */ 1867 rid = 0; 1868 sc->dc_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 1869 RF_SHAREABLE | RF_ACTIVE); 1870 1871 if (sc->dc_irq == NULL) { 1872 device_printf(dev, "couldn't map interrupt\n"); 1873 error = ENXIO; 1874 goto fail; 1875 } 1876 1877 /* Need this info to decide on a chip type. */ 1878 sc->dc_info = dc_devtype(dev); 1879 revision = pci_read_config(dev, DC_PCI_CFRV, 4) & 0x000000FF; 1880 1881 /* Get the eeprom width, but PNIC and XIRCOM have diff eeprom */ 1882 if (sc->dc_info->dc_did != DC_DEVICEID_82C168 && 1883 sc->dc_info->dc_did != DC_DEVICEID_X3201) 1884 dc_eeprom_width(sc); 1885 1886 switch (sc->dc_info->dc_did) { 1887 case DC_DEVICEID_21143: 1888 sc->dc_type = DC_TYPE_21143; 1889 sc->dc_flags |= DC_TX_POLL | DC_TX_USE_TX_INTR; 1890 sc->dc_flags |= DC_REDUCED_MII_POLL; 1891 /* Save EEPROM contents so we can parse them later. */ 1892 dc_read_srom(sc, sc->dc_romwidth); 1893 break; 1894 case DC_DEVICEID_DM9009: 1895 case DC_DEVICEID_DM9100: 1896 case DC_DEVICEID_DM9102: 1897 sc->dc_type = DC_TYPE_DM9102; 1898 sc->dc_flags |= DC_TX_COALESCE | DC_TX_INTR_ALWAYS; 1899 sc->dc_flags |= DC_REDUCED_MII_POLL | DC_TX_STORENFWD; 1900 sc->dc_flags |= DC_TX_ALIGN; 1901 sc->dc_pmode = DC_PMODE_MII; 1902 /* Increase the latency timer value. */ 1903 command = pci_read_config(dev, DC_PCI_CFLT, 4); 1904 command &= 0xFFFF00FF; 1905 command |= 0x00008000; 1906 pci_write_config(dev, DC_PCI_CFLT, command, 4); 1907 break; 1908 case DC_DEVICEID_AL981: 1909 sc->dc_type = DC_TYPE_AL981; 1910 sc->dc_flags |= DC_TX_USE_TX_INTR; 1911 sc->dc_flags |= DC_TX_ADMTEK_WAR; 1912 sc->dc_pmode = DC_PMODE_MII; 1913 dc_read_srom(sc, sc->dc_romwidth); 1914 break; 1915 case DC_DEVICEID_AN985: 1916 case DC_DEVICEID_ADM9511: 1917 case DC_DEVICEID_ADM9513: 1918 case DC_DEVICEID_FA511: 1919 case DC_DEVICEID_FE2500: 1920 case DC_DEVICEID_EN2242: 1921 case DC_DEVICEID_HAWKING_PN672TX: 1922 case DC_DEVICEID_3CSOHOB: 1923 case DC_DEVICEID_MSMN120: 1924 case DC_DEVICEID_MSMN130_FAKE: /* XXX avoid collision with PNIC*/ 1925 sc->dc_type = DC_TYPE_AN985; 1926 sc->dc_flags |= DC_64BIT_HASH; 1927 sc->dc_flags |= DC_TX_USE_TX_INTR; 1928 sc->dc_flags |= DC_TX_ADMTEK_WAR; 1929 sc->dc_pmode = DC_PMODE_MII; 1930 /* Don't read SROM for - auto-loaded on reset */ 1931 break; 1932 case DC_DEVICEID_98713: 1933 case DC_DEVICEID_98713_CP: 1934 if (revision < DC_REVISION_98713A) { 1935 sc->dc_type = DC_TYPE_98713; 1936 } 1937 if (revision >= DC_REVISION_98713A) { 1938 sc->dc_type = DC_TYPE_98713A; 1939 sc->dc_flags |= DC_21143_NWAY; 1940 } 1941 sc->dc_flags |= DC_REDUCED_MII_POLL; 1942 sc->dc_flags |= DC_TX_POLL | DC_TX_USE_TX_INTR; 1943 break; 1944 case DC_DEVICEID_987x5: 1945 case DC_DEVICEID_EN1217: 1946 /* 1947 * Macronix MX98715AEC-C/D/E parts have only a 1948 * 128-bit hash table. We need to deal with these 1949 * in the same manner as the PNIC II so that we 1950 * get the right number of bits out of the 1951 * CRC routine. 1952 */ 1953 if (revision >= DC_REVISION_98715AEC_C && 1954 revision < DC_REVISION_98725) 1955 sc->dc_flags |= DC_128BIT_HASH; 1956 sc->dc_type = DC_TYPE_987x5; 1957 sc->dc_flags |= DC_TX_POLL | DC_TX_USE_TX_INTR; 1958 sc->dc_flags |= DC_REDUCED_MII_POLL | DC_21143_NWAY; 1959 break; 1960 case DC_DEVICEID_98727: 1961 sc->dc_type = DC_TYPE_987x5; 1962 sc->dc_flags |= DC_TX_POLL | DC_TX_USE_TX_INTR; 1963 sc->dc_flags |= DC_REDUCED_MII_POLL | DC_21143_NWAY; 1964 break; 1965 case DC_DEVICEID_82C115: 1966 sc->dc_type = DC_TYPE_PNICII; 1967 sc->dc_flags |= DC_TX_POLL | DC_TX_USE_TX_INTR | DC_128BIT_HASH; 1968 sc->dc_flags |= DC_REDUCED_MII_POLL | DC_21143_NWAY; 1969 break; 1970 case DC_DEVICEID_82C168: 1971 sc->dc_type = DC_TYPE_PNIC; 1972 sc->dc_flags |= DC_TX_STORENFWD | DC_TX_INTR_ALWAYS; 1973 sc->dc_flags |= DC_PNIC_RX_BUG_WAR; 1974 sc->dc_pnic_rx_buf = malloc(DC_RXLEN * 5, M_DEVBUF, M_NOWAIT); 1975 if (revision < DC_REVISION_82C169) 1976 sc->dc_pmode = DC_PMODE_SYM; 1977 break; 1978 case DC_DEVICEID_AX88140A: 1979 sc->dc_type = DC_TYPE_ASIX; 1980 sc->dc_flags |= DC_TX_USE_TX_INTR | DC_TX_INTR_FIRSTFRAG; 1981 sc->dc_flags |= DC_REDUCED_MII_POLL; 1982 sc->dc_pmode = DC_PMODE_MII; 1983 break; 1984 case DC_DEVICEID_X3201: 1985 sc->dc_type = DC_TYPE_XIRCOM; 1986 sc->dc_flags |= DC_TX_INTR_ALWAYS | DC_TX_COALESCE | 1987 DC_TX_ALIGN; 1988 /* 1989 * We don't actually need to coalesce, but we're doing 1990 * it to obtain a double word aligned buffer. 1991 * The DC_TX_COALESCE flag is required. 1992 */ 1993 sc->dc_pmode = DC_PMODE_MII; 1994 break; 1995 case DC_DEVICEID_RS7112: 1996 sc->dc_type = DC_TYPE_CONEXANT; 1997 sc->dc_flags |= DC_TX_INTR_ALWAYS; 1998 sc->dc_flags |= DC_REDUCED_MII_POLL; 1999 sc->dc_pmode = DC_PMODE_MII; 2000 dc_read_srom(sc, sc->dc_romwidth); 2001 break; 2002 default: 2003 device_printf(dev, "unknown device: %x\n", sc->dc_info->dc_did); 2004 break; 2005 } 2006 2007 /* Save the cache line size. */ 2008 if (DC_IS_DAVICOM(sc)) 2009 sc->dc_cachesize = 0; 2010 else 2011 sc->dc_cachesize = pci_read_config(dev, 2012 DC_PCI_CFLT, 4) & 0xFF; 2013 2014 /* Reset the adapter. */ 2015 dc_reset(sc); 2016 2017 /* Take 21143 out of snooze mode */ 2018 if (DC_IS_INTEL(sc) || DC_IS_XIRCOM(sc)) { 2019 command = pci_read_config(dev, DC_PCI_CFDD, 4); 2020 command &= ~(DC_CFDD_SNOOZE_MODE | DC_CFDD_SLEEP_MODE); 2021 pci_write_config(dev, DC_PCI_CFDD, command, 4); 2022 } 2023 2024 /* 2025 * Try to learn something about the supported media. 2026 * We know that ASIX and ADMtek and Davicom devices 2027 * will *always* be using MII media, so that's a no-brainer. 2028 * The tricky ones are the Macronix/PNIC II and the 2029 * Intel 21143. 2030 */ 2031 if (DC_IS_INTEL(sc)) 2032 dc_parse_21143_srom(sc); 2033 else if (DC_IS_MACRONIX(sc) || DC_IS_PNICII(sc)) { 2034 if (sc->dc_type == DC_TYPE_98713) 2035 sc->dc_pmode = DC_PMODE_MII; 2036 else 2037 sc->dc_pmode = DC_PMODE_SYM; 2038 } else if (!sc->dc_pmode) 2039 sc->dc_pmode = DC_PMODE_MII; 2040 2041 /* 2042 * Get station address from the EEPROM. 2043 */ 2044 switch(sc->dc_type) { 2045 case DC_TYPE_98713: 2046 case DC_TYPE_98713A: 2047 case DC_TYPE_987x5: 2048 case DC_TYPE_PNICII: 2049 dc_read_eeprom(sc, (caddr_t)&mac_offset, 2050 (DC_EE_NODEADDR_OFFSET / 2), 1, 0); 2051 dc_read_eeprom(sc, (caddr_t)&eaddr, (mac_offset / 2), 3, 0); 2052 break; 2053 case DC_TYPE_PNIC: 2054 dc_read_eeprom(sc, (caddr_t)&eaddr, 0, 3, 1); 2055 break; 2056 case DC_TYPE_DM9102: 2057 dc_read_eeprom(sc, (caddr_t)&eaddr, DC_EE_NODEADDR, 3, 0); 2058 #ifdef __sparc64__ 2059 /* 2060 * If this is an onboard dc(4) the station address read from 2061 * the EEPROM is all zero and we have to get it from the fcode. 2062 */ 2063 for (i = 0; i < ETHER_ADDR_LEN; i++) 2064 if (eaddr[i] != 0x00) 2065 break; 2066 if (i >= ETHER_ADDR_LEN) 2067 OF_getetheraddr(dev, eaddr); 2068 #endif 2069 break; 2070 case DC_TYPE_21143: 2071 case DC_TYPE_ASIX: 2072 dc_read_eeprom(sc, (caddr_t)&eaddr, DC_EE_NODEADDR, 3, 0); 2073 break; 2074 case DC_TYPE_AL981: 2075 case DC_TYPE_AN985: 2076 *(u_int32_t *)(&eaddr[0]) = CSR_READ_4(sc, DC_AL_PAR0); 2077 *(u_int16_t *)(&eaddr[4]) = CSR_READ_4(sc, DC_AL_PAR1); 2078 break; 2079 case DC_TYPE_CONEXANT: 2080 bcopy(sc->dc_srom + DC_CONEXANT_EE_NODEADDR, &eaddr, 2081 ETHER_ADDR_LEN); 2082 break; 2083 case DC_TYPE_XIRCOM: 2084 /* The MAC comes from the CIS. */ 2085 mac = pci_get_ether(dev); 2086 if (!mac) { 2087 device_printf(dev, "No station address in CIS!\n"); 2088 error = ENXIO; 2089 goto fail; 2090 } 2091 bcopy(mac, eaddr, ETHER_ADDR_LEN); 2092 break; 2093 default: 2094 dc_read_eeprom(sc, (caddr_t)&eaddr, DC_EE_NODEADDR, 3, 0); 2095 break; 2096 } 2097 2098 /* Allocate a busdma tag and DMA safe memory for TX/RX descriptors. */ 2099 error = bus_dma_tag_create(NULL, PAGE_SIZE, 0, BUS_SPACE_MAXADDR_32BIT, 2100 BUS_SPACE_MAXADDR, NULL, NULL, sizeof(struct dc_list_data), 1, 2101 sizeof(struct dc_list_data), 0, NULL, NULL, &sc->dc_ltag); 2102 if (error) { 2103 device_printf(dev, "failed to allocate busdma tag\n"); 2104 error = ENXIO; 2105 goto fail; 2106 } 2107 error = bus_dmamem_alloc(sc->dc_ltag, (void **)&sc->dc_ldata, 2108 BUS_DMA_NOWAIT | BUS_DMA_ZERO, &sc->dc_lmap); 2109 if (error) { 2110 device_printf(dev, "failed to allocate DMA safe memory\n"); 2111 error = ENXIO; 2112 goto fail; 2113 } 2114 error = bus_dmamap_load(sc->dc_ltag, sc->dc_lmap, sc->dc_ldata, 2115 sizeof(struct dc_list_data), dc_dma_map_addr, &sc->dc_laddr, 2116 BUS_DMA_NOWAIT); 2117 if (error) { 2118 device_printf(dev, "cannot get address of the descriptors\n"); 2119 error = ENXIO; 2120 goto fail; 2121 } 2122 2123 /* 2124 * Allocate a busdma tag and DMA safe memory for the multicast 2125 * setup frame. 2126 */ 2127 error = bus_dma_tag_create(NULL, PAGE_SIZE, 0, BUS_SPACE_MAXADDR_32BIT, 2128 BUS_SPACE_MAXADDR, NULL, NULL, DC_SFRAME_LEN + DC_MIN_FRAMELEN, 1, 2129 DC_SFRAME_LEN + DC_MIN_FRAMELEN, 0, NULL, NULL, &sc->dc_stag); 2130 if (error) { 2131 device_printf(dev, "failed to allocate busdma tag\n"); 2132 error = ENXIO; 2133 goto fail; 2134 } 2135 error = bus_dmamem_alloc(sc->dc_stag, (void **)&sc->dc_cdata.dc_sbuf, 2136 BUS_DMA_NOWAIT, &sc->dc_smap); 2137 if (error) { 2138 device_printf(dev, "failed to allocate DMA safe memory\n"); 2139 error = ENXIO; 2140 goto fail; 2141 } 2142 error = bus_dmamap_load(sc->dc_stag, sc->dc_smap, sc->dc_cdata.dc_sbuf, 2143 DC_SFRAME_LEN, dc_dma_map_addr, &sc->dc_saddr, BUS_DMA_NOWAIT); 2144 if (error) { 2145 device_printf(dev, "cannot get address of the descriptors\n"); 2146 error = ENXIO; 2147 goto fail; 2148 } 2149 2150 /* Allocate a busdma tag for mbufs. */ 2151 error = bus_dma_tag_create(NULL, 1, 0, BUS_SPACE_MAXADDR_32BIT, 2152 BUS_SPACE_MAXADDR, NULL, NULL, MCLBYTES, DC_TX_LIST_CNT, MCLBYTES, 2153 0, NULL, NULL, &sc->dc_mtag); 2154 if (error) { 2155 device_printf(dev, "failed to allocate busdma tag\n"); 2156 error = ENXIO; 2157 goto fail; 2158 } 2159 2160 /* Create the TX/RX busdma maps. */ 2161 for (i = 0; i < DC_TX_LIST_CNT; i++) { 2162 error = bus_dmamap_create(sc->dc_mtag, 0, 2163 &sc->dc_cdata.dc_tx_map[i]); 2164 if (error) { 2165 device_printf(dev, "failed to init TX ring\n"); 2166 error = ENXIO; 2167 goto fail; 2168 } 2169 } 2170 for (i = 0; i < DC_RX_LIST_CNT; i++) { 2171 error = bus_dmamap_create(sc->dc_mtag, 0, 2172 &sc->dc_cdata.dc_rx_map[i]); 2173 if (error) { 2174 device_printf(dev, "failed to init RX ring\n"); 2175 error = ENXIO; 2176 goto fail; 2177 } 2178 } 2179 error = bus_dmamap_create(sc->dc_mtag, 0, &sc->dc_sparemap); 2180 if (error) { 2181 device_printf(dev, "failed to init RX ring\n"); 2182 error = ENXIO; 2183 goto fail; 2184 } 2185 2186 ifp = sc->dc_ifp = if_alloc(IFT_ETHER); 2187 if (ifp == NULL) { 2188 device_printf(dev, "can not if_alloc()\n"); 2189 error = ENOSPC; 2190 goto fail; 2191 } 2192 ifp->if_softc = sc; 2193 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 2194 /* XXX: bleah, MTU gets overwritten in ether_ifattach() */ 2195 ifp->if_mtu = ETHERMTU; 2196 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 2197 if (!IS_MPSAFE) 2198 ifp->if_flags |= IFF_NEEDSGIANT; 2199 ifp->if_ioctl = dc_ioctl; 2200 ifp->if_start = dc_start; 2201 ifp->if_watchdog = dc_watchdog; 2202 ifp->if_init = dc_init; 2203 ifp->if_baudrate = 10000000; 2204 IFQ_SET_MAXLEN(&ifp->if_snd, DC_TX_LIST_CNT - 1); 2205 ifp->if_snd.ifq_drv_maxlen = DC_TX_LIST_CNT - 1; 2206 IFQ_SET_READY(&ifp->if_snd); 2207 2208 /* 2209 * Do MII setup. If this is a 21143, check for a PHY on the 2210 * MII bus after applying any necessary fixups to twiddle the 2211 * GPIO bits. If we don't end up finding a PHY, restore the 2212 * old selection (SIA only or SIA/SYM) and attach the dcphy 2213 * driver instead. 2214 */ 2215 if (DC_IS_INTEL(sc)) { 2216 dc_apply_fixup(sc, IFM_AUTO); 2217 tmp = sc->dc_pmode; 2218 sc->dc_pmode = DC_PMODE_MII; 2219 } 2220 2221 /* 2222 * Setup General Purpose port mode and data so the tulip can talk 2223 * to the MII. This needs to be done before mii_phy_probe so that 2224 * we can actually see them. 2225 */ 2226 if (DC_IS_XIRCOM(sc)) { 2227 CSR_WRITE_4(sc, DC_SIAGP, DC_SIAGP_WRITE_EN | DC_SIAGP_INT1_EN | 2228 DC_SIAGP_MD_GP2_OUTPUT | DC_SIAGP_MD_GP0_OUTPUT); 2229 DELAY(10); 2230 CSR_WRITE_4(sc, DC_SIAGP, DC_SIAGP_INT1_EN | 2231 DC_SIAGP_MD_GP2_OUTPUT | DC_SIAGP_MD_GP0_OUTPUT); 2232 DELAY(10); 2233 } 2234 2235 error = mii_phy_probe(dev, &sc->dc_miibus, 2236 dc_ifmedia_upd, dc_ifmedia_sts); 2237 2238 if (error && DC_IS_INTEL(sc)) { 2239 sc->dc_pmode = tmp; 2240 if (sc->dc_pmode != DC_PMODE_SIA) 2241 sc->dc_pmode = DC_PMODE_SYM; 2242 sc->dc_flags |= DC_21143_NWAY; 2243 mii_phy_probe(dev, &sc->dc_miibus, 2244 dc_ifmedia_upd, dc_ifmedia_sts); 2245 /* 2246 * For non-MII cards, we need to have the 21143 2247 * drive the LEDs. Except there are some systems 2248 * like the NEC VersaPro NoteBook PC which have no 2249 * LEDs, and twiddling these bits has adverse effects 2250 * on them. (I.e. you suddenly can't get a link.) 2251 */ 2252 if (pci_read_config(dev, DC_PCI_CSID, 4) != 0x80281033) 2253 sc->dc_flags |= DC_TULIP_LEDS; 2254 error = 0; 2255 } 2256 2257 if (error) { 2258 device_printf(dev, "MII without any PHY!\n"); 2259 goto fail; 2260 } 2261 2262 if (DC_IS_ADMTEK(sc)) { 2263 /* 2264 * Set automatic TX underrun recovery for the ADMtek chips 2265 */ 2266 DC_SETBIT(sc, DC_AL_CR, DC_AL_CR_ATUR); 2267 } 2268 2269 /* 2270 * Tell the upper layer(s) we support long frames. 2271 */ 2272 ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header); 2273 ifp->if_capabilities |= IFCAP_VLAN_MTU; 2274 #ifdef DEVICE_POLLING 2275 ifp->if_capabilities |= IFCAP_POLLING; 2276 #endif 2277 ifp->if_capenable = ifp->if_capabilities; 2278 2279 callout_init(&sc->dc_stat_ch, IS_MPSAFE ? CALLOUT_MPSAFE : 0); 2280 2281 #ifdef SRM_MEDIA 2282 sc->dc_srm_media = 0; 2283 2284 /* Remember the SRM console media setting */ 2285 if (DC_IS_INTEL(sc)) { 2286 command = pci_read_config(dev, DC_PCI_CFDD, 4); 2287 command &= ~(DC_CFDD_SNOOZE_MODE | DC_CFDD_SLEEP_MODE); 2288 switch ((command >> 8) & 0xff) { 2289 case 3: 2290 sc->dc_srm_media = IFM_10_T; 2291 break; 2292 case 4: 2293 sc->dc_srm_media = IFM_10_T | IFM_FDX; 2294 break; 2295 case 5: 2296 sc->dc_srm_media = IFM_100_TX; 2297 break; 2298 case 6: 2299 sc->dc_srm_media = IFM_100_TX | IFM_FDX; 2300 break; 2301 } 2302 if (sc->dc_srm_media) 2303 sc->dc_srm_media |= IFM_ACTIVE | IFM_ETHER; 2304 } 2305 #endif 2306 2307 /* 2308 * Call MI attach routine. 2309 */ 2310 ether_ifattach(ifp, eaddr); 2311 2312 /* Hook interrupt last to avoid having to lock softc */ 2313 error = bus_setup_intr(dev, sc->dc_irq, INTR_TYPE_NET | 2314 (IS_MPSAFE ? INTR_MPSAFE : 0), 2315 dc_intr, sc, &sc->dc_intrhand); 2316 2317 if (error) { 2318 device_printf(dev, "couldn't set up irq\n"); 2319 ether_ifdetach(ifp); 2320 if_free(ifp); 2321 goto fail; 2322 } 2323 2324 fail: 2325 if (error) 2326 dc_detach(dev); 2327 return (error); 2328 } 2329 2330 /* 2331 * Shutdown hardware and free up resources. This can be called any 2332 * time after the mutex has been initialized. It is called in both 2333 * the error case in attach and the normal detach case so it needs 2334 * to be careful about only freeing resources that have actually been 2335 * allocated. 2336 */ 2337 static int 2338 dc_detach(device_t dev) 2339 { 2340 struct dc_softc *sc; 2341 struct ifnet *ifp; 2342 struct dc_mediainfo *m; 2343 int i; 2344 2345 sc = device_get_softc(dev); 2346 KASSERT(mtx_initialized(&sc->dc_mtx), ("dc mutex not initialized")); 2347 DC_LOCK(sc); 2348 2349 ifp = sc->dc_ifp; 2350 2351 /* These should only be active if attach succeeded */ 2352 if (device_is_attached(dev)) { 2353 dc_stop(sc); 2354 ether_ifdetach(ifp); 2355 if_free(ifp); 2356 } 2357 if (sc->dc_miibus) 2358 device_delete_child(dev, sc->dc_miibus); 2359 bus_generic_detach(dev); 2360 2361 if (sc->dc_intrhand) 2362 bus_teardown_intr(dev, sc->dc_irq, sc->dc_intrhand); 2363 if (sc->dc_irq) 2364 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->dc_irq); 2365 if (sc->dc_res) 2366 bus_release_resource(dev, DC_RES, DC_RID, sc->dc_res); 2367 2368 if (sc->dc_cdata.dc_sbuf != NULL) 2369 bus_dmamem_free(sc->dc_stag, sc->dc_cdata.dc_sbuf, sc->dc_smap); 2370 if (sc->dc_ldata != NULL) 2371 bus_dmamem_free(sc->dc_ltag, sc->dc_ldata, sc->dc_lmap); 2372 for (i = 0; i < DC_TX_LIST_CNT; i++) 2373 bus_dmamap_destroy(sc->dc_mtag, sc->dc_cdata.dc_tx_map[i]); 2374 for (i = 0; i < DC_RX_LIST_CNT; i++) 2375 bus_dmamap_destroy(sc->dc_mtag, sc->dc_cdata.dc_rx_map[i]); 2376 bus_dmamap_destroy(sc->dc_mtag, sc->dc_sparemap); 2377 if (sc->dc_stag) 2378 bus_dma_tag_destroy(sc->dc_stag); 2379 if (sc->dc_mtag) 2380 bus_dma_tag_destroy(sc->dc_mtag); 2381 if (sc->dc_ltag) 2382 bus_dma_tag_destroy(sc->dc_ltag); 2383 2384 free(sc->dc_pnic_rx_buf, M_DEVBUF); 2385 2386 while (sc->dc_mi != NULL) { 2387 m = sc->dc_mi->dc_next; 2388 free(sc->dc_mi, M_DEVBUF); 2389 sc->dc_mi = m; 2390 } 2391 free(sc->dc_srom, M_DEVBUF); 2392 2393 DC_UNLOCK(sc); 2394 mtx_destroy(&sc->dc_mtx); 2395 2396 return (0); 2397 } 2398 2399 /* 2400 * Initialize the transmit descriptors. 2401 */ 2402 static int 2403 dc_list_tx_init(struct dc_softc *sc) 2404 { 2405 struct dc_chain_data *cd; 2406 struct dc_list_data *ld; 2407 int i, nexti; 2408 2409 cd = &sc->dc_cdata; 2410 ld = sc->dc_ldata; 2411 for (i = 0; i < DC_TX_LIST_CNT; i++) { 2412 if (i == DC_TX_LIST_CNT - 1) 2413 nexti = 0; 2414 else 2415 nexti = i + 1; 2416 ld->dc_tx_list[i].dc_next = htole32(DC_TXDESC(sc, nexti)); 2417 cd->dc_tx_chain[i] = NULL; 2418 ld->dc_tx_list[i].dc_data = 0; 2419 ld->dc_tx_list[i].dc_ctl = 0; 2420 } 2421 2422 cd->dc_tx_prod = cd->dc_tx_cons = cd->dc_tx_cnt = 0; 2423 bus_dmamap_sync(sc->dc_ltag, sc->dc_lmap, 2424 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2425 return (0); 2426 } 2427 2428 2429 /* 2430 * Initialize the RX descriptors and allocate mbufs for them. Note that 2431 * we arrange the descriptors in a closed ring, so that the last descriptor 2432 * points back to the first. 2433 */ 2434 static int 2435 dc_list_rx_init(struct dc_softc *sc) 2436 { 2437 struct dc_chain_data *cd; 2438 struct dc_list_data *ld; 2439 int i, nexti; 2440 2441 cd = &sc->dc_cdata; 2442 ld = sc->dc_ldata; 2443 2444 for (i = 0; i < DC_RX_LIST_CNT; i++) { 2445 if (dc_newbuf(sc, i, 1) != 0) 2446 return (ENOBUFS); 2447 if (i == DC_RX_LIST_CNT - 1) 2448 nexti = 0; 2449 else 2450 nexti = i + 1; 2451 ld->dc_rx_list[i].dc_next = htole32(DC_RXDESC(sc, nexti)); 2452 } 2453 2454 cd->dc_rx_prod = 0; 2455 bus_dmamap_sync(sc->dc_ltag, sc->dc_lmap, 2456 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2457 return (0); 2458 } 2459 2460 static void 2461 dc_dma_map_rxbuf(arg, segs, nseg, mapsize, error) 2462 void *arg; 2463 bus_dma_segment_t *segs; 2464 int nseg; 2465 bus_size_t mapsize; 2466 int error; 2467 { 2468 struct dc_softc *sc; 2469 struct dc_desc *c; 2470 2471 sc = arg; 2472 c = &sc->dc_ldata->dc_rx_list[sc->dc_cdata.dc_rx_cur]; 2473 if (error) { 2474 sc->dc_cdata.dc_rx_err = error; 2475 return; 2476 } 2477 2478 KASSERT(nseg == 1, ("wrong number of segments, should be 1")); 2479 sc->dc_cdata.dc_rx_err = 0; 2480 c->dc_data = htole32(segs->ds_addr); 2481 } 2482 2483 /* 2484 * Initialize an RX descriptor and attach an MBUF cluster. 2485 */ 2486 static int 2487 dc_newbuf(struct dc_softc *sc, int i, int alloc) 2488 { 2489 struct mbuf *m_new; 2490 bus_dmamap_t tmp; 2491 int error; 2492 2493 if (alloc) { 2494 m_new = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR); 2495 if (m_new == NULL) 2496 return (ENOBUFS); 2497 } else { 2498 m_new = sc->dc_cdata.dc_rx_chain[i]; 2499 m_new->m_data = m_new->m_ext.ext_buf; 2500 } 2501 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 2502 m_adj(m_new, sizeof(u_int64_t)); 2503 2504 /* 2505 * If this is a PNIC chip, zero the buffer. This is part 2506 * of the workaround for the receive bug in the 82c168 and 2507 * 82c169 chips. 2508 */ 2509 if (sc->dc_flags & DC_PNIC_RX_BUG_WAR) 2510 bzero(mtod(m_new, char *), m_new->m_len); 2511 2512 /* No need to remap the mbuf if we're reusing it. */ 2513 if (alloc) { 2514 sc->dc_cdata.dc_rx_cur = i; 2515 error = bus_dmamap_load_mbuf(sc->dc_mtag, sc->dc_sparemap, 2516 m_new, dc_dma_map_rxbuf, sc, 0); 2517 if (error) { 2518 m_freem(m_new); 2519 return (error); 2520 } 2521 if (sc->dc_cdata.dc_rx_err != 0) { 2522 m_freem(m_new); 2523 return (sc->dc_cdata.dc_rx_err); 2524 } 2525 bus_dmamap_unload(sc->dc_mtag, sc->dc_cdata.dc_rx_map[i]); 2526 tmp = sc->dc_cdata.dc_rx_map[i]; 2527 sc->dc_cdata.dc_rx_map[i] = sc->dc_sparemap; 2528 sc->dc_sparemap = tmp; 2529 sc->dc_cdata.dc_rx_chain[i] = m_new; 2530 } 2531 2532 sc->dc_ldata->dc_rx_list[i].dc_ctl = htole32(DC_RXCTL_RLINK | DC_RXLEN); 2533 sc->dc_ldata->dc_rx_list[i].dc_status = htole32(DC_RXSTAT_OWN); 2534 bus_dmamap_sync(sc->dc_mtag, sc->dc_cdata.dc_rx_map[i], 2535 BUS_DMASYNC_PREREAD); 2536 bus_dmamap_sync(sc->dc_ltag, sc->dc_lmap, 2537 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2538 return (0); 2539 } 2540 2541 /* 2542 * Grrrrr. 2543 * The PNIC chip has a terrible bug in it that manifests itself during 2544 * periods of heavy activity. The exact mode of failure if difficult to 2545 * pinpoint: sometimes it only happens in promiscuous mode, sometimes it 2546 * will happen on slow machines. The bug is that sometimes instead of 2547 * uploading one complete frame during reception, it uploads what looks 2548 * like the entire contents of its FIFO memory. The frame we want is at 2549 * the end of the whole mess, but we never know exactly how much data has 2550 * been uploaded, so salvaging the frame is hard. 2551 * 2552 * There is only one way to do it reliably, and it's disgusting. 2553 * Here's what we know: 2554 * 2555 * - We know there will always be somewhere between one and three extra 2556 * descriptors uploaded. 2557 * 2558 * - We know the desired received frame will always be at the end of the 2559 * total data upload. 2560 * 2561 * - We know the size of the desired received frame because it will be 2562 * provided in the length field of the status word in the last descriptor. 2563 * 2564 * Here's what we do: 2565 * 2566 * - When we allocate buffers for the receive ring, we bzero() them. 2567 * This means that we know that the buffer contents should be all 2568 * zeros, except for data uploaded by the chip. 2569 * 2570 * - We also force the PNIC chip to upload frames that include the 2571 * ethernet CRC at the end. 2572 * 2573 * - We gather all of the bogus frame data into a single buffer. 2574 * 2575 * - We then position a pointer at the end of this buffer and scan 2576 * backwards until we encounter the first non-zero byte of data. 2577 * This is the end of the received frame. We know we will encounter 2578 * some data at the end of the frame because the CRC will always be 2579 * there, so even if the sender transmits a packet of all zeros, 2580 * we won't be fooled. 2581 * 2582 * - We know the size of the actual received frame, so we subtract 2583 * that value from the current pointer location. This brings us 2584 * to the start of the actual received packet. 2585 * 2586 * - We copy this into an mbuf and pass it on, along with the actual 2587 * frame length. 2588 * 2589 * The performance hit is tremendous, but it beats dropping frames all 2590 * the time. 2591 */ 2592 2593 #define DC_WHOLEFRAME (DC_RXSTAT_FIRSTFRAG | DC_RXSTAT_LASTFRAG) 2594 static void 2595 dc_pnic_rx_bug_war(struct dc_softc *sc, int idx) 2596 { 2597 struct dc_desc *cur_rx; 2598 struct dc_desc *c = NULL; 2599 struct mbuf *m = NULL; 2600 unsigned char *ptr; 2601 int i, total_len; 2602 u_int32_t rxstat = 0; 2603 2604 i = sc->dc_pnic_rx_bug_save; 2605 cur_rx = &sc->dc_ldata->dc_rx_list[idx]; 2606 ptr = sc->dc_pnic_rx_buf; 2607 bzero(ptr, DC_RXLEN * 5); 2608 2609 /* Copy all the bytes from the bogus buffers. */ 2610 while (1) { 2611 c = &sc->dc_ldata->dc_rx_list[i]; 2612 rxstat = le32toh(c->dc_status); 2613 m = sc->dc_cdata.dc_rx_chain[i]; 2614 bcopy(mtod(m, char *), ptr, DC_RXLEN); 2615 ptr += DC_RXLEN; 2616 /* If this is the last buffer, break out. */ 2617 if (i == idx || rxstat & DC_RXSTAT_LASTFRAG) 2618 break; 2619 dc_newbuf(sc, i, 0); 2620 DC_INC(i, DC_RX_LIST_CNT); 2621 } 2622 2623 /* Find the length of the actual receive frame. */ 2624 total_len = DC_RXBYTES(rxstat); 2625 2626 /* Scan backwards until we hit a non-zero byte. */ 2627 while (*ptr == 0x00) 2628 ptr--; 2629 2630 /* Round off. */ 2631 if ((uintptr_t)(ptr) & 0x3) 2632 ptr -= 1; 2633 2634 /* Now find the start of the frame. */ 2635 ptr -= total_len; 2636 if (ptr < sc->dc_pnic_rx_buf) 2637 ptr = sc->dc_pnic_rx_buf; 2638 2639 /* 2640 * Now copy the salvaged frame to the last mbuf and fake up 2641 * the status word to make it look like a successful 2642 * frame reception. 2643 */ 2644 dc_newbuf(sc, i, 0); 2645 bcopy(ptr, mtod(m, char *), total_len); 2646 cur_rx->dc_status = htole32(rxstat | DC_RXSTAT_FIRSTFRAG); 2647 } 2648 2649 /* 2650 * This routine searches the RX ring for dirty descriptors in the 2651 * event that the rxeof routine falls out of sync with the chip's 2652 * current descriptor pointer. This may happen sometimes as a result 2653 * of a "no RX buffer available" condition that happens when the chip 2654 * consumes all of the RX buffers before the driver has a chance to 2655 * process the RX ring. This routine may need to be called more than 2656 * once to bring the driver back in sync with the chip, however we 2657 * should still be getting RX DONE interrupts to drive the search 2658 * for new packets in the RX ring, so we should catch up eventually. 2659 */ 2660 static int 2661 dc_rx_resync(struct dc_softc *sc) 2662 { 2663 struct dc_desc *cur_rx; 2664 int i, pos; 2665 2666 pos = sc->dc_cdata.dc_rx_prod; 2667 2668 for (i = 0; i < DC_RX_LIST_CNT; i++) { 2669 cur_rx = &sc->dc_ldata->dc_rx_list[pos]; 2670 if (!(le32toh(cur_rx->dc_status) & DC_RXSTAT_OWN)) 2671 break; 2672 DC_INC(pos, DC_RX_LIST_CNT); 2673 } 2674 2675 /* If the ring really is empty, then just return. */ 2676 if (i == DC_RX_LIST_CNT) 2677 return (0); 2678 2679 /* We've fallen behing the chip: catch it. */ 2680 sc->dc_cdata.dc_rx_prod = pos; 2681 2682 return (EAGAIN); 2683 } 2684 2685 /* 2686 * A frame has been uploaded: pass the resulting mbuf chain up to 2687 * the higher level protocols. 2688 */ 2689 static void 2690 dc_rxeof(struct dc_softc *sc) 2691 { 2692 struct mbuf *m; 2693 struct ifnet *ifp; 2694 struct dc_desc *cur_rx; 2695 int i, total_len = 0; 2696 u_int32_t rxstat; 2697 2698 DC_LOCK_ASSERT(sc); 2699 2700 ifp = sc->dc_ifp; 2701 i = sc->dc_cdata.dc_rx_prod; 2702 2703 bus_dmamap_sync(sc->dc_ltag, sc->dc_lmap, BUS_DMASYNC_POSTREAD); 2704 while (!(le32toh(sc->dc_ldata->dc_rx_list[i].dc_status) & 2705 DC_RXSTAT_OWN)) { 2706 #ifdef DEVICE_POLLING 2707 if (ifp->if_flags & IFF_POLLING) { 2708 if (sc->rxcycles <= 0) 2709 break; 2710 sc->rxcycles--; 2711 } 2712 #endif 2713 cur_rx = &sc->dc_ldata->dc_rx_list[i]; 2714 rxstat = le32toh(cur_rx->dc_status); 2715 m = sc->dc_cdata.dc_rx_chain[i]; 2716 bus_dmamap_sync(sc->dc_mtag, sc->dc_cdata.dc_rx_map[i], 2717 BUS_DMASYNC_POSTREAD); 2718 total_len = DC_RXBYTES(rxstat); 2719 2720 if (sc->dc_flags & DC_PNIC_RX_BUG_WAR) { 2721 if ((rxstat & DC_WHOLEFRAME) != DC_WHOLEFRAME) { 2722 if (rxstat & DC_RXSTAT_FIRSTFRAG) 2723 sc->dc_pnic_rx_bug_save = i; 2724 if ((rxstat & DC_RXSTAT_LASTFRAG) == 0) { 2725 DC_INC(i, DC_RX_LIST_CNT); 2726 continue; 2727 } 2728 dc_pnic_rx_bug_war(sc, i); 2729 rxstat = le32toh(cur_rx->dc_status); 2730 total_len = DC_RXBYTES(rxstat); 2731 } 2732 } 2733 2734 /* 2735 * If an error occurs, update stats, clear the 2736 * status word and leave the mbuf cluster in place: 2737 * it should simply get re-used next time this descriptor 2738 * comes up in the ring. However, don't report long 2739 * frames as errors since they could be vlans. 2740 */ 2741 if ((rxstat & DC_RXSTAT_RXERR)) { 2742 if (!(rxstat & DC_RXSTAT_GIANT) || 2743 (rxstat & (DC_RXSTAT_CRCERR | DC_RXSTAT_DRIBBLE | 2744 DC_RXSTAT_MIIERE | DC_RXSTAT_COLLSEEN | 2745 DC_RXSTAT_RUNT | DC_RXSTAT_DE))) { 2746 ifp->if_ierrors++; 2747 if (rxstat & DC_RXSTAT_COLLSEEN) 2748 ifp->if_collisions++; 2749 dc_newbuf(sc, i, 0); 2750 if (rxstat & DC_RXSTAT_CRCERR) { 2751 DC_INC(i, DC_RX_LIST_CNT); 2752 continue; 2753 } else { 2754 dc_init(sc); 2755 return; 2756 } 2757 } 2758 } 2759 2760 /* No errors; receive the packet. */ 2761 total_len -= ETHER_CRC_LEN; 2762 #ifdef __i386__ 2763 /* 2764 * On the x86 we do not have alignment problems, so try to 2765 * allocate a new buffer for the receive ring, and pass up 2766 * the one where the packet is already, saving the expensive 2767 * copy done in m_devget(). 2768 * If we are on an architecture with alignment problems, or 2769 * if the allocation fails, then use m_devget and leave the 2770 * existing buffer in the receive ring. 2771 */ 2772 if (dc_quick && dc_newbuf(sc, i, 1) == 0) { 2773 m->m_pkthdr.rcvif = ifp; 2774 m->m_pkthdr.len = m->m_len = total_len; 2775 DC_INC(i, DC_RX_LIST_CNT); 2776 } else 2777 #endif 2778 { 2779 struct mbuf *m0; 2780 2781 m0 = m_devget(mtod(m, char *), total_len, 2782 ETHER_ALIGN, ifp, NULL); 2783 dc_newbuf(sc, i, 0); 2784 DC_INC(i, DC_RX_LIST_CNT); 2785 if (m0 == NULL) { 2786 ifp->if_ierrors++; 2787 continue; 2788 } 2789 m = m0; 2790 } 2791 2792 ifp->if_ipackets++; 2793 DC_UNLOCK(sc); 2794 (*ifp->if_input)(ifp, m); 2795 DC_LOCK(sc); 2796 } 2797 2798 sc->dc_cdata.dc_rx_prod = i; 2799 } 2800 2801 /* 2802 * A frame was downloaded to the chip. It's safe for us to clean up 2803 * the list buffers. 2804 */ 2805 2806 static void 2807 dc_txeof(struct dc_softc *sc) 2808 { 2809 struct dc_desc *cur_tx = NULL; 2810 struct ifnet *ifp; 2811 int idx; 2812 u_int32_t ctl, txstat; 2813 2814 ifp = sc->dc_ifp; 2815 2816 /* 2817 * Go through our tx list and free mbufs for those 2818 * frames that have been transmitted. 2819 */ 2820 bus_dmamap_sync(sc->dc_ltag, sc->dc_lmap, BUS_DMASYNC_POSTREAD); 2821 idx = sc->dc_cdata.dc_tx_cons; 2822 while (idx != sc->dc_cdata.dc_tx_prod) { 2823 2824 cur_tx = &sc->dc_ldata->dc_tx_list[idx]; 2825 txstat = le32toh(cur_tx->dc_status); 2826 ctl = le32toh(cur_tx->dc_ctl); 2827 2828 if (txstat & DC_TXSTAT_OWN) 2829 break; 2830 2831 if (!(ctl & DC_TXCTL_LASTFRAG) || ctl & DC_TXCTL_SETUP) { 2832 if (ctl & DC_TXCTL_SETUP) { 2833 /* 2834 * Yes, the PNIC is so brain damaged 2835 * that it will sometimes generate a TX 2836 * underrun error while DMAing the RX 2837 * filter setup frame. If we detect this, 2838 * we have to send the setup frame again, 2839 * or else the filter won't be programmed 2840 * correctly. 2841 */ 2842 if (DC_IS_PNIC(sc)) { 2843 if (txstat & DC_TXSTAT_ERRSUM) 2844 dc_setfilt(sc); 2845 } 2846 sc->dc_cdata.dc_tx_chain[idx] = NULL; 2847 } 2848 sc->dc_cdata.dc_tx_cnt--; 2849 DC_INC(idx, DC_TX_LIST_CNT); 2850 continue; 2851 } 2852 2853 if (DC_IS_XIRCOM(sc) || DC_IS_CONEXANT(sc)) { 2854 /* 2855 * XXX: Why does my Xircom taunt me so? 2856 * For some reason it likes setting the CARRLOST flag 2857 * even when the carrier is there. wtf?!? 2858 * Who knows, but Conexant chips have the 2859 * same problem. Maybe they took lessons 2860 * from Xircom. 2861 */ 2862 if (/*sc->dc_type == DC_TYPE_21143 &&*/ 2863 sc->dc_pmode == DC_PMODE_MII && 2864 ((txstat & 0xFFFF) & ~(DC_TXSTAT_ERRSUM | 2865 DC_TXSTAT_NOCARRIER))) 2866 txstat &= ~DC_TXSTAT_ERRSUM; 2867 } else { 2868 if (/*sc->dc_type == DC_TYPE_21143 &&*/ 2869 sc->dc_pmode == DC_PMODE_MII && 2870 ((txstat & 0xFFFF) & ~(DC_TXSTAT_ERRSUM | 2871 DC_TXSTAT_NOCARRIER | DC_TXSTAT_CARRLOST))) 2872 txstat &= ~DC_TXSTAT_ERRSUM; 2873 } 2874 2875 if (txstat & DC_TXSTAT_ERRSUM) { 2876 ifp->if_oerrors++; 2877 if (txstat & DC_TXSTAT_EXCESSCOLL) 2878 ifp->if_collisions++; 2879 if (txstat & DC_TXSTAT_LATECOLL) 2880 ifp->if_collisions++; 2881 if (!(txstat & DC_TXSTAT_UNDERRUN)) { 2882 dc_init(sc); 2883 return; 2884 } 2885 } 2886 2887 ifp->if_collisions += (txstat & DC_TXSTAT_COLLCNT) >> 3; 2888 2889 ifp->if_opackets++; 2890 if (sc->dc_cdata.dc_tx_chain[idx] != NULL) { 2891 bus_dmamap_sync(sc->dc_mtag, 2892 sc->dc_cdata.dc_tx_map[idx], 2893 BUS_DMASYNC_POSTWRITE); 2894 bus_dmamap_unload(sc->dc_mtag, 2895 sc->dc_cdata.dc_tx_map[idx]); 2896 m_freem(sc->dc_cdata.dc_tx_chain[idx]); 2897 sc->dc_cdata.dc_tx_chain[idx] = NULL; 2898 } 2899 2900 sc->dc_cdata.dc_tx_cnt--; 2901 DC_INC(idx, DC_TX_LIST_CNT); 2902 } 2903 2904 if (idx != sc->dc_cdata.dc_tx_cons) { 2905 /* Some buffers have been freed. */ 2906 sc->dc_cdata.dc_tx_cons = idx; 2907 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 2908 } 2909 ifp->if_timer = (sc->dc_cdata.dc_tx_cnt == 0) ? 0 : 5; 2910 } 2911 2912 static void 2913 dc_tick(void *xsc) 2914 { 2915 struct dc_softc *sc; 2916 struct mii_data *mii; 2917 struct ifnet *ifp; 2918 u_int32_t r; 2919 2920 sc = xsc; 2921 DC_LOCK(sc); 2922 ifp = sc->dc_ifp; 2923 mii = device_get_softc(sc->dc_miibus); 2924 2925 if (sc->dc_flags & DC_REDUCED_MII_POLL) { 2926 if (sc->dc_flags & DC_21143_NWAY) { 2927 r = CSR_READ_4(sc, DC_10BTSTAT); 2928 if (IFM_SUBTYPE(mii->mii_media_active) == 2929 IFM_100_TX && (r & DC_TSTAT_LS100)) { 2930 sc->dc_link = 0; 2931 mii_mediachg(mii); 2932 } 2933 if (IFM_SUBTYPE(mii->mii_media_active) == 2934 IFM_10_T && (r & DC_TSTAT_LS10)) { 2935 sc->dc_link = 0; 2936 mii_mediachg(mii); 2937 } 2938 if (sc->dc_link == 0) 2939 mii_tick(mii); 2940 } else { 2941 r = CSR_READ_4(sc, DC_ISR); 2942 if ((r & DC_ISR_RX_STATE) == DC_RXSTATE_WAIT && 2943 sc->dc_cdata.dc_tx_cnt == 0) { 2944 mii_tick(mii); 2945 if (!(mii->mii_media_status & IFM_ACTIVE)) 2946 sc->dc_link = 0; 2947 } 2948 } 2949 } else 2950 mii_tick(mii); 2951 2952 /* 2953 * When the init routine completes, we expect to be able to send 2954 * packets right away, and in fact the network code will send a 2955 * gratuitous ARP the moment the init routine marks the interface 2956 * as running. However, even though the MAC may have been initialized, 2957 * there may be a delay of a few seconds before the PHY completes 2958 * autonegotiation and the link is brought up. Any transmissions 2959 * made during that delay will be lost. Dealing with this is tricky: 2960 * we can't just pause in the init routine while waiting for the 2961 * PHY to come ready since that would bring the whole system to 2962 * a screeching halt for several seconds. 2963 * 2964 * What we do here is prevent the TX start routine from sending 2965 * any packets until a link has been established. After the 2966 * interface has been initialized, the tick routine will poll 2967 * the state of the PHY until the IFM_ACTIVE flag is set. Until 2968 * that time, packets will stay in the send queue, and once the 2969 * link comes up, they will be flushed out to the wire. 2970 */ 2971 if (!sc->dc_link && mii->mii_media_status & IFM_ACTIVE && 2972 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) { 2973 sc->dc_link++; 2974 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 2975 dc_start(ifp); 2976 } 2977 2978 if (sc->dc_flags & DC_21143_NWAY && !sc->dc_link) 2979 callout_reset(&sc->dc_stat_ch, hz/10, dc_tick, sc); 2980 else 2981 callout_reset(&sc->dc_stat_ch, hz, dc_tick, sc); 2982 2983 DC_UNLOCK(sc); 2984 } 2985 2986 /* 2987 * A transmit underrun has occurred. Back off the transmit threshold, 2988 * or switch to store and forward mode if we have to. 2989 */ 2990 static void 2991 dc_tx_underrun(struct dc_softc *sc) 2992 { 2993 u_int32_t isr; 2994 int i; 2995 2996 if (DC_IS_DAVICOM(sc)) 2997 dc_init(sc); 2998 2999 if (DC_IS_INTEL(sc)) { 3000 /* 3001 * The real 21143 requires that the transmitter be idle 3002 * in order to change the transmit threshold or store 3003 * and forward state. 3004 */ 3005 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_TX_ON); 3006 3007 for (i = 0; i < DC_TIMEOUT; i++) { 3008 isr = CSR_READ_4(sc, DC_ISR); 3009 if (isr & DC_ISR_TX_IDLE) 3010 break; 3011 DELAY(10); 3012 } 3013 if (i == DC_TIMEOUT) { 3014 if_printf(sc->dc_ifp, 3015 "failed to force tx to idle state\n"); 3016 dc_init(sc); 3017 } 3018 } 3019 3020 if_printf(sc->dc_ifp, "TX underrun -- "); 3021 sc->dc_txthresh += DC_TXTHRESH_INC; 3022 if (sc->dc_txthresh > DC_TXTHRESH_MAX) { 3023 printf("using store and forward mode\n"); 3024 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_STORENFWD); 3025 } else { 3026 printf("increasing TX threshold\n"); 3027 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_TX_THRESH); 3028 DC_SETBIT(sc, DC_NETCFG, sc->dc_txthresh); 3029 } 3030 3031 if (DC_IS_INTEL(sc)) 3032 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_TX_ON); 3033 } 3034 3035 #ifdef DEVICE_POLLING 3036 static poll_handler_t dc_poll; 3037 3038 static void 3039 dc_poll(struct ifnet *ifp, enum poll_cmd cmd, int count) 3040 { 3041 struct dc_softc *sc = ifp->if_softc; 3042 3043 if (!(ifp->if_capenable & IFCAP_POLLING)) { 3044 ether_poll_deregister(ifp); 3045 cmd = POLL_DEREGISTER; 3046 } 3047 if (cmd == POLL_DEREGISTER) { /* final call, enable interrupts */ 3048 /* Re-enable interrupts. */ 3049 CSR_WRITE_4(sc, DC_IMR, DC_INTRS); 3050 return; 3051 } 3052 DC_LOCK(sc); 3053 sc->rxcycles = count; 3054 dc_rxeof(sc); 3055 dc_txeof(sc); 3056 if (!IFQ_IS_EMPTY(&ifp->if_snd) && 3057 !(ifp->if_drv_flags & IFF_DRV_OACTIVE)) 3058 dc_start(ifp); 3059 3060 if (cmd == POLL_AND_CHECK_STATUS) { /* also check status register */ 3061 u_int32_t status; 3062 3063 status = CSR_READ_4(sc, DC_ISR); 3064 status &= (DC_ISR_RX_WATDOGTIMEO | DC_ISR_RX_NOBUF | 3065 DC_ISR_TX_NOBUF | DC_ISR_TX_IDLE | DC_ISR_TX_UNDERRUN | 3066 DC_ISR_BUS_ERR); 3067 if (!status) { 3068 DC_UNLOCK(sc); 3069 return; 3070 } 3071 /* ack what we have */ 3072 CSR_WRITE_4(sc, DC_ISR, status); 3073 3074 if (status & (DC_ISR_RX_WATDOGTIMEO | DC_ISR_RX_NOBUF)) { 3075 u_int32_t r = CSR_READ_4(sc, DC_FRAMESDISCARDED); 3076 ifp->if_ierrors += (r & 0xffff) + ((r >> 17) & 0x7ff); 3077 3078 if (dc_rx_resync(sc)) 3079 dc_rxeof(sc); 3080 } 3081 /* restart transmit unit if necessary */ 3082 if (status & DC_ISR_TX_IDLE && sc->dc_cdata.dc_tx_cnt) 3083 CSR_WRITE_4(sc, DC_TXSTART, 0xFFFFFFFF); 3084 3085 if (status & DC_ISR_TX_UNDERRUN) 3086 dc_tx_underrun(sc); 3087 3088 if (status & DC_ISR_BUS_ERR) { 3089 if_printf(ifp, "dc_poll: bus error\n"); 3090 dc_reset(sc); 3091 dc_init(sc); 3092 } 3093 } 3094 DC_UNLOCK(sc); 3095 } 3096 #endif /* DEVICE_POLLING */ 3097 3098 static void 3099 dc_intr(void *arg) 3100 { 3101 struct dc_softc *sc; 3102 struct ifnet *ifp; 3103 u_int32_t status; 3104 3105 sc = arg; 3106 3107 if (sc->suspended) 3108 return; 3109 3110 if ((CSR_READ_4(sc, DC_ISR) & DC_INTRS) == 0) 3111 return; 3112 3113 DC_LOCK(sc); 3114 ifp = sc->dc_ifp; 3115 #ifdef DEVICE_POLLING 3116 if (ifp->if_flags & IFF_POLLING) 3117 goto done; 3118 if ((ifp->if_capenable & IFCAP_POLLING) && 3119 ether_poll_register(dc_poll, ifp)) { /* ok, disable interrupts */ 3120 CSR_WRITE_4(sc, DC_IMR, 0x00000000); 3121 goto done; 3122 } 3123 #endif 3124 3125 /* Suppress unwanted interrupts */ 3126 if (!(ifp->if_flags & IFF_UP)) { 3127 if (CSR_READ_4(sc, DC_ISR) & DC_INTRS) 3128 dc_stop(sc); 3129 DC_UNLOCK(sc); 3130 return; 3131 } 3132 3133 /* Disable interrupts. */ 3134 CSR_WRITE_4(sc, DC_IMR, 0x00000000); 3135 3136 while (((status = CSR_READ_4(sc, DC_ISR)) & DC_INTRS) 3137 && status != 0xFFFFFFFF) { 3138 3139 CSR_WRITE_4(sc, DC_ISR, status); 3140 3141 if (status & DC_ISR_RX_OK) { 3142 int curpkts; 3143 curpkts = ifp->if_ipackets; 3144 dc_rxeof(sc); 3145 if (curpkts == ifp->if_ipackets) { 3146 while (dc_rx_resync(sc)) 3147 dc_rxeof(sc); 3148 } 3149 } 3150 3151 if (status & (DC_ISR_TX_OK | DC_ISR_TX_NOBUF)) 3152 dc_txeof(sc); 3153 3154 if (status & DC_ISR_TX_IDLE) { 3155 dc_txeof(sc); 3156 if (sc->dc_cdata.dc_tx_cnt) { 3157 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_TX_ON); 3158 CSR_WRITE_4(sc, DC_TXSTART, 0xFFFFFFFF); 3159 } 3160 } 3161 3162 if (status & DC_ISR_TX_UNDERRUN) 3163 dc_tx_underrun(sc); 3164 3165 if ((status & DC_ISR_RX_WATDOGTIMEO) 3166 || (status & DC_ISR_RX_NOBUF)) { 3167 int curpkts; 3168 curpkts = ifp->if_ipackets; 3169 dc_rxeof(sc); 3170 if (curpkts == ifp->if_ipackets) { 3171 while (dc_rx_resync(sc)) 3172 dc_rxeof(sc); 3173 } 3174 } 3175 3176 if (status & DC_ISR_BUS_ERR) { 3177 dc_reset(sc); 3178 dc_init(sc); 3179 } 3180 } 3181 3182 /* Re-enable interrupts. */ 3183 CSR_WRITE_4(sc, DC_IMR, DC_INTRS); 3184 3185 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 3186 dc_start(ifp); 3187 3188 #ifdef DEVICE_POLLING 3189 done: 3190 #endif 3191 3192 DC_UNLOCK(sc); 3193 } 3194 3195 static void 3196 dc_dma_map_txbuf(arg, segs, nseg, mapsize, error) 3197 void *arg; 3198 bus_dma_segment_t *segs; 3199 int nseg; 3200 bus_size_t mapsize; 3201 int error; 3202 { 3203 struct dc_softc *sc; 3204 struct dc_desc *f; 3205 int cur, first, frag, i; 3206 3207 sc = arg; 3208 if (error) { 3209 sc->dc_cdata.dc_tx_err = error; 3210 return; 3211 } 3212 3213 first = cur = frag = sc->dc_cdata.dc_tx_prod; 3214 for (i = 0; i < nseg; i++) { 3215 if ((sc->dc_flags & DC_TX_ADMTEK_WAR) && 3216 (frag == (DC_TX_LIST_CNT - 1)) && 3217 (first != sc->dc_cdata.dc_tx_first)) { 3218 bus_dmamap_unload(sc->dc_mtag, 3219 sc->dc_cdata.dc_tx_map[first]); 3220 sc->dc_cdata.dc_tx_err = ENOBUFS; 3221 return; 3222 } 3223 3224 f = &sc->dc_ldata->dc_tx_list[frag]; 3225 f->dc_ctl = htole32(DC_TXCTL_TLINK | segs[i].ds_len); 3226 if (i == 0) { 3227 f->dc_status = 0; 3228 f->dc_ctl |= htole32(DC_TXCTL_FIRSTFRAG); 3229 } else 3230 f->dc_status = htole32(DC_TXSTAT_OWN); 3231 f->dc_data = htole32(segs[i].ds_addr); 3232 cur = frag; 3233 DC_INC(frag, DC_TX_LIST_CNT); 3234 } 3235 3236 sc->dc_cdata.dc_tx_err = 0; 3237 sc->dc_cdata.dc_tx_prod = frag; 3238 sc->dc_cdata.dc_tx_cnt += nseg; 3239 sc->dc_ldata->dc_tx_list[cur].dc_ctl |= htole32(DC_TXCTL_LASTFRAG); 3240 sc->dc_cdata.dc_tx_chain[cur] = sc->dc_cdata.dc_tx_mapping; 3241 if (sc->dc_flags & DC_TX_INTR_FIRSTFRAG) 3242 sc->dc_ldata->dc_tx_list[first].dc_ctl |= 3243 htole32(DC_TXCTL_FINT); 3244 if (sc->dc_flags & DC_TX_INTR_ALWAYS) 3245 sc->dc_ldata->dc_tx_list[cur].dc_ctl |= htole32(DC_TXCTL_FINT); 3246 if (sc->dc_flags & DC_TX_USE_TX_INTR && sc->dc_cdata.dc_tx_cnt > 64) 3247 sc->dc_ldata->dc_tx_list[cur].dc_ctl |= htole32(DC_TXCTL_FINT); 3248 sc->dc_ldata->dc_tx_list[first].dc_status = htole32(DC_TXSTAT_OWN); 3249 } 3250 3251 /* 3252 * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data 3253 * pointers to the fragment pointers. 3254 */ 3255 static int 3256 dc_encap(struct dc_softc *sc, struct mbuf **m_head) 3257 { 3258 struct mbuf *m; 3259 int error, idx, chainlen = 0; 3260 3261 /* 3262 * If there's no way we can send any packets, return now. 3263 */ 3264 if (DC_TX_LIST_CNT - sc->dc_cdata.dc_tx_cnt < 6) 3265 return (ENOBUFS); 3266 3267 /* 3268 * Count the number of frags in this chain to see if 3269 * we need to m_defrag. Since the descriptor list is shared 3270 * by all packets, we'll m_defrag long chains so that they 3271 * do not use up the entire list, even if they would fit. 3272 */ 3273 for (m = *m_head; m != NULL; m = m->m_next) 3274 chainlen++; 3275 3276 if ((chainlen > DC_TX_LIST_CNT / 4) || 3277 ((DC_TX_LIST_CNT - (chainlen + sc->dc_cdata.dc_tx_cnt)) < 6)) { 3278 m = m_defrag(*m_head, M_DONTWAIT); 3279 if (m == NULL) 3280 return (ENOBUFS); 3281 *m_head = m; 3282 } 3283 3284 /* 3285 * Start packing the mbufs in this chain into 3286 * the fragment pointers. Stop when we run out 3287 * of fragments or hit the end of the mbuf chain. 3288 */ 3289 idx = sc->dc_cdata.dc_tx_prod; 3290 sc->dc_cdata.dc_tx_mapping = *m_head; 3291 error = bus_dmamap_load_mbuf(sc->dc_mtag, sc->dc_cdata.dc_tx_map[idx], 3292 *m_head, dc_dma_map_txbuf, sc, 0); 3293 if (error) 3294 return (error); 3295 if (sc->dc_cdata.dc_tx_err != 0) 3296 return (sc->dc_cdata.dc_tx_err); 3297 bus_dmamap_sync(sc->dc_mtag, sc->dc_cdata.dc_tx_map[idx], 3298 BUS_DMASYNC_PREWRITE); 3299 bus_dmamap_sync(sc->dc_ltag, sc->dc_lmap, 3300 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3301 return (0); 3302 } 3303 3304 /* 3305 * Main transmit routine. To avoid having to do mbuf copies, we put pointers 3306 * to the mbuf data regions directly in the transmit lists. We also save a 3307 * copy of the pointers since the transmit list fragment pointers are 3308 * physical addresses. 3309 */ 3310 3311 static void 3312 dc_start(struct ifnet *ifp) 3313 { 3314 struct dc_softc *sc; 3315 struct mbuf *m_head = NULL, *m; 3316 unsigned int queued = 0; 3317 int idx; 3318 3319 sc = ifp->if_softc; 3320 3321 DC_LOCK(sc); 3322 3323 if (!sc->dc_link && ifp->if_snd.ifq_len < 10) { 3324 DC_UNLOCK(sc); 3325 return; 3326 } 3327 3328 if (ifp->if_drv_flags & IFF_DRV_OACTIVE) { 3329 DC_UNLOCK(sc); 3330 return; 3331 } 3332 3333 idx = sc->dc_cdata.dc_tx_first = sc->dc_cdata.dc_tx_prod; 3334 3335 while (sc->dc_cdata.dc_tx_chain[idx] == NULL) { 3336 IFQ_DRV_DEQUEUE(&ifp->if_snd, m_head); 3337 if (m_head == NULL) 3338 break; 3339 3340 if (sc->dc_flags & DC_TX_COALESCE && 3341 (m_head->m_next != NULL || 3342 sc->dc_flags & DC_TX_ALIGN)) { 3343 m = m_defrag(m_head, M_DONTWAIT); 3344 if (m == NULL) { 3345 IFQ_DRV_PREPEND(&ifp->if_snd, m_head); 3346 ifp->if_drv_flags |= IFF_DRV_OACTIVE; 3347 break; 3348 } else { 3349 m_head = m; 3350 } 3351 } 3352 3353 if (dc_encap(sc, &m_head)) { 3354 IFQ_DRV_PREPEND(&ifp->if_snd, m_head); 3355 ifp->if_drv_flags |= IFF_DRV_OACTIVE; 3356 break; 3357 } 3358 idx = sc->dc_cdata.dc_tx_prod; 3359 3360 queued++; 3361 /* 3362 * If there's a BPF listener, bounce a copy of this frame 3363 * to him. 3364 */ 3365 BPF_MTAP(ifp, m_head); 3366 3367 if (sc->dc_flags & DC_TX_ONE) { 3368 ifp->if_drv_flags |= IFF_DRV_OACTIVE; 3369 break; 3370 } 3371 } 3372 3373 if (queued > 0) { 3374 /* Transmit */ 3375 if (!(sc->dc_flags & DC_TX_POLL)) 3376 CSR_WRITE_4(sc, DC_TXSTART, 0xFFFFFFFF); 3377 3378 /* 3379 * Set a timeout in case the chip goes out to lunch. 3380 */ 3381 ifp->if_timer = 5; 3382 } 3383 3384 DC_UNLOCK(sc); 3385 } 3386 3387 static void 3388 dc_init(void *xsc) 3389 { 3390 struct dc_softc *sc = xsc; 3391 struct ifnet *ifp = sc->dc_ifp; 3392 struct mii_data *mii; 3393 3394 DC_LOCK(sc); 3395 3396 mii = device_get_softc(sc->dc_miibus); 3397 3398 /* 3399 * Cancel pending I/O and free all RX/TX buffers. 3400 */ 3401 dc_stop(sc); 3402 dc_reset(sc); 3403 3404 /* 3405 * Set cache alignment and burst length. 3406 */ 3407 if (DC_IS_ASIX(sc) || DC_IS_DAVICOM(sc)) 3408 CSR_WRITE_4(sc, DC_BUSCTL, 0); 3409 else 3410 CSR_WRITE_4(sc, DC_BUSCTL, DC_BUSCTL_MRME | DC_BUSCTL_MRLE); 3411 /* 3412 * Evenly share the bus between receive and transmit process. 3413 */ 3414 if (DC_IS_INTEL(sc)) 3415 DC_SETBIT(sc, DC_BUSCTL, DC_BUSCTL_ARBITRATION); 3416 if (DC_IS_DAVICOM(sc) || DC_IS_INTEL(sc)) { 3417 DC_SETBIT(sc, DC_BUSCTL, DC_BURSTLEN_USECA); 3418 } else { 3419 DC_SETBIT(sc, DC_BUSCTL, DC_BURSTLEN_16LONG); 3420 } 3421 if (sc->dc_flags & DC_TX_POLL) 3422 DC_SETBIT(sc, DC_BUSCTL, DC_TXPOLL_1); 3423 switch(sc->dc_cachesize) { 3424 case 32: 3425 DC_SETBIT(sc, DC_BUSCTL, DC_CACHEALIGN_32LONG); 3426 break; 3427 case 16: 3428 DC_SETBIT(sc, DC_BUSCTL, DC_CACHEALIGN_16LONG); 3429 break; 3430 case 8: 3431 DC_SETBIT(sc, DC_BUSCTL, DC_CACHEALIGN_8LONG); 3432 break; 3433 case 0: 3434 default: 3435 DC_SETBIT(sc, DC_BUSCTL, DC_CACHEALIGN_NONE); 3436 break; 3437 } 3438 3439 if (sc->dc_flags & DC_TX_STORENFWD) 3440 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_STORENFWD); 3441 else { 3442 if (sc->dc_txthresh > DC_TXTHRESH_MAX) { 3443 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_STORENFWD); 3444 } else { 3445 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_STORENFWD); 3446 DC_SETBIT(sc, DC_NETCFG, sc->dc_txthresh); 3447 } 3448 } 3449 3450 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_NO_RXCRC); 3451 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_TX_BACKOFF); 3452 3453 if (DC_IS_MACRONIX(sc) || DC_IS_PNICII(sc)) { 3454 /* 3455 * The app notes for the 98713 and 98715A say that 3456 * in order to have the chips operate properly, a magic 3457 * number must be written to CSR16. Macronix does not 3458 * document the meaning of these bits so there's no way 3459 * to know exactly what they do. The 98713 has a magic 3460 * number all its own; the rest all use a different one. 3461 */ 3462 DC_CLRBIT(sc, DC_MX_MAGICPACKET, 0xFFFF0000); 3463 if (sc->dc_type == DC_TYPE_98713) 3464 DC_SETBIT(sc, DC_MX_MAGICPACKET, DC_MX_MAGIC_98713); 3465 else 3466 DC_SETBIT(sc, DC_MX_MAGICPACKET, DC_MX_MAGIC_98715); 3467 } 3468 3469 if (DC_IS_XIRCOM(sc)) { 3470 /* 3471 * setup General Purpose Port mode and data so the tulip 3472 * can talk to the MII. 3473 */ 3474 CSR_WRITE_4(sc, DC_SIAGP, DC_SIAGP_WRITE_EN | DC_SIAGP_INT1_EN | 3475 DC_SIAGP_MD_GP2_OUTPUT | DC_SIAGP_MD_GP0_OUTPUT); 3476 DELAY(10); 3477 CSR_WRITE_4(sc, DC_SIAGP, DC_SIAGP_INT1_EN | 3478 DC_SIAGP_MD_GP2_OUTPUT | DC_SIAGP_MD_GP0_OUTPUT); 3479 DELAY(10); 3480 } 3481 3482 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_TX_THRESH); 3483 DC_SETBIT(sc, DC_NETCFG, DC_TXTHRESH_MIN); 3484 3485 /* Init circular RX list. */ 3486 if (dc_list_rx_init(sc) == ENOBUFS) { 3487 if_printf(ifp, 3488 "initialization failed: no memory for rx buffers\n"); 3489 dc_stop(sc); 3490 DC_UNLOCK(sc); 3491 return; 3492 } 3493 3494 /* 3495 * Init TX descriptors. 3496 */ 3497 dc_list_tx_init(sc); 3498 3499 /* 3500 * Load the address of the RX list. 3501 */ 3502 CSR_WRITE_4(sc, DC_RXADDR, DC_RXDESC(sc, 0)); 3503 CSR_WRITE_4(sc, DC_TXADDR, DC_TXDESC(sc, 0)); 3504 3505 /* 3506 * Enable interrupts. 3507 */ 3508 #ifdef DEVICE_POLLING 3509 /* 3510 * ... but only if we are not polling, and make sure they are off in 3511 * the case of polling. Some cards (e.g. fxp) turn interrupts on 3512 * after a reset. 3513 */ 3514 if (ifp->if_flags & IFF_POLLING) 3515 CSR_WRITE_4(sc, DC_IMR, 0x00000000); 3516 else 3517 #endif 3518 CSR_WRITE_4(sc, DC_IMR, DC_INTRS); 3519 CSR_WRITE_4(sc, DC_ISR, 0xFFFFFFFF); 3520 3521 /* Enable transmitter. */ 3522 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_TX_ON); 3523 3524 /* 3525 * If this is an Intel 21143 and we're not using the 3526 * MII port, program the LED control pins so we get 3527 * link and activity indications. 3528 */ 3529 if (sc->dc_flags & DC_TULIP_LEDS) { 3530 CSR_WRITE_4(sc, DC_WATCHDOG, 3531 DC_WDOG_CTLWREN | DC_WDOG_LINK | DC_WDOG_ACTIVITY); 3532 CSR_WRITE_4(sc, DC_WATCHDOG, 0); 3533 } 3534 3535 /* 3536 * Load the RX/multicast filter. We do this sort of late 3537 * because the filter programming scheme on the 21143 and 3538 * some clones requires DMAing a setup frame via the TX 3539 * engine, and we need the transmitter enabled for that. 3540 */ 3541 dc_setfilt(sc); 3542 3543 /* Enable receiver. */ 3544 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_ON); 3545 CSR_WRITE_4(sc, DC_RXSTART, 0xFFFFFFFF); 3546 3547 mii_mediachg(mii); 3548 dc_setcfg(sc, sc->dc_if_media); 3549 3550 ifp->if_drv_flags |= IFF_DRV_RUNNING; 3551 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 3552 3553 /* Don't start the ticker if this is a homePNA link. */ 3554 if (IFM_SUBTYPE(mii->mii_media.ifm_media) == IFM_HPNA_1) 3555 sc->dc_link = 1; 3556 else { 3557 if (sc->dc_flags & DC_21143_NWAY) 3558 callout_reset(&sc->dc_stat_ch, hz/10, dc_tick, sc); 3559 else 3560 callout_reset(&sc->dc_stat_ch, hz, dc_tick, sc); 3561 } 3562 3563 #ifdef SRM_MEDIA 3564 if(sc->dc_srm_media) { 3565 struct ifreq ifr; 3566 3567 ifr.ifr_media = sc->dc_srm_media; 3568 ifmedia_ioctl(ifp, &ifr, &mii->mii_media, SIOCSIFMEDIA); 3569 sc->dc_srm_media = 0; 3570 } 3571 #endif 3572 DC_UNLOCK(sc); 3573 } 3574 3575 /* 3576 * Set media options. 3577 */ 3578 static int 3579 dc_ifmedia_upd(struct ifnet *ifp) 3580 { 3581 struct dc_softc *sc; 3582 struct mii_data *mii; 3583 struct ifmedia *ifm; 3584 3585 sc = ifp->if_softc; 3586 mii = device_get_softc(sc->dc_miibus); 3587 mii_mediachg(mii); 3588 ifm = &mii->mii_media; 3589 3590 if (DC_IS_DAVICOM(sc) && 3591 IFM_SUBTYPE(ifm->ifm_media) == IFM_HPNA_1) 3592 dc_setcfg(sc, ifm->ifm_media); 3593 else 3594 sc->dc_link = 0; 3595 3596 return (0); 3597 } 3598 3599 /* 3600 * Report current media status. 3601 */ 3602 static void 3603 dc_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 3604 { 3605 struct dc_softc *sc; 3606 struct mii_data *mii; 3607 struct ifmedia *ifm; 3608 3609 sc = ifp->if_softc; 3610 mii = device_get_softc(sc->dc_miibus); 3611 mii_pollstat(mii); 3612 ifm = &mii->mii_media; 3613 if (DC_IS_DAVICOM(sc)) { 3614 if (IFM_SUBTYPE(ifm->ifm_media) == IFM_HPNA_1) { 3615 ifmr->ifm_active = ifm->ifm_media; 3616 ifmr->ifm_status = 0; 3617 return; 3618 } 3619 } 3620 ifmr->ifm_active = mii->mii_media_active; 3621 ifmr->ifm_status = mii->mii_media_status; 3622 } 3623 3624 static int 3625 dc_ioctl(struct ifnet *ifp, u_long command, caddr_t data) 3626 { 3627 struct dc_softc *sc = ifp->if_softc; 3628 struct ifreq *ifr = (struct ifreq *)data; 3629 struct mii_data *mii; 3630 int error = 0; 3631 3632 DC_LOCK(sc); 3633 3634 switch (command) { 3635 case SIOCSIFFLAGS: 3636 if (ifp->if_flags & IFF_UP) { 3637 int need_setfilt = (ifp->if_flags ^ sc->dc_if_flags) & 3638 (IFF_PROMISC | IFF_ALLMULTI); 3639 3640 if (ifp->if_drv_flags & IFF_DRV_RUNNING) { 3641 if (need_setfilt) 3642 dc_setfilt(sc); 3643 } else { 3644 sc->dc_txthresh = 0; 3645 dc_init(sc); 3646 } 3647 } else { 3648 if (ifp->if_drv_flags & IFF_DRV_RUNNING) 3649 dc_stop(sc); 3650 } 3651 sc->dc_if_flags = ifp->if_flags; 3652 error = 0; 3653 break; 3654 case SIOCADDMULTI: 3655 case SIOCDELMULTI: 3656 dc_setfilt(sc); 3657 error = 0; 3658 break; 3659 case SIOCGIFMEDIA: 3660 case SIOCSIFMEDIA: 3661 mii = device_get_softc(sc->dc_miibus); 3662 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 3663 #ifdef SRM_MEDIA 3664 if (sc->dc_srm_media) 3665 sc->dc_srm_media = 0; 3666 #endif 3667 break; 3668 case SIOCSIFCAP: 3669 ifp->if_capenable &= ~IFCAP_POLLING; 3670 ifp->if_capenable |= ifr->ifr_reqcap & IFCAP_POLLING; 3671 break; 3672 default: 3673 error = ether_ioctl(ifp, command, data); 3674 break; 3675 } 3676 3677 DC_UNLOCK(sc); 3678 3679 return (error); 3680 } 3681 3682 static void 3683 dc_watchdog(struct ifnet *ifp) 3684 { 3685 struct dc_softc *sc; 3686 3687 sc = ifp->if_softc; 3688 3689 DC_LOCK(sc); 3690 3691 ifp->if_oerrors++; 3692 if_printf(ifp, "watchdog timeout\n"); 3693 3694 dc_stop(sc); 3695 dc_reset(sc); 3696 dc_init(sc); 3697 3698 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 3699 dc_start(ifp); 3700 3701 DC_UNLOCK(sc); 3702 } 3703 3704 /* 3705 * Stop the adapter and free any mbufs allocated to the 3706 * RX and TX lists. 3707 */ 3708 static void 3709 dc_stop(struct dc_softc *sc) 3710 { 3711 struct ifnet *ifp; 3712 struct dc_list_data *ld; 3713 struct dc_chain_data *cd; 3714 int i; 3715 u_int32_t ctl; 3716 3717 DC_LOCK(sc); 3718 3719 ifp = sc->dc_ifp; 3720 ifp->if_timer = 0; 3721 ld = sc->dc_ldata; 3722 cd = &sc->dc_cdata; 3723 3724 callout_stop(&sc->dc_stat_ch); 3725 3726 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE); 3727 #ifdef DEVICE_POLLING 3728 ether_poll_deregister(ifp); 3729 #endif 3730 3731 DC_CLRBIT(sc, DC_NETCFG, (DC_NETCFG_RX_ON | DC_NETCFG_TX_ON)); 3732 CSR_WRITE_4(sc, DC_IMR, 0x00000000); 3733 CSR_WRITE_4(sc, DC_TXADDR, 0x00000000); 3734 CSR_WRITE_4(sc, DC_RXADDR, 0x00000000); 3735 sc->dc_link = 0; 3736 3737 /* 3738 * Free data in the RX lists. 3739 */ 3740 for (i = 0; i < DC_RX_LIST_CNT; i++) { 3741 if (cd->dc_rx_chain[i] != NULL) { 3742 m_freem(cd->dc_rx_chain[i]); 3743 cd->dc_rx_chain[i] = NULL; 3744 } 3745 } 3746 bzero(&ld->dc_rx_list, sizeof(ld->dc_rx_list)); 3747 3748 /* 3749 * Free the TX list buffers. 3750 */ 3751 for (i = 0; i < DC_TX_LIST_CNT; i++) { 3752 if (cd->dc_tx_chain[i] != NULL) { 3753 ctl = le32toh(ld->dc_tx_list[i].dc_ctl); 3754 if ((ctl & DC_TXCTL_SETUP) || 3755 !(ctl & DC_TXCTL_LASTFRAG)) { 3756 cd->dc_tx_chain[i] = NULL; 3757 continue; 3758 } 3759 bus_dmamap_unload(sc->dc_mtag, cd->dc_tx_map[i]); 3760 m_freem(cd->dc_tx_chain[i]); 3761 cd->dc_tx_chain[i] = NULL; 3762 } 3763 } 3764 bzero(&ld->dc_tx_list, sizeof(ld->dc_tx_list)); 3765 3766 DC_UNLOCK(sc); 3767 } 3768 3769 /* 3770 * Device suspend routine. Stop the interface and save some PCI 3771 * settings in case the BIOS doesn't restore them properly on 3772 * resume. 3773 */ 3774 static int 3775 dc_suspend(device_t dev) 3776 { 3777 struct dc_softc *sc; 3778 int s; 3779 3780 s = splimp(); 3781 3782 sc = device_get_softc(dev); 3783 dc_stop(sc); 3784 sc->suspended = 1; 3785 3786 splx(s); 3787 return (0); 3788 } 3789 3790 /* 3791 * Device resume routine. Restore some PCI settings in case the BIOS 3792 * doesn't, re-enable busmastering, and restart the interface if 3793 * appropriate. 3794 */ 3795 static int 3796 dc_resume(device_t dev) 3797 { 3798 struct dc_softc *sc; 3799 struct ifnet *ifp; 3800 int s; 3801 3802 s = splimp(); 3803 3804 sc = device_get_softc(dev); 3805 ifp = sc->dc_ifp; 3806 3807 /* reinitialize interface if necessary */ 3808 if (ifp->if_flags & IFF_UP) 3809 dc_init(sc); 3810 3811 sc->suspended = 0; 3812 3813 splx(s); 3814 return (0); 3815 } 3816 3817 /* 3818 * Stop all chip I/O so that the kernel's probe routines don't 3819 * get confused by errant DMAs when rebooting. 3820 */ 3821 static void 3822 dc_shutdown(device_t dev) 3823 { 3824 struct dc_softc *sc; 3825 3826 sc = device_get_softc(dev); 3827 3828 dc_stop(sc); 3829 } 3830