1 /* 2 * Copyright (c) 1997, 1998, 1999 3 * Bill Paul <wpaul@ee.columbia.edu>. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 3. All advertising materials mentioning features or use of this software 14 * must display the following acknowledgement: 15 * This product includes software developed by Bill Paul. 16 * 4. Neither the name of the author nor the names of any co-contributors 17 * may be used to endorse or promote products derived from this software 18 * without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30 * THE POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33 /* 34 * DEC "tulip" clone ethernet driver. Supports the DEC/Intel 21143 35 * series chips and several workalikes including the following: 36 * 37 * Macronix 98713/98715/98725/98727/98732 PMAC (www.macronix.com) 38 * Macronix/Lite-On 82c115 PNIC II (www.macronix.com) 39 * Lite-On 82c168/82c169 PNIC (www.litecom.com) 40 * ASIX Electronics AX88140A (www.asix.com.tw) 41 * ASIX Electronics AX88141 (www.asix.com.tw) 42 * ADMtek AL981 (www.admtek.com.tw) 43 * ADMtek AN985 (www.admtek.com.tw) 44 * Davicom DM9100, DM9102, DM9102A (www.davicom8.com) 45 * Accton EN1217 (www.accton.com) 46 * Xircom X3201 (www.xircom.com) 47 * Abocom FE2500 48 * Conexant LANfinity (www.conexant.com) 49 * 3Com OfficeConnect 10/100B 3CSOHO100B (www.3com.com) 50 * 51 * Datasheets for the 21143 are available at developer.intel.com. 52 * Datasheets for the clone parts can be found at their respective sites. 53 * (Except for the PNIC; see www.freebsd.org/~wpaul/PNIC/pnic.ps.gz.) 54 * The PNIC II is essentially a Macronix 98715A chip; the only difference 55 * worth noting is that its multicast hash table is only 128 bits wide 56 * instead of 512. 57 * 58 * Written by Bill Paul <wpaul@ee.columbia.edu> 59 * Electrical Engineering Department 60 * Columbia University, New York City 61 */ 62 63 /* 64 * The Intel 21143 is the successor to the DEC 21140. It is basically 65 * the same as the 21140 but with a few new features. The 21143 supports 66 * three kinds of media attachments: 67 * 68 * o MII port, for 10Mbps and 100Mbps support and NWAY 69 * autonegotiation provided by an external PHY. 70 * o SYM port, for symbol mode 100Mbps support. 71 * o 10baseT port. 72 * o AUI/BNC port. 73 * 74 * The 100Mbps SYM port and 10baseT port can be used together in 75 * combination with the internal NWAY support to create a 10/100 76 * autosensing configuration. 77 * 78 * Note that not all tulip workalikes are handled in this driver: we only 79 * deal with those which are relatively well behaved. The Winbond is 80 * handled separately due to its different register offsets and the 81 * special handling needed for its various bugs. The PNIC is handled 82 * here, but I'm not thrilled about it. 83 * 84 * All of the workalike chips use some form of MII transceiver support 85 * with the exception of the Macronix chips, which also have a SYM port. 86 * The ASIX AX88140A is also documented to have a SYM port, but all 87 * the cards I've seen use an MII transceiver, probably because the 88 * AX88140A doesn't support internal NWAY. 89 */ 90 91 #include <sys/cdefs.h> 92 __FBSDID("$FreeBSD$"); 93 94 #include <sys/param.h> 95 #include <sys/systm.h> 96 #include <sys/sockio.h> 97 #include <sys/mbuf.h> 98 #include <sys/malloc.h> 99 #include <sys/kernel.h> 100 #include <sys/socket.h> 101 #include <sys/sysctl.h> 102 103 #include <net/if.h> 104 #include <net/if_arp.h> 105 #include <net/ethernet.h> 106 #include <net/if_dl.h> 107 #include <net/if_media.h> 108 #include <net/if_types.h> 109 #include <net/if_vlan_var.h> 110 111 #include <net/bpf.h> 112 113 #include <machine/bus_pio.h> 114 #include <machine/bus_memio.h> 115 #include <machine/bus.h> 116 #include <machine/resource.h> 117 #include <sys/bus.h> 118 #include <sys/rman.h> 119 120 #include <dev/mii/mii.h> 121 #include <dev/mii/miivar.h> 122 123 #include <pci/pcireg.h> 124 #include <pci/pcivar.h> 125 126 #define DC_USEIOSPACE 127 #ifdef __alpha__ 128 #define SRM_MEDIA 129 #endif 130 131 #include <pci/if_dcreg.h> 132 133 MODULE_DEPEND(dc, pci, 1, 1, 1); 134 MODULE_DEPEND(dc, ether, 1, 1, 1); 135 MODULE_DEPEND(dc, miibus, 1, 1, 1); 136 137 /* "controller miibus0" required. See GENERIC if you get errors here. */ 138 #include "miibus_if.h" 139 140 /* 141 * Various supported device vendors/types and their names. 142 */ 143 static struct dc_type dc_devs[] = { 144 { DC_VENDORID_DEC, DC_DEVICEID_21143, 145 "Intel 21143 10/100BaseTX" }, 146 { DC_VENDORID_DAVICOM, DC_DEVICEID_DM9009, 147 "Davicom DM9009 10/100BaseTX" }, 148 { DC_VENDORID_DAVICOM, DC_DEVICEID_DM9100, 149 "Davicom DM9100 10/100BaseTX" }, 150 { DC_VENDORID_DAVICOM, DC_DEVICEID_DM9102, 151 "Davicom DM9102 10/100BaseTX" }, 152 { DC_VENDORID_DAVICOM, DC_DEVICEID_DM9102, 153 "Davicom DM9102A 10/100BaseTX" }, 154 { DC_VENDORID_ADMTEK, DC_DEVICEID_AL981, 155 "ADMtek AL981 10/100BaseTX" }, 156 { DC_VENDORID_ADMTEK, DC_DEVICEID_AN985, 157 "ADMtek AN985 10/100BaseTX" }, 158 { DC_VENDORID_ADMTEK, DC_DEVICEID_ADM9511, 159 "ADMtek ADM9511 10/100BaseTX" }, 160 { DC_VENDORID_ADMTEK, DC_DEVICEID_ADM9513, 161 "ADMtek ADM9513 10/100BaseTX" }, 162 { DC_VENDORID_ASIX, DC_DEVICEID_AX88140A, 163 "ASIX AX88140A 10/100BaseTX" }, 164 { DC_VENDORID_ASIX, DC_DEVICEID_AX88140A, 165 "ASIX AX88141 10/100BaseTX" }, 166 { DC_VENDORID_MX, DC_DEVICEID_98713, 167 "Macronix 98713 10/100BaseTX" }, 168 { DC_VENDORID_MX, DC_DEVICEID_98713, 169 "Macronix 98713A 10/100BaseTX" }, 170 { DC_VENDORID_CP, DC_DEVICEID_98713_CP, 171 "Compex RL100-TX 10/100BaseTX" }, 172 { DC_VENDORID_CP, DC_DEVICEID_98713_CP, 173 "Compex RL100-TX 10/100BaseTX" }, 174 { DC_VENDORID_MX, DC_DEVICEID_987x5, 175 "Macronix 98715/98715A 10/100BaseTX" }, 176 { DC_VENDORID_MX, DC_DEVICEID_987x5, 177 "Macronix 98715AEC-C 10/100BaseTX" }, 178 { DC_VENDORID_MX, DC_DEVICEID_987x5, 179 "Macronix 98725 10/100BaseTX" }, 180 { DC_VENDORID_MX, DC_DEVICEID_98727, 181 "Macronix 98727/98732 10/100BaseTX" }, 182 { DC_VENDORID_LO, DC_DEVICEID_82C115, 183 "LC82C115 PNIC II 10/100BaseTX" }, 184 { DC_VENDORID_LO, DC_DEVICEID_82C168, 185 "82c168 PNIC 10/100BaseTX" }, 186 { DC_VENDORID_LO, DC_DEVICEID_82C168, 187 "82c169 PNIC 10/100BaseTX" }, 188 { DC_VENDORID_ACCTON, DC_DEVICEID_EN1217, 189 "Accton EN1217 10/100BaseTX" }, 190 { DC_VENDORID_ACCTON, DC_DEVICEID_EN2242, 191 "Accton EN2242 MiniPCI 10/100BaseTX" }, 192 { DC_VENDORID_XIRCOM, DC_DEVICEID_X3201, 193 "Xircom X3201 10/100BaseTX" }, 194 { DC_VENDORID_ABOCOM, DC_DEVICEID_FE2500, 195 "Abocom FE2500 10/100BaseTX" }, 196 { DC_VENDORID_CONEXANT, DC_DEVICEID_RS7112, 197 "Conexant LANfinity MiniPCI 10/100BaseTX" }, 198 { DC_VENDORID_HAWKING, DC_DEVICEID_HAWKING_PN672TX, 199 "Hawking CB102 CardBus 10/100" }, 200 { DC_VENDORID_PLANEX, DC_DEVICEID_FNW3602T, 201 "PlaneX FNW-3602-T CardBus 10/100" }, 202 { DC_VENDORID_3COM, DC_DEVICEID_3CSOHOB, 203 "3Com OfficeConnect 10/100B" }, 204 { 0, 0, NULL } 205 }; 206 207 static int dc_probe (device_t); 208 static int dc_attach (device_t); 209 static int dc_detach (device_t); 210 static int dc_suspend (device_t); 211 static int dc_resume (device_t); 212 #ifndef BURN_BRIDGES 213 static void dc_acpi (device_t); 214 #endif 215 static struct dc_type *dc_devtype (device_t); 216 static int dc_newbuf (struct dc_softc *, int, int); 217 static int dc_encap (struct dc_softc *, struct mbuf *); 218 static void dc_pnic_rx_bug_war (struct dc_softc *, int); 219 static int dc_rx_resync (struct dc_softc *); 220 static void dc_rxeof (struct dc_softc *); 221 static void dc_txeof (struct dc_softc *); 222 static void dc_tick (void *); 223 static void dc_tx_underrun (struct dc_softc *); 224 static void dc_intr (void *); 225 static void dc_start (struct ifnet *); 226 static int dc_ioctl (struct ifnet *, u_long, caddr_t); 227 static void dc_init (void *); 228 static void dc_stop (struct dc_softc *); 229 static void dc_watchdog (struct ifnet *); 230 static void dc_shutdown (device_t); 231 static int dc_ifmedia_upd (struct ifnet *); 232 static void dc_ifmedia_sts (struct ifnet *, struct ifmediareq *); 233 234 static void dc_delay (struct dc_softc *); 235 static void dc_eeprom_idle (struct dc_softc *); 236 static void dc_eeprom_putbyte (struct dc_softc *, int); 237 static void dc_eeprom_getword (struct dc_softc *, int, u_int16_t *); 238 static void dc_eeprom_getword_pnic 239 (struct dc_softc *, int, u_int16_t *); 240 static void dc_eeprom_getword_xircom 241 (struct dc_softc *, int, u_int16_t *); 242 static void dc_eeprom_width (struct dc_softc *); 243 static void dc_read_eeprom (struct dc_softc *, caddr_t, int, int, int); 244 245 static void dc_mii_writebit (struct dc_softc *, int); 246 static int dc_mii_readbit (struct dc_softc *); 247 static void dc_mii_sync (struct dc_softc *); 248 static void dc_mii_send (struct dc_softc *, u_int32_t, int); 249 static int dc_mii_readreg (struct dc_softc *, struct dc_mii_frame *); 250 static int dc_mii_writereg (struct dc_softc *, struct dc_mii_frame *); 251 static int dc_miibus_readreg (device_t, int, int); 252 static int dc_miibus_writereg (device_t, int, int, int); 253 static void dc_miibus_statchg (device_t); 254 static void dc_miibus_mediainit (device_t); 255 256 static void dc_setcfg (struct dc_softc *, int); 257 static u_int32_t dc_crc_le (struct dc_softc *, caddr_t); 258 static u_int32_t dc_crc_be (caddr_t); 259 static void dc_setfilt_21143 (struct dc_softc *); 260 static void dc_setfilt_asix (struct dc_softc *); 261 static void dc_setfilt_admtek (struct dc_softc *); 262 static void dc_setfilt_xircom (struct dc_softc *); 263 264 static void dc_setfilt (struct dc_softc *); 265 266 static void dc_reset (struct dc_softc *); 267 static int dc_list_rx_init (struct dc_softc *); 268 static int dc_list_tx_init (struct dc_softc *); 269 270 static void dc_read_srom (struct dc_softc *, int); 271 static void dc_parse_21143_srom (struct dc_softc *); 272 static void dc_decode_leaf_sia (struct dc_softc *, struct dc_eblock_sia *); 273 static void dc_decode_leaf_mii (struct dc_softc *, struct dc_eblock_mii *); 274 static void dc_decode_leaf_sym (struct dc_softc *, struct dc_eblock_sym *); 275 static void dc_apply_fixup (struct dc_softc *, int); 276 277 static void dc_dma_map_txbuf (void *, bus_dma_segment_t *, int, bus_size_t, 278 int); 279 static void dc_dma_map_rxbuf (void *, bus_dma_segment_t *, int, bus_size_t, 280 int); 281 282 #ifdef DC_USEIOSPACE 283 #define DC_RES SYS_RES_IOPORT 284 #define DC_RID DC_PCI_CFBIO 285 #else 286 #define DC_RES SYS_RES_MEMORY 287 #define DC_RID DC_PCI_CFBMA 288 #endif 289 290 static device_method_t dc_methods[] = { 291 /* Device interface */ 292 DEVMETHOD(device_probe, dc_probe), 293 DEVMETHOD(device_attach, dc_attach), 294 DEVMETHOD(device_detach, dc_detach), 295 DEVMETHOD(device_suspend, dc_suspend), 296 DEVMETHOD(device_resume, dc_resume), 297 DEVMETHOD(device_shutdown, dc_shutdown), 298 299 /* bus interface */ 300 DEVMETHOD(bus_print_child, bus_generic_print_child), 301 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 302 303 /* MII interface */ 304 DEVMETHOD(miibus_readreg, dc_miibus_readreg), 305 DEVMETHOD(miibus_writereg, dc_miibus_writereg), 306 DEVMETHOD(miibus_statchg, dc_miibus_statchg), 307 DEVMETHOD(miibus_mediainit, dc_miibus_mediainit), 308 309 { 0, 0 } 310 }; 311 312 static driver_t dc_driver = { 313 "dc", 314 dc_methods, 315 sizeof(struct dc_softc) 316 }; 317 318 static devclass_t dc_devclass; 319 #ifdef __i386__ 320 static int dc_quick = 1; 321 SYSCTL_INT(_hw, OID_AUTO, dc_quick, CTLFLAG_RW, &dc_quick, 0, 322 "do not mdevget in dc driver"); 323 #endif 324 325 DRIVER_MODULE(dc, cardbus, dc_driver, dc_devclass, 0, 0); 326 DRIVER_MODULE(dc, pci, dc_driver, dc_devclass, 0, 0); 327 DRIVER_MODULE(miibus, dc, miibus_driver, miibus_devclass, 0, 0); 328 329 #define DC_SETBIT(sc, reg, x) \ 330 CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) | (x)) 331 332 #define DC_CLRBIT(sc, reg, x) \ 333 CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) & ~(x)) 334 335 #define SIO_SET(x) DC_SETBIT(sc, DC_SIO, (x)) 336 #define SIO_CLR(x) DC_CLRBIT(sc, DC_SIO, (x)) 337 338 #define IS_MPSAFE 0 339 340 static void 341 dc_delay(struct dc_softc *sc) 342 { 343 int idx; 344 345 for (idx = (300 / 33) + 1; idx > 0; idx--) 346 CSR_READ_4(sc, DC_BUSCTL); 347 } 348 349 static void 350 dc_eeprom_width(struct dc_softc *sc) 351 { 352 int i; 353 354 /* Force EEPROM to idle state. */ 355 dc_eeprom_idle(sc); 356 357 /* Enter EEPROM access mode. */ 358 CSR_WRITE_4(sc, DC_SIO, DC_SIO_EESEL); 359 dc_delay(sc); 360 DC_SETBIT(sc, DC_SIO, DC_SIO_ROMCTL_READ); 361 dc_delay(sc); 362 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); 363 dc_delay(sc); 364 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CS); 365 dc_delay(sc); 366 367 for (i = 3; i--;) { 368 if (6 & (1 << i)) 369 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_DATAIN); 370 else 371 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_DATAIN); 372 dc_delay(sc); 373 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CLK); 374 dc_delay(sc); 375 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); 376 dc_delay(sc); 377 } 378 379 for (i = 1; i <= 12; i++) { 380 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CLK); 381 dc_delay(sc); 382 if (!(CSR_READ_4(sc, DC_SIO) & DC_SIO_EE_DATAOUT)) { 383 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); 384 dc_delay(sc); 385 break; 386 } 387 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); 388 dc_delay(sc); 389 } 390 391 /* Turn off EEPROM access mode. */ 392 dc_eeprom_idle(sc); 393 394 if (i < 4 || i > 12) 395 sc->dc_romwidth = 6; 396 else 397 sc->dc_romwidth = i; 398 399 /* Enter EEPROM access mode. */ 400 CSR_WRITE_4(sc, DC_SIO, DC_SIO_EESEL); 401 dc_delay(sc); 402 DC_SETBIT(sc, DC_SIO, DC_SIO_ROMCTL_READ); 403 dc_delay(sc); 404 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); 405 dc_delay(sc); 406 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CS); 407 dc_delay(sc); 408 409 /* Turn off EEPROM access mode. */ 410 dc_eeprom_idle(sc); 411 } 412 413 static void 414 dc_eeprom_idle(struct dc_softc *sc) 415 { 416 int i; 417 418 CSR_WRITE_4(sc, DC_SIO, DC_SIO_EESEL); 419 dc_delay(sc); 420 DC_SETBIT(sc, DC_SIO, DC_SIO_ROMCTL_READ); 421 dc_delay(sc); 422 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); 423 dc_delay(sc); 424 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CS); 425 dc_delay(sc); 426 427 for (i = 0; i < 25; i++) { 428 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); 429 dc_delay(sc); 430 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CLK); 431 dc_delay(sc); 432 } 433 434 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); 435 dc_delay(sc); 436 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CS); 437 dc_delay(sc); 438 CSR_WRITE_4(sc, DC_SIO, 0x00000000); 439 } 440 441 /* 442 * Send a read command and address to the EEPROM, check for ACK. 443 */ 444 static void 445 dc_eeprom_putbyte(struct dc_softc *sc, int addr) 446 { 447 int d, i; 448 449 d = DC_EECMD_READ >> 6; 450 for (i = 3; i--; ) { 451 if (d & (1 << i)) 452 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_DATAIN); 453 else 454 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_DATAIN); 455 dc_delay(sc); 456 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CLK); 457 dc_delay(sc); 458 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); 459 dc_delay(sc); 460 } 461 462 /* 463 * Feed in each bit and strobe the clock. 464 */ 465 for (i = sc->dc_romwidth; i--;) { 466 if (addr & (1 << i)) { 467 SIO_SET(DC_SIO_EE_DATAIN); 468 } else { 469 SIO_CLR(DC_SIO_EE_DATAIN); 470 } 471 dc_delay(sc); 472 SIO_SET(DC_SIO_EE_CLK); 473 dc_delay(sc); 474 SIO_CLR(DC_SIO_EE_CLK); 475 dc_delay(sc); 476 } 477 } 478 479 /* 480 * Read a word of data stored in the EEPROM at address 'addr.' 481 * The PNIC 82c168/82c169 has its own non-standard way to read 482 * the EEPROM. 483 */ 484 static void 485 dc_eeprom_getword_pnic(struct dc_softc *sc, int addr, u_int16_t *dest) 486 { 487 int i; 488 u_int32_t r; 489 490 CSR_WRITE_4(sc, DC_PN_SIOCTL, DC_PN_EEOPCODE_READ | addr); 491 492 for (i = 0; i < DC_TIMEOUT; i++) { 493 DELAY(1); 494 r = CSR_READ_4(sc, DC_SIO); 495 if (!(r & DC_PN_SIOCTL_BUSY)) { 496 *dest = (u_int16_t)(r & 0xFFFF); 497 return; 498 } 499 } 500 } 501 502 /* 503 * Read a word of data stored in the EEPROM at address 'addr.' 504 * The Xircom X3201 has its own non-standard way to read 505 * the EEPROM, too. 506 */ 507 static void 508 dc_eeprom_getword_xircom(struct dc_softc *sc, int addr, u_int16_t *dest) 509 { 510 511 SIO_SET(DC_SIO_ROMSEL | DC_SIO_ROMCTL_READ); 512 513 addr *= 2; 514 CSR_WRITE_4(sc, DC_ROM, addr | 0x160); 515 *dest = (u_int16_t)CSR_READ_4(sc, DC_SIO) & 0xff; 516 addr += 1; 517 CSR_WRITE_4(sc, DC_ROM, addr | 0x160); 518 *dest |= ((u_int16_t)CSR_READ_4(sc, DC_SIO) & 0xff) << 8; 519 520 SIO_CLR(DC_SIO_ROMSEL | DC_SIO_ROMCTL_READ); 521 } 522 523 /* 524 * Read a word of data stored in the EEPROM at address 'addr.' 525 */ 526 static void 527 dc_eeprom_getword(struct dc_softc *sc, int addr, u_int16_t *dest) 528 { 529 int i; 530 u_int16_t word = 0; 531 532 /* Force EEPROM to idle state. */ 533 dc_eeprom_idle(sc); 534 535 /* Enter EEPROM access mode. */ 536 CSR_WRITE_4(sc, DC_SIO, DC_SIO_EESEL); 537 dc_delay(sc); 538 DC_SETBIT(sc, DC_SIO, DC_SIO_ROMCTL_READ); 539 dc_delay(sc); 540 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); 541 dc_delay(sc); 542 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CS); 543 dc_delay(sc); 544 545 /* 546 * Send address of word we want to read. 547 */ 548 dc_eeprom_putbyte(sc, addr); 549 550 /* 551 * Start reading bits from EEPROM. 552 */ 553 for (i = 0x8000; i; i >>= 1) { 554 SIO_SET(DC_SIO_EE_CLK); 555 dc_delay(sc); 556 if (CSR_READ_4(sc, DC_SIO) & DC_SIO_EE_DATAOUT) 557 word |= i; 558 dc_delay(sc); 559 SIO_CLR(DC_SIO_EE_CLK); 560 dc_delay(sc); 561 } 562 563 /* Turn off EEPROM access mode. */ 564 dc_eeprom_idle(sc); 565 566 *dest = word; 567 } 568 569 /* 570 * Read a sequence of words from the EEPROM. 571 */ 572 static void 573 dc_read_eeprom(struct dc_softc *sc, caddr_t dest, int off, int cnt, int swap) 574 { 575 int i; 576 u_int16_t word = 0, *ptr; 577 578 for (i = 0; i < cnt; i++) { 579 if (DC_IS_PNIC(sc)) 580 dc_eeprom_getword_pnic(sc, off + i, &word); 581 else if (DC_IS_XIRCOM(sc)) 582 dc_eeprom_getword_xircom(sc, off + i, &word); 583 else 584 dc_eeprom_getword(sc, off + i, &word); 585 ptr = (u_int16_t *)(dest + (i * 2)); 586 if (swap) 587 *ptr = ntohs(word); 588 else 589 *ptr = word; 590 } 591 } 592 593 /* 594 * The following two routines are taken from the Macronix 98713 595 * Application Notes pp.19-21. 596 */ 597 /* 598 * Write a bit to the MII bus. 599 */ 600 static void 601 dc_mii_writebit(struct dc_softc *sc, int bit) 602 { 603 604 if (bit) 605 CSR_WRITE_4(sc, DC_SIO, 606 DC_SIO_ROMCTL_WRITE | DC_SIO_MII_DATAOUT); 607 else 608 CSR_WRITE_4(sc, DC_SIO, DC_SIO_ROMCTL_WRITE); 609 610 DC_SETBIT(sc, DC_SIO, DC_SIO_MII_CLK); 611 DC_CLRBIT(sc, DC_SIO, DC_SIO_MII_CLK); 612 } 613 614 /* 615 * Read a bit from the MII bus. 616 */ 617 static int 618 dc_mii_readbit(struct dc_softc *sc) 619 { 620 621 CSR_WRITE_4(sc, DC_SIO, DC_SIO_ROMCTL_READ | DC_SIO_MII_DIR); 622 CSR_READ_4(sc, DC_SIO); 623 DC_SETBIT(sc, DC_SIO, DC_SIO_MII_CLK); 624 DC_CLRBIT(sc, DC_SIO, DC_SIO_MII_CLK); 625 if (CSR_READ_4(sc, DC_SIO) & DC_SIO_MII_DATAIN) 626 return (1); 627 628 return (0); 629 } 630 631 /* 632 * Sync the PHYs by setting data bit and strobing the clock 32 times. 633 */ 634 static void 635 dc_mii_sync(struct dc_softc *sc) 636 { 637 int i; 638 639 CSR_WRITE_4(sc, DC_SIO, DC_SIO_ROMCTL_WRITE); 640 641 for (i = 0; i < 32; i++) 642 dc_mii_writebit(sc, 1); 643 } 644 645 /* 646 * Clock a series of bits through the MII. 647 */ 648 static void 649 dc_mii_send(struct dc_softc *sc, u_int32_t bits, int cnt) 650 { 651 int i; 652 653 for (i = (0x1 << (cnt - 1)); i; i >>= 1) 654 dc_mii_writebit(sc, bits & i); 655 } 656 657 /* 658 * Read an PHY register through the MII. 659 */ 660 static int 661 dc_mii_readreg(struct dc_softc *sc, struct dc_mii_frame *frame) 662 { 663 int i, ack; 664 665 DC_LOCK(sc); 666 667 /* 668 * Set up frame for RX. 669 */ 670 frame->mii_stdelim = DC_MII_STARTDELIM; 671 frame->mii_opcode = DC_MII_READOP; 672 frame->mii_turnaround = 0; 673 frame->mii_data = 0; 674 675 /* 676 * Sync the PHYs. 677 */ 678 dc_mii_sync(sc); 679 680 /* 681 * Send command/address info. 682 */ 683 dc_mii_send(sc, frame->mii_stdelim, 2); 684 dc_mii_send(sc, frame->mii_opcode, 2); 685 dc_mii_send(sc, frame->mii_phyaddr, 5); 686 dc_mii_send(sc, frame->mii_regaddr, 5); 687 688 #ifdef notdef 689 /* Idle bit */ 690 dc_mii_writebit(sc, 1); 691 dc_mii_writebit(sc, 0); 692 #endif 693 694 /* Check for ack. */ 695 ack = dc_mii_readbit(sc); 696 697 /* 698 * Now try reading data bits. If the ack failed, we still 699 * need to clock through 16 cycles to keep the PHY(s) in sync. 700 */ 701 if (ack) { 702 for (i = 0; i < 16; i++) 703 dc_mii_readbit(sc); 704 goto fail; 705 } 706 707 for (i = 0x8000; i; i >>= 1) { 708 if (!ack) { 709 if (dc_mii_readbit(sc)) 710 frame->mii_data |= i; 711 } 712 } 713 714 fail: 715 716 dc_mii_writebit(sc, 0); 717 dc_mii_writebit(sc, 0); 718 719 DC_UNLOCK(sc); 720 721 if (ack) 722 return (1); 723 return (0); 724 } 725 726 /* 727 * Write to a PHY register through the MII. 728 */ 729 static int 730 dc_mii_writereg(struct dc_softc *sc, struct dc_mii_frame *frame) 731 { 732 733 DC_LOCK(sc); 734 /* 735 * Set up frame for TX. 736 */ 737 738 frame->mii_stdelim = DC_MII_STARTDELIM; 739 frame->mii_opcode = DC_MII_WRITEOP; 740 frame->mii_turnaround = DC_MII_TURNAROUND; 741 742 /* 743 * Sync the PHYs. 744 */ 745 dc_mii_sync(sc); 746 747 dc_mii_send(sc, frame->mii_stdelim, 2); 748 dc_mii_send(sc, frame->mii_opcode, 2); 749 dc_mii_send(sc, frame->mii_phyaddr, 5); 750 dc_mii_send(sc, frame->mii_regaddr, 5); 751 dc_mii_send(sc, frame->mii_turnaround, 2); 752 dc_mii_send(sc, frame->mii_data, 16); 753 754 /* Idle bit. */ 755 dc_mii_writebit(sc, 0); 756 dc_mii_writebit(sc, 0); 757 758 DC_UNLOCK(sc); 759 760 return (0); 761 } 762 763 static int 764 dc_miibus_readreg(device_t dev, int phy, int reg) 765 { 766 struct dc_mii_frame frame; 767 struct dc_softc *sc; 768 int i, rval, phy_reg = 0; 769 770 sc = device_get_softc(dev); 771 bzero(&frame, sizeof(frame)); 772 773 /* 774 * Note: both the AL981 and AN985 have internal PHYs, 775 * however the AL981 provides direct access to the PHY 776 * registers while the AN985 uses a serial MII interface. 777 * The AN985's MII interface is also buggy in that you 778 * can read from any MII address (0 to 31), but only address 1 779 * behaves normally. To deal with both cases, we pretend 780 * that the PHY is at MII address 1. 781 */ 782 if (DC_IS_ADMTEK(sc) && phy != DC_ADMTEK_PHYADDR) 783 return (0); 784 785 /* 786 * Note: the ukphy probes of the RS7112 report a PHY at 787 * MII address 0 (possibly HomePNA?) and 1 (ethernet) 788 * so we only respond to correct one. 789 */ 790 if (DC_IS_CONEXANT(sc) && phy != DC_CONEXANT_PHYADDR) 791 return (0); 792 793 if (sc->dc_pmode != DC_PMODE_MII) { 794 if (phy == (MII_NPHY - 1)) { 795 switch (reg) { 796 case MII_BMSR: 797 /* 798 * Fake something to make the probe 799 * code think there's a PHY here. 800 */ 801 return (BMSR_MEDIAMASK); 802 break; 803 case MII_PHYIDR1: 804 if (DC_IS_PNIC(sc)) 805 return (DC_VENDORID_LO); 806 return (DC_VENDORID_DEC); 807 break; 808 case MII_PHYIDR2: 809 if (DC_IS_PNIC(sc)) 810 return (DC_DEVICEID_82C168); 811 return (DC_DEVICEID_21143); 812 break; 813 default: 814 return (0); 815 break; 816 } 817 } else 818 return (0); 819 } 820 821 if (DC_IS_PNIC(sc)) { 822 CSR_WRITE_4(sc, DC_PN_MII, DC_PN_MIIOPCODE_READ | 823 (phy << 23) | (reg << 18)); 824 for (i = 0; i < DC_TIMEOUT; i++) { 825 DELAY(1); 826 rval = CSR_READ_4(sc, DC_PN_MII); 827 if (!(rval & DC_PN_MII_BUSY)) { 828 rval &= 0xFFFF; 829 return (rval == 0xFFFF ? 0 : rval); 830 } 831 } 832 return (0); 833 } 834 835 if (DC_IS_COMET(sc)) { 836 switch (reg) { 837 case MII_BMCR: 838 phy_reg = DC_AL_BMCR; 839 break; 840 case MII_BMSR: 841 phy_reg = DC_AL_BMSR; 842 break; 843 case MII_PHYIDR1: 844 phy_reg = DC_AL_VENID; 845 break; 846 case MII_PHYIDR2: 847 phy_reg = DC_AL_DEVID; 848 break; 849 case MII_ANAR: 850 phy_reg = DC_AL_ANAR; 851 break; 852 case MII_ANLPAR: 853 phy_reg = DC_AL_LPAR; 854 break; 855 case MII_ANER: 856 phy_reg = DC_AL_ANER; 857 break; 858 default: 859 printf("dc%d: phy_read: bad phy register %x\n", 860 sc->dc_unit, reg); 861 return (0); 862 break; 863 } 864 865 rval = CSR_READ_4(sc, phy_reg) & 0x0000FFFF; 866 867 if (rval == 0xFFFF) 868 return (0); 869 return (rval); 870 } 871 872 frame.mii_phyaddr = phy; 873 frame.mii_regaddr = reg; 874 if (sc->dc_type == DC_TYPE_98713) { 875 phy_reg = CSR_READ_4(sc, DC_NETCFG); 876 CSR_WRITE_4(sc, DC_NETCFG, phy_reg & ~DC_NETCFG_PORTSEL); 877 } 878 dc_mii_readreg(sc, &frame); 879 if (sc->dc_type == DC_TYPE_98713) 880 CSR_WRITE_4(sc, DC_NETCFG, phy_reg); 881 882 return (frame.mii_data); 883 } 884 885 static int 886 dc_miibus_writereg(device_t dev, int phy, int reg, int data) 887 { 888 struct dc_softc *sc; 889 struct dc_mii_frame frame; 890 int i, phy_reg = 0; 891 892 sc = device_get_softc(dev); 893 bzero(&frame, sizeof(frame)); 894 895 if (DC_IS_ADMTEK(sc) && phy != DC_ADMTEK_PHYADDR) 896 return (0); 897 898 if (DC_IS_CONEXANT(sc) && phy != DC_CONEXANT_PHYADDR) 899 return (0); 900 901 if (DC_IS_PNIC(sc)) { 902 CSR_WRITE_4(sc, DC_PN_MII, DC_PN_MIIOPCODE_WRITE | 903 (phy << 23) | (reg << 10) | data); 904 for (i = 0; i < DC_TIMEOUT; i++) { 905 if (!(CSR_READ_4(sc, DC_PN_MII) & DC_PN_MII_BUSY)) 906 break; 907 } 908 return (0); 909 } 910 911 if (DC_IS_COMET(sc)) { 912 switch (reg) { 913 case MII_BMCR: 914 phy_reg = DC_AL_BMCR; 915 break; 916 case MII_BMSR: 917 phy_reg = DC_AL_BMSR; 918 break; 919 case MII_PHYIDR1: 920 phy_reg = DC_AL_VENID; 921 break; 922 case MII_PHYIDR2: 923 phy_reg = DC_AL_DEVID; 924 break; 925 case MII_ANAR: 926 phy_reg = DC_AL_ANAR; 927 break; 928 case MII_ANLPAR: 929 phy_reg = DC_AL_LPAR; 930 break; 931 case MII_ANER: 932 phy_reg = DC_AL_ANER; 933 break; 934 default: 935 printf("dc%d: phy_write: bad phy register %x\n", 936 sc->dc_unit, reg); 937 return (0); 938 break; 939 } 940 941 CSR_WRITE_4(sc, phy_reg, data); 942 return (0); 943 } 944 945 frame.mii_phyaddr = phy; 946 frame.mii_regaddr = reg; 947 frame.mii_data = data; 948 949 if (sc->dc_type == DC_TYPE_98713) { 950 phy_reg = CSR_READ_4(sc, DC_NETCFG); 951 CSR_WRITE_4(sc, DC_NETCFG, phy_reg & ~DC_NETCFG_PORTSEL); 952 } 953 dc_mii_writereg(sc, &frame); 954 if (sc->dc_type == DC_TYPE_98713) 955 CSR_WRITE_4(sc, DC_NETCFG, phy_reg); 956 957 return (0); 958 } 959 960 static void 961 dc_miibus_statchg(device_t dev) 962 { 963 struct dc_softc *sc; 964 struct mii_data *mii; 965 struct ifmedia *ifm; 966 967 sc = device_get_softc(dev); 968 if (DC_IS_ADMTEK(sc)) 969 return; 970 971 mii = device_get_softc(sc->dc_miibus); 972 ifm = &mii->mii_media; 973 if (DC_IS_DAVICOM(sc) && 974 IFM_SUBTYPE(ifm->ifm_media) == IFM_HPNA_1) { 975 dc_setcfg(sc, ifm->ifm_media); 976 sc->dc_if_media = ifm->ifm_media; 977 } else { 978 dc_setcfg(sc, mii->mii_media_active); 979 sc->dc_if_media = mii->mii_media_active; 980 } 981 } 982 983 /* 984 * Special support for DM9102A cards with HomePNA PHYs. Note: 985 * with the Davicom DM9102A/DM9801 eval board that I have, it seems 986 * to be impossible to talk to the management interface of the DM9801 987 * PHY (its MDIO pin is not connected to anything). Consequently, 988 * the driver has to just 'know' about the additional mode and deal 989 * with it itself. *sigh* 990 */ 991 static void 992 dc_miibus_mediainit(device_t dev) 993 { 994 struct dc_softc *sc; 995 struct mii_data *mii; 996 struct ifmedia *ifm; 997 int rev; 998 999 rev = pci_read_config(dev, DC_PCI_CFRV, 4) & 0xFF; 1000 1001 sc = device_get_softc(dev); 1002 mii = device_get_softc(sc->dc_miibus); 1003 ifm = &mii->mii_media; 1004 1005 if (DC_IS_DAVICOM(sc) && rev >= DC_REVISION_DM9102A) 1006 ifmedia_add(ifm, IFM_ETHER | IFM_HPNA_1, 0, NULL); 1007 } 1008 1009 #define DC_POLY 0xEDB88320 1010 #define DC_BITS_512 9 1011 #define DC_BITS_128 7 1012 #define DC_BITS_64 6 1013 1014 static u_int32_t 1015 dc_crc_le(struct dc_softc *sc, caddr_t addr) 1016 { 1017 u_int32_t idx, bit, data, crc; 1018 1019 /* Compute CRC for the address value. */ 1020 crc = 0xFFFFFFFF; /* initial value */ 1021 1022 for (idx = 0; idx < 6; idx++) { 1023 for (data = *addr++, bit = 0; bit < 8; bit++, data >>= 1) 1024 crc = (crc >> 1) ^ (((crc ^ data) & 1) ? DC_POLY : 0); 1025 } 1026 1027 /* 1028 * The hash table on the PNIC II and the MX98715AEC-C/D/E 1029 * chips is only 128 bits wide. 1030 */ 1031 if (sc->dc_flags & DC_128BIT_HASH) 1032 return (crc & ((1 << DC_BITS_128) - 1)); 1033 1034 /* The hash table on the MX98715BEC is only 64 bits wide. */ 1035 if (sc->dc_flags & DC_64BIT_HASH) 1036 return (crc & ((1 << DC_BITS_64) - 1)); 1037 1038 /* Xircom's hash filtering table is different (read: weird) */ 1039 /* Xircom uses the LEAST significant bits */ 1040 if (DC_IS_XIRCOM(sc)) { 1041 if ((crc & 0x180) == 0x180) 1042 return ((crc & 0x0F) + (crc & 0x70) * 3 + (14 << 4)); 1043 else 1044 return ((crc & 0x1F) + ((crc >> 1) & 0xF0) * 3 + 1045 (12 << 4)); 1046 } 1047 1048 return (crc & ((1 << DC_BITS_512) - 1)); 1049 } 1050 1051 /* 1052 * Calculate CRC of a multicast group address, return the lower 6 bits. 1053 */ 1054 static u_int32_t 1055 dc_crc_be(caddr_t addr) 1056 { 1057 u_int32_t crc, carry; 1058 int i, j; 1059 u_int8_t c; 1060 1061 /* Compute CRC for the address value. */ 1062 crc = 0xFFFFFFFF; /* initial value */ 1063 1064 for (i = 0; i < 6; i++) { 1065 c = *(addr + i); 1066 for (j = 0; j < 8; j++) { 1067 carry = ((crc & 0x80000000) ? 1 : 0) ^ (c & 0x01); 1068 crc <<= 1; 1069 c >>= 1; 1070 if (carry) 1071 crc = (crc ^ 0x04c11db6) | carry; 1072 } 1073 } 1074 1075 /* Return the filter bit position. */ 1076 return ((crc >> 26) & 0x0000003F); 1077 } 1078 1079 /* 1080 * 21143-style RX filter setup routine. Filter programming is done by 1081 * downloading a special setup frame into the TX engine. 21143, Macronix, 1082 * PNIC, PNIC II and Davicom chips are programmed this way. 1083 * 1084 * We always program the chip using 'hash perfect' mode, i.e. one perfect 1085 * address (our node address) and a 512-bit hash filter for multicast 1086 * frames. We also sneak the broadcast address into the hash filter since 1087 * we need that too. 1088 */ 1089 static void 1090 dc_setfilt_21143(struct dc_softc *sc) 1091 { 1092 struct dc_desc *sframe; 1093 u_int32_t h, *sp; 1094 struct ifmultiaddr *ifma; 1095 struct ifnet *ifp; 1096 int i; 1097 1098 ifp = &sc->arpcom.ac_if; 1099 1100 i = sc->dc_cdata.dc_tx_prod; 1101 DC_INC(sc->dc_cdata.dc_tx_prod, DC_TX_LIST_CNT); 1102 sc->dc_cdata.dc_tx_cnt++; 1103 sframe = &sc->dc_ldata->dc_tx_list[i]; 1104 sp = sc->dc_cdata.dc_sbuf; 1105 bzero(sp, DC_SFRAME_LEN); 1106 1107 sframe->dc_data = sc->dc_saddr; 1108 sframe->dc_ctl = DC_SFRAME_LEN | DC_TXCTL_SETUP | DC_TXCTL_TLINK | 1109 DC_FILTER_HASHPERF | DC_TXCTL_FINT; 1110 1111 sc->dc_cdata.dc_tx_chain[i] = (struct mbuf *)sc->dc_cdata.dc_sbuf; 1112 1113 /* If we want promiscuous mode, set the allframes bit. */ 1114 if (ifp->if_flags & IFF_PROMISC) 1115 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC); 1116 else 1117 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC); 1118 1119 if (ifp->if_flags & IFF_ALLMULTI) 1120 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI); 1121 else 1122 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI); 1123 1124 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 1125 if (ifma->ifma_addr->sa_family != AF_LINK) 1126 continue; 1127 h = dc_crc_le(sc, 1128 LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 1129 sp[h >> 4] |= 1 << (h & 0xF); 1130 } 1131 1132 if (ifp->if_flags & IFF_BROADCAST) { 1133 h = dc_crc_le(sc, (caddr_t)ifp->if_broadcastaddr); 1134 sp[h >> 4] |= 1 << (h & 0xF); 1135 } 1136 1137 /* Set our MAC address */ 1138 sp[39] = ((u_int16_t *)sc->arpcom.ac_enaddr)[0]; 1139 sp[40] = ((u_int16_t *)sc->arpcom.ac_enaddr)[1]; 1140 sp[41] = ((u_int16_t *)sc->arpcom.ac_enaddr)[2]; 1141 1142 sframe->dc_status = DC_TXSTAT_OWN; 1143 CSR_WRITE_4(sc, DC_TXSTART, 0xFFFFFFFF); 1144 1145 /* 1146 * The PNIC takes an exceedingly long time to process its 1147 * setup frame; wait 10ms after posting the setup frame 1148 * before proceeding, just so it has time to swallow its 1149 * medicine. 1150 */ 1151 DELAY(10000); 1152 1153 ifp->if_timer = 5; 1154 } 1155 1156 static void 1157 dc_setfilt_admtek(struct dc_softc *sc) 1158 { 1159 struct ifnet *ifp; 1160 struct ifmultiaddr *ifma; 1161 int h = 0; 1162 u_int32_t hashes[2] = { 0, 0 }; 1163 1164 ifp = &sc->arpcom.ac_if; 1165 1166 /* Init our MAC address. */ 1167 CSR_WRITE_4(sc, DC_AL_PAR0, *(u_int32_t *)(&sc->arpcom.ac_enaddr[0])); 1168 CSR_WRITE_4(sc, DC_AL_PAR1, *(u_int32_t *)(&sc->arpcom.ac_enaddr[4])); 1169 1170 /* If we want promiscuous mode, set the allframes bit. */ 1171 if (ifp->if_flags & IFF_PROMISC) 1172 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC); 1173 else 1174 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC); 1175 1176 if (ifp->if_flags & IFF_ALLMULTI) 1177 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI); 1178 else 1179 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI); 1180 1181 /* First, zot all the existing hash bits. */ 1182 CSR_WRITE_4(sc, DC_AL_MAR0, 0); 1183 CSR_WRITE_4(sc, DC_AL_MAR1, 0); 1184 1185 /* 1186 * If we're already in promisc or allmulti mode, we 1187 * don't have to bother programming the multicast filter. 1188 */ 1189 if (ifp->if_flags & (IFF_PROMISC | IFF_ALLMULTI)) 1190 return; 1191 1192 /* Now program new ones. */ 1193 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 1194 if (ifma->ifma_addr->sa_family != AF_LINK) 1195 continue; 1196 if (DC_IS_CENTAUR(sc)) 1197 h = dc_crc_le(sc, LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 1198 else 1199 h = dc_crc_be(LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 1200 if (h < 32) 1201 hashes[0] |= (1 << h); 1202 else 1203 hashes[1] |= (1 << (h - 32)); 1204 } 1205 1206 CSR_WRITE_4(sc, DC_AL_MAR0, hashes[0]); 1207 CSR_WRITE_4(sc, DC_AL_MAR1, hashes[1]); 1208 } 1209 1210 static void 1211 dc_setfilt_asix(struct dc_softc *sc) 1212 { 1213 struct ifnet *ifp; 1214 struct ifmultiaddr *ifma; 1215 int h = 0; 1216 u_int32_t hashes[2] = { 0, 0 }; 1217 1218 ifp = &sc->arpcom.ac_if; 1219 1220 /* Init our MAC address */ 1221 CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_PAR0); 1222 CSR_WRITE_4(sc, DC_AX_FILTDATA, 1223 *(u_int32_t *)(&sc->arpcom.ac_enaddr[0])); 1224 CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_PAR1); 1225 CSR_WRITE_4(sc, DC_AX_FILTDATA, 1226 *(u_int32_t *)(&sc->arpcom.ac_enaddr[4])); 1227 1228 /* If we want promiscuous mode, set the allframes bit. */ 1229 if (ifp->if_flags & IFF_PROMISC) 1230 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC); 1231 else 1232 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC); 1233 1234 if (ifp->if_flags & IFF_ALLMULTI) 1235 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI); 1236 else 1237 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI); 1238 1239 /* 1240 * The ASIX chip has a special bit to enable reception 1241 * of broadcast frames. 1242 */ 1243 if (ifp->if_flags & IFF_BROADCAST) 1244 DC_SETBIT(sc, DC_NETCFG, DC_AX_NETCFG_RX_BROAD); 1245 else 1246 DC_CLRBIT(sc, DC_NETCFG, DC_AX_NETCFG_RX_BROAD); 1247 1248 /* first, zot all the existing hash bits */ 1249 CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_MAR0); 1250 CSR_WRITE_4(sc, DC_AX_FILTDATA, 0); 1251 CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_MAR1); 1252 CSR_WRITE_4(sc, DC_AX_FILTDATA, 0); 1253 1254 /* 1255 * If we're already in promisc or allmulti mode, we 1256 * don't have to bother programming the multicast filter. 1257 */ 1258 if (ifp->if_flags & (IFF_PROMISC | IFF_ALLMULTI)) 1259 return; 1260 1261 /* now program new ones */ 1262 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 1263 if (ifma->ifma_addr->sa_family != AF_LINK) 1264 continue; 1265 h = dc_crc_be(LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 1266 if (h < 32) 1267 hashes[0] |= (1 << h); 1268 else 1269 hashes[1] |= (1 << (h - 32)); 1270 } 1271 1272 CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_MAR0); 1273 CSR_WRITE_4(sc, DC_AX_FILTDATA, hashes[0]); 1274 CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_MAR1); 1275 CSR_WRITE_4(sc, DC_AX_FILTDATA, hashes[1]); 1276 } 1277 1278 static void 1279 dc_setfilt_xircom(struct dc_softc *sc) 1280 { 1281 struct ifnet *ifp; 1282 struct ifmultiaddr *ifma; 1283 struct dc_desc *sframe; 1284 u_int32_t h, *sp; 1285 int i; 1286 1287 ifp = &sc->arpcom.ac_if; 1288 DC_CLRBIT(sc, DC_NETCFG, (DC_NETCFG_TX_ON | DC_NETCFG_RX_ON)); 1289 1290 i = sc->dc_cdata.dc_tx_prod; 1291 DC_INC(sc->dc_cdata.dc_tx_prod, DC_TX_LIST_CNT); 1292 sc->dc_cdata.dc_tx_cnt++; 1293 sframe = &sc->dc_ldata->dc_tx_list[i]; 1294 sp = sc->dc_cdata.dc_sbuf; 1295 bzero(sp, DC_SFRAME_LEN); 1296 1297 sframe->dc_data = sc->dc_saddr; 1298 sframe->dc_ctl = DC_SFRAME_LEN | DC_TXCTL_SETUP | DC_TXCTL_TLINK | 1299 DC_FILTER_HASHPERF | DC_TXCTL_FINT; 1300 1301 sc->dc_cdata.dc_tx_chain[i] = (struct mbuf *)sc->dc_cdata.dc_sbuf; 1302 1303 /* If we want promiscuous mode, set the allframes bit. */ 1304 if (ifp->if_flags & IFF_PROMISC) 1305 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC); 1306 else 1307 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC); 1308 1309 if (ifp->if_flags & IFF_ALLMULTI) 1310 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI); 1311 else 1312 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI); 1313 1314 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 1315 if (ifma->ifma_addr->sa_family != AF_LINK) 1316 continue; 1317 h = dc_crc_le(sc, 1318 LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 1319 sp[h >> 4] |= 1 << (h & 0xF); 1320 } 1321 1322 if (ifp->if_flags & IFF_BROADCAST) { 1323 h = dc_crc_le(sc, (caddr_t)ifp->if_broadcastaddr); 1324 sp[h >> 4] |= 1 << (h & 0xF); 1325 } 1326 1327 /* Set our MAC address */ 1328 sp[0] = ((u_int16_t *)sc->arpcom.ac_enaddr)[0]; 1329 sp[1] = ((u_int16_t *)sc->arpcom.ac_enaddr)[1]; 1330 sp[2] = ((u_int16_t *)sc->arpcom.ac_enaddr)[2]; 1331 1332 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_TX_ON); 1333 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_ON); 1334 ifp->if_flags |= IFF_RUNNING; 1335 sframe->dc_status = DC_TXSTAT_OWN; 1336 CSR_WRITE_4(sc, DC_TXSTART, 0xFFFFFFFF); 1337 1338 /* 1339 * Wait some time... 1340 */ 1341 DELAY(1000); 1342 1343 ifp->if_timer = 5; 1344 } 1345 1346 static void 1347 dc_setfilt(struct dc_softc *sc) 1348 { 1349 1350 if (DC_IS_INTEL(sc) || DC_IS_MACRONIX(sc) || DC_IS_PNIC(sc) || 1351 DC_IS_PNICII(sc) || DC_IS_DAVICOM(sc) || DC_IS_CONEXANT(sc)) 1352 dc_setfilt_21143(sc); 1353 1354 if (DC_IS_ASIX(sc)) 1355 dc_setfilt_asix(sc); 1356 1357 if (DC_IS_ADMTEK(sc)) 1358 dc_setfilt_admtek(sc); 1359 1360 if (DC_IS_XIRCOM(sc)) 1361 dc_setfilt_xircom(sc); 1362 } 1363 1364 /* 1365 * In order to fiddle with the 'full-duplex' and '100Mbps' bits in 1366 * the netconfig register, we first have to put the transmit and/or 1367 * receive logic in the idle state. 1368 */ 1369 static void 1370 dc_setcfg(struct dc_softc *sc, int media) 1371 { 1372 int i, restart = 0, watchdogreg; 1373 u_int32_t isr; 1374 1375 if (IFM_SUBTYPE(media) == IFM_NONE) 1376 return; 1377 1378 if (CSR_READ_4(sc, DC_NETCFG) & (DC_NETCFG_TX_ON | DC_NETCFG_RX_ON)) { 1379 restart = 1; 1380 DC_CLRBIT(sc, DC_NETCFG, (DC_NETCFG_TX_ON | DC_NETCFG_RX_ON)); 1381 1382 for (i = 0; i < DC_TIMEOUT; i++) { 1383 isr = CSR_READ_4(sc, DC_ISR); 1384 if (isr & DC_ISR_TX_IDLE && 1385 ((isr & DC_ISR_RX_STATE) == DC_RXSTATE_STOPPED || 1386 (isr & DC_ISR_RX_STATE) == DC_RXSTATE_WAIT)) 1387 break; 1388 DELAY(10); 1389 } 1390 1391 if (i == DC_TIMEOUT) 1392 printf("dc%d: failed to force tx and " 1393 "rx to idle state\n", sc->dc_unit); 1394 } 1395 1396 if (IFM_SUBTYPE(media) == IFM_100_TX) { 1397 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_SPEEDSEL); 1398 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_HEARTBEAT); 1399 if (sc->dc_pmode == DC_PMODE_MII) { 1400 if (DC_IS_INTEL(sc)) { 1401 /* There's a write enable bit here that reads as 1. */ 1402 watchdogreg = CSR_READ_4(sc, DC_WATCHDOG); 1403 watchdogreg &= ~DC_WDOG_CTLWREN; 1404 watchdogreg |= DC_WDOG_JABBERDIS; 1405 CSR_WRITE_4(sc, DC_WATCHDOG, watchdogreg); 1406 } else { 1407 DC_SETBIT(sc, DC_WATCHDOG, DC_WDOG_JABBERDIS); 1408 } 1409 DC_CLRBIT(sc, DC_NETCFG, (DC_NETCFG_PCS | 1410 DC_NETCFG_PORTSEL | DC_NETCFG_SCRAMBLER)); 1411 if (sc->dc_type == DC_TYPE_98713) 1412 DC_SETBIT(sc, DC_NETCFG, (DC_NETCFG_PCS | 1413 DC_NETCFG_SCRAMBLER)); 1414 if (!DC_IS_DAVICOM(sc)) 1415 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL); 1416 DC_CLRBIT(sc, DC_10BTCTRL, 0xFFFF); 1417 if (DC_IS_INTEL(sc)) 1418 dc_apply_fixup(sc, IFM_AUTO); 1419 } else { 1420 if (DC_IS_PNIC(sc)) { 1421 DC_PN_GPIO_SETBIT(sc, DC_PN_GPIO_SPEEDSEL); 1422 DC_PN_GPIO_SETBIT(sc, DC_PN_GPIO_100TX_LOOP); 1423 DC_SETBIT(sc, DC_PN_NWAY, DC_PN_NWAY_SPEEDSEL); 1424 } 1425 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL); 1426 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PCS); 1427 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_SCRAMBLER); 1428 if (DC_IS_INTEL(sc)) 1429 dc_apply_fixup(sc, 1430 (media & IFM_GMASK) == IFM_FDX ? 1431 IFM_100_TX | IFM_FDX : IFM_100_TX); 1432 } 1433 } 1434 1435 if (IFM_SUBTYPE(media) == IFM_10_T) { 1436 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_SPEEDSEL); 1437 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_HEARTBEAT); 1438 if (sc->dc_pmode == DC_PMODE_MII) { 1439 /* There's a write enable bit here that reads as 1. */ 1440 if (DC_IS_INTEL(sc)) { 1441 watchdogreg = CSR_READ_4(sc, DC_WATCHDOG); 1442 watchdogreg &= ~DC_WDOG_CTLWREN; 1443 watchdogreg |= DC_WDOG_JABBERDIS; 1444 CSR_WRITE_4(sc, DC_WATCHDOG, watchdogreg); 1445 } else { 1446 DC_SETBIT(sc, DC_WATCHDOG, DC_WDOG_JABBERDIS); 1447 } 1448 DC_CLRBIT(sc, DC_NETCFG, (DC_NETCFG_PCS | 1449 DC_NETCFG_PORTSEL | DC_NETCFG_SCRAMBLER)); 1450 if (sc->dc_type == DC_TYPE_98713) 1451 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PCS); 1452 if (!DC_IS_DAVICOM(sc)) 1453 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL); 1454 DC_CLRBIT(sc, DC_10BTCTRL, 0xFFFF); 1455 if (DC_IS_INTEL(sc)) 1456 dc_apply_fixup(sc, IFM_AUTO); 1457 } else { 1458 if (DC_IS_PNIC(sc)) { 1459 DC_PN_GPIO_CLRBIT(sc, DC_PN_GPIO_SPEEDSEL); 1460 DC_PN_GPIO_SETBIT(sc, DC_PN_GPIO_100TX_LOOP); 1461 DC_CLRBIT(sc, DC_PN_NWAY, DC_PN_NWAY_SPEEDSEL); 1462 } 1463 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL); 1464 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_PCS); 1465 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_SCRAMBLER); 1466 if (DC_IS_INTEL(sc)) { 1467 DC_CLRBIT(sc, DC_SIARESET, DC_SIA_RESET); 1468 DC_CLRBIT(sc, DC_10BTCTRL, 0xFFFF); 1469 if ((media & IFM_GMASK) == IFM_FDX) 1470 DC_SETBIT(sc, DC_10BTCTRL, 0x7F3D); 1471 else 1472 DC_SETBIT(sc, DC_10BTCTRL, 0x7F3F); 1473 DC_SETBIT(sc, DC_SIARESET, DC_SIA_RESET); 1474 DC_CLRBIT(sc, DC_10BTCTRL, 1475 DC_TCTL_AUTONEGENBL); 1476 dc_apply_fixup(sc, 1477 (media & IFM_GMASK) == IFM_FDX ? 1478 IFM_10_T | IFM_FDX : IFM_10_T); 1479 DELAY(20000); 1480 } 1481 } 1482 } 1483 1484 /* 1485 * If this is a Davicom DM9102A card with a DM9801 HomePNA 1486 * PHY and we want HomePNA mode, set the portsel bit to turn 1487 * on the external MII port. 1488 */ 1489 if (DC_IS_DAVICOM(sc)) { 1490 if (IFM_SUBTYPE(media) == IFM_HPNA_1) { 1491 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL); 1492 sc->dc_link = 1; 1493 } else { 1494 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL); 1495 } 1496 } 1497 1498 if ((media & IFM_GMASK) == IFM_FDX) { 1499 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_FULLDUPLEX); 1500 if (sc->dc_pmode == DC_PMODE_SYM && DC_IS_PNIC(sc)) 1501 DC_SETBIT(sc, DC_PN_NWAY, DC_PN_NWAY_DUPLEX); 1502 } else { 1503 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_FULLDUPLEX); 1504 if (sc->dc_pmode == DC_PMODE_SYM && DC_IS_PNIC(sc)) 1505 DC_CLRBIT(sc, DC_PN_NWAY, DC_PN_NWAY_DUPLEX); 1506 } 1507 1508 if (restart) 1509 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_TX_ON | DC_NETCFG_RX_ON); 1510 } 1511 1512 static void 1513 dc_reset(struct dc_softc *sc) 1514 { 1515 int i; 1516 1517 DC_SETBIT(sc, DC_BUSCTL, DC_BUSCTL_RESET); 1518 1519 for (i = 0; i < DC_TIMEOUT; i++) { 1520 DELAY(10); 1521 if (!(CSR_READ_4(sc, DC_BUSCTL) & DC_BUSCTL_RESET)) 1522 break; 1523 } 1524 1525 if (DC_IS_ASIX(sc) || DC_IS_ADMTEK(sc) || DC_IS_CONEXANT(sc) || 1526 DC_IS_XIRCOM(sc) || DC_IS_INTEL(sc)) { 1527 DELAY(10000); 1528 DC_CLRBIT(sc, DC_BUSCTL, DC_BUSCTL_RESET); 1529 i = 0; 1530 } 1531 1532 if (i == DC_TIMEOUT) 1533 printf("dc%d: reset never completed!\n", sc->dc_unit); 1534 1535 /* Wait a little while for the chip to get its brains in order. */ 1536 DELAY(1000); 1537 1538 CSR_WRITE_4(sc, DC_IMR, 0x00000000); 1539 CSR_WRITE_4(sc, DC_BUSCTL, 0x00000000); 1540 CSR_WRITE_4(sc, DC_NETCFG, 0x00000000); 1541 1542 /* 1543 * Bring the SIA out of reset. In some cases, it looks 1544 * like failing to unreset the SIA soon enough gets it 1545 * into a state where it will never come out of reset 1546 * until we reset the whole chip again. 1547 */ 1548 if (DC_IS_INTEL(sc)) { 1549 DC_SETBIT(sc, DC_SIARESET, DC_SIA_RESET); 1550 CSR_WRITE_4(sc, DC_10BTCTRL, 0); 1551 CSR_WRITE_4(sc, DC_WATCHDOG, 0); 1552 } 1553 } 1554 1555 static struct dc_type * 1556 dc_devtype(device_t dev) 1557 { 1558 struct dc_type *t; 1559 u_int32_t rev; 1560 1561 t = dc_devs; 1562 1563 while (t->dc_name != NULL) { 1564 if ((pci_get_vendor(dev) == t->dc_vid) && 1565 (pci_get_device(dev) == t->dc_did)) { 1566 /* Check the PCI revision */ 1567 rev = pci_read_config(dev, DC_PCI_CFRV, 4) & 0xFF; 1568 if (t->dc_did == DC_DEVICEID_98713 && 1569 rev >= DC_REVISION_98713A) 1570 t++; 1571 if (t->dc_did == DC_DEVICEID_98713_CP && 1572 rev >= DC_REVISION_98713A) 1573 t++; 1574 if (t->dc_did == DC_DEVICEID_987x5 && 1575 rev >= DC_REVISION_98715AEC_C) 1576 t++; 1577 if (t->dc_did == DC_DEVICEID_987x5 && 1578 rev >= DC_REVISION_98725) 1579 t++; 1580 if (t->dc_did == DC_DEVICEID_AX88140A && 1581 rev >= DC_REVISION_88141) 1582 t++; 1583 if (t->dc_did == DC_DEVICEID_82C168 && 1584 rev >= DC_REVISION_82C169) 1585 t++; 1586 if (t->dc_did == DC_DEVICEID_DM9102 && 1587 rev >= DC_REVISION_DM9102A) 1588 t++; 1589 return (t); 1590 } 1591 t++; 1592 } 1593 1594 return (NULL); 1595 } 1596 1597 /* 1598 * Probe for a 21143 or clone chip. Check the PCI vendor and device 1599 * IDs against our list and return a device name if we find a match. 1600 * We do a little bit of extra work to identify the exact type of 1601 * chip. The MX98713 and MX98713A have the same PCI vendor/device ID, 1602 * but different revision IDs. The same is true for 98715/98715A 1603 * chips and the 98725, as well as the ASIX and ADMtek chips. In some 1604 * cases, the exact chip revision affects driver behavior. 1605 */ 1606 static int 1607 dc_probe(device_t dev) 1608 { 1609 struct dc_type *t; 1610 1611 t = dc_devtype(dev); 1612 1613 if (t != NULL) { 1614 device_set_desc(dev, t->dc_name); 1615 return (0); 1616 } 1617 1618 return (ENXIO); 1619 } 1620 1621 #ifndef BURN_BRIDGES 1622 static void 1623 dc_acpi(device_t dev) 1624 { 1625 int unit; 1626 u_int32_t iobase, membase, irq; 1627 1628 unit = device_get_unit(dev); 1629 1630 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) { 1631 /* Save important PCI config data. */ 1632 iobase = pci_read_config(dev, DC_PCI_CFBIO, 4); 1633 membase = pci_read_config(dev, DC_PCI_CFBMA, 4); 1634 irq = pci_read_config(dev, DC_PCI_CFIT, 4); 1635 1636 /* Reset the power state. */ 1637 printf("dc%d: chip is in D%d power mode " 1638 "-- setting to D0\n", unit, 1639 pci_get_powerstate(dev)); 1640 pci_set_powerstate(dev, PCI_POWERSTATE_D0); 1641 1642 /* Restore PCI config data. */ 1643 pci_write_config(dev, DC_PCI_CFBIO, iobase, 4); 1644 pci_write_config(dev, DC_PCI_CFBMA, membase, 4); 1645 pci_write_config(dev, DC_PCI_CFIT, irq, 4); 1646 } 1647 } 1648 #endif 1649 1650 static void 1651 dc_apply_fixup(struct dc_softc *sc, int media) 1652 { 1653 struct dc_mediainfo *m; 1654 u_int8_t *p; 1655 int i; 1656 u_int32_t reg; 1657 1658 m = sc->dc_mi; 1659 1660 while (m != NULL) { 1661 if (m->dc_media == media) 1662 break; 1663 m = m->dc_next; 1664 } 1665 1666 if (m == NULL) 1667 return; 1668 1669 for (i = 0, p = m->dc_reset_ptr; i < m->dc_reset_len; i++, p += 2) { 1670 reg = (p[0] | (p[1] << 8)) << 16; 1671 CSR_WRITE_4(sc, DC_WATCHDOG, reg); 1672 } 1673 1674 for (i = 0, p = m->dc_gp_ptr; i < m->dc_gp_len; i++, p += 2) { 1675 reg = (p[0] | (p[1] << 8)) << 16; 1676 CSR_WRITE_4(sc, DC_WATCHDOG, reg); 1677 } 1678 } 1679 1680 static void 1681 dc_decode_leaf_sia(struct dc_softc *sc, struct dc_eblock_sia *l) 1682 { 1683 struct dc_mediainfo *m; 1684 1685 m = malloc(sizeof(struct dc_mediainfo), M_DEVBUF, M_NOWAIT | M_ZERO); 1686 if (l->dc_sia_code == DC_SIA_CODE_10BT) 1687 m->dc_media = IFM_10_T; 1688 1689 if (l->dc_sia_code == DC_SIA_CODE_10BT_FDX) 1690 m->dc_media = IFM_10_T | IFM_FDX; 1691 1692 if (l->dc_sia_code == DC_SIA_CODE_10B2) 1693 m->dc_media = IFM_10_2; 1694 1695 if (l->dc_sia_code == DC_SIA_CODE_10B5) 1696 m->dc_media = IFM_10_5; 1697 1698 m->dc_gp_len = 2; 1699 m->dc_gp_ptr = (u_int8_t *)&l->dc_sia_gpio_ctl; 1700 1701 m->dc_next = sc->dc_mi; 1702 sc->dc_mi = m; 1703 1704 sc->dc_pmode = DC_PMODE_SIA; 1705 } 1706 1707 static void 1708 dc_decode_leaf_sym(struct dc_softc *sc, struct dc_eblock_sym *l) 1709 { 1710 struct dc_mediainfo *m; 1711 1712 m = malloc(sizeof(struct dc_mediainfo), M_DEVBUF, M_NOWAIT | M_ZERO); 1713 if (l->dc_sym_code == DC_SYM_CODE_100BT) 1714 m->dc_media = IFM_100_TX; 1715 1716 if (l->dc_sym_code == DC_SYM_CODE_100BT_FDX) 1717 m->dc_media = IFM_100_TX | IFM_FDX; 1718 1719 m->dc_gp_len = 2; 1720 m->dc_gp_ptr = (u_int8_t *)&l->dc_sym_gpio_ctl; 1721 1722 m->dc_next = sc->dc_mi; 1723 sc->dc_mi = m; 1724 1725 sc->dc_pmode = DC_PMODE_SYM; 1726 } 1727 1728 static void 1729 dc_decode_leaf_mii(struct dc_softc *sc, struct dc_eblock_mii *l) 1730 { 1731 struct dc_mediainfo *m; 1732 u_int8_t *p; 1733 1734 m = malloc(sizeof(struct dc_mediainfo), M_DEVBUF, M_NOWAIT | M_ZERO); 1735 /* We abuse IFM_AUTO to represent MII. */ 1736 m->dc_media = IFM_AUTO; 1737 m->dc_gp_len = l->dc_gpr_len; 1738 1739 p = (u_int8_t *)l; 1740 p += sizeof(struct dc_eblock_mii); 1741 m->dc_gp_ptr = p; 1742 p += 2 * l->dc_gpr_len; 1743 m->dc_reset_len = *p; 1744 p++; 1745 m->dc_reset_ptr = p; 1746 1747 m->dc_next = sc->dc_mi; 1748 sc->dc_mi = m; 1749 } 1750 1751 static void 1752 dc_read_srom(struct dc_softc *sc, int bits) 1753 { 1754 int size; 1755 1756 size = 2 << bits; 1757 sc->dc_srom = malloc(size, M_DEVBUF, M_NOWAIT); 1758 dc_read_eeprom(sc, (caddr_t)sc->dc_srom, 0, (size / 2), 0); 1759 } 1760 1761 static void 1762 dc_parse_21143_srom(struct dc_softc *sc) 1763 { 1764 struct dc_leaf_hdr *lhdr; 1765 struct dc_eblock_hdr *hdr; 1766 int have_mii, i, loff; 1767 char *ptr; 1768 1769 have_mii = 0; 1770 loff = sc->dc_srom[27]; 1771 lhdr = (struct dc_leaf_hdr *)&(sc->dc_srom[loff]); 1772 1773 ptr = (char *)lhdr; 1774 ptr += sizeof(struct dc_leaf_hdr) - 1; 1775 /* 1776 * Look if we got a MII media block. 1777 */ 1778 for (i = 0; i < lhdr->dc_mcnt; i++) { 1779 hdr = (struct dc_eblock_hdr *)ptr; 1780 if (hdr->dc_type == DC_EBLOCK_MII) 1781 have_mii++; 1782 1783 ptr += (hdr->dc_len & 0x7F); 1784 ptr++; 1785 } 1786 1787 /* 1788 * Do the same thing again. Only use SIA and SYM media 1789 * blocks if no MII media block is available. 1790 */ 1791 ptr = (char *)lhdr; 1792 ptr += sizeof(struct dc_leaf_hdr) - 1; 1793 for (i = 0; i < lhdr->dc_mcnt; i++) { 1794 hdr = (struct dc_eblock_hdr *)ptr; 1795 switch (hdr->dc_type) { 1796 case DC_EBLOCK_MII: 1797 dc_decode_leaf_mii(sc, (struct dc_eblock_mii *)hdr); 1798 break; 1799 case DC_EBLOCK_SIA: 1800 if (! have_mii) 1801 dc_decode_leaf_sia(sc, 1802 (struct dc_eblock_sia *)hdr); 1803 break; 1804 case DC_EBLOCK_SYM: 1805 if (! have_mii) 1806 dc_decode_leaf_sym(sc, 1807 (struct dc_eblock_sym *)hdr); 1808 break; 1809 default: 1810 /* Don't care. Yet. */ 1811 break; 1812 } 1813 ptr += (hdr->dc_len & 0x7F); 1814 ptr++; 1815 } 1816 } 1817 1818 static void 1819 dc_dma_map_addr(void *arg, bus_dma_segment_t *segs, int nseg, int error) 1820 { 1821 u_int32_t *paddr; 1822 1823 KASSERT(nseg == 1, ("wrong number of segments, should be 1")); 1824 paddr = arg; 1825 *paddr = segs->ds_addr; 1826 } 1827 1828 /* 1829 * Attach the interface. Allocate softc structures, do ifmedia 1830 * setup and ethernet/BPF attach. 1831 */ 1832 static int 1833 dc_attach(device_t dev) 1834 { 1835 int tmp = 0; 1836 u_char eaddr[ETHER_ADDR_LEN]; 1837 u_int32_t command; 1838 struct dc_softc *sc; 1839 struct ifnet *ifp; 1840 u_int32_t revision; 1841 int unit, error = 0, rid, mac_offset; 1842 int i; 1843 u_int8_t *mac; 1844 1845 sc = device_get_softc(dev); 1846 unit = device_get_unit(dev); 1847 1848 mtx_init(&sc->dc_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 1849 MTX_DEF | MTX_RECURSE); 1850 #ifndef BURN_BRIDGES 1851 /* 1852 * Handle power management nonsense. 1853 */ 1854 dc_acpi(dev); 1855 #endif 1856 /* 1857 * Map control/status registers. 1858 */ 1859 pci_enable_busmaster(dev); 1860 1861 rid = DC_RID; 1862 sc->dc_res = bus_alloc_resource(dev, DC_RES, &rid, 1863 0, ~0, 1, RF_ACTIVE); 1864 1865 if (sc->dc_res == NULL) { 1866 printf("dc%d: couldn't map ports/memory\n", unit); 1867 error = ENXIO; 1868 goto fail; 1869 } 1870 1871 sc->dc_btag = rman_get_bustag(sc->dc_res); 1872 sc->dc_bhandle = rman_get_bushandle(sc->dc_res); 1873 1874 /* Allocate interrupt. */ 1875 rid = 0; 1876 sc->dc_irq = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, 0, ~0, 1, 1877 RF_SHAREABLE | RF_ACTIVE); 1878 1879 if (sc->dc_irq == NULL) { 1880 printf("dc%d: couldn't map interrupt\n", unit); 1881 error = ENXIO; 1882 goto fail; 1883 } 1884 1885 /* Need this info to decide on a chip type. */ 1886 sc->dc_info = dc_devtype(dev); 1887 revision = pci_read_config(dev, DC_PCI_CFRV, 4) & 0x000000FF; 1888 1889 /* Get the eeprom width, but PNIC and XIRCOM have diff eeprom */ 1890 if (sc->dc_info->dc_did != DC_DEVICEID_82C168 && 1891 sc->dc_info->dc_did != DC_DEVICEID_X3201) 1892 dc_eeprom_width(sc); 1893 1894 switch (sc->dc_info->dc_did) { 1895 case DC_DEVICEID_21143: 1896 sc->dc_type = DC_TYPE_21143; 1897 sc->dc_flags |= DC_TX_POLL | DC_TX_USE_TX_INTR; 1898 sc->dc_flags |= DC_REDUCED_MII_POLL; 1899 /* Save EEPROM contents so we can parse them later. */ 1900 dc_read_srom(sc, sc->dc_romwidth); 1901 break; 1902 case DC_DEVICEID_DM9009: 1903 case DC_DEVICEID_DM9100: 1904 case DC_DEVICEID_DM9102: 1905 sc->dc_type = DC_TYPE_DM9102; 1906 sc->dc_flags |= DC_TX_COALESCE | DC_TX_INTR_ALWAYS; 1907 sc->dc_flags |= DC_REDUCED_MII_POLL | DC_TX_STORENFWD; 1908 sc->dc_pmode = DC_PMODE_MII; 1909 /* Increase the latency timer value. */ 1910 command = pci_read_config(dev, DC_PCI_CFLT, 4); 1911 command &= 0xFFFF00FF; 1912 command |= 0x00008000; 1913 pci_write_config(dev, DC_PCI_CFLT, command, 4); 1914 break; 1915 case DC_DEVICEID_AL981: 1916 sc->dc_type = DC_TYPE_AL981; 1917 sc->dc_flags |= DC_TX_USE_TX_INTR; 1918 sc->dc_flags |= DC_TX_ADMTEK_WAR; 1919 sc->dc_pmode = DC_PMODE_MII; 1920 dc_read_srom(sc, sc->dc_romwidth); 1921 break; 1922 case DC_DEVICEID_AN985: 1923 case DC_DEVICEID_ADM9511: 1924 case DC_DEVICEID_ADM9513: 1925 case DC_DEVICEID_FE2500: 1926 case DC_DEVICEID_EN2242: 1927 case DC_DEVICEID_HAWKING_PN672TX: 1928 case DC_DEVICEID_3CSOHOB: 1929 sc->dc_type = DC_TYPE_AN985; 1930 sc->dc_flags |= DC_64BIT_HASH; 1931 sc->dc_flags |= DC_TX_USE_TX_INTR; 1932 sc->dc_flags |= DC_TX_ADMTEK_WAR; 1933 sc->dc_pmode = DC_PMODE_MII; 1934 dc_read_srom(sc, sc->dc_romwidth); 1935 break; 1936 case DC_DEVICEID_98713: 1937 case DC_DEVICEID_98713_CP: 1938 if (revision < DC_REVISION_98713A) { 1939 sc->dc_type = DC_TYPE_98713; 1940 } 1941 if (revision >= DC_REVISION_98713A) { 1942 sc->dc_type = DC_TYPE_98713A; 1943 sc->dc_flags |= DC_21143_NWAY; 1944 } 1945 sc->dc_flags |= DC_REDUCED_MII_POLL; 1946 sc->dc_flags |= DC_TX_POLL | DC_TX_USE_TX_INTR; 1947 break; 1948 case DC_DEVICEID_987x5: 1949 case DC_DEVICEID_EN1217: 1950 /* 1951 * Macronix MX98715AEC-C/D/E parts have only a 1952 * 128-bit hash table. We need to deal with these 1953 * in the same manner as the PNIC II so that we 1954 * get the right number of bits out of the 1955 * CRC routine. 1956 */ 1957 if (revision >= DC_REVISION_98715AEC_C && 1958 revision < DC_REVISION_98725) 1959 sc->dc_flags |= DC_128BIT_HASH; 1960 sc->dc_type = DC_TYPE_987x5; 1961 sc->dc_flags |= DC_TX_POLL | DC_TX_USE_TX_INTR; 1962 sc->dc_flags |= DC_REDUCED_MII_POLL | DC_21143_NWAY; 1963 break; 1964 case DC_DEVICEID_98727: 1965 sc->dc_type = DC_TYPE_987x5; 1966 sc->dc_flags |= DC_TX_POLL | DC_TX_USE_TX_INTR; 1967 sc->dc_flags |= DC_REDUCED_MII_POLL | DC_21143_NWAY; 1968 break; 1969 case DC_DEVICEID_82C115: 1970 sc->dc_type = DC_TYPE_PNICII; 1971 sc->dc_flags |= DC_TX_POLL | DC_TX_USE_TX_INTR | DC_128BIT_HASH; 1972 sc->dc_flags |= DC_REDUCED_MII_POLL | DC_21143_NWAY; 1973 break; 1974 case DC_DEVICEID_82C168: 1975 sc->dc_type = DC_TYPE_PNIC; 1976 sc->dc_flags |= DC_TX_STORENFWD | DC_TX_INTR_ALWAYS; 1977 sc->dc_flags |= DC_PNIC_RX_BUG_WAR; 1978 sc->dc_pnic_rx_buf = malloc(DC_RXLEN * 5, M_DEVBUF, M_NOWAIT); 1979 if (revision < DC_REVISION_82C169) 1980 sc->dc_pmode = DC_PMODE_SYM; 1981 break; 1982 case DC_DEVICEID_AX88140A: 1983 sc->dc_type = DC_TYPE_ASIX; 1984 sc->dc_flags |= DC_TX_USE_TX_INTR | DC_TX_INTR_FIRSTFRAG; 1985 sc->dc_flags |= DC_REDUCED_MII_POLL; 1986 sc->dc_pmode = DC_PMODE_MII; 1987 break; 1988 case DC_DEVICEID_X3201: 1989 sc->dc_type = DC_TYPE_XIRCOM; 1990 sc->dc_flags |= DC_TX_INTR_ALWAYS | DC_TX_COALESCE | 1991 DC_TX_ALIGN; 1992 /* 1993 * We don't actually need to coalesce, but we're doing 1994 * it to obtain a double word aligned buffer. 1995 * The DC_TX_COALESCE flag is required. 1996 */ 1997 sc->dc_pmode = DC_PMODE_MII; 1998 break; 1999 case DC_DEVICEID_RS7112: 2000 sc->dc_type = DC_TYPE_CONEXANT; 2001 sc->dc_flags |= DC_TX_INTR_ALWAYS; 2002 sc->dc_flags |= DC_REDUCED_MII_POLL; 2003 sc->dc_pmode = DC_PMODE_MII; 2004 dc_read_srom(sc, sc->dc_romwidth); 2005 break; 2006 default: 2007 printf("dc%d: unknown device: %x\n", sc->dc_unit, 2008 sc->dc_info->dc_did); 2009 break; 2010 } 2011 2012 /* Save the cache line size. */ 2013 if (DC_IS_DAVICOM(sc)) 2014 sc->dc_cachesize = 0; 2015 else 2016 sc->dc_cachesize = pci_read_config(dev, 2017 DC_PCI_CFLT, 4) & 0xFF; 2018 2019 /* Reset the adapter. */ 2020 dc_reset(sc); 2021 2022 /* Take 21143 out of snooze mode */ 2023 if (DC_IS_INTEL(sc) || DC_IS_XIRCOM(sc)) { 2024 command = pci_read_config(dev, DC_PCI_CFDD, 4); 2025 command &= ~(DC_CFDD_SNOOZE_MODE | DC_CFDD_SLEEP_MODE); 2026 pci_write_config(dev, DC_PCI_CFDD, command, 4); 2027 } 2028 2029 /* 2030 * Try to learn something about the supported media. 2031 * We know that ASIX and ADMtek and Davicom devices 2032 * will *always* be using MII media, so that's a no-brainer. 2033 * The tricky ones are the Macronix/PNIC II and the 2034 * Intel 21143. 2035 */ 2036 if (DC_IS_INTEL(sc)) 2037 dc_parse_21143_srom(sc); 2038 else if (DC_IS_MACRONIX(sc) || DC_IS_PNICII(sc)) { 2039 if (sc->dc_type == DC_TYPE_98713) 2040 sc->dc_pmode = DC_PMODE_MII; 2041 else 2042 sc->dc_pmode = DC_PMODE_SYM; 2043 } else if (!sc->dc_pmode) 2044 sc->dc_pmode = DC_PMODE_MII; 2045 2046 /* 2047 * Get station address from the EEPROM. 2048 */ 2049 switch(sc->dc_type) { 2050 case DC_TYPE_98713: 2051 case DC_TYPE_98713A: 2052 case DC_TYPE_987x5: 2053 case DC_TYPE_PNICII: 2054 dc_read_eeprom(sc, (caddr_t)&mac_offset, 2055 (DC_EE_NODEADDR_OFFSET / 2), 1, 0); 2056 dc_read_eeprom(sc, (caddr_t)&eaddr, (mac_offset / 2), 3, 0); 2057 break; 2058 case DC_TYPE_PNIC: 2059 dc_read_eeprom(sc, (caddr_t)&eaddr, 0, 3, 1); 2060 break; 2061 case DC_TYPE_DM9102: 2062 case DC_TYPE_21143: 2063 case DC_TYPE_ASIX: 2064 dc_read_eeprom(sc, (caddr_t)&eaddr, DC_EE_NODEADDR, 3, 0); 2065 break; 2066 case DC_TYPE_AL981: 2067 case DC_TYPE_AN985: 2068 bcopy(sc->dc_srom + DC_AL_EE_NODEADDR, &eaddr, 2069 ETHER_ADDR_LEN); 2070 dc_read_eeprom(sc, (caddr_t)&eaddr, DC_AL_EE_NODEADDR, 3, 0); 2071 break; 2072 case DC_TYPE_CONEXANT: 2073 bcopy(sc->dc_srom + DC_CONEXANT_EE_NODEADDR, &eaddr, 2074 ETHER_ADDR_LEN); 2075 break; 2076 case DC_TYPE_XIRCOM: 2077 /* The MAC comes from the CIS. */ 2078 mac = pci_get_ether(dev); 2079 if (!mac) { 2080 device_printf(dev, "No station address in CIS!\n"); 2081 error = ENXIO; 2082 goto fail; 2083 } 2084 bcopy(mac, eaddr, ETHER_ADDR_LEN); 2085 break; 2086 default: 2087 dc_read_eeprom(sc, (caddr_t)&eaddr, DC_EE_NODEADDR, 3, 0); 2088 break; 2089 } 2090 2091 /* 2092 * A 21143 or clone chip was detected. Inform the world. 2093 */ 2094 printf("dc%d: Ethernet address: %6D\n", unit, eaddr, ":"); 2095 2096 sc->dc_unit = unit; 2097 bcopy(eaddr, &sc->arpcom.ac_enaddr, ETHER_ADDR_LEN); 2098 2099 /* Allocate a busdma tag and DMA safe memory for TX/RX descriptors. */ 2100 error = bus_dma_tag_create(NULL, PAGE_SIZE, 0, BUS_SPACE_MAXADDR_32BIT, 2101 BUS_SPACE_MAXADDR, NULL, NULL, sizeof(struct dc_list_data), 1, 2102 sizeof(struct dc_list_data), 0, NULL, NULL, &sc->dc_ltag); 2103 if (error) { 2104 printf("dc%d: failed to allocate busdma tag\n", unit); 2105 error = ENXIO; 2106 goto fail; 2107 } 2108 error = bus_dmamem_alloc(sc->dc_ltag, (void **)&sc->dc_ldata, 2109 BUS_DMA_NOWAIT, &sc->dc_lmap); 2110 if (error) { 2111 printf("dc%d: failed to allocate DMA safe memory\n", unit); 2112 error = ENXIO; 2113 goto fail; 2114 } 2115 error = bus_dmamap_load(sc->dc_ltag, sc->dc_lmap, sc->dc_ldata, 2116 sizeof(struct dc_list_data), dc_dma_map_addr, &sc->dc_laddr, 2117 BUS_DMA_NOWAIT); 2118 if (error) { 2119 printf("dc%d: cannot get address of the descriptors\n", unit); 2120 error = ENXIO; 2121 goto fail; 2122 } 2123 bzero(sc->dc_ldata, sizeof(struct dc_list_data)); 2124 2125 /* 2126 * Allocate a busdma tag and DMA safe memory for the multicast 2127 * setup frame. 2128 */ 2129 error = bus_dma_tag_create(NULL, PAGE_SIZE, 0, BUS_SPACE_MAXADDR_32BIT, 2130 BUS_SPACE_MAXADDR, NULL, NULL, DC_SFRAME_LEN + DC_MIN_FRAMELEN, 1, 2131 DC_SFRAME_LEN + DC_MIN_FRAMELEN, 0, NULL, NULL, &sc->dc_stag); 2132 if (error) { 2133 printf("dc%d: failed to allocate busdma tag\n", unit); 2134 error = ENXIO; 2135 goto fail; 2136 } 2137 error = bus_dmamem_alloc(sc->dc_stag, (void **)&sc->dc_cdata.dc_sbuf, 2138 BUS_DMA_NOWAIT, &sc->dc_smap); 2139 if (error) { 2140 printf("dc%d: failed to allocate DMA safe memory\n", unit); 2141 error = ENXIO; 2142 goto fail; 2143 } 2144 error = bus_dmamap_load(sc->dc_stag, sc->dc_smap, sc->dc_cdata.dc_sbuf, 2145 DC_SFRAME_LEN, dc_dma_map_addr, &sc->dc_saddr, BUS_DMA_NOWAIT); 2146 if (error) { 2147 printf("dc%d: cannot get address of the descriptors\n", unit); 2148 error = ENXIO; 2149 goto fail; 2150 } 2151 2152 /* Allocate a busdma tag for mbufs. */ 2153 error = bus_dma_tag_create(NULL, PAGE_SIZE, 0, BUS_SPACE_MAXADDR_32BIT, 2154 BUS_SPACE_MAXADDR, NULL, NULL, MCLBYTES * DC_TX_LIST_CNT, 2155 DC_TX_LIST_CNT, MCLBYTES, 0, NULL, NULL, &sc->dc_mtag); 2156 if (error) { 2157 printf("dc%d: failed to allocate busdma tag\n", unit); 2158 error = ENXIO; 2159 goto fail; 2160 } 2161 2162 /* Create the TX/RX busdma maps. */ 2163 for (i = 0; i < DC_TX_LIST_CNT; i++) { 2164 error = bus_dmamap_create(sc->dc_mtag, 0, 2165 &sc->dc_cdata.dc_tx_map[i]); 2166 if (error) { 2167 printf("dc%d: failed to init TX ring\n", unit); 2168 error = ENXIO; 2169 goto fail; 2170 } 2171 } 2172 for (i = 0; i < DC_RX_LIST_CNT; i++) { 2173 error = bus_dmamap_create(sc->dc_mtag, 0, 2174 &sc->dc_cdata.dc_rx_map[i]); 2175 if (error) { 2176 printf("dc%d: failed to init RX ring\n", unit); 2177 error = ENXIO; 2178 goto fail; 2179 } 2180 } 2181 error = bus_dmamap_create(sc->dc_mtag, 0, &sc->dc_sparemap); 2182 if (error) { 2183 printf("dc%d: failed to init RX ring\n", unit); 2184 error = ENXIO; 2185 goto fail; 2186 } 2187 2188 ifp = &sc->arpcom.ac_if; 2189 ifp->if_softc = sc; 2190 ifp->if_unit = unit; 2191 ifp->if_name = "dc"; 2192 /* XXX: bleah, MTU gets overwritten in ether_ifattach() */ 2193 ifp->if_mtu = ETHERMTU; 2194 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 2195 ifp->if_ioctl = dc_ioctl; 2196 ifp->if_start = dc_start; 2197 ifp->if_watchdog = dc_watchdog; 2198 ifp->if_init = dc_init; 2199 ifp->if_baudrate = 10000000; 2200 ifp->if_snd.ifq_maxlen = DC_TX_LIST_CNT - 1; 2201 2202 /* 2203 * Do MII setup. If this is a 21143, check for a PHY on the 2204 * MII bus after applying any necessary fixups to twiddle the 2205 * GPIO bits. If we don't end up finding a PHY, restore the 2206 * old selection (SIA only or SIA/SYM) and attach the dcphy 2207 * driver instead. 2208 */ 2209 if (DC_IS_INTEL(sc)) { 2210 dc_apply_fixup(sc, IFM_AUTO); 2211 tmp = sc->dc_pmode; 2212 sc->dc_pmode = DC_PMODE_MII; 2213 } 2214 2215 error = mii_phy_probe(dev, &sc->dc_miibus, 2216 dc_ifmedia_upd, dc_ifmedia_sts); 2217 2218 if (error && DC_IS_INTEL(sc)) { 2219 sc->dc_pmode = tmp; 2220 if (sc->dc_pmode != DC_PMODE_SIA) 2221 sc->dc_pmode = DC_PMODE_SYM; 2222 sc->dc_flags |= DC_21143_NWAY; 2223 mii_phy_probe(dev, &sc->dc_miibus, 2224 dc_ifmedia_upd, dc_ifmedia_sts); 2225 /* 2226 * For non-MII cards, we need to have the 21143 2227 * drive the LEDs. Except there are some systems 2228 * like the NEC VersaPro NoteBook PC which have no 2229 * LEDs, and twiddling these bits has adverse effects 2230 * on them. (I.e. you suddenly can't get a link.) 2231 */ 2232 if (pci_read_config(dev, DC_PCI_CSID, 4) != 0x80281033) 2233 sc->dc_flags |= DC_TULIP_LEDS; 2234 error = 0; 2235 } 2236 2237 if (error) { 2238 printf("dc%d: MII without any PHY!\n", sc->dc_unit); 2239 goto fail; 2240 } 2241 2242 if (DC_IS_XIRCOM(sc)) { 2243 /* 2244 * setup General Purpose Port mode and data so the tulip 2245 * can talk to the MII. 2246 */ 2247 CSR_WRITE_4(sc, DC_SIAGP, DC_SIAGP_WRITE_EN | DC_SIAGP_INT1_EN | 2248 DC_SIAGP_MD_GP2_OUTPUT | DC_SIAGP_MD_GP0_OUTPUT); 2249 DELAY(10); 2250 CSR_WRITE_4(sc, DC_SIAGP, DC_SIAGP_INT1_EN | 2251 DC_SIAGP_MD_GP2_OUTPUT | DC_SIAGP_MD_GP0_OUTPUT); 2252 DELAY(10); 2253 } 2254 2255 if (DC_IS_ADMTEK(sc)) { 2256 /* 2257 * Set automatic TX underrun recovery for the ADMtek chips 2258 */ 2259 DC_SETBIT(sc, DC_AL_CR, DC_AL_CR_ATUR); 2260 } 2261 2262 /* 2263 * Tell the upper layer(s) we support long frames. 2264 */ 2265 ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header); 2266 ifp->if_capabilities |= IFCAP_VLAN_MTU; 2267 2268 callout_init(&sc->dc_stat_ch, IS_MPSAFE); 2269 2270 #ifdef SRM_MEDIA 2271 sc->dc_srm_media = 0; 2272 2273 /* Remember the SRM console media setting */ 2274 if (DC_IS_INTEL(sc)) { 2275 command = pci_read_config(dev, DC_PCI_CFDD, 4); 2276 command &= ~(DC_CFDD_SNOOZE_MODE | DC_CFDD_SLEEP_MODE); 2277 switch ((command >> 8) & 0xff) { 2278 case 3: 2279 sc->dc_srm_media = IFM_10_T; 2280 break; 2281 case 4: 2282 sc->dc_srm_media = IFM_10_T | IFM_FDX; 2283 break; 2284 case 5: 2285 sc->dc_srm_media = IFM_100_TX; 2286 break; 2287 case 6: 2288 sc->dc_srm_media = IFM_100_TX | IFM_FDX; 2289 break; 2290 } 2291 if (sc->dc_srm_media) 2292 sc->dc_srm_media |= IFM_ACTIVE | IFM_ETHER; 2293 } 2294 #endif 2295 2296 /* 2297 * Call MI attach routine. 2298 */ 2299 ether_ifattach(ifp, eaddr); 2300 2301 /* Hook interrupt last to avoid having to lock softc */ 2302 error = bus_setup_intr(dev, sc->dc_irq, INTR_TYPE_NET | 2303 (IS_MPSAFE ? INTR_MPSAFE : 0), 2304 dc_intr, sc, &sc->dc_intrhand); 2305 2306 if (error) { 2307 printf("dc%d: couldn't set up irq\n", unit); 2308 ether_ifdetach(ifp); 2309 goto fail; 2310 } 2311 2312 fail: 2313 if (error) 2314 dc_detach(dev); 2315 return (error); 2316 } 2317 2318 /* 2319 * Shutdown hardware and free up resources. This can be called any 2320 * time after the mutex has been initialized. It is called in both 2321 * the error case in attach and the normal detach case so it needs 2322 * to be careful about only freeing resources that have actually been 2323 * allocated. 2324 */ 2325 static int 2326 dc_detach(device_t dev) 2327 { 2328 struct dc_softc *sc; 2329 struct ifnet *ifp; 2330 struct dc_mediainfo *m; 2331 int i; 2332 2333 sc = device_get_softc(dev); 2334 KASSERT(mtx_initialized(&sc->dc_mtx), ("dc mutex not initialized")); 2335 DC_LOCK(sc); 2336 2337 ifp = &sc->arpcom.ac_if; 2338 2339 /* These should only be active if attach succeeded */ 2340 if (device_is_attached(dev)) { 2341 dc_stop(sc); 2342 ether_ifdetach(ifp); 2343 } 2344 if (sc->dc_miibus) 2345 device_delete_child(dev, sc->dc_miibus); 2346 bus_generic_detach(dev); 2347 2348 if (sc->dc_intrhand) 2349 bus_teardown_intr(dev, sc->dc_irq, sc->dc_intrhand); 2350 if (sc->dc_irq) 2351 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->dc_irq); 2352 if (sc->dc_res) 2353 bus_release_resource(dev, DC_RES, DC_RID, sc->dc_res); 2354 2355 if (sc->dc_cdata.dc_sbuf != NULL) 2356 bus_dmamem_free(sc->dc_stag, sc->dc_cdata.dc_sbuf, sc->dc_smap); 2357 if (sc->dc_ldata != NULL) 2358 bus_dmamem_free(sc->dc_ltag, sc->dc_ldata, sc->dc_lmap); 2359 for (i = 0; i < DC_TX_LIST_CNT; i++) 2360 bus_dmamap_destroy(sc->dc_mtag, sc->dc_cdata.dc_tx_map[i]); 2361 for (i = 0; i < DC_RX_LIST_CNT; i++) 2362 bus_dmamap_destroy(sc->dc_mtag, sc->dc_cdata.dc_rx_map[i]); 2363 bus_dmamap_destroy(sc->dc_mtag, sc->dc_sparemap); 2364 if (sc->dc_stag) 2365 bus_dma_tag_destroy(sc->dc_stag); 2366 if (sc->dc_mtag) 2367 bus_dma_tag_destroy(sc->dc_mtag); 2368 if (sc->dc_ltag) 2369 bus_dma_tag_destroy(sc->dc_ltag); 2370 2371 free(sc->dc_pnic_rx_buf, M_DEVBUF); 2372 2373 while (sc->dc_mi != NULL) { 2374 m = sc->dc_mi->dc_next; 2375 free(sc->dc_mi, M_DEVBUF); 2376 sc->dc_mi = m; 2377 } 2378 free(sc->dc_srom, M_DEVBUF); 2379 2380 DC_UNLOCK(sc); 2381 mtx_destroy(&sc->dc_mtx); 2382 2383 return (0); 2384 } 2385 2386 /* 2387 * Initialize the transmit descriptors. 2388 */ 2389 static int 2390 dc_list_tx_init(struct dc_softc *sc) 2391 { 2392 struct dc_chain_data *cd; 2393 struct dc_list_data *ld; 2394 int i, nexti; 2395 2396 cd = &sc->dc_cdata; 2397 ld = sc->dc_ldata; 2398 for (i = 0; i < DC_TX_LIST_CNT; i++) { 2399 if (i == DC_TX_LIST_CNT - 1) 2400 nexti = 0; 2401 else 2402 nexti = i + 1; 2403 ld->dc_tx_list[i].dc_next = DC_TXDESC(sc, nexti); 2404 cd->dc_tx_chain[i] = NULL; 2405 ld->dc_tx_list[i].dc_data = 0; 2406 ld->dc_tx_list[i].dc_ctl = 0; 2407 } 2408 2409 cd->dc_tx_prod = cd->dc_tx_cons = cd->dc_tx_cnt = 0; 2410 bus_dmamap_sync(sc->dc_ltag, sc->dc_lmap, 2411 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2412 return (0); 2413 } 2414 2415 2416 /* 2417 * Initialize the RX descriptors and allocate mbufs for them. Note that 2418 * we arrange the descriptors in a closed ring, so that the last descriptor 2419 * points back to the first. 2420 */ 2421 static int 2422 dc_list_rx_init(struct dc_softc *sc) 2423 { 2424 struct dc_chain_data *cd; 2425 struct dc_list_data *ld; 2426 int i, nexti; 2427 2428 cd = &sc->dc_cdata; 2429 ld = sc->dc_ldata; 2430 2431 for (i = 0; i < DC_RX_LIST_CNT; i++) { 2432 if (dc_newbuf(sc, i, 1) != 0) 2433 return (ENOBUFS); 2434 if (i == DC_RX_LIST_CNT - 1) 2435 nexti = 0; 2436 else 2437 nexti = i + 1; 2438 ld->dc_rx_list[i].dc_next = DC_RXDESC(sc, nexti); 2439 } 2440 2441 cd->dc_rx_prod = 0; 2442 bus_dmamap_sync(sc->dc_ltag, sc->dc_lmap, 2443 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2444 return (0); 2445 } 2446 2447 static void 2448 dc_dma_map_rxbuf(arg, segs, nseg, mapsize, error) 2449 void *arg; 2450 bus_dma_segment_t *segs; 2451 int nseg; 2452 bus_size_t mapsize; 2453 int error; 2454 { 2455 struct dc_softc *sc; 2456 struct dc_desc *c; 2457 2458 sc = arg; 2459 c = &sc->dc_ldata->dc_rx_list[sc->dc_cdata.dc_rx_cur]; 2460 if (error) { 2461 sc->dc_cdata.dc_rx_err = error; 2462 return; 2463 } 2464 2465 KASSERT(nseg == 1, ("wrong number of segments, should be 1")); 2466 sc->dc_cdata.dc_rx_err = 0; 2467 c->dc_data = segs->ds_addr; 2468 } 2469 2470 /* 2471 * Initialize an RX descriptor and attach an MBUF cluster. 2472 */ 2473 static int 2474 dc_newbuf(struct dc_softc *sc, int i, int alloc) 2475 { 2476 struct mbuf *m_new; 2477 bus_dmamap_t tmp; 2478 int error; 2479 2480 if (alloc) { 2481 m_new = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR); 2482 if (m_new == NULL) 2483 return (ENOBUFS); 2484 } else { 2485 m_new = sc->dc_cdata.dc_rx_chain[i]; 2486 m_new->m_data = m_new->m_ext.ext_buf; 2487 } 2488 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 2489 m_adj(m_new, sizeof(u_int64_t)); 2490 2491 /* 2492 * If this is a PNIC chip, zero the buffer. This is part 2493 * of the workaround for the receive bug in the 82c168 and 2494 * 82c169 chips. 2495 */ 2496 if (sc->dc_flags & DC_PNIC_RX_BUG_WAR) 2497 bzero(mtod(m_new, char *), m_new->m_len); 2498 2499 /* No need to remap the mbuf if we're reusing it. */ 2500 if (alloc) { 2501 sc->dc_cdata.dc_rx_cur = i; 2502 error = bus_dmamap_load_mbuf(sc->dc_mtag, sc->dc_sparemap, 2503 m_new, dc_dma_map_rxbuf, sc, 0); 2504 if (error) { 2505 m_freem(m_new); 2506 return (error); 2507 } 2508 if (sc->dc_cdata.dc_rx_err != 0) { 2509 m_freem(m_new); 2510 return (sc->dc_cdata.dc_rx_err); 2511 } 2512 bus_dmamap_unload(sc->dc_mtag, sc->dc_cdata.dc_rx_map[i]); 2513 tmp = sc->dc_cdata.dc_rx_map[i]; 2514 sc->dc_cdata.dc_rx_map[i] = sc->dc_sparemap; 2515 sc->dc_sparemap = tmp; 2516 sc->dc_cdata.dc_rx_chain[i] = m_new; 2517 } 2518 2519 sc->dc_ldata->dc_rx_list[i].dc_ctl = DC_RXCTL_RLINK | DC_RXLEN; 2520 sc->dc_ldata->dc_rx_list[i].dc_status = DC_RXSTAT_OWN; 2521 bus_dmamap_sync(sc->dc_mtag, sc->dc_cdata.dc_rx_map[i], 2522 BUS_DMASYNC_PREREAD); 2523 bus_dmamap_sync(sc->dc_ltag, sc->dc_lmap, 2524 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2525 return (0); 2526 } 2527 2528 /* 2529 * Grrrrr. 2530 * The PNIC chip has a terrible bug in it that manifests itself during 2531 * periods of heavy activity. The exact mode of failure if difficult to 2532 * pinpoint: sometimes it only happens in promiscuous mode, sometimes it 2533 * will happen on slow machines. The bug is that sometimes instead of 2534 * uploading one complete frame during reception, it uploads what looks 2535 * like the entire contents of its FIFO memory. The frame we want is at 2536 * the end of the whole mess, but we never know exactly how much data has 2537 * been uploaded, so salvaging the frame is hard. 2538 * 2539 * There is only one way to do it reliably, and it's disgusting. 2540 * Here's what we know: 2541 * 2542 * - We know there will always be somewhere between one and three extra 2543 * descriptors uploaded. 2544 * 2545 * - We know the desired received frame will always be at the end of the 2546 * total data upload. 2547 * 2548 * - We know the size of the desired received frame because it will be 2549 * provided in the length field of the status word in the last descriptor. 2550 * 2551 * Here's what we do: 2552 * 2553 * - When we allocate buffers for the receive ring, we bzero() them. 2554 * This means that we know that the buffer contents should be all 2555 * zeros, except for data uploaded by the chip. 2556 * 2557 * - We also force the PNIC chip to upload frames that include the 2558 * ethernet CRC at the end. 2559 * 2560 * - We gather all of the bogus frame data into a single buffer. 2561 * 2562 * - We then position a pointer at the end of this buffer and scan 2563 * backwards until we encounter the first non-zero byte of data. 2564 * This is the end of the received frame. We know we will encounter 2565 * some data at the end of the frame because the CRC will always be 2566 * there, so even if the sender transmits a packet of all zeros, 2567 * we won't be fooled. 2568 * 2569 * - We know the size of the actual received frame, so we subtract 2570 * that value from the current pointer location. This brings us 2571 * to the start of the actual received packet. 2572 * 2573 * - We copy this into an mbuf and pass it on, along with the actual 2574 * frame length. 2575 * 2576 * The performance hit is tremendous, but it beats dropping frames all 2577 * the time. 2578 */ 2579 2580 #define DC_WHOLEFRAME (DC_RXSTAT_FIRSTFRAG | DC_RXSTAT_LASTFRAG) 2581 static void 2582 dc_pnic_rx_bug_war(struct dc_softc *sc, int idx) 2583 { 2584 struct dc_desc *cur_rx; 2585 struct dc_desc *c = NULL; 2586 struct mbuf *m = NULL; 2587 unsigned char *ptr; 2588 int i, total_len; 2589 u_int32_t rxstat = 0; 2590 2591 i = sc->dc_pnic_rx_bug_save; 2592 cur_rx = &sc->dc_ldata->dc_rx_list[idx]; 2593 ptr = sc->dc_pnic_rx_buf; 2594 bzero(ptr, DC_RXLEN * 5); 2595 2596 /* Copy all the bytes from the bogus buffers. */ 2597 while (1) { 2598 c = &sc->dc_ldata->dc_rx_list[i]; 2599 rxstat = c->dc_status; 2600 m = sc->dc_cdata.dc_rx_chain[i]; 2601 bcopy(mtod(m, char *), ptr, DC_RXLEN); 2602 ptr += DC_RXLEN; 2603 /* If this is the last buffer, break out. */ 2604 if (i == idx || rxstat & DC_RXSTAT_LASTFRAG) 2605 break; 2606 dc_newbuf(sc, i, 0); 2607 DC_INC(i, DC_RX_LIST_CNT); 2608 } 2609 2610 /* Find the length of the actual receive frame. */ 2611 total_len = DC_RXBYTES(rxstat); 2612 2613 /* Scan backwards until we hit a non-zero byte. */ 2614 while (*ptr == 0x00) 2615 ptr--; 2616 2617 /* Round off. */ 2618 if ((uintptr_t)(ptr) & 0x3) 2619 ptr -= 1; 2620 2621 /* Now find the start of the frame. */ 2622 ptr -= total_len; 2623 if (ptr < sc->dc_pnic_rx_buf) 2624 ptr = sc->dc_pnic_rx_buf; 2625 2626 /* 2627 * Now copy the salvaged frame to the last mbuf and fake up 2628 * the status word to make it look like a successful 2629 * frame reception. 2630 */ 2631 dc_newbuf(sc, i, 0); 2632 bcopy(ptr, mtod(m, char *), total_len); 2633 cur_rx->dc_status = rxstat | DC_RXSTAT_FIRSTFRAG; 2634 } 2635 2636 /* 2637 * This routine searches the RX ring for dirty descriptors in the 2638 * event that the rxeof routine falls out of sync with the chip's 2639 * current descriptor pointer. This may happen sometimes as a result 2640 * of a "no RX buffer available" condition that happens when the chip 2641 * consumes all of the RX buffers before the driver has a chance to 2642 * process the RX ring. This routine may need to be called more than 2643 * once to bring the driver back in sync with the chip, however we 2644 * should still be getting RX DONE interrupts to drive the search 2645 * for new packets in the RX ring, so we should catch up eventually. 2646 */ 2647 static int 2648 dc_rx_resync(struct dc_softc *sc) 2649 { 2650 struct dc_desc *cur_rx; 2651 int i, pos; 2652 2653 pos = sc->dc_cdata.dc_rx_prod; 2654 2655 for (i = 0; i < DC_RX_LIST_CNT; i++) { 2656 cur_rx = &sc->dc_ldata->dc_rx_list[pos]; 2657 if (!(cur_rx->dc_status & DC_RXSTAT_OWN)) 2658 break; 2659 DC_INC(pos, DC_RX_LIST_CNT); 2660 } 2661 2662 /* If the ring really is empty, then just return. */ 2663 if (i == DC_RX_LIST_CNT) 2664 return (0); 2665 2666 /* We've fallen behing the chip: catch it. */ 2667 sc->dc_cdata.dc_rx_prod = pos; 2668 2669 return (EAGAIN); 2670 } 2671 2672 /* 2673 * A frame has been uploaded: pass the resulting mbuf chain up to 2674 * the higher level protocols. 2675 */ 2676 static void 2677 dc_rxeof(struct dc_softc *sc) 2678 { 2679 struct mbuf *m; 2680 struct ifnet *ifp; 2681 struct dc_desc *cur_rx; 2682 int i, total_len = 0; 2683 u_int32_t rxstat; 2684 2685 ifp = &sc->arpcom.ac_if; 2686 i = sc->dc_cdata.dc_rx_prod; 2687 2688 bus_dmamap_sync(sc->dc_ltag, sc->dc_lmap, BUS_DMASYNC_POSTREAD); 2689 while (!(sc->dc_ldata->dc_rx_list[i].dc_status & DC_RXSTAT_OWN)) { 2690 #ifdef DEVICE_POLLING 2691 if (ifp->if_flags & IFF_POLLING) { 2692 if (sc->rxcycles <= 0) 2693 break; 2694 sc->rxcycles--; 2695 } 2696 #endif 2697 cur_rx = &sc->dc_ldata->dc_rx_list[i]; 2698 rxstat = cur_rx->dc_status; 2699 m = sc->dc_cdata.dc_rx_chain[i]; 2700 bus_dmamap_sync(sc->dc_mtag, sc->dc_cdata.dc_rx_map[i], 2701 BUS_DMASYNC_POSTREAD); 2702 total_len = DC_RXBYTES(rxstat); 2703 2704 if (sc->dc_flags & DC_PNIC_RX_BUG_WAR) { 2705 if ((rxstat & DC_WHOLEFRAME) != DC_WHOLEFRAME) { 2706 if (rxstat & DC_RXSTAT_FIRSTFRAG) 2707 sc->dc_pnic_rx_bug_save = i; 2708 if ((rxstat & DC_RXSTAT_LASTFRAG) == 0) { 2709 DC_INC(i, DC_RX_LIST_CNT); 2710 continue; 2711 } 2712 dc_pnic_rx_bug_war(sc, i); 2713 rxstat = cur_rx->dc_status; 2714 total_len = DC_RXBYTES(rxstat); 2715 } 2716 } 2717 2718 /* 2719 * If an error occurs, update stats, clear the 2720 * status word and leave the mbuf cluster in place: 2721 * it should simply get re-used next time this descriptor 2722 * comes up in the ring. However, don't report long 2723 * frames as errors since they could be vlans. 2724 */ 2725 if ((rxstat & DC_RXSTAT_RXERR)) { 2726 if (!(rxstat & DC_RXSTAT_GIANT) || 2727 (rxstat & (DC_RXSTAT_CRCERR | DC_RXSTAT_DRIBBLE | 2728 DC_RXSTAT_MIIERE | DC_RXSTAT_COLLSEEN | 2729 DC_RXSTAT_RUNT | DC_RXSTAT_DE))) { 2730 ifp->if_ierrors++; 2731 if (rxstat & DC_RXSTAT_COLLSEEN) 2732 ifp->if_collisions++; 2733 dc_newbuf(sc, i, 0); 2734 if (rxstat & DC_RXSTAT_CRCERR) { 2735 DC_INC(i, DC_RX_LIST_CNT); 2736 continue; 2737 } else { 2738 dc_init(sc); 2739 return; 2740 } 2741 } 2742 } 2743 2744 /* No errors; receive the packet. */ 2745 total_len -= ETHER_CRC_LEN; 2746 #ifdef __i386__ 2747 /* 2748 * On the x86 we do not have alignment problems, so try to 2749 * allocate a new buffer for the receive ring, and pass up 2750 * the one where the packet is already, saving the expensive 2751 * copy done in m_devget(). 2752 * If we are on an architecture with alignment problems, or 2753 * if the allocation fails, then use m_devget and leave the 2754 * existing buffer in the receive ring. 2755 */ 2756 if (dc_quick && dc_newbuf(sc, i, 1) == 0) { 2757 m->m_pkthdr.rcvif = ifp; 2758 m->m_pkthdr.len = m->m_len = total_len; 2759 DC_INC(i, DC_RX_LIST_CNT); 2760 } else 2761 #endif 2762 { 2763 struct mbuf *m0; 2764 2765 m0 = m_devget(mtod(m, char *), total_len, 2766 ETHER_ALIGN, ifp, NULL); 2767 dc_newbuf(sc, i, 0); 2768 DC_INC(i, DC_RX_LIST_CNT); 2769 if (m0 == NULL) { 2770 ifp->if_ierrors++; 2771 continue; 2772 } 2773 m = m0; 2774 } 2775 2776 ifp->if_ipackets++; 2777 (*ifp->if_input)(ifp, m); 2778 } 2779 2780 sc->dc_cdata.dc_rx_prod = i; 2781 } 2782 2783 /* 2784 * A frame was downloaded to the chip. It's safe for us to clean up 2785 * the list buffers. 2786 */ 2787 2788 static void 2789 dc_txeof(struct dc_softc *sc) 2790 { 2791 struct dc_desc *cur_tx = NULL; 2792 struct ifnet *ifp; 2793 int idx; 2794 u_int32_t txstat; 2795 2796 ifp = &sc->arpcom.ac_if; 2797 2798 /* 2799 * Go through our tx list and free mbufs for those 2800 * frames that have been transmitted. 2801 */ 2802 bus_dmamap_sync(sc->dc_ltag, sc->dc_lmap, BUS_DMASYNC_POSTREAD); 2803 idx = sc->dc_cdata.dc_tx_cons; 2804 while (idx != sc->dc_cdata.dc_tx_prod) { 2805 2806 cur_tx = &sc->dc_ldata->dc_tx_list[idx]; 2807 txstat = cur_tx->dc_status; 2808 2809 if (txstat & DC_TXSTAT_OWN) 2810 break; 2811 2812 if (!(cur_tx->dc_ctl & DC_TXCTL_FIRSTFRAG) || 2813 cur_tx->dc_ctl & DC_TXCTL_SETUP) { 2814 if (cur_tx->dc_ctl & DC_TXCTL_SETUP) { 2815 /* 2816 * Yes, the PNIC is so brain damaged 2817 * that it will sometimes generate a TX 2818 * underrun error while DMAing the RX 2819 * filter setup frame. If we detect this, 2820 * we have to send the setup frame again, 2821 * or else the filter won't be programmed 2822 * correctly. 2823 */ 2824 if (DC_IS_PNIC(sc)) { 2825 if (txstat & DC_TXSTAT_ERRSUM) 2826 dc_setfilt(sc); 2827 } 2828 sc->dc_cdata.dc_tx_chain[idx] = NULL; 2829 } 2830 sc->dc_cdata.dc_tx_cnt--; 2831 DC_INC(idx, DC_TX_LIST_CNT); 2832 continue; 2833 } 2834 2835 if (DC_IS_XIRCOM(sc) || DC_IS_CONEXANT(sc)) { 2836 /* 2837 * XXX: Why does my Xircom taunt me so? 2838 * For some reason it likes setting the CARRLOST flag 2839 * even when the carrier is there. wtf?!? 2840 * Who knows, but Conexant chips have the 2841 * same problem. Maybe they took lessons 2842 * from Xircom. 2843 */ 2844 if (/*sc->dc_type == DC_TYPE_21143 &&*/ 2845 sc->dc_pmode == DC_PMODE_MII && 2846 ((txstat & 0xFFFF) & ~(DC_TXSTAT_ERRSUM | 2847 DC_TXSTAT_NOCARRIER))) 2848 txstat &= ~DC_TXSTAT_ERRSUM; 2849 } else { 2850 if (/*sc->dc_type == DC_TYPE_21143 &&*/ 2851 sc->dc_pmode == DC_PMODE_MII && 2852 ((txstat & 0xFFFF) & ~(DC_TXSTAT_ERRSUM | 2853 DC_TXSTAT_NOCARRIER | DC_TXSTAT_CARRLOST))) 2854 txstat &= ~DC_TXSTAT_ERRSUM; 2855 } 2856 2857 if (txstat & DC_TXSTAT_ERRSUM) { 2858 ifp->if_oerrors++; 2859 if (txstat & DC_TXSTAT_EXCESSCOLL) 2860 ifp->if_collisions++; 2861 if (txstat & DC_TXSTAT_LATECOLL) 2862 ifp->if_collisions++; 2863 if (!(txstat & DC_TXSTAT_UNDERRUN)) { 2864 dc_init(sc); 2865 return; 2866 } 2867 } 2868 2869 ifp->if_collisions += (txstat & DC_TXSTAT_COLLCNT) >> 3; 2870 2871 ifp->if_opackets++; 2872 if (sc->dc_cdata.dc_tx_chain[idx] != NULL) { 2873 bus_dmamap_sync(sc->dc_mtag, 2874 sc->dc_cdata.dc_tx_map[idx], 2875 BUS_DMASYNC_POSTWRITE); 2876 bus_dmamap_unload(sc->dc_mtag, 2877 sc->dc_cdata.dc_tx_map[idx]); 2878 m_freem(sc->dc_cdata.dc_tx_chain[idx]); 2879 sc->dc_cdata.dc_tx_chain[idx] = NULL; 2880 } 2881 2882 sc->dc_cdata.dc_tx_cnt--; 2883 DC_INC(idx, DC_TX_LIST_CNT); 2884 } 2885 2886 if (idx != sc->dc_cdata.dc_tx_cons) { 2887 /* Some buffers have been freed. */ 2888 sc->dc_cdata.dc_tx_cons = idx; 2889 ifp->if_flags &= ~IFF_OACTIVE; 2890 } 2891 ifp->if_timer = (sc->dc_cdata.dc_tx_cnt == 0) ? 0 : 5; 2892 } 2893 2894 static void 2895 dc_tick(void *xsc) 2896 { 2897 struct dc_softc *sc; 2898 struct mii_data *mii; 2899 struct ifnet *ifp; 2900 u_int32_t r; 2901 2902 sc = xsc; 2903 DC_LOCK(sc); 2904 ifp = &sc->arpcom.ac_if; 2905 mii = device_get_softc(sc->dc_miibus); 2906 2907 if (sc->dc_flags & DC_REDUCED_MII_POLL) { 2908 if (sc->dc_flags & DC_21143_NWAY) { 2909 r = CSR_READ_4(sc, DC_10BTSTAT); 2910 if (IFM_SUBTYPE(mii->mii_media_active) == 2911 IFM_100_TX && (r & DC_TSTAT_LS100)) { 2912 sc->dc_link = 0; 2913 mii_mediachg(mii); 2914 } 2915 if (IFM_SUBTYPE(mii->mii_media_active) == 2916 IFM_10_T && (r & DC_TSTAT_LS10)) { 2917 sc->dc_link = 0; 2918 mii_mediachg(mii); 2919 } 2920 if (sc->dc_link == 0) 2921 mii_tick(mii); 2922 } else { 2923 r = CSR_READ_4(sc, DC_ISR); 2924 if ((r & DC_ISR_RX_STATE) == DC_RXSTATE_WAIT && 2925 sc->dc_cdata.dc_tx_cnt == 0) { 2926 mii_tick(mii); 2927 if (!(mii->mii_media_status & IFM_ACTIVE)) 2928 sc->dc_link = 0; 2929 } 2930 } 2931 } else 2932 mii_tick(mii); 2933 2934 /* 2935 * When the init routine completes, we expect to be able to send 2936 * packets right away, and in fact the network code will send a 2937 * gratuitous ARP the moment the init routine marks the interface 2938 * as running. However, even though the MAC may have been initialized, 2939 * there may be a delay of a few seconds before the PHY completes 2940 * autonegotiation and the link is brought up. Any transmissions 2941 * made during that delay will be lost. Dealing with this is tricky: 2942 * we can't just pause in the init routine while waiting for the 2943 * PHY to come ready since that would bring the whole system to 2944 * a screeching halt for several seconds. 2945 * 2946 * What we do here is prevent the TX start routine from sending 2947 * any packets until a link has been established. After the 2948 * interface has been initialized, the tick routine will poll 2949 * the state of the PHY until the IFM_ACTIVE flag is set. Until 2950 * that time, packets will stay in the send queue, and once the 2951 * link comes up, they will be flushed out to the wire. 2952 */ 2953 if (!sc->dc_link && mii->mii_media_status & IFM_ACTIVE && 2954 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) { 2955 sc->dc_link++; 2956 if (ifp->if_snd.ifq_head != NULL) 2957 dc_start(ifp); 2958 } 2959 2960 if (sc->dc_flags & DC_21143_NWAY && !sc->dc_link) 2961 callout_reset(&sc->dc_stat_ch, hz/10, dc_tick, sc); 2962 else 2963 callout_reset(&sc->dc_stat_ch, hz, dc_tick, sc); 2964 2965 DC_UNLOCK(sc); 2966 } 2967 2968 /* 2969 * A transmit underrun has occurred. Back off the transmit threshold, 2970 * or switch to store and forward mode if we have to. 2971 */ 2972 static void 2973 dc_tx_underrun(struct dc_softc *sc) 2974 { 2975 u_int32_t isr; 2976 int i; 2977 2978 if (DC_IS_DAVICOM(sc)) 2979 dc_init(sc); 2980 2981 if (DC_IS_INTEL(sc)) { 2982 /* 2983 * The real 21143 requires that the transmitter be idle 2984 * in order to change the transmit threshold or store 2985 * and forward state. 2986 */ 2987 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_TX_ON); 2988 2989 for (i = 0; i < DC_TIMEOUT; i++) { 2990 isr = CSR_READ_4(sc, DC_ISR); 2991 if (isr & DC_ISR_TX_IDLE) 2992 break; 2993 DELAY(10); 2994 } 2995 if (i == DC_TIMEOUT) { 2996 printf("dc%d: failed to force tx to idle state\n", 2997 sc->dc_unit); 2998 dc_init(sc); 2999 } 3000 } 3001 3002 printf("dc%d: TX underrun -- ", sc->dc_unit); 3003 sc->dc_txthresh += DC_TXTHRESH_INC; 3004 if (sc->dc_txthresh > DC_TXTHRESH_MAX) { 3005 printf("using store and forward mode\n"); 3006 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_STORENFWD); 3007 } else { 3008 printf("increasing TX threshold\n"); 3009 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_TX_THRESH); 3010 DC_SETBIT(sc, DC_NETCFG, sc->dc_txthresh); 3011 } 3012 3013 if (DC_IS_INTEL(sc)) 3014 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_TX_ON); 3015 } 3016 3017 #ifdef DEVICE_POLLING 3018 static poll_handler_t dc_poll; 3019 3020 static void 3021 dc_poll(struct ifnet *ifp, enum poll_cmd cmd, int count) 3022 { 3023 struct dc_softc *sc = ifp->if_softc; 3024 3025 if (cmd == POLL_DEREGISTER) { /* final call, enable interrupts */ 3026 /* Re-enable interrupts. */ 3027 CSR_WRITE_4(sc, DC_IMR, DC_INTRS); 3028 return; 3029 } 3030 sc->rxcycles = count; 3031 dc_rxeof(sc); 3032 dc_txeof(sc); 3033 if (ifp->if_snd.ifq_head != NULL && !(ifp->if_flags & IFF_OACTIVE)) 3034 dc_start(ifp); 3035 3036 if (cmd == POLL_AND_CHECK_STATUS) { /* also check status register */ 3037 u_int32_t status; 3038 3039 status = CSR_READ_4(sc, DC_ISR); 3040 status &= (DC_ISR_RX_WATDOGTIMEO | DC_ISR_RX_NOBUF | 3041 DC_ISR_TX_NOBUF | DC_ISR_TX_IDLE | DC_ISR_TX_UNDERRUN | 3042 DC_ISR_BUS_ERR); 3043 if (!status) 3044 return; 3045 /* ack what we have */ 3046 CSR_WRITE_4(sc, DC_ISR, status); 3047 3048 if (status & (DC_ISR_RX_WATDOGTIMEO | DC_ISR_RX_NOBUF)) { 3049 u_int32_t r = CSR_READ_4(sc, DC_FRAMESDISCARDED); 3050 ifp->if_ierrors += (r & 0xffff) + ((r >> 17) & 0x7ff); 3051 3052 if (dc_rx_resync(sc)) 3053 dc_rxeof(sc); 3054 } 3055 /* restart transmit unit if necessary */ 3056 if (status & DC_ISR_TX_IDLE && sc->dc_cdata.dc_tx_cnt) 3057 CSR_WRITE_4(sc, DC_TXSTART, 0xFFFFFFFF); 3058 3059 if (status & DC_ISR_TX_UNDERRUN) 3060 dc_tx_underrun(sc); 3061 3062 if (status & DC_ISR_BUS_ERR) { 3063 printf("dc_poll: dc%d bus error\n", sc->dc_unit); 3064 dc_reset(sc); 3065 dc_init(sc); 3066 } 3067 } 3068 } 3069 #endif /* DEVICE_POLLING */ 3070 3071 static void 3072 dc_intr(void *arg) 3073 { 3074 struct dc_softc *sc; 3075 struct ifnet *ifp; 3076 u_int32_t status; 3077 3078 sc = arg; 3079 3080 if (sc->suspended) 3081 return; 3082 3083 if ((CSR_READ_4(sc, DC_ISR) & DC_INTRS) == 0) 3084 return; 3085 3086 DC_LOCK(sc); 3087 ifp = &sc->arpcom.ac_if; 3088 #ifdef DEVICE_POLLING 3089 if (ifp->if_flags & IFF_POLLING) 3090 goto done; 3091 if (ether_poll_register(dc_poll, ifp)) { /* ok, disable interrupts */ 3092 CSR_WRITE_4(sc, DC_IMR, 0x00000000); 3093 goto done; 3094 } 3095 #endif 3096 3097 /* Suppress unwanted interrupts */ 3098 if (!(ifp->if_flags & IFF_UP)) { 3099 if (CSR_READ_4(sc, DC_ISR) & DC_INTRS) 3100 dc_stop(sc); 3101 DC_UNLOCK(sc); 3102 return; 3103 } 3104 3105 /* Disable interrupts. */ 3106 CSR_WRITE_4(sc, DC_IMR, 0x00000000); 3107 3108 while (((status = CSR_READ_4(sc, DC_ISR)) & DC_INTRS) 3109 && status != 0xFFFFFFFF) { 3110 3111 CSR_WRITE_4(sc, DC_ISR, status); 3112 3113 if (status & DC_ISR_RX_OK) { 3114 int curpkts; 3115 curpkts = ifp->if_ipackets; 3116 dc_rxeof(sc); 3117 if (curpkts == ifp->if_ipackets) { 3118 while (dc_rx_resync(sc)) 3119 dc_rxeof(sc); 3120 } 3121 } 3122 3123 if (status & (DC_ISR_TX_OK | DC_ISR_TX_NOBUF)) 3124 dc_txeof(sc); 3125 3126 if (status & DC_ISR_TX_IDLE) { 3127 dc_txeof(sc); 3128 if (sc->dc_cdata.dc_tx_cnt) { 3129 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_TX_ON); 3130 CSR_WRITE_4(sc, DC_TXSTART, 0xFFFFFFFF); 3131 } 3132 } 3133 3134 if (status & DC_ISR_TX_UNDERRUN) 3135 dc_tx_underrun(sc); 3136 3137 if ((status & DC_ISR_RX_WATDOGTIMEO) 3138 || (status & DC_ISR_RX_NOBUF)) { 3139 int curpkts; 3140 curpkts = ifp->if_ipackets; 3141 dc_rxeof(sc); 3142 if (curpkts == ifp->if_ipackets) { 3143 while (dc_rx_resync(sc)) 3144 dc_rxeof(sc); 3145 } 3146 } 3147 3148 if (status & DC_ISR_BUS_ERR) { 3149 dc_reset(sc); 3150 dc_init(sc); 3151 } 3152 } 3153 3154 /* Re-enable interrupts. */ 3155 CSR_WRITE_4(sc, DC_IMR, DC_INTRS); 3156 3157 if (ifp->if_snd.ifq_head != NULL) 3158 dc_start(ifp); 3159 3160 #ifdef DEVICE_POLLING 3161 done: 3162 #endif 3163 3164 DC_UNLOCK(sc); 3165 } 3166 3167 static void 3168 dc_dma_map_txbuf(arg, segs, nseg, mapsize, error) 3169 void *arg; 3170 bus_dma_segment_t *segs; 3171 int nseg; 3172 bus_size_t mapsize; 3173 int error; 3174 { 3175 struct dc_softc *sc; 3176 struct dc_desc *f; 3177 int cur, first, frag, i; 3178 3179 sc = arg; 3180 if (error) { 3181 sc->dc_cdata.dc_tx_err = error; 3182 return; 3183 } 3184 3185 first = cur = frag = sc->dc_cdata.dc_tx_prod; 3186 for (i = 0; i < nseg; i++) { 3187 if ((sc->dc_flags & DC_TX_ADMTEK_WAR) && 3188 (frag == (DC_TX_LIST_CNT - 1)) && 3189 (first != sc->dc_cdata.dc_tx_first)) { 3190 bus_dmamap_unload(sc->dc_mtag, 3191 sc->dc_cdata.dc_tx_map[first]); 3192 sc->dc_cdata.dc_tx_err = ENOBUFS; 3193 return; 3194 } 3195 3196 f = &sc->dc_ldata->dc_tx_list[frag]; 3197 f->dc_ctl = DC_TXCTL_TLINK | segs[i].ds_len; 3198 if (i == 0) { 3199 f->dc_status = 0; 3200 f->dc_ctl |= DC_TXCTL_FIRSTFRAG; 3201 } else 3202 f->dc_status = DC_TXSTAT_OWN; 3203 f->dc_data = segs[i].ds_addr; 3204 cur = frag; 3205 DC_INC(frag, DC_TX_LIST_CNT); 3206 } 3207 3208 sc->dc_cdata.dc_tx_err = 0; 3209 sc->dc_cdata.dc_tx_prod = frag; 3210 sc->dc_cdata.dc_tx_cnt += nseg; 3211 sc->dc_ldata->dc_tx_list[cur].dc_ctl |= DC_TXCTL_LASTFRAG; 3212 if (sc->dc_flags & DC_TX_INTR_FIRSTFRAG) 3213 sc->dc_ldata->dc_tx_list[first].dc_ctl |= DC_TXCTL_FINT; 3214 if (sc->dc_flags & DC_TX_INTR_ALWAYS) 3215 sc->dc_ldata->dc_tx_list[cur].dc_ctl |= DC_TXCTL_FINT; 3216 if (sc->dc_flags & DC_TX_USE_TX_INTR && sc->dc_cdata.dc_tx_cnt > 64) 3217 sc->dc_ldata->dc_tx_list[cur].dc_ctl |= DC_TXCTL_FINT; 3218 sc->dc_ldata->dc_tx_list[first].dc_status = DC_TXSTAT_OWN; 3219 } 3220 3221 /* 3222 * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data 3223 * pointers to the fragment pointers. 3224 */ 3225 static int 3226 dc_encap(struct dc_softc *sc, struct mbuf *m_head) 3227 { 3228 struct mbuf *m; 3229 int error, idx, chainlen = 0; 3230 3231 /* 3232 * If there's no way we can send any packets, return now. 3233 */ 3234 if (DC_TX_LIST_CNT - sc->dc_cdata.dc_tx_cnt < 6) 3235 return (ENOBUFS); 3236 3237 /* 3238 * Count the number of frags in this chain to see if 3239 * we need to m_defrag. Since the descriptor list is shared 3240 * by all packets, we'll m_defrag long chains so that they 3241 * do not use up the entire list, even if they would fit. 3242 */ 3243 for (m = m_head; m != NULL; m = m->m_next) 3244 chainlen++; 3245 3246 if ((chainlen > DC_TX_LIST_CNT / 4) || 3247 ((DC_TX_LIST_CNT - (chainlen + sc->dc_cdata.dc_tx_cnt)) < 6)) { 3248 m = m_defrag(m_head, M_DONTWAIT); 3249 if (m == NULL) 3250 return (ENOBUFS); 3251 m_head = m; 3252 } 3253 3254 /* 3255 * Start packing the mbufs in this chain into 3256 * the fragment pointers. Stop when we run out 3257 * of fragments or hit the end of the mbuf chain. 3258 */ 3259 idx = sc->dc_cdata.dc_tx_prod; 3260 error = bus_dmamap_load_mbuf(sc->dc_mtag, sc->dc_cdata.dc_tx_map[idx], 3261 m_head, dc_dma_map_txbuf, sc, 0); 3262 if (error) 3263 return (error); 3264 if (sc->dc_cdata.dc_tx_err != 0) 3265 return (sc->dc_cdata.dc_tx_err); 3266 sc->dc_cdata.dc_tx_chain[idx] = m_head; 3267 bus_dmamap_sync(sc->dc_mtag, sc->dc_cdata.dc_tx_map[idx], 3268 BUS_DMASYNC_PREWRITE); 3269 bus_dmamap_sync(sc->dc_ltag, sc->dc_lmap, 3270 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3271 return (0); 3272 } 3273 3274 /* 3275 * Main transmit routine. To avoid having to do mbuf copies, we put pointers 3276 * to the mbuf data regions directly in the transmit lists. We also save a 3277 * copy of the pointers since the transmit list fragment pointers are 3278 * physical addresses. 3279 */ 3280 3281 static void 3282 dc_start(struct ifnet *ifp) 3283 { 3284 struct dc_softc *sc; 3285 struct mbuf *m_head = NULL, *m; 3286 int idx; 3287 3288 sc = ifp->if_softc; 3289 3290 DC_LOCK(sc); 3291 3292 if (!sc->dc_link && ifp->if_snd.ifq_len < 10) { 3293 DC_UNLOCK(sc); 3294 return; 3295 } 3296 3297 if (ifp->if_flags & IFF_OACTIVE) { 3298 DC_UNLOCK(sc); 3299 return; 3300 } 3301 3302 idx = sc->dc_cdata.dc_tx_first = sc->dc_cdata.dc_tx_prod; 3303 3304 while (sc->dc_cdata.dc_tx_chain[idx] == NULL) { 3305 IF_DEQUEUE(&ifp->if_snd, m_head); 3306 if (m_head == NULL) 3307 break; 3308 3309 if (sc->dc_flags & DC_TX_COALESCE && 3310 (m_head->m_next != NULL || 3311 sc->dc_flags & DC_TX_ALIGN)) { 3312 m = m_defrag(m_head, M_DONTWAIT); 3313 if (m == NULL) { 3314 IF_PREPEND(&ifp->if_snd, m_head); 3315 ifp->if_flags |= IFF_OACTIVE; 3316 break; 3317 } else { 3318 m_head = m; 3319 } 3320 } 3321 3322 if (dc_encap(sc, m_head)) { 3323 IF_PREPEND(&ifp->if_snd, m_head); 3324 ifp->if_flags |= IFF_OACTIVE; 3325 break; 3326 } 3327 idx = sc->dc_cdata.dc_tx_prod; 3328 3329 /* 3330 * If there's a BPF listener, bounce a copy of this frame 3331 * to him. 3332 */ 3333 BPF_MTAP(ifp, m_head); 3334 3335 if (sc->dc_flags & DC_TX_ONE) { 3336 ifp->if_flags |= IFF_OACTIVE; 3337 break; 3338 } 3339 } 3340 3341 /* Transmit */ 3342 if (!(sc->dc_flags & DC_TX_POLL)) 3343 CSR_WRITE_4(sc, DC_TXSTART, 0xFFFFFFFF); 3344 3345 /* 3346 * Set a timeout in case the chip goes out to lunch. 3347 */ 3348 ifp->if_timer = 5; 3349 3350 DC_UNLOCK(sc); 3351 } 3352 3353 static void 3354 dc_init(void *xsc) 3355 { 3356 struct dc_softc *sc = xsc; 3357 struct ifnet *ifp = &sc->arpcom.ac_if; 3358 struct mii_data *mii; 3359 3360 DC_LOCK(sc); 3361 3362 mii = device_get_softc(sc->dc_miibus); 3363 3364 /* 3365 * Cancel pending I/O and free all RX/TX buffers. 3366 */ 3367 dc_stop(sc); 3368 dc_reset(sc); 3369 3370 /* 3371 * Set cache alignment and burst length. 3372 */ 3373 if (DC_IS_ASIX(sc) || DC_IS_DAVICOM(sc)) 3374 CSR_WRITE_4(sc, DC_BUSCTL, 0); 3375 else 3376 CSR_WRITE_4(sc, DC_BUSCTL, DC_BUSCTL_MRME | DC_BUSCTL_MRLE); 3377 /* 3378 * Evenly share the bus between receive and transmit process. 3379 */ 3380 if (DC_IS_INTEL(sc)) 3381 DC_SETBIT(sc, DC_BUSCTL, DC_BUSCTL_ARBITRATION); 3382 if (DC_IS_DAVICOM(sc) || DC_IS_INTEL(sc)) { 3383 DC_SETBIT(sc, DC_BUSCTL, DC_BURSTLEN_USECA); 3384 } else { 3385 DC_SETBIT(sc, DC_BUSCTL, DC_BURSTLEN_16LONG); 3386 } 3387 if (sc->dc_flags & DC_TX_POLL) 3388 DC_SETBIT(sc, DC_BUSCTL, DC_TXPOLL_1); 3389 switch(sc->dc_cachesize) { 3390 case 32: 3391 DC_SETBIT(sc, DC_BUSCTL, DC_CACHEALIGN_32LONG); 3392 break; 3393 case 16: 3394 DC_SETBIT(sc, DC_BUSCTL, DC_CACHEALIGN_16LONG); 3395 break; 3396 case 8: 3397 DC_SETBIT(sc, DC_BUSCTL, DC_CACHEALIGN_8LONG); 3398 break; 3399 case 0: 3400 default: 3401 DC_SETBIT(sc, DC_BUSCTL, DC_CACHEALIGN_NONE); 3402 break; 3403 } 3404 3405 if (sc->dc_flags & DC_TX_STORENFWD) 3406 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_STORENFWD); 3407 else { 3408 if (sc->dc_txthresh > DC_TXTHRESH_MAX) { 3409 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_STORENFWD); 3410 } else { 3411 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_STORENFWD); 3412 DC_SETBIT(sc, DC_NETCFG, sc->dc_txthresh); 3413 } 3414 } 3415 3416 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_NO_RXCRC); 3417 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_TX_BACKOFF); 3418 3419 if (DC_IS_MACRONIX(sc) || DC_IS_PNICII(sc)) { 3420 /* 3421 * The app notes for the 98713 and 98715A say that 3422 * in order to have the chips operate properly, a magic 3423 * number must be written to CSR16. Macronix does not 3424 * document the meaning of these bits so there's no way 3425 * to know exactly what they do. The 98713 has a magic 3426 * number all its own; the rest all use a different one. 3427 */ 3428 DC_CLRBIT(sc, DC_MX_MAGICPACKET, 0xFFFF0000); 3429 if (sc->dc_type == DC_TYPE_98713) 3430 DC_SETBIT(sc, DC_MX_MAGICPACKET, DC_MX_MAGIC_98713); 3431 else 3432 DC_SETBIT(sc, DC_MX_MAGICPACKET, DC_MX_MAGIC_98715); 3433 } 3434 3435 if (DC_IS_XIRCOM(sc)) { 3436 /* 3437 * setup General Purpose Port mode and data so the tulip 3438 * can talk to the MII. 3439 */ 3440 CSR_WRITE_4(sc, DC_SIAGP, DC_SIAGP_WRITE_EN | DC_SIAGP_INT1_EN | 3441 DC_SIAGP_MD_GP2_OUTPUT | DC_SIAGP_MD_GP0_OUTPUT); 3442 DELAY(10); 3443 CSR_WRITE_4(sc, DC_SIAGP, DC_SIAGP_INT1_EN | 3444 DC_SIAGP_MD_GP2_OUTPUT | DC_SIAGP_MD_GP0_OUTPUT); 3445 DELAY(10); 3446 } 3447 3448 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_TX_THRESH); 3449 DC_SETBIT(sc, DC_NETCFG, DC_TXTHRESH_MIN); 3450 3451 /* Init circular RX list. */ 3452 if (dc_list_rx_init(sc) == ENOBUFS) { 3453 printf("dc%d: initialization failed: no " 3454 "memory for rx buffers\n", sc->dc_unit); 3455 dc_stop(sc); 3456 DC_UNLOCK(sc); 3457 return; 3458 } 3459 3460 /* 3461 * Init TX descriptors. 3462 */ 3463 dc_list_tx_init(sc); 3464 3465 /* 3466 * Load the address of the RX list. 3467 */ 3468 CSR_WRITE_4(sc, DC_RXADDR, DC_RXDESC(sc, 0)); 3469 CSR_WRITE_4(sc, DC_TXADDR, DC_TXDESC(sc, 0)); 3470 3471 /* 3472 * Enable interrupts. 3473 */ 3474 #ifdef DEVICE_POLLING 3475 /* 3476 * ... but only if we are not polling, and make sure they are off in 3477 * the case of polling. Some cards (e.g. fxp) turn interrupts on 3478 * after a reset. 3479 */ 3480 if (ifp->if_flags & IFF_POLLING) 3481 CSR_WRITE_4(sc, DC_IMR, 0x00000000); 3482 else 3483 #endif 3484 CSR_WRITE_4(sc, DC_IMR, DC_INTRS); 3485 CSR_WRITE_4(sc, DC_ISR, 0xFFFFFFFF); 3486 3487 /* Enable transmitter. */ 3488 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_TX_ON); 3489 3490 /* 3491 * If this is an Intel 21143 and we're not using the 3492 * MII port, program the LED control pins so we get 3493 * link and activity indications. 3494 */ 3495 if (sc->dc_flags & DC_TULIP_LEDS) { 3496 CSR_WRITE_4(sc, DC_WATCHDOG, 3497 DC_WDOG_CTLWREN | DC_WDOG_LINK | DC_WDOG_ACTIVITY); 3498 CSR_WRITE_4(sc, DC_WATCHDOG, 0); 3499 } 3500 3501 /* 3502 * Load the RX/multicast filter. We do this sort of late 3503 * because the filter programming scheme on the 21143 and 3504 * some clones requires DMAing a setup frame via the TX 3505 * engine, and we need the transmitter enabled for that. 3506 */ 3507 dc_setfilt(sc); 3508 3509 /* Enable receiver. */ 3510 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_ON); 3511 CSR_WRITE_4(sc, DC_RXSTART, 0xFFFFFFFF); 3512 3513 mii_mediachg(mii); 3514 dc_setcfg(sc, sc->dc_if_media); 3515 3516 ifp->if_flags |= IFF_RUNNING; 3517 ifp->if_flags &= ~IFF_OACTIVE; 3518 3519 /* Don't start the ticker if this is a homePNA link. */ 3520 if (IFM_SUBTYPE(mii->mii_media.ifm_media) == IFM_HPNA_1) 3521 sc->dc_link = 1; 3522 else { 3523 if (sc->dc_flags & DC_21143_NWAY) 3524 callout_reset(&sc->dc_stat_ch, hz/10, dc_tick, sc); 3525 else 3526 callout_reset(&sc->dc_stat_ch, hz, dc_tick, sc); 3527 } 3528 3529 #ifdef SRM_MEDIA 3530 if(sc->dc_srm_media) { 3531 struct ifreq ifr; 3532 3533 ifr.ifr_media = sc->dc_srm_media; 3534 ifmedia_ioctl(ifp, &ifr, &mii->mii_media, SIOCSIFMEDIA); 3535 sc->dc_srm_media = 0; 3536 } 3537 #endif 3538 DC_UNLOCK(sc); 3539 } 3540 3541 /* 3542 * Set media options. 3543 */ 3544 static int 3545 dc_ifmedia_upd(struct ifnet *ifp) 3546 { 3547 struct dc_softc *sc; 3548 struct mii_data *mii; 3549 struct ifmedia *ifm; 3550 3551 sc = ifp->if_softc; 3552 mii = device_get_softc(sc->dc_miibus); 3553 mii_mediachg(mii); 3554 ifm = &mii->mii_media; 3555 3556 if (DC_IS_DAVICOM(sc) && 3557 IFM_SUBTYPE(ifm->ifm_media) == IFM_HPNA_1) 3558 dc_setcfg(sc, ifm->ifm_media); 3559 else 3560 sc->dc_link = 0; 3561 3562 return (0); 3563 } 3564 3565 /* 3566 * Report current media status. 3567 */ 3568 static void 3569 dc_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 3570 { 3571 struct dc_softc *sc; 3572 struct mii_data *mii; 3573 struct ifmedia *ifm; 3574 3575 sc = ifp->if_softc; 3576 mii = device_get_softc(sc->dc_miibus); 3577 mii_pollstat(mii); 3578 ifm = &mii->mii_media; 3579 if (DC_IS_DAVICOM(sc)) { 3580 if (IFM_SUBTYPE(ifm->ifm_media) == IFM_HPNA_1) { 3581 ifmr->ifm_active = ifm->ifm_media; 3582 ifmr->ifm_status = 0; 3583 return; 3584 } 3585 } 3586 ifmr->ifm_active = mii->mii_media_active; 3587 ifmr->ifm_status = mii->mii_media_status; 3588 } 3589 3590 static int 3591 dc_ioctl(struct ifnet *ifp, u_long command, caddr_t data) 3592 { 3593 struct dc_softc *sc = ifp->if_softc; 3594 struct ifreq *ifr = (struct ifreq *)data; 3595 struct mii_data *mii; 3596 int error = 0; 3597 3598 DC_LOCK(sc); 3599 3600 switch (command) { 3601 case SIOCSIFFLAGS: 3602 if (ifp->if_flags & IFF_UP) { 3603 int need_setfilt = (ifp->if_flags ^ sc->dc_if_flags) & 3604 (IFF_PROMISC | IFF_ALLMULTI); 3605 3606 if (ifp->if_flags & IFF_RUNNING) { 3607 if (need_setfilt) 3608 dc_setfilt(sc); 3609 } else { 3610 sc->dc_txthresh = 0; 3611 dc_init(sc); 3612 } 3613 } else { 3614 if (ifp->if_flags & IFF_RUNNING) 3615 dc_stop(sc); 3616 } 3617 sc->dc_if_flags = ifp->if_flags; 3618 error = 0; 3619 break; 3620 case SIOCADDMULTI: 3621 case SIOCDELMULTI: 3622 dc_setfilt(sc); 3623 error = 0; 3624 break; 3625 case SIOCGIFMEDIA: 3626 case SIOCSIFMEDIA: 3627 mii = device_get_softc(sc->dc_miibus); 3628 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 3629 #ifdef SRM_MEDIA 3630 if (sc->dc_srm_media) 3631 sc->dc_srm_media = 0; 3632 #endif 3633 break; 3634 default: 3635 error = ether_ioctl(ifp, command, data); 3636 break; 3637 } 3638 3639 DC_UNLOCK(sc); 3640 3641 return (error); 3642 } 3643 3644 static void 3645 dc_watchdog(struct ifnet *ifp) 3646 { 3647 struct dc_softc *sc; 3648 3649 sc = ifp->if_softc; 3650 3651 DC_LOCK(sc); 3652 3653 ifp->if_oerrors++; 3654 printf("dc%d: watchdog timeout\n", sc->dc_unit); 3655 3656 dc_stop(sc); 3657 dc_reset(sc); 3658 dc_init(sc); 3659 3660 if (ifp->if_snd.ifq_head != NULL) 3661 dc_start(ifp); 3662 3663 DC_UNLOCK(sc); 3664 } 3665 3666 /* 3667 * Stop the adapter and free any mbufs allocated to the 3668 * RX and TX lists. 3669 */ 3670 static void 3671 dc_stop(struct dc_softc *sc) 3672 { 3673 struct ifnet *ifp; 3674 struct dc_list_data *ld; 3675 struct dc_chain_data *cd; 3676 int i; 3677 3678 DC_LOCK(sc); 3679 3680 ifp = &sc->arpcom.ac_if; 3681 ifp->if_timer = 0; 3682 ld = sc->dc_ldata; 3683 cd = &sc->dc_cdata; 3684 3685 callout_stop(&sc->dc_stat_ch); 3686 3687 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 3688 #ifdef DEVICE_POLLING 3689 ether_poll_deregister(ifp); 3690 #endif 3691 3692 DC_CLRBIT(sc, DC_NETCFG, (DC_NETCFG_RX_ON | DC_NETCFG_TX_ON)); 3693 CSR_WRITE_4(sc, DC_IMR, 0x00000000); 3694 CSR_WRITE_4(sc, DC_TXADDR, 0x00000000); 3695 CSR_WRITE_4(sc, DC_RXADDR, 0x00000000); 3696 sc->dc_link = 0; 3697 3698 /* 3699 * Free data in the RX lists. 3700 */ 3701 for (i = 0; i < DC_RX_LIST_CNT; i++) { 3702 if (cd->dc_rx_chain[i] != NULL) { 3703 m_freem(cd->dc_rx_chain[i]); 3704 cd->dc_rx_chain[i] = NULL; 3705 } 3706 } 3707 bzero(&ld->dc_rx_list, sizeof(ld->dc_rx_list)); 3708 3709 /* 3710 * Free the TX list buffers. 3711 */ 3712 for (i = 0; i < DC_TX_LIST_CNT; i++) { 3713 if (cd->dc_tx_chain[i] != NULL) { 3714 if ((ld->dc_tx_list[i].dc_ctl & DC_TXCTL_SETUP) || 3715 !(ld->dc_tx_list[i].dc_ctl & DC_TXCTL_FIRSTFRAG)) { 3716 cd->dc_tx_chain[i] = NULL; 3717 continue; 3718 } 3719 bus_dmamap_unload(sc->dc_mtag, cd->dc_tx_map[i]); 3720 m_freem(cd->dc_tx_chain[i]); 3721 cd->dc_tx_chain[i] = NULL; 3722 } 3723 } 3724 bzero(&ld->dc_tx_list, sizeof(ld->dc_tx_list)); 3725 3726 DC_UNLOCK(sc); 3727 } 3728 3729 /* 3730 * Device suspend routine. Stop the interface and save some PCI 3731 * settings in case the BIOS doesn't restore them properly on 3732 * resume. 3733 */ 3734 static int 3735 dc_suspend(device_t dev) 3736 { 3737 struct dc_softc *sc; 3738 int i, s; 3739 3740 s = splimp(); 3741 3742 sc = device_get_softc(dev); 3743 3744 dc_stop(sc); 3745 3746 for (i = 0; i < 5; i++) 3747 sc->saved_maps[i] = pci_read_config(dev, PCIR_MAPS + i * 4, 4); 3748 sc->saved_biosaddr = pci_read_config(dev, PCIR_BIOS, 4); 3749 sc->saved_intline = pci_read_config(dev, PCIR_INTLINE, 1); 3750 sc->saved_cachelnsz = pci_read_config(dev, PCIR_CACHELNSZ, 1); 3751 sc->saved_lattimer = pci_read_config(dev, PCIR_LATTIMER, 1); 3752 3753 sc->suspended = 1; 3754 3755 splx(s); 3756 return (0); 3757 } 3758 3759 /* 3760 * Device resume routine. Restore some PCI settings in case the BIOS 3761 * doesn't, re-enable busmastering, and restart the interface if 3762 * appropriate. 3763 */ 3764 static int 3765 dc_resume(device_t dev) 3766 { 3767 struct dc_softc *sc; 3768 struct ifnet *ifp; 3769 int i, s; 3770 3771 s = splimp(); 3772 3773 sc = device_get_softc(dev); 3774 ifp = &sc->arpcom.ac_if; 3775 #ifndef BURN_BRIDGES 3776 dc_acpi(dev); 3777 #endif 3778 /* better way to do this? */ 3779 for (i = 0; i < 5; i++) 3780 pci_write_config(dev, PCIR_MAPS + i * 4, sc->saved_maps[i], 4); 3781 pci_write_config(dev, PCIR_BIOS, sc->saved_biosaddr, 4); 3782 pci_write_config(dev, PCIR_INTLINE, sc->saved_intline, 1); 3783 pci_write_config(dev, PCIR_CACHELNSZ, sc->saved_cachelnsz, 1); 3784 pci_write_config(dev, PCIR_LATTIMER, sc->saved_lattimer, 1); 3785 3786 /* reenable busmastering */ 3787 pci_enable_busmaster(dev); 3788 pci_enable_io(dev, DC_RES); 3789 3790 /* reinitialize interface if necessary */ 3791 if (ifp->if_flags & IFF_UP) 3792 dc_init(sc); 3793 3794 sc->suspended = 0; 3795 3796 splx(s); 3797 return (0); 3798 } 3799 3800 /* 3801 * Stop all chip I/O so that the kernel's probe routines don't 3802 * get confused by errant DMAs when rebooting. 3803 */ 3804 static void 3805 dc_shutdown(device_t dev) 3806 { 3807 struct dc_softc *sc; 3808 3809 sc = device_get_softc(dev); 3810 3811 dc_stop(sc); 3812 } 3813