1 /*- 2 * SPDX-License-Identifier: BSD-4-Clause 3 * 4 * Copyright (c) 1997, 1998, 1999 5 * Bill Paul <wpaul@ee.columbia.edu>. All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed by Bill Paul. 18 * 4. Neither the name of the author nor the names of any co-contributors 19 * may be used to endorse or promote products derived from this software 20 * without specific prior written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 23 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 25 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 26 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 27 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 28 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 29 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 30 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 31 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 32 * THE POSSIBILITY OF SUCH DAMAGE. 33 */ 34 35 #include <sys/cdefs.h> 36 /* 37 * DEC "tulip" clone ethernet driver. Supports the DEC/Intel 21143 38 * series chips and several workalikes including the following: 39 * 40 * Macronix 98713/98715/98725/98727/98732 PMAC (www.macronix.com) 41 * Macronix/Lite-On 82c115 PNIC II (www.macronix.com) 42 * Lite-On 82c168/82c169 PNIC (www.litecom.com) 43 * ASIX Electronics AX88140A (www.asix.com.tw) 44 * ASIX Electronics AX88141 (www.asix.com.tw) 45 * ADMtek AL981 (www.admtek.com.tw) 46 * ADMtek AN983 (www.admtek.com.tw) 47 * ADMtek CardBus AN985 (www.admtek.com.tw) 48 * Netgear FA511 (www.netgear.com) Appears to be rebadged ADMTek CardBus AN985 49 * Davicom DM9100, DM9102, DM9102A (www.davicom8.com) 50 * Accton EN1217 (www.accton.com) 51 * Xircom X3201 (www.xircom.com) 52 * Abocom FE2500 53 * Conexant LANfinity (www.conexant.com) 54 * 3Com OfficeConnect 10/100B 3CSOHO100B (www.3com.com) 55 * 56 * Datasheets for the 21143 are available at developer.intel.com. 57 * Datasheets for the clone parts can be found at their respective sites. 58 * (Except for the PNIC; see www.freebsd.org/~wpaul/PNIC/pnic.ps.gz.) 59 * The PNIC II is essentially a Macronix 98715A chip; the only difference 60 * worth noting is that its multicast hash table is only 128 bits wide 61 * instead of 512. 62 * 63 * Written by Bill Paul <wpaul@ee.columbia.edu> 64 * Electrical Engineering Department 65 * Columbia University, New York City 66 */ 67 /* 68 * The Intel 21143 is the successor to the DEC 21140. It is basically 69 * the same as the 21140 but with a few new features. The 21143 supports 70 * three kinds of media attachments: 71 * 72 * o MII port, for 10Mbps and 100Mbps support and NWAY 73 * autonegotiation provided by an external PHY. 74 * o SYM port, for symbol mode 100Mbps support. 75 * o 10baseT port. 76 * o AUI/BNC port. 77 * 78 * The 100Mbps SYM port and 10baseT port can be used together in 79 * combination with the internal NWAY support to create a 10/100 80 * autosensing configuration. 81 * 82 * Note that not all tulip workalikes are handled in this driver: we only 83 * deal with those which are relatively well behaved. The Winbond is 84 * handled separately due to its different register offsets and the 85 * special handling needed for its various bugs. The PNIC is handled 86 * here, but I'm not thrilled about it. 87 * 88 * All of the workalike chips use some form of MII transceiver support 89 * with the exception of the Macronix chips, which also have a SYM port. 90 * The ASIX AX88140A is also documented to have a SYM port, but all 91 * the cards I've seen use an MII transceiver, probably because the 92 * AX88140A doesn't support internal NWAY. 93 */ 94 95 #ifdef HAVE_KERNEL_OPTION_HEADERS 96 #include "opt_device_polling.h" 97 #endif 98 99 #include <sys/param.h> 100 #include <sys/endian.h> 101 #include <sys/systm.h> 102 #include <sys/sockio.h> 103 #include <sys/mbuf.h> 104 #include <sys/malloc.h> 105 #include <sys/kernel.h> 106 #include <sys/module.h> 107 #include <sys/socket.h> 108 109 #include <net/if.h> 110 #include <net/if_var.h> 111 #include <net/if_arp.h> 112 #include <net/ethernet.h> 113 #include <net/if_dl.h> 114 #include <net/if_media.h> 115 #include <net/if_types.h> 116 #include <net/if_vlan_var.h> 117 118 #include <net/bpf.h> 119 120 #include <machine/bus.h> 121 #include <machine/resource.h> 122 #include <sys/bus.h> 123 #include <sys/rman.h> 124 125 #include <dev/mii/mii.h> 126 #include <dev/mii/mii_bitbang.h> 127 #include <dev/mii/miivar.h> 128 129 #include <dev/pci/pcireg.h> 130 #include <dev/pci/pcivar.h> 131 132 #define DC_USEIOSPACE 133 134 #include <dev/dc/if_dcreg.h> 135 136 MODULE_DEPEND(dc, pci, 1, 1, 1); 137 MODULE_DEPEND(dc, ether, 1, 1, 1); 138 MODULE_DEPEND(dc, miibus, 1, 1, 1); 139 140 /* 141 * "device miibus" is required in kernel config. See GENERIC if you get 142 * errors here. 143 */ 144 #include "miibus_if.h" 145 146 /* 147 * Various supported device vendors/types and their names. 148 */ 149 static const struct dc_type dc_devs[] = { 150 { DC_DEVID(DC_VENDORID_DEC, DC_DEVICEID_21143), 0, 151 "Intel 21143 10/100BaseTX" }, 152 { DC_DEVID(DC_VENDORID_DAVICOM, DC_DEVICEID_DM9009), 0, 153 "Davicom DM9009 10/100BaseTX" }, 154 { DC_DEVID(DC_VENDORID_DAVICOM, DC_DEVICEID_DM9100), 0, 155 "Davicom DM9100 10/100BaseTX" }, 156 { DC_DEVID(DC_VENDORID_DAVICOM, DC_DEVICEID_DM9102), DC_REVISION_DM9102A, 157 "Davicom DM9102A 10/100BaseTX" }, 158 { DC_DEVID(DC_VENDORID_DAVICOM, DC_DEVICEID_DM9102), 0, 159 "Davicom DM9102 10/100BaseTX" }, 160 { DC_DEVID(DC_VENDORID_ADMTEK, DC_DEVICEID_AL981), 0, 161 "ADMtek AL981 10/100BaseTX" }, 162 { DC_DEVID(DC_VENDORID_ADMTEK, DC_DEVICEID_AN983), 0, 163 "ADMtek AN983 10/100BaseTX" }, 164 { DC_DEVID(DC_VENDORID_ADMTEK, DC_DEVICEID_AN985), 0, 165 "ADMtek AN985 CardBus 10/100BaseTX or clone" }, 166 { DC_DEVID(DC_VENDORID_ADMTEK, DC_DEVICEID_ADM9511), 0, 167 "ADMtek ADM9511 10/100BaseTX" }, 168 { DC_DEVID(DC_VENDORID_ADMTEK, DC_DEVICEID_ADM9513), 0, 169 "ADMtek ADM9513 10/100BaseTX" }, 170 { DC_DEVID(DC_VENDORID_ASIX, DC_DEVICEID_AX88140A), DC_REVISION_88141, 171 "ASIX AX88141 10/100BaseTX" }, 172 { DC_DEVID(DC_VENDORID_ASIX, DC_DEVICEID_AX88140A), 0, 173 "ASIX AX88140A 10/100BaseTX" }, 174 { DC_DEVID(DC_VENDORID_MX, DC_DEVICEID_98713), DC_REVISION_98713A, 175 "Macronix 98713A 10/100BaseTX" }, 176 { DC_DEVID(DC_VENDORID_MX, DC_DEVICEID_98713), 0, 177 "Macronix 98713 10/100BaseTX" }, 178 { DC_DEVID(DC_VENDORID_CP, DC_DEVICEID_98713_CP), DC_REVISION_98713A, 179 "Compex RL100-TX 10/100BaseTX" }, 180 { DC_DEVID(DC_VENDORID_CP, DC_DEVICEID_98713_CP), 0, 181 "Compex RL100-TX 10/100BaseTX" }, 182 { DC_DEVID(DC_VENDORID_MX, DC_DEVICEID_987x5), DC_REVISION_98725, 183 "Macronix 98725 10/100BaseTX" }, 184 { DC_DEVID(DC_VENDORID_MX, DC_DEVICEID_987x5), DC_REVISION_98715AEC_C, 185 "Macronix 98715AEC-C 10/100BaseTX" }, 186 { DC_DEVID(DC_VENDORID_MX, DC_DEVICEID_987x5), 0, 187 "Macronix 98715/98715A 10/100BaseTX" }, 188 { DC_DEVID(DC_VENDORID_MX, DC_DEVICEID_98727), 0, 189 "Macronix 98727/98732 10/100BaseTX" }, 190 { DC_DEVID(DC_VENDORID_LO, DC_DEVICEID_82C115), 0, 191 "LC82C115 PNIC II 10/100BaseTX" }, 192 { DC_DEVID(DC_VENDORID_LO, DC_DEVICEID_82C168), DC_REVISION_82C169, 193 "82c169 PNIC 10/100BaseTX" }, 194 { DC_DEVID(DC_VENDORID_LO, DC_DEVICEID_82C168), 0, 195 "82c168 PNIC 10/100BaseTX" }, 196 { DC_DEVID(DC_VENDORID_ACCTON, DC_DEVICEID_EN1217), 0, 197 "Accton EN1217 10/100BaseTX" }, 198 { DC_DEVID(DC_VENDORID_ACCTON, DC_DEVICEID_EN2242), 0, 199 "Accton EN2242 MiniPCI 10/100BaseTX" }, 200 { DC_DEVID(DC_VENDORID_XIRCOM, DC_DEVICEID_X3201), 0, 201 "Xircom X3201 10/100BaseTX" }, 202 { DC_DEVID(DC_VENDORID_DLINK, DC_DEVICEID_DRP32TXD), 0, 203 "Neteasy DRP-32TXD Cardbus 10/100" }, 204 { DC_DEVID(DC_VENDORID_ABOCOM, DC_DEVICEID_FE2500), 0, 205 "Abocom FE2500 10/100BaseTX" }, 206 { DC_DEVID(DC_VENDORID_ABOCOM, DC_DEVICEID_FE2500MX), 0, 207 "Abocom FE2500MX 10/100BaseTX" }, 208 { DC_DEVID(DC_VENDORID_CONEXANT, DC_DEVICEID_RS7112), 0, 209 "Conexant LANfinity MiniPCI 10/100BaseTX" }, 210 { DC_DEVID(DC_VENDORID_HAWKING, DC_DEVICEID_HAWKING_PN672TX), 0, 211 "Hawking CB102 CardBus 10/100" }, 212 { DC_DEVID(DC_VENDORID_PLANEX, DC_DEVICEID_FNW3602T), 0, 213 "PlaneX FNW-3602-T CardBus 10/100" }, 214 { DC_DEVID(DC_VENDORID_3COM, DC_DEVICEID_3CSOHOB), 0, 215 "3Com OfficeConnect 10/100B" }, 216 { DC_DEVID(DC_VENDORID_MICROSOFT, DC_DEVICEID_MSMN120), 0, 217 "Microsoft MN-120 CardBus 10/100" }, 218 { DC_DEVID(DC_VENDORID_MICROSOFT, DC_DEVICEID_MSMN130), 0, 219 "Microsoft MN-130 10/100" }, 220 { DC_DEVID(DC_VENDORID_LINKSYS, DC_DEVICEID_PCMPC200_AB08), 0, 221 "Linksys PCMPC200 CardBus 10/100" }, 222 { DC_DEVID(DC_VENDORID_LINKSYS, DC_DEVICEID_PCMPC200_AB09), 0, 223 "Linksys PCMPC200 CardBus 10/100" }, 224 { DC_DEVID(DC_VENDORID_ULI, DC_DEVICEID_M5261), 0, 225 "ULi M5261 FastEthernet" }, 226 { DC_DEVID(DC_VENDORID_ULI, DC_DEVICEID_M5263), 0, 227 "ULi M5263 FastEthernet" }, 228 { 0, 0, NULL } 229 }; 230 231 static int dc_probe(device_t); 232 static int dc_attach(device_t); 233 static int dc_detach(device_t); 234 static int dc_suspend(device_t); 235 static int dc_resume(device_t); 236 static const struct dc_type *dc_devtype(device_t); 237 static void dc_discard_rxbuf(struct dc_softc *, int); 238 static int dc_newbuf(struct dc_softc *, int); 239 static int dc_encap(struct dc_softc *, struct mbuf **); 240 static void dc_pnic_rx_bug_war(struct dc_softc *, int); 241 static int dc_rx_resync(struct dc_softc *); 242 static int dc_rxeof(struct dc_softc *); 243 static void dc_txeof(struct dc_softc *); 244 static void dc_tick(void *); 245 static void dc_tx_underrun(struct dc_softc *); 246 static void dc_intr(void *); 247 static void dc_start(if_t); 248 static void dc_start_locked(if_t); 249 static int dc_ioctl(if_t, u_long, caddr_t); 250 static void dc_init(void *); 251 static void dc_init_locked(struct dc_softc *); 252 static void dc_stop(struct dc_softc *); 253 static void dc_watchdog(void *); 254 static int dc_shutdown(device_t); 255 static int dc_ifmedia_upd(if_t); 256 static int dc_ifmedia_upd_locked(struct dc_softc *); 257 static void dc_ifmedia_sts(if_t, struct ifmediareq *); 258 259 static int dc_dma_alloc(struct dc_softc *); 260 static void dc_dma_free(struct dc_softc *); 261 static void dc_dma_map_addr(void *, bus_dma_segment_t *, int, int); 262 263 static void dc_delay(struct dc_softc *); 264 static void dc_eeprom_idle(struct dc_softc *); 265 static void dc_eeprom_putbyte(struct dc_softc *, int); 266 static void dc_eeprom_getword(struct dc_softc *, int, uint16_t *); 267 static void dc_eeprom_getword_pnic(struct dc_softc *, int, uint16_t *); 268 static void dc_eeprom_getword_xircom(struct dc_softc *, int, uint16_t *); 269 static void dc_eeprom_width(struct dc_softc *); 270 static void dc_read_eeprom(struct dc_softc *, caddr_t, int, int, int); 271 272 static int dc_miibus_readreg(device_t, int, int); 273 static int dc_miibus_writereg(device_t, int, int, int); 274 static void dc_miibus_statchg(device_t); 275 static void dc_miibus_mediainit(device_t); 276 277 static void dc_setcfg(struct dc_softc *, int); 278 static void dc_netcfg_wait(struct dc_softc *); 279 static uint32_t dc_mchash_le(struct dc_softc *, const uint8_t *); 280 static uint32_t dc_mchash_be(const uint8_t *); 281 static void dc_setfilt_21143(struct dc_softc *); 282 static void dc_setfilt_asix(struct dc_softc *); 283 static void dc_setfilt_admtek(struct dc_softc *); 284 static void dc_setfilt_uli(struct dc_softc *); 285 static void dc_setfilt_xircom(struct dc_softc *); 286 287 static void dc_setfilt(struct dc_softc *); 288 289 static void dc_reset(struct dc_softc *); 290 static int dc_list_rx_init(struct dc_softc *); 291 static int dc_list_tx_init(struct dc_softc *); 292 293 static int dc_read_srom(struct dc_softc *, int); 294 static int dc_parse_21143_srom(struct dc_softc *); 295 static int dc_decode_leaf_sia(struct dc_softc *, struct dc_eblock_sia *); 296 static int dc_decode_leaf_mii(struct dc_softc *, struct dc_eblock_mii *); 297 static int dc_decode_leaf_sym(struct dc_softc *, struct dc_eblock_sym *); 298 static void dc_apply_fixup(struct dc_softc *, int); 299 static int dc_check_multiport(struct dc_softc *); 300 301 /* 302 * MII bit-bang glue 303 */ 304 static uint32_t dc_mii_bitbang_read(device_t); 305 static void dc_mii_bitbang_write(device_t, uint32_t); 306 307 static const struct mii_bitbang_ops dc_mii_bitbang_ops = { 308 dc_mii_bitbang_read, 309 dc_mii_bitbang_write, 310 { 311 DC_SIO_MII_DATAOUT, /* MII_BIT_MDO */ 312 DC_SIO_MII_DATAIN, /* MII_BIT_MDI */ 313 DC_SIO_MII_CLK, /* MII_BIT_MDC */ 314 0, /* MII_BIT_DIR_HOST_PHY */ 315 DC_SIO_MII_DIR, /* MII_BIT_DIR_PHY_HOST */ 316 } 317 }; 318 319 #ifdef DC_USEIOSPACE 320 #define DC_RES SYS_RES_IOPORT 321 #define DC_RID DC_PCI_CFBIO 322 #else 323 #define DC_RES SYS_RES_MEMORY 324 #define DC_RID DC_PCI_CFBMA 325 #endif 326 327 static device_method_t dc_methods[] = { 328 /* Device interface */ 329 DEVMETHOD(device_probe, dc_probe), 330 DEVMETHOD(device_attach, dc_attach), 331 DEVMETHOD(device_detach, dc_detach), 332 DEVMETHOD(device_suspend, dc_suspend), 333 DEVMETHOD(device_resume, dc_resume), 334 DEVMETHOD(device_shutdown, dc_shutdown), 335 336 /* MII interface */ 337 DEVMETHOD(miibus_readreg, dc_miibus_readreg), 338 DEVMETHOD(miibus_writereg, dc_miibus_writereg), 339 DEVMETHOD(miibus_statchg, dc_miibus_statchg), 340 DEVMETHOD(miibus_mediainit, dc_miibus_mediainit), 341 342 DEVMETHOD_END 343 }; 344 345 static driver_t dc_driver = { 346 "dc", 347 dc_methods, 348 sizeof(struct dc_softc) 349 }; 350 351 DRIVER_MODULE_ORDERED(dc, pci, dc_driver, NULL, NULL, SI_ORDER_ANY); 352 MODULE_PNP_INFO("W32:vendor/device;U8:revision;D:#", pci, dc, dc_devs, 353 nitems(dc_devs) - 1); 354 DRIVER_MODULE(miibus, dc, miibus_driver, NULL, NULL); 355 356 #define DC_SETBIT(sc, reg, x) \ 357 CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) | (x)) 358 359 #define DC_CLRBIT(sc, reg, x) \ 360 CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) & ~(x)) 361 362 #define SIO_SET(x) DC_SETBIT(sc, DC_SIO, (x)) 363 #define SIO_CLR(x) DC_CLRBIT(sc, DC_SIO, (x)) 364 365 static void 366 dc_delay(struct dc_softc *sc) 367 { 368 int idx; 369 370 for (idx = (300 / 33) + 1; idx > 0; idx--) 371 CSR_READ_4(sc, DC_BUSCTL); 372 } 373 374 static void 375 dc_eeprom_width(struct dc_softc *sc) 376 { 377 int i; 378 379 /* Force EEPROM to idle state. */ 380 dc_eeprom_idle(sc); 381 382 /* Enter EEPROM access mode. */ 383 CSR_WRITE_4(sc, DC_SIO, DC_SIO_EESEL); 384 dc_delay(sc); 385 DC_SETBIT(sc, DC_SIO, DC_SIO_ROMCTL_READ); 386 dc_delay(sc); 387 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); 388 dc_delay(sc); 389 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CS); 390 dc_delay(sc); 391 392 for (i = 3; i--;) { 393 if (6 & (1 << i)) 394 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_DATAIN); 395 else 396 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_DATAIN); 397 dc_delay(sc); 398 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CLK); 399 dc_delay(sc); 400 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); 401 dc_delay(sc); 402 } 403 404 for (i = 1; i <= 12; i++) { 405 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CLK); 406 dc_delay(sc); 407 if (!(CSR_READ_4(sc, DC_SIO) & DC_SIO_EE_DATAOUT)) { 408 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); 409 dc_delay(sc); 410 break; 411 } 412 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); 413 dc_delay(sc); 414 } 415 416 /* Turn off EEPROM access mode. */ 417 dc_eeprom_idle(sc); 418 419 if (i < 4 || i > 12) 420 sc->dc_romwidth = 6; 421 else 422 sc->dc_romwidth = i; 423 424 /* Enter EEPROM access mode. */ 425 CSR_WRITE_4(sc, DC_SIO, DC_SIO_EESEL); 426 dc_delay(sc); 427 DC_SETBIT(sc, DC_SIO, DC_SIO_ROMCTL_READ); 428 dc_delay(sc); 429 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); 430 dc_delay(sc); 431 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CS); 432 dc_delay(sc); 433 434 /* Turn off EEPROM access mode. */ 435 dc_eeprom_idle(sc); 436 } 437 438 static void 439 dc_eeprom_idle(struct dc_softc *sc) 440 { 441 int i; 442 443 CSR_WRITE_4(sc, DC_SIO, DC_SIO_EESEL); 444 dc_delay(sc); 445 DC_SETBIT(sc, DC_SIO, DC_SIO_ROMCTL_READ); 446 dc_delay(sc); 447 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); 448 dc_delay(sc); 449 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CS); 450 dc_delay(sc); 451 452 for (i = 0; i < 25; i++) { 453 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); 454 dc_delay(sc); 455 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CLK); 456 dc_delay(sc); 457 } 458 459 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); 460 dc_delay(sc); 461 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CS); 462 dc_delay(sc); 463 CSR_WRITE_4(sc, DC_SIO, 0x00000000); 464 } 465 466 /* 467 * Send a read command and address to the EEPROM, check for ACK. 468 */ 469 static void 470 dc_eeprom_putbyte(struct dc_softc *sc, int addr) 471 { 472 int d, i; 473 474 d = DC_EECMD_READ >> 6; 475 for (i = 3; i--; ) { 476 if (d & (1 << i)) 477 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_DATAIN); 478 else 479 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_DATAIN); 480 dc_delay(sc); 481 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CLK); 482 dc_delay(sc); 483 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); 484 dc_delay(sc); 485 } 486 487 /* 488 * Feed in each bit and strobe the clock. 489 */ 490 for (i = sc->dc_romwidth; i--;) { 491 if (addr & (1 << i)) { 492 SIO_SET(DC_SIO_EE_DATAIN); 493 } else { 494 SIO_CLR(DC_SIO_EE_DATAIN); 495 } 496 dc_delay(sc); 497 SIO_SET(DC_SIO_EE_CLK); 498 dc_delay(sc); 499 SIO_CLR(DC_SIO_EE_CLK); 500 dc_delay(sc); 501 } 502 } 503 504 /* 505 * Read a word of data stored in the EEPROM at address 'addr.' 506 * The PNIC 82c168/82c169 has its own non-standard way to read 507 * the EEPROM. 508 */ 509 static void 510 dc_eeprom_getword_pnic(struct dc_softc *sc, int addr, uint16_t *dest) 511 { 512 int i; 513 uint32_t r; 514 515 CSR_WRITE_4(sc, DC_PN_SIOCTL, DC_PN_EEOPCODE_READ | addr); 516 517 for (i = 0; i < DC_TIMEOUT; i++) { 518 DELAY(1); 519 r = CSR_READ_4(sc, DC_SIO); 520 if (!(r & DC_PN_SIOCTL_BUSY)) { 521 *dest = (uint16_t)(r & 0xFFFF); 522 return; 523 } 524 } 525 } 526 527 /* 528 * Read a word of data stored in the EEPROM at address 'addr.' 529 * The Xircom X3201 has its own non-standard way to read 530 * the EEPROM, too. 531 */ 532 static void 533 dc_eeprom_getword_xircom(struct dc_softc *sc, int addr, uint16_t *dest) 534 { 535 536 SIO_SET(DC_SIO_ROMSEL | DC_SIO_ROMCTL_READ); 537 538 addr *= 2; 539 CSR_WRITE_4(sc, DC_ROM, addr | 0x160); 540 *dest = (uint16_t)CSR_READ_4(sc, DC_SIO) & 0xff; 541 addr += 1; 542 CSR_WRITE_4(sc, DC_ROM, addr | 0x160); 543 *dest |= ((uint16_t)CSR_READ_4(sc, DC_SIO) & 0xff) << 8; 544 545 SIO_CLR(DC_SIO_ROMSEL | DC_SIO_ROMCTL_READ); 546 } 547 548 /* 549 * Read a word of data stored in the EEPROM at address 'addr.' 550 */ 551 static void 552 dc_eeprom_getword(struct dc_softc *sc, int addr, uint16_t *dest) 553 { 554 int i; 555 uint16_t word = 0; 556 557 /* Force EEPROM to idle state. */ 558 dc_eeprom_idle(sc); 559 560 /* Enter EEPROM access mode. */ 561 CSR_WRITE_4(sc, DC_SIO, DC_SIO_EESEL); 562 dc_delay(sc); 563 DC_SETBIT(sc, DC_SIO, DC_SIO_ROMCTL_READ); 564 dc_delay(sc); 565 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); 566 dc_delay(sc); 567 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CS); 568 dc_delay(sc); 569 570 /* 571 * Send address of word we want to read. 572 */ 573 dc_eeprom_putbyte(sc, addr); 574 575 /* 576 * Start reading bits from EEPROM. 577 */ 578 for (i = 0x8000; i; i >>= 1) { 579 SIO_SET(DC_SIO_EE_CLK); 580 dc_delay(sc); 581 if (CSR_READ_4(sc, DC_SIO) & DC_SIO_EE_DATAOUT) 582 word |= i; 583 dc_delay(sc); 584 SIO_CLR(DC_SIO_EE_CLK); 585 dc_delay(sc); 586 } 587 588 /* Turn off EEPROM access mode. */ 589 dc_eeprom_idle(sc); 590 591 *dest = word; 592 } 593 594 /* 595 * Read a sequence of words from the EEPROM. 596 */ 597 static void 598 dc_read_eeprom(struct dc_softc *sc, caddr_t dest, int off, int cnt, int be) 599 { 600 int i; 601 uint16_t word = 0, *ptr; 602 603 for (i = 0; i < cnt; i++) { 604 if (DC_IS_PNIC(sc)) 605 dc_eeprom_getword_pnic(sc, off + i, &word); 606 else if (DC_IS_XIRCOM(sc)) 607 dc_eeprom_getword_xircom(sc, off + i, &word); 608 else 609 dc_eeprom_getword(sc, off + i, &word); 610 ptr = (uint16_t *)(dest + (i * 2)); 611 if (be) 612 *ptr = be16toh(word); 613 else 614 *ptr = le16toh(word); 615 } 616 } 617 618 /* 619 * Write the MII serial port for the MII bit-bang module. 620 */ 621 static void 622 dc_mii_bitbang_write(device_t dev, uint32_t val) 623 { 624 struct dc_softc *sc; 625 626 sc = device_get_softc(dev); 627 628 CSR_WRITE_4(sc, DC_SIO, val); 629 CSR_BARRIER_4(sc, DC_SIO, 630 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 631 } 632 633 /* 634 * Read the MII serial port for the MII bit-bang module. 635 */ 636 static uint32_t 637 dc_mii_bitbang_read(device_t dev) 638 { 639 struct dc_softc *sc; 640 uint32_t val; 641 642 sc = device_get_softc(dev); 643 644 val = CSR_READ_4(sc, DC_SIO); 645 CSR_BARRIER_4(sc, DC_SIO, 646 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 647 648 return (val); 649 } 650 651 static int 652 dc_miibus_readreg(device_t dev, int phy, int reg) 653 { 654 struct dc_softc *sc; 655 int i, rval, phy_reg = 0; 656 657 sc = device_get_softc(dev); 658 659 if (sc->dc_pmode != DC_PMODE_MII) { 660 if (phy == (MII_NPHY - 1)) { 661 switch (reg) { 662 case MII_BMSR: 663 /* 664 * Fake something to make the probe 665 * code think there's a PHY here. 666 */ 667 return (BMSR_MEDIAMASK); 668 case MII_PHYIDR1: 669 if (DC_IS_PNIC(sc)) 670 return (DC_VENDORID_LO); 671 return (DC_VENDORID_DEC); 672 case MII_PHYIDR2: 673 if (DC_IS_PNIC(sc)) 674 return (DC_DEVICEID_82C168); 675 return (DC_DEVICEID_21143); 676 default: 677 return (0); 678 } 679 } else 680 return (0); 681 } 682 683 if (DC_IS_PNIC(sc)) { 684 CSR_WRITE_4(sc, DC_PN_MII, DC_PN_MIIOPCODE_READ | 685 (phy << 23) | (reg << 18)); 686 for (i = 0; i < DC_TIMEOUT; i++) { 687 DELAY(1); 688 rval = CSR_READ_4(sc, DC_PN_MII); 689 if (!(rval & DC_PN_MII_BUSY)) { 690 rval &= 0xFFFF; 691 return (rval == 0xFFFF ? 0 : rval); 692 } 693 } 694 return (0); 695 } 696 697 if (sc->dc_type == DC_TYPE_ULI_M5263) { 698 CSR_WRITE_4(sc, DC_ROM, 699 ((phy << DC_ULI_PHY_ADDR_SHIFT) & DC_ULI_PHY_ADDR_MASK) | 700 ((reg << DC_ULI_PHY_REG_SHIFT) & DC_ULI_PHY_REG_MASK) | 701 DC_ULI_PHY_OP_READ); 702 for (i = 0; i < DC_TIMEOUT; i++) { 703 DELAY(1); 704 rval = CSR_READ_4(sc, DC_ROM); 705 if ((rval & DC_ULI_PHY_OP_DONE) != 0) { 706 return (rval & DC_ULI_PHY_DATA_MASK); 707 } 708 } 709 if (i == DC_TIMEOUT) 710 device_printf(dev, "phy read timed out\n"); 711 return (0); 712 } 713 714 if (DC_IS_COMET(sc)) { 715 switch (reg) { 716 case MII_BMCR: 717 phy_reg = DC_AL_BMCR; 718 break; 719 case MII_BMSR: 720 phy_reg = DC_AL_BMSR; 721 break; 722 case MII_PHYIDR1: 723 phy_reg = DC_AL_VENID; 724 break; 725 case MII_PHYIDR2: 726 phy_reg = DC_AL_DEVID; 727 break; 728 case MII_ANAR: 729 phy_reg = DC_AL_ANAR; 730 break; 731 case MII_ANLPAR: 732 phy_reg = DC_AL_LPAR; 733 break; 734 case MII_ANER: 735 phy_reg = DC_AL_ANER; 736 break; 737 default: 738 device_printf(dev, "phy_read: bad phy register %x\n", 739 reg); 740 return (0); 741 } 742 743 rval = CSR_READ_4(sc, phy_reg) & 0x0000FFFF; 744 if (rval == 0xFFFF) 745 return (0); 746 return (rval); 747 } 748 749 if (sc->dc_type == DC_TYPE_98713) { 750 phy_reg = CSR_READ_4(sc, DC_NETCFG); 751 CSR_WRITE_4(sc, DC_NETCFG, phy_reg & ~DC_NETCFG_PORTSEL); 752 } 753 rval = mii_bitbang_readreg(dev, &dc_mii_bitbang_ops, phy, reg); 754 if (sc->dc_type == DC_TYPE_98713) 755 CSR_WRITE_4(sc, DC_NETCFG, phy_reg); 756 757 return (rval); 758 } 759 760 static int 761 dc_miibus_writereg(device_t dev, int phy, int reg, int data) 762 { 763 struct dc_softc *sc; 764 int i, phy_reg = 0; 765 766 sc = device_get_softc(dev); 767 768 if (DC_IS_PNIC(sc)) { 769 CSR_WRITE_4(sc, DC_PN_MII, DC_PN_MIIOPCODE_WRITE | 770 (phy << 23) | (reg << 10) | data); 771 for (i = 0; i < DC_TIMEOUT; i++) { 772 if (!(CSR_READ_4(sc, DC_PN_MII) & DC_PN_MII_BUSY)) 773 break; 774 } 775 return (0); 776 } 777 778 if (sc->dc_type == DC_TYPE_ULI_M5263) { 779 CSR_WRITE_4(sc, DC_ROM, 780 ((phy << DC_ULI_PHY_ADDR_SHIFT) & DC_ULI_PHY_ADDR_MASK) | 781 ((reg << DC_ULI_PHY_REG_SHIFT) & DC_ULI_PHY_REG_MASK) | 782 ((data << DC_ULI_PHY_DATA_SHIFT) & DC_ULI_PHY_DATA_MASK) | 783 DC_ULI_PHY_OP_WRITE); 784 DELAY(1); 785 return (0); 786 } 787 788 if (DC_IS_COMET(sc)) { 789 switch (reg) { 790 case MII_BMCR: 791 phy_reg = DC_AL_BMCR; 792 break; 793 case MII_BMSR: 794 phy_reg = DC_AL_BMSR; 795 break; 796 case MII_PHYIDR1: 797 phy_reg = DC_AL_VENID; 798 break; 799 case MII_PHYIDR2: 800 phy_reg = DC_AL_DEVID; 801 break; 802 case MII_ANAR: 803 phy_reg = DC_AL_ANAR; 804 break; 805 case MII_ANLPAR: 806 phy_reg = DC_AL_LPAR; 807 break; 808 case MII_ANER: 809 phy_reg = DC_AL_ANER; 810 break; 811 default: 812 device_printf(dev, "phy_write: bad phy register %x\n", 813 reg); 814 return (0); 815 break; 816 } 817 818 CSR_WRITE_4(sc, phy_reg, data); 819 return (0); 820 } 821 822 if (sc->dc_type == DC_TYPE_98713) { 823 phy_reg = CSR_READ_4(sc, DC_NETCFG); 824 CSR_WRITE_4(sc, DC_NETCFG, phy_reg & ~DC_NETCFG_PORTSEL); 825 } 826 mii_bitbang_writereg(dev, &dc_mii_bitbang_ops, phy, reg, data); 827 if (sc->dc_type == DC_TYPE_98713) 828 CSR_WRITE_4(sc, DC_NETCFG, phy_reg); 829 830 return (0); 831 } 832 833 static void 834 dc_miibus_statchg(device_t dev) 835 { 836 struct dc_softc *sc; 837 if_t ifp; 838 struct mii_data *mii; 839 struct ifmedia *ifm; 840 841 sc = device_get_softc(dev); 842 843 mii = device_get_softc(sc->dc_miibus); 844 ifp = sc->dc_ifp; 845 if (mii == NULL || ifp == NULL || 846 (if_getdrvflags(ifp) & IFF_DRV_RUNNING) == 0) 847 return; 848 849 ifm = &mii->mii_media; 850 if (DC_IS_DAVICOM(sc) && IFM_SUBTYPE(ifm->ifm_media) == IFM_HPNA_1) { 851 dc_setcfg(sc, ifm->ifm_media); 852 return; 853 } else if (!DC_IS_ADMTEK(sc)) 854 dc_setcfg(sc, mii->mii_media_active); 855 856 sc->dc_link = 0; 857 if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) == 858 (IFM_ACTIVE | IFM_AVALID)) { 859 switch (IFM_SUBTYPE(mii->mii_media_active)) { 860 case IFM_10_T: 861 case IFM_100_TX: 862 sc->dc_link = 1; 863 break; 864 } 865 } 866 } 867 868 /* 869 * Special support for DM9102A cards with HomePNA PHYs. Note: 870 * with the Davicom DM9102A/DM9801 eval board that I have, it seems 871 * to be impossible to talk to the management interface of the DM9801 872 * PHY (its MDIO pin is not connected to anything). Consequently, 873 * the driver has to just 'know' about the additional mode and deal 874 * with it itself. *sigh* 875 */ 876 static void 877 dc_miibus_mediainit(device_t dev) 878 { 879 struct dc_softc *sc; 880 struct mii_data *mii; 881 struct ifmedia *ifm; 882 int rev; 883 884 rev = pci_get_revid(dev); 885 886 sc = device_get_softc(dev); 887 mii = device_get_softc(sc->dc_miibus); 888 ifm = &mii->mii_media; 889 890 if (DC_IS_DAVICOM(sc) && rev >= DC_REVISION_DM9102A) 891 ifmedia_add(ifm, IFM_ETHER | IFM_HPNA_1, 0, NULL); 892 } 893 894 #define DC_BITS_512 9 895 #define DC_BITS_128 7 896 #define DC_BITS_64 6 897 898 static uint32_t 899 dc_mchash_le(struct dc_softc *sc, const uint8_t *addr) 900 { 901 uint32_t crc; 902 903 /* Compute CRC for the address value. */ 904 crc = ether_crc32_le(addr, ETHER_ADDR_LEN); 905 906 /* 907 * The hash table on the PNIC II and the MX98715AEC-C/D/E 908 * chips is only 128 bits wide. 909 */ 910 if (sc->dc_flags & DC_128BIT_HASH) 911 return (crc & ((1 << DC_BITS_128) - 1)); 912 913 /* The hash table on the MX98715BEC is only 64 bits wide. */ 914 if (sc->dc_flags & DC_64BIT_HASH) 915 return (crc & ((1 << DC_BITS_64) - 1)); 916 917 /* Xircom's hash filtering table is different (read: weird) */ 918 /* Xircom uses the LEAST significant bits */ 919 if (DC_IS_XIRCOM(sc)) { 920 if ((crc & 0x180) == 0x180) 921 return ((crc & 0x0F) + (crc & 0x70) * 3 + (14 << 4)); 922 else 923 return ((crc & 0x1F) + ((crc >> 1) & 0xF0) * 3 + 924 (12 << 4)); 925 } 926 927 return (crc & ((1 << DC_BITS_512) - 1)); 928 } 929 930 /* 931 * Calculate CRC of a multicast group address, return the lower 6 bits. 932 */ 933 static uint32_t 934 dc_mchash_be(const uint8_t *addr) 935 { 936 uint32_t crc; 937 938 /* Compute CRC for the address value. */ 939 crc = ether_crc32_be(addr, ETHER_ADDR_LEN); 940 941 /* Return the filter bit position. */ 942 return ((crc >> 26) & 0x0000003F); 943 } 944 945 /* 946 * 21143-style RX filter setup routine. Filter programming is done by 947 * downloading a special setup frame into the TX engine. 21143, Macronix, 948 * PNIC, PNIC II and Davicom chips are programmed this way. 949 * 950 * We always program the chip using 'hash perfect' mode, i.e. one perfect 951 * address (our node address) and a 512-bit hash filter for multicast 952 * frames. We also sneak the broadcast address into the hash filter since 953 * we need that too. 954 */ 955 static u_int 956 dc_hash_maddr_21143(void *arg, struct sockaddr_dl *sdl, u_int cnt) 957 { 958 struct dc_softc *sc = arg; 959 uint32_t h; 960 961 h = dc_mchash_le(sc, LLADDR(sdl)); 962 sc->dc_cdata.dc_sbuf[h >> 4] |= htole32(1 << (h & 0xF)); 963 964 return (1); 965 } 966 967 static void 968 dc_setfilt_21143(struct dc_softc *sc) 969 { 970 uint16_t eaddr[(ETHER_ADDR_LEN+1)/2]; 971 struct dc_desc *sframe; 972 uint32_t h, *sp; 973 if_t ifp; 974 int i; 975 976 ifp = sc->dc_ifp; 977 978 i = sc->dc_cdata.dc_tx_prod; 979 DC_INC(sc->dc_cdata.dc_tx_prod, DC_TX_LIST_CNT); 980 sc->dc_cdata.dc_tx_cnt++; 981 sframe = &sc->dc_ldata.dc_tx_list[i]; 982 sp = sc->dc_cdata.dc_sbuf; 983 bzero(sp, DC_SFRAME_LEN); 984 985 sframe->dc_data = htole32(DC_ADDR_LO(sc->dc_saddr)); 986 sframe->dc_ctl = htole32(DC_SFRAME_LEN | DC_TXCTL_SETUP | 987 DC_TXCTL_TLINK | DC_FILTER_HASHPERF | DC_TXCTL_FINT); 988 989 sc->dc_cdata.dc_tx_chain[i] = (struct mbuf *)sc->dc_cdata.dc_sbuf; 990 991 /* If we want promiscuous mode, set the allframes bit. */ 992 if (if_getflags(ifp) & IFF_PROMISC) 993 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC); 994 else 995 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC); 996 997 if (if_getflags(ifp) & IFF_ALLMULTI) 998 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI); 999 else 1000 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI); 1001 1002 if_foreach_llmaddr(ifp, dc_hash_maddr_21143, sp); 1003 1004 if (if_getflags(ifp) & IFF_BROADCAST) { 1005 h = dc_mchash_le(sc, if_getbroadcastaddr(ifp)); 1006 sp[h >> 4] |= htole32(1 << (h & 0xF)); 1007 } 1008 1009 /* Set our MAC address. */ 1010 bcopy(if_getlladdr(sc->dc_ifp), eaddr, ETHER_ADDR_LEN); 1011 sp[39] = DC_SP_MAC(eaddr[0]); 1012 sp[40] = DC_SP_MAC(eaddr[1]); 1013 sp[41] = DC_SP_MAC(eaddr[2]); 1014 1015 sframe->dc_status = htole32(DC_TXSTAT_OWN); 1016 bus_dmamap_sync(sc->dc_tx_ltag, sc->dc_tx_lmap, BUS_DMASYNC_PREREAD | 1017 BUS_DMASYNC_PREWRITE); 1018 bus_dmamap_sync(sc->dc_stag, sc->dc_smap, BUS_DMASYNC_PREWRITE); 1019 CSR_WRITE_4(sc, DC_TXSTART, 0xFFFFFFFF); 1020 1021 /* 1022 * The PNIC takes an exceedingly long time to process its 1023 * setup frame; wait 10ms after posting the setup frame 1024 * before proceeding, just so it has time to swallow its 1025 * medicine. 1026 */ 1027 DELAY(10000); 1028 1029 sc->dc_wdog_timer = 5; 1030 } 1031 1032 static u_int 1033 dc_hash_maddr_admtek_be(void *arg, struct sockaddr_dl *sdl, u_int cnt) 1034 { 1035 uint32_t *hashes = arg; 1036 int h = 0; 1037 1038 h = dc_mchash_be(LLADDR(sdl)); 1039 if (h < 32) 1040 hashes[0] |= (1 << h); 1041 else 1042 hashes[1] |= (1 << (h - 32)); 1043 1044 return (1); 1045 } 1046 1047 struct dc_hash_maddr_admtek_le_ctx { 1048 struct dc_softc *sc; 1049 uint32_t hashes[2]; 1050 }; 1051 1052 static u_int 1053 dc_hash_maddr_admtek_le(void *arg, struct sockaddr_dl *sdl, u_int cnt) 1054 { 1055 struct dc_hash_maddr_admtek_le_ctx *ctx = arg; 1056 int h = 0; 1057 1058 h = dc_mchash_le(ctx->sc, LLADDR(sdl)); 1059 if (h < 32) 1060 ctx->hashes[0] |= (1 << h); 1061 else 1062 ctx->hashes[1] |= (1 << (h - 32)); 1063 1064 return (1); 1065 } 1066 1067 static void 1068 dc_setfilt_admtek(struct dc_softc *sc) 1069 { 1070 uint8_t eaddr[ETHER_ADDR_LEN]; 1071 if_t ifp; 1072 struct dc_hash_maddr_admtek_le_ctx ctx = { sc, { 0, 0 }}; 1073 1074 ifp = sc->dc_ifp; 1075 1076 /* Init our MAC address. */ 1077 bcopy(if_getlladdr(sc->dc_ifp), eaddr, ETHER_ADDR_LEN); 1078 CSR_WRITE_4(sc, DC_AL_PAR0, eaddr[3] << 24 | eaddr[2] << 16 | 1079 eaddr[1] << 8 | eaddr[0]); 1080 CSR_WRITE_4(sc, DC_AL_PAR1, eaddr[5] << 8 | eaddr[4]); 1081 1082 /* If we want promiscuous mode, set the allframes bit. */ 1083 if (if_getflags(ifp) & IFF_PROMISC) 1084 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC); 1085 else 1086 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC); 1087 1088 if (if_getflags(ifp) & IFF_ALLMULTI) 1089 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI); 1090 else 1091 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI); 1092 1093 /* First, zot all the existing hash bits. */ 1094 CSR_WRITE_4(sc, DC_AL_MAR0, 0); 1095 CSR_WRITE_4(sc, DC_AL_MAR1, 0); 1096 1097 /* 1098 * If we're already in promisc or allmulti mode, we 1099 * don't have to bother programming the multicast filter. 1100 */ 1101 if (if_getflags(ifp) & (IFF_PROMISC | IFF_ALLMULTI)) 1102 return; 1103 1104 /* Now program new ones. */ 1105 if (DC_IS_CENTAUR(sc)) 1106 if_foreach_llmaddr(ifp, dc_hash_maddr_admtek_le, &ctx); 1107 else 1108 if_foreach_llmaddr(ifp, dc_hash_maddr_admtek_be, &ctx.hashes); 1109 1110 CSR_WRITE_4(sc, DC_AL_MAR0, ctx.hashes[0]); 1111 CSR_WRITE_4(sc, DC_AL_MAR1, ctx.hashes[1]); 1112 } 1113 1114 static void 1115 dc_setfilt_asix(struct dc_softc *sc) 1116 { 1117 uint32_t eaddr[(ETHER_ADDR_LEN+3)/4]; 1118 if_t ifp; 1119 uint32_t hashes[2] = { 0, 0 }; 1120 1121 ifp = sc->dc_ifp; 1122 1123 /* Init our MAC address. */ 1124 bcopy(if_getlladdr(sc->dc_ifp), eaddr, ETHER_ADDR_LEN); 1125 CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_PAR0); 1126 CSR_WRITE_4(sc, DC_AX_FILTDATA, eaddr[0]); 1127 CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_PAR1); 1128 CSR_WRITE_4(sc, DC_AX_FILTDATA, eaddr[1]); 1129 1130 /* If we want promiscuous mode, set the allframes bit. */ 1131 if (if_getflags(ifp) & IFF_PROMISC) 1132 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC); 1133 else 1134 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC); 1135 1136 if (if_getflags(ifp) & IFF_ALLMULTI) 1137 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI); 1138 else 1139 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI); 1140 1141 /* 1142 * The ASIX chip has a special bit to enable reception 1143 * of broadcast frames. 1144 */ 1145 if (if_getflags(ifp) & IFF_BROADCAST) 1146 DC_SETBIT(sc, DC_NETCFG, DC_AX_NETCFG_RX_BROAD); 1147 else 1148 DC_CLRBIT(sc, DC_NETCFG, DC_AX_NETCFG_RX_BROAD); 1149 1150 /* first, zot all the existing hash bits */ 1151 CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_MAR0); 1152 CSR_WRITE_4(sc, DC_AX_FILTDATA, 0); 1153 CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_MAR1); 1154 CSR_WRITE_4(sc, DC_AX_FILTDATA, 0); 1155 1156 /* 1157 * If we're already in promisc or allmulti mode, we 1158 * don't have to bother programming the multicast filter. 1159 */ 1160 if (if_getflags(ifp) & (IFF_PROMISC | IFF_ALLMULTI)) 1161 return; 1162 1163 /* now program new ones */ 1164 if_foreach_llmaddr(ifp, dc_hash_maddr_admtek_be, hashes); 1165 1166 CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_MAR0); 1167 CSR_WRITE_4(sc, DC_AX_FILTDATA, hashes[0]); 1168 CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_MAR1); 1169 CSR_WRITE_4(sc, DC_AX_FILTDATA, hashes[1]); 1170 } 1171 1172 static u_int 1173 dc_hash_maddr_uli(void *arg, struct sockaddr_dl *sdl, u_int mcnt) 1174 { 1175 uint32_t **sp = arg; 1176 uint8_t *ma; 1177 1178 if (mcnt == DC_ULI_FILTER_NPERF) 1179 return (0); 1180 ma = LLADDR(sdl); 1181 *(*sp)++ = DC_SP_MAC(ma[1] << 8 | ma[0]); 1182 *(*sp)++ = DC_SP_MAC(ma[3] << 8 | ma[2]); 1183 *(*sp)++ = DC_SP_MAC(ma[5] << 8 | ma[4]); 1184 1185 return (1); 1186 } 1187 1188 static void 1189 dc_setfilt_uli(struct dc_softc *sc) 1190 { 1191 uint8_t eaddr[ETHER_ADDR_LEN]; 1192 if_t ifp; 1193 struct dc_desc *sframe; 1194 uint32_t filter, *sp; 1195 int i, mcnt; 1196 1197 ifp = sc->dc_ifp; 1198 1199 i = sc->dc_cdata.dc_tx_prod; 1200 DC_INC(sc->dc_cdata.dc_tx_prod, DC_TX_LIST_CNT); 1201 sc->dc_cdata.dc_tx_cnt++; 1202 sframe = &sc->dc_ldata.dc_tx_list[i]; 1203 sp = sc->dc_cdata.dc_sbuf; 1204 bzero(sp, DC_SFRAME_LEN); 1205 1206 sframe->dc_data = htole32(DC_ADDR_LO(sc->dc_saddr)); 1207 sframe->dc_ctl = htole32(DC_SFRAME_LEN | DC_TXCTL_SETUP | 1208 DC_TXCTL_TLINK | DC_FILTER_PERFECT | DC_TXCTL_FINT); 1209 1210 sc->dc_cdata.dc_tx_chain[i] = (struct mbuf *)sc->dc_cdata.dc_sbuf; 1211 1212 /* Set station address. */ 1213 bcopy(if_getlladdr(sc->dc_ifp), eaddr, ETHER_ADDR_LEN); 1214 *sp++ = DC_SP_MAC(eaddr[1] << 8 | eaddr[0]); 1215 *sp++ = DC_SP_MAC(eaddr[3] << 8 | eaddr[2]); 1216 *sp++ = DC_SP_MAC(eaddr[5] << 8 | eaddr[4]); 1217 1218 /* Set broadcast address. */ 1219 *sp++ = DC_SP_MAC(0xFFFF); 1220 *sp++ = DC_SP_MAC(0xFFFF); 1221 *sp++ = DC_SP_MAC(0xFFFF); 1222 1223 /* Extract current filter configuration. */ 1224 filter = CSR_READ_4(sc, DC_NETCFG); 1225 filter &= ~(DC_NETCFG_RX_PROMISC | DC_NETCFG_RX_ALLMULTI); 1226 1227 /* Now build perfect filters. */ 1228 mcnt = if_foreach_llmaddr(ifp, dc_hash_maddr_uli, &sp); 1229 1230 if (mcnt == DC_ULI_FILTER_NPERF) 1231 filter |= DC_NETCFG_RX_ALLMULTI; 1232 else 1233 for (; mcnt < DC_ULI_FILTER_NPERF; mcnt++) { 1234 *sp++ = DC_SP_MAC(0xFFFF); 1235 *sp++ = DC_SP_MAC(0xFFFF); 1236 *sp++ = DC_SP_MAC(0xFFFF); 1237 } 1238 1239 if (filter & (DC_NETCFG_TX_ON | DC_NETCFG_RX_ON)) 1240 CSR_WRITE_4(sc, DC_NETCFG, 1241 filter & ~(DC_NETCFG_TX_ON | DC_NETCFG_RX_ON)); 1242 if (if_getflags(ifp) & IFF_PROMISC) 1243 filter |= DC_NETCFG_RX_PROMISC | DC_NETCFG_RX_ALLMULTI; 1244 if (if_getflags(ifp) & IFF_ALLMULTI) 1245 filter |= DC_NETCFG_RX_ALLMULTI; 1246 CSR_WRITE_4(sc, DC_NETCFG, 1247 filter & ~(DC_NETCFG_TX_ON | DC_NETCFG_RX_ON)); 1248 if (filter & (DC_NETCFG_TX_ON | DC_NETCFG_RX_ON)) 1249 CSR_WRITE_4(sc, DC_NETCFG, filter); 1250 1251 sframe->dc_status = htole32(DC_TXSTAT_OWN); 1252 bus_dmamap_sync(sc->dc_tx_ltag, sc->dc_tx_lmap, BUS_DMASYNC_PREREAD | 1253 BUS_DMASYNC_PREWRITE); 1254 bus_dmamap_sync(sc->dc_stag, sc->dc_smap, BUS_DMASYNC_PREWRITE); 1255 CSR_WRITE_4(sc, DC_TXSTART, 0xFFFFFFFF); 1256 1257 /* 1258 * Wait some time... 1259 */ 1260 DELAY(1000); 1261 1262 sc->dc_wdog_timer = 5; 1263 } 1264 1265 static u_int 1266 dc_hash_maddr_xircom(void *arg, struct sockaddr_dl *sdl, u_int cnt) 1267 { 1268 struct dc_softc *sc = arg; 1269 uint32_t h; 1270 1271 h = dc_mchash_le(sc, LLADDR(sdl)); 1272 sc->dc_cdata.dc_sbuf[h >> 4] |= htole32(1 << (h & 0xF)); 1273 return (1); 1274 } 1275 1276 static void 1277 dc_setfilt_xircom(struct dc_softc *sc) 1278 { 1279 uint16_t eaddr[(ETHER_ADDR_LEN+1)/2]; 1280 if_t ifp; 1281 struct dc_desc *sframe; 1282 uint32_t h, *sp; 1283 int i; 1284 1285 ifp = sc->dc_ifp; 1286 DC_CLRBIT(sc, DC_NETCFG, (DC_NETCFG_TX_ON | DC_NETCFG_RX_ON)); 1287 1288 i = sc->dc_cdata.dc_tx_prod; 1289 DC_INC(sc->dc_cdata.dc_tx_prod, DC_TX_LIST_CNT); 1290 sc->dc_cdata.dc_tx_cnt++; 1291 sframe = &sc->dc_ldata.dc_tx_list[i]; 1292 sp = sc->dc_cdata.dc_sbuf; 1293 bzero(sp, DC_SFRAME_LEN); 1294 1295 sframe->dc_data = htole32(DC_ADDR_LO(sc->dc_saddr)); 1296 sframe->dc_ctl = htole32(DC_SFRAME_LEN | DC_TXCTL_SETUP | 1297 DC_TXCTL_TLINK | DC_FILTER_HASHPERF | DC_TXCTL_FINT); 1298 1299 sc->dc_cdata.dc_tx_chain[i] = (struct mbuf *)sc->dc_cdata.dc_sbuf; 1300 1301 /* If we want promiscuous mode, set the allframes bit. */ 1302 if (if_getflags(ifp) & IFF_PROMISC) 1303 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC); 1304 else 1305 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC); 1306 1307 if (if_getflags(ifp) & IFF_ALLMULTI) 1308 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI); 1309 else 1310 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI); 1311 1312 if_foreach_llmaddr(ifp, dc_hash_maddr_xircom, &sp); 1313 1314 if (if_getflags(ifp) & IFF_BROADCAST) { 1315 h = dc_mchash_le(sc, if_getbroadcastaddr(ifp)); 1316 sp[h >> 4] |= htole32(1 << (h & 0xF)); 1317 } 1318 1319 /* Set our MAC address. */ 1320 bcopy(if_getlladdr(sc->dc_ifp), eaddr, ETHER_ADDR_LEN); 1321 sp[0] = DC_SP_MAC(eaddr[0]); 1322 sp[1] = DC_SP_MAC(eaddr[1]); 1323 sp[2] = DC_SP_MAC(eaddr[2]); 1324 1325 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_TX_ON); 1326 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_ON); 1327 sframe->dc_status = htole32(DC_TXSTAT_OWN); 1328 bus_dmamap_sync(sc->dc_tx_ltag, sc->dc_tx_lmap, BUS_DMASYNC_PREREAD | 1329 BUS_DMASYNC_PREWRITE); 1330 bus_dmamap_sync(sc->dc_stag, sc->dc_smap, BUS_DMASYNC_PREWRITE); 1331 CSR_WRITE_4(sc, DC_TXSTART, 0xFFFFFFFF); 1332 1333 /* 1334 * Wait some time... 1335 */ 1336 DELAY(1000); 1337 1338 sc->dc_wdog_timer = 5; 1339 } 1340 1341 static void 1342 dc_setfilt(struct dc_softc *sc) 1343 { 1344 1345 if (DC_IS_INTEL(sc) || DC_IS_MACRONIX(sc) || DC_IS_PNIC(sc) || 1346 DC_IS_PNICII(sc) || DC_IS_DAVICOM(sc) || DC_IS_CONEXANT(sc)) 1347 dc_setfilt_21143(sc); 1348 1349 if (DC_IS_ASIX(sc)) 1350 dc_setfilt_asix(sc); 1351 1352 if (DC_IS_ADMTEK(sc)) 1353 dc_setfilt_admtek(sc); 1354 1355 if (DC_IS_ULI(sc)) 1356 dc_setfilt_uli(sc); 1357 1358 if (DC_IS_XIRCOM(sc)) 1359 dc_setfilt_xircom(sc); 1360 } 1361 1362 static void 1363 dc_netcfg_wait(struct dc_softc *sc) 1364 { 1365 uint32_t isr; 1366 int i; 1367 1368 for (i = 0; i < DC_TIMEOUT; i++) { 1369 isr = CSR_READ_4(sc, DC_ISR); 1370 if (isr & DC_ISR_TX_IDLE && 1371 ((isr & DC_ISR_RX_STATE) == DC_RXSTATE_STOPPED || 1372 (isr & DC_ISR_RX_STATE) == DC_RXSTATE_WAIT)) 1373 break; 1374 DELAY(10); 1375 } 1376 if (i == DC_TIMEOUT && bus_child_present(sc->dc_dev)) { 1377 if (!(isr & DC_ISR_TX_IDLE) && !DC_IS_ASIX(sc)) 1378 device_printf(sc->dc_dev, 1379 "%s: failed to force tx to idle state\n", __func__); 1380 if (!((isr & DC_ISR_RX_STATE) == DC_RXSTATE_STOPPED || 1381 (isr & DC_ISR_RX_STATE) == DC_RXSTATE_WAIT) && 1382 !DC_HAS_BROKEN_RXSTATE(sc)) 1383 device_printf(sc->dc_dev, 1384 "%s: failed to force rx to idle state\n", __func__); 1385 } 1386 } 1387 1388 /* 1389 * In order to fiddle with the 'full-duplex' and '100Mbps' bits in 1390 * the netconfig register, we first have to put the transmit and/or 1391 * receive logic in the idle state. 1392 */ 1393 static void 1394 dc_setcfg(struct dc_softc *sc, int media) 1395 { 1396 int restart = 0, watchdogreg; 1397 1398 if (IFM_SUBTYPE(media) == IFM_NONE) 1399 return; 1400 1401 if (CSR_READ_4(sc, DC_NETCFG) & (DC_NETCFG_TX_ON | DC_NETCFG_RX_ON)) { 1402 restart = 1; 1403 DC_CLRBIT(sc, DC_NETCFG, (DC_NETCFG_TX_ON | DC_NETCFG_RX_ON)); 1404 dc_netcfg_wait(sc); 1405 } 1406 1407 if (IFM_SUBTYPE(media) == IFM_100_TX) { 1408 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_SPEEDSEL); 1409 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_HEARTBEAT); 1410 if (sc->dc_pmode == DC_PMODE_MII) { 1411 if (DC_IS_INTEL(sc)) { 1412 /* There's a write enable bit here that reads as 1. */ 1413 watchdogreg = CSR_READ_4(sc, DC_WATCHDOG); 1414 watchdogreg &= ~DC_WDOG_CTLWREN; 1415 watchdogreg |= DC_WDOG_JABBERDIS; 1416 CSR_WRITE_4(sc, DC_WATCHDOG, watchdogreg); 1417 } else { 1418 DC_SETBIT(sc, DC_WATCHDOG, DC_WDOG_JABBERDIS); 1419 } 1420 DC_CLRBIT(sc, DC_NETCFG, (DC_NETCFG_PCS | 1421 DC_NETCFG_PORTSEL | DC_NETCFG_SCRAMBLER)); 1422 if (sc->dc_type == DC_TYPE_98713) 1423 DC_SETBIT(sc, DC_NETCFG, (DC_NETCFG_PCS | 1424 DC_NETCFG_SCRAMBLER)); 1425 if (!DC_IS_DAVICOM(sc)) 1426 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL); 1427 DC_CLRBIT(sc, DC_10BTCTRL, 0xFFFF); 1428 } else { 1429 if (DC_IS_PNIC(sc)) { 1430 DC_PN_GPIO_SETBIT(sc, DC_PN_GPIO_SPEEDSEL); 1431 DC_PN_GPIO_SETBIT(sc, DC_PN_GPIO_100TX_LOOP); 1432 DC_SETBIT(sc, DC_PN_NWAY, DC_PN_NWAY_SPEEDSEL); 1433 } 1434 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL); 1435 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PCS); 1436 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_SCRAMBLER); 1437 } 1438 } 1439 1440 if (IFM_SUBTYPE(media) == IFM_10_T) { 1441 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_SPEEDSEL); 1442 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_HEARTBEAT); 1443 if (sc->dc_pmode == DC_PMODE_MII) { 1444 /* There's a write enable bit here that reads as 1. */ 1445 if (DC_IS_INTEL(sc)) { 1446 watchdogreg = CSR_READ_4(sc, DC_WATCHDOG); 1447 watchdogreg &= ~DC_WDOG_CTLWREN; 1448 watchdogreg |= DC_WDOG_JABBERDIS; 1449 CSR_WRITE_4(sc, DC_WATCHDOG, watchdogreg); 1450 } else { 1451 DC_SETBIT(sc, DC_WATCHDOG, DC_WDOG_JABBERDIS); 1452 } 1453 DC_CLRBIT(sc, DC_NETCFG, (DC_NETCFG_PCS | 1454 DC_NETCFG_PORTSEL | DC_NETCFG_SCRAMBLER)); 1455 if (sc->dc_type == DC_TYPE_98713) 1456 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PCS); 1457 if (!DC_IS_DAVICOM(sc)) 1458 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL); 1459 DC_CLRBIT(sc, DC_10BTCTRL, 0xFFFF); 1460 } else { 1461 if (DC_IS_PNIC(sc)) { 1462 DC_PN_GPIO_CLRBIT(sc, DC_PN_GPIO_SPEEDSEL); 1463 DC_PN_GPIO_SETBIT(sc, DC_PN_GPIO_100TX_LOOP); 1464 DC_CLRBIT(sc, DC_PN_NWAY, DC_PN_NWAY_SPEEDSEL); 1465 } 1466 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL); 1467 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_PCS); 1468 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_SCRAMBLER); 1469 if (DC_IS_INTEL(sc)) { 1470 DC_CLRBIT(sc, DC_SIARESET, DC_SIA_RESET); 1471 DC_CLRBIT(sc, DC_10BTCTRL, 0xFFFF); 1472 if ((media & IFM_GMASK) == IFM_FDX) 1473 DC_SETBIT(sc, DC_10BTCTRL, 0x7F3D); 1474 else 1475 DC_SETBIT(sc, DC_10BTCTRL, 0x7F3F); 1476 DC_SETBIT(sc, DC_SIARESET, DC_SIA_RESET); 1477 DC_CLRBIT(sc, DC_10BTCTRL, 1478 DC_TCTL_AUTONEGENBL); 1479 DELAY(20000); 1480 } 1481 } 1482 } 1483 1484 /* 1485 * If this is a Davicom DM9102A card with a DM9801 HomePNA 1486 * PHY and we want HomePNA mode, set the portsel bit to turn 1487 * on the external MII port. 1488 */ 1489 if (DC_IS_DAVICOM(sc)) { 1490 if (IFM_SUBTYPE(media) == IFM_HPNA_1) { 1491 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL); 1492 sc->dc_link = 1; 1493 } else { 1494 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL); 1495 } 1496 } 1497 1498 if ((media & IFM_GMASK) == IFM_FDX) { 1499 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_FULLDUPLEX); 1500 if (sc->dc_pmode == DC_PMODE_SYM && DC_IS_PNIC(sc)) 1501 DC_SETBIT(sc, DC_PN_NWAY, DC_PN_NWAY_DUPLEX); 1502 } else { 1503 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_FULLDUPLEX); 1504 if (sc->dc_pmode == DC_PMODE_SYM && DC_IS_PNIC(sc)) 1505 DC_CLRBIT(sc, DC_PN_NWAY, DC_PN_NWAY_DUPLEX); 1506 } 1507 1508 if (restart) 1509 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_TX_ON | DC_NETCFG_RX_ON); 1510 } 1511 1512 static void 1513 dc_reset(struct dc_softc *sc) 1514 { 1515 int i; 1516 1517 DC_SETBIT(sc, DC_BUSCTL, DC_BUSCTL_RESET); 1518 1519 for (i = 0; i < DC_TIMEOUT; i++) { 1520 DELAY(10); 1521 if (!(CSR_READ_4(sc, DC_BUSCTL) & DC_BUSCTL_RESET)) 1522 break; 1523 } 1524 1525 if (DC_IS_ASIX(sc) || DC_IS_ADMTEK(sc) || DC_IS_CONEXANT(sc) || 1526 DC_IS_XIRCOM(sc) || DC_IS_INTEL(sc) || DC_IS_ULI(sc)) { 1527 DELAY(10000); 1528 DC_CLRBIT(sc, DC_BUSCTL, DC_BUSCTL_RESET); 1529 i = 0; 1530 } 1531 1532 if (i == DC_TIMEOUT) 1533 device_printf(sc->dc_dev, "reset never completed!\n"); 1534 1535 /* Wait a little while for the chip to get its brains in order. */ 1536 DELAY(1000); 1537 1538 CSR_WRITE_4(sc, DC_IMR, 0x00000000); 1539 CSR_WRITE_4(sc, DC_BUSCTL, 0x00000000); 1540 CSR_WRITE_4(sc, DC_NETCFG, 0x00000000); 1541 1542 /* 1543 * Bring the SIA out of reset. In some cases, it looks 1544 * like failing to unreset the SIA soon enough gets it 1545 * into a state where it will never come out of reset 1546 * until we reset the whole chip again. 1547 */ 1548 if (DC_IS_INTEL(sc)) { 1549 DC_SETBIT(sc, DC_SIARESET, DC_SIA_RESET); 1550 CSR_WRITE_4(sc, DC_10BTCTRL, 0xFFFFFFFF); 1551 CSR_WRITE_4(sc, DC_WATCHDOG, 0); 1552 } 1553 } 1554 1555 static const struct dc_type * 1556 dc_devtype(device_t dev) 1557 { 1558 const struct dc_type *t; 1559 uint32_t devid; 1560 uint8_t rev; 1561 1562 t = dc_devs; 1563 devid = pci_get_devid(dev); 1564 rev = pci_get_revid(dev); 1565 1566 while (t->dc_name != NULL) { 1567 if (devid == t->dc_devid && rev >= t->dc_minrev) 1568 return (t); 1569 t++; 1570 } 1571 1572 return (NULL); 1573 } 1574 1575 /* 1576 * Probe for a 21143 or clone chip. Check the PCI vendor and device 1577 * IDs against our list and return a device name if we find a match. 1578 * We do a little bit of extra work to identify the exact type of 1579 * chip. The MX98713 and MX98713A have the same PCI vendor/device ID, 1580 * but different revision IDs. The same is true for 98715/98715A 1581 * chips and the 98725, as well as the ASIX and ADMtek chips. In some 1582 * cases, the exact chip revision affects driver behavior. 1583 */ 1584 static int 1585 dc_probe(device_t dev) 1586 { 1587 const struct dc_type *t; 1588 1589 t = dc_devtype(dev); 1590 1591 if (t != NULL) { 1592 device_set_desc(dev, t->dc_name); 1593 return (BUS_PROBE_DEFAULT); 1594 } 1595 1596 return (ENXIO); 1597 } 1598 1599 static void 1600 dc_apply_fixup(struct dc_softc *sc, int media) 1601 { 1602 struct dc_mediainfo *m; 1603 uint8_t *p; 1604 int i; 1605 uint32_t reg; 1606 1607 m = sc->dc_mi; 1608 1609 while (m != NULL) { 1610 if (m->dc_media == media) 1611 break; 1612 m = m->dc_next; 1613 } 1614 1615 if (m == NULL) 1616 return; 1617 1618 for (i = 0, p = m->dc_reset_ptr; i < m->dc_reset_len; i++, p += 2) { 1619 reg = (p[0] | (p[1] << 8)) << 16; 1620 CSR_WRITE_4(sc, DC_WATCHDOG, reg); 1621 } 1622 1623 for (i = 0, p = m->dc_gp_ptr; i < m->dc_gp_len; i++, p += 2) { 1624 reg = (p[0] | (p[1] << 8)) << 16; 1625 CSR_WRITE_4(sc, DC_WATCHDOG, reg); 1626 } 1627 } 1628 1629 static int 1630 dc_decode_leaf_sia(struct dc_softc *sc, struct dc_eblock_sia *l) 1631 { 1632 struct dc_mediainfo *m; 1633 1634 m = malloc(sizeof(struct dc_mediainfo), M_DEVBUF, M_NOWAIT | M_ZERO); 1635 if (m == NULL) { 1636 device_printf(sc->dc_dev, "Could not allocate mediainfo\n"); 1637 return (ENOMEM); 1638 } 1639 switch (l->dc_sia_code & ~DC_SIA_CODE_EXT) { 1640 case DC_SIA_CODE_10BT: 1641 m->dc_media = IFM_10_T; 1642 break; 1643 case DC_SIA_CODE_10BT_FDX: 1644 m->dc_media = IFM_10_T | IFM_FDX; 1645 break; 1646 case DC_SIA_CODE_10B2: 1647 m->dc_media = IFM_10_2; 1648 break; 1649 case DC_SIA_CODE_10B5: 1650 m->dc_media = IFM_10_5; 1651 break; 1652 default: 1653 break; 1654 } 1655 1656 /* 1657 * We need to ignore CSR13, CSR14, CSR15 for SIA mode. 1658 * Things apparently already work for cards that do 1659 * supply Media Specific Data. 1660 */ 1661 if (l->dc_sia_code & DC_SIA_CODE_EXT) { 1662 m->dc_gp_len = 2; 1663 m->dc_gp_ptr = 1664 (uint8_t *)&l->dc_un.dc_sia_ext.dc_sia_gpio_ctl; 1665 } else { 1666 m->dc_gp_len = 2; 1667 m->dc_gp_ptr = 1668 (uint8_t *)&l->dc_un.dc_sia_noext.dc_sia_gpio_ctl; 1669 } 1670 1671 m->dc_next = sc->dc_mi; 1672 sc->dc_mi = m; 1673 1674 sc->dc_pmode = DC_PMODE_SIA; 1675 return (0); 1676 } 1677 1678 static int 1679 dc_decode_leaf_sym(struct dc_softc *sc, struct dc_eblock_sym *l) 1680 { 1681 struct dc_mediainfo *m; 1682 1683 m = malloc(sizeof(struct dc_mediainfo), M_DEVBUF, M_NOWAIT | M_ZERO); 1684 if (m == NULL) { 1685 device_printf(sc->dc_dev, "Could not allocate mediainfo\n"); 1686 return (ENOMEM); 1687 } 1688 if (l->dc_sym_code == DC_SYM_CODE_100BT) 1689 m->dc_media = IFM_100_TX; 1690 1691 if (l->dc_sym_code == DC_SYM_CODE_100BT_FDX) 1692 m->dc_media = IFM_100_TX | IFM_FDX; 1693 1694 m->dc_gp_len = 2; 1695 m->dc_gp_ptr = (uint8_t *)&l->dc_sym_gpio_ctl; 1696 1697 m->dc_next = sc->dc_mi; 1698 sc->dc_mi = m; 1699 1700 sc->dc_pmode = DC_PMODE_SYM; 1701 return (0); 1702 } 1703 1704 static int 1705 dc_decode_leaf_mii(struct dc_softc *sc, struct dc_eblock_mii *l) 1706 { 1707 struct dc_mediainfo *m; 1708 uint8_t *p; 1709 1710 m = malloc(sizeof(struct dc_mediainfo), M_DEVBUF, M_NOWAIT | M_ZERO); 1711 if (m == NULL) { 1712 device_printf(sc->dc_dev, "Could not allocate mediainfo\n"); 1713 return (ENOMEM); 1714 } 1715 /* We abuse IFM_AUTO to represent MII. */ 1716 m->dc_media = IFM_AUTO; 1717 m->dc_gp_len = l->dc_gpr_len; 1718 1719 p = (uint8_t *)l; 1720 p += sizeof(struct dc_eblock_mii); 1721 m->dc_gp_ptr = p; 1722 p += 2 * l->dc_gpr_len; 1723 m->dc_reset_len = *p; 1724 p++; 1725 m->dc_reset_ptr = p; 1726 1727 m->dc_next = sc->dc_mi; 1728 sc->dc_mi = m; 1729 return (0); 1730 } 1731 1732 static int 1733 dc_read_srom(struct dc_softc *sc, int bits) 1734 { 1735 int size; 1736 1737 size = DC_ROM_SIZE(bits); 1738 sc->dc_srom = malloc(size, M_DEVBUF, M_NOWAIT | M_ZERO); 1739 if (sc->dc_srom == NULL) { 1740 device_printf(sc->dc_dev, "Could not allocate SROM buffer\n"); 1741 return (ENOMEM); 1742 } 1743 dc_read_eeprom(sc, (caddr_t)sc->dc_srom, 0, (size / 2), 0); 1744 return (0); 1745 } 1746 1747 static int 1748 dc_parse_21143_srom(struct dc_softc *sc) 1749 { 1750 struct dc_leaf_hdr *lhdr; 1751 struct dc_eblock_hdr *hdr; 1752 int error, have_mii, i, loff; 1753 char *ptr; 1754 1755 have_mii = 0; 1756 loff = sc->dc_srom[27]; 1757 lhdr = (struct dc_leaf_hdr *)&(sc->dc_srom[loff]); 1758 1759 ptr = (char *)lhdr; 1760 ptr += sizeof(struct dc_leaf_hdr) - 1; 1761 /* 1762 * Look if we got a MII media block. 1763 */ 1764 for (i = 0; i < lhdr->dc_mcnt; i++) { 1765 hdr = (struct dc_eblock_hdr *)ptr; 1766 if (hdr->dc_type == DC_EBLOCK_MII) 1767 have_mii++; 1768 1769 ptr += (hdr->dc_len & 0x7F); 1770 ptr++; 1771 } 1772 1773 /* 1774 * Do the same thing again. Only use SIA and SYM media 1775 * blocks if no MII media block is available. 1776 */ 1777 ptr = (char *)lhdr; 1778 ptr += sizeof(struct dc_leaf_hdr) - 1; 1779 error = 0; 1780 for (i = 0; i < lhdr->dc_mcnt; i++) { 1781 hdr = (struct dc_eblock_hdr *)ptr; 1782 switch (hdr->dc_type) { 1783 case DC_EBLOCK_MII: 1784 error = dc_decode_leaf_mii(sc, (struct dc_eblock_mii *)hdr); 1785 break; 1786 case DC_EBLOCK_SIA: 1787 if (! have_mii) 1788 error = dc_decode_leaf_sia(sc, 1789 (struct dc_eblock_sia *)hdr); 1790 break; 1791 case DC_EBLOCK_SYM: 1792 if (! have_mii) 1793 error = dc_decode_leaf_sym(sc, 1794 (struct dc_eblock_sym *)hdr); 1795 break; 1796 default: 1797 /* Don't care. Yet. */ 1798 break; 1799 } 1800 ptr += (hdr->dc_len & 0x7F); 1801 ptr++; 1802 } 1803 return (error); 1804 } 1805 1806 static void 1807 dc_dma_map_addr(void *arg, bus_dma_segment_t *segs, int nseg, int error) 1808 { 1809 bus_addr_t *paddr; 1810 1811 KASSERT(nseg == 1, 1812 ("%s: wrong number of segments (%d)", __func__, nseg)); 1813 paddr = arg; 1814 *paddr = segs->ds_addr; 1815 } 1816 1817 static int 1818 dc_dma_alloc(struct dc_softc *sc) 1819 { 1820 int error, i; 1821 1822 error = bus_dma_tag_create(bus_get_dma_tag(sc->dc_dev), 1, 0, 1823 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL, 1824 BUS_SPACE_MAXSIZE_32BIT, 0, BUS_SPACE_MAXSIZE_32BIT, 0, 1825 NULL, NULL, &sc->dc_ptag); 1826 if (error) { 1827 device_printf(sc->dc_dev, 1828 "failed to allocate parent DMA tag\n"); 1829 goto fail; 1830 } 1831 1832 /* Allocate a busdma tag and DMA safe memory for TX/RX descriptors. */ 1833 error = bus_dma_tag_create(sc->dc_ptag, DC_LIST_ALIGN, 0, 1834 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL, DC_RX_LIST_SZ, 1, 1835 DC_RX_LIST_SZ, 0, NULL, NULL, &sc->dc_rx_ltag); 1836 if (error) { 1837 device_printf(sc->dc_dev, "failed to create RX list DMA tag\n"); 1838 goto fail; 1839 } 1840 1841 error = bus_dma_tag_create(sc->dc_ptag, DC_LIST_ALIGN, 0, 1842 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL, DC_TX_LIST_SZ, 1, 1843 DC_TX_LIST_SZ, 0, NULL, NULL, &sc->dc_tx_ltag); 1844 if (error) { 1845 device_printf(sc->dc_dev, "failed to create TX list DMA tag\n"); 1846 goto fail; 1847 } 1848 1849 /* RX descriptor list. */ 1850 error = bus_dmamem_alloc(sc->dc_rx_ltag, 1851 (void **)&sc->dc_ldata.dc_rx_list, BUS_DMA_NOWAIT | 1852 BUS_DMA_ZERO | BUS_DMA_COHERENT, &sc->dc_rx_lmap); 1853 if (error) { 1854 device_printf(sc->dc_dev, 1855 "failed to allocate DMA'able memory for RX list\n"); 1856 goto fail; 1857 } 1858 error = bus_dmamap_load(sc->dc_rx_ltag, sc->dc_rx_lmap, 1859 sc->dc_ldata.dc_rx_list, DC_RX_LIST_SZ, dc_dma_map_addr, 1860 &sc->dc_ldata.dc_rx_list_paddr, BUS_DMA_NOWAIT); 1861 if (error) { 1862 device_printf(sc->dc_dev, 1863 "failed to load DMA'able memory for RX list\n"); 1864 goto fail; 1865 } 1866 /* TX descriptor list. */ 1867 error = bus_dmamem_alloc(sc->dc_tx_ltag, 1868 (void **)&sc->dc_ldata.dc_tx_list, BUS_DMA_NOWAIT | 1869 BUS_DMA_ZERO | BUS_DMA_COHERENT, &sc->dc_tx_lmap); 1870 if (error) { 1871 device_printf(sc->dc_dev, 1872 "failed to allocate DMA'able memory for TX list\n"); 1873 goto fail; 1874 } 1875 error = bus_dmamap_load(sc->dc_tx_ltag, sc->dc_tx_lmap, 1876 sc->dc_ldata.dc_tx_list, DC_TX_LIST_SZ, dc_dma_map_addr, 1877 &sc->dc_ldata.dc_tx_list_paddr, BUS_DMA_NOWAIT); 1878 if (error) { 1879 device_printf(sc->dc_dev, 1880 "cannot load DMA'able memory for TX list\n"); 1881 goto fail; 1882 } 1883 1884 /* 1885 * Allocate a busdma tag and DMA safe memory for the multicast 1886 * setup frame. 1887 */ 1888 error = bus_dma_tag_create(sc->dc_ptag, DC_LIST_ALIGN, 0, 1889 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL, 1890 DC_SFRAME_LEN + DC_MIN_FRAMELEN, 1, DC_SFRAME_LEN + DC_MIN_FRAMELEN, 1891 0, NULL, NULL, &sc->dc_stag); 1892 if (error) { 1893 device_printf(sc->dc_dev, 1894 "failed to create DMA tag for setup frame\n"); 1895 goto fail; 1896 } 1897 error = bus_dmamem_alloc(sc->dc_stag, (void **)&sc->dc_cdata.dc_sbuf, 1898 BUS_DMA_NOWAIT, &sc->dc_smap); 1899 if (error) { 1900 device_printf(sc->dc_dev, 1901 "failed to allocate DMA'able memory for setup frame\n"); 1902 goto fail; 1903 } 1904 error = bus_dmamap_load(sc->dc_stag, sc->dc_smap, sc->dc_cdata.dc_sbuf, 1905 DC_SFRAME_LEN, dc_dma_map_addr, &sc->dc_saddr, BUS_DMA_NOWAIT); 1906 if (error) { 1907 device_printf(sc->dc_dev, 1908 "cannot load DMA'able memory for setup frame\n"); 1909 goto fail; 1910 } 1911 1912 /* Allocate a busdma tag for RX mbufs. */ 1913 error = bus_dma_tag_create(sc->dc_ptag, DC_RXBUF_ALIGN, 0, 1914 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL, 1915 MCLBYTES, 1, MCLBYTES, 0, NULL, NULL, &sc->dc_rx_mtag); 1916 if (error) { 1917 device_printf(sc->dc_dev, "failed to create RX mbuf tag\n"); 1918 goto fail; 1919 } 1920 1921 /* Allocate a busdma tag for TX mbufs. */ 1922 error = bus_dma_tag_create(sc->dc_ptag, 1, 0, 1923 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL, 1924 MCLBYTES * DC_MAXFRAGS, DC_MAXFRAGS, MCLBYTES, 1925 0, NULL, NULL, &sc->dc_tx_mtag); 1926 if (error) { 1927 device_printf(sc->dc_dev, "failed to create TX mbuf tag\n"); 1928 goto fail; 1929 } 1930 1931 /* Create the TX/RX busdma maps. */ 1932 for (i = 0; i < DC_TX_LIST_CNT; i++) { 1933 error = bus_dmamap_create(sc->dc_tx_mtag, 0, 1934 &sc->dc_cdata.dc_tx_map[i]); 1935 if (error) { 1936 device_printf(sc->dc_dev, 1937 "failed to create TX mbuf dmamap\n"); 1938 goto fail; 1939 } 1940 } 1941 for (i = 0; i < DC_RX_LIST_CNT; i++) { 1942 error = bus_dmamap_create(sc->dc_rx_mtag, 0, 1943 &sc->dc_cdata.dc_rx_map[i]); 1944 if (error) { 1945 device_printf(sc->dc_dev, 1946 "failed to create RX mbuf dmamap\n"); 1947 goto fail; 1948 } 1949 } 1950 error = bus_dmamap_create(sc->dc_rx_mtag, 0, &sc->dc_sparemap); 1951 if (error) { 1952 device_printf(sc->dc_dev, 1953 "failed to create spare RX mbuf dmamap\n"); 1954 goto fail; 1955 } 1956 1957 fail: 1958 return (error); 1959 } 1960 1961 static void 1962 dc_dma_free(struct dc_softc *sc) 1963 { 1964 int i; 1965 1966 /* RX buffers. */ 1967 if (sc->dc_rx_mtag != NULL) { 1968 for (i = 0; i < DC_RX_LIST_CNT; i++) { 1969 if (sc->dc_cdata.dc_rx_map[i] != NULL) 1970 bus_dmamap_destroy(sc->dc_rx_mtag, 1971 sc->dc_cdata.dc_rx_map[i]); 1972 } 1973 if (sc->dc_sparemap != NULL) 1974 bus_dmamap_destroy(sc->dc_rx_mtag, sc->dc_sparemap); 1975 bus_dma_tag_destroy(sc->dc_rx_mtag); 1976 } 1977 1978 /* TX buffers. */ 1979 if (sc->dc_rx_mtag != NULL) { 1980 for (i = 0; i < DC_TX_LIST_CNT; i++) { 1981 if (sc->dc_cdata.dc_tx_map[i] != NULL) 1982 bus_dmamap_destroy(sc->dc_tx_mtag, 1983 sc->dc_cdata.dc_tx_map[i]); 1984 } 1985 bus_dma_tag_destroy(sc->dc_tx_mtag); 1986 } 1987 1988 /* RX descriptor list. */ 1989 if (sc->dc_rx_ltag) { 1990 if (sc->dc_ldata.dc_rx_list_paddr != 0) 1991 bus_dmamap_unload(sc->dc_rx_ltag, sc->dc_rx_lmap); 1992 if (sc->dc_ldata.dc_rx_list != NULL) 1993 bus_dmamem_free(sc->dc_rx_ltag, sc->dc_ldata.dc_rx_list, 1994 sc->dc_rx_lmap); 1995 bus_dma_tag_destroy(sc->dc_rx_ltag); 1996 } 1997 1998 /* TX descriptor list. */ 1999 if (sc->dc_tx_ltag) { 2000 if (sc->dc_ldata.dc_tx_list_paddr != 0) 2001 bus_dmamap_unload(sc->dc_tx_ltag, sc->dc_tx_lmap); 2002 if (sc->dc_ldata.dc_tx_list != NULL) 2003 bus_dmamem_free(sc->dc_tx_ltag, sc->dc_ldata.dc_tx_list, 2004 sc->dc_tx_lmap); 2005 bus_dma_tag_destroy(sc->dc_tx_ltag); 2006 } 2007 2008 /* multicast setup frame. */ 2009 if (sc->dc_stag) { 2010 if (sc->dc_saddr != 0) 2011 bus_dmamap_unload(sc->dc_stag, sc->dc_smap); 2012 if (sc->dc_cdata.dc_sbuf != NULL) 2013 bus_dmamem_free(sc->dc_stag, sc->dc_cdata.dc_sbuf, 2014 sc->dc_smap); 2015 bus_dma_tag_destroy(sc->dc_stag); 2016 } 2017 } 2018 2019 /* 2020 * Attach the interface. Allocate softc structures, do ifmedia 2021 * setup and ethernet/BPF attach. 2022 */ 2023 static int 2024 dc_attach(device_t dev) 2025 { 2026 uint32_t eaddr[(ETHER_ADDR_LEN+3)/4]; 2027 uint32_t command; 2028 struct dc_softc *sc; 2029 if_t ifp; 2030 struct dc_mediainfo *m; 2031 uint32_t reg, revision; 2032 uint16_t *srom; 2033 int error, mac_offset, n, phy, rid, tmp; 2034 uint8_t *mac; 2035 2036 sc = device_get_softc(dev); 2037 sc->dc_dev = dev; 2038 2039 mtx_init(&sc->dc_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 2040 MTX_DEF); 2041 2042 /* 2043 * Map control/status registers. 2044 */ 2045 pci_enable_busmaster(dev); 2046 2047 rid = DC_RID; 2048 sc->dc_res = bus_alloc_resource_any(dev, DC_RES, &rid, RF_ACTIVE); 2049 2050 if (sc->dc_res == NULL) { 2051 device_printf(dev, "couldn't map ports/memory\n"); 2052 error = ENXIO; 2053 goto fail; 2054 } 2055 2056 sc->dc_btag = rman_get_bustag(sc->dc_res); 2057 sc->dc_bhandle = rman_get_bushandle(sc->dc_res); 2058 2059 /* Allocate interrupt. */ 2060 rid = 0; 2061 sc->dc_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 2062 RF_SHAREABLE | RF_ACTIVE); 2063 2064 if (sc->dc_irq == NULL) { 2065 device_printf(dev, "couldn't map interrupt\n"); 2066 error = ENXIO; 2067 goto fail; 2068 } 2069 2070 /* Need this info to decide on a chip type. */ 2071 sc->dc_info = dc_devtype(dev); 2072 revision = pci_get_revid(dev); 2073 2074 error = 0; 2075 /* Get the eeprom width, but PNIC and XIRCOM have diff eeprom */ 2076 if (sc->dc_info->dc_devid != 2077 DC_DEVID(DC_VENDORID_LO, DC_DEVICEID_82C168) && 2078 sc->dc_info->dc_devid != 2079 DC_DEVID(DC_VENDORID_XIRCOM, DC_DEVICEID_X3201)) 2080 dc_eeprom_width(sc); 2081 2082 switch (sc->dc_info->dc_devid) { 2083 case DC_DEVID(DC_VENDORID_DEC, DC_DEVICEID_21143): 2084 sc->dc_type = DC_TYPE_21143; 2085 sc->dc_flags |= DC_TX_POLL | DC_TX_USE_TX_INTR; 2086 sc->dc_flags |= DC_REDUCED_MII_POLL; 2087 /* Save EEPROM contents so we can parse them later. */ 2088 error = dc_read_srom(sc, sc->dc_romwidth); 2089 if (error != 0) 2090 goto fail; 2091 break; 2092 case DC_DEVID(DC_VENDORID_DAVICOM, DC_DEVICEID_DM9009): 2093 case DC_DEVID(DC_VENDORID_DAVICOM, DC_DEVICEID_DM9100): 2094 case DC_DEVID(DC_VENDORID_DAVICOM, DC_DEVICEID_DM9102): 2095 sc->dc_type = DC_TYPE_DM9102; 2096 sc->dc_flags |= DC_TX_COALESCE | DC_TX_INTR_ALWAYS; 2097 sc->dc_flags |= DC_REDUCED_MII_POLL | DC_TX_STORENFWD; 2098 sc->dc_flags |= DC_TX_ALIGN; 2099 sc->dc_pmode = DC_PMODE_MII; 2100 2101 /* Increase the latency timer value. */ 2102 pci_write_config(dev, PCIR_LATTIMER, 0x80, 1); 2103 break; 2104 case DC_DEVID(DC_VENDORID_ADMTEK, DC_DEVICEID_AL981): 2105 sc->dc_type = DC_TYPE_AL981; 2106 sc->dc_flags |= DC_TX_USE_TX_INTR; 2107 sc->dc_flags |= DC_TX_ADMTEK_WAR; 2108 sc->dc_pmode = DC_PMODE_MII; 2109 error = dc_read_srom(sc, sc->dc_romwidth); 2110 if (error != 0) 2111 goto fail; 2112 break; 2113 case DC_DEVID(DC_VENDORID_ADMTEK, DC_DEVICEID_AN983): 2114 case DC_DEVID(DC_VENDORID_ADMTEK, DC_DEVICEID_AN985): 2115 case DC_DEVID(DC_VENDORID_ADMTEK, DC_DEVICEID_ADM9511): 2116 case DC_DEVID(DC_VENDORID_ADMTEK, DC_DEVICEID_ADM9513): 2117 case DC_DEVID(DC_VENDORID_DLINK, DC_DEVICEID_DRP32TXD): 2118 case DC_DEVID(DC_VENDORID_ABOCOM, DC_DEVICEID_FE2500): 2119 case DC_DEVID(DC_VENDORID_ABOCOM, DC_DEVICEID_FE2500MX): 2120 case DC_DEVID(DC_VENDORID_ACCTON, DC_DEVICEID_EN2242): 2121 case DC_DEVID(DC_VENDORID_HAWKING, DC_DEVICEID_HAWKING_PN672TX): 2122 case DC_DEVID(DC_VENDORID_PLANEX, DC_DEVICEID_FNW3602T): 2123 case DC_DEVID(DC_VENDORID_3COM, DC_DEVICEID_3CSOHOB): 2124 case DC_DEVID(DC_VENDORID_MICROSOFT, DC_DEVICEID_MSMN120): 2125 case DC_DEVID(DC_VENDORID_MICROSOFT, DC_DEVICEID_MSMN130): 2126 case DC_DEVID(DC_VENDORID_LINKSYS, DC_DEVICEID_PCMPC200_AB08): 2127 case DC_DEVID(DC_VENDORID_LINKSYS, DC_DEVICEID_PCMPC200_AB09): 2128 sc->dc_type = DC_TYPE_AN983; 2129 sc->dc_flags |= DC_64BIT_HASH; 2130 sc->dc_flags |= DC_TX_USE_TX_INTR; 2131 sc->dc_flags |= DC_TX_ADMTEK_WAR; 2132 sc->dc_pmode = DC_PMODE_MII; 2133 /* Don't read SROM for - auto-loaded on reset */ 2134 break; 2135 case DC_DEVID(DC_VENDORID_MX, DC_DEVICEID_98713): 2136 case DC_DEVID(DC_VENDORID_CP, DC_DEVICEID_98713_CP): 2137 if (revision < DC_REVISION_98713A) { 2138 sc->dc_type = DC_TYPE_98713; 2139 } 2140 if (revision >= DC_REVISION_98713A) { 2141 sc->dc_type = DC_TYPE_98713A; 2142 sc->dc_flags |= DC_21143_NWAY; 2143 } 2144 sc->dc_flags |= DC_REDUCED_MII_POLL; 2145 sc->dc_flags |= DC_TX_POLL | DC_TX_USE_TX_INTR; 2146 break; 2147 case DC_DEVID(DC_VENDORID_MX, DC_DEVICEID_987x5): 2148 case DC_DEVID(DC_VENDORID_ACCTON, DC_DEVICEID_EN1217): 2149 /* 2150 * Macronix MX98715AEC-C/D/E parts have only a 2151 * 128-bit hash table. We need to deal with these 2152 * in the same manner as the PNIC II so that we 2153 * get the right number of bits out of the 2154 * CRC routine. 2155 */ 2156 if (revision >= DC_REVISION_98715AEC_C && 2157 revision < DC_REVISION_98725) 2158 sc->dc_flags |= DC_128BIT_HASH; 2159 sc->dc_type = DC_TYPE_987x5; 2160 sc->dc_flags |= DC_TX_POLL | DC_TX_USE_TX_INTR; 2161 sc->dc_flags |= DC_REDUCED_MII_POLL | DC_21143_NWAY; 2162 break; 2163 case DC_DEVID(DC_VENDORID_MX, DC_DEVICEID_98727): 2164 sc->dc_type = DC_TYPE_987x5; 2165 sc->dc_flags |= DC_TX_POLL | DC_TX_USE_TX_INTR; 2166 sc->dc_flags |= DC_REDUCED_MII_POLL | DC_21143_NWAY; 2167 break; 2168 case DC_DEVID(DC_VENDORID_LO, DC_DEVICEID_82C115): 2169 sc->dc_type = DC_TYPE_PNICII; 2170 sc->dc_flags |= DC_TX_POLL | DC_TX_USE_TX_INTR | DC_128BIT_HASH; 2171 sc->dc_flags |= DC_REDUCED_MII_POLL | DC_21143_NWAY; 2172 break; 2173 case DC_DEVID(DC_VENDORID_LO, DC_DEVICEID_82C168): 2174 sc->dc_type = DC_TYPE_PNIC; 2175 sc->dc_flags |= DC_TX_STORENFWD | DC_TX_INTR_ALWAYS; 2176 sc->dc_flags |= DC_PNIC_RX_BUG_WAR; 2177 sc->dc_pnic_rx_buf = malloc(DC_RXLEN * 5, M_DEVBUF, M_NOWAIT); 2178 if (sc->dc_pnic_rx_buf == NULL) { 2179 device_printf(sc->dc_dev, 2180 "Could not allocate PNIC RX buffer\n"); 2181 error = ENOMEM; 2182 goto fail; 2183 } 2184 if (revision < DC_REVISION_82C169) 2185 sc->dc_pmode = DC_PMODE_SYM; 2186 break; 2187 case DC_DEVID(DC_VENDORID_ASIX, DC_DEVICEID_AX88140A): 2188 sc->dc_type = DC_TYPE_ASIX; 2189 sc->dc_flags |= DC_TX_USE_TX_INTR | DC_TX_INTR_FIRSTFRAG; 2190 sc->dc_flags |= DC_REDUCED_MII_POLL; 2191 sc->dc_pmode = DC_PMODE_MII; 2192 break; 2193 case DC_DEVID(DC_VENDORID_XIRCOM, DC_DEVICEID_X3201): 2194 sc->dc_type = DC_TYPE_XIRCOM; 2195 sc->dc_flags |= DC_TX_INTR_ALWAYS | DC_TX_COALESCE | 2196 DC_TX_ALIGN; 2197 /* 2198 * We don't actually need to coalesce, but we're doing 2199 * it to obtain a double word aligned buffer. 2200 * The DC_TX_COALESCE flag is required. 2201 */ 2202 sc->dc_pmode = DC_PMODE_MII; 2203 break; 2204 case DC_DEVID(DC_VENDORID_CONEXANT, DC_DEVICEID_RS7112): 2205 sc->dc_type = DC_TYPE_CONEXANT; 2206 sc->dc_flags |= DC_TX_INTR_ALWAYS; 2207 sc->dc_flags |= DC_REDUCED_MII_POLL; 2208 sc->dc_pmode = DC_PMODE_MII; 2209 error = dc_read_srom(sc, sc->dc_romwidth); 2210 if (error != 0) 2211 goto fail; 2212 break; 2213 case DC_DEVID(DC_VENDORID_ULI, DC_DEVICEID_M5261): 2214 case DC_DEVID(DC_VENDORID_ULI, DC_DEVICEID_M5263): 2215 if (sc->dc_info->dc_devid == 2216 DC_DEVID(DC_VENDORID_ULI, DC_DEVICEID_M5261)) 2217 sc->dc_type = DC_TYPE_ULI_M5261; 2218 else 2219 sc->dc_type = DC_TYPE_ULI_M5263; 2220 /* TX buffers should be aligned on 4 byte boundary. */ 2221 sc->dc_flags |= DC_TX_INTR_ALWAYS | DC_TX_COALESCE | 2222 DC_TX_ALIGN; 2223 sc->dc_pmode = DC_PMODE_MII; 2224 error = dc_read_srom(sc, sc->dc_romwidth); 2225 if (error != 0) 2226 goto fail; 2227 break; 2228 default: 2229 device_printf(dev, "unknown device: %x\n", 2230 sc->dc_info->dc_devid); 2231 break; 2232 } 2233 2234 /* Save the cache line size. */ 2235 if (DC_IS_DAVICOM(sc)) 2236 sc->dc_cachesize = 0; 2237 else 2238 sc->dc_cachesize = pci_get_cachelnsz(dev); 2239 2240 /* Reset the adapter. */ 2241 dc_reset(sc); 2242 2243 /* Take 21143 out of snooze mode */ 2244 if (DC_IS_INTEL(sc) || DC_IS_XIRCOM(sc)) { 2245 command = pci_read_config(dev, DC_PCI_CFDD, 4); 2246 command &= ~(DC_CFDD_SNOOZE_MODE | DC_CFDD_SLEEP_MODE); 2247 pci_write_config(dev, DC_PCI_CFDD, command, 4); 2248 } 2249 2250 /* 2251 * Try to learn something about the supported media. 2252 * We know that ASIX and ADMtek and Davicom devices 2253 * will *always* be using MII media, so that's a no-brainer. 2254 * The tricky ones are the Macronix/PNIC II and the 2255 * Intel 21143. 2256 */ 2257 if (DC_IS_INTEL(sc)) { 2258 error = dc_parse_21143_srom(sc); 2259 if (error != 0) 2260 goto fail; 2261 } else if (DC_IS_MACRONIX(sc) || DC_IS_PNICII(sc)) { 2262 if (sc->dc_type == DC_TYPE_98713) 2263 sc->dc_pmode = DC_PMODE_MII; 2264 else 2265 sc->dc_pmode = DC_PMODE_SYM; 2266 } else if (!sc->dc_pmode) 2267 sc->dc_pmode = DC_PMODE_MII; 2268 2269 /* 2270 * Get station address from the EEPROM. 2271 */ 2272 switch(sc->dc_type) { 2273 case DC_TYPE_98713: 2274 case DC_TYPE_98713A: 2275 case DC_TYPE_987x5: 2276 case DC_TYPE_PNICII: 2277 dc_read_eeprom(sc, (caddr_t)&mac_offset, 2278 (DC_EE_NODEADDR_OFFSET / 2), 1, 0); 2279 dc_read_eeprom(sc, (caddr_t)&eaddr, (mac_offset / 2), 3, 0); 2280 break; 2281 case DC_TYPE_PNIC: 2282 dc_read_eeprom(sc, (caddr_t)&eaddr, 0, 3, 1); 2283 break; 2284 case DC_TYPE_DM9102: 2285 dc_read_eeprom(sc, (caddr_t)&eaddr, DC_EE_NODEADDR, 3, 0); 2286 break; 2287 case DC_TYPE_21143: 2288 case DC_TYPE_ASIX: 2289 dc_read_eeprom(sc, (caddr_t)&eaddr, DC_EE_NODEADDR, 3, 0); 2290 break; 2291 case DC_TYPE_AL981: 2292 case DC_TYPE_AN983: 2293 reg = CSR_READ_4(sc, DC_AL_PAR0); 2294 mac = (uint8_t *)&eaddr[0]; 2295 mac[0] = (reg >> 0) & 0xff; 2296 mac[1] = (reg >> 8) & 0xff; 2297 mac[2] = (reg >> 16) & 0xff; 2298 mac[3] = (reg >> 24) & 0xff; 2299 reg = CSR_READ_4(sc, DC_AL_PAR1); 2300 mac[4] = (reg >> 0) & 0xff; 2301 mac[5] = (reg >> 8) & 0xff; 2302 break; 2303 case DC_TYPE_CONEXANT: 2304 bcopy(sc->dc_srom + DC_CONEXANT_EE_NODEADDR, &eaddr, 2305 ETHER_ADDR_LEN); 2306 break; 2307 case DC_TYPE_XIRCOM: 2308 /* The MAC comes from the CIS. */ 2309 mac = pci_get_ether(dev); 2310 if (!mac) { 2311 device_printf(dev, "No station address in CIS!\n"); 2312 error = ENXIO; 2313 goto fail; 2314 } 2315 bcopy(mac, eaddr, ETHER_ADDR_LEN); 2316 break; 2317 case DC_TYPE_ULI_M5261: 2318 case DC_TYPE_ULI_M5263: 2319 srom = (uint16_t *)sc->dc_srom; 2320 if (srom == NULL || *srom == 0xFFFF || *srom == 0) { 2321 /* 2322 * No valid SROM present, read station address 2323 * from ID Table. 2324 */ 2325 device_printf(dev, 2326 "Reading station address from ID Table.\n"); 2327 CSR_WRITE_4(sc, DC_BUSCTL, 0x10000); 2328 CSR_WRITE_4(sc, DC_SIARESET, 0x01C0); 2329 CSR_WRITE_4(sc, DC_10BTCTRL, 0x0000); 2330 CSR_WRITE_4(sc, DC_10BTCTRL, 0x0010); 2331 CSR_WRITE_4(sc, DC_10BTCTRL, 0x0000); 2332 CSR_WRITE_4(sc, DC_SIARESET, 0x0000); 2333 CSR_WRITE_4(sc, DC_SIARESET, 0x01B0); 2334 mac = (uint8_t *)eaddr; 2335 for (n = 0; n < ETHER_ADDR_LEN; n++) 2336 mac[n] = (uint8_t)CSR_READ_4(sc, DC_10BTCTRL); 2337 CSR_WRITE_4(sc, DC_SIARESET, 0x0000); 2338 CSR_WRITE_4(sc, DC_BUSCTL, 0x0000); 2339 DELAY(10); 2340 } else 2341 dc_read_eeprom(sc, (caddr_t)&eaddr, DC_EE_NODEADDR, 3, 2342 0); 2343 break; 2344 default: 2345 dc_read_eeprom(sc, (caddr_t)&eaddr, DC_EE_NODEADDR, 3, 0); 2346 break; 2347 } 2348 2349 bcopy(eaddr, sc->dc_eaddr, sizeof(eaddr)); 2350 /* 2351 * If we still have invalid station address, see whether we can 2352 * find station address for chip 0. Some multi-port controllers 2353 * just store station address for chip 0 if they have a shared 2354 * SROM. 2355 */ 2356 if ((sc->dc_eaddr[0] == 0 && (sc->dc_eaddr[1] & ~0xffff) == 0) || 2357 (sc->dc_eaddr[0] == 0xffffffff && 2358 (sc->dc_eaddr[1] & 0xffff) == 0xffff)) { 2359 error = dc_check_multiport(sc); 2360 if (error == 0) { 2361 bcopy(sc->dc_eaddr, eaddr, sizeof(eaddr)); 2362 /* Extract media information. */ 2363 if (DC_IS_INTEL(sc) && sc->dc_srom != NULL) { 2364 while (sc->dc_mi != NULL) { 2365 m = sc->dc_mi->dc_next; 2366 free(sc->dc_mi, M_DEVBUF); 2367 sc->dc_mi = m; 2368 } 2369 error = dc_parse_21143_srom(sc); 2370 if (error != 0) 2371 goto fail; 2372 } 2373 } else if (error == ENOMEM) 2374 goto fail; 2375 else 2376 error = 0; 2377 } 2378 2379 if ((error = dc_dma_alloc(sc)) != 0) 2380 goto fail; 2381 2382 ifp = sc->dc_ifp = if_alloc(IFT_ETHER); 2383 if_setsoftc(ifp, sc); 2384 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 2385 if_setflags(ifp, IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST); 2386 if_setioctlfn(ifp, dc_ioctl); 2387 if_setstartfn(ifp, dc_start); 2388 if_setinitfn(ifp, dc_init); 2389 if_setsendqlen(ifp, DC_TX_LIST_CNT - 1); 2390 if_setsendqready(ifp); 2391 2392 /* 2393 * Do MII setup. If this is a 21143, check for a PHY on the 2394 * MII bus after applying any necessary fixups to twiddle the 2395 * GPIO bits. If we don't end up finding a PHY, restore the 2396 * old selection (SIA only or SIA/SYM) and attach the dcphy 2397 * driver instead. 2398 */ 2399 tmp = 0; 2400 if (DC_IS_INTEL(sc)) { 2401 dc_apply_fixup(sc, IFM_AUTO); 2402 tmp = sc->dc_pmode; 2403 sc->dc_pmode = DC_PMODE_MII; 2404 } 2405 2406 /* 2407 * Setup General Purpose port mode and data so the tulip can talk 2408 * to the MII. This needs to be done before mii_attach so that 2409 * we can actually see them. 2410 */ 2411 if (DC_IS_XIRCOM(sc)) { 2412 CSR_WRITE_4(sc, DC_SIAGP, DC_SIAGP_WRITE_EN | DC_SIAGP_INT1_EN | 2413 DC_SIAGP_MD_GP2_OUTPUT | DC_SIAGP_MD_GP0_OUTPUT); 2414 DELAY(10); 2415 CSR_WRITE_4(sc, DC_SIAGP, DC_SIAGP_INT1_EN | 2416 DC_SIAGP_MD_GP2_OUTPUT | DC_SIAGP_MD_GP0_OUTPUT); 2417 DELAY(10); 2418 } 2419 2420 phy = MII_PHY_ANY; 2421 /* 2422 * Note: both the AL981 and AN983 have internal PHYs, however the 2423 * AL981 provides direct access to the PHY registers while the AN983 2424 * uses a serial MII interface. The AN983's MII interface is also 2425 * buggy in that you can read from any MII address (0 to 31), but 2426 * only address 1 behaves normally. To deal with both cases, we 2427 * pretend that the PHY is at MII address 1. 2428 */ 2429 if (DC_IS_ADMTEK(sc)) 2430 phy = DC_ADMTEK_PHYADDR; 2431 2432 /* 2433 * Note: the ukphy probes of the RS7112 report a PHY at MII address 2434 * 0 (possibly HomePNA?) and 1 (ethernet) so we only respond to the 2435 * correct one. 2436 */ 2437 if (DC_IS_CONEXANT(sc)) 2438 phy = DC_CONEXANT_PHYADDR; 2439 2440 error = mii_attach(dev, &sc->dc_miibus, ifp, dc_ifmedia_upd, 2441 dc_ifmedia_sts, BMSR_DEFCAPMASK, phy, MII_OFFSET_ANY, 0); 2442 2443 if (error && DC_IS_INTEL(sc)) { 2444 sc->dc_pmode = tmp; 2445 if (sc->dc_pmode != DC_PMODE_SIA) 2446 sc->dc_pmode = DC_PMODE_SYM; 2447 sc->dc_flags |= DC_21143_NWAY; 2448 /* 2449 * For non-MII cards, we need to have the 21143 2450 * drive the LEDs. Except there are some systems 2451 * like the NEC VersaPro NoteBook PC which have no 2452 * LEDs, and twiddling these bits has adverse effects 2453 * on them. (I.e. you suddenly can't get a link.) 2454 */ 2455 if (!(pci_get_subvendor(dev) == 0x1033 && 2456 pci_get_subdevice(dev) == 0x8028)) 2457 sc->dc_flags |= DC_TULIP_LEDS; 2458 error = mii_attach(dev, &sc->dc_miibus, ifp, dc_ifmedia_upd, 2459 dc_ifmedia_sts, BMSR_DEFCAPMASK, MII_PHY_ANY, 2460 MII_OFFSET_ANY, 0); 2461 } 2462 2463 if (error) { 2464 device_printf(dev, "attaching PHYs failed\n"); 2465 goto fail; 2466 } 2467 2468 if (DC_IS_ADMTEK(sc)) { 2469 /* 2470 * Set automatic TX underrun recovery for the ADMtek chips 2471 */ 2472 DC_SETBIT(sc, DC_AL_CR, DC_AL_CR_ATUR); 2473 } 2474 2475 /* 2476 * Tell the upper layer(s) we support long frames. 2477 */ 2478 if_setifheaderlen(ifp, sizeof(struct ether_vlan_header)); 2479 if_setcapabilitiesbit(ifp, IFCAP_VLAN_MTU, 0); 2480 if_setcapenable(ifp, if_getcapabilities(ifp)); 2481 #ifdef DEVICE_POLLING 2482 if_setcapabilitiesbit(ifp, IFCAP_POLLING, 0); 2483 #endif 2484 2485 callout_init_mtx(&sc->dc_stat_ch, &sc->dc_mtx, 0); 2486 callout_init_mtx(&sc->dc_wdog_ch, &sc->dc_mtx, 0); 2487 2488 /* 2489 * Call MI attach routine. 2490 */ 2491 ether_ifattach(ifp, (caddr_t)eaddr); 2492 2493 /* Hook interrupt last to avoid having to lock softc */ 2494 error = bus_setup_intr(dev, sc->dc_irq, INTR_TYPE_NET | INTR_MPSAFE, 2495 NULL, dc_intr, sc, &sc->dc_intrhand); 2496 2497 if (error) { 2498 device_printf(dev, "couldn't set up irq\n"); 2499 ether_ifdetach(ifp); 2500 goto fail; 2501 } 2502 2503 fail: 2504 if (error) 2505 dc_detach(dev); 2506 return (error); 2507 } 2508 2509 /* 2510 * Shutdown hardware and free up resources. This can be called any 2511 * time after the mutex has been initialized. It is called in both 2512 * the error case in attach and the normal detach case so it needs 2513 * to be careful about only freeing resources that have actually been 2514 * allocated. 2515 */ 2516 static int 2517 dc_detach(device_t dev) 2518 { 2519 struct dc_softc *sc; 2520 if_t ifp; 2521 struct dc_mediainfo *m; 2522 2523 sc = device_get_softc(dev); 2524 KASSERT(mtx_initialized(&sc->dc_mtx), ("dc mutex not initialized")); 2525 2526 ifp = sc->dc_ifp; 2527 2528 #ifdef DEVICE_POLLING 2529 if (ifp != NULL && if_getcapenable(ifp) & IFCAP_POLLING) 2530 ether_poll_deregister(ifp); 2531 #endif 2532 2533 /* These should only be active if attach succeeded */ 2534 if (device_is_attached(dev)) { 2535 DC_LOCK(sc); 2536 dc_stop(sc); 2537 DC_UNLOCK(sc); 2538 callout_drain(&sc->dc_stat_ch); 2539 callout_drain(&sc->dc_wdog_ch); 2540 ether_ifdetach(ifp); 2541 } 2542 if (sc->dc_miibus) 2543 device_delete_child(dev, sc->dc_miibus); 2544 bus_generic_detach(dev); 2545 2546 if (sc->dc_intrhand) 2547 bus_teardown_intr(dev, sc->dc_irq, sc->dc_intrhand); 2548 if (sc->dc_irq) 2549 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->dc_irq); 2550 if (sc->dc_res) 2551 bus_release_resource(dev, DC_RES, DC_RID, sc->dc_res); 2552 2553 if (ifp != NULL) 2554 if_free(ifp); 2555 2556 dc_dma_free(sc); 2557 2558 free(sc->dc_pnic_rx_buf, M_DEVBUF); 2559 2560 while (sc->dc_mi != NULL) { 2561 m = sc->dc_mi->dc_next; 2562 free(sc->dc_mi, M_DEVBUF); 2563 sc->dc_mi = m; 2564 } 2565 free(sc->dc_srom, M_DEVBUF); 2566 2567 mtx_destroy(&sc->dc_mtx); 2568 2569 return (0); 2570 } 2571 2572 /* 2573 * Initialize the transmit descriptors. 2574 */ 2575 static int 2576 dc_list_tx_init(struct dc_softc *sc) 2577 { 2578 struct dc_chain_data *cd; 2579 struct dc_list_data *ld; 2580 int i, nexti; 2581 2582 cd = &sc->dc_cdata; 2583 ld = &sc->dc_ldata; 2584 for (i = 0; i < DC_TX_LIST_CNT; i++) { 2585 if (i == DC_TX_LIST_CNT - 1) 2586 nexti = 0; 2587 else 2588 nexti = i + 1; 2589 ld->dc_tx_list[i].dc_status = 0; 2590 ld->dc_tx_list[i].dc_ctl = 0; 2591 ld->dc_tx_list[i].dc_data = 0; 2592 ld->dc_tx_list[i].dc_next = htole32(DC_TXDESC(sc, nexti)); 2593 cd->dc_tx_chain[i] = NULL; 2594 } 2595 2596 cd->dc_tx_prod = cd->dc_tx_cons = cd->dc_tx_cnt = 0; 2597 cd->dc_tx_pkts = 0; 2598 bus_dmamap_sync(sc->dc_tx_ltag, sc->dc_tx_lmap, 2599 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2600 return (0); 2601 } 2602 2603 /* 2604 * Initialize the RX descriptors and allocate mbufs for them. Note that 2605 * we arrange the descriptors in a closed ring, so that the last descriptor 2606 * points back to the first. 2607 */ 2608 static int 2609 dc_list_rx_init(struct dc_softc *sc) 2610 { 2611 struct dc_chain_data *cd; 2612 struct dc_list_data *ld; 2613 int i, nexti; 2614 2615 cd = &sc->dc_cdata; 2616 ld = &sc->dc_ldata; 2617 2618 for (i = 0; i < DC_RX_LIST_CNT; i++) { 2619 if (dc_newbuf(sc, i) != 0) 2620 return (ENOBUFS); 2621 if (i == DC_RX_LIST_CNT - 1) 2622 nexti = 0; 2623 else 2624 nexti = i + 1; 2625 ld->dc_rx_list[i].dc_next = htole32(DC_RXDESC(sc, nexti)); 2626 } 2627 2628 cd->dc_rx_prod = 0; 2629 bus_dmamap_sync(sc->dc_rx_ltag, sc->dc_rx_lmap, 2630 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2631 return (0); 2632 } 2633 2634 /* 2635 * Initialize an RX descriptor and attach an MBUF cluster. 2636 */ 2637 static int 2638 dc_newbuf(struct dc_softc *sc, int i) 2639 { 2640 struct mbuf *m; 2641 bus_dmamap_t map; 2642 bus_dma_segment_t segs[1]; 2643 int error, nseg; 2644 2645 m = m_getcl(M_NOWAIT, MT_DATA, M_PKTHDR); 2646 if (m == NULL) 2647 return (ENOBUFS); 2648 m->m_len = m->m_pkthdr.len = MCLBYTES; 2649 m_adj(m, sizeof(u_int64_t)); 2650 2651 /* 2652 * If this is a PNIC chip, zero the buffer. This is part 2653 * of the workaround for the receive bug in the 82c168 and 2654 * 82c169 chips. 2655 */ 2656 if (sc->dc_flags & DC_PNIC_RX_BUG_WAR) 2657 bzero(mtod(m, char *), m->m_len); 2658 2659 error = bus_dmamap_load_mbuf_sg(sc->dc_rx_mtag, sc->dc_sparemap, 2660 m, segs, &nseg, 0); 2661 if (error) { 2662 m_freem(m); 2663 return (error); 2664 } 2665 KASSERT(nseg == 1, ("%s: wrong number of segments (%d)", __func__, 2666 nseg)); 2667 if (sc->dc_cdata.dc_rx_chain[i] != NULL) 2668 bus_dmamap_unload(sc->dc_rx_mtag, sc->dc_cdata.dc_rx_map[i]); 2669 2670 map = sc->dc_cdata.dc_rx_map[i]; 2671 sc->dc_cdata.dc_rx_map[i] = sc->dc_sparemap; 2672 sc->dc_sparemap = map; 2673 sc->dc_cdata.dc_rx_chain[i] = m; 2674 bus_dmamap_sync(sc->dc_rx_mtag, sc->dc_cdata.dc_rx_map[i], 2675 BUS_DMASYNC_PREREAD); 2676 2677 sc->dc_ldata.dc_rx_list[i].dc_ctl = htole32(DC_RXCTL_RLINK | DC_RXLEN); 2678 sc->dc_ldata.dc_rx_list[i].dc_data = 2679 htole32(DC_ADDR_LO(segs[0].ds_addr)); 2680 sc->dc_ldata.dc_rx_list[i].dc_status = htole32(DC_RXSTAT_OWN); 2681 bus_dmamap_sync(sc->dc_rx_ltag, sc->dc_rx_lmap, 2682 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2683 return (0); 2684 } 2685 2686 /* 2687 * Grrrrr. 2688 * The PNIC chip has a terrible bug in it that manifests itself during 2689 * periods of heavy activity. The exact mode of failure if difficult to 2690 * pinpoint: sometimes it only happens in promiscuous mode, sometimes it 2691 * will happen on slow machines. The bug is that sometimes instead of 2692 * uploading one complete frame during reception, it uploads what looks 2693 * like the entire contents of its FIFO memory. The frame we want is at 2694 * the end of the whole mess, but we never know exactly how much data has 2695 * been uploaded, so salvaging the frame is hard. 2696 * 2697 * There is only one way to do it reliably, and it's disgusting. 2698 * Here's what we know: 2699 * 2700 * - We know there will always be somewhere between one and three extra 2701 * descriptors uploaded. 2702 * 2703 * - We know the desired received frame will always be at the end of the 2704 * total data upload. 2705 * 2706 * - We know the size of the desired received frame because it will be 2707 * provided in the length field of the status word in the last descriptor. 2708 * 2709 * Here's what we do: 2710 * 2711 * - When we allocate buffers for the receive ring, we bzero() them. 2712 * This means that we know that the buffer contents should be all 2713 * zeros, except for data uploaded by the chip. 2714 * 2715 * - We also force the PNIC chip to upload frames that include the 2716 * ethernet CRC at the end. 2717 * 2718 * - We gather all of the bogus frame data into a single buffer. 2719 * 2720 * - We then position a pointer at the end of this buffer and scan 2721 * backwards until we encounter the first non-zero byte of data. 2722 * This is the end of the received frame. We know we will encounter 2723 * some data at the end of the frame because the CRC will always be 2724 * there, so even if the sender transmits a packet of all zeros, 2725 * we won't be fooled. 2726 * 2727 * - We know the size of the actual received frame, so we subtract 2728 * that value from the current pointer location. This brings us 2729 * to the start of the actual received packet. 2730 * 2731 * - We copy this into an mbuf and pass it on, along with the actual 2732 * frame length. 2733 * 2734 * The performance hit is tremendous, but it beats dropping frames all 2735 * the time. 2736 */ 2737 2738 #define DC_WHOLEFRAME (DC_RXSTAT_FIRSTFRAG | DC_RXSTAT_LASTFRAG) 2739 static void 2740 dc_pnic_rx_bug_war(struct dc_softc *sc, int idx) 2741 { 2742 struct dc_desc *cur_rx; 2743 struct dc_desc *c = NULL; 2744 struct mbuf *m = NULL; 2745 unsigned char *ptr; 2746 int i, total_len; 2747 uint32_t rxstat = 0; 2748 2749 i = sc->dc_pnic_rx_bug_save; 2750 cur_rx = &sc->dc_ldata.dc_rx_list[idx]; 2751 ptr = sc->dc_pnic_rx_buf; 2752 bzero(ptr, DC_RXLEN * 5); 2753 2754 /* Copy all the bytes from the bogus buffers. */ 2755 while (1) { 2756 c = &sc->dc_ldata.dc_rx_list[i]; 2757 rxstat = le32toh(c->dc_status); 2758 m = sc->dc_cdata.dc_rx_chain[i]; 2759 bcopy(mtod(m, char *), ptr, DC_RXLEN); 2760 ptr += DC_RXLEN; 2761 /* If this is the last buffer, break out. */ 2762 if (i == idx || rxstat & DC_RXSTAT_LASTFRAG) 2763 break; 2764 dc_discard_rxbuf(sc, i); 2765 DC_INC(i, DC_RX_LIST_CNT); 2766 } 2767 2768 /* Find the length of the actual receive frame. */ 2769 total_len = DC_RXBYTES(rxstat); 2770 2771 /* Scan backwards until we hit a non-zero byte. */ 2772 while (*ptr == 0x00) 2773 ptr--; 2774 2775 /* Round off. */ 2776 if ((uintptr_t)(ptr) & 0x3) 2777 ptr -= 1; 2778 2779 /* Now find the start of the frame. */ 2780 ptr -= total_len; 2781 if (ptr < sc->dc_pnic_rx_buf) 2782 ptr = sc->dc_pnic_rx_buf; 2783 2784 /* 2785 * Now copy the salvaged frame to the last mbuf and fake up 2786 * the status word to make it look like a successful 2787 * frame reception. 2788 */ 2789 bcopy(ptr, mtod(m, char *), total_len); 2790 cur_rx->dc_status = htole32(rxstat | DC_RXSTAT_FIRSTFRAG); 2791 } 2792 2793 /* 2794 * This routine searches the RX ring for dirty descriptors in the 2795 * event that the rxeof routine falls out of sync with the chip's 2796 * current descriptor pointer. This may happen sometimes as a result 2797 * of a "no RX buffer available" condition that happens when the chip 2798 * consumes all of the RX buffers before the driver has a chance to 2799 * process the RX ring. This routine may need to be called more than 2800 * once to bring the driver back in sync with the chip, however we 2801 * should still be getting RX DONE interrupts to drive the search 2802 * for new packets in the RX ring, so we should catch up eventually. 2803 */ 2804 static int 2805 dc_rx_resync(struct dc_softc *sc) 2806 { 2807 struct dc_desc *cur_rx; 2808 int i, pos; 2809 2810 pos = sc->dc_cdata.dc_rx_prod; 2811 2812 for (i = 0; i < DC_RX_LIST_CNT; i++) { 2813 cur_rx = &sc->dc_ldata.dc_rx_list[pos]; 2814 if (!(le32toh(cur_rx->dc_status) & DC_RXSTAT_OWN)) 2815 break; 2816 DC_INC(pos, DC_RX_LIST_CNT); 2817 } 2818 2819 /* If the ring really is empty, then just return. */ 2820 if (i == DC_RX_LIST_CNT) 2821 return (0); 2822 2823 /* We've fallen behing the chip: catch it. */ 2824 sc->dc_cdata.dc_rx_prod = pos; 2825 2826 return (EAGAIN); 2827 } 2828 2829 static void 2830 dc_discard_rxbuf(struct dc_softc *sc, int i) 2831 { 2832 struct mbuf *m; 2833 2834 if (sc->dc_flags & DC_PNIC_RX_BUG_WAR) { 2835 m = sc->dc_cdata.dc_rx_chain[i]; 2836 bzero(mtod(m, char *), m->m_len); 2837 } 2838 2839 sc->dc_ldata.dc_rx_list[i].dc_ctl = htole32(DC_RXCTL_RLINK | DC_RXLEN); 2840 sc->dc_ldata.dc_rx_list[i].dc_status = htole32(DC_RXSTAT_OWN); 2841 bus_dmamap_sync(sc->dc_rx_ltag, sc->dc_rx_lmap, BUS_DMASYNC_PREREAD | 2842 BUS_DMASYNC_PREWRITE); 2843 } 2844 2845 /* 2846 * A frame has been uploaded: pass the resulting mbuf chain up to 2847 * the higher level protocols. 2848 */ 2849 static int 2850 dc_rxeof(struct dc_softc *sc) 2851 { 2852 struct mbuf *m; 2853 if_t ifp; 2854 struct dc_desc *cur_rx; 2855 int i, total_len, rx_npkts; 2856 uint32_t rxstat; 2857 2858 DC_LOCK_ASSERT(sc); 2859 2860 ifp = sc->dc_ifp; 2861 rx_npkts = 0; 2862 2863 bus_dmamap_sync(sc->dc_rx_ltag, sc->dc_rx_lmap, BUS_DMASYNC_POSTREAD | 2864 BUS_DMASYNC_POSTWRITE); 2865 for (i = sc->dc_cdata.dc_rx_prod; 2866 (if_getdrvflags(ifp) & IFF_DRV_RUNNING) != 0; 2867 DC_INC(i, DC_RX_LIST_CNT)) { 2868 #ifdef DEVICE_POLLING 2869 if (if_getcapenable(ifp) & IFCAP_POLLING) { 2870 if (sc->rxcycles <= 0) 2871 break; 2872 sc->rxcycles--; 2873 } 2874 #endif 2875 cur_rx = &sc->dc_ldata.dc_rx_list[i]; 2876 rxstat = le32toh(cur_rx->dc_status); 2877 if ((rxstat & DC_RXSTAT_OWN) != 0) 2878 break; 2879 m = sc->dc_cdata.dc_rx_chain[i]; 2880 bus_dmamap_sync(sc->dc_rx_mtag, sc->dc_cdata.dc_rx_map[i], 2881 BUS_DMASYNC_POSTREAD); 2882 total_len = DC_RXBYTES(rxstat); 2883 rx_npkts++; 2884 2885 if (sc->dc_flags & DC_PNIC_RX_BUG_WAR) { 2886 if ((rxstat & DC_WHOLEFRAME) != DC_WHOLEFRAME) { 2887 if (rxstat & DC_RXSTAT_FIRSTFRAG) 2888 sc->dc_pnic_rx_bug_save = i; 2889 if ((rxstat & DC_RXSTAT_LASTFRAG) == 0) 2890 continue; 2891 dc_pnic_rx_bug_war(sc, i); 2892 rxstat = le32toh(cur_rx->dc_status); 2893 total_len = DC_RXBYTES(rxstat); 2894 } 2895 } 2896 2897 /* 2898 * If an error occurs, update stats, clear the 2899 * status word and leave the mbuf cluster in place: 2900 * it should simply get re-used next time this descriptor 2901 * comes up in the ring. However, don't report long 2902 * frames as errors since they could be vlans. 2903 */ 2904 if ((rxstat & DC_RXSTAT_RXERR)) { 2905 if (!(rxstat & DC_RXSTAT_GIANT) || 2906 (rxstat & (DC_RXSTAT_CRCERR | DC_RXSTAT_DRIBBLE | 2907 DC_RXSTAT_MIIERE | DC_RXSTAT_COLLSEEN | 2908 DC_RXSTAT_RUNT | DC_RXSTAT_DE))) { 2909 if_inc_counter(ifp, IFCOUNTER_IERRORS, 1); 2910 if (rxstat & DC_RXSTAT_COLLSEEN) 2911 if_inc_counter(ifp, IFCOUNTER_COLLISIONS, 1); 2912 dc_discard_rxbuf(sc, i); 2913 if (rxstat & DC_RXSTAT_CRCERR) 2914 continue; 2915 else { 2916 if_setdrvflagbits(ifp, 0, IFF_DRV_RUNNING); 2917 dc_init_locked(sc); 2918 return (rx_npkts); 2919 } 2920 } 2921 } 2922 2923 /* No errors; receive the packet. */ 2924 total_len -= ETHER_CRC_LEN; 2925 #ifdef __NO_STRICT_ALIGNMENT 2926 /* 2927 * On architectures without alignment problems we try to 2928 * allocate a new buffer for the receive ring, and pass up 2929 * the one where the packet is already, saving the expensive 2930 * copy done in m_devget(). 2931 * If we are on an architecture with alignment problems, or 2932 * if the allocation fails, then use m_devget and leave the 2933 * existing buffer in the receive ring. 2934 */ 2935 if (dc_newbuf(sc, i) != 0) { 2936 dc_discard_rxbuf(sc, i); 2937 if_inc_counter(ifp, IFCOUNTER_IQDROPS, 1); 2938 continue; 2939 } 2940 m->m_pkthdr.rcvif = ifp; 2941 m->m_pkthdr.len = m->m_len = total_len; 2942 #else 2943 { 2944 struct mbuf *m0; 2945 2946 m0 = m_devget(mtod(m, char *), total_len, 2947 ETHER_ALIGN, ifp, NULL); 2948 dc_discard_rxbuf(sc, i); 2949 if (m0 == NULL) { 2950 if_inc_counter(ifp, IFCOUNTER_IQDROPS, 1); 2951 continue; 2952 } 2953 m = m0; 2954 } 2955 #endif 2956 2957 if_inc_counter(ifp, IFCOUNTER_IPACKETS, 1); 2958 DC_UNLOCK(sc); 2959 if_input(ifp, m); 2960 DC_LOCK(sc); 2961 } 2962 2963 sc->dc_cdata.dc_rx_prod = i; 2964 return (rx_npkts); 2965 } 2966 2967 /* 2968 * A frame was downloaded to the chip. It's safe for us to clean up 2969 * the list buffers. 2970 */ 2971 static void 2972 dc_txeof(struct dc_softc *sc) 2973 { 2974 struct dc_desc *cur_tx; 2975 if_t ifp; 2976 int idx, setup; 2977 uint32_t ctl, txstat; 2978 2979 if (sc->dc_cdata.dc_tx_cnt == 0) 2980 return; 2981 2982 ifp = sc->dc_ifp; 2983 2984 /* 2985 * Go through our tx list and free mbufs for those 2986 * frames that have been transmitted. 2987 */ 2988 bus_dmamap_sync(sc->dc_tx_ltag, sc->dc_tx_lmap, BUS_DMASYNC_POSTREAD | 2989 BUS_DMASYNC_POSTWRITE); 2990 setup = 0; 2991 for (idx = sc->dc_cdata.dc_tx_cons; idx != sc->dc_cdata.dc_tx_prod; 2992 DC_INC(idx, DC_TX_LIST_CNT), sc->dc_cdata.dc_tx_cnt--) { 2993 cur_tx = &sc->dc_ldata.dc_tx_list[idx]; 2994 txstat = le32toh(cur_tx->dc_status); 2995 ctl = le32toh(cur_tx->dc_ctl); 2996 2997 if (txstat & DC_TXSTAT_OWN) 2998 break; 2999 3000 if (sc->dc_cdata.dc_tx_chain[idx] == NULL) 3001 continue; 3002 3003 if (ctl & DC_TXCTL_SETUP) { 3004 cur_tx->dc_ctl = htole32(ctl & ~DC_TXCTL_SETUP); 3005 setup++; 3006 bus_dmamap_sync(sc->dc_stag, sc->dc_smap, 3007 BUS_DMASYNC_POSTWRITE); 3008 /* 3009 * Yes, the PNIC is so brain damaged 3010 * that it will sometimes generate a TX 3011 * underrun error while DMAing the RX 3012 * filter setup frame. If we detect this, 3013 * we have to send the setup frame again, 3014 * or else the filter won't be programmed 3015 * correctly. 3016 */ 3017 if (DC_IS_PNIC(sc)) { 3018 if (txstat & DC_TXSTAT_ERRSUM) 3019 dc_setfilt(sc); 3020 } 3021 sc->dc_cdata.dc_tx_chain[idx] = NULL; 3022 continue; 3023 } 3024 3025 if (DC_IS_XIRCOM(sc) || DC_IS_CONEXANT(sc)) { 3026 /* 3027 * XXX: Why does my Xircom taunt me so? 3028 * For some reason it likes setting the CARRLOST flag 3029 * even when the carrier is there. wtf?!? 3030 * Who knows, but Conexant chips have the 3031 * same problem. Maybe they took lessons 3032 * from Xircom. 3033 */ 3034 if (/*sc->dc_type == DC_TYPE_21143 &&*/ 3035 sc->dc_pmode == DC_PMODE_MII && 3036 ((txstat & 0xFFFF) & ~(DC_TXSTAT_ERRSUM | 3037 DC_TXSTAT_NOCARRIER))) 3038 txstat &= ~DC_TXSTAT_ERRSUM; 3039 } else { 3040 if (/*sc->dc_type == DC_TYPE_21143 &&*/ 3041 sc->dc_pmode == DC_PMODE_MII && 3042 ((txstat & 0xFFFF) & ~(DC_TXSTAT_ERRSUM | 3043 DC_TXSTAT_NOCARRIER | DC_TXSTAT_CARRLOST))) 3044 txstat &= ~DC_TXSTAT_ERRSUM; 3045 } 3046 3047 if (txstat & DC_TXSTAT_ERRSUM) { 3048 if_inc_counter(ifp, IFCOUNTER_OERRORS, 1); 3049 if (txstat & DC_TXSTAT_EXCESSCOLL) 3050 if_inc_counter(ifp, IFCOUNTER_COLLISIONS, 1); 3051 if (txstat & DC_TXSTAT_LATECOLL) 3052 if_inc_counter(ifp, IFCOUNTER_COLLISIONS, 1); 3053 if (!(txstat & DC_TXSTAT_UNDERRUN)) { 3054 if_setdrvflagbits(ifp, 0, IFF_DRV_RUNNING); 3055 dc_init_locked(sc); 3056 return; 3057 } 3058 } else 3059 if_inc_counter(ifp, IFCOUNTER_OPACKETS, 1); 3060 if_inc_counter(ifp, IFCOUNTER_COLLISIONS, (txstat & DC_TXSTAT_COLLCNT) >> 3); 3061 3062 bus_dmamap_sync(sc->dc_tx_mtag, sc->dc_cdata.dc_tx_map[idx], 3063 BUS_DMASYNC_POSTWRITE); 3064 bus_dmamap_unload(sc->dc_tx_mtag, sc->dc_cdata.dc_tx_map[idx]); 3065 m_freem(sc->dc_cdata.dc_tx_chain[idx]); 3066 sc->dc_cdata.dc_tx_chain[idx] = NULL; 3067 } 3068 sc->dc_cdata.dc_tx_cons = idx; 3069 3070 if (sc->dc_cdata.dc_tx_cnt <= DC_TX_LIST_CNT - DC_TX_LIST_RSVD) { 3071 if_setdrvflagbits(ifp, 0, IFF_DRV_OACTIVE); 3072 if (sc->dc_cdata.dc_tx_cnt == 0) 3073 sc->dc_wdog_timer = 0; 3074 } 3075 if (setup > 0) 3076 bus_dmamap_sync(sc->dc_tx_ltag, sc->dc_tx_lmap, 3077 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 3078 } 3079 3080 static void 3081 dc_tick(void *xsc) 3082 { 3083 struct dc_softc *sc; 3084 struct mii_data *mii; 3085 if_t ifp; 3086 uint32_t r; 3087 3088 sc = xsc; 3089 DC_LOCK_ASSERT(sc); 3090 ifp = sc->dc_ifp; 3091 mii = device_get_softc(sc->dc_miibus); 3092 3093 /* 3094 * Reclaim transmitted frames for controllers that do 3095 * not generate TX completion interrupt for every frame. 3096 */ 3097 if (sc->dc_flags & DC_TX_USE_TX_INTR) 3098 dc_txeof(sc); 3099 3100 if (sc->dc_flags & DC_REDUCED_MII_POLL) { 3101 if (sc->dc_flags & DC_21143_NWAY) { 3102 r = CSR_READ_4(sc, DC_10BTSTAT); 3103 if (IFM_SUBTYPE(mii->mii_media_active) == 3104 IFM_100_TX && (r & DC_TSTAT_LS100)) { 3105 sc->dc_link = 0; 3106 mii_mediachg(mii); 3107 } 3108 if (IFM_SUBTYPE(mii->mii_media_active) == 3109 IFM_10_T && (r & DC_TSTAT_LS10)) { 3110 sc->dc_link = 0; 3111 mii_mediachg(mii); 3112 } 3113 if (sc->dc_link == 0) 3114 mii_tick(mii); 3115 } else { 3116 /* 3117 * For NICs which never report DC_RXSTATE_WAIT, we 3118 * have to bite the bullet... 3119 */ 3120 if ((DC_HAS_BROKEN_RXSTATE(sc) || (CSR_READ_4(sc, 3121 DC_ISR) & DC_ISR_RX_STATE) == DC_RXSTATE_WAIT) && 3122 sc->dc_cdata.dc_tx_cnt == 0) 3123 mii_tick(mii); 3124 } 3125 } else 3126 mii_tick(mii); 3127 3128 /* 3129 * When the init routine completes, we expect to be able to send 3130 * packets right away, and in fact the network code will send a 3131 * gratuitous ARP the moment the init routine marks the interface 3132 * as running. However, even though the MAC may have been initialized, 3133 * there may be a delay of a few seconds before the PHY completes 3134 * autonegotiation and the link is brought up. Any transmissions 3135 * made during that delay will be lost. Dealing with this is tricky: 3136 * we can't just pause in the init routine while waiting for the 3137 * PHY to come ready since that would bring the whole system to 3138 * a screeching halt for several seconds. 3139 * 3140 * What we do here is prevent the TX start routine from sending 3141 * any packets until a link has been established. After the 3142 * interface has been initialized, the tick routine will poll 3143 * the state of the PHY until the IFM_ACTIVE flag is set. Until 3144 * that time, packets will stay in the send queue, and once the 3145 * link comes up, they will be flushed out to the wire. 3146 */ 3147 if (sc->dc_link != 0 && !if_sendq_empty(ifp)) 3148 dc_start_locked(ifp); 3149 3150 if (sc->dc_flags & DC_21143_NWAY && !sc->dc_link) 3151 callout_reset(&sc->dc_stat_ch, hz/10, dc_tick, sc); 3152 else 3153 callout_reset(&sc->dc_stat_ch, hz, dc_tick, sc); 3154 } 3155 3156 /* 3157 * A transmit underrun has occurred. Back off the transmit threshold, 3158 * or switch to store and forward mode if we have to. 3159 */ 3160 static void 3161 dc_tx_underrun(struct dc_softc *sc) 3162 { 3163 uint32_t netcfg, isr; 3164 int i, reinit; 3165 3166 reinit = 0; 3167 netcfg = CSR_READ_4(sc, DC_NETCFG); 3168 device_printf(sc->dc_dev, "TX underrun -- "); 3169 if ((sc->dc_flags & DC_TX_STORENFWD) == 0) { 3170 if (sc->dc_txthresh + DC_TXTHRESH_INC > DC_TXTHRESH_MAX) { 3171 printf("using store and forward mode\n"); 3172 netcfg |= DC_NETCFG_STORENFWD; 3173 } else { 3174 printf("increasing TX threshold\n"); 3175 sc->dc_txthresh += DC_TXTHRESH_INC; 3176 netcfg &= ~DC_NETCFG_TX_THRESH; 3177 netcfg |= sc->dc_txthresh; 3178 } 3179 3180 if (DC_IS_INTEL(sc)) { 3181 /* 3182 * The real 21143 requires that the transmitter be idle 3183 * in order to change the transmit threshold or store 3184 * and forward state. 3185 */ 3186 CSR_WRITE_4(sc, DC_NETCFG, netcfg & ~DC_NETCFG_TX_ON); 3187 3188 for (i = 0; i < DC_TIMEOUT; i++) { 3189 isr = CSR_READ_4(sc, DC_ISR); 3190 if (isr & DC_ISR_TX_IDLE) 3191 break; 3192 DELAY(10); 3193 } 3194 if (i == DC_TIMEOUT) { 3195 device_printf(sc->dc_dev, 3196 "%s: failed to force tx to idle state\n", 3197 __func__); 3198 reinit++; 3199 } 3200 } 3201 } else { 3202 printf("resetting\n"); 3203 reinit++; 3204 } 3205 3206 if (reinit == 0) { 3207 CSR_WRITE_4(sc, DC_NETCFG, netcfg); 3208 if (DC_IS_INTEL(sc)) 3209 CSR_WRITE_4(sc, DC_NETCFG, netcfg | DC_NETCFG_TX_ON); 3210 } else { 3211 if_setdrvflagbits(sc->dc_ifp, 0, IFF_DRV_RUNNING); 3212 dc_init_locked(sc); 3213 } 3214 } 3215 3216 #ifdef DEVICE_POLLING 3217 static poll_handler_t dc_poll; 3218 3219 static int 3220 dc_poll(if_t ifp, enum poll_cmd cmd, int count) 3221 { 3222 struct dc_softc *sc = if_getsoftc(ifp); 3223 int rx_npkts = 0; 3224 3225 DC_LOCK(sc); 3226 3227 if (!(if_getdrvflags(ifp) & IFF_DRV_RUNNING)) { 3228 DC_UNLOCK(sc); 3229 return (rx_npkts); 3230 } 3231 3232 sc->rxcycles = count; 3233 rx_npkts = dc_rxeof(sc); 3234 dc_txeof(sc); 3235 if (!if_sendq_empty(ifp) && 3236 !(if_getdrvflags(ifp) & IFF_DRV_OACTIVE)) 3237 dc_start_locked(ifp); 3238 3239 if (cmd == POLL_AND_CHECK_STATUS) { /* also check status register */ 3240 uint32_t status; 3241 3242 status = CSR_READ_4(sc, DC_ISR); 3243 status &= (DC_ISR_RX_WATDOGTIMEO | DC_ISR_RX_NOBUF | 3244 DC_ISR_TX_NOBUF | DC_ISR_TX_IDLE | DC_ISR_TX_UNDERRUN | 3245 DC_ISR_BUS_ERR); 3246 if (!status) { 3247 DC_UNLOCK(sc); 3248 return (rx_npkts); 3249 } 3250 /* ack what we have */ 3251 CSR_WRITE_4(sc, DC_ISR, status); 3252 3253 if (status & (DC_ISR_RX_WATDOGTIMEO | DC_ISR_RX_NOBUF)) { 3254 uint32_t r = CSR_READ_4(sc, DC_FRAMESDISCARDED); 3255 if_inc_counter(ifp, IFCOUNTER_IERRORS, (r & 0xffff) + ((r >> 17) & 0x7ff)); 3256 3257 if (dc_rx_resync(sc)) 3258 dc_rxeof(sc); 3259 } 3260 /* restart transmit unit if necessary */ 3261 if (status & DC_ISR_TX_IDLE && sc->dc_cdata.dc_tx_cnt) 3262 CSR_WRITE_4(sc, DC_TXSTART, 0xFFFFFFFF); 3263 3264 if (status & DC_ISR_TX_UNDERRUN) 3265 dc_tx_underrun(sc); 3266 3267 if (status & DC_ISR_BUS_ERR) { 3268 if_printf(ifp, "%s: bus error\n", __func__); 3269 if_setdrvflagbits(ifp, 0, IFF_DRV_RUNNING); 3270 dc_init_locked(sc); 3271 } 3272 } 3273 DC_UNLOCK(sc); 3274 return (rx_npkts); 3275 } 3276 #endif /* DEVICE_POLLING */ 3277 3278 static void 3279 dc_intr(void *arg) 3280 { 3281 struct dc_softc *sc; 3282 if_t ifp; 3283 uint32_t r, status; 3284 int n; 3285 3286 sc = arg; 3287 3288 if (sc->suspended) 3289 return; 3290 3291 DC_LOCK(sc); 3292 status = CSR_READ_4(sc, DC_ISR); 3293 if (status == 0xFFFFFFFF || (status & DC_INTRS) == 0) { 3294 DC_UNLOCK(sc); 3295 return; 3296 } 3297 ifp = sc->dc_ifp; 3298 #ifdef DEVICE_POLLING 3299 if (if_getcapenable(ifp) & IFCAP_POLLING) { 3300 DC_UNLOCK(sc); 3301 return; 3302 } 3303 #endif 3304 /* Disable interrupts. */ 3305 CSR_WRITE_4(sc, DC_IMR, 0x00000000); 3306 3307 for (n = 16; n > 0; n--) { 3308 if ((if_getdrvflags(ifp) & IFF_DRV_RUNNING) == 0) 3309 break; 3310 /* Ack interrupts. */ 3311 CSR_WRITE_4(sc, DC_ISR, status); 3312 3313 if (status & DC_ISR_RX_OK) { 3314 if (dc_rxeof(sc) == 0) { 3315 while (dc_rx_resync(sc)) 3316 dc_rxeof(sc); 3317 } 3318 } 3319 3320 if (status & (DC_ISR_TX_OK | DC_ISR_TX_NOBUF)) 3321 dc_txeof(sc); 3322 3323 if (status & DC_ISR_TX_IDLE) { 3324 dc_txeof(sc); 3325 if (sc->dc_cdata.dc_tx_cnt) { 3326 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_TX_ON); 3327 CSR_WRITE_4(sc, DC_TXSTART, 0xFFFFFFFF); 3328 } 3329 } 3330 3331 if (status & DC_ISR_TX_UNDERRUN) 3332 dc_tx_underrun(sc); 3333 3334 if ((status & DC_ISR_RX_WATDOGTIMEO) 3335 || (status & DC_ISR_RX_NOBUF)) { 3336 r = CSR_READ_4(sc, DC_FRAMESDISCARDED); 3337 if_inc_counter(ifp, IFCOUNTER_IERRORS, (r & 0xffff) + ((r >> 17) & 0x7ff)); 3338 if (dc_rxeof(sc) == 0) { 3339 while (dc_rx_resync(sc)) 3340 dc_rxeof(sc); 3341 } 3342 } 3343 3344 if (!if_sendq_empty(ifp)) 3345 dc_start_locked(ifp); 3346 3347 if (status & DC_ISR_BUS_ERR) { 3348 if_setdrvflagbits(ifp, 0, IFF_DRV_RUNNING); 3349 dc_init_locked(sc); 3350 DC_UNLOCK(sc); 3351 return; 3352 } 3353 status = CSR_READ_4(sc, DC_ISR); 3354 if (status == 0xFFFFFFFF || (status & DC_INTRS) == 0) 3355 break; 3356 } 3357 3358 /* Re-enable interrupts. */ 3359 if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) 3360 CSR_WRITE_4(sc, DC_IMR, DC_INTRS); 3361 3362 DC_UNLOCK(sc); 3363 } 3364 3365 /* 3366 * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data 3367 * pointers to the fragment pointers. 3368 */ 3369 static int 3370 dc_encap(struct dc_softc *sc, struct mbuf **m_head) 3371 { 3372 bus_dma_segment_t segs[DC_MAXFRAGS]; 3373 bus_dmamap_t map; 3374 struct dc_desc *f; 3375 struct mbuf *m; 3376 int cur, defragged, error, first, frag, i, idx, nseg; 3377 3378 m = NULL; 3379 defragged = 0; 3380 if (sc->dc_flags & DC_TX_COALESCE && 3381 ((*m_head)->m_next != NULL || sc->dc_flags & DC_TX_ALIGN)) { 3382 m = m_defrag(*m_head, M_NOWAIT); 3383 defragged = 1; 3384 } else { 3385 /* 3386 * Count the number of frags in this chain to see if we 3387 * need to m_collapse. Since the descriptor list is shared 3388 * by all packets, we'll m_collapse long chains so that they 3389 * do not use up the entire list, even if they would fit. 3390 */ 3391 i = 0; 3392 for (m = *m_head; m != NULL; m = m->m_next) 3393 i++; 3394 if (i > DC_TX_LIST_CNT / 4 || 3395 DC_TX_LIST_CNT - i + sc->dc_cdata.dc_tx_cnt <= 3396 DC_TX_LIST_RSVD) { 3397 m = m_collapse(*m_head, M_NOWAIT, DC_MAXFRAGS); 3398 defragged = 1; 3399 } 3400 } 3401 if (defragged != 0) { 3402 if (m == NULL) { 3403 m_freem(*m_head); 3404 *m_head = NULL; 3405 return (ENOBUFS); 3406 } 3407 *m_head = m; 3408 } 3409 3410 idx = sc->dc_cdata.dc_tx_prod; 3411 error = bus_dmamap_load_mbuf_sg(sc->dc_tx_mtag, 3412 sc->dc_cdata.dc_tx_map[idx], *m_head, segs, &nseg, 0); 3413 if (error == EFBIG) { 3414 if (defragged != 0 || (m = m_collapse(*m_head, M_NOWAIT, 3415 DC_MAXFRAGS)) == NULL) { 3416 m_freem(*m_head); 3417 *m_head = NULL; 3418 return (defragged != 0 ? error : ENOBUFS); 3419 } 3420 *m_head = m; 3421 error = bus_dmamap_load_mbuf_sg(sc->dc_tx_mtag, 3422 sc->dc_cdata.dc_tx_map[idx], *m_head, segs, &nseg, 0); 3423 if (error != 0) { 3424 m_freem(*m_head); 3425 *m_head = NULL; 3426 return (error); 3427 } 3428 } else if (error != 0) 3429 return (error); 3430 KASSERT(nseg <= DC_MAXFRAGS, 3431 ("%s: wrong number of segments (%d)", __func__, nseg)); 3432 if (nseg == 0) { 3433 m_freem(*m_head); 3434 *m_head = NULL; 3435 return (EIO); 3436 } 3437 3438 /* Check descriptor overruns. */ 3439 if (sc->dc_cdata.dc_tx_cnt + nseg > DC_TX_LIST_CNT - DC_TX_LIST_RSVD) { 3440 bus_dmamap_unload(sc->dc_tx_mtag, sc->dc_cdata.dc_tx_map[idx]); 3441 return (ENOBUFS); 3442 } 3443 bus_dmamap_sync(sc->dc_tx_mtag, sc->dc_cdata.dc_tx_map[idx], 3444 BUS_DMASYNC_PREWRITE); 3445 3446 first = cur = frag = sc->dc_cdata.dc_tx_prod; 3447 for (i = 0; i < nseg; i++) { 3448 if ((sc->dc_flags & DC_TX_ADMTEK_WAR) && 3449 (frag == (DC_TX_LIST_CNT - 1)) && 3450 (first != sc->dc_cdata.dc_tx_first)) { 3451 bus_dmamap_unload(sc->dc_tx_mtag, 3452 sc->dc_cdata.dc_tx_map[first]); 3453 m_freem(*m_head); 3454 *m_head = NULL; 3455 return (ENOBUFS); 3456 } 3457 3458 f = &sc->dc_ldata.dc_tx_list[frag]; 3459 f->dc_ctl = htole32(DC_TXCTL_TLINK | segs[i].ds_len); 3460 if (i == 0) { 3461 f->dc_status = 0; 3462 f->dc_ctl |= htole32(DC_TXCTL_FIRSTFRAG); 3463 } else 3464 f->dc_status = htole32(DC_TXSTAT_OWN); 3465 f->dc_data = htole32(DC_ADDR_LO(segs[i].ds_addr)); 3466 cur = frag; 3467 DC_INC(frag, DC_TX_LIST_CNT); 3468 } 3469 3470 sc->dc_cdata.dc_tx_prod = frag; 3471 sc->dc_cdata.dc_tx_cnt += nseg; 3472 sc->dc_cdata.dc_tx_chain[cur] = *m_head; 3473 sc->dc_ldata.dc_tx_list[cur].dc_ctl |= htole32(DC_TXCTL_LASTFRAG); 3474 if (sc->dc_flags & DC_TX_INTR_FIRSTFRAG) 3475 sc->dc_ldata.dc_tx_list[first].dc_ctl |= 3476 htole32(DC_TXCTL_FINT); 3477 if (sc->dc_flags & DC_TX_INTR_ALWAYS) 3478 sc->dc_ldata.dc_tx_list[cur].dc_ctl |= htole32(DC_TXCTL_FINT); 3479 if (sc->dc_flags & DC_TX_USE_TX_INTR && 3480 ++sc->dc_cdata.dc_tx_pkts >= 8) { 3481 sc->dc_cdata.dc_tx_pkts = 0; 3482 sc->dc_ldata.dc_tx_list[cur].dc_ctl |= htole32(DC_TXCTL_FINT); 3483 } 3484 sc->dc_ldata.dc_tx_list[first].dc_status = htole32(DC_TXSTAT_OWN); 3485 3486 bus_dmamap_sync(sc->dc_tx_ltag, sc->dc_tx_lmap, 3487 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 3488 3489 /* 3490 * Swap the last and the first dmamaps to ensure the map for 3491 * this transmission is placed at the last descriptor. 3492 */ 3493 map = sc->dc_cdata.dc_tx_map[cur]; 3494 sc->dc_cdata.dc_tx_map[cur] = sc->dc_cdata.dc_tx_map[first]; 3495 sc->dc_cdata.dc_tx_map[first] = map; 3496 3497 return (0); 3498 } 3499 3500 static void 3501 dc_start(if_t ifp) 3502 { 3503 struct dc_softc *sc; 3504 3505 sc = if_getsoftc(ifp); 3506 DC_LOCK(sc); 3507 dc_start_locked(ifp); 3508 DC_UNLOCK(sc); 3509 } 3510 3511 /* 3512 * Main transmit routine 3513 * To avoid having to do mbuf copies, we put pointers to the mbuf data 3514 * regions directly in the transmit lists. We also save a copy of the 3515 * pointers since the transmit list fragment pointers are physical 3516 * addresses. 3517 */ 3518 static void 3519 dc_start_locked(if_t ifp) 3520 { 3521 struct dc_softc *sc; 3522 struct mbuf *m_head; 3523 int queued; 3524 3525 sc = if_getsoftc(ifp); 3526 3527 DC_LOCK_ASSERT(sc); 3528 3529 if ((if_getdrvflags(ifp) & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) != 3530 IFF_DRV_RUNNING || sc->dc_link == 0) 3531 return; 3532 3533 sc->dc_cdata.dc_tx_first = sc->dc_cdata.dc_tx_prod; 3534 3535 for (queued = 0; !if_sendq_empty(ifp); ) { 3536 /* 3537 * If there's no way we can send any packets, return now. 3538 */ 3539 if (sc->dc_cdata.dc_tx_cnt > DC_TX_LIST_CNT - DC_TX_LIST_RSVD) { 3540 if_setdrvflagbits(ifp, IFF_DRV_OACTIVE, 0); 3541 break; 3542 } 3543 m_head = if_dequeue(ifp); 3544 if (m_head == NULL) 3545 break; 3546 3547 if (dc_encap(sc, &m_head)) { 3548 if (m_head == NULL) 3549 break; 3550 if_sendq_prepend(ifp, m_head); 3551 if_setdrvflagbits(ifp, IFF_DRV_OACTIVE, 0); 3552 break; 3553 } 3554 3555 queued++; 3556 /* 3557 * If there's a BPF listener, bounce a copy of this frame 3558 * to him. 3559 */ 3560 BPF_MTAP(ifp, m_head); 3561 } 3562 3563 if (queued > 0) { 3564 /* Transmit */ 3565 if (!(sc->dc_flags & DC_TX_POLL)) 3566 CSR_WRITE_4(sc, DC_TXSTART, 0xFFFFFFFF); 3567 3568 /* 3569 * Set a timeout in case the chip goes out to lunch. 3570 */ 3571 sc->dc_wdog_timer = 5; 3572 } 3573 } 3574 3575 static void 3576 dc_init(void *xsc) 3577 { 3578 struct dc_softc *sc = xsc; 3579 3580 DC_LOCK(sc); 3581 dc_init_locked(sc); 3582 DC_UNLOCK(sc); 3583 } 3584 3585 static void 3586 dc_init_locked(struct dc_softc *sc) 3587 { 3588 if_t ifp = sc->dc_ifp; 3589 struct mii_data *mii; 3590 struct ifmedia *ifm; 3591 3592 DC_LOCK_ASSERT(sc); 3593 3594 if ((if_getdrvflags(ifp) & IFF_DRV_RUNNING) != 0) 3595 return; 3596 3597 mii = device_get_softc(sc->dc_miibus); 3598 3599 /* 3600 * Cancel pending I/O and free all RX/TX buffers. 3601 */ 3602 dc_stop(sc); 3603 dc_reset(sc); 3604 if (DC_IS_INTEL(sc)) { 3605 ifm = &mii->mii_media; 3606 dc_apply_fixup(sc, ifm->ifm_media); 3607 } 3608 3609 /* 3610 * Set cache alignment and burst length. 3611 */ 3612 if (DC_IS_ASIX(sc) || DC_IS_DAVICOM(sc) || DC_IS_ULI(sc)) 3613 CSR_WRITE_4(sc, DC_BUSCTL, 0); 3614 else 3615 CSR_WRITE_4(sc, DC_BUSCTL, DC_BUSCTL_MRME | DC_BUSCTL_MRLE); 3616 /* 3617 * Evenly share the bus between receive and transmit process. 3618 */ 3619 if (DC_IS_INTEL(sc)) 3620 DC_SETBIT(sc, DC_BUSCTL, DC_BUSCTL_ARBITRATION); 3621 if (DC_IS_DAVICOM(sc) || DC_IS_INTEL(sc)) { 3622 DC_SETBIT(sc, DC_BUSCTL, DC_BURSTLEN_USECA); 3623 } else { 3624 DC_SETBIT(sc, DC_BUSCTL, DC_BURSTLEN_16LONG); 3625 } 3626 if (sc->dc_flags & DC_TX_POLL) 3627 DC_SETBIT(sc, DC_BUSCTL, DC_TXPOLL_1); 3628 switch(sc->dc_cachesize) { 3629 case 32: 3630 DC_SETBIT(sc, DC_BUSCTL, DC_CACHEALIGN_32LONG); 3631 break; 3632 case 16: 3633 DC_SETBIT(sc, DC_BUSCTL, DC_CACHEALIGN_16LONG); 3634 break; 3635 case 8: 3636 DC_SETBIT(sc, DC_BUSCTL, DC_CACHEALIGN_8LONG); 3637 break; 3638 case 0: 3639 default: 3640 DC_SETBIT(sc, DC_BUSCTL, DC_CACHEALIGN_NONE); 3641 break; 3642 } 3643 3644 if (sc->dc_flags & DC_TX_STORENFWD) 3645 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_STORENFWD); 3646 else { 3647 if (sc->dc_txthresh > DC_TXTHRESH_MAX) { 3648 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_STORENFWD); 3649 } else { 3650 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_STORENFWD); 3651 DC_SETBIT(sc, DC_NETCFG, sc->dc_txthresh); 3652 } 3653 } 3654 3655 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_NO_RXCRC); 3656 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_TX_BACKOFF); 3657 3658 if (DC_IS_MACRONIX(sc) || DC_IS_PNICII(sc)) { 3659 /* 3660 * The app notes for the 98713 and 98715A say that 3661 * in order to have the chips operate properly, a magic 3662 * number must be written to CSR16. Macronix does not 3663 * document the meaning of these bits so there's no way 3664 * to know exactly what they do. The 98713 has a magic 3665 * number all its own; the rest all use a different one. 3666 */ 3667 DC_CLRBIT(sc, DC_MX_MAGICPACKET, 0xFFFF0000); 3668 if (sc->dc_type == DC_TYPE_98713) 3669 DC_SETBIT(sc, DC_MX_MAGICPACKET, DC_MX_MAGIC_98713); 3670 else 3671 DC_SETBIT(sc, DC_MX_MAGICPACKET, DC_MX_MAGIC_98715); 3672 } 3673 3674 if (DC_IS_XIRCOM(sc)) { 3675 /* 3676 * setup General Purpose Port mode and data so the tulip 3677 * can talk to the MII. 3678 */ 3679 CSR_WRITE_4(sc, DC_SIAGP, DC_SIAGP_WRITE_EN | DC_SIAGP_INT1_EN | 3680 DC_SIAGP_MD_GP2_OUTPUT | DC_SIAGP_MD_GP0_OUTPUT); 3681 DELAY(10); 3682 CSR_WRITE_4(sc, DC_SIAGP, DC_SIAGP_INT1_EN | 3683 DC_SIAGP_MD_GP2_OUTPUT | DC_SIAGP_MD_GP0_OUTPUT); 3684 DELAY(10); 3685 } 3686 3687 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_TX_THRESH); 3688 DC_SETBIT(sc, DC_NETCFG, DC_TXTHRESH_MIN); 3689 3690 /* Init circular RX list. */ 3691 if (dc_list_rx_init(sc) == ENOBUFS) { 3692 device_printf(sc->dc_dev, 3693 "initialization failed: no memory for rx buffers\n"); 3694 dc_stop(sc); 3695 return; 3696 } 3697 3698 /* 3699 * Init TX descriptors. 3700 */ 3701 dc_list_tx_init(sc); 3702 3703 /* 3704 * Load the address of the RX list. 3705 */ 3706 CSR_WRITE_4(sc, DC_RXADDR, DC_RXDESC(sc, 0)); 3707 CSR_WRITE_4(sc, DC_TXADDR, DC_TXDESC(sc, 0)); 3708 3709 /* 3710 * Enable interrupts. 3711 */ 3712 #ifdef DEVICE_POLLING 3713 /* 3714 * ... but only if we are not polling, and make sure they are off in 3715 * the case of polling. Some cards (e.g. fxp) turn interrupts on 3716 * after a reset. 3717 */ 3718 if (if_getcapenable(ifp) & IFCAP_POLLING) 3719 CSR_WRITE_4(sc, DC_IMR, 0x00000000); 3720 else 3721 #endif 3722 CSR_WRITE_4(sc, DC_IMR, DC_INTRS); 3723 CSR_WRITE_4(sc, DC_ISR, 0xFFFFFFFF); 3724 3725 /* Initialize TX jabber and RX watchdog timer. */ 3726 if (DC_IS_ULI(sc)) 3727 CSR_WRITE_4(sc, DC_WATCHDOG, DC_WDOG_JABBERCLK | 3728 DC_WDOG_HOSTUNJAB); 3729 3730 /* Enable transmitter. */ 3731 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_TX_ON); 3732 3733 /* 3734 * If this is an Intel 21143 and we're not using the 3735 * MII port, program the LED control pins so we get 3736 * link and activity indications. 3737 */ 3738 if (sc->dc_flags & DC_TULIP_LEDS) { 3739 CSR_WRITE_4(sc, DC_WATCHDOG, 3740 DC_WDOG_CTLWREN | DC_WDOG_LINK | DC_WDOG_ACTIVITY); 3741 CSR_WRITE_4(sc, DC_WATCHDOG, 0); 3742 } 3743 3744 /* 3745 * Load the RX/multicast filter. We do this sort of late 3746 * because the filter programming scheme on the 21143 and 3747 * some clones requires DMAing a setup frame via the TX 3748 * engine, and we need the transmitter enabled for that. 3749 */ 3750 dc_setfilt(sc); 3751 3752 /* Enable receiver. */ 3753 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_ON); 3754 CSR_WRITE_4(sc, DC_RXSTART, 0xFFFFFFFF); 3755 3756 if_setdrvflagbits(ifp, IFF_DRV_RUNNING, 0); 3757 if_setdrvflagbits(ifp, 0, IFF_DRV_OACTIVE); 3758 3759 dc_ifmedia_upd_locked(sc); 3760 3761 /* Clear missed frames and overflow counter. */ 3762 CSR_READ_4(sc, DC_FRAMESDISCARDED); 3763 3764 /* Don't start the ticker if this is a homePNA link. */ 3765 if (IFM_SUBTYPE(mii->mii_media.ifm_media) == IFM_HPNA_1) 3766 sc->dc_link = 1; 3767 else { 3768 if (sc->dc_flags & DC_21143_NWAY) 3769 callout_reset(&sc->dc_stat_ch, hz/10, dc_tick, sc); 3770 else 3771 callout_reset(&sc->dc_stat_ch, hz, dc_tick, sc); 3772 } 3773 3774 sc->dc_wdog_timer = 0; 3775 callout_reset(&sc->dc_wdog_ch, hz, dc_watchdog, sc); 3776 } 3777 3778 /* 3779 * Set media options. 3780 */ 3781 static int 3782 dc_ifmedia_upd(if_t ifp) 3783 { 3784 struct dc_softc *sc; 3785 int error; 3786 3787 sc = if_getsoftc(ifp); 3788 DC_LOCK(sc); 3789 error = dc_ifmedia_upd_locked(sc); 3790 DC_UNLOCK(sc); 3791 return (error); 3792 } 3793 3794 static int 3795 dc_ifmedia_upd_locked(struct dc_softc *sc) 3796 { 3797 struct mii_data *mii; 3798 struct ifmedia *ifm; 3799 int error; 3800 3801 DC_LOCK_ASSERT(sc); 3802 3803 sc->dc_link = 0; 3804 mii = device_get_softc(sc->dc_miibus); 3805 error = mii_mediachg(mii); 3806 if (error == 0) { 3807 ifm = &mii->mii_media; 3808 if (DC_IS_INTEL(sc)) 3809 dc_setcfg(sc, ifm->ifm_media); 3810 else if (DC_IS_DAVICOM(sc) && 3811 IFM_SUBTYPE(ifm->ifm_media) == IFM_HPNA_1) 3812 dc_setcfg(sc, ifm->ifm_media); 3813 } 3814 3815 return (error); 3816 } 3817 3818 /* 3819 * Report current media status. 3820 */ 3821 static void 3822 dc_ifmedia_sts(if_t ifp, struct ifmediareq *ifmr) 3823 { 3824 struct dc_softc *sc; 3825 struct mii_data *mii; 3826 struct ifmedia *ifm; 3827 3828 sc = if_getsoftc(ifp); 3829 mii = device_get_softc(sc->dc_miibus); 3830 DC_LOCK(sc); 3831 mii_pollstat(mii); 3832 ifm = &mii->mii_media; 3833 if (DC_IS_DAVICOM(sc)) { 3834 if (IFM_SUBTYPE(ifm->ifm_media) == IFM_HPNA_1) { 3835 ifmr->ifm_active = ifm->ifm_media; 3836 ifmr->ifm_status = 0; 3837 DC_UNLOCK(sc); 3838 return; 3839 } 3840 } 3841 ifmr->ifm_active = mii->mii_media_active; 3842 ifmr->ifm_status = mii->mii_media_status; 3843 DC_UNLOCK(sc); 3844 } 3845 3846 static int 3847 dc_ioctl(if_t ifp, u_long command, caddr_t data) 3848 { 3849 struct dc_softc *sc = if_getsoftc(ifp); 3850 struct ifreq *ifr = (struct ifreq *)data; 3851 struct mii_data *mii; 3852 int error = 0; 3853 3854 switch (command) { 3855 case SIOCSIFFLAGS: 3856 DC_LOCK(sc); 3857 if (if_getflags(ifp) & IFF_UP) { 3858 int need_setfilt = (if_getflags(ifp) ^ sc->dc_if_flags) & 3859 (IFF_PROMISC | IFF_ALLMULTI); 3860 3861 if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) { 3862 if (need_setfilt) 3863 dc_setfilt(sc); 3864 } else { 3865 if_setdrvflagbits(ifp, 0, IFF_DRV_RUNNING); 3866 dc_init_locked(sc); 3867 } 3868 } else { 3869 if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) 3870 dc_stop(sc); 3871 } 3872 sc->dc_if_flags = if_getflags(ifp); 3873 DC_UNLOCK(sc); 3874 break; 3875 case SIOCADDMULTI: 3876 case SIOCDELMULTI: 3877 DC_LOCK(sc); 3878 if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) 3879 dc_setfilt(sc); 3880 DC_UNLOCK(sc); 3881 break; 3882 case SIOCGIFMEDIA: 3883 case SIOCSIFMEDIA: 3884 mii = device_get_softc(sc->dc_miibus); 3885 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 3886 break; 3887 case SIOCSIFCAP: 3888 #ifdef DEVICE_POLLING 3889 if (ifr->ifr_reqcap & IFCAP_POLLING && 3890 !(if_getcapenable(ifp) & IFCAP_POLLING)) { 3891 error = ether_poll_register(dc_poll, ifp); 3892 if (error) 3893 return(error); 3894 DC_LOCK(sc); 3895 /* Disable interrupts */ 3896 CSR_WRITE_4(sc, DC_IMR, 0x00000000); 3897 if_setcapenablebit(ifp, IFCAP_POLLING, 0); 3898 DC_UNLOCK(sc); 3899 return (error); 3900 } 3901 if (!(ifr->ifr_reqcap & IFCAP_POLLING) && 3902 if_getcapenable(ifp) & IFCAP_POLLING) { 3903 error = ether_poll_deregister(ifp); 3904 /* Enable interrupts. */ 3905 DC_LOCK(sc); 3906 CSR_WRITE_4(sc, DC_IMR, DC_INTRS); 3907 if_setcapenablebit(ifp, 0, IFCAP_POLLING); 3908 DC_UNLOCK(sc); 3909 return (error); 3910 } 3911 #endif /* DEVICE_POLLING */ 3912 break; 3913 default: 3914 error = ether_ioctl(ifp, command, data); 3915 break; 3916 } 3917 3918 return (error); 3919 } 3920 3921 static void 3922 dc_watchdog(void *xsc) 3923 { 3924 struct dc_softc *sc = xsc; 3925 if_t ifp; 3926 3927 DC_LOCK_ASSERT(sc); 3928 3929 if (sc->dc_wdog_timer == 0 || --sc->dc_wdog_timer != 0) { 3930 callout_reset(&sc->dc_wdog_ch, hz, dc_watchdog, sc); 3931 return; 3932 } 3933 3934 ifp = sc->dc_ifp; 3935 if_inc_counter(ifp, IFCOUNTER_OERRORS, 1); 3936 device_printf(sc->dc_dev, "watchdog timeout\n"); 3937 3938 if_setdrvflagbits(ifp, 0, IFF_DRV_RUNNING); 3939 dc_init_locked(sc); 3940 3941 if (!if_sendq_empty(ifp)) 3942 dc_start_locked(ifp); 3943 } 3944 3945 /* 3946 * Stop the adapter and free any mbufs allocated to the 3947 * RX and TX lists. 3948 */ 3949 static void 3950 dc_stop(struct dc_softc *sc) 3951 { 3952 if_t ifp; 3953 struct dc_list_data *ld; 3954 struct dc_chain_data *cd; 3955 int i; 3956 uint32_t ctl, netcfg; 3957 3958 DC_LOCK_ASSERT(sc); 3959 3960 ifp = sc->dc_ifp; 3961 ld = &sc->dc_ldata; 3962 cd = &sc->dc_cdata; 3963 3964 callout_stop(&sc->dc_stat_ch); 3965 callout_stop(&sc->dc_wdog_ch); 3966 sc->dc_wdog_timer = 0; 3967 sc->dc_link = 0; 3968 3969 if_setdrvflagbits(ifp, 0, (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)); 3970 3971 netcfg = CSR_READ_4(sc, DC_NETCFG); 3972 if (netcfg & (DC_NETCFG_RX_ON | DC_NETCFG_TX_ON)) 3973 CSR_WRITE_4(sc, DC_NETCFG, 3974 netcfg & ~(DC_NETCFG_RX_ON | DC_NETCFG_TX_ON)); 3975 CSR_WRITE_4(sc, DC_IMR, 0x00000000); 3976 /* Wait the completion of TX/RX SM. */ 3977 if (netcfg & (DC_NETCFG_RX_ON | DC_NETCFG_TX_ON)) 3978 dc_netcfg_wait(sc); 3979 3980 CSR_WRITE_4(sc, DC_TXADDR, 0x00000000); 3981 CSR_WRITE_4(sc, DC_RXADDR, 0x00000000); 3982 3983 /* 3984 * Free data in the RX lists. 3985 */ 3986 for (i = 0; i < DC_RX_LIST_CNT; i++) { 3987 if (cd->dc_rx_chain[i] != NULL) { 3988 bus_dmamap_sync(sc->dc_rx_mtag, 3989 cd->dc_rx_map[i], BUS_DMASYNC_POSTREAD); 3990 bus_dmamap_unload(sc->dc_rx_mtag, 3991 cd->dc_rx_map[i]); 3992 m_freem(cd->dc_rx_chain[i]); 3993 cd->dc_rx_chain[i] = NULL; 3994 } 3995 } 3996 bzero(ld->dc_rx_list, DC_RX_LIST_SZ); 3997 bus_dmamap_sync(sc->dc_rx_ltag, sc->dc_rx_lmap, 3998 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 3999 4000 /* 4001 * Free the TX list buffers. 4002 */ 4003 for (i = 0; i < DC_TX_LIST_CNT; i++) { 4004 if (cd->dc_tx_chain[i] != NULL) { 4005 ctl = le32toh(ld->dc_tx_list[i].dc_ctl); 4006 if (ctl & DC_TXCTL_SETUP) { 4007 bus_dmamap_sync(sc->dc_stag, sc->dc_smap, 4008 BUS_DMASYNC_POSTWRITE); 4009 } else { 4010 bus_dmamap_sync(sc->dc_tx_mtag, 4011 cd->dc_tx_map[i], BUS_DMASYNC_POSTWRITE); 4012 bus_dmamap_unload(sc->dc_tx_mtag, 4013 cd->dc_tx_map[i]); 4014 m_freem(cd->dc_tx_chain[i]); 4015 } 4016 cd->dc_tx_chain[i] = NULL; 4017 } 4018 } 4019 bzero(ld->dc_tx_list, DC_TX_LIST_SZ); 4020 bus_dmamap_sync(sc->dc_tx_ltag, sc->dc_tx_lmap, 4021 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 4022 } 4023 4024 /* 4025 * Device suspend routine. Stop the interface and save some PCI 4026 * settings in case the BIOS doesn't restore them properly on 4027 * resume. 4028 */ 4029 static int 4030 dc_suspend(device_t dev) 4031 { 4032 struct dc_softc *sc; 4033 4034 sc = device_get_softc(dev); 4035 DC_LOCK(sc); 4036 dc_stop(sc); 4037 sc->suspended = 1; 4038 DC_UNLOCK(sc); 4039 4040 return (0); 4041 } 4042 4043 /* 4044 * Device resume routine. Restore some PCI settings in case the BIOS 4045 * doesn't, re-enable busmastering, and restart the interface if 4046 * appropriate. 4047 */ 4048 static int 4049 dc_resume(device_t dev) 4050 { 4051 struct dc_softc *sc; 4052 if_t ifp; 4053 4054 sc = device_get_softc(dev); 4055 ifp = sc->dc_ifp; 4056 4057 /* reinitialize interface if necessary */ 4058 DC_LOCK(sc); 4059 if (if_getflags(ifp) & IFF_UP) 4060 dc_init_locked(sc); 4061 4062 sc->suspended = 0; 4063 DC_UNLOCK(sc); 4064 4065 return (0); 4066 } 4067 4068 /* 4069 * Stop all chip I/O so that the kernel's probe routines don't 4070 * get confused by errant DMAs when rebooting. 4071 */ 4072 static int 4073 dc_shutdown(device_t dev) 4074 { 4075 struct dc_softc *sc; 4076 4077 sc = device_get_softc(dev); 4078 4079 DC_LOCK(sc); 4080 dc_stop(sc); 4081 DC_UNLOCK(sc); 4082 4083 return (0); 4084 } 4085 4086 static int 4087 dc_check_multiport(struct dc_softc *sc) 4088 { 4089 struct dc_softc *dsc; 4090 devclass_t dc; 4091 device_t child; 4092 uint8_t *eaddr; 4093 int unit; 4094 4095 dc = devclass_find("dc"); 4096 for (unit = 0; unit < devclass_get_maxunit(dc); unit++) { 4097 child = devclass_get_device(dc, unit); 4098 if (child == NULL) 4099 continue; 4100 if (child == sc->dc_dev) 4101 continue; 4102 if (device_get_parent(child) != device_get_parent(sc->dc_dev)) 4103 continue; 4104 if (unit > device_get_unit(sc->dc_dev)) 4105 continue; 4106 if (device_is_attached(child) == 0) 4107 continue; 4108 dsc = device_get_softc(child); 4109 device_printf(sc->dc_dev, 4110 "Using station address of %s as base\n", 4111 device_get_nameunit(child)); 4112 bcopy(dsc->dc_eaddr, sc->dc_eaddr, ETHER_ADDR_LEN); 4113 eaddr = (uint8_t *)sc->dc_eaddr; 4114 eaddr[5]++; 4115 /* Prepare SROM to parse again. */ 4116 if (DC_IS_INTEL(sc) && dsc->dc_srom != NULL && 4117 sc->dc_romwidth != 0) { 4118 free(sc->dc_srom, M_DEVBUF); 4119 sc->dc_romwidth = dsc->dc_romwidth; 4120 sc->dc_srom = malloc(DC_ROM_SIZE(sc->dc_romwidth), 4121 M_DEVBUF, M_NOWAIT); 4122 if (sc->dc_srom == NULL) { 4123 device_printf(sc->dc_dev, 4124 "Could not allocate SROM buffer\n"); 4125 return (ENOMEM); 4126 } 4127 bcopy(dsc->dc_srom, sc->dc_srom, 4128 DC_ROM_SIZE(sc->dc_romwidth)); 4129 } 4130 return (0); 4131 } 4132 return (ENOENT); 4133 } 4134