1 /* 2 * Copyright (c) 1997, 1998, 1999 3 * Bill Paul <wpaul@ee.columbia.edu>. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 3. All advertising materials mentioning features or use of this software 14 * must display the following acknowledgement: 15 * This product includes software developed by Bill Paul. 16 * 4. Neither the name of the author nor the names of any co-contributors 17 * may be used to endorse or promote products derived from this software 18 * without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30 * THE POSSIBILITY OF SUCH DAMAGE. 31 * 32 * $FreeBSD$ 33 */ 34 35 /* 36 * DEC "tulip" clone ethernet driver. Supports the DEC/Intel 21143 37 * series chips and several workalikes including the following: 38 * 39 * Macronix 98713/98715/98725 PMAC (www.macronix.com) 40 * Macronix/Lite-On 82c115 PNIC II (www.macronix.com) 41 * Lite-On 82c168/82c169 PNIC (www.litecom.com) 42 * ASIX Electronics AX88140A (www.asix.com.tw) 43 * ASIX Electronics AX88141 (www.asix.com.tw) 44 * ADMtek AL981 (www.admtek.com.tw) 45 * ADMtek AN985 (www.admtek.com.tw) 46 * Davicom DM9100, DM9102, DM9102A (www.davicom8.com) 47 * 48 * Datasheets for the 21143 are available at developer.intel.com. 49 * Datasheets for the clone parts can be found at their respective sites. 50 * (Except for the PNIC; see www.freebsd.org/~wpaul/PNIC/pnic.ps.gz.) 51 * The PNIC II is essentially a Macronix 98715A chip; the only difference 52 * worth noting is that its multicast hash table is only 128 bits wide 53 * instead of 512. 54 * 55 * Written by Bill Paul <wpaul@ee.columbia.edu> 56 * Electrical Engineering Department 57 * Columbia University, New York City 58 */ 59 60 /* 61 * The Intel 21143 is the successor to the DEC 21140. It is basically 62 * the same as the 21140 but with a few new features. The 21143 supports 63 * three kinds of media attachments: 64 * 65 * o MII port, for 10Mbps and 100Mbps support and NWAY 66 * autonegotiation provided by an external PHY. 67 * o SYM port, for symbol mode 100Mbps support. 68 * o 10baseT port. 69 * o AUI/BNC port. 70 * 71 * The 100Mbps SYM port and 10baseT port can be used together in 72 * combination with the internal NWAY support to create a 10/100 73 * autosensing configuration. 74 * 75 * Knowing which media is available on a given card is tough: you're 76 * supposed to go slogging through the EEPROM looking for media 77 * description structures. Unfortunately, some card vendors that use 78 * the 21143 don't obey the DEC SROM spec correctly, which means that 79 * what you find in the EEPROM may not agree with reality. Fortunately, 80 * the 21143 provides us a way to get around this issue: lurking in 81 * PCI configuration space is the Configuration Wake-Up Command Register. 82 * This register is loaded with a value from the EEPROM when wake on LAN 83 * mode is enabled; this value tells us quite clearly what kind of media 84 * is attached to the NIC. The main purpose of this register is to tell 85 * the NIC what media to scan when in wake on LAN mode, however by 86 * forcibly enabling wake on LAN mode, we can use to learn what kind of 87 * media a given NIC has available and adapt ourselves accordingly. 88 * 89 * Of course, if the media description blocks in the EEPROM are bogus. 90 * what are the odds that the CWUC aren't bogus as well, right? Well, 91 * the CWUC value is more likely to be correct since wake on LAN mode 92 * won't work correctly without it, and wake on LAN is a big selling 93 * point these days. It's also harder to screw up a single byte than 94 * a whole media descriptor block. 95 * 96 * Note that not all tulip workalikes are handled in this driver: we only 97 * deal with those which are relatively well behaved. The Winbond is 98 * handled separately due to its different register offsets and the 99 * special handling needed for its various bugs. The PNIC is handled 100 * here, but I'm not thrilled about it. 101 * 102 * All of the workalike chips use some form of MII transceiver support 103 * with the exception of the Macronix chips, which also have a SYM port. 104 * The ASIX AX88140A is also documented to have a SYM port, but all 105 * the cards I've seen use an MII transceiver, probably because the 106 * AX88140A doesn't support internal NWAY. 107 */ 108 109 #include <sys/param.h> 110 #include <sys/systm.h> 111 #include <sys/sockio.h> 112 #include <sys/mbuf.h> 113 #include <sys/malloc.h> 114 #include <sys/kernel.h> 115 #include <sys/socket.h> 116 117 #include <net/if.h> 118 #include <net/if_arp.h> 119 #include <net/ethernet.h> 120 #include <net/if_dl.h> 121 #include <net/if_media.h> 122 123 #include <net/bpf.h> 124 125 #include <vm/vm.h> /* for vtophys */ 126 #include <vm/pmap.h> /* for vtophys */ 127 #include <machine/clock.h> /* for DELAY */ 128 #include <machine/bus_pio.h> 129 #include <machine/bus_memio.h> 130 #include <machine/bus.h> 131 #include <machine/resource.h> 132 #include <sys/bus.h> 133 #include <sys/rman.h> 134 135 #include <dev/mii/mii.h> 136 #include <dev/mii/miivar.h> 137 138 #include <pci/pcireg.h> 139 #include <pci/pcivar.h> 140 141 #define DC_USEIOSPACE 142 143 #include <pci/if_dcreg.h> 144 145 /* "controller miibus0" required. See GENERIC if you get errors here. */ 146 #include "miibus_if.h" 147 148 #ifndef lint 149 static const char rcsid[] = 150 "$FreeBSD$"; 151 #endif 152 153 /* 154 * Various supported device vendors/types and their names. 155 */ 156 static struct dc_type dc_devs[] = { 157 { DC_VENDORID_DEC, DC_DEVICEID_21143, 158 "Intel 21143 10/100BaseTX" }, 159 { DC_VENDORID_DAVICOM, DC_DEVICEID_DM9100, 160 "Davicom DM9100 10/100BaseTX" }, 161 { DC_VENDORID_DAVICOM, DC_DEVICEID_DM9102, 162 "Davicom DM9102 10/100BaseTX" }, 163 { DC_VENDORID_DAVICOM, DC_DEVICEID_DM9102, 164 "Davicom DM9102A 10/100BaseTX" }, 165 { DC_VENDORID_ADMTEK, DC_DEVICEID_AL981, 166 "ADMtek AL981 10/100BaseTX" }, 167 { DC_VENDORID_ADMTEK, DC_DEVICEID_AN985, 168 "ADMtek AN985 10/100BaseTX" }, 169 { DC_VENDORID_ASIX, DC_DEVICEID_AX88140A, 170 "ASIX AX88140A 10/100BaseTX" }, 171 { DC_VENDORID_ASIX, DC_DEVICEID_AX88140A, 172 "ASIX AX88141 10/100BaseTX" }, 173 { DC_VENDORID_MX, DC_DEVICEID_98713, 174 "Macronix 98713 10/100BaseTX" }, 175 { DC_VENDORID_MX, DC_DEVICEID_98713, 176 "Macronix 98713A 10/100BaseTX" }, 177 { DC_VENDORID_CP, DC_DEVICEID_98713_CP, 178 "Compex RL100-TX 10/100BaseTX" }, 179 { DC_VENDORID_CP, DC_DEVICEID_98713_CP, 180 "Compex RL100-TX 10/100BaseTX" }, 181 { DC_VENDORID_MX, DC_DEVICEID_987x5, 182 "Macronix 98715/98715A 10/100BaseTX" }, 183 { DC_VENDORID_MX, DC_DEVICEID_987x5, 184 "Macronix 98725 10/100BaseTX" }, 185 { DC_VENDORID_LO, DC_DEVICEID_82C115, 186 "LC82C115 PNIC II 10/100BaseTX" }, 187 { DC_VENDORID_LO, DC_DEVICEID_82C168, 188 "82c168 PNIC 10/100BaseTX" }, 189 { DC_VENDORID_LO, DC_DEVICEID_82C168, 190 "82c169 PNIC 10/100BaseTX" }, 191 { 0, 0, NULL } 192 }; 193 194 static int dc_probe __P((device_t)); 195 static int dc_attach __P((device_t)); 196 static int dc_detach __P((device_t)); 197 static void dc_acpi __P((device_t)); 198 static struct dc_type *dc_devtype __P((device_t)); 199 static int dc_newbuf __P((struct dc_softc *, int, struct mbuf *)); 200 static int dc_encap __P((struct dc_softc *, struct mbuf *, 201 u_int32_t *)); 202 static int dc_coal __P((struct dc_softc *, struct mbuf **)); 203 static void dc_pnic_rx_bug_war __P((struct dc_softc *, int)); 204 static int dc_rx_resync __P((struct dc_softc *)); 205 static void dc_rxeof __P((struct dc_softc *)); 206 static void dc_txeof __P((struct dc_softc *)); 207 static void dc_tick __P((void *)); 208 static void dc_intr __P((void *)); 209 static void dc_start __P((struct ifnet *)); 210 static int dc_ioctl __P((struct ifnet *, u_long, caddr_t)); 211 static void dc_init __P((void *)); 212 static void dc_stop __P((struct dc_softc *)); 213 static void dc_watchdog __P((struct ifnet *)); 214 static void dc_shutdown __P((device_t)); 215 static int dc_ifmedia_upd __P((struct ifnet *)); 216 static void dc_ifmedia_sts __P((struct ifnet *, struct ifmediareq *)); 217 218 static void dc_delay __P((struct dc_softc *)); 219 static void dc_eeprom_idle __P((struct dc_softc *)); 220 static void dc_eeprom_putbyte __P((struct dc_softc *, int)); 221 static void dc_eeprom_getword __P((struct dc_softc *, int, u_int16_t *)); 222 static void dc_eeprom_getword_pnic 223 __P((struct dc_softc *, int, u_int16_t *)); 224 static void dc_read_eeprom __P((struct dc_softc *, caddr_t, int, 225 int, int)); 226 227 static void dc_mii_writebit __P((struct dc_softc *, int)); 228 static int dc_mii_readbit __P((struct dc_softc *)); 229 static void dc_mii_sync __P((struct dc_softc *)); 230 static void dc_mii_send __P((struct dc_softc *, u_int32_t, int)); 231 static int dc_mii_readreg __P((struct dc_softc *, struct dc_mii_frame *)); 232 static int dc_mii_writereg __P((struct dc_softc *, struct dc_mii_frame *)); 233 static int dc_miibus_readreg __P((device_t, int, int)); 234 static int dc_miibus_writereg __P((device_t, int, int, int)); 235 static void dc_miibus_statchg __P((device_t)); 236 static void dc_miibus_mediainit __P((device_t)); 237 238 static void dc_setcfg __P((struct dc_softc *, int)); 239 static u_int32_t dc_crc_le __P((struct dc_softc *, caddr_t)); 240 static u_int32_t dc_crc_be __P((caddr_t)); 241 static void dc_setfilt_21143 __P((struct dc_softc *)); 242 static void dc_setfilt_asix __P((struct dc_softc *)); 243 static void dc_setfilt_admtek __P((struct dc_softc *)); 244 245 static void dc_setfilt __P((struct dc_softc *)); 246 247 static void dc_reset __P((struct dc_softc *)); 248 static int dc_list_rx_init __P((struct dc_softc *)); 249 static int dc_list_tx_init __P((struct dc_softc *)); 250 251 #ifdef DC_USEIOSPACE 252 #define DC_RES SYS_RES_IOPORT 253 #define DC_RID DC_PCI_CFBIO 254 #else 255 #define DC_RES SYS_RES_MEMORY 256 #define DC_RID DC_PCI_CFBMA 257 #endif 258 259 static device_method_t dc_methods[] = { 260 /* Device interface */ 261 DEVMETHOD(device_probe, dc_probe), 262 DEVMETHOD(device_attach, dc_attach), 263 DEVMETHOD(device_detach, dc_detach), 264 DEVMETHOD(device_shutdown, dc_shutdown), 265 266 /* bus interface */ 267 DEVMETHOD(bus_print_child, bus_generic_print_child), 268 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 269 270 /* MII interface */ 271 DEVMETHOD(miibus_readreg, dc_miibus_readreg), 272 DEVMETHOD(miibus_writereg, dc_miibus_writereg), 273 DEVMETHOD(miibus_statchg, dc_miibus_statchg), 274 DEVMETHOD(miibus_mediainit, dc_miibus_mediainit), 275 276 { 0, 0 } 277 }; 278 279 static driver_t dc_driver = { 280 "dc", 281 dc_methods, 282 sizeof(struct dc_softc) 283 }; 284 285 static devclass_t dc_devclass; 286 287 DRIVER_MODULE(if_dc, pci, dc_driver, dc_devclass, 0, 0); 288 DRIVER_MODULE(miibus, dc, miibus_driver, miibus_devclass, 0, 0); 289 290 #define DC_SETBIT(sc, reg, x) \ 291 CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) | (x)) 292 293 #define DC_CLRBIT(sc, reg, x) \ 294 CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) & ~(x)) 295 296 #define SIO_SET(x) DC_SETBIT(sc, DC_SIO, (x)) 297 #define SIO_CLR(x) DC_CLRBIT(sc, DC_SIO, (x)) 298 299 static void dc_delay(sc) 300 struct dc_softc *sc; 301 { 302 int idx; 303 304 for (idx = (300 / 33) + 1; idx > 0; idx--) 305 CSR_READ_4(sc, DC_BUSCTL); 306 } 307 308 static void dc_eeprom_idle(sc) 309 struct dc_softc *sc; 310 { 311 register int i; 312 313 CSR_WRITE_4(sc, DC_SIO, DC_SIO_EESEL); 314 dc_delay(sc); 315 DC_SETBIT(sc, DC_SIO, DC_SIO_ROMCTL_READ); 316 dc_delay(sc); 317 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); 318 dc_delay(sc); 319 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CS); 320 dc_delay(sc); 321 322 for (i = 0; i < 25; i++) { 323 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); 324 dc_delay(sc); 325 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CLK); 326 dc_delay(sc); 327 } 328 329 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); 330 dc_delay(sc); 331 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CS); 332 dc_delay(sc); 333 CSR_WRITE_4(sc, DC_SIO, 0x00000000); 334 335 return; 336 } 337 338 /* 339 * Send a read command and address to the EEPROM, check for ACK. 340 */ 341 static void dc_eeprom_putbyte(sc, addr) 342 struct dc_softc *sc; 343 int addr; 344 { 345 register int d, i; 346 347 /* 348 * The AN985 has a 93C66 EEPROM on it instead of 349 * a 93C46. It uses a different bit sequence for 350 * specifying the "read" opcode. 351 */ 352 if (DC_IS_CENTAUR(sc)) 353 d = addr | (DC_EECMD_READ << 2); 354 else 355 d = addr | DC_EECMD_READ; 356 357 /* 358 * Feed in each bit and strobe the clock. 359 */ 360 for (i = 0x400; i; i >>= 1) { 361 if (d & i) { 362 SIO_SET(DC_SIO_EE_DATAIN); 363 } else { 364 SIO_CLR(DC_SIO_EE_DATAIN); 365 } 366 dc_delay(sc); 367 SIO_SET(DC_SIO_EE_CLK); 368 dc_delay(sc); 369 SIO_CLR(DC_SIO_EE_CLK); 370 dc_delay(sc); 371 } 372 373 return; 374 } 375 376 /* 377 * Read a word of data stored in the EEPROM at address 'addr.' 378 * The PNIC 82c168/82c169 has its own non-standard way to read 379 * the EEPROM. 380 */ 381 static void dc_eeprom_getword_pnic(sc, addr, dest) 382 struct dc_softc *sc; 383 int addr; 384 u_int16_t *dest; 385 { 386 register int i; 387 u_int32_t r; 388 389 CSR_WRITE_4(sc, DC_PN_SIOCTL, DC_PN_EEOPCODE_READ|addr); 390 391 for (i = 0; i < DC_TIMEOUT; i++) { 392 DELAY(1); 393 r = CSR_READ_4(sc, DC_SIO); 394 if (!(r & DC_PN_SIOCTL_BUSY)) { 395 *dest = (u_int16_t)(r & 0xFFFF); 396 return; 397 } 398 } 399 400 return; 401 } 402 403 /* 404 * Read a word of data stored in the EEPROM at address 'addr.' 405 */ 406 static void dc_eeprom_getword(sc, addr, dest) 407 struct dc_softc *sc; 408 int addr; 409 u_int16_t *dest; 410 { 411 register int i; 412 u_int16_t word = 0; 413 414 /* Force EEPROM to idle state. */ 415 dc_eeprom_idle(sc); 416 417 /* Enter EEPROM access mode. */ 418 CSR_WRITE_4(sc, DC_SIO, DC_SIO_EESEL); 419 dc_delay(sc); 420 DC_SETBIT(sc, DC_SIO, DC_SIO_ROMCTL_READ); 421 dc_delay(sc); 422 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); 423 dc_delay(sc); 424 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CS); 425 dc_delay(sc); 426 427 /* 428 * Send address of word we want to read. 429 */ 430 dc_eeprom_putbyte(sc, addr); 431 432 /* 433 * Start reading bits from EEPROM. 434 */ 435 for (i = 0x8000; i; i >>= 1) { 436 SIO_SET(DC_SIO_EE_CLK); 437 dc_delay(sc); 438 if (CSR_READ_4(sc, DC_SIO) & DC_SIO_EE_DATAOUT) 439 word |= i; 440 dc_delay(sc); 441 SIO_CLR(DC_SIO_EE_CLK); 442 dc_delay(sc); 443 } 444 445 /* Turn off EEPROM access mode. */ 446 dc_eeprom_idle(sc); 447 448 *dest = word; 449 450 return; 451 } 452 453 /* 454 * Read a sequence of words from the EEPROM. 455 */ 456 static void dc_read_eeprom(sc, dest, off, cnt, swap) 457 struct dc_softc *sc; 458 caddr_t dest; 459 int off; 460 int cnt; 461 int swap; 462 { 463 int i; 464 u_int16_t word = 0, *ptr; 465 466 for (i = 0; i < cnt; i++) { 467 if (DC_IS_PNIC(sc)) 468 dc_eeprom_getword_pnic(sc, off + i, &word); 469 else 470 dc_eeprom_getword(sc, off + i, &word); 471 ptr = (u_int16_t *)(dest + (i * 2)); 472 if (swap) 473 *ptr = ntohs(word); 474 else 475 *ptr = word; 476 } 477 478 return; 479 } 480 481 /* 482 * The following two routines are taken from the Macronix 98713 483 * Application Notes pp.19-21. 484 */ 485 /* 486 * Write a bit to the MII bus. 487 */ 488 static void dc_mii_writebit(sc, bit) 489 struct dc_softc *sc; 490 int bit; 491 { 492 if (bit) 493 CSR_WRITE_4(sc, DC_SIO, 494 DC_SIO_ROMCTL_WRITE|DC_SIO_MII_DATAOUT); 495 else 496 CSR_WRITE_4(sc, DC_SIO, DC_SIO_ROMCTL_WRITE); 497 498 DC_SETBIT(sc, DC_SIO, DC_SIO_MII_CLK); 499 DC_CLRBIT(sc, DC_SIO, DC_SIO_MII_CLK); 500 501 return; 502 } 503 504 /* 505 * Read a bit from the MII bus. 506 */ 507 static int dc_mii_readbit(sc) 508 struct dc_softc *sc; 509 { 510 CSR_WRITE_4(sc, DC_SIO, DC_SIO_ROMCTL_READ|DC_SIO_MII_DIR); 511 CSR_READ_4(sc, DC_SIO); 512 DC_SETBIT(sc, DC_SIO, DC_SIO_MII_CLK); 513 DC_CLRBIT(sc, DC_SIO, DC_SIO_MII_CLK); 514 if (CSR_READ_4(sc, DC_SIO) & DC_SIO_MII_DATAIN) 515 return(1); 516 517 return(0); 518 } 519 520 /* 521 * Sync the PHYs by setting data bit and strobing the clock 32 times. 522 */ 523 static void dc_mii_sync(sc) 524 struct dc_softc *sc; 525 { 526 register int i; 527 528 CSR_WRITE_4(sc, DC_SIO, DC_SIO_ROMCTL_WRITE); 529 530 for (i = 0; i < 32; i++) 531 dc_mii_writebit(sc, 1); 532 533 return; 534 } 535 536 /* 537 * Clock a series of bits through the MII. 538 */ 539 static void dc_mii_send(sc, bits, cnt) 540 struct dc_softc *sc; 541 u_int32_t bits; 542 int cnt; 543 { 544 int i; 545 546 for (i = (0x1 << (cnt - 1)); i; i >>= 1) 547 dc_mii_writebit(sc, bits & i); 548 } 549 550 /* 551 * Read an PHY register through the MII. 552 */ 553 static int dc_mii_readreg(sc, frame) 554 struct dc_softc *sc; 555 struct dc_mii_frame *frame; 556 557 { 558 int i, ack, s; 559 560 s = splimp(); 561 562 /* 563 * Set up frame for RX. 564 */ 565 frame->mii_stdelim = DC_MII_STARTDELIM; 566 frame->mii_opcode = DC_MII_READOP; 567 frame->mii_turnaround = 0; 568 frame->mii_data = 0; 569 570 /* 571 * Sync the PHYs. 572 */ 573 dc_mii_sync(sc); 574 575 /* 576 * Send command/address info. 577 */ 578 dc_mii_send(sc, frame->mii_stdelim, 2); 579 dc_mii_send(sc, frame->mii_opcode, 2); 580 dc_mii_send(sc, frame->mii_phyaddr, 5); 581 dc_mii_send(sc, frame->mii_regaddr, 5); 582 583 #ifdef notdef 584 /* Idle bit */ 585 dc_mii_writebit(sc, 1); 586 dc_mii_writebit(sc, 0); 587 #endif 588 589 /* Check for ack */ 590 ack = dc_mii_readbit(sc); 591 592 /* 593 * Now try reading data bits. If the ack failed, we still 594 * need to clock through 16 cycles to keep the PHY(s) in sync. 595 */ 596 if (ack) { 597 for(i = 0; i < 16; i++) { 598 dc_mii_readbit(sc); 599 } 600 goto fail; 601 } 602 603 for (i = 0x8000; i; i >>= 1) { 604 if (!ack) { 605 if (dc_mii_readbit(sc)) 606 frame->mii_data |= i; 607 } 608 } 609 610 fail: 611 612 dc_mii_writebit(sc, 0); 613 dc_mii_writebit(sc, 0); 614 615 splx(s); 616 617 if (ack) 618 return(1); 619 return(0); 620 } 621 622 /* 623 * Write to a PHY register through the MII. 624 */ 625 static int dc_mii_writereg(sc, frame) 626 struct dc_softc *sc; 627 struct dc_mii_frame *frame; 628 629 { 630 int s; 631 632 s = splimp(); 633 /* 634 * Set up frame for TX. 635 */ 636 637 frame->mii_stdelim = DC_MII_STARTDELIM; 638 frame->mii_opcode = DC_MII_WRITEOP; 639 frame->mii_turnaround = DC_MII_TURNAROUND; 640 641 /* 642 * Sync the PHYs. 643 */ 644 dc_mii_sync(sc); 645 646 dc_mii_send(sc, frame->mii_stdelim, 2); 647 dc_mii_send(sc, frame->mii_opcode, 2); 648 dc_mii_send(sc, frame->mii_phyaddr, 5); 649 dc_mii_send(sc, frame->mii_regaddr, 5); 650 dc_mii_send(sc, frame->mii_turnaround, 2); 651 dc_mii_send(sc, frame->mii_data, 16); 652 653 /* Idle bit. */ 654 dc_mii_writebit(sc, 0); 655 dc_mii_writebit(sc, 0); 656 657 splx(s); 658 659 return(0); 660 } 661 662 static int dc_miibus_readreg(dev, phy, reg) 663 device_t dev; 664 int phy, reg; 665 { 666 struct dc_mii_frame frame; 667 struct dc_softc *sc; 668 int i, rval, phy_reg; 669 670 sc = device_get_softc(dev); 671 bzero((char *)&frame, sizeof(frame)); 672 673 /* 674 * Note: both the AL981 and AN985 have internal PHYs, 675 * however the AL981 provides direct access to the PHY 676 * registers while the AN985 uses a serial MII interface. 677 * The AN985's MII interface is also buggy in that you 678 * can read from any MII address (0 to 31), but only address 1 679 * behaves normally. To deal with both cases, we pretend 680 * that the PHY is at MII address 1. 681 */ 682 if (DC_IS_ADMTEK(sc) && phy != DC_ADMTEK_PHYADDR) 683 return(0); 684 685 if (sc->dc_pmode == DC_PMODE_SYM) { 686 if (phy == (MII_NPHY - 1)) { 687 switch(reg) { 688 case MII_BMSR: 689 /* 690 * Fake something to make the probe 691 * code think there's a PHY here. 692 */ 693 return(BMSR_MEDIAMASK); 694 break; 695 case MII_PHYIDR1: 696 if (DC_IS_PNIC(sc)) 697 return(DC_VENDORID_LO); 698 return(DC_VENDORID_DEC); 699 break; 700 case MII_PHYIDR2: 701 if (DC_IS_PNIC(sc)) 702 return(DC_DEVICEID_82C168); 703 return(DC_DEVICEID_21143); 704 break; 705 default: 706 return(0); 707 break; 708 } 709 } else 710 return(0); 711 } 712 713 if (DC_IS_PNIC(sc)) { 714 CSR_WRITE_4(sc, DC_PN_MII, DC_PN_MIIOPCODE_READ | 715 (phy << 23) | (reg << 18)); 716 for (i = 0; i < DC_TIMEOUT; i++) { 717 DELAY(1); 718 rval = CSR_READ_4(sc, DC_PN_MII); 719 if (!(rval & DC_PN_MII_BUSY)) { 720 rval &= 0xFFFF; 721 return(rval == 0xFFFF ? 0 : rval); 722 } 723 } 724 return(0); 725 } 726 727 if (DC_IS_COMET(sc)) { 728 switch(reg) { 729 case MII_BMCR: 730 phy_reg = DC_AL_BMCR; 731 break; 732 case MII_BMSR: 733 phy_reg = DC_AL_BMSR; 734 break; 735 case MII_PHYIDR1: 736 phy_reg = DC_AL_VENID; 737 break; 738 case MII_PHYIDR2: 739 phy_reg = DC_AL_DEVID; 740 break; 741 case MII_ANAR: 742 phy_reg = DC_AL_ANAR; 743 break; 744 case MII_ANLPAR: 745 phy_reg = DC_AL_LPAR; 746 break; 747 case MII_ANER: 748 phy_reg = DC_AL_ANER; 749 break; 750 default: 751 printf("dc%d: phy_read: bad phy register %x\n", 752 sc->dc_unit, reg); 753 return(0); 754 break; 755 } 756 757 rval = CSR_READ_4(sc, phy_reg) & 0x0000FFFF; 758 759 if (rval == 0xFFFF) 760 return(0); 761 return(rval); 762 } 763 764 frame.mii_phyaddr = phy; 765 frame.mii_regaddr = reg; 766 phy_reg = CSR_READ_4(sc, DC_NETCFG); 767 CSR_WRITE_4(sc, DC_NETCFG, phy_reg & ~DC_NETCFG_PORTSEL); 768 dc_mii_readreg(sc, &frame); 769 CSR_WRITE_4(sc, DC_NETCFG, phy_reg); 770 771 return(frame.mii_data); 772 } 773 774 static int dc_miibus_writereg(dev, phy, reg, data) 775 device_t dev; 776 int phy, reg, data; 777 { 778 struct dc_softc *sc; 779 struct dc_mii_frame frame; 780 int i, phy_reg; 781 782 sc = device_get_softc(dev); 783 bzero((char *)&frame, sizeof(frame)); 784 785 if (DC_IS_ADMTEK(sc) && phy != DC_ADMTEK_PHYADDR) 786 return(0); 787 788 if (DC_IS_PNIC(sc)) { 789 CSR_WRITE_4(sc, DC_PN_MII, DC_PN_MIIOPCODE_WRITE | 790 (phy << 23) | (reg << 10) | data); 791 for (i = 0; i < DC_TIMEOUT; i++) { 792 if (!(CSR_READ_4(sc, DC_PN_MII) & DC_PN_MII_BUSY)) 793 break; 794 } 795 return(0); 796 } 797 798 if (DC_IS_COMET(sc)) { 799 switch(reg) { 800 case MII_BMCR: 801 phy_reg = DC_AL_BMCR; 802 break; 803 case MII_BMSR: 804 phy_reg = DC_AL_BMSR; 805 break; 806 case MII_PHYIDR1: 807 phy_reg = DC_AL_VENID; 808 break; 809 case MII_PHYIDR2: 810 phy_reg = DC_AL_DEVID; 811 break; 812 case MII_ANAR: 813 phy_reg = DC_AL_ANAR; 814 break; 815 case MII_ANLPAR: 816 phy_reg = DC_AL_LPAR; 817 break; 818 case MII_ANER: 819 phy_reg = DC_AL_ANER; 820 break; 821 default: 822 printf("dc%d: phy_write: bad phy register %x\n", 823 sc->dc_unit, reg); 824 return(0); 825 break; 826 } 827 828 CSR_WRITE_4(sc, phy_reg, data); 829 return(0); 830 } 831 832 frame.mii_phyaddr = phy; 833 frame.mii_regaddr = reg; 834 frame.mii_data = data; 835 836 phy_reg = CSR_READ_4(sc, DC_NETCFG); 837 CSR_WRITE_4(sc, DC_NETCFG, phy_reg & ~DC_NETCFG_PORTSEL); 838 dc_mii_writereg(sc, &frame); 839 CSR_WRITE_4(sc, DC_NETCFG, phy_reg); 840 841 return(0); 842 } 843 844 static void dc_miibus_statchg(dev) 845 device_t dev; 846 { 847 struct dc_softc *sc; 848 struct mii_data *mii; 849 struct ifmedia *ifm; 850 851 sc = device_get_softc(dev); 852 if (DC_IS_ADMTEK(sc)) 853 return; 854 mii = device_get_softc(sc->dc_miibus); 855 ifm = &mii->mii_media; 856 if (DC_IS_DAVICOM(sc) && 857 IFM_SUBTYPE(ifm->ifm_media) == IFM_homePNA) { 858 dc_setcfg(sc, ifm->ifm_media); 859 sc->dc_if_media = ifm->ifm_media; 860 } else { 861 dc_setcfg(sc, mii->mii_media_active); 862 sc->dc_if_media = mii->mii_media_active; 863 } 864 865 return; 866 } 867 868 /* 869 * Special support for DM9102A cards with HomePNA PHYs. Note: 870 * with the Davicom DM9102A/DM9801 eval board that I have, it seems 871 * to be impossible to talk to the management interface of the DM9801 872 * PHY (its MDIO pin is not connected to anything). Consequently, 873 * the driver has to just 'know' about the additional mode and deal 874 * with it itself. *sigh* 875 */ 876 static void dc_miibus_mediainit(dev) 877 device_t dev; 878 { 879 struct dc_softc *sc; 880 struct mii_data *mii; 881 struct ifmedia *ifm; 882 int rev; 883 884 rev = pci_read_config(dev, DC_PCI_CFRV, 4) & 0xFF; 885 886 sc = device_get_softc(dev); 887 mii = device_get_softc(sc->dc_miibus); 888 ifm = &mii->mii_media; 889 890 if (DC_IS_DAVICOM(sc) && rev >= DC_REVISION_DM9102A) 891 ifmedia_add(ifm, IFM_ETHER|IFM_homePNA, 0, NULL); 892 893 return; 894 } 895 896 #define DC_POLY 0xEDB88320 897 #define DC_BITS 9 898 #define DC_BITS_PNIC_II 7 899 900 static u_int32_t dc_crc_le(sc, addr) 901 struct dc_softc *sc; 902 caddr_t addr; 903 { 904 u_int32_t idx, bit, data, crc; 905 906 /* Compute CRC for the address value. */ 907 crc = 0xFFFFFFFF; /* initial value */ 908 909 for (idx = 0; idx < 6; idx++) { 910 for (data = *addr++, bit = 0; bit < 8; bit++, data >>= 1) 911 crc = (crc >> 1) ^ (((crc ^ data) & 1) ? DC_POLY : 0); 912 } 913 914 /* The hash table on the PNIC II is only 128 bits wide. */ 915 if (DC_IS_PNICII(sc)) 916 return (crc & ((1 << DC_BITS_PNIC_II) - 1)); 917 918 return (crc & ((1 << DC_BITS) - 1)); 919 } 920 921 /* 922 * Calculate CRC of a multicast group address, return the lower 6 bits. 923 */ 924 static u_int32_t dc_crc_be(addr) 925 caddr_t addr; 926 { 927 u_int32_t crc, carry; 928 int i, j; 929 u_int8_t c; 930 931 /* Compute CRC for the address value. */ 932 crc = 0xFFFFFFFF; /* initial value */ 933 934 for (i = 0; i < 6; i++) { 935 c = *(addr + i); 936 for (j = 0; j < 8; j++) { 937 carry = ((crc & 0x80000000) ? 1 : 0) ^ (c & 0x01); 938 crc <<= 1; 939 c >>= 1; 940 if (carry) 941 crc = (crc ^ 0x04c11db6) | carry; 942 } 943 } 944 945 /* return the filter bit position */ 946 return((crc >> 26) & 0x0000003F); 947 } 948 949 /* 950 * 21143-style RX filter setup routine. Filter programming is done by 951 * downloading a special setup frame into the TX engine. 21143, Macronix, 952 * PNIC, PNIC II and Davicom chips are programmed this way. 953 * 954 * We always program the chip using 'hash perfect' mode, i.e. one perfect 955 * address (our node address) and a 512-bit hash filter for multicast 956 * frames. We also sneak the broadcast address into the hash filter since 957 * we need that too. 958 */ 959 void dc_setfilt_21143(sc) 960 struct dc_softc *sc; 961 { 962 struct dc_desc *sframe; 963 u_int32_t h, *sp; 964 struct ifmultiaddr *ifma; 965 struct ifnet *ifp; 966 int i; 967 968 ifp = &sc->arpcom.ac_if; 969 970 i = sc->dc_cdata.dc_tx_prod; 971 DC_INC(sc->dc_cdata.dc_tx_prod, DC_TX_LIST_CNT); 972 sc->dc_cdata.dc_tx_cnt++; 973 sframe = &sc->dc_ldata->dc_tx_list[i]; 974 sp = (u_int32_t *)&sc->dc_cdata.dc_sbuf; 975 bzero((char *)sp, DC_SFRAME_LEN); 976 977 sframe->dc_data = vtophys(&sc->dc_cdata.dc_sbuf); 978 sframe->dc_ctl = DC_SFRAME_LEN | DC_TXCTL_SETUP | DC_TXCTL_TLINK | 979 DC_FILTER_HASHPERF | DC_TXCTL_FINT; 980 981 sc->dc_cdata.dc_tx_chain[i] = (struct mbuf *)&sc->dc_cdata.dc_sbuf; 982 983 /* If we want promiscuous mode, set the allframes bit. */ 984 if (ifp->if_flags & IFF_PROMISC) 985 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC); 986 else 987 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC); 988 989 if (ifp->if_flags & IFF_ALLMULTI) 990 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI); 991 else 992 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI); 993 994 for (ifma = ifp->if_multiaddrs.lh_first; ifma != NULL; 995 ifma = ifma->ifma_link.le_next) { 996 if (ifma->ifma_addr->sa_family != AF_LINK) 997 continue; 998 h = dc_crc_le(sc, 999 LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 1000 sp[h >> 4] |= 1 << (h & 0xF); 1001 } 1002 1003 if (ifp->if_flags & IFF_BROADCAST) { 1004 h = dc_crc_le(sc, (caddr_t)ðerbroadcastaddr); 1005 sp[h >> 4] |= 1 << (h & 0xF); 1006 } 1007 1008 /* Set our MAC address */ 1009 sp[39] = ((u_int16_t *)sc->arpcom.ac_enaddr)[0]; 1010 sp[40] = ((u_int16_t *)sc->arpcom.ac_enaddr)[1]; 1011 sp[41] = ((u_int16_t *)sc->arpcom.ac_enaddr)[2]; 1012 1013 sframe->dc_status = DC_TXSTAT_OWN; 1014 CSR_WRITE_4(sc, DC_TXSTART, 0xFFFFFFFF); 1015 1016 /* 1017 * The PNIC takes an exceedingly long time to process its 1018 * setup frame; wait 10ms after posting the setup frame 1019 * before proceeding, just so it has time to swallow its 1020 * medicine. 1021 */ 1022 DELAY(10000); 1023 1024 ifp->if_timer = 5; 1025 1026 return; 1027 } 1028 1029 void dc_setfilt_admtek(sc) 1030 struct dc_softc *sc; 1031 { 1032 struct ifnet *ifp; 1033 int h = 0; 1034 u_int32_t hashes[2] = { 0, 0 }; 1035 struct ifmultiaddr *ifma; 1036 1037 ifp = &sc->arpcom.ac_if; 1038 1039 /* Init our MAC address */ 1040 CSR_WRITE_4(sc, DC_AL_PAR0, *(u_int32_t *)(&sc->arpcom.ac_enaddr[0])); 1041 CSR_WRITE_4(sc, DC_AL_PAR1, *(u_int32_t *)(&sc->arpcom.ac_enaddr[4])); 1042 1043 /* If we want promiscuous mode, set the allframes bit. */ 1044 if (ifp->if_flags & IFF_PROMISC) 1045 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC); 1046 else 1047 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC); 1048 1049 if (ifp->if_flags & IFF_ALLMULTI) 1050 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI); 1051 else 1052 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI); 1053 1054 /* first, zot all the existing hash bits */ 1055 CSR_WRITE_4(sc, DC_AL_MAR0, 0); 1056 CSR_WRITE_4(sc, DC_AL_MAR1, 0); 1057 1058 /* 1059 * If we're already in promisc or allmulti mode, we 1060 * don't have to bother programming the multicast filter. 1061 */ 1062 if (ifp->if_flags & (IFF_PROMISC|IFF_ALLMULTI)) 1063 return; 1064 1065 /* now program new ones */ 1066 for (ifma = ifp->if_multiaddrs.lh_first; ifma != NULL; 1067 ifma = ifma->ifma_link.le_next) { 1068 if (ifma->ifma_addr->sa_family != AF_LINK) 1069 continue; 1070 h = dc_crc_be(LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 1071 if (h < 32) 1072 hashes[0] |= (1 << h); 1073 else 1074 hashes[1] |= (1 << (h - 32)); 1075 } 1076 1077 CSR_WRITE_4(sc, DC_AL_MAR0, hashes[0]); 1078 CSR_WRITE_4(sc, DC_AL_MAR1, hashes[1]); 1079 1080 return; 1081 } 1082 1083 void dc_setfilt_asix(sc) 1084 struct dc_softc *sc; 1085 { 1086 struct ifnet *ifp; 1087 int h = 0; 1088 u_int32_t hashes[2] = { 0, 0 }; 1089 struct ifmultiaddr *ifma; 1090 1091 ifp = &sc->arpcom.ac_if; 1092 1093 /* Init our MAC address */ 1094 CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_PAR0); 1095 CSR_WRITE_4(sc, DC_AX_FILTDATA, 1096 *(u_int32_t *)(&sc->arpcom.ac_enaddr[0])); 1097 CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_PAR1); 1098 CSR_WRITE_4(sc, DC_AX_FILTDATA, 1099 *(u_int32_t *)(&sc->arpcom.ac_enaddr[4])); 1100 1101 /* If we want promiscuous mode, set the allframes bit. */ 1102 if (ifp->if_flags & IFF_PROMISC) 1103 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC); 1104 else 1105 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC); 1106 1107 if (ifp->if_flags & IFF_ALLMULTI) 1108 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI); 1109 else 1110 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI); 1111 1112 /* 1113 * The ASIX chip has a special bit to enable reception 1114 * of broadcast frames. 1115 */ 1116 if (ifp->if_flags & IFF_BROADCAST) 1117 DC_SETBIT(sc, DC_NETCFG, DC_AX_NETCFG_RX_BROAD); 1118 else 1119 DC_CLRBIT(sc, DC_NETCFG, DC_AX_NETCFG_RX_BROAD); 1120 1121 /* first, zot all the existing hash bits */ 1122 CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_MAR0); 1123 CSR_WRITE_4(sc, DC_AX_FILTDATA, 0); 1124 CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_MAR1); 1125 CSR_WRITE_4(sc, DC_AX_FILTDATA, 0); 1126 1127 /* 1128 * If we're already in promisc or allmulti mode, we 1129 * don't have to bother programming the multicast filter. 1130 */ 1131 if (ifp->if_flags & (IFF_PROMISC|IFF_ALLMULTI)) 1132 return; 1133 1134 /* now program new ones */ 1135 for (ifma = ifp->if_multiaddrs.lh_first; ifma != NULL; 1136 ifma = ifma->ifma_link.le_next) { 1137 if (ifma->ifma_addr->sa_family != AF_LINK) 1138 continue; 1139 h = dc_crc_be(LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 1140 if (h < 32) 1141 hashes[0] |= (1 << h); 1142 else 1143 hashes[1] |= (1 << (h - 32)); 1144 } 1145 1146 CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_MAR0); 1147 CSR_WRITE_4(sc, DC_AX_FILTDATA, hashes[0]); 1148 CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_MAR1); 1149 CSR_WRITE_4(sc, DC_AX_FILTDATA, hashes[1]); 1150 1151 return; 1152 } 1153 1154 static void dc_setfilt(sc) 1155 struct dc_softc *sc; 1156 { 1157 if (DC_IS_INTEL(sc) || DC_IS_MACRONIX(sc) || DC_IS_PNIC(sc) || 1158 DC_IS_PNICII(sc) || DC_IS_DAVICOM(sc)) 1159 dc_setfilt_21143(sc); 1160 1161 if (DC_IS_ASIX(sc)) 1162 dc_setfilt_asix(sc); 1163 1164 if (DC_IS_ADMTEK(sc)) 1165 dc_setfilt_admtek(sc); 1166 1167 return; 1168 } 1169 1170 /* 1171 * In order to fiddle with the 1172 * 'full-duplex' and '100Mbps' bits in the netconfig register, we 1173 * first have to put the transmit and/or receive logic in the idle state. 1174 */ 1175 static void dc_setcfg(sc, media) 1176 struct dc_softc *sc; 1177 int media; 1178 { 1179 int i, restart = 0; 1180 u_int32_t isr; 1181 1182 if (IFM_SUBTYPE(media) == IFM_NONE) 1183 return; 1184 1185 if (CSR_READ_4(sc, DC_NETCFG) & (DC_NETCFG_TX_ON|DC_NETCFG_RX_ON)) { 1186 restart = 1; 1187 DC_CLRBIT(sc, DC_NETCFG, (DC_NETCFG_TX_ON|DC_NETCFG_RX_ON)); 1188 1189 for (i = 0; i < DC_TIMEOUT; i++) { 1190 DELAY(10); 1191 isr = CSR_READ_4(sc, DC_ISR); 1192 if (isr & DC_ISR_TX_IDLE || 1193 (isr & DC_ISR_RX_STATE) == DC_RXSTATE_STOPPED) 1194 break; 1195 } 1196 1197 if (i == DC_TIMEOUT) 1198 printf("dc%d: failed to force tx and " 1199 "rx to idle state\n", sc->dc_unit); 1200 1201 } 1202 1203 if (IFM_SUBTYPE(media) == IFM_100_TX) { 1204 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_SPEEDSEL); 1205 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_HEARTBEAT); 1206 if (sc->dc_pmode == DC_PMODE_MII) { 1207 DC_SETBIT(sc, DC_WATCHDOG, DC_WDOG_JABBERDIS); 1208 DC_CLRBIT(sc, DC_NETCFG, (DC_NETCFG_PCS| 1209 DC_NETCFG_PORTSEL|DC_NETCFG_SCRAMBLER)); 1210 if (sc->dc_type == DC_TYPE_98713) 1211 DC_SETBIT(sc, DC_NETCFG, (DC_NETCFG_PCS| 1212 DC_NETCFG_SCRAMBLER)); 1213 if (!DC_IS_DAVICOM(sc)) 1214 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL); 1215 DC_CLRBIT(sc, DC_10BTCTRL, 0xFFFF); 1216 } else { 1217 if (DC_IS_PNIC(sc)) { 1218 DC_PN_GPIO_SETBIT(sc, DC_PN_GPIO_SPEEDSEL); 1219 DC_PN_GPIO_SETBIT(sc, DC_PN_GPIO_100TX_LOOP); 1220 DC_SETBIT(sc, DC_PN_NWAY, DC_PN_NWAY_SPEEDSEL); 1221 } 1222 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL| 1223 DC_NETCFG_PCS|DC_NETCFG_SCRAMBLER); 1224 } 1225 } 1226 1227 if (IFM_SUBTYPE(media) == IFM_10_T) { 1228 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_SPEEDSEL); 1229 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_HEARTBEAT); 1230 if (sc->dc_pmode == DC_PMODE_MII) { 1231 DC_SETBIT(sc, DC_WATCHDOG, DC_WDOG_JABBERDIS); 1232 DC_CLRBIT(sc, DC_NETCFG, (DC_NETCFG_PCS| 1233 DC_NETCFG_PORTSEL|DC_NETCFG_SCRAMBLER)); 1234 if (sc->dc_type == DC_TYPE_98713) 1235 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PCS); 1236 if (!DC_IS_DAVICOM(sc)) 1237 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL); 1238 DC_CLRBIT(sc, DC_10BTCTRL, 0xFFFF); 1239 } else { 1240 if (DC_IS_PNIC(sc)) { 1241 DC_PN_GPIO_CLRBIT(sc, DC_PN_GPIO_SPEEDSEL); 1242 DC_PN_GPIO_SETBIT(sc, DC_PN_GPIO_100TX_LOOP); 1243 DC_CLRBIT(sc, DC_PN_NWAY, DC_PN_NWAY_SPEEDSEL); 1244 } 1245 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL); 1246 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_SCRAMBLER); 1247 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PCS); 1248 } 1249 } 1250 1251 /* 1252 * If this is a Davicom DM9102A card with a DM9801 HomePNA 1253 * PHY and we want HomePNA mode, set the portsel bit to turn 1254 * on the external MII port. 1255 */ 1256 if (DC_IS_DAVICOM(sc)) { 1257 if (IFM_SUBTYPE(media) == IFM_homePNA) { 1258 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL); 1259 sc->dc_link = 1; 1260 } else { 1261 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL); 1262 } 1263 } 1264 1265 if ((media & IFM_GMASK) == IFM_FDX) { 1266 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_FULLDUPLEX); 1267 if (sc->dc_pmode == DC_PMODE_SYM && DC_IS_PNIC(sc)) 1268 DC_SETBIT(sc, DC_PN_NWAY, DC_PN_NWAY_DUPLEX); 1269 } else { 1270 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_FULLDUPLEX); 1271 if (sc->dc_pmode == DC_PMODE_SYM && DC_IS_PNIC(sc)) 1272 DC_CLRBIT(sc, DC_PN_NWAY, DC_PN_NWAY_DUPLEX); 1273 } 1274 1275 if (restart) 1276 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_TX_ON|DC_NETCFG_RX_ON); 1277 1278 return; 1279 } 1280 1281 static void dc_reset(sc) 1282 struct dc_softc *sc; 1283 { 1284 register int i; 1285 1286 DC_SETBIT(sc, DC_BUSCTL, DC_BUSCTL_RESET); 1287 1288 for (i = 0; i < DC_TIMEOUT; i++) { 1289 DELAY(10); 1290 if (!(CSR_READ_4(sc, DC_BUSCTL) & DC_BUSCTL_RESET)) 1291 break; 1292 } 1293 1294 if (DC_IS_ASIX(sc) || DC_IS_ADMTEK(sc)) { 1295 DELAY(10000); 1296 DC_CLRBIT(sc, DC_BUSCTL, DC_BUSCTL_RESET); 1297 i = 0; 1298 } 1299 1300 if (i == DC_TIMEOUT) 1301 printf("dc%d: reset never completed!\n", sc->dc_unit); 1302 1303 /* Wait a little while for the chip to get its brains in order. */ 1304 DELAY(1000); 1305 1306 CSR_WRITE_4(sc, DC_IMR, 0x00000000); 1307 CSR_WRITE_4(sc, DC_BUSCTL, 0x00000000); 1308 CSR_WRITE_4(sc, DC_NETCFG, 0x00000000); 1309 1310 /* 1311 * Bring the SIA out of reset. In some cases, it looks 1312 * like failing to unreset the SIA soon enough gets it 1313 * into a state where it will never come out of reset 1314 * until we reset the whole chip again. 1315 */ 1316 if (DC_IS_INTEL(sc)) 1317 DC_SETBIT(sc, DC_SIARESET, DC_SIA_RESET); 1318 1319 return; 1320 } 1321 1322 static struct dc_type *dc_devtype(dev) 1323 device_t dev; 1324 { 1325 struct dc_type *t; 1326 u_int32_t rev; 1327 1328 t = dc_devs; 1329 1330 while(t->dc_name != NULL) { 1331 if ((pci_get_vendor(dev) == t->dc_vid) && 1332 (pci_get_device(dev) == t->dc_did)) { 1333 /* Check the PCI revision */ 1334 rev = pci_read_config(dev, DC_PCI_CFRV, 4) & 0xFF; 1335 if (t->dc_did == DC_DEVICEID_98713 && 1336 rev >= DC_REVISION_98713A) 1337 t++; 1338 if (t->dc_did == DC_DEVICEID_98713_CP && 1339 rev >= DC_REVISION_98713A) 1340 t++; 1341 if (t->dc_did == DC_DEVICEID_987x5 && 1342 rev >= DC_REVISION_98725) 1343 t++; 1344 if (t->dc_did == DC_DEVICEID_AX88140A && 1345 rev >= DC_REVISION_88141) 1346 t++; 1347 if (t->dc_did == DC_DEVICEID_82C168 && 1348 rev >= DC_REVISION_82C169) 1349 t++; 1350 if (t->dc_did == DC_DEVICEID_DM9102 && 1351 rev >= DC_REVISION_DM9102A) 1352 t++; 1353 return(t); 1354 } 1355 t++; 1356 } 1357 1358 return(NULL); 1359 } 1360 1361 /* 1362 * Probe for a 21143 or clone chip. Check the PCI vendor and device 1363 * IDs against our list and return a device name if we find a match. 1364 * We do a little bit of extra work to identify the exact type of 1365 * chip. The MX98713 and MX98713A have the same PCI vendor/device ID, 1366 * but different revision IDs. The same is true for 98715/98715A 1367 * chips and the 98725, as well as the ASIX and ADMtek chips. In some 1368 * cases, the exact chip revision affects driver behavior. 1369 */ 1370 static int dc_probe(dev) 1371 device_t dev; 1372 { 1373 struct dc_type *t; 1374 1375 t = dc_devtype(dev); 1376 1377 if (t != NULL) { 1378 device_set_desc(dev, t->dc_name); 1379 return(0); 1380 } 1381 1382 return(ENXIO); 1383 } 1384 1385 static void dc_acpi(dev) 1386 device_t dev; 1387 { 1388 u_int32_t r, cptr; 1389 int unit; 1390 1391 unit = device_get_unit(dev); 1392 1393 /* Find the location of the capabilities block */ 1394 cptr = pci_read_config(dev, DC_PCI_CCAP, 4) & 0xFF; 1395 1396 r = pci_read_config(dev, cptr, 4) & 0xFF; 1397 if (r == 0x01) { 1398 1399 r = pci_read_config(dev, cptr + 4, 4); 1400 if (r & DC_PSTATE_D3) { 1401 u_int32_t iobase, membase, irq; 1402 1403 /* Save important PCI config data. */ 1404 iobase = pci_read_config(dev, DC_PCI_CFBIO, 4); 1405 membase = pci_read_config(dev, DC_PCI_CFBMA, 4); 1406 irq = pci_read_config(dev, DC_PCI_CFIT, 4); 1407 1408 /* Reset the power state. */ 1409 printf("dc%d: chip is in D%d power mode " 1410 "-- setting to D0\n", unit, r & DC_PSTATE_D3); 1411 r &= 0xFFFFFFFC; 1412 pci_write_config(dev, cptr + 4, r, 4); 1413 1414 /* Restore PCI config data. */ 1415 pci_write_config(dev, DC_PCI_CFBIO, iobase, 4); 1416 pci_write_config(dev, DC_PCI_CFBMA, membase, 4); 1417 pci_write_config(dev, DC_PCI_CFIT, irq, 4); 1418 } 1419 } 1420 return; 1421 } 1422 1423 /* 1424 * Attach the interface. Allocate softc structures, do ifmedia 1425 * setup and ethernet/BPF attach. 1426 */ 1427 static int dc_attach(dev) 1428 device_t dev; 1429 { 1430 int s; 1431 u_char eaddr[ETHER_ADDR_LEN]; 1432 u_int32_t command; 1433 struct dc_softc *sc; 1434 struct ifnet *ifp; 1435 u_int32_t revision; 1436 int unit, error = 0, rid, mac_offset; 1437 1438 s = splimp(); 1439 1440 sc = device_get_softc(dev); 1441 unit = device_get_unit(dev); 1442 bzero(sc, sizeof(struct dc_softc)); 1443 1444 /* 1445 * Handle power management nonsense. 1446 */ 1447 dc_acpi(dev); 1448 1449 /* 1450 * Map control/status registers. 1451 */ 1452 command = pci_read_config(dev, PCI_COMMAND_STATUS_REG, 4); 1453 command |= (PCIM_CMD_PORTEN|PCIM_CMD_MEMEN|PCIM_CMD_BUSMASTEREN); 1454 pci_write_config(dev, PCI_COMMAND_STATUS_REG, command, 4); 1455 command = pci_read_config(dev, PCI_COMMAND_STATUS_REG, 4); 1456 1457 #ifdef DC_USEIOSPACE 1458 if (!(command & PCIM_CMD_PORTEN)) { 1459 printf("dc%d: failed to enable I/O ports!\n", unit); 1460 error = ENXIO; 1461 goto fail; 1462 } 1463 #else 1464 if (!(command & PCIM_CMD_MEMEN)) { 1465 printf("dc%d: failed to enable memory mapping!\n", unit); 1466 error = ENXIO; 1467 goto fail; 1468 } 1469 #endif 1470 1471 rid = DC_RID; 1472 sc->dc_res = bus_alloc_resource(dev, DC_RES, &rid, 1473 0, ~0, 1, RF_ACTIVE); 1474 1475 if (sc->dc_res == NULL) { 1476 printf("dc%d: couldn't map ports/memory\n", unit); 1477 error = ENXIO; 1478 goto fail; 1479 } 1480 1481 sc->dc_btag = rman_get_bustag(sc->dc_res); 1482 sc->dc_bhandle = rman_get_bushandle(sc->dc_res); 1483 1484 /* Allocate interrupt */ 1485 rid = 0; 1486 sc->dc_irq = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, 0, ~0, 1, 1487 RF_SHAREABLE | RF_ACTIVE); 1488 1489 if (sc->dc_irq == NULL) { 1490 printf("dc%d: couldn't map interrupt\n", unit); 1491 bus_release_resource(dev, DC_RES, DC_RID, sc->dc_res); 1492 error = ENXIO; 1493 goto fail; 1494 } 1495 1496 error = bus_setup_intr(dev, sc->dc_irq, INTR_TYPE_NET, 1497 dc_intr, sc, &sc->dc_intrhand); 1498 1499 if (error) { 1500 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->dc_irq); 1501 bus_release_resource(dev, DC_RES, DC_RID, sc->dc_res); 1502 printf("dc%d: couldn't set up irq\n", unit); 1503 goto fail; 1504 } 1505 1506 /* Need this info to decide on a chip type. */ 1507 sc->dc_info = dc_devtype(dev); 1508 revision = pci_read_config(dev, DC_PCI_CFRV, 4) & 0x000000FF; 1509 1510 switch(sc->dc_info->dc_did) { 1511 case DC_DEVICEID_21143: 1512 sc->dc_type = DC_TYPE_21143; 1513 sc->dc_flags |= DC_TX_POLL|DC_TX_USE_TX_INTR; 1514 sc->dc_flags |= DC_REDUCED_MII_POLL; 1515 break; 1516 case DC_DEVICEID_DM9100: 1517 case DC_DEVICEID_DM9102: 1518 sc->dc_type = DC_TYPE_DM9102; 1519 sc->dc_flags |= DC_TX_COALESCE|DC_TX_USE_TX_INTR; 1520 sc->dc_flags |= DC_REDUCED_MII_POLL; 1521 sc->dc_pmode = DC_PMODE_MII; 1522 break; 1523 case DC_DEVICEID_AL981: 1524 sc->dc_type = DC_TYPE_AL981; 1525 sc->dc_flags |= DC_TX_USE_TX_INTR; 1526 sc->dc_flags |= DC_TX_ADMTEK_WAR; 1527 sc->dc_pmode = DC_PMODE_MII; 1528 break; 1529 case DC_DEVICEID_AN985: 1530 sc->dc_type = DC_TYPE_AN985; 1531 sc->dc_flags |= DC_TX_USE_TX_INTR; 1532 sc->dc_flags |= DC_TX_ADMTEK_WAR; 1533 sc->dc_pmode = DC_PMODE_MII; 1534 break; 1535 case DC_DEVICEID_98713: 1536 case DC_DEVICEID_98713_CP: 1537 if (revision < DC_REVISION_98713A) { 1538 sc->dc_type = DC_TYPE_98713; 1539 sc->dc_flags |= DC_REDUCED_MII_POLL; 1540 } 1541 if (revision >= DC_REVISION_98713A) 1542 sc->dc_type = DC_TYPE_98713A; 1543 sc->dc_flags |= DC_TX_POLL|DC_TX_USE_TX_INTR; 1544 break; 1545 case DC_DEVICEID_987x5: 1546 sc->dc_type = DC_TYPE_987x5; 1547 sc->dc_flags |= DC_TX_POLL|DC_TX_USE_TX_INTR; 1548 break; 1549 case DC_DEVICEID_82C115: 1550 sc->dc_type = DC_TYPE_PNICII; 1551 sc->dc_flags |= DC_TX_POLL|DC_TX_USE_TX_INTR; 1552 break; 1553 case DC_DEVICEID_82C168: 1554 sc->dc_type = DC_TYPE_PNIC; 1555 sc->dc_flags |= DC_TX_STORENFWD|DC_TX_INTR_ALWAYS; 1556 sc->dc_flags |= DC_PNIC_RX_BUG_WAR; 1557 sc->dc_pnic_rx_buf = malloc(DC_RXLEN * 5, M_DEVBUF, M_NOWAIT); 1558 if (revision < DC_REVISION_82C169) 1559 sc->dc_pmode = DC_PMODE_SYM; 1560 break; 1561 case DC_DEVICEID_AX88140A: 1562 sc->dc_type = DC_TYPE_ASIX; 1563 sc->dc_flags |= DC_TX_USE_TX_INTR|DC_TX_INTR_FIRSTFRAG; 1564 sc->dc_flags |= DC_REDUCED_MII_POLL; 1565 sc->dc_pmode = DC_PMODE_MII; 1566 break; 1567 default: 1568 printf("dc%d: unknown device: %x\n", sc->dc_unit, 1569 sc->dc_info->dc_did); 1570 break; 1571 } 1572 1573 /* Save the cache line size. */ 1574 if (DC_IS_DAVICOM(sc)) 1575 sc->dc_cachesize = 0; 1576 else 1577 sc->dc_cachesize = pci_read_config(dev, 1578 DC_PCI_CFLT, 4) & 0xFF; 1579 1580 /* Reset the adapter. */ 1581 dc_reset(sc); 1582 1583 /* Take 21143 out of snooze mode */ 1584 if (DC_IS_INTEL(sc)) { 1585 command = pci_read_config(dev, DC_PCI_CFDD, 4); 1586 command &= ~(DC_CFDD_SNOOZE_MODE|DC_CFDD_SLEEP_MODE); 1587 pci_write_config(dev, DC_PCI_CFDD, command, 4); 1588 } 1589 1590 /* 1591 * Try to learn something about the supported media. 1592 * We know that ASIX and ADMtek and Davicom devices 1593 * will *always* be using MII media, so that's a no-brainer. 1594 * The tricky ones are the Macronix/PNIC II and the 1595 * Intel 21143. 1596 */ 1597 if (DC_IS_INTEL(sc)) { 1598 u_int32_t media, cwuc; 1599 cwuc = pci_read_config(dev, DC_PCI_CWUC, 4); 1600 cwuc |= DC_CWUC_FORCE_WUL; 1601 pci_write_config(dev, DC_PCI_CWUC, cwuc, 4); 1602 DELAY(10000); 1603 media = pci_read_config(dev, DC_PCI_CWUC, 4); 1604 cwuc &= ~DC_CWUC_FORCE_WUL; 1605 pci_write_config(dev, DC_PCI_CWUC, cwuc, 4); 1606 DELAY(10000); 1607 if (media & DC_CWUC_MII_ABILITY) 1608 sc->dc_pmode = DC_PMODE_MII; 1609 if (media & DC_CWUC_SYM_ABILITY) 1610 sc->dc_pmode = DC_PMODE_SYM; 1611 /* 1612 * If none of the bits are set, then this NIC 1613 * isn't meant to support 'wake up LAN' mode. 1614 * This is usually only the case on multiport 1615 * cards, and these cards almost always have 1616 * MII transceivers. 1617 */ 1618 if (media == 0) 1619 sc->dc_pmode = DC_PMODE_MII; 1620 } else if (DC_IS_MACRONIX(sc) || DC_IS_PNICII(sc)) { 1621 if (sc->dc_type == DC_TYPE_98713) 1622 sc->dc_pmode = DC_PMODE_MII; 1623 else 1624 sc->dc_pmode = DC_PMODE_SYM; 1625 } else if (!sc->dc_pmode) 1626 sc->dc_pmode = DC_PMODE_MII; 1627 1628 /* 1629 * Get station address from the EEPROM. 1630 */ 1631 switch(sc->dc_type) { 1632 case DC_TYPE_98713: 1633 case DC_TYPE_98713A: 1634 case DC_TYPE_987x5: 1635 case DC_TYPE_PNICII: 1636 dc_read_eeprom(sc, (caddr_t)&mac_offset, 1637 (DC_EE_NODEADDR_OFFSET / 2), 1, 0); 1638 dc_read_eeprom(sc, (caddr_t)&eaddr, (mac_offset / 2), 3, 0); 1639 break; 1640 case DC_TYPE_PNIC: 1641 dc_read_eeprom(sc, (caddr_t)&eaddr, 0, 3, 1); 1642 break; 1643 case DC_TYPE_DM9102: 1644 case DC_TYPE_21143: 1645 case DC_TYPE_ASIX: 1646 dc_read_eeprom(sc, (caddr_t)&eaddr, DC_EE_NODEADDR, 3, 0); 1647 break; 1648 case DC_TYPE_AL981: 1649 case DC_TYPE_AN985: 1650 dc_read_eeprom(sc, (caddr_t)&eaddr, DC_AL_EE_NODEADDR, 3, 0); 1651 break; 1652 default: 1653 dc_read_eeprom(sc, (caddr_t)&eaddr, DC_EE_NODEADDR, 3, 0); 1654 break; 1655 } 1656 1657 /* 1658 * A 21143 or clone chip was detected. Inform the world. 1659 */ 1660 printf("dc%d: Ethernet address: %6D\n", unit, eaddr, ":"); 1661 1662 sc->dc_unit = unit; 1663 bcopy(eaddr, (char *)&sc->arpcom.ac_enaddr, ETHER_ADDR_LEN); 1664 1665 sc->dc_ldata = contigmalloc(sizeof(struct dc_list_data), M_DEVBUF, 1666 M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0); 1667 1668 if (sc->dc_ldata == NULL) { 1669 printf("dc%d: no memory for list buffers!\n", unit); 1670 bus_teardown_intr(dev, sc->dc_irq, sc->dc_intrhand); 1671 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->dc_irq); 1672 bus_release_resource(dev, DC_RES, DC_RID, sc->dc_res); 1673 error = ENXIO; 1674 goto fail; 1675 } 1676 1677 bzero(sc->dc_ldata, sizeof(struct dc_list_data)); 1678 1679 ifp = &sc->arpcom.ac_if; 1680 ifp->if_softc = sc; 1681 ifp->if_unit = unit; 1682 ifp->if_name = "dc"; 1683 ifp->if_mtu = ETHERMTU; 1684 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 1685 ifp->if_ioctl = dc_ioctl; 1686 ifp->if_output = ether_output; 1687 ifp->if_start = dc_start; 1688 ifp->if_watchdog = dc_watchdog; 1689 ifp->if_init = dc_init; 1690 ifp->if_baudrate = 10000000; 1691 ifp->if_snd.ifq_maxlen = DC_TX_LIST_CNT - 1; 1692 1693 /* 1694 * Do MII setup. 1695 */ 1696 error = mii_phy_probe(dev, &sc->dc_miibus, 1697 dc_ifmedia_upd, dc_ifmedia_sts); 1698 1699 if (error && DC_IS_INTEL(sc)) { 1700 sc->dc_pmode = DC_PMODE_SYM; 1701 mii_phy_probe(dev, &sc->dc_miibus, 1702 dc_ifmedia_upd, dc_ifmedia_sts); 1703 error = 0; 1704 } 1705 1706 if (error) { 1707 printf("dc%d: MII without any PHY!\n", sc->dc_unit); 1708 bus_teardown_intr(dev, sc->dc_irq, sc->dc_intrhand); 1709 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->dc_irq); 1710 bus_release_resource(dev, DC_RES, DC_RID, sc->dc_res); 1711 error = ENXIO; 1712 goto fail; 1713 } 1714 1715 /* 1716 * Call MI attach routines. 1717 */ 1718 if_attach(ifp); 1719 ether_ifattach(ifp); 1720 callout_handle_init(&sc->dc_stat_ch); 1721 1722 bpfattach(ifp, DLT_EN10MB, sizeof(struct ether_header)); 1723 1724 fail: 1725 splx(s); 1726 1727 return(error); 1728 } 1729 1730 static int dc_detach(dev) 1731 device_t dev; 1732 { 1733 struct dc_softc *sc; 1734 struct ifnet *ifp; 1735 int s; 1736 1737 s = splimp(); 1738 1739 sc = device_get_softc(dev); 1740 ifp = &sc->arpcom.ac_if; 1741 1742 dc_stop(sc); 1743 if_detach(ifp); 1744 1745 bus_generic_detach(dev); 1746 device_delete_child(dev, sc->dc_miibus); 1747 1748 bus_teardown_intr(dev, sc->dc_irq, sc->dc_intrhand); 1749 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->dc_irq); 1750 bus_release_resource(dev, DC_RES, DC_RID, sc->dc_res); 1751 1752 contigfree(sc->dc_ldata, sizeof(struct dc_list_data), M_DEVBUF); 1753 if (sc->dc_pnic_rx_buf != NULL) 1754 free(sc->dc_pnic_rx_buf, M_DEVBUF); 1755 1756 splx(s); 1757 1758 return(0); 1759 } 1760 1761 /* 1762 * Initialize the transmit descriptors. 1763 */ 1764 static int dc_list_tx_init(sc) 1765 struct dc_softc *sc; 1766 { 1767 struct dc_chain_data *cd; 1768 struct dc_list_data *ld; 1769 int i; 1770 1771 cd = &sc->dc_cdata; 1772 ld = sc->dc_ldata; 1773 for (i = 0; i < DC_TX_LIST_CNT; i++) { 1774 if (i == (DC_TX_LIST_CNT - 1)) { 1775 ld->dc_tx_list[i].dc_next = 1776 vtophys(&ld->dc_tx_list[0]); 1777 } else { 1778 ld->dc_tx_list[i].dc_next = 1779 vtophys(&ld->dc_tx_list[i + 1]); 1780 } 1781 cd->dc_tx_chain[i] = NULL; 1782 ld->dc_tx_list[i].dc_data = 0; 1783 ld->dc_tx_list[i].dc_ctl = 0; 1784 } 1785 1786 cd->dc_tx_prod = cd->dc_tx_cons = cd->dc_tx_cnt = 0; 1787 1788 return(0); 1789 } 1790 1791 1792 /* 1793 * Initialize the RX descriptors and allocate mbufs for them. Note that 1794 * we arrange the descriptors in a closed ring, so that the last descriptor 1795 * points back to the first. 1796 */ 1797 static int dc_list_rx_init(sc) 1798 struct dc_softc *sc; 1799 { 1800 struct dc_chain_data *cd; 1801 struct dc_list_data *ld; 1802 int i; 1803 1804 cd = &sc->dc_cdata; 1805 ld = sc->dc_ldata; 1806 1807 for (i = 0; i < DC_RX_LIST_CNT; i++) { 1808 if (dc_newbuf(sc, i, NULL) == ENOBUFS) 1809 return(ENOBUFS); 1810 if (i == (DC_RX_LIST_CNT - 1)) { 1811 ld->dc_rx_list[i].dc_next = 1812 vtophys(&ld->dc_rx_list[0]); 1813 } else { 1814 ld->dc_rx_list[i].dc_next = 1815 vtophys(&ld->dc_rx_list[i + 1]); 1816 } 1817 } 1818 1819 cd->dc_rx_prod = 0; 1820 1821 return(0); 1822 } 1823 1824 /* 1825 * Initialize an RX descriptor and attach an MBUF cluster. 1826 */ 1827 static int dc_newbuf(sc, i, m) 1828 struct dc_softc *sc; 1829 int i; 1830 struct mbuf *m; 1831 { 1832 struct mbuf *m_new = NULL; 1833 struct dc_desc *c; 1834 1835 c = &sc->dc_ldata->dc_rx_list[i]; 1836 1837 if (m == NULL) { 1838 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 1839 if (m_new == NULL) { 1840 printf("dc%d: no memory for rx list " 1841 "-- packet dropped!\n", sc->dc_unit); 1842 return(ENOBUFS); 1843 } 1844 1845 MCLGET(m_new, M_DONTWAIT); 1846 if (!(m_new->m_flags & M_EXT)) { 1847 printf("dc%d: no memory for rx list " 1848 "-- packet dropped!\n", sc->dc_unit); 1849 m_freem(m_new); 1850 return(ENOBUFS); 1851 } 1852 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 1853 } else { 1854 m_new = m; 1855 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 1856 m_new->m_data = m_new->m_ext.ext_buf; 1857 } 1858 1859 m_adj(m_new, sizeof(u_int64_t)); 1860 1861 /* 1862 * If this is a PNIC chip, zero the buffer. This is part 1863 * of the workaround for the receive bug in the 82c168 and 1864 * 82c169 chips. 1865 */ 1866 if (sc->dc_flags & DC_PNIC_RX_BUG_WAR) 1867 bzero((char *)mtod(m_new, char *), m_new->m_len); 1868 1869 sc->dc_cdata.dc_rx_chain[i] = m_new; 1870 c->dc_data = vtophys(mtod(m_new, caddr_t)); 1871 c->dc_ctl = DC_RXCTL_RLINK | DC_RXLEN; 1872 c->dc_status = DC_RXSTAT_OWN; 1873 1874 return(0); 1875 } 1876 1877 /* 1878 * Grrrrr. 1879 * The PNIC chip has a terrible bug in it that manifests itself during 1880 * periods of heavy activity. The exact mode of failure if difficult to 1881 * pinpoint: sometimes it only happens in promiscuous mode, sometimes it 1882 * will happen on slow machines. The bug is that sometimes instead of 1883 * uploading one complete frame during reception, it uploads what looks 1884 * like the entire contents of its FIFO memory. The frame we want is at 1885 * the end of the whole mess, but we never know exactly how much data has 1886 * been uploaded, so salvaging the frame is hard. 1887 * 1888 * There is only one way to do it reliably, and it's disgusting. 1889 * Here's what we know: 1890 * 1891 * - We know there will always be somewhere between one and three extra 1892 * descriptors uploaded. 1893 * 1894 * - We know the desired received frame will always be at the end of the 1895 * total data upload. 1896 * 1897 * - We know the size of the desired received frame because it will be 1898 * provided in the length field of the status word in the last descriptor. 1899 * 1900 * Here's what we do: 1901 * 1902 * - When we allocate buffers for the receive ring, we bzero() them. 1903 * This means that we know that the buffer contents should be all 1904 * zeros, except for data uploaded by the chip. 1905 * 1906 * - We also force the PNIC chip to upload frames that include the 1907 * ethernet CRC at the end. 1908 * 1909 * - We gather all of the bogus frame data into a single buffer. 1910 * 1911 * - We then position a pointer at the end of this buffer and scan 1912 * backwards until we encounter the first non-zero byte of data. 1913 * This is the end of the received frame. We know we will encounter 1914 * some data at the end of the frame because the CRC will always be 1915 * there, so even if the sender transmits a packet of all zeros, 1916 * we won't be fooled. 1917 * 1918 * - We know the size of the actual received frame, so we subtract 1919 * that value from the current pointer location. This brings us 1920 * to the start of the actual received packet. 1921 * 1922 * - We copy this into an mbuf and pass it on, along with the actual 1923 * frame length. 1924 * 1925 * The performance hit is tremendous, but it beats dropping frames all 1926 * the time. 1927 */ 1928 1929 #define DC_WHOLEFRAME (DC_RXSTAT_FIRSTFRAG|DC_RXSTAT_LASTFRAG) 1930 static void dc_pnic_rx_bug_war(sc, idx) 1931 struct dc_softc *sc; 1932 int idx; 1933 { 1934 struct dc_desc *cur_rx; 1935 struct dc_desc *c = NULL; 1936 struct mbuf *m = NULL; 1937 unsigned char *ptr; 1938 int i, total_len; 1939 u_int32_t rxstat = 0; 1940 1941 i = sc->dc_pnic_rx_bug_save; 1942 cur_rx = &sc->dc_ldata->dc_rx_list[idx]; 1943 ptr = sc->dc_pnic_rx_buf; 1944 bzero(ptr, sizeof(DC_RXLEN * 5)); 1945 1946 /* Copy all the bytes from the bogus buffers. */ 1947 while (1) { 1948 c = &sc->dc_ldata->dc_rx_list[i]; 1949 rxstat = c->dc_status; 1950 m = sc->dc_cdata.dc_rx_chain[i]; 1951 bcopy(mtod(m, char *), ptr, DC_RXLEN); 1952 ptr += DC_RXLEN; 1953 /* If this is the last buffer, break out. */ 1954 if (i == idx || rxstat & DC_RXSTAT_LASTFRAG) 1955 break; 1956 dc_newbuf(sc, i, m); 1957 DC_INC(i, DC_RX_LIST_CNT); 1958 } 1959 1960 /* Find the length of the actual receive frame. */ 1961 total_len = DC_RXBYTES(rxstat); 1962 1963 /* Scan backwards until we hit a non-zero byte. */ 1964 while(*ptr == 0x00) 1965 ptr--; 1966 1967 /* Round off. */ 1968 if ((uintptr_t)(ptr) & 0x3) 1969 ptr -= 1; 1970 1971 /* Now find the start of the frame. */ 1972 ptr -= total_len; 1973 if (ptr < sc->dc_pnic_rx_buf) 1974 ptr = sc->dc_pnic_rx_buf; 1975 1976 /* 1977 * Now copy the salvaged frame to the last mbuf and fake up 1978 * the status word to make it look like a successful 1979 * frame reception. 1980 */ 1981 dc_newbuf(sc, i, m); 1982 bcopy(ptr, mtod(m, char *), total_len); 1983 cur_rx->dc_status = rxstat | DC_RXSTAT_FIRSTFRAG; 1984 1985 return; 1986 } 1987 1988 /* 1989 * This routine searches the RX ring for dirty descriptors in the 1990 * event that the rxeof routine falls out of sync with the chip's 1991 * current descriptor pointer. This may happen sometimes as a result 1992 * of a "no RX buffer available" condition that happens when the chip 1993 * consumes all of the RX buffers before the driver has a chance to 1994 * process the RX ring. This routine may need to be called more than 1995 * once to bring the driver back in sync with the chip, however we 1996 * should still be getting RX DONE interrupts to drive the search 1997 * for new packets in the RX ring, so we should catch up eventually. 1998 */ 1999 static int dc_rx_resync(sc) 2000 struct dc_softc *sc; 2001 { 2002 int i, pos; 2003 struct dc_desc *cur_rx; 2004 2005 pos = sc->dc_cdata.dc_rx_prod; 2006 2007 for (i = 0; i < DC_RX_LIST_CNT; i++) { 2008 cur_rx = &sc->dc_ldata->dc_rx_list[pos]; 2009 if (!(cur_rx->dc_status & DC_RXSTAT_OWN)) 2010 break; 2011 DC_INC(pos, DC_RX_LIST_CNT); 2012 } 2013 2014 /* If the ring really is empty, then just return. */ 2015 if (i == DC_RX_LIST_CNT) 2016 return(0); 2017 2018 /* We've fallen behing the chip: catch it. */ 2019 sc->dc_cdata.dc_rx_prod = pos; 2020 2021 return(EAGAIN); 2022 } 2023 2024 /* 2025 * A frame has been uploaded: pass the resulting mbuf chain up to 2026 * the higher level protocols. 2027 */ 2028 static void dc_rxeof(sc) 2029 struct dc_softc *sc; 2030 { 2031 struct ether_header *eh; 2032 struct mbuf *m; 2033 struct ifnet *ifp; 2034 struct dc_desc *cur_rx; 2035 int i, total_len = 0; 2036 u_int32_t rxstat; 2037 2038 ifp = &sc->arpcom.ac_if; 2039 i = sc->dc_cdata.dc_rx_prod; 2040 2041 while(!(sc->dc_ldata->dc_rx_list[i].dc_status & DC_RXSTAT_OWN)) { 2042 struct mbuf *m0 = NULL; 2043 2044 cur_rx = &sc->dc_ldata->dc_rx_list[i]; 2045 rxstat = cur_rx->dc_status; 2046 m = sc->dc_cdata.dc_rx_chain[i]; 2047 total_len = DC_RXBYTES(rxstat); 2048 2049 if (sc->dc_flags & DC_PNIC_RX_BUG_WAR) { 2050 if ((rxstat & DC_WHOLEFRAME) != DC_WHOLEFRAME) { 2051 if (rxstat & DC_RXSTAT_FIRSTFRAG) 2052 sc->dc_pnic_rx_bug_save = i; 2053 if ((rxstat & DC_RXSTAT_LASTFRAG) == 0) { 2054 DC_INC(i, DC_RX_LIST_CNT); 2055 continue; 2056 } 2057 dc_pnic_rx_bug_war(sc, i); 2058 rxstat = cur_rx->dc_status; 2059 total_len = DC_RXBYTES(rxstat); 2060 } 2061 } 2062 2063 sc->dc_cdata.dc_rx_chain[i] = NULL; 2064 2065 /* 2066 * If an error occurs, update stats, clear the 2067 * status word and leave the mbuf cluster in place: 2068 * it should simply get re-used next time this descriptor 2069 * comes up in the ring. 2070 */ 2071 if (rxstat & DC_RXSTAT_RXERR) { 2072 ifp->if_ierrors++; 2073 if (rxstat & DC_RXSTAT_COLLSEEN) 2074 ifp->if_collisions++; 2075 dc_newbuf(sc, i, m); 2076 if (rxstat & DC_RXSTAT_CRCERR) { 2077 DC_INC(i, DC_RX_LIST_CNT); 2078 continue; 2079 } else { 2080 dc_init(sc); 2081 return; 2082 } 2083 } 2084 2085 /* No errors; receive the packet. */ 2086 total_len -= ETHER_CRC_LEN; 2087 2088 m0 = m_devget(mtod(m, char *) - ETHER_ALIGN, 2089 total_len + ETHER_ALIGN, 0, ifp, NULL); 2090 dc_newbuf(sc, i, m); 2091 DC_INC(i, DC_RX_LIST_CNT); 2092 if (m0 == NULL) { 2093 ifp->if_ierrors++; 2094 continue; 2095 } 2096 m_adj(m0, ETHER_ALIGN); 2097 m = m0; 2098 2099 ifp->if_ipackets++; 2100 eh = mtod(m, struct ether_header *); 2101 2102 /* 2103 * Handle BPF listeners. Let the BPF user see the packet, but 2104 * don't pass it up to the ether_input() layer unless it's 2105 * a broadcast packet, multicast packet, matches our ethernet 2106 * address or the interface is in promiscuous mode. 2107 */ 2108 if (ifp->if_bpf) { 2109 bpf_mtap(ifp, m); 2110 if (ifp->if_flags & IFF_PROMISC && 2111 (bcmp(eh->ether_dhost, sc->arpcom.ac_enaddr, 2112 ETHER_ADDR_LEN) && 2113 (eh->ether_dhost[0] & 1) == 0)) { 2114 m_freem(m); 2115 continue; 2116 } 2117 } 2118 2119 /* Remove header from mbuf and pass it on. */ 2120 m_adj(m, sizeof(struct ether_header)); 2121 ether_input(ifp, eh, m); 2122 } 2123 2124 sc->dc_cdata.dc_rx_prod = i; 2125 2126 return; 2127 } 2128 2129 /* 2130 * A frame was downloaded to the chip. It's safe for us to clean up 2131 * the list buffers. 2132 */ 2133 2134 static void dc_txeof(sc) 2135 struct dc_softc *sc; 2136 { 2137 struct dc_desc *cur_tx = NULL; 2138 struct ifnet *ifp; 2139 int idx; 2140 2141 ifp = &sc->arpcom.ac_if; 2142 2143 /* Clear the timeout timer. */ 2144 ifp->if_timer = 0; 2145 2146 /* 2147 * Go through our tx list and free mbufs for those 2148 * frames that have been transmitted. 2149 */ 2150 idx = sc->dc_cdata.dc_tx_cons; 2151 while(idx != sc->dc_cdata.dc_tx_prod) { 2152 u_int32_t txstat; 2153 2154 cur_tx = &sc->dc_ldata->dc_tx_list[idx]; 2155 txstat = cur_tx->dc_status; 2156 2157 if (txstat & DC_TXSTAT_OWN) 2158 break; 2159 2160 if (!(cur_tx->dc_ctl & DC_TXCTL_LASTFRAG) || 2161 cur_tx->dc_ctl & DC_TXCTL_SETUP) { 2162 sc->dc_cdata.dc_tx_cnt--; 2163 if (cur_tx->dc_ctl & DC_TXCTL_SETUP) { 2164 /* 2165 * Yes, the PNIC is so brain damaged 2166 * that it will sometimes generate a TX 2167 * underrun error while DMAing the RX 2168 * filter setup frame. If we detect this, 2169 * we have to send the setup frame again, 2170 * or else the filter won't be programmed 2171 * correctly. 2172 */ 2173 if (DC_IS_PNIC(sc)) { 2174 if (txstat & DC_TXSTAT_ERRSUM) 2175 dc_setfilt(sc); 2176 } 2177 sc->dc_cdata.dc_tx_chain[idx] = NULL; 2178 } 2179 DC_INC(idx, DC_TX_LIST_CNT); 2180 continue; 2181 } 2182 2183 if (/*sc->dc_type == DC_TYPE_21143 &&*/ 2184 sc->dc_pmode == DC_PMODE_MII && 2185 ((txstat & 0xFFFF) & ~(DC_TXSTAT_ERRSUM| 2186 DC_TXSTAT_NOCARRIER|DC_TXSTAT_CARRLOST))) 2187 txstat &= ~DC_TXSTAT_ERRSUM; 2188 2189 if (txstat & DC_TXSTAT_ERRSUM) { 2190 ifp->if_oerrors++; 2191 if (txstat & DC_TXSTAT_EXCESSCOLL) 2192 ifp->if_collisions++; 2193 if (txstat & DC_TXSTAT_LATECOLL) 2194 ifp->if_collisions++; 2195 if (!(txstat & DC_TXSTAT_UNDERRUN)) { 2196 dc_init(sc); 2197 return; 2198 } 2199 } 2200 2201 ifp->if_collisions += (txstat & DC_TXSTAT_COLLCNT) >> 3; 2202 2203 ifp->if_opackets++; 2204 if (sc->dc_cdata.dc_tx_chain[idx] != NULL) { 2205 m_freem(sc->dc_cdata.dc_tx_chain[idx]); 2206 sc->dc_cdata.dc_tx_chain[idx] = NULL; 2207 } 2208 2209 sc->dc_cdata.dc_tx_cnt--; 2210 DC_INC(idx, DC_TX_LIST_CNT); 2211 } 2212 2213 sc->dc_cdata.dc_tx_cons = idx; 2214 if (cur_tx != NULL) 2215 ifp->if_flags &= ~IFF_OACTIVE; 2216 2217 return; 2218 } 2219 2220 static void dc_tick(xsc) 2221 void *xsc; 2222 { 2223 struct dc_softc *sc; 2224 struct mii_data *mii; 2225 struct ifnet *ifp; 2226 int s; 2227 u_int32_t r; 2228 2229 s = splimp(); 2230 2231 sc = xsc; 2232 ifp = &sc->arpcom.ac_if; 2233 mii = device_get_softc(sc->dc_miibus); 2234 2235 if (sc->dc_flags & DC_REDUCED_MII_POLL) { 2236 r = CSR_READ_4(sc, DC_ISR); 2237 if (DC_IS_INTEL(sc)) { 2238 if (r & DC_ISR_LINKFAIL) 2239 sc->dc_link = 0; 2240 if (sc->dc_link == 0) 2241 mii_tick(mii); 2242 } else { 2243 if ((r & DC_ISR_RX_STATE) == DC_RXSTATE_WAIT && 2244 sc->dc_cdata.dc_tx_prod == 0) 2245 mii_tick(mii); 2246 } 2247 } else 2248 mii_tick(mii); 2249 2250 /* 2251 * When the init routine completes, we expect to be able to send 2252 * packets right away, and in fact the network code will send a 2253 * gratuitous ARP the moment the init routine marks the interface 2254 * as running. However, even though the MAC may have been initialized, 2255 * there may be a delay of a few seconds before the PHY completes 2256 * autonegotiation and the link is brought up. Any transmissions 2257 * made during that delay will be lost. Dealing with this is tricky: 2258 * we can't just pause in the init routine while waiting for the 2259 * PHY to come ready since that would bring the whole system to 2260 * a screeching halt for several seconds. 2261 * 2262 * What we do here is prevent the TX start routine from sending 2263 * any packets until a link has been established. After the 2264 * interface has been initialized, the tick routine will poll 2265 * the state of the PHY until the IFM_ACTIVE flag is set. Until 2266 * that time, packets will stay in the send queue, and once the 2267 * link comes up, they will be flushed out to the wire. 2268 */ 2269 if (!sc->dc_link) { 2270 mii_pollstat(mii); 2271 if (mii->mii_media_status & IFM_ACTIVE && 2272 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) { 2273 sc->dc_link++; 2274 if (ifp->if_snd.ifq_head != NULL) 2275 dc_start(ifp); 2276 } 2277 } 2278 2279 sc->dc_stat_ch = timeout(dc_tick, sc, hz); 2280 2281 splx(s); 2282 2283 return; 2284 } 2285 2286 static void dc_intr(arg) 2287 void *arg; 2288 { 2289 struct dc_softc *sc; 2290 struct ifnet *ifp; 2291 u_int32_t status; 2292 2293 sc = arg; 2294 ifp = &sc->arpcom.ac_if; 2295 2296 /* Supress unwanted interrupts */ 2297 if (!(ifp->if_flags & IFF_UP)) { 2298 if (CSR_READ_4(sc, DC_ISR) & DC_INTRS) 2299 dc_stop(sc); 2300 return; 2301 } 2302 2303 /* Disable interrupts. */ 2304 CSR_WRITE_4(sc, DC_IMR, 0x00000000); 2305 2306 while((status = CSR_READ_4(sc, DC_ISR)) & DC_INTRS) { 2307 2308 CSR_WRITE_4(sc, DC_ISR, status); 2309 2310 if (status & DC_ISR_RX_OK) { 2311 int curpkts; 2312 curpkts = ifp->if_ipackets; 2313 dc_rxeof(sc); 2314 if (curpkts == ifp->if_ipackets) { 2315 while(dc_rx_resync(sc)) 2316 dc_rxeof(sc); 2317 } 2318 } 2319 2320 if (status & (DC_ISR_TX_OK|DC_ISR_TX_NOBUF)) 2321 dc_txeof(sc); 2322 2323 if (status & DC_ISR_TX_IDLE) { 2324 dc_txeof(sc); 2325 if (sc->dc_cdata.dc_tx_cnt) { 2326 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_TX_ON); 2327 CSR_WRITE_4(sc, DC_TXSTART, 0xFFFFFFFF); 2328 } 2329 } 2330 2331 if (status & DC_ISR_TX_UNDERRUN) { 2332 u_int32_t cfg; 2333 2334 printf("dc%d: TX underrun -- ", sc->dc_unit); 2335 if (DC_IS_DAVICOM(sc) || DC_IS_INTEL(sc)) 2336 dc_init(sc); 2337 cfg = CSR_READ_4(sc, DC_NETCFG); 2338 cfg &= ~DC_NETCFG_TX_THRESH; 2339 if (sc->dc_txthresh == DC_TXTHRESH_160BYTES) { 2340 printf("using store and forward mode\n"); 2341 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_STORENFWD); 2342 } else if (sc->dc_flags & DC_TX_STORENFWD) { 2343 printf("resetting\n"); 2344 } else { 2345 sc->dc_txthresh += 0x4000; 2346 printf("increasing TX threshold\n"); 2347 CSR_WRITE_4(sc, DC_NETCFG, cfg); 2348 DC_SETBIT(sc, DC_NETCFG, sc->dc_txthresh); 2349 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_STORENFWD); 2350 } 2351 } 2352 2353 if ((status & DC_ISR_RX_WATDOGTIMEO) 2354 || (status & DC_ISR_RX_NOBUF)) { 2355 int curpkts; 2356 curpkts = ifp->if_ipackets; 2357 dc_rxeof(sc); 2358 if (curpkts == ifp->if_ipackets) { 2359 while(dc_rx_resync(sc)) 2360 dc_rxeof(sc); 2361 } 2362 } 2363 2364 if (status & DC_ISR_BUS_ERR) { 2365 dc_reset(sc); 2366 dc_init(sc); 2367 } 2368 } 2369 2370 /* Re-enable interrupts. */ 2371 CSR_WRITE_4(sc, DC_IMR, DC_INTRS); 2372 2373 if (ifp->if_snd.ifq_head != NULL) 2374 dc_start(ifp); 2375 2376 return; 2377 } 2378 2379 /* 2380 * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data 2381 * pointers to the fragment pointers. 2382 */ 2383 static int dc_encap(sc, m_head, txidx) 2384 struct dc_softc *sc; 2385 struct mbuf *m_head; 2386 u_int32_t *txidx; 2387 { 2388 struct dc_desc *f = NULL; 2389 struct mbuf *m; 2390 int frag, cur, cnt = 0; 2391 2392 /* 2393 * Start packing the mbufs in this chain into 2394 * the fragment pointers. Stop when we run out 2395 * of fragments or hit the end of the mbuf chain. 2396 */ 2397 m = m_head; 2398 cur = frag = *txidx; 2399 2400 for (m = m_head; m != NULL; m = m->m_next) { 2401 if (m->m_len != 0) { 2402 if (sc->dc_flags & DC_TX_ADMTEK_WAR) { 2403 if (*txidx != sc->dc_cdata.dc_tx_prod && 2404 frag == (DC_TX_LIST_CNT - 1)) 2405 return(ENOBUFS); 2406 } 2407 if ((DC_TX_LIST_CNT - 2408 (sc->dc_cdata.dc_tx_cnt + cnt)) < 5) 2409 return(ENOBUFS); 2410 2411 f = &sc->dc_ldata->dc_tx_list[frag]; 2412 f->dc_ctl = DC_TXCTL_TLINK | m->m_len; 2413 if (cnt == 0) { 2414 f->dc_status = 0; 2415 f->dc_ctl |= DC_TXCTL_FIRSTFRAG; 2416 } else 2417 f->dc_status = DC_TXSTAT_OWN; 2418 f->dc_data = vtophys(mtod(m, vm_offset_t)); 2419 cur = frag; 2420 DC_INC(frag, DC_TX_LIST_CNT); 2421 cnt++; 2422 } 2423 } 2424 2425 if (m != NULL) 2426 return(ENOBUFS); 2427 2428 sc->dc_cdata.dc_tx_cnt += cnt; 2429 sc->dc_cdata.dc_tx_chain[cur] = m_head; 2430 sc->dc_ldata->dc_tx_list[cur].dc_ctl |= DC_TXCTL_LASTFRAG; 2431 if (sc->dc_flags & DC_TX_INTR_FIRSTFRAG) 2432 sc->dc_ldata->dc_tx_list[*txidx].dc_ctl |= DC_TXCTL_FINT; 2433 if (sc->dc_flags & DC_TX_INTR_ALWAYS) 2434 sc->dc_ldata->dc_tx_list[cur].dc_ctl |= DC_TXCTL_FINT; 2435 if (sc->dc_flags & DC_TX_USE_TX_INTR && sc->dc_cdata.dc_tx_cnt > 64) 2436 sc->dc_ldata->dc_tx_list[cur].dc_ctl |= DC_TXCTL_FINT; 2437 sc->dc_ldata->dc_tx_list[*txidx].dc_status = DC_TXSTAT_OWN; 2438 *txidx = frag; 2439 2440 return(0); 2441 } 2442 2443 /* 2444 * Coalesce an mbuf chain into a single mbuf cluster buffer. 2445 * Needed for some really badly behaved chips that just can't 2446 * do scatter/gather correctly. 2447 */ 2448 static int dc_coal(sc, m_head) 2449 struct dc_softc *sc; 2450 struct mbuf **m_head; 2451 { 2452 struct mbuf *m_new, *m; 2453 2454 m = *m_head; 2455 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 2456 if (m_new == NULL) { 2457 printf("dc%d: no memory for tx list", sc->dc_unit); 2458 return(ENOBUFS); 2459 } 2460 if (m->m_pkthdr.len > MHLEN) { 2461 MCLGET(m_new, M_DONTWAIT); 2462 if (!(m_new->m_flags & M_EXT)) { 2463 m_freem(m_new); 2464 printf("dc%d: no memory for tx list", sc->dc_unit); 2465 return(ENOBUFS); 2466 } 2467 } 2468 m_copydata(m, 0, m->m_pkthdr.len, mtod(m_new, caddr_t)); 2469 m_new->m_pkthdr.len = m_new->m_len = m->m_pkthdr.len; 2470 m_freem(m); 2471 *m_head = m_new; 2472 2473 return(0); 2474 } 2475 2476 /* 2477 * Main transmit routine. To avoid having to do mbuf copies, we put pointers 2478 * to the mbuf data regions directly in the transmit lists. We also save a 2479 * copy of the pointers since the transmit list fragment pointers are 2480 * physical addresses. 2481 */ 2482 2483 static void dc_start(ifp) 2484 struct ifnet *ifp; 2485 { 2486 struct dc_softc *sc; 2487 struct mbuf *m_head = NULL; 2488 int idx; 2489 2490 sc = ifp->if_softc; 2491 2492 if (!sc->dc_link) 2493 return; 2494 2495 if (ifp->if_flags & IFF_OACTIVE) 2496 return; 2497 2498 idx = sc->dc_cdata.dc_tx_prod; 2499 2500 while(sc->dc_cdata.dc_tx_chain[idx] == NULL) { 2501 IF_DEQUEUE(&ifp->if_snd, m_head); 2502 if (m_head == NULL) 2503 break; 2504 2505 if (sc->dc_flags & DC_TX_COALESCE) { 2506 if (dc_coal(sc, &m_head)) { 2507 IF_PREPEND(&ifp->if_snd, m_head); 2508 ifp->if_flags |= IFF_OACTIVE; 2509 break; 2510 } 2511 } 2512 2513 if (dc_encap(sc, m_head, &idx)) { 2514 IF_PREPEND(&ifp->if_snd, m_head); 2515 ifp->if_flags |= IFF_OACTIVE; 2516 break; 2517 } 2518 2519 /* 2520 * If there's a BPF listener, bounce a copy of this frame 2521 * to him. 2522 */ 2523 if (ifp->if_bpf) 2524 bpf_mtap(ifp, m_head); 2525 } 2526 2527 /* Transmit */ 2528 sc->dc_cdata.dc_tx_prod = idx; 2529 if (!(sc->dc_flags & DC_TX_POLL)) 2530 CSR_WRITE_4(sc, DC_TXSTART, 0xFFFFFFFF); 2531 2532 /* 2533 * Set a timeout in case the chip goes out to lunch. 2534 */ 2535 ifp->if_timer = 5; 2536 2537 return; 2538 } 2539 2540 static void dc_init(xsc) 2541 void *xsc; 2542 { 2543 struct dc_softc *sc = xsc; 2544 struct ifnet *ifp = &sc->arpcom.ac_if; 2545 struct mii_data *mii; 2546 int s; 2547 2548 s = splimp(); 2549 2550 mii = device_get_softc(sc->dc_miibus); 2551 2552 /* 2553 * Cancel pending I/O and free all RX/TX buffers. 2554 */ 2555 dc_stop(sc); 2556 dc_reset(sc); 2557 2558 /* 2559 * Set cache alignment and burst length. 2560 */ 2561 if (DC_IS_ASIX(sc) || DC_IS_DAVICOM(sc)) 2562 CSR_WRITE_4(sc, DC_BUSCTL, 0); 2563 else 2564 CSR_WRITE_4(sc, DC_BUSCTL, DC_BUSCTL_MRME|DC_BUSCTL_MRLE); 2565 if (DC_IS_DAVICOM(sc) || DC_IS_INTEL(sc)) { 2566 DC_SETBIT(sc, DC_BUSCTL, DC_BURSTLEN_USECA); 2567 } else { 2568 DC_SETBIT(sc, DC_BUSCTL, DC_BURSTLEN_16LONG); 2569 } 2570 if (sc->dc_flags & DC_TX_POLL) 2571 DC_SETBIT(sc, DC_BUSCTL, DC_TXPOLL_1); 2572 switch(sc->dc_cachesize) { 2573 case 32: 2574 DC_SETBIT(sc, DC_BUSCTL, DC_CACHEALIGN_32LONG); 2575 break; 2576 case 16: 2577 DC_SETBIT(sc, DC_BUSCTL, DC_CACHEALIGN_16LONG); 2578 break; 2579 case 8: 2580 DC_SETBIT(sc, DC_BUSCTL, DC_CACHEALIGN_8LONG); 2581 break; 2582 case 0: 2583 default: 2584 DC_SETBIT(sc, DC_BUSCTL, DC_CACHEALIGN_NONE); 2585 break; 2586 } 2587 2588 if (sc->dc_flags & DC_TX_STORENFWD) 2589 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_STORENFWD); 2590 else { 2591 if (sc->dc_txthresh == DC_TXTHRESH_160BYTES) { 2592 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_STORENFWD); 2593 } else { 2594 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_STORENFWD); 2595 DC_SETBIT(sc, DC_NETCFG, sc->dc_txthresh); 2596 } 2597 } 2598 2599 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_NO_RXCRC); 2600 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_TX_BACKOFF); 2601 2602 if (DC_IS_MACRONIX(sc) || DC_IS_PNICII(sc)) { 2603 /* 2604 * The app notes for the 98713 and 98715A say that 2605 * in order to have the chips operate properly, a magic 2606 * number must be written to CSR16. Macronix does not 2607 * document the meaning of these bits so there's no way 2608 * to know exactly what they do. The 98713 has a magic 2609 * number all its own; the rest all use a different one. 2610 */ 2611 DC_CLRBIT(sc, DC_MX_MAGICPACKET, 0xFFFF0000); 2612 if (sc->dc_type == DC_TYPE_98713) 2613 DC_SETBIT(sc, DC_MX_MAGICPACKET, DC_MX_MAGIC_98713); 2614 else 2615 DC_SETBIT(sc, DC_MX_MAGICPACKET, DC_MX_MAGIC_98715); 2616 } 2617 2618 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_TX_THRESH); 2619 DC_SETBIT(sc, DC_NETCFG, DC_TXTHRESH_72BYTES); 2620 2621 /* Init circular RX list. */ 2622 if (dc_list_rx_init(sc) == ENOBUFS) { 2623 printf("dc%d: initialization failed: no " 2624 "memory for rx buffers\n", sc->dc_unit); 2625 dc_stop(sc); 2626 (void)splx(s); 2627 return; 2628 } 2629 2630 /* 2631 * Init tx descriptors. 2632 */ 2633 dc_list_tx_init(sc); 2634 2635 /* 2636 * Load the address of the RX list. 2637 */ 2638 CSR_WRITE_4(sc, DC_RXADDR, vtophys(&sc->dc_ldata->dc_rx_list[0])); 2639 CSR_WRITE_4(sc, DC_TXADDR, vtophys(&sc->dc_ldata->dc_tx_list[0])); 2640 2641 /* 2642 * Enable interrupts. 2643 */ 2644 CSR_WRITE_4(sc, DC_IMR, DC_INTRS); 2645 CSR_WRITE_4(sc, DC_ISR, 0xFFFFFFFF); 2646 2647 /* Enable transmitter. */ 2648 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_TX_ON); 2649 2650 /* 2651 * Load the RX/multicast filter. We do this sort of late 2652 * because the filter programming scheme on the 21143 and 2653 * some clones requires DMAing a setup frame via the TX 2654 * engine, and we need the transmitter enabled for that. 2655 */ 2656 dc_setfilt(sc); 2657 2658 /* Enable receiver. */ 2659 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_ON); 2660 CSR_WRITE_4(sc, DC_RXSTART, 0xFFFFFFFF); 2661 2662 mii_mediachg(mii); 2663 dc_setcfg(sc, sc->dc_if_media); 2664 2665 ifp->if_flags |= IFF_RUNNING; 2666 ifp->if_flags &= ~IFF_OACTIVE; 2667 2668 (void)splx(s); 2669 2670 sc->dc_stat_ch = timeout(dc_tick, sc, hz); 2671 2672 return; 2673 } 2674 2675 /* 2676 * Set media options. 2677 */ 2678 static int dc_ifmedia_upd(ifp) 2679 struct ifnet *ifp; 2680 { 2681 struct dc_softc *sc; 2682 struct mii_data *mii; 2683 struct ifmedia *ifm; 2684 2685 sc = ifp->if_softc; 2686 mii = device_get_softc(sc->dc_miibus); 2687 mii_mediachg(mii); 2688 ifm = &mii->mii_media; 2689 2690 if (DC_IS_DAVICOM(sc) && 2691 IFM_SUBTYPE(ifm->ifm_media) == IFM_homePNA) 2692 dc_setcfg(sc, ifm->ifm_media); 2693 else 2694 sc->dc_link = 0; 2695 2696 return(0); 2697 } 2698 2699 /* 2700 * Report current media status. 2701 */ 2702 static void dc_ifmedia_sts(ifp, ifmr) 2703 struct ifnet *ifp; 2704 struct ifmediareq *ifmr; 2705 { 2706 struct dc_softc *sc; 2707 struct mii_data *mii; 2708 struct ifmedia *ifm; 2709 2710 sc = ifp->if_softc; 2711 mii = device_get_softc(sc->dc_miibus); 2712 mii_pollstat(mii); 2713 ifm = &mii->mii_media; 2714 if (DC_IS_DAVICOM(sc)) { 2715 if (IFM_SUBTYPE(ifm->ifm_media) == IFM_homePNA) { 2716 ifmr->ifm_active = ifm->ifm_media; 2717 ifmr->ifm_status = 0; 2718 return; 2719 } 2720 } 2721 ifmr->ifm_active = mii->mii_media_active; 2722 ifmr->ifm_status = mii->mii_media_status; 2723 2724 return; 2725 } 2726 2727 static int dc_ioctl(ifp, command, data) 2728 struct ifnet *ifp; 2729 u_long command; 2730 caddr_t data; 2731 { 2732 struct dc_softc *sc = ifp->if_softc; 2733 struct ifreq *ifr = (struct ifreq *) data; 2734 struct mii_data *mii; 2735 int s, error = 0; 2736 2737 s = splimp(); 2738 2739 switch(command) { 2740 case SIOCSIFADDR: 2741 case SIOCGIFADDR: 2742 case SIOCSIFMTU: 2743 error = ether_ioctl(ifp, command, data); 2744 break; 2745 case SIOCSIFFLAGS: 2746 if (ifp->if_flags & IFF_UP) { 2747 if (ifp->if_flags & IFF_RUNNING && 2748 ifp->if_flags & IFF_PROMISC && 2749 !(sc->dc_if_flags & IFF_PROMISC)) { 2750 dc_setfilt(sc); 2751 } else if (ifp->if_flags & IFF_RUNNING && 2752 !(ifp->if_flags & IFF_PROMISC) && 2753 sc->dc_if_flags & IFF_PROMISC) { 2754 dc_setfilt(sc); 2755 } else if (!(ifp->if_flags & IFF_RUNNING)) { 2756 sc->dc_txthresh = 0; 2757 dc_init(sc); 2758 } 2759 } else { 2760 if (ifp->if_flags & IFF_RUNNING) 2761 dc_stop(sc); 2762 } 2763 sc->dc_if_flags = ifp->if_flags; 2764 error = 0; 2765 break; 2766 case SIOCADDMULTI: 2767 case SIOCDELMULTI: 2768 dc_setfilt(sc); 2769 error = 0; 2770 break; 2771 case SIOCGIFMEDIA: 2772 case SIOCSIFMEDIA: 2773 mii = device_get_softc(sc->dc_miibus); 2774 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 2775 break; 2776 default: 2777 error = EINVAL; 2778 break; 2779 } 2780 2781 (void)splx(s); 2782 2783 return(error); 2784 } 2785 2786 static void dc_watchdog(ifp) 2787 struct ifnet *ifp; 2788 { 2789 struct dc_softc *sc; 2790 2791 sc = ifp->if_softc; 2792 2793 ifp->if_oerrors++; 2794 printf("dc%d: watchdog timeout\n", sc->dc_unit); 2795 2796 dc_stop(sc); 2797 dc_reset(sc); 2798 dc_init(sc); 2799 2800 if (ifp->if_snd.ifq_head != NULL) 2801 dc_start(ifp); 2802 2803 return; 2804 } 2805 2806 /* 2807 * Stop the adapter and free any mbufs allocated to the 2808 * RX and TX lists. 2809 */ 2810 static void dc_stop(sc) 2811 struct dc_softc *sc; 2812 { 2813 register int i; 2814 struct ifnet *ifp; 2815 2816 ifp = &sc->arpcom.ac_if; 2817 ifp->if_timer = 0; 2818 2819 untimeout(dc_tick, sc, sc->dc_stat_ch); 2820 2821 DC_CLRBIT(sc, DC_NETCFG, (DC_NETCFG_RX_ON|DC_NETCFG_TX_ON)); 2822 CSR_WRITE_4(sc, DC_IMR, 0x00000000); 2823 CSR_WRITE_4(sc, DC_TXADDR, 0x00000000); 2824 CSR_WRITE_4(sc, DC_RXADDR, 0x00000000); 2825 sc->dc_link = 0; 2826 2827 /* 2828 * Free data in the RX lists. 2829 */ 2830 for (i = 0; i < DC_RX_LIST_CNT; i++) { 2831 if (sc->dc_cdata.dc_rx_chain[i] != NULL) { 2832 m_freem(sc->dc_cdata.dc_rx_chain[i]); 2833 sc->dc_cdata.dc_rx_chain[i] = NULL; 2834 } 2835 } 2836 bzero((char *)&sc->dc_ldata->dc_rx_list, 2837 sizeof(sc->dc_ldata->dc_rx_list)); 2838 2839 /* 2840 * Free the TX list buffers. 2841 */ 2842 for (i = 0; i < DC_TX_LIST_CNT; i++) { 2843 if (sc->dc_cdata.dc_tx_chain[i] != NULL) { 2844 if (sc->dc_ldata->dc_tx_list[i].dc_ctl & 2845 DC_TXCTL_SETUP) { 2846 sc->dc_cdata.dc_tx_chain[i] = NULL; 2847 continue; 2848 } 2849 m_freem(sc->dc_cdata.dc_tx_chain[i]); 2850 sc->dc_cdata.dc_tx_chain[i] = NULL; 2851 } 2852 } 2853 2854 bzero((char *)&sc->dc_ldata->dc_tx_list, 2855 sizeof(sc->dc_ldata->dc_tx_list)); 2856 2857 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 2858 2859 return; 2860 } 2861 2862 /* 2863 * Stop all chip I/O so that the kernel's probe routines don't 2864 * get confused by errant DMAs when rebooting. 2865 */ 2866 static void dc_shutdown(dev) 2867 device_t dev; 2868 { 2869 struct dc_softc *sc; 2870 2871 sc = device_get_softc(dev); 2872 2873 dc_stop(sc); 2874 2875 return; 2876 } 2877