1 /* 2 * Copyright (c) 1997, 1998, 1999 3 * Bill Paul <wpaul@ee.columbia.edu>. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 3. All advertising materials mentioning features or use of this software 14 * must display the following acknowledgement: 15 * This product includes software developed by Bill Paul. 16 * 4. Neither the name of the author nor the names of any co-contributors 17 * may be used to endorse or promote products derived from this software 18 * without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30 * THE POSSIBILITY OF SUCH DAMAGE. 31 * 32 * $FreeBSD$ 33 */ 34 35 /* 36 * DEC "tulip" clone ethernet driver. Supports the DEC/Intel 21143 37 * series chips and several workalikes including the following: 38 * 39 * Macronix 98713/98715/98725/98727/98732 PMAC (www.macronix.com) 40 * Macronix/Lite-On 82c115 PNIC II (www.macronix.com) 41 * Lite-On 82c168/82c169 PNIC (www.litecom.com) 42 * ASIX Electronics AX88140A (www.asix.com.tw) 43 * ASIX Electronics AX88141 (www.asix.com.tw) 44 * ADMtek AL981 (www.admtek.com.tw) 45 * ADMtek AN985 (www.admtek.com.tw) 46 * Davicom DM9100, DM9102, DM9102A (www.davicom8.com) 47 * Accton EN1217 (www.accton.com) 48 * Xircom X3201 (www.xircom.com) 49 * 50 * Datasheets for the 21143 are available at developer.intel.com. 51 * Datasheets for the clone parts can be found at their respective sites. 52 * (Except for the PNIC; see www.freebsd.org/~wpaul/PNIC/pnic.ps.gz.) 53 * The PNIC II is essentially a Macronix 98715A chip; the only difference 54 * worth noting is that its multicast hash table is only 128 bits wide 55 * instead of 512. 56 * 57 * Written by Bill Paul <wpaul@ee.columbia.edu> 58 * Electrical Engineering Department 59 * Columbia University, New York City 60 */ 61 62 /* 63 * The Intel 21143 is the successor to the DEC 21140. It is basically 64 * the same as the 21140 but with a few new features. The 21143 supports 65 * three kinds of media attachments: 66 * 67 * o MII port, for 10Mbps and 100Mbps support and NWAY 68 * autonegotiation provided by an external PHY. 69 * o SYM port, for symbol mode 100Mbps support. 70 * o 10baseT port. 71 * o AUI/BNC port. 72 * 73 * The 100Mbps SYM port and 10baseT port can be used together in 74 * combination with the internal NWAY support to create a 10/100 75 * autosensing configuration. 76 * 77 * Note that not all tulip workalikes are handled in this driver: we only 78 * deal with those which are relatively well behaved. The Winbond is 79 * handled separately due to its different register offsets and the 80 * special handling needed for its various bugs. The PNIC is handled 81 * here, but I'm not thrilled about it. 82 * 83 * All of the workalike chips use some form of MII transceiver support 84 * with the exception of the Macronix chips, which also have a SYM port. 85 * The ASIX AX88140A is also documented to have a SYM port, but all 86 * the cards I've seen use an MII transceiver, probably because the 87 * AX88140A doesn't support internal NWAY. 88 */ 89 90 #include <sys/param.h> 91 #include <sys/systm.h> 92 #include <sys/sockio.h> 93 #include <sys/mbuf.h> 94 #include <sys/malloc.h> 95 #include <sys/kernel.h> 96 #include <sys/socket.h> 97 98 #include <net/if.h> 99 #include <net/if_arp.h> 100 #include <net/ethernet.h> 101 #include <net/if_dl.h> 102 #include <net/if_media.h> 103 104 #include <net/bpf.h> 105 106 #include <vm/vm.h> /* for vtophys */ 107 #include <vm/pmap.h> /* for vtophys */ 108 #include <machine/bus_pio.h> 109 #include <machine/bus_memio.h> 110 #include <machine/bus.h> 111 #include <machine/resource.h> 112 #include <sys/bus.h> 113 #include <sys/rman.h> 114 115 #include <dev/mii/mii.h> 116 #include <dev/mii/miivar.h> 117 118 #include <pci/pcireg.h> 119 #include <pci/pcivar.h> 120 121 #define DC_USEIOSPACE 122 #ifdef __alpha__ 123 #define SRM_MEDIA 124 #endif 125 126 #include <pci/if_dcreg.h> 127 128 MODULE_DEPEND(dc, miibus, 1, 1, 1); 129 130 /* "controller miibus0" required. See GENERIC if you get errors here. */ 131 #include "miibus_if.h" 132 133 #ifndef lint 134 static const char rcsid[] = 135 "$FreeBSD$"; 136 #endif 137 138 /* 139 * Various supported device vendors/types and their names. 140 */ 141 static struct dc_type dc_devs[] = { 142 { DC_VENDORID_DEC, DC_DEVICEID_21143, 143 "Intel 21143 10/100BaseTX" }, 144 { DC_VENDORID_DAVICOM, DC_DEVICEID_DM9100, 145 "Davicom DM9100 10/100BaseTX" }, 146 { DC_VENDORID_DAVICOM, DC_DEVICEID_DM9102, 147 "Davicom DM9102 10/100BaseTX" }, 148 { DC_VENDORID_DAVICOM, DC_DEVICEID_DM9102, 149 "Davicom DM9102A 10/100BaseTX" }, 150 { DC_VENDORID_ADMTEK, DC_DEVICEID_AL981, 151 "ADMtek AL981 10/100BaseTX" }, 152 { DC_VENDORID_ADMTEK, DC_DEVICEID_AN985, 153 "ADMtek AN985 10/100BaseTX" }, 154 { DC_VENDORID_ASIX, DC_DEVICEID_AX88140A, 155 "ASIX AX88140A 10/100BaseTX" }, 156 { DC_VENDORID_ASIX, DC_DEVICEID_AX88140A, 157 "ASIX AX88141 10/100BaseTX" }, 158 { DC_VENDORID_MX, DC_DEVICEID_98713, 159 "Macronix 98713 10/100BaseTX" }, 160 { DC_VENDORID_MX, DC_DEVICEID_98713, 161 "Macronix 98713A 10/100BaseTX" }, 162 { DC_VENDORID_CP, DC_DEVICEID_98713_CP, 163 "Compex RL100-TX 10/100BaseTX" }, 164 { DC_VENDORID_CP, DC_DEVICEID_98713_CP, 165 "Compex RL100-TX 10/100BaseTX" }, 166 { DC_VENDORID_MX, DC_DEVICEID_987x5, 167 "Macronix 98715/98715A 10/100BaseTX" }, 168 { DC_VENDORID_MX, DC_DEVICEID_987x5, 169 "Macronix 98715AEC-C 10/100BaseTX" }, 170 { DC_VENDORID_MX, DC_DEVICEID_987x5, 171 "Macronix 98725 10/100BaseTX" }, 172 { DC_VENDORID_MX, DC_DEVICEID_98727, 173 "Macronix 98727/98732 10/100BaseTX" }, 174 { DC_VENDORID_LO, DC_DEVICEID_82C115, 175 "LC82C115 PNIC II 10/100BaseTX" }, 176 { DC_VENDORID_LO, DC_DEVICEID_82C168, 177 "82c168 PNIC 10/100BaseTX" }, 178 { DC_VENDORID_LO, DC_DEVICEID_82C168, 179 "82c169 PNIC 10/100BaseTX" }, 180 { DC_VENDORID_ACCTON, DC_DEVICEID_EN1217, 181 "Accton EN1217 10/100BaseTX" }, 182 { DC_VENDORID_XIRCOM, DC_DEVICEID_X3201, 183 "Xircom X3201 10/100BaseTX" }, 184 { 0, 0, NULL } 185 }; 186 187 static int dc_probe __P((device_t)); 188 static int dc_attach __P((device_t)); 189 static int dc_detach __P((device_t)); 190 static void dc_acpi __P((device_t)); 191 static struct dc_type *dc_devtype __P((device_t)); 192 static int dc_newbuf __P((struct dc_softc *, int, struct mbuf *)); 193 static int dc_encap __P((struct dc_softc *, struct mbuf *, 194 u_int32_t *)); 195 static int dc_coal __P((struct dc_softc *, struct mbuf **)); 196 static void dc_pnic_rx_bug_war __P((struct dc_softc *, int)); 197 static int dc_rx_resync __P((struct dc_softc *)); 198 static void dc_rxeof __P((struct dc_softc *)); 199 static void dc_txeof __P((struct dc_softc *)); 200 static void dc_tick __P((void *)); 201 static void dc_intr __P((void *)); 202 static void dc_start __P((struct ifnet *)); 203 static int dc_ioctl __P((struct ifnet *, u_long, caddr_t)); 204 static void dc_init __P((void *)); 205 static void dc_stop __P((struct dc_softc *)); 206 static void dc_watchdog __P((struct ifnet *)); 207 static void dc_shutdown __P((device_t)); 208 static int dc_ifmedia_upd __P((struct ifnet *)); 209 static void dc_ifmedia_sts __P((struct ifnet *, struct ifmediareq *)); 210 211 static void dc_delay __P((struct dc_softc *)); 212 static void dc_eeprom_idle __P((struct dc_softc *)); 213 static void dc_eeprom_putbyte __P((struct dc_softc *, int)); 214 static void dc_eeprom_getword __P((struct dc_softc *, int, u_int16_t *)); 215 static void dc_eeprom_getword_pnic 216 __P((struct dc_softc *, int, u_int16_t *)); 217 static void dc_eeprom_getword_xircom 218 __P((struct dc_softc *, int, u_int16_t *)); 219 static void dc_read_eeprom __P((struct dc_softc *, caddr_t, int, 220 int, int)); 221 222 static void dc_mii_writebit __P((struct dc_softc *, int)); 223 static int dc_mii_readbit __P((struct dc_softc *)); 224 static void dc_mii_sync __P((struct dc_softc *)); 225 static void dc_mii_send __P((struct dc_softc *, u_int32_t, int)); 226 static int dc_mii_readreg __P((struct dc_softc *, struct dc_mii_frame *)); 227 static int dc_mii_writereg __P((struct dc_softc *, struct dc_mii_frame *)); 228 static int dc_miibus_readreg __P((device_t, int, int)); 229 static int dc_miibus_writereg __P((device_t, int, int, int)); 230 static void dc_miibus_statchg __P((device_t)); 231 static void dc_miibus_mediainit __P((device_t)); 232 233 static void dc_setcfg __P((struct dc_softc *, int)); 234 static u_int32_t dc_crc_le __P((struct dc_softc *, caddr_t)); 235 static u_int32_t dc_crc_be __P((caddr_t)); 236 static void dc_setfilt_21143 __P((struct dc_softc *)); 237 static void dc_setfilt_asix __P((struct dc_softc *)); 238 static void dc_setfilt_admtek __P((struct dc_softc *)); 239 static void dc_setfilt_xircom __P((struct dc_softc *)); 240 241 static void dc_setfilt __P((struct dc_softc *)); 242 243 static void dc_reset __P((struct dc_softc *)); 244 static int dc_list_rx_init __P((struct dc_softc *)); 245 static int dc_list_tx_init __P((struct dc_softc *)); 246 247 static void dc_parse_21143_srom __P((struct dc_softc *)); 248 static void dc_decode_leaf_sia __P((struct dc_softc *, 249 struct dc_eblock_sia *)); 250 static void dc_decode_leaf_mii __P((struct dc_softc *, 251 struct dc_eblock_mii *)); 252 static void dc_decode_leaf_sym __P((struct dc_softc *, 253 struct dc_eblock_sym *)); 254 static void dc_apply_fixup __P((struct dc_softc *, int)); 255 256 #ifdef DC_USEIOSPACE 257 #define DC_RES SYS_RES_IOPORT 258 #define DC_RID DC_PCI_CFBIO 259 #else 260 #define DC_RES SYS_RES_MEMORY 261 #define DC_RID DC_PCI_CFBMA 262 #endif 263 264 static device_method_t dc_methods[] = { 265 /* Device interface */ 266 DEVMETHOD(device_probe, dc_probe), 267 DEVMETHOD(device_attach, dc_attach), 268 DEVMETHOD(device_detach, dc_detach), 269 DEVMETHOD(device_shutdown, dc_shutdown), 270 271 /* bus interface */ 272 DEVMETHOD(bus_print_child, bus_generic_print_child), 273 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 274 275 /* MII interface */ 276 DEVMETHOD(miibus_readreg, dc_miibus_readreg), 277 DEVMETHOD(miibus_writereg, dc_miibus_writereg), 278 DEVMETHOD(miibus_statchg, dc_miibus_statchg), 279 DEVMETHOD(miibus_mediainit, dc_miibus_mediainit), 280 281 { 0, 0 } 282 }; 283 284 static driver_t dc_driver = { 285 "dc", 286 dc_methods, 287 sizeof(struct dc_softc) 288 }; 289 290 static devclass_t dc_devclass; 291 292 DRIVER_MODULE(if_dc, cardbus, dc_driver, dc_devclass, 0, 0); 293 DRIVER_MODULE(if_dc, pci, dc_driver, dc_devclass, 0, 0); 294 DRIVER_MODULE(miibus, dc, miibus_driver, miibus_devclass, 0, 0); 295 296 #define DC_SETBIT(sc, reg, x) \ 297 CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) | (x)) 298 299 #define DC_CLRBIT(sc, reg, x) \ 300 CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) & ~(x)) 301 302 #define SIO_SET(x) DC_SETBIT(sc, DC_SIO, (x)) 303 #define SIO_CLR(x) DC_CLRBIT(sc, DC_SIO, (x)) 304 305 static void dc_delay(sc) 306 struct dc_softc *sc; 307 { 308 int idx; 309 310 for (idx = (300 / 33) + 1; idx > 0; idx--) 311 CSR_READ_4(sc, DC_BUSCTL); 312 } 313 314 static void dc_eeprom_idle(sc) 315 struct dc_softc *sc; 316 { 317 register int i; 318 319 CSR_WRITE_4(sc, DC_SIO, DC_SIO_EESEL); 320 dc_delay(sc); 321 DC_SETBIT(sc, DC_SIO, DC_SIO_ROMCTL_READ); 322 dc_delay(sc); 323 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); 324 dc_delay(sc); 325 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CS); 326 dc_delay(sc); 327 328 for (i = 0; i < 25; i++) { 329 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); 330 dc_delay(sc); 331 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CLK); 332 dc_delay(sc); 333 } 334 335 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); 336 dc_delay(sc); 337 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CS); 338 dc_delay(sc); 339 CSR_WRITE_4(sc, DC_SIO, 0x00000000); 340 341 return; 342 } 343 344 /* 345 * Send a read command and address to the EEPROM, check for ACK. 346 */ 347 static void dc_eeprom_putbyte(sc, addr) 348 struct dc_softc *sc; 349 int addr; 350 { 351 register int d, i; 352 353 /* 354 * The AN985 has a 93C66 EEPROM on it instead of 355 * a 93C46. It uses a different bit sequence for 356 * specifying the "read" opcode. 357 */ 358 if (DC_IS_CENTAUR(sc)) 359 d = addr | (DC_EECMD_READ << 2); 360 else 361 d = addr | DC_EECMD_READ; 362 363 /* 364 * Feed in each bit and strobe the clock. 365 */ 366 for (i = 0x400; i; i >>= 1) { 367 if (d & i) { 368 SIO_SET(DC_SIO_EE_DATAIN); 369 } else { 370 SIO_CLR(DC_SIO_EE_DATAIN); 371 } 372 dc_delay(sc); 373 SIO_SET(DC_SIO_EE_CLK); 374 dc_delay(sc); 375 SIO_CLR(DC_SIO_EE_CLK); 376 dc_delay(sc); 377 } 378 379 return; 380 } 381 382 /* 383 * Read a word of data stored in the EEPROM at address 'addr.' 384 * The PNIC 82c168/82c169 has its own non-standard way to read 385 * the EEPROM. 386 */ 387 static void dc_eeprom_getword_pnic(sc, addr, dest) 388 struct dc_softc *sc; 389 int addr; 390 u_int16_t *dest; 391 { 392 register int i; 393 u_int32_t r; 394 395 CSR_WRITE_4(sc, DC_PN_SIOCTL, DC_PN_EEOPCODE_READ|addr); 396 397 for (i = 0; i < DC_TIMEOUT; i++) { 398 DELAY(1); 399 r = CSR_READ_4(sc, DC_SIO); 400 if (!(r & DC_PN_SIOCTL_BUSY)) { 401 *dest = (u_int16_t)(r & 0xFFFF); 402 return; 403 } 404 } 405 406 return; 407 } 408 409 /* 410 * Read a word of data stored in the EEPROM at address 'addr.' 411 * The Xircom X3201 has its own non-standard way to read 412 * the EEPROM, too. 413 */ 414 static void dc_eeprom_getword_xircom(sc, addr, dest) 415 struct dc_softc *sc; 416 int addr; 417 u_int16_t *dest; 418 { 419 SIO_SET(DC_SIO_ROMSEL | DC_SIO_ROMCTL_READ); 420 421 addr *= 2; 422 CSR_WRITE_4(sc, DC_ROM, addr | 0x160); 423 *dest = (u_int16_t)CSR_READ_4(sc, DC_SIO)&0xff; 424 addr += 1; 425 CSR_WRITE_4(sc, DC_ROM, addr | 0x160); 426 *dest |= ((u_int16_t)CSR_READ_4(sc, DC_SIO)&0xff) << 8; 427 428 SIO_CLR(DC_SIO_ROMSEL | DC_SIO_ROMCTL_READ); 429 return; 430 } 431 432 /* 433 * Read a word of data stored in the EEPROM at address 'addr.' 434 */ 435 static void dc_eeprom_getword(sc, addr, dest) 436 struct dc_softc *sc; 437 int addr; 438 u_int16_t *dest; 439 { 440 register int i; 441 u_int16_t word = 0; 442 443 /* Force EEPROM to idle state. */ 444 dc_eeprom_idle(sc); 445 446 /* Enter EEPROM access mode. */ 447 CSR_WRITE_4(sc, DC_SIO, DC_SIO_EESEL); 448 dc_delay(sc); 449 DC_SETBIT(sc, DC_SIO, DC_SIO_ROMCTL_READ); 450 dc_delay(sc); 451 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); 452 dc_delay(sc); 453 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CS); 454 dc_delay(sc); 455 456 /* 457 * Send address of word we want to read. 458 */ 459 dc_eeprom_putbyte(sc, addr); 460 461 /* 462 * Start reading bits from EEPROM. 463 */ 464 for (i = 0x8000; i; i >>= 1) { 465 SIO_SET(DC_SIO_EE_CLK); 466 dc_delay(sc); 467 if (CSR_READ_4(sc, DC_SIO) & DC_SIO_EE_DATAOUT) 468 word |= i; 469 dc_delay(sc); 470 SIO_CLR(DC_SIO_EE_CLK); 471 dc_delay(sc); 472 } 473 474 /* Turn off EEPROM access mode. */ 475 dc_eeprom_idle(sc); 476 477 *dest = word; 478 479 return; 480 } 481 482 /* 483 * Read a sequence of words from the EEPROM. 484 */ 485 static void dc_read_eeprom(sc, dest, off, cnt, swap) 486 struct dc_softc *sc; 487 caddr_t dest; 488 int off; 489 int cnt; 490 int swap; 491 { 492 int i; 493 u_int16_t word = 0, *ptr; 494 495 for (i = 0; i < cnt; i++) { 496 if (DC_IS_PNIC(sc)) 497 dc_eeprom_getword_pnic(sc, off + i, &word); 498 else if (DC_IS_XIRCOM(sc)) 499 dc_eeprom_getword_xircom(sc, off + i, &word); 500 else 501 dc_eeprom_getword(sc, off + i, &word); 502 ptr = (u_int16_t *)(dest + (i * 2)); 503 if (swap) 504 *ptr = ntohs(word); 505 else 506 *ptr = word; 507 } 508 509 return; 510 } 511 512 /* 513 * The following two routines are taken from the Macronix 98713 514 * Application Notes pp.19-21. 515 */ 516 /* 517 * Write a bit to the MII bus. 518 */ 519 static void dc_mii_writebit(sc, bit) 520 struct dc_softc *sc; 521 int bit; 522 { 523 if (bit) 524 CSR_WRITE_4(sc, DC_SIO, 525 DC_SIO_ROMCTL_WRITE|DC_SIO_MII_DATAOUT); 526 else 527 CSR_WRITE_4(sc, DC_SIO, DC_SIO_ROMCTL_WRITE); 528 529 DC_SETBIT(sc, DC_SIO, DC_SIO_MII_CLK); 530 DC_CLRBIT(sc, DC_SIO, DC_SIO_MII_CLK); 531 532 return; 533 } 534 535 /* 536 * Read a bit from the MII bus. 537 */ 538 static int dc_mii_readbit(sc) 539 struct dc_softc *sc; 540 { 541 CSR_WRITE_4(sc, DC_SIO, DC_SIO_ROMCTL_READ|DC_SIO_MII_DIR); 542 CSR_READ_4(sc, DC_SIO); 543 DC_SETBIT(sc, DC_SIO, DC_SIO_MII_CLK); 544 DC_CLRBIT(sc, DC_SIO, DC_SIO_MII_CLK); 545 if (CSR_READ_4(sc, DC_SIO) & DC_SIO_MII_DATAIN) 546 return(1); 547 548 return(0); 549 } 550 551 /* 552 * Sync the PHYs by setting data bit and strobing the clock 32 times. 553 */ 554 static void dc_mii_sync(sc) 555 struct dc_softc *sc; 556 { 557 register int i; 558 559 CSR_WRITE_4(sc, DC_SIO, DC_SIO_ROMCTL_WRITE); 560 561 for (i = 0; i < 32; i++) 562 dc_mii_writebit(sc, 1); 563 564 return; 565 } 566 567 /* 568 * Clock a series of bits through the MII. 569 */ 570 static void dc_mii_send(sc, bits, cnt) 571 struct dc_softc *sc; 572 u_int32_t bits; 573 int cnt; 574 { 575 int i; 576 577 for (i = (0x1 << (cnt - 1)); i; i >>= 1) 578 dc_mii_writebit(sc, bits & i); 579 } 580 581 /* 582 * Read an PHY register through the MII. 583 */ 584 static int dc_mii_readreg(sc, frame) 585 struct dc_softc *sc; 586 struct dc_mii_frame *frame; 587 588 { 589 int i, ack; 590 591 DC_LOCK(sc); 592 593 /* 594 * Set up frame for RX. 595 */ 596 frame->mii_stdelim = DC_MII_STARTDELIM; 597 frame->mii_opcode = DC_MII_READOP; 598 frame->mii_turnaround = 0; 599 frame->mii_data = 0; 600 601 /* 602 * Sync the PHYs. 603 */ 604 dc_mii_sync(sc); 605 606 /* 607 * Send command/address info. 608 */ 609 dc_mii_send(sc, frame->mii_stdelim, 2); 610 dc_mii_send(sc, frame->mii_opcode, 2); 611 dc_mii_send(sc, frame->mii_phyaddr, 5); 612 dc_mii_send(sc, frame->mii_regaddr, 5); 613 614 #ifdef notdef 615 /* Idle bit */ 616 dc_mii_writebit(sc, 1); 617 dc_mii_writebit(sc, 0); 618 #endif 619 620 /* Check for ack */ 621 ack = dc_mii_readbit(sc); 622 623 /* 624 * Now try reading data bits. If the ack failed, we still 625 * need to clock through 16 cycles to keep the PHY(s) in sync. 626 */ 627 if (ack) { 628 for(i = 0; i < 16; i++) { 629 dc_mii_readbit(sc); 630 } 631 goto fail; 632 } 633 634 for (i = 0x8000; i; i >>= 1) { 635 if (!ack) { 636 if (dc_mii_readbit(sc)) 637 frame->mii_data |= i; 638 } 639 } 640 641 fail: 642 643 dc_mii_writebit(sc, 0); 644 dc_mii_writebit(sc, 0); 645 646 DC_UNLOCK(sc); 647 648 if (ack) 649 return(1); 650 return(0); 651 } 652 653 /* 654 * Write to a PHY register through the MII. 655 */ 656 static int dc_mii_writereg(sc, frame) 657 struct dc_softc *sc; 658 struct dc_mii_frame *frame; 659 660 { 661 DC_LOCK(sc); 662 /* 663 * Set up frame for TX. 664 */ 665 666 frame->mii_stdelim = DC_MII_STARTDELIM; 667 frame->mii_opcode = DC_MII_WRITEOP; 668 frame->mii_turnaround = DC_MII_TURNAROUND; 669 670 /* 671 * Sync the PHYs. 672 */ 673 dc_mii_sync(sc); 674 675 dc_mii_send(sc, frame->mii_stdelim, 2); 676 dc_mii_send(sc, frame->mii_opcode, 2); 677 dc_mii_send(sc, frame->mii_phyaddr, 5); 678 dc_mii_send(sc, frame->mii_regaddr, 5); 679 dc_mii_send(sc, frame->mii_turnaround, 2); 680 dc_mii_send(sc, frame->mii_data, 16); 681 682 /* Idle bit. */ 683 dc_mii_writebit(sc, 0); 684 dc_mii_writebit(sc, 0); 685 686 DC_UNLOCK(sc); 687 688 return(0); 689 } 690 691 static int dc_miibus_readreg(dev, phy, reg) 692 device_t dev; 693 int phy, reg; 694 { 695 struct dc_mii_frame frame; 696 struct dc_softc *sc; 697 int i, rval, phy_reg; 698 699 sc = device_get_softc(dev); 700 bzero((char *)&frame, sizeof(frame)); 701 702 /* 703 * Note: both the AL981 and AN985 have internal PHYs, 704 * however the AL981 provides direct access to the PHY 705 * registers while the AN985 uses a serial MII interface. 706 * The AN985's MII interface is also buggy in that you 707 * can read from any MII address (0 to 31), but only address 1 708 * behaves normally. To deal with both cases, we pretend 709 * that the PHY is at MII address 1. 710 */ 711 if (DC_IS_ADMTEK(sc) && phy != DC_ADMTEK_PHYADDR) 712 return(0); 713 714 if (sc->dc_pmode != DC_PMODE_MII) { 715 if (phy == (MII_NPHY - 1)) { 716 switch(reg) { 717 case MII_BMSR: 718 /* 719 * Fake something to make the probe 720 * code think there's a PHY here. 721 */ 722 return(BMSR_MEDIAMASK); 723 break; 724 case MII_PHYIDR1: 725 if (DC_IS_PNIC(sc)) 726 return(DC_VENDORID_LO); 727 return(DC_VENDORID_DEC); 728 break; 729 case MII_PHYIDR2: 730 if (DC_IS_PNIC(sc)) 731 return(DC_DEVICEID_82C168); 732 return(DC_DEVICEID_21143); 733 break; 734 default: 735 return(0); 736 break; 737 } 738 } else 739 return(0); 740 } 741 742 if (DC_IS_PNIC(sc)) { 743 CSR_WRITE_4(sc, DC_PN_MII, DC_PN_MIIOPCODE_READ | 744 (phy << 23) | (reg << 18)); 745 for (i = 0; i < DC_TIMEOUT; i++) { 746 DELAY(1); 747 rval = CSR_READ_4(sc, DC_PN_MII); 748 if (!(rval & DC_PN_MII_BUSY)) { 749 rval &= 0xFFFF; 750 return(rval == 0xFFFF ? 0 : rval); 751 } 752 } 753 return(0); 754 } 755 756 if (DC_IS_COMET(sc)) { 757 switch(reg) { 758 case MII_BMCR: 759 phy_reg = DC_AL_BMCR; 760 break; 761 case MII_BMSR: 762 phy_reg = DC_AL_BMSR; 763 break; 764 case MII_PHYIDR1: 765 phy_reg = DC_AL_VENID; 766 break; 767 case MII_PHYIDR2: 768 phy_reg = DC_AL_DEVID; 769 break; 770 case MII_ANAR: 771 phy_reg = DC_AL_ANAR; 772 break; 773 case MII_ANLPAR: 774 phy_reg = DC_AL_LPAR; 775 break; 776 case MII_ANER: 777 phy_reg = DC_AL_ANER; 778 break; 779 default: 780 printf("dc%d: phy_read: bad phy register %x\n", 781 sc->dc_unit, reg); 782 return(0); 783 break; 784 } 785 786 rval = CSR_READ_4(sc, phy_reg) & 0x0000FFFF; 787 788 if (rval == 0xFFFF) 789 return(0); 790 return(rval); 791 } 792 793 frame.mii_phyaddr = phy; 794 frame.mii_regaddr = reg; 795 phy_reg = CSR_READ_4(sc, DC_NETCFG); 796 CSR_WRITE_4(sc, DC_NETCFG, phy_reg & ~DC_NETCFG_PORTSEL); 797 dc_mii_readreg(sc, &frame); 798 CSR_WRITE_4(sc, DC_NETCFG, phy_reg); 799 800 return(frame.mii_data); 801 } 802 803 static int dc_miibus_writereg(dev, phy, reg, data) 804 device_t dev; 805 int phy, reg, data; 806 { 807 struct dc_softc *sc; 808 struct dc_mii_frame frame; 809 int i, phy_reg; 810 811 sc = device_get_softc(dev); 812 bzero((char *)&frame, sizeof(frame)); 813 814 if (DC_IS_ADMTEK(sc) && phy != DC_ADMTEK_PHYADDR) 815 return(0); 816 817 if (DC_IS_PNIC(sc)) { 818 CSR_WRITE_4(sc, DC_PN_MII, DC_PN_MIIOPCODE_WRITE | 819 (phy << 23) | (reg << 10) | data); 820 for (i = 0; i < DC_TIMEOUT; i++) { 821 if (!(CSR_READ_4(sc, DC_PN_MII) & DC_PN_MII_BUSY)) 822 break; 823 } 824 return(0); 825 } 826 827 if (DC_IS_COMET(sc)) { 828 switch(reg) { 829 case MII_BMCR: 830 phy_reg = DC_AL_BMCR; 831 break; 832 case MII_BMSR: 833 phy_reg = DC_AL_BMSR; 834 break; 835 case MII_PHYIDR1: 836 phy_reg = DC_AL_VENID; 837 break; 838 case MII_PHYIDR2: 839 phy_reg = DC_AL_DEVID; 840 break; 841 case MII_ANAR: 842 phy_reg = DC_AL_ANAR; 843 break; 844 case MII_ANLPAR: 845 phy_reg = DC_AL_LPAR; 846 break; 847 case MII_ANER: 848 phy_reg = DC_AL_ANER; 849 break; 850 default: 851 printf("dc%d: phy_write: bad phy register %x\n", 852 sc->dc_unit, reg); 853 return(0); 854 break; 855 } 856 857 CSR_WRITE_4(sc, phy_reg, data); 858 return(0); 859 } 860 861 frame.mii_phyaddr = phy; 862 frame.mii_regaddr = reg; 863 frame.mii_data = data; 864 865 phy_reg = CSR_READ_4(sc, DC_NETCFG); 866 CSR_WRITE_4(sc, DC_NETCFG, phy_reg & ~DC_NETCFG_PORTSEL); 867 dc_mii_writereg(sc, &frame); 868 CSR_WRITE_4(sc, DC_NETCFG, phy_reg); 869 870 return(0); 871 } 872 873 static void dc_miibus_statchg(dev) 874 device_t dev; 875 { 876 struct dc_softc *sc; 877 struct mii_data *mii; 878 struct ifmedia *ifm; 879 880 sc = device_get_softc(dev); 881 if (DC_IS_ADMTEK(sc)) 882 return; 883 884 mii = device_get_softc(sc->dc_miibus); 885 ifm = &mii->mii_media; 886 if (DC_IS_DAVICOM(sc) && 887 IFM_SUBTYPE(ifm->ifm_media) == IFM_homePNA) { 888 dc_setcfg(sc, ifm->ifm_media); 889 sc->dc_if_media = ifm->ifm_media; 890 } else { 891 dc_setcfg(sc, mii->mii_media_active); 892 sc->dc_if_media = mii->mii_media_active; 893 } 894 895 return; 896 } 897 898 /* 899 * Special support for DM9102A cards with HomePNA PHYs. Note: 900 * with the Davicom DM9102A/DM9801 eval board that I have, it seems 901 * to be impossible to talk to the management interface of the DM9801 902 * PHY (its MDIO pin is not connected to anything). Consequently, 903 * the driver has to just 'know' about the additional mode and deal 904 * with it itself. *sigh* 905 */ 906 static void dc_miibus_mediainit(dev) 907 device_t dev; 908 { 909 struct dc_softc *sc; 910 struct mii_data *mii; 911 struct ifmedia *ifm; 912 int rev; 913 914 rev = pci_read_config(dev, DC_PCI_CFRV, 4) & 0xFF; 915 916 sc = device_get_softc(dev); 917 mii = device_get_softc(sc->dc_miibus); 918 ifm = &mii->mii_media; 919 920 if (DC_IS_DAVICOM(sc) && rev >= DC_REVISION_DM9102A) 921 ifmedia_add(ifm, IFM_ETHER|IFM_homePNA, 0, NULL); 922 923 return; 924 } 925 926 #define DC_POLY 0xEDB88320 927 #define DC_BITS_512 9 928 #define DC_BITS_128 7 929 #define DC_BITS_64 6 930 931 static u_int32_t dc_crc_le(sc, addr) 932 struct dc_softc *sc; 933 caddr_t addr; 934 { 935 u_int32_t idx, bit, data, crc; 936 937 /* Compute CRC for the address value. */ 938 crc = 0xFFFFFFFF; /* initial value */ 939 940 for (idx = 0; idx < 6; idx++) { 941 for (data = *addr++, bit = 0; bit < 8; bit++, data >>= 1) 942 crc = (crc >> 1) ^ (((crc ^ data) & 1) ? DC_POLY : 0); 943 } 944 945 /* 946 * The hash table on the PNIC II and the MX98715AEC-C/D/E 947 * chips is only 128 bits wide. 948 */ 949 if (sc->dc_flags & DC_128BIT_HASH) 950 return (crc & ((1 << DC_BITS_128) - 1)); 951 952 /* The hash table on the MX98715BEC is only 64 bits wide. */ 953 if (sc->dc_flags & DC_64BIT_HASH) 954 return (crc & ((1 << DC_BITS_64) - 1)); 955 956 /* Xircom's hash filtering table is different (read: weird) */ 957 /* Xircom uses the LEAST significant bits */ 958 if (DC_IS_XIRCOM(sc)) { 959 if ((crc & 0x180) == 0x180) 960 return (crc & 0x0F) + (crc & 0x70)*3 + (14 << 4); 961 else 962 return (crc & 0x1F) + ((crc>>1) & 0xF0)*3 + (12 << 4); 963 } 964 965 return (crc & ((1 << DC_BITS_512) - 1)); 966 } 967 968 /* 969 * Calculate CRC of a multicast group address, return the lower 6 bits. 970 */ 971 static u_int32_t dc_crc_be(addr) 972 caddr_t addr; 973 { 974 u_int32_t crc, carry; 975 int i, j; 976 u_int8_t c; 977 978 /* Compute CRC for the address value. */ 979 crc = 0xFFFFFFFF; /* initial value */ 980 981 for (i = 0; i < 6; i++) { 982 c = *(addr + i); 983 for (j = 0; j < 8; j++) { 984 carry = ((crc & 0x80000000) ? 1 : 0) ^ (c & 0x01); 985 crc <<= 1; 986 c >>= 1; 987 if (carry) 988 crc = (crc ^ 0x04c11db6) | carry; 989 } 990 } 991 992 /* return the filter bit position */ 993 return((crc >> 26) & 0x0000003F); 994 } 995 996 /* 997 * 21143-style RX filter setup routine. Filter programming is done by 998 * downloading a special setup frame into the TX engine. 21143, Macronix, 999 * PNIC, PNIC II and Davicom chips are programmed this way. 1000 * 1001 * We always program the chip using 'hash perfect' mode, i.e. one perfect 1002 * address (our node address) and a 512-bit hash filter for multicast 1003 * frames. We also sneak the broadcast address into the hash filter since 1004 * we need that too. 1005 */ 1006 void dc_setfilt_21143(sc) 1007 struct dc_softc *sc; 1008 { 1009 struct dc_desc *sframe; 1010 u_int32_t h, *sp; 1011 struct ifmultiaddr *ifma; 1012 struct ifnet *ifp; 1013 int i; 1014 1015 ifp = &sc->arpcom.ac_if; 1016 1017 i = sc->dc_cdata.dc_tx_prod; 1018 DC_INC(sc->dc_cdata.dc_tx_prod, DC_TX_LIST_CNT); 1019 sc->dc_cdata.dc_tx_cnt++; 1020 sframe = &sc->dc_ldata->dc_tx_list[i]; 1021 sp = (u_int32_t *)&sc->dc_cdata.dc_sbuf; 1022 bzero((char *)sp, DC_SFRAME_LEN); 1023 1024 sframe->dc_data = vtophys(&sc->dc_cdata.dc_sbuf); 1025 sframe->dc_ctl = DC_SFRAME_LEN | DC_TXCTL_SETUP | DC_TXCTL_TLINK | 1026 DC_FILTER_HASHPERF | DC_TXCTL_FINT; 1027 1028 sc->dc_cdata.dc_tx_chain[i] = (struct mbuf *)&sc->dc_cdata.dc_sbuf; 1029 1030 /* If we want promiscuous mode, set the allframes bit. */ 1031 if (ifp->if_flags & IFF_PROMISC) 1032 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC); 1033 else 1034 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC); 1035 1036 if (ifp->if_flags & IFF_ALLMULTI) 1037 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI); 1038 else 1039 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI); 1040 1041 for (ifma = ifp->if_multiaddrs.lh_first; ifma != NULL; 1042 ifma = ifma->ifma_link.le_next) { 1043 if (ifma->ifma_addr->sa_family != AF_LINK) 1044 continue; 1045 h = dc_crc_le(sc, 1046 LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 1047 sp[h >> 4] |= 1 << (h & 0xF); 1048 } 1049 1050 if (ifp->if_flags & IFF_BROADCAST) { 1051 h = dc_crc_le(sc, (caddr_t)ðerbroadcastaddr); 1052 sp[h >> 4] |= 1 << (h & 0xF); 1053 } 1054 1055 /* Set our MAC address */ 1056 sp[39] = ((u_int16_t *)sc->arpcom.ac_enaddr)[0]; 1057 sp[40] = ((u_int16_t *)sc->arpcom.ac_enaddr)[1]; 1058 sp[41] = ((u_int16_t *)sc->arpcom.ac_enaddr)[2]; 1059 1060 sframe->dc_status = DC_TXSTAT_OWN; 1061 CSR_WRITE_4(sc, DC_TXSTART, 0xFFFFFFFF); 1062 1063 /* 1064 * The PNIC takes an exceedingly long time to process its 1065 * setup frame; wait 10ms after posting the setup frame 1066 * before proceeding, just so it has time to swallow its 1067 * medicine. 1068 */ 1069 DELAY(10000); 1070 1071 ifp->if_timer = 5; 1072 1073 return; 1074 } 1075 1076 void dc_setfilt_admtek(sc) 1077 struct dc_softc *sc; 1078 { 1079 struct ifnet *ifp; 1080 int h = 0; 1081 u_int32_t hashes[2] = { 0, 0 }; 1082 struct ifmultiaddr *ifma; 1083 1084 ifp = &sc->arpcom.ac_if; 1085 1086 /* Init our MAC address */ 1087 CSR_WRITE_4(sc, DC_AL_PAR0, *(u_int32_t *)(&sc->arpcom.ac_enaddr[0])); 1088 CSR_WRITE_4(sc, DC_AL_PAR1, *(u_int32_t *)(&sc->arpcom.ac_enaddr[4])); 1089 1090 /* If we want promiscuous mode, set the allframes bit. */ 1091 if (ifp->if_flags & IFF_PROMISC) 1092 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC); 1093 else 1094 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC); 1095 1096 if (ifp->if_flags & IFF_ALLMULTI) 1097 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI); 1098 else 1099 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI); 1100 1101 /* first, zot all the existing hash bits */ 1102 CSR_WRITE_4(sc, DC_AL_MAR0, 0); 1103 CSR_WRITE_4(sc, DC_AL_MAR1, 0); 1104 1105 /* 1106 * If we're already in promisc or allmulti mode, we 1107 * don't have to bother programming the multicast filter. 1108 */ 1109 if (ifp->if_flags & (IFF_PROMISC|IFF_ALLMULTI)) 1110 return; 1111 1112 /* now program new ones */ 1113 for (ifma = ifp->if_multiaddrs.lh_first; ifma != NULL; 1114 ifma = ifma->ifma_link.le_next) { 1115 if (ifma->ifma_addr->sa_family != AF_LINK) 1116 continue; 1117 h = dc_crc_be(LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 1118 if (h < 32) 1119 hashes[0] |= (1 << h); 1120 else 1121 hashes[1] |= (1 << (h - 32)); 1122 } 1123 1124 CSR_WRITE_4(sc, DC_AL_MAR0, hashes[0]); 1125 CSR_WRITE_4(sc, DC_AL_MAR1, hashes[1]); 1126 1127 return; 1128 } 1129 1130 void dc_setfilt_asix(sc) 1131 struct dc_softc *sc; 1132 { 1133 struct ifnet *ifp; 1134 int h = 0; 1135 u_int32_t hashes[2] = { 0, 0 }; 1136 struct ifmultiaddr *ifma; 1137 1138 ifp = &sc->arpcom.ac_if; 1139 1140 /* Init our MAC address */ 1141 CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_PAR0); 1142 CSR_WRITE_4(sc, DC_AX_FILTDATA, 1143 *(u_int32_t *)(&sc->arpcom.ac_enaddr[0])); 1144 CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_PAR1); 1145 CSR_WRITE_4(sc, DC_AX_FILTDATA, 1146 *(u_int32_t *)(&sc->arpcom.ac_enaddr[4])); 1147 1148 /* If we want promiscuous mode, set the allframes bit. */ 1149 if (ifp->if_flags & IFF_PROMISC) 1150 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC); 1151 else 1152 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC); 1153 1154 if (ifp->if_flags & IFF_ALLMULTI) 1155 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI); 1156 else 1157 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI); 1158 1159 /* 1160 * The ASIX chip has a special bit to enable reception 1161 * of broadcast frames. 1162 */ 1163 if (ifp->if_flags & IFF_BROADCAST) 1164 DC_SETBIT(sc, DC_NETCFG, DC_AX_NETCFG_RX_BROAD); 1165 else 1166 DC_CLRBIT(sc, DC_NETCFG, DC_AX_NETCFG_RX_BROAD); 1167 1168 /* first, zot all the existing hash bits */ 1169 CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_MAR0); 1170 CSR_WRITE_4(sc, DC_AX_FILTDATA, 0); 1171 CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_MAR1); 1172 CSR_WRITE_4(sc, DC_AX_FILTDATA, 0); 1173 1174 /* 1175 * If we're already in promisc or allmulti mode, we 1176 * don't have to bother programming the multicast filter. 1177 */ 1178 if (ifp->if_flags & (IFF_PROMISC|IFF_ALLMULTI)) 1179 return; 1180 1181 /* now program new ones */ 1182 for (ifma = ifp->if_multiaddrs.lh_first; ifma != NULL; 1183 ifma = ifma->ifma_link.le_next) { 1184 if (ifma->ifma_addr->sa_family != AF_LINK) 1185 continue; 1186 h = dc_crc_be(LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 1187 if (h < 32) 1188 hashes[0] |= (1 << h); 1189 else 1190 hashes[1] |= (1 << (h - 32)); 1191 } 1192 1193 CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_MAR0); 1194 CSR_WRITE_4(sc, DC_AX_FILTDATA, hashes[0]); 1195 CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_MAR1); 1196 CSR_WRITE_4(sc, DC_AX_FILTDATA, hashes[1]); 1197 1198 return; 1199 } 1200 1201 void dc_setfilt_xircom(sc) 1202 struct dc_softc *sc; 1203 { 1204 struct dc_desc *sframe; 1205 u_int32_t h, *sp; 1206 struct ifmultiaddr *ifma; 1207 struct ifnet *ifp; 1208 int i; 1209 1210 ifp = &sc->arpcom.ac_if; 1211 DC_CLRBIT(sc, DC_NETCFG, (DC_NETCFG_TX_ON|DC_NETCFG_RX_ON)); 1212 1213 i = sc->dc_cdata.dc_tx_prod; 1214 DC_INC(sc->dc_cdata.dc_tx_prod, DC_TX_LIST_CNT); 1215 sc->dc_cdata.dc_tx_cnt++; 1216 sframe = &sc->dc_ldata->dc_tx_list[i]; 1217 sp = (u_int32_t *)&sc->dc_cdata.dc_sbuf; 1218 bzero((char *)sp, DC_SFRAME_LEN); 1219 1220 sframe->dc_data = vtophys(&sc->dc_cdata.dc_sbuf); 1221 sframe->dc_ctl = DC_SFRAME_LEN | DC_TXCTL_SETUP | DC_TXCTL_TLINK | 1222 DC_FILTER_HASHPERF | DC_TXCTL_FINT; 1223 1224 sc->dc_cdata.dc_tx_chain[i] = (struct mbuf *)&sc->dc_cdata.dc_sbuf; 1225 1226 /* If we want promiscuous mode, set the allframes bit. */ 1227 if (ifp->if_flags & IFF_PROMISC) 1228 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC); 1229 else 1230 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC); 1231 1232 if (ifp->if_flags & IFF_ALLMULTI) 1233 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI); 1234 else 1235 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI); 1236 1237 for (ifma = ifp->if_multiaddrs.lh_first; ifma != NULL; 1238 ifma = ifma->ifma_link.le_next) { 1239 if (ifma->ifma_addr->sa_family != AF_LINK) 1240 continue; 1241 h = dc_crc_le(sc, LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 1242 sp[h >> 4] |= 1 << (h & 0xF); 1243 } 1244 1245 if (ifp->if_flags & IFF_BROADCAST) { 1246 h = dc_crc_le(sc, (caddr_t)ðerbroadcastaddr); 1247 sp[h >> 4] |= 1 << (h & 0xF); 1248 } 1249 1250 /* Set our MAC address */ 1251 sp[0] = ((u_int16_t *)sc->arpcom.ac_enaddr)[0]; 1252 sp[1] = ((u_int16_t *)sc->arpcom.ac_enaddr)[1]; 1253 sp[2] = ((u_int16_t *)sc->arpcom.ac_enaddr)[2]; 1254 1255 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_TX_ON); 1256 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_ON); 1257 ifp->if_flags |= IFF_RUNNING; 1258 sframe->dc_status = DC_TXSTAT_OWN; 1259 CSR_WRITE_4(sc, DC_TXSTART, 0xFFFFFFFF); 1260 1261 /* 1262 * wait some time... 1263 */ 1264 DELAY(1000); 1265 1266 ifp->if_timer = 5; 1267 1268 return; 1269 } 1270 1271 static void dc_setfilt(sc) 1272 struct dc_softc *sc; 1273 { 1274 if (DC_IS_INTEL(sc) || DC_IS_MACRONIX(sc) || DC_IS_PNIC(sc) || 1275 DC_IS_PNICII(sc) || DC_IS_DAVICOM(sc)) 1276 dc_setfilt_21143(sc); 1277 1278 if (DC_IS_ASIX(sc)) 1279 dc_setfilt_asix(sc); 1280 1281 if (DC_IS_ADMTEK(sc)) 1282 dc_setfilt_admtek(sc); 1283 1284 if (DC_IS_XIRCOM(sc)) 1285 dc_setfilt_xircom(sc); 1286 1287 return; 1288 } 1289 1290 /* 1291 * In order to fiddle with the 1292 * 'full-duplex' and '100Mbps' bits in the netconfig register, we 1293 * first have to put the transmit and/or receive logic in the idle state. 1294 */ 1295 static void dc_setcfg(sc, media) 1296 struct dc_softc *sc; 1297 int media; 1298 { 1299 int i, restart = 0; 1300 u_int32_t isr; 1301 1302 if (IFM_SUBTYPE(media) == IFM_NONE) 1303 return; 1304 1305 if (CSR_READ_4(sc, DC_NETCFG) & (DC_NETCFG_TX_ON|DC_NETCFG_RX_ON)) { 1306 restart = 1; 1307 DC_CLRBIT(sc, DC_NETCFG, (DC_NETCFG_TX_ON|DC_NETCFG_RX_ON)); 1308 1309 for (i = 0; i < DC_TIMEOUT; i++) { 1310 DELAY(10); 1311 isr = CSR_READ_4(sc, DC_ISR); 1312 if (isr & DC_ISR_TX_IDLE || 1313 (isr & DC_ISR_RX_STATE) == DC_RXSTATE_STOPPED) 1314 break; 1315 } 1316 1317 if (i == DC_TIMEOUT) 1318 printf("dc%d: failed to force tx and " 1319 "rx to idle state\n", sc->dc_unit); 1320 1321 } 1322 1323 if (IFM_SUBTYPE(media) == IFM_100_TX) { 1324 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_SPEEDSEL); 1325 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_HEARTBEAT); 1326 if (sc->dc_pmode == DC_PMODE_MII) { 1327 int watchdogreg; 1328 1329 if (DC_IS_INTEL(sc)) { 1330 /* there's a write enable bit here that reads as 1 */ 1331 watchdogreg = CSR_READ_4(sc, DC_WATCHDOG); 1332 watchdogreg &= ~DC_WDOG_CTLWREN; 1333 watchdogreg |= DC_WDOG_JABBERDIS; 1334 CSR_WRITE_4(sc, DC_WATCHDOG, watchdogreg); 1335 } else { 1336 DC_SETBIT(sc, DC_WATCHDOG, DC_WDOG_JABBERDIS); 1337 } 1338 DC_CLRBIT(sc, DC_NETCFG, (DC_NETCFG_PCS| 1339 DC_NETCFG_PORTSEL|DC_NETCFG_SCRAMBLER)); 1340 if (sc->dc_type == DC_TYPE_98713) 1341 DC_SETBIT(sc, DC_NETCFG, (DC_NETCFG_PCS| 1342 DC_NETCFG_SCRAMBLER)); 1343 if (!DC_IS_DAVICOM(sc)) 1344 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL); 1345 DC_CLRBIT(sc, DC_10BTCTRL, 0xFFFF); 1346 } else { 1347 if (DC_IS_PNIC(sc)) { 1348 DC_PN_GPIO_SETBIT(sc, DC_PN_GPIO_SPEEDSEL); 1349 DC_PN_GPIO_SETBIT(sc, DC_PN_GPIO_100TX_LOOP); 1350 DC_SETBIT(sc, DC_PN_NWAY, DC_PN_NWAY_SPEEDSEL); 1351 } 1352 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL); 1353 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PCS); 1354 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_SCRAMBLER); 1355 if (DC_IS_INTEL(sc)) 1356 dc_apply_fixup(sc, 1357 (media & IFM_GMASK) == IFM_FDX ? 1358 IFM_100_TX|IFM_FDX : IFM_100_TX); 1359 } 1360 } 1361 1362 if (IFM_SUBTYPE(media) == IFM_10_T) { 1363 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_SPEEDSEL); 1364 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_HEARTBEAT); 1365 if (sc->dc_pmode == DC_PMODE_MII) { 1366 int watchdogreg; 1367 1368 /* there's a write enable bit here that reads as 1 */ 1369 if (DC_IS_INTEL(sc)) { 1370 watchdogreg = CSR_READ_4(sc, DC_WATCHDOG); 1371 watchdogreg &= ~DC_WDOG_CTLWREN; 1372 watchdogreg |= DC_WDOG_JABBERDIS; 1373 CSR_WRITE_4(sc, DC_WATCHDOG, watchdogreg); 1374 } else { 1375 DC_SETBIT(sc, DC_WATCHDOG, DC_WDOG_JABBERDIS); 1376 } 1377 DC_CLRBIT(sc, DC_NETCFG, (DC_NETCFG_PCS| 1378 DC_NETCFG_PORTSEL|DC_NETCFG_SCRAMBLER)); 1379 if (sc->dc_type == DC_TYPE_98713) 1380 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PCS); 1381 if (!DC_IS_DAVICOM(sc)) 1382 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL); 1383 DC_CLRBIT(sc, DC_10BTCTRL, 0xFFFF); 1384 } else { 1385 if (DC_IS_PNIC(sc)) { 1386 DC_PN_GPIO_CLRBIT(sc, DC_PN_GPIO_SPEEDSEL); 1387 DC_PN_GPIO_SETBIT(sc, DC_PN_GPIO_100TX_LOOP); 1388 DC_CLRBIT(sc, DC_PN_NWAY, DC_PN_NWAY_SPEEDSEL); 1389 } 1390 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL); 1391 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_PCS); 1392 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_SCRAMBLER); 1393 if (DC_IS_INTEL(sc)) { 1394 DC_CLRBIT(sc, DC_SIARESET, DC_SIA_RESET); 1395 DC_CLRBIT(sc, DC_10BTCTRL, 0xFFFF); 1396 if ((media & IFM_GMASK) == IFM_FDX) 1397 DC_SETBIT(sc, DC_10BTCTRL, 0x7F3D); 1398 else 1399 DC_SETBIT(sc, DC_10BTCTRL, 0x7F3F); 1400 DC_SETBIT(sc, DC_SIARESET, DC_SIA_RESET); 1401 DC_CLRBIT(sc, DC_10BTCTRL, 1402 DC_TCTL_AUTONEGENBL); 1403 dc_apply_fixup(sc, 1404 (media & IFM_GMASK) == IFM_FDX ? 1405 IFM_10_T|IFM_FDX : IFM_10_T); 1406 DELAY(20000); 1407 } 1408 } 1409 } 1410 1411 /* 1412 * If this is a Davicom DM9102A card with a DM9801 HomePNA 1413 * PHY and we want HomePNA mode, set the portsel bit to turn 1414 * on the external MII port. 1415 */ 1416 if (DC_IS_DAVICOM(sc)) { 1417 if (IFM_SUBTYPE(media) == IFM_homePNA) { 1418 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL); 1419 sc->dc_link = 1; 1420 } else { 1421 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL); 1422 } 1423 } 1424 1425 if ((media & IFM_GMASK) == IFM_FDX) { 1426 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_FULLDUPLEX); 1427 if (sc->dc_pmode == DC_PMODE_SYM && DC_IS_PNIC(sc)) 1428 DC_SETBIT(sc, DC_PN_NWAY, DC_PN_NWAY_DUPLEX); 1429 } else { 1430 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_FULLDUPLEX); 1431 if (sc->dc_pmode == DC_PMODE_SYM && DC_IS_PNIC(sc)) 1432 DC_CLRBIT(sc, DC_PN_NWAY, DC_PN_NWAY_DUPLEX); 1433 } 1434 1435 if (restart) 1436 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_TX_ON|DC_NETCFG_RX_ON); 1437 1438 return; 1439 } 1440 1441 static void dc_reset(sc) 1442 struct dc_softc *sc; 1443 { 1444 register int i; 1445 1446 DC_SETBIT(sc, DC_BUSCTL, DC_BUSCTL_RESET); 1447 1448 for (i = 0; i < DC_TIMEOUT; i++) { 1449 DELAY(10); 1450 if (!(CSR_READ_4(sc, DC_BUSCTL) & DC_BUSCTL_RESET)) 1451 break; 1452 } 1453 1454 if (DC_IS_ASIX(sc) || DC_IS_ADMTEK(sc) || DC_IS_XIRCOM(sc) || DC_IS_INTEL(sc)) { 1455 DELAY(10000); 1456 DC_CLRBIT(sc, DC_BUSCTL, DC_BUSCTL_RESET); 1457 i = 0; 1458 } 1459 1460 if (i == DC_TIMEOUT) 1461 printf("dc%d: reset never completed!\n", sc->dc_unit); 1462 1463 /* Wait a little while for the chip to get its brains in order. */ 1464 DELAY(1000); 1465 1466 CSR_WRITE_4(sc, DC_IMR, 0x00000000); 1467 CSR_WRITE_4(sc, DC_BUSCTL, 0x00000000); 1468 CSR_WRITE_4(sc, DC_NETCFG, 0x00000000); 1469 1470 /* 1471 * Bring the SIA out of reset. In some cases, it looks 1472 * like failing to unreset the SIA soon enough gets it 1473 * into a state where it will never come out of reset 1474 * until we reset the whole chip again. 1475 */ 1476 if (DC_IS_INTEL(sc)) { 1477 DC_SETBIT(sc, DC_SIARESET, DC_SIA_RESET); 1478 CSR_WRITE_4(sc, DC_10BTCTRL, 0); 1479 CSR_WRITE_4(sc, DC_WATCHDOG, 0); 1480 } 1481 1482 return; 1483 } 1484 1485 static struct dc_type *dc_devtype(dev) 1486 device_t dev; 1487 { 1488 struct dc_type *t; 1489 u_int32_t rev; 1490 1491 t = dc_devs; 1492 1493 while(t->dc_name != NULL) { 1494 if ((pci_get_vendor(dev) == t->dc_vid) && 1495 (pci_get_device(dev) == t->dc_did)) { 1496 /* Check the PCI revision */ 1497 rev = pci_read_config(dev, DC_PCI_CFRV, 4) & 0xFF; 1498 if (t->dc_did == DC_DEVICEID_98713 && 1499 rev >= DC_REVISION_98713A) 1500 t++; 1501 if (t->dc_did == DC_DEVICEID_98713_CP && 1502 rev >= DC_REVISION_98713A) 1503 t++; 1504 if (t->dc_did == DC_DEVICEID_987x5 && 1505 rev >= DC_REVISION_98715AEC_C) 1506 t++; 1507 if (t->dc_did == DC_DEVICEID_987x5 && 1508 rev >= DC_REVISION_98725) 1509 t++; 1510 if (t->dc_did == DC_DEVICEID_AX88140A && 1511 rev >= DC_REVISION_88141) 1512 t++; 1513 if (t->dc_did == DC_DEVICEID_82C168 && 1514 rev >= DC_REVISION_82C169) 1515 t++; 1516 if (t->dc_did == DC_DEVICEID_DM9102 && 1517 rev >= DC_REVISION_DM9102A) 1518 t++; 1519 return(t); 1520 } 1521 t++; 1522 } 1523 1524 return(NULL); 1525 } 1526 1527 /* 1528 * Probe for a 21143 or clone chip. Check the PCI vendor and device 1529 * IDs against our list and return a device name if we find a match. 1530 * We do a little bit of extra work to identify the exact type of 1531 * chip. The MX98713 and MX98713A have the same PCI vendor/device ID, 1532 * but different revision IDs. The same is true for 98715/98715A 1533 * chips and the 98725, as well as the ASIX and ADMtek chips. In some 1534 * cases, the exact chip revision affects driver behavior. 1535 */ 1536 static int dc_probe(dev) 1537 device_t dev; 1538 { 1539 struct dc_type *t; 1540 1541 t = dc_devtype(dev); 1542 1543 if (t != NULL) { 1544 device_set_desc(dev, t->dc_name); 1545 return(0); 1546 } 1547 1548 return(ENXIO); 1549 } 1550 1551 static void dc_acpi(dev) 1552 device_t dev; 1553 { 1554 u_int32_t r, cptr; 1555 int unit; 1556 1557 unit = device_get_unit(dev); 1558 1559 /* Find the location of the capabilities block */ 1560 cptr = pci_read_config(dev, DC_PCI_CCAP, 4) & 0xFF; 1561 1562 r = pci_read_config(dev, cptr, 4) & 0xFF; 1563 if (r == 0x01) { 1564 1565 r = pci_read_config(dev, cptr + 4, 4); 1566 if (r & DC_PSTATE_D3) { 1567 u_int32_t iobase, membase, irq; 1568 1569 /* Save important PCI config data. */ 1570 iobase = pci_read_config(dev, DC_PCI_CFBIO, 4); 1571 membase = pci_read_config(dev, DC_PCI_CFBMA, 4); 1572 irq = pci_read_config(dev, DC_PCI_CFIT, 4); 1573 1574 /* Reset the power state. */ 1575 printf("dc%d: chip is in D%d power mode " 1576 "-- setting to D0\n", unit, r & DC_PSTATE_D3); 1577 r &= 0xFFFFFFFC; 1578 pci_write_config(dev, cptr + 4, r, 4); 1579 1580 /* Restore PCI config data. */ 1581 pci_write_config(dev, DC_PCI_CFBIO, iobase, 4); 1582 pci_write_config(dev, DC_PCI_CFBMA, membase, 4); 1583 pci_write_config(dev, DC_PCI_CFIT, irq, 4); 1584 } 1585 } 1586 return; 1587 } 1588 1589 static void dc_apply_fixup(sc, media) 1590 struct dc_softc *sc; 1591 int media; 1592 { 1593 struct dc_mediainfo *m; 1594 u_int8_t *p; 1595 int i; 1596 u_int8_t reg; 1597 1598 m = sc->dc_mi; 1599 1600 while (m != NULL) { 1601 if (m->dc_media == media) 1602 break; 1603 m = m->dc_next; 1604 } 1605 1606 if (m == NULL) 1607 return; 1608 1609 for (i = 0, p = m->dc_reset_ptr; i < m->dc_reset_len; i++, p += 2) { 1610 reg = (p[0] | (p[1] << 8)) << 16; 1611 CSR_WRITE_4(sc, DC_WATCHDOG, reg); 1612 } 1613 1614 for (i = 0, p = m->dc_gp_ptr; i < m->dc_gp_len; i++, p += 2) { 1615 reg = (p[0] | (p[1] << 8)) << 16; 1616 CSR_WRITE_4(sc, DC_WATCHDOG, reg); 1617 } 1618 1619 return; 1620 } 1621 1622 static void dc_decode_leaf_sia(sc, l) 1623 struct dc_softc *sc; 1624 struct dc_eblock_sia *l; 1625 { 1626 struct dc_mediainfo *m; 1627 1628 m = malloc(sizeof(struct dc_mediainfo), M_DEVBUF, M_NOWAIT); 1629 if (l->dc_sia_code == DC_SIA_CODE_10BT) 1630 m->dc_media = IFM_10_T; 1631 1632 if (l->dc_sia_code == DC_SIA_CODE_10BT_FDX) 1633 m->dc_media = IFM_10_T|IFM_FDX; 1634 1635 if (l->dc_sia_code == DC_SIA_CODE_10B2) 1636 m->dc_media = IFM_10_2; 1637 1638 if (l->dc_sia_code == DC_SIA_CODE_10B5) 1639 m->dc_media = IFM_10_5; 1640 1641 m->dc_gp_len = 2; 1642 m->dc_gp_ptr = (u_int8_t *)&l->dc_sia_gpio_ctl; 1643 1644 m->dc_next = sc->dc_mi; 1645 sc->dc_mi = m; 1646 1647 sc->dc_pmode = DC_PMODE_SIA; 1648 1649 return; 1650 } 1651 1652 static void dc_decode_leaf_sym(sc, l) 1653 struct dc_softc *sc; 1654 struct dc_eblock_sym *l; 1655 { 1656 struct dc_mediainfo *m; 1657 1658 m = malloc(sizeof(struct dc_mediainfo), M_DEVBUF, M_NOWAIT); 1659 if (l->dc_sym_code == DC_SYM_CODE_100BT) 1660 m->dc_media = IFM_100_TX; 1661 1662 if (l->dc_sym_code == DC_SYM_CODE_100BT_FDX) 1663 m->dc_media = IFM_100_TX|IFM_FDX; 1664 1665 m->dc_gp_len = 2; 1666 m->dc_gp_ptr = (u_int8_t *)&l->dc_sym_gpio_ctl; 1667 1668 m->dc_next = sc->dc_mi; 1669 sc->dc_mi = m; 1670 1671 sc->dc_pmode = DC_PMODE_SYM; 1672 1673 return; 1674 } 1675 1676 static void dc_decode_leaf_mii(sc, l) 1677 struct dc_softc *sc; 1678 struct dc_eblock_mii *l; 1679 { 1680 u_int8_t *p; 1681 struct dc_mediainfo *m; 1682 1683 m = malloc(sizeof(struct dc_mediainfo), M_DEVBUF, M_NOWAIT); 1684 /* We abuse IFM_AUTO to represent MII. */ 1685 m->dc_media = IFM_AUTO; 1686 m->dc_gp_len = l->dc_gpr_len; 1687 1688 p = (u_int8_t *)l; 1689 p += sizeof(struct dc_eblock_mii); 1690 m->dc_gp_ptr = p; 1691 p += 2 * l->dc_gpr_len; 1692 m->dc_reset_len = *p; 1693 p++; 1694 m->dc_reset_ptr = p; 1695 1696 m->dc_next = sc->dc_mi; 1697 sc->dc_mi = m; 1698 1699 return; 1700 } 1701 1702 static void dc_parse_21143_srom(sc) 1703 struct dc_softc *sc; 1704 { 1705 struct dc_leaf_hdr *lhdr; 1706 struct dc_eblock_hdr *hdr; 1707 int i, loff; 1708 char *ptr; 1709 1710 loff = sc->dc_srom[27]; 1711 lhdr = (struct dc_leaf_hdr *)&(sc->dc_srom[loff]); 1712 1713 ptr = (char *)lhdr; 1714 ptr += sizeof(struct dc_leaf_hdr) - 1; 1715 for (i = 0; i < lhdr->dc_mcnt; i++) { 1716 hdr = (struct dc_eblock_hdr *)ptr; 1717 switch(hdr->dc_type) { 1718 case DC_EBLOCK_MII: 1719 dc_decode_leaf_mii(sc, (struct dc_eblock_mii *)hdr); 1720 break; 1721 case DC_EBLOCK_SIA: 1722 dc_decode_leaf_sia(sc, (struct dc_eblock_sia *)hdr); 1723 break; 1724 case DC_EBLOCK_SYM: 1725 dc_decode_leaf_sym(sc, (struct dc_eblock_sym *)hdr); 1726 break; 1727 default: 1728 /* Don't care. Yet. */ 1729 break; 1730 } 1731 ptr += (hdr->dc_len & 0x7F); 1732 ptr++; 1733 } 1734 1735 return; 1736 } 1737 1738 /* 1739 * Attach the interface. Allocate softc structures, do ifmedia 1740 * setup and ethernet/BPF attach. 1741 */ 1742 static int dc_attach(dev) 1743 device_t dev; 1744 { 1745 int tmp = 0; 1746 u_char eaddr[ETHER_ADDR_LEN]; 1747 u_int32_t command; 1748 struct dc_softc *sc; 1749 struct ifnet *ifp; 1750 u_int32_t revision; 1751 int unit, error = 0, rid, mac_offset; 1752 1753 sc = device_get_softc(dev); 1754 unit = device_get_unit(dev); 1755 bzero(sc, sizeof(struct dc_softc)); 1756 1757 /* 1758 * Handle power management nonsense. 1759 */ 1760 dc_acpi(dev); 1761 1762 /* 1763 * Map control/status registers. 1764 */ 1765 command = pci_read_config(dev, PCIR_COMMAND, 4); 1766 command |= (PCIM_CMD_PORTEN|PCIM_CMD_MEMEN|PCIM_CMD_BUSMASTEREN); 1767 pci_write_config(dev, PCIR_COMMAND, command, 4); 1768 command = pci_read_config(dev, PCIR_COMMAND, 4); 1769 1770 #ifdef DC_USEIOSPACE 1771 if (!(command & PCIM_CMD_PORTEN)) { 1772 printf("dc%d: failed to enable I/O ports!\n", unit); 1773 error = ENXIO; 1774 goto fail; 1775 } 1776 #else 1777 if (!(command & PCIM_CMD_MEMEN)) { 1778 printf("dc%d: failed to enable memory mapping!\n", unit); 1779 error = ENXIO; 1780 goto fail; 1781 } 1782 #endif 1783 1784 rid = DC_RID; 1785 sc->dc_res = bus_alloc_resource(dev, DC_RES, &rid, 1786 0, ~0, 1, RF_ACTIVE); 1787 1788 if (sc->dc_res == NULL) { 1789 printf("dc%d: couldn't map ports/memory\n", unit); 1790 error = ENXIO; 1791 goto fail; 1792 } 1793 1794 sc->dc_btag = rman_get_bustag(sc->dc_res); 1795 sc->dc_bhandle = rman_get_bushandle(sc->dc_res); 1796 1797 /* Allocate interrupt */ 1798 rid = 0; 1799 sc->dc_irq = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, 0, ~0, 1, 1800 RF_SHAREABLE | RF_ACTIVE); 1801 1802 if (sc->dc_irq == NULL) { 1803 printf("dc%d: couldn't map interrupt\n", unit); 1804 bus_release_resource(dev, DC_RES, DC_RID, sc->dc_res); 1805 error = ENXIO; 1806 goto fail; 1807 } 1808 1809 error = bus_setup_intr(dev, sc->dc_irq, INTR_TYPE_NET, 1810 dc_intr, sc, &sc->dc_intrhand); 1811 1812 if (error) { 1813 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->dc_irq); 1814 bus_release_resource(dev, DC_RES, DC_RID, sc->dc_res); 1815 printf("dc%d: couldn't set up irq\n", unit); 1816 goto fail; 1817 } 1818 1819 mtx_init(&sc->dc_mtx, device_get_nameunit(dev), MTX_DEF); 1820 DC_LOCK(sc); 1821 /* Need this info to decide on a chip type. */ 1822 sc->dc_info = dc_devtype(dev); 1823 revision = pci_read_config(dev, DC_PCI_CFRV, 4) & 0x000000FF; 1824 1825 switch(sc->dc_info->dc_did) { 1826 case DC_DEVICEID_21143: 1827 sc->dc_type = DC_TYPE_21143; 1828 sc->dc_flags |= DC_TX_POLL|DC_TX_USE_TX_INTR; 1829 sc->dc_flags |= DC_REDUCED_MII_POLL; 1830 /* Save EEPROM contents so we can parse them later. */ 1831 dc_read_eeprom(sc, (caddr_t)&sc->dc_srom, 0, 512, 0); 1832 break; 1833 case DC_DEVICEID_DM9100: 1834 case DC_DEVICEID_DM9102: 1835 sc->dc_type = DC_TYPE_DM9102; 1836 sc->dc_flags |= DC_TX_COALESCE|DC_TX_INTR_ALWAYS; 1837 sc->dc_flags |= DC_REDUCED_MII_POLL|DC_TX_STORENFWD; 1838 sc->dc_pmode = DC_PMODE_MII; 1839 break; 1840 case DC_DEVICEID_AL981: 1841 sc->dc_type = DC_TYPE_AL981; 1842 sc->dc_flags |= DC_TX_USE_TX_INTR; 1843 sc->dc_flags |= DC_TX_ADMTEK_WAR; 1844 sc->dc_pmode = DC_PMODE_MII; 1845 break; 1846 case DC_DEVICEID_AN985: 1847 sc->dc_type = DC_TYPE_AN985; 1848 sc->dc_flags |= DC_TX_USE_TX_INTR; 1849 sc->dc_flags |= DC_TX_ADMTEK_WAR; 1850 sc->dc_pmode = DC_PMODE_MII; 1851 break; 1852 case DC_DEVICEID_98713: 1853 case DC_DEVICEID_98713_CP: 1854 if (revision < DC_REVISION_98713A) { 1855 sc->dc_type = DC_TYPE_98713; 1856 } 1857 if (revision >= DC_REVISION_98713A) { 1858 sc->dc_type = DC_TYPE_98713A; 1859 sc->dc_flags |= DC_21143_NWAY; 1860 } 1861 sc->dc_flags |= DC_REDUCED_MII_POLL; 1862 sc->dc_flags |= DC_TX_POLL|DC_TX_USE_TX_INTR; 1863 break; 1864 case DC_DEVICEID_987x5: 1865 case DC_DEVICEID_EN1217: 1866 /* 1867 * Macronix MX98715AEC-C/D/E parts have only a 1868 * 128-bit hash table. We need to deal with these 1869 * in the same manner as the PNIC II so that we 1870 * get the right number of bits out of the 1871 * CRC routine. 1872 */ 1873 if (revision >= DC_REVISION_98715AEC_C && 1874 revision < DC_REVISION_98725) 1875 sc->dc_flags |= DC_128BIT_HASH; 1876 sc->dc_type = DC_TYPE_987x5; 1877 sc->dc_flags |= DC_TX_POLL|DC_TX_USE_TX_INTR; 1878 sc->dc_flags |= DC_REDUCED_MII_POLL|DC_21143_NWAY; 1879 break; 1880 case DC_DEVICEID_98727: 1881 sc->dc_type = DC_TYPE_987x5; 1882 sc->dc_flags |= DC_TX_POLL|DC_TX_USE_TX_INTR; 1883 sc->dc_flags |= DC_REDUCED_MII_POLL|DC_21143_NWAY; 1884 break; 1885 case DC_DEVICEID_82C115: 1886 sc->dc_type = DC_TYPE_PNICII; 1887 sc->dc_flags |= DC_TX_POLL|DC_TX_USE_TX_INTR|DC_128BIT_HASH; 1888 sc->dc_flags |= DC_REDUCED_MII_POLL|DC_21143_NWAY; 1889 break; 1890 case DC_DEVICEID_82C168: 1891 sc->dc_type = DC_TYPE_PNIC; 1892 sc->dc_flags |= DC_TX_STORENFWD|DC_TX_INTR_ALWAYS; 1893 sc->dc_flags |= DC_PNIC_RX_BUG_WAR; 1894 sc->dc_pnic_rx_buf = malloc(DC_RXLEN * 5, M_DEVBUF, M_NOWAIT); 1895 if (revision < DC_REVISION_82C169) 1896 sc->dc_pmode = DC_PMODE_SYM; 1897 break; 1898 case DC_DEVICEID_AX88140A: 1899 sc->dc_type = DC_TYPE_ASIX; 1900 sc->dc_flags |= DC_TX_USE_TX_INTR|DC_TX_INTR_FIRSTFRAG; 1901 sc->dc_flags |= DC_REDUCED_MII_POLL; 1902 sc->dc_pmode = DC_PMODE_MII; 1903 break; 1904 case DC_DEVICEID_X3201: 1905 sc->dc_type = DC_TYPE_XIRCOM; 1906 sc->dc_flags |= DC_TX_INTR_ALWAYS | DC_TX_COALESCE; 1907 /* 1908 * We don't actually need to coalesce, but we're doing 1909 * it to obtain a double word aligned buffer. 1910 */ 1911 break; 1912 default: 1913 printf("dc%d: unknown device: %x\n", sc->dc_unit, 1914 sc->dc_info->dc_did); 1915 break; 1916 } 1917 1918 /* Save the cache line size. */ 1919 if (DC_IS_DAVICOM(sc)) 1920 sc->dc_cachesize = 0; 1921 else 1922 sc->dc_cachesize = pci_read_config(dev, 1923 DC_PCI_CFLT, 4) & 0xFF; 1924 1925 /* Reset the adapter. */ 1926 dc_reset(sc); 1927 1928 /* Take 21143 out of snooze mode */ 1929 if (DC_IS_INTEL(sc) || DC_IS_XIRCOM(sc)) { 1930 command = pci_read_config(dev, DC_PCI_CFDD, 4); 1931 command &= ~(DC_CFDD_SNOOZE_MODE|DC_CFDD_SLEEP_MODE); 1932 pci_write_config(dev, DC_PCI_CFDD, command, 4); 1933 } 1934 1935 /* 1936 * Try to learn something about the supported media. 1937 * We know that ASIX and ADMtek and Davicom devices 1938 * will *always* be using MII media, so that's a no-brainer. 1939 * The tricky ones are the Macronix/PNIC II and the 1940 * Intel 21143. 1941 */ 1942 if (DC_IS_INTEL(sc)) 1943 dc_parse_21143_srom(sc); 1944 else if (DC_IS_MACRONIX(sc) || DC_IS_PNICII(sc)) { 1945 if (sc->dc_type == DC_TYPE_98713) 1946 sc->dc_pmode = DC_PMODE_MII; 1947 else 1948 sc->dc_pmode = DC_PMODE_SYM; 1949 } else if (!sc->dc_pmode) 1950 sc->dc_pmode = DC_PMODE_MII; 1951 1952 /* 1953 * Get station address from the EEPROM. 1954 */ 1955 switch(sc->dc_type) { 1956 case DC_TYPE_98713: 1957 case DC_TYPE_98713A: 1958 case DC_TYPE_987x5: 1959 case DC_TYPE_PNICII: 1960 dc_read_eeprom(sc, (caddr_t)&mac_offset, 1961 (DC_EE_NODEADDR_OFFSET / 2), 1, 0); 1962 dc_read_eeprom(sc, (caddr_t)&eaddr, (mac_offset / 2), 3, 0); 1963 break; 1964 case DC_TYPE_PNIC: 1965 dc_read_eeprom(sc, (caddr_t)&eaddr, 0, 3, 1); 1966 break; 1967 case DC_TYPE_DM9102: 1968 case DC_TYPE_21143: 1969 case DC_TYPE_ASIX: 1970 dc_read_eeprom(sc, (caddr_t)&eaddr, DC_EE_NODEADDR, 3, 0); 1971 break; 1972 case DC_TYPE_AL981: 1973 case DC_TYPE_AN985: 1974 dc_read_eeprom(sc, (caddr_t)&eaddr, DC_AL_EE_NODEADDR, 3, 0); 1975 break; 1976 case DC_TYPE_XIRCOM: 1977 dc_read_eeprom(sc, (caddr_t)&eaddr, 3, 3, 0); 1978 break; 1979 default: 1980 dc_read_eeprom(sc, (caddr_t)&eaddr, DC_EE_NODEADDR, 3, 0); 1981 break; 1982 } 1983 1984 /* 1985 * A 21143 or clone chip was detected. Inform the world. 1986 */ 1987 printf("dc%d: Ethernet address: %6D\n", unit, eaddr, ":"); 1988 1989 sc->dc_unit = unit; 1990 bcopy(eaddr, (char *)&sc->arpcom.ac_enaddr, ETHER_ADDR_LEN); 1991 1992 sc->dc_ldata = contigmalloc(sizeof(struct dc_list_data), M_DEVBUF, 1993 M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0); 1994 1995 if (sc->dc_ldata == NULL) { 1996 printf("dc%d: no memory for list buffers!\n", unit); 1997 bus_teardown_intr(dev, sc->dc_irq, sc->dc_intrhand); 1998 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->dc_irq); 1999 bus_release_resource(dev, DC_RES, DC_RID, sc->dc_res); 2000 error = ENXIO; 2001 goto fail; 2002 } 2003 2004 bzero(sc->dc_ldata, sizeof(struct dc_list_data)); 2005 2006 ifp = &sc->arpcom.ac_if; 2007 ifp->if_softc = sc; 2008 ifp->if_unit = unit; 2009 ifp->if_name = "dc"; 2010 /* XXX: bleah, MTU gets overwritten in ether_ifattach() */ 2011 ifp->if_mtu = ETHERMTU; 2012 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 2013 ifp->if_ioctl = dc_ioctl; 2014 ifp->if_output = ether_output; 2015 ifp->if_start = dc_start; 2016 ifp->if_watchdog = dc_watchdog; 2017 ifp->if_init = dc_init; 2018 ifp->if_baudrate = 10000000; 2019 ifp->if_snd.ifq_maxlen = DC_TX_LIST_CNT - 1; 2020 2021 /* 2022 * Do MII setup. If this is a 21143, check for a PHY on the 2023 * MII bus after applying any necessary fixups to twiddle the 2024 * GPIO bits. If we don't end up finding a PHY, restore the 2025 * old selection (SIA only or SIA/SYM) and attach the dcphy 2026 * driver instead. 2027 */ 2028 if (DC_IS_INTEL(sc)) { 2029 dc_apply_fixup(sc, IFM_AUTO); 2030 tmp = sc->dc_pmode; 2031 sc->dc_pmode = DC_PMODE_MII; 2032 } 2033 2034 error = mii_phy_probe(dev, &sc->dc_miibus, 2035 dc_ifmedia_upd, dc_ifmedia_sts); 2036 2037 if (error && DC_IS_INTEL(sc)) { 2038 sc->dc_pmode = tmp; 2039 if (sc->dc_pmode != DC_PMODE_SIA) 2040 sc->dc_pmode = DC_PMODE_SYM; 2041 sc->dc_flags |= DC_21143_NWAY; 2042 mii_phy_probe(dev, &sc->dc_miibus, 2043 dc_ifmedia_upd, dc_ifmedia_sts); 2044 /* 2045 * For non-MII cards, we need to have the 21143 2046 * drive the LEDs. Except there are some systems 2047 * like the NEC VersaPro NoteBook PC which have no 2048 * LEDs, and twiddling these bits has adverse effects 2049 * on them. (I.e. you suddenly can't get a link.) 2050 */ 2051 if (pci_read_config(dev, DC_PCI_CSID, 4) != 0x80281033) 2052 sc->dc_flags |= DC_TULIP_LEDS; 2053 error = 0; 2054 } 2055 2056 if (error) { 2057 printf("dc%d: MII without any PHY!\n", sc->dc_unit); 2058 bus_teardown_intr(dev, sc->dc_irq, sc->dc_intrhand); 2059 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->dc_irq); 2060 bus_release_resource(dev, DC_RES, DC_RID, sc->dc_res); 2061 error = ENXIO; 2062 goto fail; 2063 } 2064 2065 if (DC_IS_XIRCOM(sc)) { 2066 /* 2067 * setup General Purpose Port mode and data so the tulip 2068 * can talk to the MII. 2069 */ 2070 CSR_WRITE_4(sc, DC_SIAGP, DC_SIAGP_WRITE_EN | DC_SIAGP_INT1_EN | 2071 DC_SIAGP_MD_GP2_OUTPUT | DC_SIAGP_MD_GP0_OUTPUT); 2072 DELAY(10); 2073 CSR_WRITE_4(sc, DC_SIAGP, DC_SIAGP_INT1_EN | 2074 DC_SIAGP_MD_GP2_OUTPUT | DC_SIAGP_MD_GP0_OUTPUT); 2075 DELAY(10); 2076 } 2077 2078 /* 2079 * Call MI attach routine. 2080 */ 2081 ether_ifattach(ifp, ETHER_BPF_SUPPORTED); 2082 callout_handle_init(&sc->dc_stat_ch); 2083 2084 #ifdef SRM_MEDIA 2085 sc->dc_srm_media = 0; 2086 2087 /* Remember the SRM console media setting */ 2088 if (DC_IS_INTEL(sc)) { 2089 command = pci_read_config(dev, DC_PCI_CFDD, 4); 2090 command &= ~(DC_CFDD_SNOOZE_MODE|DC_CFDD_SLEEP_MODE); 2091 switch ((command >> 8) & 0xff) { 2092 case 3: 2093 sc->dc_srm_media = IFM_10_T; 2094 break; 2095 case 4: 2096 sc->dc_srm_media = IFM_10_T | IFM_FDX; 2097 break; 2098 case 5: 2099 sc->dc_srm_media = IFM_100_TX; 2100 break; 2101 case 6: 2102 sc->dc_srm_media = IFM_100_TX | IFM_FDX; 2103 break; 2104 } 2105 if (sc->dc_srm_media) 2106 sc->dc_srm_media |= IFM_ACTIVE | IFM_ETHER; 2107 } 2108 #endif 2109 2110 DC_UNLOCK(sc); 2111 return(0); 2112 2113 fail: 2114 DC_UNLOCK(sc); 2115 mtx_destroy(&sc->dc_mtx); 2116 return(error); 2117 } 2118 2119 static int dc_detach(dev) 2120 device_t dev; 2121 { 2122 struct dc_softc *sc; 2123 struct ifnet *ifp; 2124 struct dc_mediainfo *m; 2125 2126 sc = device_get_softc(dev); 2127 2128 DC_LOCK(sc); 2129 2130 ifp = &sc->arpcom.ac_if; 2131 2132 dc_stop(sc); 2133 ether_ifdetach(ifp, ETHER_BPF_SUPPORTED); 2134 2135 bus_generic_detach(dev); 2136 device_delete_child(dev, sc->dc_miibus); 2137 2138 bus_teardown_intr(dev, sc->dc_irq, sc->dc_intrhand); 2139 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->dc_irq); 2140 bus_release_resource(dev, DC_RES, DC_RID, sc->dc_res); 2141 2142 contigfree(sc->dc_ldata, sizeof(struct dc_list_data), M_DEVBUF); 2143 if (sc->dc_pnic_rx_buf != NULL) 2144 free(sc->dc_pnic_rx_buf, M_DEVBUF); 2145 2146 while(sc->dc_mi != NULL) { 2147 m = sc->dc_mi->dc_next; 2148 free(sc->dc_mi, M_DEVBUF); 2149 sc->dc_mi = m; 2150 } 2151 2152 DC_UNLOCK(sc); 2153 mtx_destroy(&sc->dc_mtx); 2154 2155 return(0); 2156 } 2157 2158 /* 2159 * Initialize the transmit descriptors. 2160 */ 2161 static int dc_list_tx_init(sc) 2162 struct dc_softc *sc; 2163 { 2164 struct dc_chain_data *cd; 2165 struct dc_list_data *ld; 2166 int i; 2167 2168 cd = &sc->dc_cdata; 2169 ld = sc->dc_ldata; 2170 for (i = 0; i < DC_TX_LIST_CNT; i++) { 2171 if (i == (DC_TX_LIST_CNT - 1)) { 2172 ld->dc_tx_list[i].dc_next = 2173 vtophys(&ld->dc_tx_list[0]); 2174 } else { 2175 ld->dc_tx_list[i].dc_next = 2176 vtophys(&ld->dc_tx_list[i + 1]); 2177 } 2178 cd->dc_tx_chain[i] = NULL; 2179 ld->dc_tx_list[i].dc_data = 0; 2180 ld->dc_tx_list[i].dc_ctl = 0; 2181 } 2182 2183 cd->dc_tx_prod = cd->dc_tx_cons = cd->dc_tx_cnt = 0; 2184 2185 return(0); 2186 } 2187 2188 2189 /* 2190 * Initialize the RX descriptors and allocate mbufs for them. Note that 2191 * we arrange the descriptors in a closed ring, so that the last descriptor 2192 * points back to the first. 2193 */ 2194 static int dc_list_rx_init(sc) 2195 struct dc_softc *sc; 2196 { 2197 struct dc_chain_data *cd; 2198 struct dc_list_data *ld; 2199 int i; 2200 2201 cd = &sc->dc_cdata; 2202 ld = sc->dc_ldata; 2203 2204 for (i = 0; i < DC_RX_LIST_CNT; i++) { 2205 if (dc_newbuf(sc, i, NULL) == ENOBUFS) 2206 return(ENOBUFS); 2207 if (i == (DC_RX_LIST_CNT - 1)) { 2208 ld->dc_rx_list[i].dc_next = 2209 vtophys(&ld->dc_rx_list[0]); 2210 } else { 2211 ld->dc_rx_list[i].dc_next = 2212 vtophys(&ld->dc_rx_list[i + 1]); 2213 } 2214 } 2215 2216 cd->dc_rx_prod = 0; 2217 2218 return(0); 2219 } 2220 2221 /* 2222 * Initialize an RX descriptor and attach an MBUF cluster. 2223 */ 2224 static int dc_newbuf(sc, i, m) 2225 struct dc_softc *sc; 2226 int i; 2227 struct mbuf *m; 2228 { 2229 struct mbuf *m_new = NULL; 2230 struct dc_desc *c; 2231 2232 c = &sc->dc_ldata->dc_rx_list[i]; 2233 2234 if (m == NULL) { 2235 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 2236 if (m_new == NULL) { 2237 printf("dc%d: no memory for rx list " 2238 "-- packet dropped!\n", sc->dc_unit); 2239 return(ENOBUFS); 2240 } 2241 2242 MCLGET(m_new, M_DONTWAIT); 2243 if (!(m_new->m_flags & M_EXT)) { 2244 printf("dc%d: no memory for rx list " 2245 "-- packet dropped!\n", sc->dc_unit); 2246 m_freem(m_new); 2247 return(ENOBUFS); 2248 } 2249 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 2250 } else { 2251 m_new = m; 2252 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 2253 m_new->m_data = m_new->m_ext.ext_buf; 2254 } 2255 2256 m_adj(m_new, sizeof(u_int64_t)); 2257 2258 /* 2259 * If this is a PNIC chip, zero the buffer. This is part 2260 * of the workaround for the receive bug in the 82c168 and 2261 * 82c169 chips. 2262 */ 2263 if (sc->dc_flags & DC_PNIC_RX_BUG_WAR) 2264 bzero((char *)mtod(m_new, char *), m_new->m_len); 2265 2266 sc->dc_cdata.dc_rx_chain[i] = m_new; 2267 c->dc_data = vtophys(mtod(m_new, caddr_t)); 2268 c->dc_ctl = DC_RXCTL_RLINK | DC_RXLEN; 2269 c->dc_status = DC_RXSTAT_OWN; 2270 2271 return(0); 2272 } 2273 2274 /* 2275 * Grrrrr. 2276 * The PNIC chip has a terrible bug in it that manifests itself during 2277 * periods of heavy activity. The exact mode of failure if difficult to 2278 * pinpoint: sometimes it only happens in promiscuous mode, sometimes it 2279 * will happen on slow machines. The bug is that sometimes instead of 2280 * uploading one complete frame during reception, it uploads what looks 2281 * like the entire contents of its FIFO memory. The frame we want is at 2282 * the end of the whole mess, but we never know exactly how much data has 2283 * been uploaded, so salvaging the frame is hard. 2284 * 2285 * There is only one way to do it reliably, and it's disgusting. 2286 * Here's what we know: 2287 * 2288 * - We know there will always be somewhere between one and three extra 2289 * descriptors uploaded. 2290 * 2291 * - We know the desired received frame will always be at the end of the 2292 * total data upload. 2293 * 2294 * - We know the size of the desired received frame because it will be 2295 * provided in the length field of the status word in the last descriptor. 2296 * 2297 * Here's what we do: 2298 * 2299 * - When we allocate buffers for the receive ring, we bzero() them. 2300 * This means that we know that the buffer contents should be all 2301 * zeros, except for data uploaded by the chip. 2302 * 2303 * - We also force the PNIC chip to upload frames that include the 2304 * ethernet CRC at the end. 2305 * 2306 * - We gather all of the bogus frame data into a single buffer. 2307 * 2308 * - We then position a pointer at the end of this buffer and scan 2309 * backwards until we encounter the first non-zero byte of data. 2310 * This is the end of the received frame. We know we will encounter 2311 * some data at the end of the frame because the CRC will always be 2312 * there, so even if the sender transmits a packet of all zeros, 2313 * we won't be fooled. 2314 * 2315 * - We know the size of the actual received frame, so we subtract 2316 * that value from the current pointer location. This brings us 2317 * to the start of the actual received packet. 2318 * 2319 * - We copy this into an mbuf and pass it on, along with the actual 2320 * frame length. 2321 * 2322 * The performance hit is tremendous, but it beats dropping frames all 2323 * the time. 2324 */ 2325 2326 #define DC_WHOLEFRAME (DC_RXSTAT_FIRSTFRAG|DC_RXSTAT_LASTFRAG) 2327 static void dc_pnic_rx_bug_war(sc, idx) 2328 struct dc_softc *sc; 2329 int idx; 2330 { 2331 struct dc_desc *cur_rx; 2332 struct dc_desc *c = NULL; 2333 struct mbuf *m = NULL; 2334 unsigned char *ptr; 2335 int i, total_len; 2336 u_int32_t rxstat = 0; 2337 2338 i = sc->dc_pnic_rx_bug_save; 2339 cur_rx = &sc->dc_ldata->dc_rx_list[idx]; 2340 ptr = sc->dc_pnic_rx_buf; 2341 bzero(ptr, sizeof(DC_RXLEN * 5)); 2342 2343 /* Copy all the bytes from the bogus buffers. */ 2344 while (1) { 2345 c = &sc->dc_ldata->dc_rx_list[i]; 2346 rxstat = c->dc_status; 2347 m = sc->dc_cdata.dc_rx_chain[i]; 2348 bcopy(mtod(m, char *), ptr, DC_RXLEN); 2349 ptr += DC_RXLEN; 2350 /* If this is the last buffer, break out. */ 2351 if (i == idx || rxstat & DC_RXSTAT_LASTFRAG) 2352 break; 2353 dc_newbuf(sc, i, m); 2354 DC_INC(i, DC_RX_LIST_CNT); 2355 } 2356 2357 /* Find the length of the actual receive frame. */ 2358 total_len = DC_RXBYTES(rxstat); 2359 2360 /* Scan backwards until we hit a non-zero byte. */ 2361 while(*ptr == 0x00) 2362 ptr--; 2363 2364 /* Round off. */ 2365 if ((uintptr_t)(ptr) & 0x3) 2366 ptr -= 1; 2367 2368 /* Now find the start of the frame. */ 2369 ptr -= total_len; 2370 if (ptr < sc->dc_pnic_rx_buf) 2371 ptr = sc->dc_pnic_rx_buf; 2372 2373 /* 2374 * Now copy the salvaged frame to the last mbuf and fake up 2375 * the status word to make it look like a successful 2376 * frame reception. 2377 */ 2378 dc_newbuf(sc, i, m); 2379 bcopy(ptr, mtod(m, char *), total_len); 2380 cur_rx->dc_status = rxstat | DC_RXSTAT_FIRSTFRAG; 2381 2382 return; 2383 } 2384 2385 /* 2386 * This routine searches the RX ring for dirty descriptors in the 2387 * event that the rxeof routine falls out of sync with the chip's 2388 * current descriptor pointer. This may happen sometimes as a result 2389 * of a "no RX buffer available" condition that happens when the chip 2390 * consumes all of the RX buffers before the driver has a chance to 2391 * process the RX ring. This routine may need to be called more than 2392 * once to bring the driver back in sync with the chip, however we 2393 * should still be getting RX DONE interrupts to drive the search 2394 * for new packets in the RX ring, so we should catch up eventually. 2395 */ 2396 static int dc_rx_resync(sc) 2397 struct dc_softc *sc; 2398 { 2399 int i, pos; 2400 struct dc_desc *cur_rx; 2401 2402 pos = sc->dc_cdata.dc_rx_prod; 2403 2404 for (i = 0; i < DC_RX_LIST_CNT; i++) { 2405 cur_rx = &sc->dc_ldata->dc_rx_list[pos]; 2406 if (!(cur_rx->dc_status & DC_RXSTAT_OWN)) 2407 break; 2408 DC_INC(pos, DC_RX_LIST_CNT); 2409 } 2410 2411 /* If the ring really is empty, then just return. */ 2412 if (i == DC_RX_LIST_CNT) 2413 return(0); 2414 2415 /* We've fallen behing the chip: catch it. */ 2416 sc->dc_cdata.dc_rx_prod = pos; 2417 2418 return(EAGAIN); 2419 } 2420 2421 /* 2422 * A frame has been uploaded: pass the resulting mbuf chain up to 2423 * the higher level protocols. 2424 */ 2425 static void dc_rxeof(sc) 2426 struct dc_softc *sc; 2427 { 2428 struct ether_header *eh; 2429 struct mbuf *m; 2430 struct ifnet *ifp; 2431 struct dc_desc *cur_rx; 2432 int i, total_len = 0; 2433 u_int32_t rxstat; 2434 2435 ifp = &sc->arpcom.ac_if; 2436 i = sc->dc_cdata.dc_rx_prod; 2437 2438 while(!(sc->dc_ldata->dc_rx_list[i].dc_status & DC_RXSTAT_OWN)) { 2439 struct mbuf *m0 = NULL; 2440 2441 cur_rx = &sc->dc_ldata->dc_rx_list[i]; 2442 rxstat = cur_rx->dc_status; 2443 m = sc->dc_cdata.dc_rx_chain[i]; 2444 total_len = DC_RXBYTES(rxstat); 2445 2446 if (sc->dc_flags & DC_PNIC_RX_BUG_WAR) { 2447 if ((rxstat & DC_WHOLEFRAME) != DC_WHOLEFRAME) { 2448 if (rxstat & DC_RXSTAT_FIRSTFRAG) 2449 sc->dc_pnic_rx_bug_save = i; 2450 if ((rxstat & DC_RXSTAT_LASTFRAG) == 0) { 2451 DC_INC(i, DC_RX_LIST_CNT); 2452 continue; 2453 } 2454 dc_pnic_rx_bug_war(sc, i); 2455 rxstat = cur_rx->dc_status; 2456 total_len = DC_RXBYTES(rxstat); 2457 } 2458 } 2459 2460 sc->dc_cdata.dc_rx_chain[i] = NULL; 2461 2462 /* 2463 * If an error occurs, update stats, clear the 2464 * status word and leave the mbuf cluster in place: 2465 * it should simply get re-used next time this descriptor 2466 * comes up in the ring. 2467 */ 2468 if (rxstat & DC_RXSTAT_RXERR) { 2469 ifp->if_ierrors++; 2470 if (rxstat & DC_RXSTAT_COLLSEEN) 2471 ifp->if_collisions++; 2472 dc_newbuf(sc, i, m); 2473 if (rxstat & DC_RXSTAT_CRCERR) { 2474 DC_INC(i, DC_RX_LIST_CNT); 2475 continue; 2476 } else { 2477 dc_init(sc); 2478 return; 2479 } 2480 } 2481 2482 /* No errors; receive the packet. */ 2483 total_len -= ETHER_CRC_LEN; 2484 2485 m0 = m_devget(mtod(m, char *) - ETHER_ALIGN, 2486 total_len + ETHER_ALIGN, 0, ifp, NULL); 2487 dc_newbuf(sc, i, m); 2488 DC_INC(i, DC_RX_LIST_CNT); 2489 if (m0 == NULL) { 2490 ifp->if_ierrors++; 2491 continue; 2492 } 2493 m_adj(m0, ETHER_ALIGN); 2494 m = m0; 2495 2496 ifp->if_ipackets++; 2497 eh = mtod(m, struct ether_header *); 2498 2499 /* Remove header from mbuf and pass it on. */ 2500 m_adj(m, sizeof(struct ether_header)); 2501 ether_input(ifp, eh, m); 2502 } 2503 2504 sc->dc_cdata.dc_rx_prod = i; 2505 } 2506 2507 /* 2508 * A frame was downloaded to the chip. It's safe for us to clean up 2509 * the list buffers. 2510 */ 2511 2512 static void dc_txeof(sc) 2513 struct dc_softc *sc; 2514 { 2515 struct dc_desc *cur_tx = NULL; 2516 struct ifnet *ifp; 2517 int idx; 2518 2519 ifp = &sc->arpcom.ac_if; 2520 2521 /* Clear the timeout timer. */ 2522 ifp->if_timer = 0; 2523 2524 /* 2525 * Go through our tx list and free mbufs for those 2526 * frames that have been transmitted. 2527 */ 2528 idx = sc->dc_cdata.dc_tx_cons; 2529 while(idx != sc->dc_cdata.dc_tx_prod) { 2530 u_int32_t txstat; 2531 2532 cur_tx = &sc->dc_ldata->dc_tx_list[idx]; 2533 txstat = cur_tx->dc_status; 2534 2535 if (txstat & DC_TXSTAT_OWN) 2536 break; 2537 2538 if (!(cur_tx->dc_ctl & DC_TXCTL_LASTFRAG) || 2539 cur_tx->dc_ctl & DC_TXCTL_SETUP) { 2540 sc->dc_cdata.dc_tx_cnt--; 2541 if (cur_tx->dc_ctl & DC_TXCTL_SETUP) { 2542 /* 2543 * Yes, the PNIC is so brain damaged 2544 * that it will sometimes generate a TX 2545 * underrun error while DMAing the RX 2546 * filter setup frame. If we detect this, 2547 * we have to send the setup frame again, 2548 * or else the filter won't be programmed 2549 * correctly. 2550 */ 2551 if (DC_IS_PNIC(sc)) { 2552 if (txstat & DC_TXSTAT_ERRSUM) 2553 dc_setfilt(sc); 2554 } 2555 sc->dc_cdata.dc_tx_chain[idx] = NULL; 2556 } 2557 DC_INC(idx, DC_TX_LIST_CNT); 2558 continue; 2559 } 2560 2561 if (DC_IS_XIRCOM(sc)) { 2562 /* 2563 * XXX: Why does my Xircom taunt me so? 2564 * For some reason it likes setting the CARRLOST flag 2565 * even when the carrier is there. wtf?!? */ 2566 if (/*sc->dc_type == DC_TYPE_21143 &&*/ 2567 sc->dc_pmode == DC_PMODE_MII && 2568 ((txstat & 0xFFFF) & ~(DC_TXSTAT_ERRSUM| 2569 DC_TXSTAT_NOCARRIER))) 2570 txstat &= ~DC_TXSTAT_ERRSUM; 2571 } else { 2572 if (/*sc->dc_type == DC_TYPE_21143 &&*/ 2573 sc->dc_pmode == DC_PMODE_MII && 2574 ((txstat & 0xFFFF) & ~(DC_TXSTAT_ERRSUM| 2575 DC_TXSTAT_NOCARRIER|DC_TXSTAT_CARRLOST))) 2576 txstat &= ~DC_TXSTAT_ERRSUM; 2577 } 2578 2579 if (txstat & DC_TXSTAT_ERRSUM) { 2580 ifp->if_oerrors++; 2581 if (txstat & DC_TXSTAT_EXCESSCOLL) 2582 ifp->if_collisions++; 2583 if (txstat & DC_TXSTAT_LATECOLL) 2584 ifp->if_collisions++; 2585 if (!(txstat & DC_TXSTAT_UNDERRUN)) { 2586 dc_init(sc); 2587 return; 2588 } 2589 } 2590 2591 ifp->if_collisions += (txstat & DC_TXSTAT_COLLCNT) >> 3; 2592 2593 ifp->if_opackets++; 2594 if (sc->dc_cdata.dc_tx_chain[idx] != NULL) { 2595 m_freem(sc->dc_cdata.dc_tx_chain[idx]); 2596 sc->dc_cdata.dc_tx_chain[idx] = NULL; 2597 } 2598 2599 sc->dc_cdata.dc_tx_cnt--; 2600 DC_INC(idx, DC_TX_LIST_CNT); 2601 } 2602 2603 sc->dc_cdata.dc_tx_cons = idx; 2604 if (cur_tx != NULL) 2605 ifp->if_flags &= ~IFF_OACTIVE; 2606 2607 return; 2608 } 2609 2610 static void dc_tick(xsc) 2611 void *xsc; 2612 { 2613 struct dc_softc *sc; 2614 struct mii_data *mii; 2615 struct ifnet *ifp; 2616 u_int32_t r; 2617 2618 sc = xsc; 2619 DC_LOCK(sc); 2620 ifp = &sc->arpcom.ac_if; 2621 mii = device_get_softc(sc->dc_miibus); 2622 2623 if (sc->dc_flags & DC_REDUCED_MII_POLL) { 2624 if (sc->dc_flags & DC_21143_NWAY) { 2625 r = CSR_READ_4(sc, DC_10BTSTAT); 2626 if (IFM_SUBTYPE(mii->mii_media_active) == 2627 IFM_100_TX && (r & DC_TSTAT_LS100)) { 2628 sc->dc_link = 0; 2629 mii_mediachg(mii); 2630 } 2631 if (IFM_SUBTYPE(mii->mii_media_active) == 2632 IFM_10_T && (r & DC_TSTAT_LS10)) { 2633 sc->dc_link = 0; 2634 mii_mediachg(mii); 2635 } 2636 if (sc->dc_link == 0) 2637 mii_tick(mii); 2638 } else { 2639 r = CSR_READ_4(sc, DC_ISR); 2640 if ((r & DC_ISR_RX_STATE) == DC_RXSTATE_WAIT && 2641 sc->dc_cdata.dc_tx_cnt == 0) 2642 mii_tick(mii); 2643 if (!(mii->mii_media_status & IFM_ACTIVE)) 2644 sc->dc_link = 0; 2645 } 2646 } else 2647 mii_tick(mii); 2648 2649 /* 2650 * When the init routine completes, we expect to be able to send 2651 * packets right away, and in fact the network code will send a 2652 * gratuitous ARP the moment the init routine marks the interface 2653 * as running. However, even though the MAC may have been initialized, 2654 * there may be a delay of a few seconds before the PHY completes 2655 * autonegotiation and the link is brought up. Any transmissions 2656 * made during that delay will be lost. Dealing with this is tricky: 2657 * we can't just pause in the init routine while waiting for the 2658 * PHY to come ready since that would bring the whole system to 2659 * a screeching halt for several seconds. 2660 * 2661 * What we do here is prevent the TX start routine from sending 2662 * any packets until a link has been established. After the 2663 * interface has been initialized, the tick routine will poll 2664 * the state of the PHY until the IFM_ACTIVE flag is set. Until 2665 * that time, packets will stay in the send queue, and once the 2666 * link comes up, they will be flushed out to the wire. 2667 */ 2668 if (!sc->dc_link) { 2669 mii_pollstat(mii); 2670 if (mii->mii_media_status & IFM_ACTIVE && 2671 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) { 2672 sc->dc_link++; 2673 if (ifp->if_snd.ifq_head != NULL) 2674 dc_start(ifp); 2675 } 2676 } 2677 2678 if (sc->dc_flags & DC_21143_NWAY && !sc->dc_link) 2679 sc->dc_stat_ch = timeout(dc_tick, sc, hz/10); 2680 else 2681 sc->dc_stat_ch = timeout(dc_tick, sc, hz); 2682 2683 DC_UNLOCK(sc); 2684 2685 return; 2686 } 2687 2688 static void dc_intr(arg) 2689 void *arg; 2690 { 2691 struct dc_softc *sc; 2692 struct ifnet *ifp; 2693 u_int32_t status; 2694 2695 sc = arg; 2696 DC_LOCK(sc); 2697 ifp = &sc->arpcom.ac_if; 2698 2699 /* Supress unwanted interrupts */ 2700 if (!(ifp->if_flags & IFF_UP)) { 2701 if (CSR_READ_4(sc, DC_ISR) & DC_INTRS) 2702 dc_stop(sc); 2703 DC_UNLOCK(sc); 2704 return; 2705 } 2706 2707 /* Disable interrupts. */ 2708 CSR_WRITE_4(sc, DC_IMR, 0x00000000); 2709 2710 while(((status = CSR_READ_4(sc, DC_ISR)) & DC_INTRS) 2711 && status != 0xFFFFFFFF) { 2712 2713 CSR_WRITE_4(sc, DC_ISR, status); 2714 2715 if (status & DC_ISR_RX_OK) { 2716 int curpkts; 2717 curpkts = ifp->if_ipackets; 2718 dc_rxeof(sc); 2719 if (curpkts == ifp->if_ipackets) { 2720 while(dc_rx_resync(sc)) 2721 dc_rxeof(sc); 2722 } 2723 } 2724 2725 if (status & (DC_ISR_TX_OK|DC_ISR_TX_NOBUF)) 2726 dc_txeof(sc); 2727 2728 if (status & DC_ISR_TX_IDLE) { 2729 dc_txeof(sc); 2730 if (sc->dc_cdata.dc_tx_cnt) { 2731 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_TX_ON); 2732 CSR_WRITE_4(sc, DC_TXSTART, 0xFFFFFFFF); 2733 } 2734 } 2735 2736 if (status & DC_ISR_TX_UNDERRUN) { 2737 u_int32_t cfg; 2738 2739 printf("dc%d: TX underrun -- ", sc->dc_unit); 2740 if (DC_IS_DAVICOM(sc) || DC_IS_INTEL(sc)) 2741 dc_init(sc); 2742 cfg = CSR_READ_4(sc, DC_NETCFG); 2743 cfg &= ~DC_NETCFG_TX_THRESH; 2744 if (sc->dc_txthresh == DC_TXTHRESH_160BYTES) { 2745 printf("using store and forward mode\n"); 2746 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_STORENFWD); 2747 } else if (sc->dc_flags & DC_TX_STORENFWD) { 2748 printf("resetting\n"); 2749 } else { 2750 sc->dc_txthresh += 0x4000; 2751 printf("increasing TX threshold\n"); 2752 CSR_WRITE_4(sc, DC_NETCFG, cfg); 2753 DC_SETBIT(sc, DC_NETCFG, sc->dc_txthresh); 2754 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_STORENFWD); 2755 } 2756 } 2757 2758 if ((status & DC_ISR_RX_WATDOGTIMEO) 2759 || (status & DC_ISR_RX_NOBUF)) { 2760 int curpkts; 2761 curpkts = ifp->if_ipackets; 2762 dc_rxeof(sc); 2763 if (curpkts == ifp->if_ipackets) { 2764 while(dc_rx_resync(sc)) 2765 dc_rxeof(sc); 2766 } 2767 } 2768 2769 if (status & DC_ISR_BUS_ERR) { 2770 dc_reset(sc); 2771 dc_init(sc); 2772 } 2773 } 2774 2775 /* Re-enable interrupts. */ 2776 CSR_WRITE_4(sc, DC_IMR, DC_INTRS); 2777 2778 if (ifp->if_snd.ifq_head != NULL) 2779 dc_start(ifp); 2780 2781 DC_UNLOCK(sc); 2782 2783 return; 2784 } 2785 2786 /* 2787 * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data 2788 * pointers to the fragment pointers. 2789 */ 2790 static int dc_encap(sc, m_head, txidx) 2791 struct dc_softc *sc; 2792 struct mbuf *m_head; 2793 u_int32_t *txidx; 2794 { 2795 struct dc_desc *f = NULL; 2796 struct mbuf *m; 2797 int frag, cur, cnt = 0; 2798 2799 /* 2800 * Start packing the mbufs in this chain into 2801 * the fragment pointers. Stop when we run out 2802 * of fragments or hit the end of the mbuf chain. 2803 */ 2804 m = m_head; 2805 cur = frag = *txidx; 2806 2807 for (m = m_head; m != NULL; m = m->m_next) { 2808 if (m->m_len != 0) { 2809 if (sc->dc_flags & DC_TX_ADMTEK_WAR) { 2810 if (*txidx != sc->dc_cdata.dc_tx_prod && 2811 frag == (DC_TX_LIST_CNT - 1)) 2812 return(ENOBUFS); 2813 } 2814 if ((DC_TX_LIST_CNT - 2815 (sc->dc_cdata.dc_tx_cnt + cnt)) < 5) 2816 return(ENOBUFS); 2817 2818 f = &sc->dc_ldata->dc_tx_list[frag]; 2819 f->dc_ctl = DC_TXCTL_TLINK | m->m_len; 2820 if (cnt == 0) { 2821 f->dc_status = 0; 2822 f->dc_ctl |= DC_TXCTL_FIRSTFRAG; 2823 } else 2824 f->dc_status = DC_TXSTAT_OWN; 2825 f->dc_data = vtophys(mtod(m, vm_offset_t)); 2826 cur = frag; 2827 DC_INC(frag, DC_TX_LIST_CNT); 2828 cnt++; 2829 } 2830 } 2831 2832 if (m != NULL) 2833 return(ENOBUFS); 2834 2835 sc->dc_cdata.dc_tx_cnt += cnt; 2836 sc->dc_cdata.dc_tx_chain[cur] = m_head; 2837 sc->dc_ldata->dc_tx_list[cur].dc_ctl |= DC_TXCTL_LASTFRAG; 2838 if (sc->dc_flags & DC_TX_INTR_FIRSTFRAG) 2839 sc->dc_ldata->dc_tx_list[*txidx].dc_ctl |= DC_TXCTL_FINT; 2840 if (sc->dc_flags & DC_TX_INTR_ALWAYS) 2841 sc->dc_ldata->dc_tx_list[cur].dc_ctl |= DC_TXCTL_FINT; 2842 if (sc->dc_flags & DC_TX_USE_TX_INTR && sc->dc_cdata.dc_tx_cnt > 64) 2843 sc->dc_ldata->dc_tx_list[cur].dc_ctl |= DC_TXCTL_FINT; 2844 sc->dc_ldata->dc_tx_list[*txidx].dc_status = DC_TXSTAT_OWN; 2845 *txidx = frag; 2846 2847 return(0); 2848 } 2849 2850 /* 2851 * Coalesce an mbuf chain into a single mbuf cluster buffer. 2852 * Needed for some really badly behaved chips that just can't 2853 * do scatter/gather correctly. 2854 */ 2855 static int dc_coal(sc, m_head) 2856 struct dc_softc *sc; 2857 struct mbuf **m_head; 2858 { 2859 struct mbuf *m_new, *m; 2860 2861 m = *m_head; 2862 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 2863 if (m_new == NULL) { 2864 printf("dc%d: no memory for tx list", sc->dc_unit); 2865 return(ENOBUFS); 2866 } 2867 if (m->m_pkthdr.len > MHLEN) { 2868 MCLGET(m_new, M_DONTWAIT); 2869 if (!(m_new->m_flags & M_EXT)) { 2870 m_freem(m_new); 2871 printf("dc%d: no memory for tx list", sc->dc_unit); 2872 return(ENOBUFS); 2873 } 2874 } 2875 m_copydata(m, 0, m->m_pkthdr.len, mtod(m_new, caddr_t)); 2876 m_new->m_pkthdr.len = m_new->m_len = m->m_pkthdr.len; 2877 m_freem(m); 2878 *m_head = m_new; 2879 2880 return(0); 2881 } 2882 2883 /* 2884 * Main transmit routine. To avoid having to do mbuf copies, we put pointers 2885 * to the mbuf data regions directly in the transmit lists. We also save a 2886 * copy of the pointers since the transmit list fragment pointers are 2887 * physical addresses. 2888 */ 2889 2890 static void dc_start(ifp) 2891 struct ifnet *ifp; 2892 { 2893 struct dc_softc *sc; 2894 struct mbuf *m_head = NULL; 2895 int idx; 2896 2897 sc = ifp->if_softc; 2898 2899 DC_LOCK(sc); 2900 2901 if (!sc->dc_link) { 2902 DC_UNLOCK(sc); 2903 return; 2904 } 2905 2906 if (ifp->if_flags & IFF_OACTIVE) { 2907 DC_UNLOCK(sc); 2908 return; 2909 } 2910 2911 idx = sc->dc_cdata.dc_tx_prod; 2912 2913 while(sc->dc_cdata.dc_tx_chain[idx] == NULL) { 2914 IF_DEQUEUE(&ifp->if_snd, m_head); 2915 if (m_head == NULL) 2916 break; 2917 2918 if (sc->dc_flags & DC_TX_COALESCE) { 2919 if (dc_coal(sc, &m_head)) { 2920 IF_PREPEND(&ifp->if_snd, m_head); 2921 ifp->if_flags |= IFF_OACTIVE; 2922 break; 2923 } 2924 } 2925 2926 if (dc_encap(sc, m_head, &idx)) { 2927 IF_PREPEND(&ifp->if_snd, m_head); 2928 ifp->if_flags |= IFF_OACTIVE; 2929 break; 2930 } 2931 2932 /* 2933 * If there's a BPF listener, bounce a copy of this frame 2934 * to him. 2935 */ 2936 if (ifp->if_bpf) 2937 bpf_mtap(ifp, m_head); 2938 2939 if (sc->dc_flags & DC_TX_ONE) { 2940 ifp->if_flags |= IFF_OACTIVE; 2941 break; 2942 } 2943 } 2944 2945 /* Transmit */ 2946 sc->dc_cdata.dc_tx_prod = idx; 2947 if (!(sc->dc_flags & DC_TX_POLL)) 2948 CSR_WRITE_4(sc, DC_TXSTART, 0xFFFFFFFF); 2949 2950 /* 2951 * Set a timeout in case the chip goes out to lunch. 2952 */ 2953 ifp->if_timer = 5; 2954 2955 DC_UNLOCK(sc); 2956 2957 return; 2958 } 2959 2960 static void dc_init(xsc) 2961 void *xsc; 2962 { 2963 struct dc_softc *sc = xsc; 2964 struct ifnet *ifp = &sc->arpcom.ac_if; 2965 struct mii_data *mii; 2966 2967 DC_LOCK(sc); 2968 2969 mii = device_get_softc(sc->dc_miibus); 2970 2971 /* 2972 * Cancel pending I/O and free all RX/TX buffers. 2973 */ 2974 dc_stop(sc); 2975 dc_reset(sc); 2976 2977 /* 2978 * Set cache alignment and burst length. 2979 */ 2980 if (DC_IS_ASIX(sc) || DC_IS_DAVICOM(sc)) 2981 CSR_WRITE_4(sc, DC_BUSCTL, 0); 2982 else 2983 CSR_WRITE_4(sc, DC_BUSCTL, DC_BUSCTL_MRME|DC_BUSCTL_MRLE); 2984 if (DC_IS_DAVICOM(sc) || DC_IS_INTEL(sc)) { 2985 DC_SETBIT(sc, DC_BUSCTL, DC_BURSTLEN_USECA); 2986 } else { 2987 DC_SETBIT(sc, DC_BUSCTL, DC_BURSTLEN_16LONG); 2988 } 2989 if (sc->dc_flags & DC_TX_POLL) 2990 DC_SETBIT(sc, DC_BUSCTL, DC_TXPOLL_1); 2991 switch(sc->dc_cachesize) { 2992 case 32: 2993 DC_SETBIT(sc, DC_BUSCTL, DC_CACHEALIGN_32LONG); 2994 break; 2995 case 16: 2996 DC_SETBIT(sc, DC_BUSCTL, DC_CACHEALIGN_16LONG); 2997 break; 2998 case 8: 2999 DC_SETBIT(sc, DC_BUSCTL, DC_CACHEALIGN_8LONG); 3000 break; 3001 case 0: 3002 default: 3003 DC_SETBIT(sc, DC_BUSCTL, DC_CACHEALIGN_NONE); 3004 break; 3005 } 3006 3007 if (sc->dc_flags & DC_TX_STORENFWD) 3008 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_STORENFWD); 3009 else { 3010 if (sc->dc_txthresh == DC_TXTHRESH_160BYTES) { 3011 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_STORENFWD); 3012 } else { 3013 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_STORENFWD); 3014 DC_SETBIT(sc, DC_NETCFG, sc->dc_txthresh); 3015 } 3016 } 3017 3018 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_NO_RXCRC); 3019 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_TX_BACKOFF); 3020 3021 if (DC_IS_MACRONIX(sc) || DC_IS_PNICII(sc)) { 3022 /* 3023 * The app notes for the 98713 and 98715A say that 3024 * in order to have the chips operate properly, a magic 3025 * number must be written to CSR16. Macronix does not 3026 * document the meaning of these bits so there's no way 3027 * to know exactly what they do. The 98713 has a magic 3028 * number all its own; the rest all use a different one. 3029 */ 3030 DC_CLRBIT(sc, DC_MX_MAGICPACKET, 0xFFFF0000); 3031 if (sc->dc_type == DC_TYPE_98713) 3032 DC_SETBIT(sc, DC_MX_MAGICPACKET, DC_MX_MAGIC_98713); 3033 else 3034 DC_SETBIT(sc, DC_MX_MAGICPACKET, DC_MX_MAGIC_98715); 3035 } 3036 3037 if (DC_IS_XIRCOM(sc)) { 3038 /* 3039 * setup General Purpose Port mode and data so the tulip 3040 * can talk to the MII. 3041 */ 3042 CSR_WRITE_4(sc, DC_SIAGP, DC_SIAGP_WRITE_EN | DC_SIAGP_INT1_EN | 3043 DC_SIAGP_MD_GP2_OUTPUT | DC_SIAGP_MD_GP0_OUTPUT); 3044 DELAY(10); 3045 CSR_WRITE_4(sc, DC_SIAGP, DC_SIAGP_INT1_EN | 3046 DC_SIAGP_MD_GP2_OUTPUT | DC_SIAGP_MD_GP0_OUTPUT); 3047 DELAY(10); 3048 } 3049 3050 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_TX_THRESH); 3051 DC_SETBIT(sc, DC_NETCFG, DC_TXTHRESH_72BYTES); 3052 3053 /* Init circular RX list. */ 3054 if (dc_list_rx_init(sc) == ENOBUFS) { 3055 printf("dc%d: initialization failed: no " 3056 "memory for rx buffers\n", sc->dc_unit); 3057 dc_stop(sc); 3058 DC_UNLOCK(sc); 3059 return; 3060 } 3061 3062 /* 3063 * Init tx descriptors. 3064 */ 3065 dc_list_tx_init(sc); 3066 3067 /* 3068 * Load the address of the RX list. 3069 */ 3070 CSR_WRITE_4(sc, DC_RXADDR, vtophys(&sc->dc_ldata->dc_rx_list[0])); 3071 CSR_WRITE_4(sc, DC_TXADDR, vtophys(&sc->dc_ldata->dc_tx_list[0])); 3072 3073 /* 3074 * Enable interrupts. 3075 */ 3076 CSR_WRITE_4(sc, DC_IMR, DC_INTRS); 3077 CSR_WRITE_4(sc, DC_ISR, 0xFFFFFFFF); 3078 3079 /* Enable transmitter. */ 3080 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_TX_ON); 3081 3082 /* 3083 * If this is an Intel 21143 and we're not using the 3084 * MII port, program the LED control pins so we get 3085 * link and activity indications. 3086 */ 3087 if (sc->dc_flags & DC_TULIP_LEDS) { 3088 CSR_WRITE_4(sc, DC_WATCHDOG, 3089 DC_WDOG_CTLWREN|DC_WDOG_LINK|DC_WDOG_ACTIVITY); 3090 CSR_WRITE_4(sc, DC_WATCHDOG, 0); 3091 } 3092 3093 /* 3094 * Load the RX/multicast filter. We do this sort of late 3095 * because the filter programming scheme on the 21143 and 3096 * some clones requires DMAing a setup frame via the TX 3097 * engine, and we need the transmitter enabled for that. 3098 */ 3099 dc_setfilt(sc); 3100 3101 /* Enable receiver. */ 3102 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_ON); 3103 CSR_WRITE_4(sc, DC_RXSTART, 0xFFFFFFFF); 3104 3105 mii_mediachg(mii); 3106 dc_setcfg(sc, sc->dc_if_media); 3107 3108 ifp->if_flags |= IFF_RUNNING; 3109 ifp->if_flags &= ~IFF_OACTIVE; 3110 3111 /* Don't start the ticker if this is a homePNA link. */ 3112 if (IFM_SUBTYPE(mii->mii_media.ifm_media) == IFM_homePNA) 3113 sc->dc_link = 1; 3114 else { 3115 if (sc->dc_flags & DC_21143_NWAY) 3116 sc->dc_stat_ch = timeout(dc_tick, sc, hz/10); 3117 else 3118 sc->dc_stat_ch = timeout(dc_tick, sc, hz); 3119 } 3120 3121 #ifdef SRM_MEDIA 3122 if(sc->dc_srm_media) { 3123 struct ifreq ifr; 3124 3125 ifr.ifr_media = sc->dc_srm_media; 3126 ifmedia_ioctl(ifp, &ifr, &mii->mii_media, SIOCSIFMEDIA); 3127 sc->dc_srm_media = 0; 3128 } 3129 #endif 3130 DC_UNLOCK(sc); 3131 return; 3132 } 3133 3134 /* 3135 * Set media options. 3136 */ 3137 static int dc_ifmedia_upd(ifp) 3138 struct ifnet *ifp; 3139 { 3140 struct dc_softc *sc; 3141 struct mii_data *mii; 3142 struct ifmedia *ifm; 3143 3144 sc = ifp->if_softc; 3145 mii = device_get_softc(sc->dc_miibus); 3146 mii_mediachg(mii); 3147 ifm = &mii->mii_media; 3148 3149 if (DC_IS_DAVICOM(sc) && 3150 IFM_SUBTYPE(ifm->ifm_media) == IFM_homePNA) 3151 dc_setcfg(sc, ifm->ifm_media); 3152 else 3153 sc->dc_link = 0; 3154 3155 return(0); 3156 } 3157 3158 /* 3159 * Report current media status. 3160 */ 3161 static void dc_ifmedia_sts(ifp, ifmr) 3162 struct ifnet *ifp; 3163 struct ifmediareq *ifmr; 3164 { 3165 struct dc_softc *sc; 3166 struct mii_data *mii; 3167 struct ifmedia *ifm; 3168 3169 sc = ifp->if_softc; 3170 mii = device_get_softc(sc->dc_miibus); 3171 mii_pollstat(mii); 3172 ifm = &mii->mii_media; 3173 if (DC_IS_DAVICOM(sc)) { 3174 if (IFM_SUBTYPE(ifm->ifm_media) == IFM_homePNA) { 3175 ifmr->ifm_active = ifm->ifm_media; 3176 ifmr->ifm_status = 0; 3177 return; 3178 } 3179 } 3180 ifmr->ifm_active = mii->mii_media_active; 3181 ifmr->ifm_status = mii->mii_media_status; 3182 3183 return; 3184 } 3185 3186 static int dc_ioctl(ifp, command, data) 3187 struct ifnet *ifp; 3188 u_long command; 3189 caddr_t data; 3190 { 3191 struct dc_softc *sc = ifp->if_softc; 3192 struct ifreq *ifr = (struct ifreq *) data; 3193 struct mii_data *mii; 3194 int error = 0; 3195 3196 DC_LOCK(sc); 3197 3198 switch(command) { 3199 case SIOCSIFADDR: 3200 case SIOCGIFADDR: 3201 case SIOCSIFMTU: 3202 error = ether_ioctl(ifp, command, data); 3203 break; 3204 case SIOCSIFFLAGS: 3205 if (ifp->if_flags & IFF_UP) { 3206 if (ifp->if_flags & IFF_RUNNING && 3207 ifp->if_flags & IFF_PROMISC && 3208 !(sc->dc_if_flags & IFF_PROMISC)) { 3209 dc_setfilt(sc); 3210 } else if (ifp->if_flags & IFF_RUNNING && 3211 !(ifp->if_flags & IFF_PROMISC) && 3212 sc->dc_if_flags & IFF_PROMISC) { 3213 dc_setfilt(sc); 3214 } else if (!(ifp->if_flags & IFF_RUNNING)) { 3215 sc->dc_txthresh = 0; 3216 dc_init(sc); 3217 } 3218 } else { 3219 if (ifp->if_flags & IFF_RUNNING) 3220 dc_stop(sc); 3221 } 3222 sc->dc_if_flags = ifp->if_flags; 3223 error = 0; 3224 break; 3225 case SIOCADDMULTI: 3226 case SIOCDELMULTI: 3227 dc_setfilt(sc); 3228 error = 0; 3229 break; 3230 case SIOCGIFMEDIA: 3231 case SIOCSIFMEDIA: 3232 mii = device_get_softc(sc->dc_miibus); 3233 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 3234 #ifdef SRM_MEDIA 3235 if (sc->dc_srm_media) 3236 sc->dc_srm_media = 0; 3237 #endif 3238 break; 3239 default: 3240 error = EINVAL; 3241 break; 3242 } 3243 3244 DC_UNLOCK(sc); 3245 3246 return(error); 3247 } 3248 3249 static void dc_watchdog(ifp) 3250 struct ifnet *ifp; 3251 { 3252 struct dc_softc *sc; 3253 3254 sc = ifp->if_softc; 3255 3256 DC_LOCK(sc); 3257 3258 ifp->if_oerrors++; 3259 printf("dc%d: watchdog timeout\n", sc->dc_unit); 3260 3261 dc_stop(sc); 3262 dc_reset(sc); 3263 dc_init(sc); 3264 3265 if (ifp->if_snd.ifq_head != NULL) 3266 dc_start(ifp); 3267 3268 DC_UNLOCK(sc); 3269 3270 return; 3271 } 3272 3273 /* 3274 * Stop the adapter and free any mbufs allocated to the 3275 * RX and TX lists. 3276 */ 3277 static void dc_stop(sc) 3278 struct dc_softc *sc; 3279 { 3280 register int i; 3281 struct ifnet *ifp; 3282 3283 DC_LOCK(sc); 3284 3285 ifp = &sc->arpcom.ac_if; 3286 ifp->if_timer = 0; 3287 3288 untimeout(dc_tick, sc, sc->dc_stat_ch); 3289 3290 DC_CLRBIT(sc, DC_NETCFG, (DC_NETCFG_RX_ON|DC_NETCFG_TX_ON)); 3291 CSR_WRITE_4(sc, DC_IMR, 0x00000000); 3292 CSR_WRITE_4(sc, DC_TXADDR, 0x00000000); 3293 CSR_WRITE_4(sc, DC_RXADDR, 0x00000000); 3294 sc->dc_link = 0; 3295 3296 /* 3297 * Free data in the RX lists. 3298 */ 3299 for (i = 0; i < DC_RX_LIST_CNT; i++) { 3300 if (sc->dc_cdata.dc_rx_chain[i] != NULL) { 3301 m_freem(sc->dc_cdata.dc_rx_chain[i]); 3302 sc->dc_cdata.dc_rx_chain[i] = NULL; 3303 } 3304 } 3305 bzero((char *)&sc->dc_ldata->dc_rx_list, 3306 sizeof(sc->dc_ldata->dc_rx_list)); 3307 3308 /* 3309 * Free the TX list buffers. 3310 */ 3311 for (i = 0; i < DC_TX_LIST_CNT; i++) { 3312 if (sc->dc_cdata.dc_tx_chain[i] != NULL) { 3313 if (sc->dc_ldata->dc_tx_list[i].dc_ctl & 3314 DC_TXCTL_SETUP) { 3315 sc->dc_cdata.dc_tx_chain[i] = NULL; 3316 continue; 3317 } 3318 m_freem(sc->dc_cdata.dc_tx_chain[i]); 3319 sc->dc_cdata.dc_tx_chain[i] = NULL; 3320 } 3321 } 3322 3323 bzero((char *)&sc->dc_ldata->dc_tx_list, 3324 sizeof(sc->dc_ldata->dc_tx_list)); 3325 3326 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 3327 3328 DC_UNLOCK(sc); 3329 3330 return; 3331 } 3332 3333 /* 3334 * Stop all chip I/O so that the kernel's probe routines don't 3335 * get confused by errant DMAs when rebooting. 3336 */ 3337 static void dc_shutdown(dev) 3338 device_t dev; 3339 { 3340 struct dc_softc *sc; 3341 3342 sc = device_get_softc(dev); 3343 3344 dc_stop(sc); 3345 3346 return; 3347 } 3348