1 /* 2 * Copyright (c) 1997, 1998, 1999 3 * Bill Paul <wpaul@ee.columbia.edu>. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 3. All advertising materials mentioning features or use of this software 14 * must display the following acknowledgement: 15 * This product includes software developed by Bill Paul. 16 * 4. Neither the name of the author nor the names of any co-contributors 17 * may be used to endorse or promote products derived from this software 18 * without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30 * THE POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33 /* 34 * DEC "tulip" clone ethernet driver. Supports the DEC/Intel 21143 35 * series chips and several workalikes including the following: 36 * 37 * Macronix 98713/98715/98725/98727/98732 PMAC (www.macronix.com) 38 * Macronix/Lite-On 82c115 PNIC II (www.macronix.com) 39 * Lite-On 82c168/82c169 PNIC (www.litecom.com) 40 * ASIX Electronics AX88140A (www.asix.com.tw) 41 * ASIX Electronics AX88141 (www.asix.com.tw) 42 * ADMtek AL981 (www.admtek.com.tw) 43 * ADMtek AN985 (www.admtek.com.tw) 44 * Davicom DM9100, DM9102, DM9102A (www.davicom8.com) 45 * Accton EN1217 (www.accton.com) 46 * Xircom X3201 (www.xircom.com) 47 * Abocom FE2500 48 * Conexant LANfinity (www.conexant.com) 49 * 3Com OfficeConnect 10/100B 3CSOHO100B (www.3com.com) 50 * 51 * Datasheets for the 21143 are available at developer.intel.com. 52 * Datasheets for the clone parts can be found at their respective sites. 53 * (Except for the PNIC; see www.freebsd.org/~wpaul/PNIC/pnic.ps.gz.) 54 * The PNIC II is essentially a Macronix 98715A chip; the only difference 55 * worth noting is that its multicast hash table is only 128 bits wide 56 * instead of 512. 57 * 58 * Written by Bill Paul <wpaul@ee.columbia.edu> 59 * Electrical Engineering Department 60 * Columbia University, New York City 61 */ 62 63 /* 64 * The Intel 21143 is the successor to the DEC 21140. It is basically 65 * the same as the 21140 but with a few new features. The 21143 supports 66 * three kinds of media attachments: 67 * 68 * o MII port, for 10Mbps and 100Mbps support and NWAY 69 * autonegotiation provided by an external PHY. 70 * o SYM port, for symbol mode 100Mbps support. 71 * o 10baseT port. 72 * o AUI/BNC port. 73 * 74 * The 100Mbps SYM port and 10baseT port can be used together in 75 * combination with the internal NWAY support to create a 10/100 76 * autosensing configuration. 77 * 78 * Note that not all tulip workalikes are handled in this driver: we only 79 * deal with those which are relatively well behaved. The Winbond is 80 * handled separately due to its different register offsets and the 81 * special handling needed for its various bugs. The PNIC is handled 82 * here, but I'm not thrilled about it. 83 * 84 * All of the workalike chips use some form of MII transceiver support 85 * with the exception of the Macronix chips, which also have a SYM port. 86 * The ASIX AX88140A is also documented to have a SYM port, but all 87 * the cards I've seen use an MII transceiver, probably because the 88 * AX88140A doesn't support internal NWAY. 89 */ 90 91 #include <sys/cdefs.h> 92 __FBSDID("$FreeBSD$"); 93 94 #include <sys/param.h> 95 #include <sys/systm.h> 96 #include <sys/sockio.h> 97 #include <sys/mbuf.h> 98 #include <sys/malloc.h> 99 #include <sys/kernel.h> 100 #include <sys/socket.h> 101 #include <sys/sysctl.h> 102 103 #include <net/if.h> 104 #include <net/if_arp.h> 105 #include <net/ethernet.h> 106 #include <net/if_dl.h> 107 #include <net/if_media.h> 108 #include <net/if_types.h> 109 #include <net/if_vlan_var.h> 110 111 #include <net/bpf.h> 112 113 #include <vm/vm.h> /* for vtophys */ 114 #include <vm/pmap.h> /* for vtophys */ 115 #include <machine/bus_pio.h> 116 #include <machine/bus_memio.h> 117 #include <machine/bus.h> 118 #include <machine/resource.h> 119 #include <sys/bus.h> 120 #include <sys/rman.h> 121 122 #include <dev/mii/mii.h> 123 #include <dev/mii/miivar.h> 124 125 #include <pci/pcireg.h> 126 #include <pci/pcivar.h> 127 128 #define DC_USEIOSPACE 129 #ifdef __alpha__ 130 #define SRM_MEDIA 131 #endif 132 133 #include <pci/if_dcreg.h> 134 135 MODULE_DEPEND(dc, pci, 1, 1, 1); 136 MODULE_DEPEND(dc, ether, 1, 1, 1); 137 MODULE_DEPEND(dc, miibus, 1, 1, 1); 138 139 /* "controller miibus0" required. See GENERIC if you get errors here. */ 140 #include "miibus_if.h" 141 142 /* 143 * Various supported device vendors/types and their names. 144 */ 145 static struct dc_type dc_devs[] = { 146 { DC_VENDORID_DEC, DC_DEVICEID_21143, 147 "Intel 21143 10/100BaseTX" }, 148 { DC_VENDORID_DAVICOM, DC_DEVICEID_DM9009, 149 "Davicom DM9009 10/100BaseTX" }, 150 { DC_VENDORID_DAVICOM, DC_DEVICEID_DM9100, 151 "Davicom DM9100 10/100BaseTX" }, 152 { DC_VENDORID_DAVICOM, DC_DEVICEID_DM9102, 153 "Davicom DM9102 10/100BaseTX" }, 154 { DC_VENDORID_DAVICOM, DC_DEVICEID_DM9102, 155 "Davicom DM9102A 10/100BaseTX" }, 156 { DC_VENDORID_ADMTEK, DC_DEVICEID_AL981, 157 "ADMtek AL981 10/100BaseTX" }, 158 { DC_VENDORID_ADMTEK, DC_DEVICEID_AN985, 159 "ADMtek AN985 10/100BaseTX" }, 160 { DC_VENDORID_ADMTEK, DC_DEVICEID_ADM9511, 161 "ADMtek ADM9511 10/100BaseTX" }, 162 { DC_VENDORID_ADMTEK, DC_DEVICEID_ADM9513, 163 "ADMtek ADM9513 10/100BaseTX" }, 164 { DC_VENDORID_ASIX, DC_DEVICEID_AX88140A, 165 "ASIX AX88140A 10/100BaseTX" }, 166 { DC_VENDORID_ASIX, DC_DEVICEID_AX88140A, 167 "ASIX AX88141 10/100BaseTX" }, 168 { DC_VENDORID_MX, DC_DEVICEID_98713, 169 "Macronix 98713 10/100BaseTX" }, 170 { DC_VENDORID_MX, DC_DEVICEID_98713, 171 "Macronix 98713A 10/100BaseTX" }, 172 { DC_VENDORID_CP, DC_DEVICEID_98713_CP, 173 "Compex RL100-TX 10/100BaseTX" }, 174 { DC_VENDORID_CP, DC_DEVICEID_98713_CP, 175 "Compex RL100-TX 10/100BaseTX" }, 176 { DC_VENDORID_MX, DC_DEVICEID_987x5, 177 "Macronix 98715/98715A 10/100BaseTX" }, 178 { DC_VENDORID_MX, DC_DEVICEID_987x5, 179 "Macronix 98715AEC-C 10/100BaseTX" }, 180 { DC_VENDORID_MX, DC_DEVICEID_987x5, 181 "Macronix 98725 10/100BaseTX" }, 182 { DC_VENDORID_MX, DC_DEVICEID_98727, 183 "Macronix 98727/98732 10/100BaseTX" }, 184 { DC_VENDORID_LO, DC_DEVICEID_82C115, 185 "LC82C115 PNIC II 10/100BaseTX" }, 186 { DC_VENDORID_LO, DC_DEVICEID_82C168, 187 "82c168 PNIC 10/100BaseTX" }, 188 { DC_VENDORID_LO, DC_DEVICEID_82C168, 189 "82c169 PNIC 10/100BaseTX" }, 190 { DC_VENDORID_ACCTON, DC_DEVICEID_EN1217, 191 "Accton EN1217 10/100BaseTX" }, 192 { DC_VENDORID_ACCTON, DC_DEVICEID_EN2242, 193 "Accton EN2242 MiniPCI 10/100BaseTX" }, 194 { DC_VENDORID_XIRCOM, DC_DEVICEID_X3201, 195 "Xircom X3201 10/100BaseTX" }, 196 { DC_VENDORID_ABOCOM, DC_DEVICEID_FE2500, 197 "Abocom FE2500 10/100BaseTX" }, 198 { DC_VENDORID_CONEXANT, DC_DEVICEID_RS7112, 199 "Conexant LANfinity MiniPCI 10/100BaseTX" }, 200 { DC_VENDORID_HAWKING, DC_DEVICEID_HAWKING_PN672TX, 201 "Hawking CB102 CardBus 10/100" }, 202 { DC_VENDORID_PLANEX, DC_DEVICEID_FNW3602T, 203 "PlaneX FNW-3602-T CardBus 10/100" }, 204 { DC_VENDORID_3COM, DC_DEVICEID_3CSOHOB, 205 "3Com OfficeConnect 10/100B" }, 206 { 0, 0, NULL } 207 }; 208 209 static int dc_probe (device_t); 210 static int dc_attach (device_t); 211 static int dc_detach (device_t); 212 static int dc_suspend (device_t); 213 static int dc_resume (device_t); 214 static void dc_acpi (device_t); 215 static struct dc_type *dc_devtype (device_t); 216 static int dc_newbuf (struct dc_softc *, int, struct mbuf *); 217 static int dc_encap (struct dc_softc *, struct mbuf *, u_int32_t *); 218 static void dc_pnic_rx_bug_war (struct dc_softc *, int); 219 static int dc_rx_resync (struct dc_softc *); 220 static void dc_rxeof (struct dc_softc *); 221 static void dc_txeof (struct dc_softc *); 222 static void dc_tick (void *); 223 static void dc_tx_underrun (struct dc_softc *); 224 static void dc_intr (void *); 225 static void dc_start (struct ifnet *); 226 static int dc_ioctl (struct ifnet *, u_long, caddr_t); 227 static void dc_init (void *); 228 static void dc_stop (struct dc_softc *); 229 static void dc_watchdog (struct ifnet *); 230 static void dc_shutdown (device_t); 231 static int dc_ifmedia_upd (struct ifnet *); 232 static void dc_ifmedia_sts (struct ifnet *, struct ifmediareq *); 233 234 static void dc_delay (struct dc_softc *); 235 static void dc_eeprom_idle (struct dc_softc *); 236 static void dc_eeprom_putbyte (struct dc_softc *, int); 237 static void dc_eeprom_getword (struct dc_softc *, int, u_int16_t *); 238 static void dc_eeprom_getword_pnic 239 (struct dc_softc *, int, u_int16_t *); 240 static void dc_eeprom_getword_xircom 241 (struct dc_softc *, int, u_int16_t *); 242 static void dc_eeprom_width (struct dc_softc *); 243 static void dc_read_eeprom (struct dc_softc *, caddr_t, int, int, int); 244 245 static void dc_mii_writebit (struct dc_softc *, int); 246 static int dc_mii_readbit (struct dc_softc *); 247 static void dc_mii_sync (struct dc_softc *); 248 static void dc_mii_send (struct dc_softc *, u_int32_t, int); 249 static int dc_mii_readreg (struct dc_softc *, struct dc_mii_frame *); 250 static int dc_mii_writereg (struct dc_softc *, struct dc_mii_frame *); 251 static int dc_miibus_readreg (device_t, int, int); 252 static int dc_miibus_writereg (device_t, int, int, int); 253 static void dc_miibus_statchg (device_t); 254 static void dc_miibus_mediainit (device_t); 255 256 static void dc_setcfg (struct dc_softc *, int); 257 static u_int32_t dc_crc_le (struct dc_softc *, caddr_t); 258 static u_int32_t dc_crc_be (caddr_t); 259 static void dc_setfilt_21143 (struct dc_softc *); 260 static void dc_setfilt_asix (struct dc_softc *); 261 static void dc_setfilt_admtek (struct dc_softc *); 262 static void dc_setfilt_xircom (struct dc_softc *); 263 264 static void dc_setfilt (struct dc_softc *); 265 266 static void dc_reset (struct dc_softc *); 267 static int dc_list_rx_init (struct dc_softc *); 268 static int dc_list_tx_init (struct dc_softc *); 269 270 static void dc_read_srom (struct dc_softc *, int); 271 static void dc_parse_21143_srom (struct dc_softc *); 272 static void dc_decode_leaf_sia (struct dc_softc *, struct dc_eblock_sia *); 273 static void dc_decode_leaf_mii (struct dc_softc *, struct dc_eblock_mii *); 274 static void dc_decode_leaf_sym (struct dc_softc *, struct dc_eblock_sym *); 275 static void dc_apply_fixup (struct dc_softc *, int); 276 277 #ifdef DC_USEIOSPACE 278 #define DC_RES SYS_RES_IOPORT 279 #define DC_RID DC_PCI_CFBIO 280 #else 281 #define DC_RES SYS_RES_MEMORY 282 #define DC_RID DC_PCI_CFBMA 283 #endif 284 285 static device_method_t dc_methods[] = { 286 /* Device interface */ 287 DEVMETHOD(device_probe, dc_probe), 288 DEVMETHOD(device_attach, dc_attach), 289 DEVMETHOD(device_detach, dc_detach), 290 DEVMETHOD(device_suspend, dc_suspend), 291 DEVMETHOD(device_resume, dc_resume), 292 DEVMETHOD(device_shutdown, dc_shutdown), 293 294 /* bus interface */ 295 DEVMETHOD(bus_print_child, bus_generic_print_child), 296 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 297 298 /* MII interface */ 299 DEVMETHOD(miibus_readreg, dc_miibus_readreg), 300 DEVMETHOD(miibus_writereg, dc_miibus_writereg), 301 DEVMETHOD(miibus_statchg, dc_miibus_statchg), 302 DEVMETHOD(miibus_mediainit, dc_miibus_mediainit), 303 304 { 0, 0 } 305 }; 306 307 static driver_t dc_driver = { 308 "dc", 309 dc_methods, 310 sizeof(struct dc_softc) 311 }; 312 313 static devclass_t dc_devclass; 314 #ifdef __i386__ 315 static int dc_quick = 1; 316 SYSCTL_INT(_hw, OID_AUTO, dc_quick, CTLFLAG_RW, 317 &dc_quick,0,"do not mdevget in dc driver"); 318 #endif 319 320 DRIVER_MODULE(dc, cardbus, dc_driver, dc_devclass, 0, 0); 321 DRIVER_MODULE(dc, pci, dc_driver, dc_devclass, 0, 0); 322 DRIVER_MODULE(miibus, dc, miibus_driver, miibus_devclass, 0, 0); 323 324 #define DC_SETBIT(sc, reg, x) \ 325 CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) | (x)) 326 327 #define DC_CLRBIT(sc, reg, x) \ 328 CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) & ~(x)) 329 330 #define SIO_SET(x) DC_SETBIT(sc, DC_SIO, (x)) 331 #define SIO_CLR(x) DC_CLRBIT(sc, DC_SIO, (x)) 332 333 #define IS_MPSAFE 0 334 335 static void 336 dc_delay(struct dc_softc *sc) 337 { 338 int idx; 339 340 for (idx = (300 / 33) + 1; idx > 0; idx--) 341 CSR_READ_4(sc, DC_BUSCTL); 342 } 343 344 static void 345 dc_eeprom_width(struct dc_softc *sc) 346 { 347 int i; 348 349 /* Force EEPROM to idle state. */ 350 dc_eeprom_idle(sc); 351 352 /* Enter EEPROM access mode. */ 353 CSR_WRITE_4(sc, DC_SIO, DC_SIO_EESEL); 354 dc_delay(sc); 355 DC_SETBIT(sc, DC_SIO, DC_SIO_ROMCTL_READ); 356 dc_delay(sc); 357 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); 358 dc_delay(sc); 359 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CS); 360 dc_delay(sc); 361 362 for (i = 3; i--;) { 363 if (6 & (1 << i)) 364 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_DATAIN); 365 else 366 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_DATAIN); 367 dc_delay(sc); 368 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CLK); 369 dc_delay(sc); 370 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); 371 dc_delay(sc); 372 } 373 374 for (i = 1; i <= 12; i++) { 375 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CLK); 376 dc_delay(sc); 377 if (!(CSR_READ_4(sc, DC_SIO) & DC_SIO_EE_DATAOUT)) { 378 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); 379 dc_delay(sc); 380 break; 381 } 382 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); 383 dc_delay(sc); 384 } 385 386 /* Turn off EEPROM access mode. */ 387 dc_eeprom_idle(sc); 388 389 if (i < 4 || i > 12) 390 sc->dc_romwidth = 6; 391 else 392 sc->dc_romwidth = i; 393 394 /* Enter EEPROM access mode. */ 395 CSR_WRITE_4(sc, DC_SIO, DC_SIO_EESEL); 396 dc_delay(sc); 397 DC_SETBIT(sc, DC_SIO, DC_SIO_ROMCTL_READ); 398 dc_delay(sc); 399 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); 400 dc_delay(sc); 401 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CS); 402 dc_delay(sc); 403 404 /* Turn off EEPROM access mode. */ 405 dc_eeprom_idle(sc); 406 } 407 408 static void 409 dc_eeprom_idle(struct dc_softc *sc) 410 { 411 int i; 412 413 CSR_WRITE_4(sc, DC_SIO, DC_SIO_EESEL); 414 dc_delay(sc); 415 DC_SETBIT(sc, DC_SIO, DC_SIO_ROMCTL_READ); 416 dc_delay(sc); 417 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); 418 dc_delay(sc); 419 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CS); 420 dc_delay(sc); 421 422 for (i = 0; i < 25; i++) { 423 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); 424 dc_delay(sc); 425 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CLK); 426 dc_delay(sc); 427 } 428 429 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); 430 dc_delay(sc); 431 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CS); 432 dc_delay(sc); 433 CSR_WRITE_4(sc, DC_SIO, 0x00000000); 434 } 435 436 /* 437 * Send a read command and address to the EEPROM, check for ACK. 438 */ 439 static void 440 dc_eeprom_putbyte(struct dc_softc *sc, int addr) 441 { 442 int d, i; 443 444 d = DC_EECMD_READ >> 6; 445 for (i = 3; i--; ) { 446 if (d & (1 << i)) 447 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_DATAIN); 448 else 449 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_DATAIN); 450 dc_delay(sc); 451 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CLK); 452 dc_delay(sc); 453 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); 454 dc_delay(sc); 455 } 456 457 /* 458 * Feed in each bit and strobe the clock. 459 */ 460 for (i = sc->dc_romwidth; i--;) { 461 if (addr & (1 << i)) { 462 SIO_SET(DC_SIO_EE_DATAIN); 463 } else { 464 SIO_CLR(DC_SIO_EE_DATAIN); 465 } 466 dc_delay(sc); 467 SIO_SET(DC_SIO_EE_CLK); 468 dc_delay(sc); 469 SIO_CLR(DC_SIO_EE_CLK); 470 dc_delay(sc); 471 } 472 } 473 474 /* 475 * Read a word of data stored in the EEPROM at address 'addr.' 476 * The PNIC 82c168/82c169 has its own non-standard way to read 477 * the EEPROM. 478 */ 479 static void 480 dc_eeprom_getword_pnic(struct dc_softc *sc, int addr, u_int16_t *dest) 481 { 482 int i; 483 u_int32_t r; 484 485 CSR_WRITE_4(sc, DC_PN_SIOCTL, DC_PN_EEOPCODE_READ | addr); 486 487 for (i = 0; i < DC_TIMEOUT; i++) { 488 DELAY(1); 489 r = CSR_READ_4(sc, DC_SIO); 490 if (!(r & DC_PN_SIOCTL_BUSY)) { 491 *dest = (u_int16_t)(r & 0xFFFF); 492 return; 493 } 494 } 495 } 496 497 /* 498 * Read a word of data stored in the EEPROM at address 'addr.' 499 * The Xircom X3201 has its own non-standard way to read 500 * the EEPROM, too. 501 */ 502 static void 503 dc_eeprom_getword_xircom(struct dc_softc *sc, int addr, u_int16_t *dest) 504 { 505 506 SIO_SET(DC_SIO_ROMSEL | DC_SIO_ROMCTL_READ); 507 508 addr *= 2; 509 CSR_WRITE_4(sc, DC_ROM, addr | 0x160); 510 *dest = (u_int16_t)CSR_READ_4(sc, DC_SIO) & 0xff; 511 addr += 1; 512 CSR_WRITE_4(sc, DC_ROM, addr | 0x160); 513 *dest |= ((u_int16_t)CSR_READ_4(sc, DC_SIO) & 0xff) << 8; 514 515 SIO_CLR(DC_SIO_ROMSEL | DC_SIO_ROMCTL_READ); 516 } 517 518 /* 519 * Read a word of data stored in the EEPROM at address 'addr.' 520 */ 521 static void 522 dc_eeprom_getword(struct dc_softc *sc, int addr, u_int16_t *dest) 523 { 524 int i; 525 u_int16_t word = 0; 526 527 /* Force EEPROM to idle state. */ 528 dc_eeprom_idle(sc); 529 530 /* Enter EEPROM access mode. */ 531 CSR_WRITE_4(sc, DC_SIO, DC_SIO_EESEL); 532 dc_delay(sc); 533 DC_SETBIT(sc, DC_SIO, DC_SIO_ROMCTL_READ); 534 dc_delay(sc); 535 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); 536 dc_delay(sc); 537 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CS); 538 dc_delay(sc); 539 540 /* 541 * Send address of word we want to read. 542 */ 543 dc_eeprom_putbyte(sc, addr); 544 545 /* 546 * Start reading bits from EEPROM. 547 */ 548 for (i = 0x8000; i; i >>= 1) { 549 SIO_SET(DC_SIO_EE_CLK); 550 dc_delay(sc); 551 if (CSR_READ_4(sc, DC_SIO) & DC_SIO_EE_DATAOUT) 552 word |= i; 553 dc_delay(sc); 554 SIO_CLR(DC_SIO_EE_CLK); 555 dc_delay(sc); 556 } 557 558 /* Turn off EEPROM access mode. */ 559 dc_eeprom_idle(sc); 560 561 *dest = word; 562 } 563 564 /* 565 * Read a sequence of words from the EEPROM. 566 */ 567 static void 568 dc_read_eeprom(struct dc_softc *sc, caddr_t dest, int off, int cnt, int swap) 569 { 570 int i; 571 u_int16_t word = 0, *ptr; 572 573 for (i = 0; i < cnt; i++) { 574 if (DC_IS_PNIC(sc)) 575 dc_eeprom_getword_pnic(sc, off + i, &word); 576 else if (DC_IS_XIRCOM(sc)) 577 dc_eeprom_getword_xircom(sc, off + i, &word); 578 else 579 dc_eeprom_getword(sc, off + i, &word); 580 ptr = (u_int16_t *)(dest + (i * 2)); 581 if (swap) 582 *ptr = ntohs(word); 583 else 584 *ptr = word; 585 } 586 } 587 588 /* 589 * The following two routines are taken from the Macronix 98713 590 * Application Notes pp.19-21. 591 */ 592 /* 593 * Write a bit to the MII bus. 594 */ 595 static void 596 dc_mii_writebit(struct dc_softc *sc, int bit) 597 { 598 599 if (bit) 600 CSR_WRITE_4(sc, DC_SIO, 601 DC_SIO_ROMCTL_WRITE | DC_SIO_MII_DATAOUT); 602 else 603 CSR_WRITE_4(sc, DC_SIO, DC_SIO_ROMCTL_WRITE); 604 605 DC_SETBIT(sc, DC_SIO, DC_SIO_MII_CLK); 606 DC_CLRBIT(sc, DC_SIO, DC_SIO_MII_CLK); 607 } 608 609 /* 610 * Read a bit from the MII bus. 611 */ 612 static int 613 dc_mii_readbit(struct dc_softc *sc) 614 { 615 616 CSR_WRITE_4(sc, DC_SIO, DC_SIO_ROMCTL_READ | DC_SIO_MII_DIR); 617 CSR_READ_4(sc, DC_SIO); 618 DC_SETBIT(sc, DC_SIO, DC_SIO_MII_CLK); 619 DC_CLRBIT(sc, DC_SIO, DC_SIO_MII_CLK); 620 if (CSR_READ_4(sc, DC_SIO) & DC_SIO_MII_DATAIN) 621 return (1); 622 623 return (0); 624 } 625 626 /* 627 * Sync the PHYs by setting data bit and strobing the clock 32 times. 628 */ 629 static void 630 dc_mii_sync(struct dc_softc *sc) 631 { 632 int i; 633 634 CSR_WRITE_4(sc, DC_SIO, DC_SIO_ROMCTL_WRITE); 635 636 for (i = 0; i < 32; i++) 637 dc_mii_writebit(sc, 1); 638 } 639 640 /* 641 * Clock a series of bits through the MII. 642 */ 643 static void 644 dc_mii_send(struct dc_softc *sc, u_int32_t bits, int cnt) 645 { 646 int i; 647 648 for (i = (0x1 << (cnt - 1)); i; i >>= 1) 649 dc_mii_writebit(sc, bits & i); 650 } 651 652 /* 653 * Read an PHY register through the MII. 654 */ 655 static int 656 dc_mii_readreg(struct dc_softc *sc, struct dc_mii_frame *frame) 657 { 658 int i, ack; 659 660 DC_LOCK(sc); 661 662 /* 663 * Set up frame for RX. 664 */ 665 frame->mii_stdelim = DC_MII_STARTDELIM; 666 frame->mii_opcode = DC_MII_READOP; 667 frame->mii_turnaround = 0; 668 frame->mii_data = 0; 669 670 /* 671 * Sync the PHYs. 672 */ 673 dc_mii_sync(sc); 674 675 /* 676 * Send command/address info. 677 */ 678 dc_mii_send(sc, frame->mii_stdelim, 2); 679 dc_mii_send(sc, frame->mii_opcode, 2); 680 dc_mii_send(sc, frame->mii_phyaddr, 5); 681 dc_mii_send(sc, frame->mii_regaddr, 5); 682 683 #ifdef notdef 684 /* Idle bit */ 685 dc_mii_writebit(sc, 1); 686 dc_mii_writebit(sc, 0); 687 #endif 688 689 /* Check for ack. */ 690 ack = dc_mii_readbit(sc); 691 692 /* 693 * Now try reading data bits. If the ack failed, we still 694 * need to clock through 16 cycles to keep the PHY(s) in sync. 695 */ 696 if (ack) { 697 for (i = 0; i < 16; i++) 698 dc_mii_readbit(sc); 699 goto fail; 700 } 701 702 for (i = 0x8000; i; i >>= 1) { 703 if (!ack) { 704 if (dc_mii_readbit(sc)) 705 frame->mii_data |= i; 706 } 707 } 708 709 fail: 710 711 dc_mii_writebit(sc, 0); 712 dc_mii_writebit(sc, 0); 713 714 DC_UNLOCK(sc); 715 716 if (ack) 717 return (1); 718 return (0); 719 } 720 721 /* 722 * Write to a PHY register through the MII. 723 */ 724 static int 725 dc_mii_writereg(struct dc_softc *sc, struct dc_mii_frame *frame) 726 { 727 728 DC_LOCK(sc); 729 /* 730 * Set up frame for TX. 731 */ 732 733 frame->mii_stdelim = DC_MII_STARTDELIM; 734 frame->mii_opcode = DC_MII_WRITEOP; 735 frame->mii_turnaround = DC_MII_TURNAROUND; 736 737 /* 738 * Sync the PHYs. 739 */ 740 dc_mii_sync(sc); 741 742 dc_mii_send(sc, frame->mii_stdelim, 2); 743 dc_mii_send(sc, frame->mii_opcode, 2); 744 dc_mii_send(sc, frame->mii_phyaddr, 5); 745 dc_mii_send(sc, frame->mii_regaddr, 5); 746 dc_mii_send(sc, frame->mii_turnaround, 2); 747 dc_mii_send(sc, frame->mii_data, 16); 748 749 /* Idle bit. */ 750 dc_mii_writebit(sc, 0); 751 dc_mii_writebit(sc, 0); 752 753 DC_UNLOCK(sc); 754 755 return (0); 756 } 757 758 static int 759 dc_miibus_readreg(device_t dev, int phy, int reg) 760 { 761 struct dc_mii_frame frame; 762 struct dc_softc *sc; 763 int i, rval, phy_reg = 0; 764 765 sc = device_get_softc(dev); 766 bzero(&frame, sizeof(frame)); 767 768 /* 769 * Note: both the AL981 and AN985 have internal PHYs, 770 * however the AL981 provides direct access to the PHY 771 * registers while the AN985 uses a serial MII interface. 772 * The AN985's MII interface is also buggy in that you 773 * can read from any MII address (0 to 31), but only address 1 774 * behaves normally. To deal with both cases, we pretend 775 * that the PHY is at MII address 1. 776 */ 777 if (DC_IS_ADMTEK(sc) && phy != DC_ADMTEK_PHYADDR) 778 return (0); 779 780 /* 781 * Note: the ukphy probes of the RS7112 report a PHY at 782 * MII address 0 (possibly HomePNA?) and 1 (ethernet) 783 * so we only respond to correct one. 784 */ 785 if (DC_IS_CONEXANT(sc) && phy != DC_CONEXANT_PHYADDR) 786 return (0); 787 788 if (sc->dc_pmode != DC_PMODE_MII) { 789 if (phy == (MII_NPHY - 1)) { 790 switch (reg) { 791 case MII_BMSR: 792 /* 793 * Fake something to make the probe 794 * code think there's a PHY here. 795 */ 796 return (BMSR_MEDIAMASK); 797 break; 798 case MII_PHYIDR1: 799 if (DC_IS_PNIC(sc)) 800 return (DC_VENDORID_LO); 801 return (DC_VENDORID_DEC); 802 break; 803 case MII_PHYIDR2: 804 if (DC_IS_PNIC(sc)) 805 return (DC_DEVICEID_82C168); 806 return (DC_DEVICEID_21143); 807 break; 808 default: 809 return (0); 810 break; 811 } 812 } else 813 return (0); 814 } 815 816 if (DC_IS_PNIC(sc)) { 817 CSR_WRITE_4(sc, DC_PN_MII, DC_PN_MIIOPCODE_READ | 818 (phy << 23) | (reg << 18)); 819 for (i = 0; i < DC_TIMEOUT; i++) { 820 DELAY(1); 821 rval = CSR_READ_4(sc, DC_PN_MII); 822 if (!(rval & DC_PN_MII_BUSY)) { 823 rval &= 0xFFFF; 824 return (rval == 0xFFFF ? 0 : rval); 825 } 826 } 827 return (0); 828 } 829 830 if (DC_IS_COMET(sc)) { 831 switch (reg) { 832 case MII_BMCR: 833 phy_reg = DC_AL_BMCR; 834 break; 835 case MII_BMSR: 836 phy_reg = DC_AL_BMSR; 837 break; 838 case MII_PHYIDR1: 839 phy_reg = DC_AL_VENID; 840 break; 841 case MII_PHYIDR2: 842 phy_reg = DC_AL_DEVID; 843 break; 844 case MII_ANAR: 845 phy_reg = DC_AL_ANAR; 846 break; 847 case MII_ANLPAR: 848 phy_reg = DC_AL_LPAR; 849 break; 850 case MII_ANER: 851 phy_reg = DC_AL_ANER; 852 break; 853 default: 854 printf("dc%d: phy_read: bad phy register %x\n", 855 sc->dc_unit, reg); 856 return (0); 857 break; 858 } 859 860 rval = CSR_READ_4(sc, phy_reg) & 0x0000FFFF; 861 862 if (rval == 0xFFFF) 863 return (0); 864 return (rval); 865 } 866 867 frame.mii_phyaddr = phy; 868 frame.mii_regaddr = reg; 869 if (sc->dc_type == DC_TYPE_98713) { 870 phy_reg = CSR_READ_4(sc, DC_NETCFG); 871 CSR_WRITE_4(sc, DC_NETCFG, phy_reg & ~DC_NETCFG_PORTSEL); 872 } 873 dc_mii_readreg(sc, &frame); 874 if (sc->dc_type == DC_TYPE_98713) 875 CSR_WRITE_4(sc, DC_NETCFG, phy_reg); 876 877 return (frame.mii_data); 878 } 879 880 static int 881 dc_miibus_writereg(device_t dev, int phy, int reg, int data) 882 { 883 struct dc_softc *sc; 884 struct dc_mii_frame frame; 885 int i, phy_reg = 0; 886 887 sc = device_get_softc(dev); 888 bzero(&frame, sizeof(frame)); 889 890 if (DC_IS_ADMTEK(sc) && phy != DC_ADMTEK_PHYADDR) 891 return (0); 892 893 if (DC_IS_CONEXANT(sc) && phy != DC_CONEXANT_PHYADDR) 894 return (0); 895 896 if (DC_IS_PNIC(sc)) { 897 CSR_WRITE_4(sc, DC_PN_MII, DC_PN_MIIOPCODE_WRITE | 898 (phy << 23) | (reg << 10) | data); 899 for (i = 0; i < DC_TIMEOUT; i++) { 900 if (!(CSR_READ_4(sc, DC_PN_MII) & DC_PN_MII_BUSY)) 901 break; 902 } 903 return (0); 904 } 905 906 if (DC_IS_COMET(sc)) { 907 switch (reg) { 908 case MII_BMCR: 909 phy_reg = DC_AL_BMCR; 910 break; 911 case MII_BMSR: 912 phy_reg = DC_AL_BMSR; 913 break; 914 case MII_PHYIDR1: 915 phy_reg = DC_AL_VENID; 916 break; 917 case MII_PHYIDR2: 918 phy_reg = DC_AL_DEVID; 919 break; 920 case MII_ANAR: 921 phy_reg = DC_AL_ANAR; 922 break; 923 case MII_ANLPAR: 924 phy_reg = DC_AL_LPAR; 925 break; 926 case MII_ANER: 927 phy_reg = DC_AL_ANER; 928 break; 929 default: 930 printf("dc%d: phy_write: bad phy register %x\n", 931 sc->dc_unit, reg); 932 return (0); 933 break; 934 } 935 936 CSR_WRITE_4(sc, phy_reg, data); 937 return (0); 938 } 939 940 frame.mii_phyaddr = phy; 941 frame.mii_regaddr = reg; 942 frame.mii_data = data; 943 944 if (sc->dc_type == DC_TYPE_98713) { 945 phy_reg = CSR_READ_4(sc, DC_NETCFG); 946 CSR_WRITE_4(sc, DC_NETCFG, phy_reg & ~DC_NETCFG_PORTSEL); 947 } 948 dc_mii_writereg(sc, &frame); 949 if (sc->dc_type == DC_TYPE_98713) 950 CSR_WRITE_4(sc, DC_NETCFG, phy_reg); 951 952 return (0); 953 } 954 955 static void 956 dc_miibus_statchg(device_t dev) 957 { 958 struct dc_softc *sc; 959 struct mii_data *mii; 960 struct ifmedia *ifm; 961 962 sc = device_get_softc(dev); 963 if (DC_IS_ADMTEK(sc)) 964 return; 965 966 mii = device_get_softc(sc->dc_miibus); 967 ifm = &mii->mii_media; 968 if (DC_IS_DAVICOM(sc) && 969 IFM_SUBTYPE(ifm->ifm_media) == IFM_HPNA_1) { 970 dc_setcfg(sc, ifm->ifm_media); 971 sc->dc_if_media = ifm->ifm_media; 972 } else { 973 dc_setcfg(sc, mii->mii_media_active); 974 sc->dc_if_media = mii->mii_media_active; 975 } 976 } 977 978 /* 979 * Special support for DM9102A cards with HomePNA PHYs. Note: 980 * with the Davicom DM9102A/DM9801 eval board that I have, it seems 981 * to be impossible to talk to the management interface of the DM9801 982 * PHY (its MDIO pin is not connected to anything). Consequently, 983 * the driver has to just 'know' about the additional mode and deal 984 * with it itself. *sigh* 985 */ 986 static void 987 dc_miibus_mediainit(device_t dev) 988 { 989 struct dc_softc *sc; 990 struct mii_data *mii; 991 struct ifmedia *ifm; 992 int rev; 993 994 rev = pci_read_config(dev, DC_PCI_CFRV, 4) & 0xFF; 995 996 sc = device_get_softc(dev); 997 mii = device_get_softc(sc->dc_miibus); 998 ifm = &mii->mii_media; 999 1000 if (DC_IS_DAVICOM(sc) && rev >= DC_REVISION_DM9102A) 1001 ifmedia_add(ifm, IFM_ETHER | IFM_HPNA_1, 0, NULL); 1002 } 1003 1004 #define DC_POLY 0xEDB88320 1005 #define DC_BITS_512 9 1006 #define DC_BITS_128 7 1007 #define DC_BITS_64 6 1008 1009 static u_int32_t 1010 dc_crc_le(struct dc_softc *sc, caddr_t addr) 1011 { 1012 u_int32_t idx, bit, data, crc; 1013 1014 /* Compute CRC for the address value. */ 1015 crc = 0xFFFFFFFF; /* initial value */ 1016 1017 for (idx = 0; idx < 6; idx++) { 1018 for (data = *addr++, bit = 0; bit < 8; bit++, data >>= 1) 1019 crc = (crc >> 1) ^ (((crc ^ data) & 1) ? DC_POLY : 0); 1020 } 1021 1022 /* 1023 * The hash table on the PNIC II and the MX98715AEC-C/D/E 1024 * chips is only 128 bits wide. 1025 */ 1026 if (sc->dc_flags & DC_128BIT_HASH) 1027 return (crc & ((1 << DC_BITS_128) - 1)); 1028 1029 /* The hash table on the MX98715BEC is only 64 bits wide. */ 1030 if (sc->dc_flags & DC_64BIT_HASH) 1031 return (crc & ((1 << DC_BITS_64) - 1)); 1032 1033 /* Xircom's hash filtering table is different (read: weird) */ 1034 /* Xircom uses the LEAST significant bits */ 1035 if (DC_IS_XIRCOM(sc)) { 1036 if ((crc & 0x180) == 0x180) 1037 return ((crc & 0x0F) + (crc & 0x70) * 3 + (14 << 4)); 1038 else 1039 return ((crc & 0x1F) + ((crc >> 1) & 0xF0) * 3 + 1040 (12 << 4)); 1041 } 1042 1043 return (crc & ((1 << DC_BITS_512) - 1)); 1044 } 1045 1046 /* 1047 * Calculate CRC of a multicast group address, return the lower 6 bits. 1048 */ 1049 static u_int32_t 1050 dc_crc_be(caddr_t addr) 1051 { 1052 u_int32_t crc, carry; 1053 int i, j; 1054 u_int8_t c; 1055 1056 /* Compute CRC for the address value. */ 1057 crc = 0xFFFFFFFF; /* initial value */ 1058 1059 for (i = 0; i < 6; i++) { 1060 c = *(addr + i); 1061 for (j = 0; j < 8; j++) { 1062 carry = ((crc & 0x80000000) ? 1 : 0) ^ (c & 0x01); 1063 crc <<= 1; 1064 c >>= 1; 1065 if (carry) 1066 crc = (crc ^ 0x04c11db6) | carry; 1067 } 1068 } 1069 1070 /* Return the filter bit position. */ 1071 return ((crc >> 26) & 0x0000003F); 1072 } 1073 1074 /* 1075 * 21143-style RX filter setup routine. Filter programming is done by 1076 * downloading a special setup frame into the TX engine. 21143, Macronix, 1077 * PNIC, PNIC II and Davicom chips are programmed this way. 1078 * 1079 * We always program the chip using 'hash perfect' mode, i.e. one perfect 1080 * address (our node address) and a 512-bit hash filter for multicast 1081 * frames. We also sneak the broadcast address into the hash filter since 1082 * we need that too. 1083 */ 1084 static void 1085 dc_setfilt_21143(struct dc_softc *sc) 1086 { 1087 struct dc_desc *sframe; 1088 u_int32_t h, *sp; 1089 struct ifmultiaddr *ifma; 1090 struct ifnet *ifp; 1091 int i; 1092 1093 ifp = &sc->arpcom.ac_if; 1094 1095 i = sc->dc_cdata.dc_tx_prod; 1096 DC_INC(sc->dc_cdata.dc_tx_prod, DC_TX_LIST_CNT); 1097 sc->dc_cdata.dc_tx_cnt++; 1098 sframe = &sc->dc_ldata->dc_tx_list[i]; 1099 sp = (u_int32_t *)&sc->dc_cdata.dc_sbuf; 1100 bzero(sp, DC_SFRAME_LEN); 1101 1102 sframe->dc_data = vtophys(&sc->dc_cdata.dc_sbuf); 1103 sframe->dc_ctl = DC_SFRAME_LEN | DC_TXCTL_SETUP | DC_TXCTL_TLINK | 1104 DC_FILTER_HASHPERF | DC_TXCTL_FINT; 1105 1106 sc->dc_cdata.dc_tx_chain[i] = (struct mbuf *)&sc->dc_cdata.dc_sbuf; 1107 1108 /* If we want promiscuous mode, set the allframes bit. */ 1109 if (ifp->if_flags & IFF_PROMISC) 1110 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC); 1111 else 1112 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC); 1113 1114 if (ifp->if_flags & IFF_ALLMULTI) 1115 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI); 1116 else 1117 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI); 1118 1119 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 1120 if (ifma->ifma_addr->sa_family != AF_LINK) 1121 continue; 1122 h = dc_crc_le(sc, 1123 LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 1124 sp[h >> 4] |= 1 << (h & 0xF); 1125 } 1126 1127 if (ifp->if_flags & IFF_BROADCAST) { 1128 h = dc_crc_le(sc, (caddr_t)ifp->if_broadcastaddr); 1129 sp[h >> 4] |= 1 << (h & 0xF); 1130 } 1131 1132 /* Set our MAC address */ 1133 sp[39] = ((u_int16_t *)sc->arpcom.ac_enaddr)[0]; 1134 sp[40] = ((u_int16_t *)sc->arpcom.ac_enaddr)[1]; 1135 sp[41] = ((u_int16_t *)sc->arpcom.ac_enaddr)[2]; 1136 1137 sframe->dc_status = DC_TXSTAT_OWN; 1138 CSR_WRITE_4(sc, DC_TXSTART, 0xFFFFFFFF); 1139 1140 /* 1141 * The PNIC takes an exceedingly long time to process its 1142 * setup frame; wait 10ms after posting the setup frame 1143 * before proceeding, just so it has time to swallow its 1144 * medicine. 1145 */ 1146 DELAY(10000); 1147 1148 ifp->if_timer = 5; 1149 } 1150 1151 static void 1152 dc_setfilt_admtek(struct dc_softc *sc) 1153 { 1154 struct ifnet *ifp; 1155 struct ifmultiaddr *ifma; 1156 int h = 0; 1157 u_int32_t hashes[2] = { 0, 0 }; 1158 1159 ifp = &sc->arpcom.ac_if; 1160 1161 /* Init our MAC address. */ 1162 CSR_WRITE_4(sc, DC_AL_PAR0, *(u_int32_t *)(&sc->arpcom.ac_enaddr[0])); 1163 CSR_WRITE_4(sc, DC_AL_PAR1, *(u_int32_t *)(&sc->arpcom.ac_enaddr[4])); 1164 1165 /* If we want promiscuous mode, set the allframes bit. */ 1166 if (ifp->if_flags & IFF_PROMISC) 1167 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC); 1168 else 1169 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC); 1170 1171 if (ifp->if_flags & IFF_ALLMULTI) 1172 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI); 1173 else 1174 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI); 1175 1176 /* First, zot all the existing hash bits. */ 1177 CSR_WRITE_4(sc, DC_AL_MAR0, 0); 1178 CSR_WRITE_4(sc, DC_AL_MAR1, 0); 1179 1180 /* 1181 * If we're already in promisc or allmulti mode, we 1182 * don't have to bother programming the multicast filter. 1183 */ 1184 if (ifp->if_flags & (IFF_PROMISC | IFF_ALLMULTI)) 1185 return; 1186 1187 /* Now program new ones. */ 1188 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 1189 if (ifma->ifma_addr->sa_family != AF_LINK) 1190 continue; 1191 if (DC_IS_CENTAUR(sc)) 1192 h = dc_crc_le(sc, LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 1193 else 1194 h = dc_crc_be(LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 1195 if (h < 32) 1196 hashes[0] |= (1 << h); 1197 else 1198 hashes[1] |= (1 << (h - 32)); 1199 } 1200 1201 CSR_WRITE_4(sc, DC_AL_MAR0, hashes[0]); 1202 CSR_WRITE_4(sc, DC_AL_MAR1, hashes[1]); 1203 } 1204 1205 static void 1206 dc_setfilt_asix(struct dc_softc *sc) 1207 { 1208 struct ifnet *ifp; 1209 struct ifmultiaddr *ifma; 1210 int h = 0; 1211 u_int32_t hashes[2] = { 0, 0 }; 1212 1213 ifp = &sc->arpcom.ac_if; 1214 1215 /* Init our MAC address */ 1216 CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_PAR0); 1217 CSR_WRITE_4(sc, DC_AX_FILTDATA, 1218 *(u_int32_t *)(&sc->arpcom.ac_enaddr[0])); 1219 CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_PAR1); 1220 CSR_WRITE_4(sc, DC_AX_FILTDATA, 1221 *(u_int32_t *)(&sc->arpcom.ac_enaddr[4])); 1222 1223 /* If we want promiscuous mode, set the allframes bit. */ 1224 if (ifp->if_flags & IFF_PROMISC) 1225 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC); 1226 else 1227 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC); 1228 1229 if (ifp->if_flags & IFF_ALLMULTI) 1230 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI); 1231 else 1232 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI); 1233 1234 /* 1235 * The ASIX chip has a special bit to enable reception 1236 * of broadcast frames. 1237 */ 1238 if (ifp->if_flags & IFF_BROADCAST) 1239 DC_SETBIT(sc, DC_NETCFG, DC_AX_NETCFG_RX_BROAD); 1240 else 1241 DC_CLRBIT(sc, DC_NETCFG, DC_AX_NETCFG_RX_BROAD); 1242 1243 /* first, zot all the existing hash bits */ 1244 CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_MAR0); 1245 CSR_WRITE_4(sc, DC_AX_FILTDATA, 0); 1246 CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_MAR1); 1247 CSR_WRITE_4(sc, DC_AX_FILTDATA, 0); 1248 1249 /* 1250 * If we're already in promisc or allmulti mode, we 1251 * don't have to bother programming the multicast filter. 1252 */ 1253 if (ifp->if_flags & (IFF_PROMISC | IFF_ALLMULTI)) 1254 return; 1255 1256 /* now program new ones */ 1257 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 1258 if (ifma->ifma_addr->sa_family != AF_LINK) 1259 continue; 1260 h = dc_crc_be(LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 1261 if (h < 32) 1262 hashes[0] |= (1 << h); 1263 else 1264 hashes[1] |= (1 << (h - 32)); 1265 } 1266 1267 CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_MAR0); 1268 CSR_WRITE_4(sc, DC_AX_FILTDATA, hashes[0]); 1269 CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_MAR1); 1270 CSR_WRITE_4(sc, DC_AX_FILTDATA, hashes[1]); 1271 } 1272 1273 static void 1274 dc_setfilt_xircom(struct dc_softc *sc) 1275 { 1276 struct ifnet *ifp; 1277 struct ifmultiaddr *ifma; 1278 struct dc_desc *sframe; 1279 u_int32_t h, *sp; 1280 int i; 1281 1282 ifp = &sc->arpcom.ac_if; 1283 DC_CLRBIT(sc, DC_NETCFG, (DC_NETCFG_TX_ON | DC_NETCFG_RX_ON)); 1284 1285 i = sc->dc_cdata.dc_tx_prod; 1286 DC_INC(sc->dc_cdata.dc_tx_prod, DC_TX_LIST_CNT); 1287 sc->dc_cdata.dc_tx_cnt++; 1288 sframe = &sc->dc_ldata->dc_tx_list[i]; 1289 sp = (u_int32_t *)&sc->dc_cdata.dc_sbuf; 1290 bzero(sp, DC_SFRAME_LEN); 1291 1292 sframe->dc_data = vtophys(&sc->dc_cdata.dc_sbuf); 1293 sframe->dc_ctl = DC_SFRAME_LEN | DC_TXCTL_SETUP | DC_TXCTL_TLINK | 1294 DC_FILTER_HASHPERF | DC_TXCTL_FINT; 1295 1296 sc->dc_cdata.dc_tx_chain[i] = (struct mbuf *)&sc->dc_cdata.dc_sbuf; 1297 1298 /* If we want promiscuous mode, set the allframes bit. */ 1299 if (ifp->if_flags & IFF_PROMISC) 1300 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC); 1301 else 1302 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC); 1303 1304 if (ifp->if_flags & IFF_ALLMULTI) 1305 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI); 1306 else 1307 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI); 1308 1309 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 1310 if (ifma->ifma_addr->sa_family != AF_LINK) 1311 continue; 1312 h = dc_crc_le(sc, 1313 LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 1314 sp[h >> 4] |= 1 << (h & 0xF); 1315 } 1316 1317 if (ifp->if_flags & IFF_BROADCAST) { 1318 h = dc_crc_le(sc, (caddr_t)ifp->if_broadcastaddr); 1319 sp[h >> 4] |= 1 << (h & 0xF); 1320 } 1321 1322 /* Set our MAC address */ 1323 sp[0] = ((u_int16_t *)sc->arpcom.ac_enaddr)[0]; 1324 sp[1] = ((u_int16_t *)sc->arpcom.ac_enaddr)[1]; 1325 sp[2] = ((u_int16_t *)sc->arpcom.ac_enaddr)[2]; 1326 1327 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_TX_ON); 1328 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_ON); 1329 ifp->if_flags |= IFF_RUNNING; 1330 sframe->dc_status = DC_TXSTAT_OWN; 1331 CSR_WRITE_4(sc, DC_TXSTART, 0xFFFFFFFF); 1332 1333 /* 1334 * Wait some time... 1335 */ 1336 DELAY(1000); 1337 1338 ifp->if_timer = 5; 1339 } 1340 1341 static void 1342 dc_setfilt(struct dc_softc *sc) 1343 { 1344 1345 if (DC_IS_INTEL(sc) || DC_IS_MACRONIX(sc) || DC_IS_PNIC(sc) || 1346 DC_IS_PNICII(sc) || DC_IS_DAVICOM(sc) || DC_IS_CONEXANT(sc)) 1347 dc_setfilt_21143(sc); 1348 1349 if (DC_IS_ASIX(sc)) 1350 dc_setfilt_asix(sc); 1351 1352 if (DC_IS_ADMTEK(sc)) 1353 dc_setfilt_admtek(sc); 1354 1355 if (DC_IS_XIRCOM(sc)) 1356 dc_setfilt_xircom(sc); 1357 } 1358 1359 /* 1360 * In order to fiddle with the 'full-duplex' and '100Mbps' bits in 1361 * the netconfig register, we first have to put the transmit and/or 1362 * receive logic in the idle state. 1363 */ 1364 static void 1365 dc_setcfg(struct dc_softc *sc, int media) 1366 { 1367 int i, restart = 0, watchdogreg; 1368 u_int32_t isr; 1369 1370 if (IFM_SUBTYPE(media) == IFM_NONE) 1371 return; 1372 1373 if (CSR_READ_4(sc, DC_NETCFG) & (DC_NETCFG_TX_ON | DC_NETCFG_RX_ON)) { 1374 restart = 1; 1375 DC_CLRBIT(sc, DC_NETCFG, (DC_NETCFG_TX_ON | DC_NETCFG_RX_ON)); 1376 1377 for (i = 0; i < DC_TIMEOUT; i++) { 1378 isr = CSR_READ_4(sc, DC_ISR); 1379 if (isr & DC_ISR_TX_IDLE && 1380 ((isr & DC_ISR_RX_STATE) == DC_RXSTATE_STOPPED || 1381 (isr & DC_ISR_RX_STATE) == DC_RXSTATE_WAIT)) 1382 break; 1383 DELAY(10); 1384 } 1385 1386 if (i == DC_TIMEOUT) 1387 printf("dc%d: failed to force tx and " 1388 "rx to idle state\n", sc->dc_unit); 1389 } 1390 1391 if (IFM_SUBTYPE(media) == IFM_100_TX) { 1392 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_SPEEDSEL); 1393 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_HEARTBEAT); 1394 if (sc->dc_pmode == DC_PMODE_MII) { 1395 if (DC_IS_INTEL(sc)) { 1396 /* There's a write enable bit here that reads as 1. */ 1397 watchdogreg = CSR_READ_4(sc, DC_WATCHDOG); 1398 watchdogreg &= ~DC_WDOG_CTLWREN; 1399 watchdogreg |= DC_WDOG_JABBERDIS; 1400 CSR_WRITE_4(sc, DC_WATCHDOG, watchdogreg); 1401 } else { 1402 DC_SETBIT(sc, DC_WATCHDOG, DC_WDOG_JABBERDIS); 1403 } 1404 DC_CLRBIT(sc, DC_NETCFG, (DC_NETCFG_PCS | 1405 DC_NETCFG_PORTSEL | DC_NETCFG_SCRAMBLER)); 1406 if (sc->dc_type == DC_TYPE_98713) 1407 DC_SETBIT(sc, DC_NETCFG, (DC_NETCFG_PCS | 1408 DC_NETCFG_SCRAMBLER)); 1409 if (!DC_IS_DAVICOM(sc)) 1410 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL); 1411 DC_CLRBIT(sc, DC_10BTCTRL, 0xFFFF); 1412 if (DC_IS_INTEL(sc)) 1413 dc_apply_fixup(sc, IFM_AUTO); 1414 } else { 1415 if (DC_IS_PNIC(sc)) { 1416 DC_PN_GPIO_SETBIT(sc, DC_PN_GPIO_SPEEDSEL); 1417 DC_PN_GPIO_SETBIT(sc, DC_PN_GPIO_100TX_LOOP); 1418 DC_SETBIT(sc, DC_PN_NWAY, DC_PN_NWAY_SPEEDSEL); 1419 } 1420 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL); 1421 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PCS); 1422 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_SCRAMBLER); 1423 if (DC_IS_INTEL(sc)) 1424 dc_apply_fixup(sc, 1425 (media & IFM_GMASK) == IFM_FDX ? 1426 IFM_100_TX | IFM_FDX : IFM_100_TX); 1427 } 1428 } 1429 1430 if (IFM_SUBTYPE(media) == IFM_10_T) { 1431 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_SPEEDSEL); 1432 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_HEARTBEAT); 1433 if (sc->dc_pmode == DC_PMODE_MII) { 1434 /* There's a write enable bit here that reads as 1. */ 1435 if (DC_IS_INTEL(sc)) { 1436 watchdogreg = CSR_READ_4(sc, DC_WATCHDOG); 1437 watchdogreg &= ~DC_WDOG_CTLWREN; 1438 watchdogreg |= DC_WDOG_JABBERDIS; 1439 CSR_WRITE_4(sc, DC_WATCHDOG, watchdogreg); 1440 } else { 1441 DC_SETBIT(sc, DC_WATCHDOG, DC_WDOG_JABBERDIS); 1442 } 1443 DC_CLRBIT(sc, DC_NETCFG, (DC_NETCFG_PCS | 1444 DC_NETCFG_PORTSEL | DC_NETCFG_SCRAMBLER)); 1445 if (sc->dc_type == DC_TYPE_98713) 1446 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PCS); 1447 if (!DC_IS_DAVICOM(sc)) 1448 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL); 1449 DC_CLRBIT(sc, DC_10BTCTRL, 0xFFFF); 1450 if (DC_IS_INTEL(sc)) 1451 dc_apply_fixup(sc, IFM_AUTO); 1452 } else { 1453 if (DC_IS_PNIC(sc)) { 1454 DC_PN_GPIO_CLRBIT(sc, DC_PN_GPIO_SPEEDSEL); 1455 DC_PN_GPIO_SETBIT(sc, DC_PN_GPIO_100TX_LOOP); 1456 DC_CLRBIT(sc, DC_PN_NWAY, DC_PN_NWAY_SPEEDSEL); 1457 } 1458 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL); 1459 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_PCS); 1460 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_SCRAMBLER); 1461 if (DC_IS_INTEL(sc)) { 1462 DC_CLRBIT(sc, DC_SIARESET, DC_SIA_RESET); 1463 DC_CLRBIT(sc, DC_10BTCTRL, 0xFFFF); 1464 if ((media & IFM_GMASK) == IFM_FDX) 1465 DC_SETBIT(sc, DC_10BTCTRL, 0x7F3D); 1466 else 1467 DC_SETBIT(sc, DC_10BTCTRL, 0x7F3F); 1468 DC_SETBIT(sc, DC_SIARESET, DC_SIA_RESET); 1469 DC_CLRBIT(sc, DC_10BTCTRL, 1470 DC_TCTL_AUTONEGENBL); 1471 dc_apply_fixup(sc, 1472 (media & IFM_GMASK) == IFM_FDX ? 1473 IFM_10_T | IFM_FDX : IFM_10_T); 1474 DELAY(20000); 1475 } 1476 } 1477 } 1478 1479 /* 1480 * If this is a Davicom DM9102A card with a DM9801 HomePNA 1481 * PHY and we want HomePNA mode, set the portsel bit to turn 1482 * on the external MII port. 1483 */ 1484 if (DC_IS_DAVICOM(sc)) { 1485 if (IFM_SUBTYPE(media) == IFM_HPNA_1) { 1486 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL); 1487 sc->dc_link = 1; 1488 } else { 1489 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL); 1490 } 1491 } 1492 1493 if ((media & IFM_GMASK) == IFM_FDX) { 1494 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_FULLDUPLEX); 1495 if (sc->dc_pmode == DC_PMODE_SYM && DC_IS_PNIC(sc)) 1496 DC_SETBIT(sc, DC_PN_NWAY, DC_PN_NWAY_DUPLEX); 1497 } else { 1498 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_FULLDUPLEX); 1499 if (sc->dc_pmode == DC_PMODE_SYM && DC_IS_PNIC(sc)) 1500 DC_CLRBIT(sc, DC_PN_NWAY, DC_PN_NWAY_DUPLEX); 1501 } 1502 1503 if (restart) 1504 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_TX_ON | DC_NETCFG_RX_ON); 1505 } 1506 1507 static void 1508 dc_reset(struct dc_softc *sc) 1509 { 1510 int i; 1511 1512 DC_SETBIT(sc, DC_BUSCTL, DC_BUSCTL_RESET); 1513 1514 for (i = 0; i < DC_TIMEOUT; i++) { 1515 DELAY(10); 1516 if (!(CSR_READ_4(sc, DC_BUSCTL) & DC_BUSCTL_RESET)) 1517 break; 1518 } 1519 1520 if (DC_IS_ASIX(sc) || DC_IS_ADMTEK(sc) || DC_IS_CONEXANT(sc) || 1521 DC_IS_XIRCOM(sc) || DC_IS_INTEL(sc)) { 1522 DELAY(10000); 1523 DC_CLRBIT(sc, DC_BUSCTL, DC_BUSCTL_RESET); 1524 i = 0; 1525 } 1526 1527 if (i == DC_TIMEOUT) 1528 printf("dc%d: reset never completed!\n", sc->dc_unit); 1529 1530 /* Wait a little while for the chip to get its brains in order. */ 1531 DELAY(1000); 1532 1533 CSR_WRITE_4(sc, DC_IMR, 0x00000000); 1534 CSR_WRITE_4(sc, DC_BUSCTL, 0x00000000); 1535 CSR_WRITE_4(sc, DC_NETCFG, 0x00000000); 1536 1537 /* 1538 * Bring the SIA out of reset. In some cases, it looks 1539 * like failing to unreset the SIA soon enough gets it 1540 * into a state where it will never come out of reset 1541 * until we reset the whole chip again. 1542 */ 1543 if (DC_IS_INTEL(sc)) { 1544 DC_SETBIT(sc, DC_SIARESET, DC_SIA_RESET); 1545 CSR_WRITE_4(sc, DC_10BTCTRL, 0); 1546 CSR_WRITE_4(sc, DC_WATCHDOG, 0); 1547 } 1548 } 1549 1550 static struct dc_type * 1551 dc_devtype(device_t dev) 1552 { 1553 struct dc_type *t; 1554 u_int32_t rev; 1555 1556 t = dc_devs; 1557 1558 while (t->dc_name != NULL) { 1559 if ((pci_get_vendor(dev) == t->dc_vid) && 1560 (pci_get_device(dev) == t->dc_did)) { 1561 /* Check the PCI revision */ 1562 rev = pci_read_config(dev, DC_PCI_CFRV, 4) & 0xFF; 1563 if (t->dc_did == DC_DEVICEID_98713 && 1564 rev >= DC_REVISION_98713A) 1565 t++; 1566 if (t->dc_did == DC_DEVICEID_98713_CP && 1567 rev >= DC_REVISION_98713A) 1568 t++; 1569 if (t->dc_did == DC_DEVICEID_987x5 && 1570 rev >= DC_REVISION_98715AEC_C) 1571 t++; 1572 if (t->dc_did == DC_DEVICEID_987x5 && 1573 rev >= DC_REVISION_98725) 1574 t++; 1575 if (t->dc_did == DC_DEVICEID_AX88140A && 1576 rev >= DC_REVISION_88141) 1577 t++; 1578 if (t->dc_did == DC_DEVICEID_82C168 && 1579 rev >= DC_REVISION_82C169) 1580 t++; 1581 if (t->dc_did == DC_DEVICEID_DM9102 && 1582 rev >= DC_REVISION_DM9102A) 1583 t++; 1584 return (t); 1585 } 1586 t++; 1587 } 1588 1589 return (NULL); 1590 } 1591 1592 /* 1593 * Probe for a 21143 or clone chip. Check the PCI vendor and device 1594 * IDs against our list and return a device name if we find a match. 1595 * We do a little bit of extra work to identify the exact type of 1596 * chip. The MX98713 and MX98713A have the same PCI vendor/device ID, 1597 * but different revision IDs. The same is true for 98715/98715A 1598 * chips and the 98725, as well as the ASIX and ADMtek chips. In some 1599 * cases, the exact chip revision affects driver behavior. 1600 */ 1601 static int 1602 dc_probe(device_t dev) 1603 { 1604 struct dc_type *t; 1605 1606 t = dc_devtype(dev); 1607 1608 if (t != NULL) { 1609 device_set_desc(dev, t->dc_name); 1610 return (0); 1611 } 1612 1613 return (ENXIO); 1614 } 1615 1616 static void 1617 dc_acpi(device_t dev) 1618 { 1619 int unit; 1620 u_int32_t iobase, membase, irq; 1621 1622 unit = device_get_unit(dev); 1623 1624 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) { 1625 /* Save important PCI config data. */ 1626 iobase = pci_read_config(dev, DC_PCI_CFBIO, 4); 1627 membase = pci_read_config(dev, DC_PCI_CFBMA, 4); 1628 irq = pci_read_config(dev, DC_PCI_CFIT, 4); 1629 1630 /* Reset the power state. */ 1631 printf("dc%d: chip is in D%d power mode " 1632 "-- setting to D0\n", unit, 1633 pci_get_powerstate(dev)); 1634 pci_set_powerstate(dev, PCI_POWERSTATE_D0); 1635 1636 /* Restore PCI config data. */ 1637 pci_write_config(dev, DC_PCI_CFBIO, iobase, 4); 1638 pci_write_config(dev, DC_PCI_CFBMA, membase, 4); 1639 pci_write_config(dev, DC_PCI_CFIT, irq, 4); 1640 } 1641 } 1642 1643 static void 1644 dc_apply_fixup(struct dc_softc *sc, int media) 1645 { 1646 struct dc_mediainfo *m; 1647 u_int8_t *p; 1648 int i; 1649 u_int32_t reg; 1650 1651 m = sc->dc_mi; 1652 1653 while (m != NULL) { 1654 if (m->dc_media == media) 1655 break; 1656 m = m->dc_next; 1657 } 1658 1659 if (m == NULL) 1660 return; 1661 1662 for (i = 0, p = m->dc_reset_ptr; i < m->dc_reset_len; i++, p += 2) { 1663 reg = (p[0] | (p[1] << 8)) << 16; 1664 CSR_WRITE_4(sc, DC_WATCHDOG, reg); 1665 } 1666 1667 for (i = 0, p = m->dc_gp_ptr; i < m->dc_gp_len; i++, p += 2) { 1668 reg = (p[0] | (p[1] << 8)) << 16; 1669 CSR_WRITE_4(sc, DC_WATCHDOG, reg); 1670 } 1671 } 1672 1673 static void 1674 dc_decode_leaf_sia(struct dc_softc *sc, struct dc_eblock_sia *l) 1675 { 1676 struct dc_mediainfo *m; 1677 1678 m = malloc(sizeof(struct dc_mediainfo), M_DEVBUF, M_NOWAIT | M_ZERO); 1679 if (l->dc_sia_code == DC_SIA_CODE_10BT) 1680 m->dc_media = IFM_10_T; 1681 1682 if (l->dc_sia_code == DC_SIA_CODE_10BT_FDX) 1683 m->dc_media = IFM_10_T | IFM_FDX; 1684 1685 if (l->dc_sia_code == DC_SIA_CODE_10B2) 1686 m->dc_media = IFM_10_2; 1687 1688 if (l->dc_sia_code == DC_SIA_CODE_10B5) 1689 m->dc_media = IFM_10_5; 1690 1691 m->dc_gp_len = 2; 1692 m->dc_gp_ptr = (u_int8_t *)&l->dc_sia_gpio_ctl; 1693 1694 m->dc_next = sc->dc_mi; 1695 sc->dc_mi = m; 1696 1697 sc->dc_pmode = DC_PMODE_SIA; 1698 } 1699 1700 static void 1701 dc_decode_leaf_sym(struct dc_softc *sc, struct dc_eblock_sym *l) 1702 { 1703 struct dc_mediainfo *m; 1704 1705 m = malloc(sizeof(struct dc_mediainfo), M_DEVBUF, M_NOWAIT | M_ZERO); 1706 if (l->dc_sym_code == DC_SYM_CODE_100BT) 1707 m->dc_media = IFM_100_TX; 1708 1709 if (l->dc_sym_code == DC_SYM_CODE_100BT_FDX) 1710 m->dc_media = IFM_100_TX | IFM_FDX; 1711 1712 m->dc_gp_len = 2; 1713 m->dc_gp_ptr = (u_int8_t *)&l->dc_sym_gpio_ctl; 1714 1715 m->dc_next = sc->dc_mi; 1716 sc->dc_mi = m; 1717 1718 sc->dc_pmode = DC_PMODE_SYM; 1719 } 1720 1721 static void 1722 dc_decode_leaf_mii(struct dc_softc *sc, struct dc_eblock_mii *l) 1723 { 1724 struct dc_mediainfo *m; 1725 u_int8_t *p; 1726 1727 m = malloc(sizeof(struct dc_mediainfo), M_DEVBUF, M_NOWAIT | M_ZERO); 1728 /* We abuse IFM_AUTO to represent MII. */ 1729 m->dc_media = IFM_AUTO; 1730 m->dc_gp_len = l->dc_gpr_len; 1731 1732 p = (u_int8_t *)l; 1733 p += sizeof(struct dc_eblock_mii); 1734 m->dc_gp_ptr = p; 1735 p += 2 * l->dc_gpr_len; 1736 m->dc_reset_len = *p; 1737 p++; 1738 m->dc_reset_ptr = p; 1739 1740 m->dc_next = sc->dc_mi; 1741 sc->dc_mi = m; 1742 } 1743 1744 static void 1745 dc_read_srom(struct dc_softc *sc, int bits) 1746 { 1747 int size; 1748 1749 size = 2 << bits; 1750 sc->dc_srom = malloc(size, M_DEVBUF, M_NOWAIT); 1751 dc_read_eeprom(sc, (caddr_t)sc->dc_srom, 0, (size / 2), 0); 1752 } 1753 1754 static void 1755 dc_parse_21143_srom(struct dc_softc *sc) 1756 { 1757 struct dc_leaf_hdr *lhdr; 1758 struct dc_eblock_hdr *hdr; 1759 int have_mii, i, loff; 1760 char *ptr; 1761 1762 have_mii = 0; 1763 loff = sc->dc_srom[27]; 1764 lhdr = (struct dc_leaf_hdr *)&(sc->dc_srom[loff]); 1765 1766 ptr = (char *)lhdr; 1767 ptr += sizeof(struct dc_leaf_hdr) - 1; 1768 /* 1769 * Look if we got a MII media block. 1770 */ 1771 for (i = 0; i < lhdr->dc_mcnt; i++) { 1772 hdr = (struct dc_eblock_hdr *)ptr; 1773 if (hdr->dc_type == DC_EBLOCK_MII) 1774 have_mii++; 1775 1776 ptr += (hdr->dc_len & 0x7F); 1777 ptr++; 1778 } 1779 1780 /* 1781 * Do the same thing again. Only use SIA and SYM media 1782 * blocks if no MII media block is available. 1783 */ 1784 ptr = (char *)lhdr; 1785 ptr += sizeof(struct dc_leaf_hdr) - 1; 1786 for (i = 0; i < lhdr->dc_mcnt; i++) { 1787 hdr = (struct dc_eblock_hdr *)ptr; 1788 switch (hdr->dc_type) { 1789 case DC_EBLOCK_MII: 1790 dc_decode_leaf_mii(sc, (struct dc_eblock_mii *)hdr); 1791 break; 1792 case DC_EBLOCK_SIA: 1793 if (! have_mii) 1794 dc_decode_leaf_sia(sc, 1795 (struct dc_eblock_sia *)hdr); 1796 break; 1797 case DC_EBLOCK_SYM: 1798 if (! have_mii) 1799 dc_decode_leaf_sym(sc, 1800 (struct dc_eblock_sym *)hdr); 1801 break; 1802 default: 1803 /* Don't care. Yet. */ 1804 break; 1805 } 1806 ptr += (hdr->dc_len & 0x7F); 1807 ptr++; 1808 } 1809 } 1810 1811 /* 1812 * Attach the interface. Allocate softc structures, do ifmedia 1813 * setup and ethernet/BPF attach. 1814 */ 1815 static int 1816 dc_attach(device_t dev) 1817 { 1818 int tmp = 0; 1819 u_char eaddr[ETHER_ADDR_LEN]; 1820 u_int32_t command; 1821 struct dc_softc *sc; 1822 struct ifnet *ifp; 1823 u_int32_t revision; 1824 int unit, error = 0, rid, mac_offset; 1825 u_int8_t *mac; 1826 1827 sc = device_get_softc(dev); 1828 unit = device_get_unit(dev); 1829 1830 mtx_init(&sc->dc_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 1831 MTX_DEF | MTX_RECURSE); 1832 1833 /* 1834 * Handle power management nonsense. 1835 */ 1836 dc_acpi(dev); 1837 1838 /* 1839 * Map control/status registers. 1840 */ 1841 pci_enable_busmaster(dev); 1842 1843 rid = DC_RID; 1844 sc->dc_res = bus_alloc_resource(dev, DC_RES, &rid, 1845 0, ~0, 1, RF_ACTIVE); 1846 1847 if (sc->dc_res == NULL) { 1848 printf("dc%d: couldn't map ports/memory\n", unit); 1849 error = ENXIO; 1850 goto fail; 1851 } 1852 1853 sc->dc_btag = rman_get_bustag(sc->dc_res); 1854 sc->dc_bhandle = rman_get_bushandle(sc->dc_res); 1855 1856 /* Allocate interrupt. */ 1857 rid = 0; 1858 sc->dc_irq = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, 0, ~0, 1, 1859 RF_SHAREABLE | RF_ACTIVE); 1860 1861 if (sc->dc_irq == NULL) { 1862 printf("dc%d: couldn't map interrupt\n", unit); 1863 error = ENXIO; 1864 goto fail; 1865 } 1866 1867 /* Need this info to decide on a chip type. */ 1868 sc->dc_info = dc_devtype(dev); 1869 revision = pci_read_config(dev, DC_PCI_CFRV, 4) & 0x000000FF; 1870 1871 /* Get the eeprom width, but PNIC and XIRCOM have diff eeprom */ 1872 if (sc->dc_info->dc_did != DC_DEVICEID_82C168 && 1873 sc->dc_info->dc_did != DC_DEVICEID_X3201) 1874 dc_eeprom_width(sc); 1875 1876 switch (sc->dc_info->dc_did) { 1877 case DC_DEVICEID_21143: 1878 sc->dc_type = DC_TYPE_21143; 1879 sc->dc_flags |= DC_TX_POLL | DC_TX_USE_TX_INTR; 1880 sc->dc_flags |= DC_REDUCED_MII_POLL; 1881 /* Save EEPROM contents so we can parse them later. */ 1882 dc_read_srom(sc, sc->dc_romwidth); 1883 break; 1884 case DC_DEVICEID_DM9009: 1885 case DC_DEVICEID_DM9100: 1886 case DC_DEVICEID_DM9102: 1887 sc->dc_type = DC_TYPE_DM9102; 1888 sc->dc_flags |= DC_TX_COALESCE | DC_TX_INTR_ALWAYS; 1889 sc->dc_flags |= DC_REDUCED_MII_POLL | DC_TX_STORENFWD; 1890 sc->dc_pmode = DC_PMODE_MII; 1891 /* Increase the latency timer value. */ 1892 command = pci_read_config(dev, DC_PCI_CFLT, 4); 1893 command &= 0xFFFF00FF; 1894 command |= 0x00008000; 1895 pci_write_config(dev, DC_PCI_CFLT, command, 4); 1896 break; 1897 case DC_DEVICEID_AL981: 1898 sc->dc_type = DC_TYPE_AL981; 1899 sc->dc_flags |= DC_TX_USE_TX_INTR; 1900 sc->dc_flags |= DC_TX_ADMTEK_WAR; 1901 sc->dc_pmode = DC_PMODE_MII; 1902 dc_read_srom(sc, sc->dc_romwidth); 1903 break; 1904 case DC_DEVICEID_AN985: 1905 case DC_DEVICEID_ADM9511: 1906 case DC_DEVICEID_ADM9513: 1907 case DC_DEVICEID_FE2500: 1908 case DC_DEVICEID_EN2242: 1909 case DC_DEVICEID_HAWKING_PN672TX: 1910 case DC_DEVICEID_3CSOHOB: 1911 sc->dc_type = DC_TYPE_AN985; 1912 sc->dc_flags |= DC_64BIT_HASH; 1913 sc->dc_flags |= DC_TX_USE_TX_INTR; 1914 sc->dc_flags |= DC_TX_ADMTEK_WAR; 1915 sc->dc_pmode = DC_PMODE_MII; 1916 dc_read_srom(sc, sc->dc_romwidth); 1917 break; 1918 case DC_DEVICEID_98713: 1919 case DC_DEVICEID_98713_CP: 1920 if (revision < DC_REVISION_98713A) { 1921 sc->dc_type = DC_TYPE_98713; 1922 } 1923 if (revision >= DC_REVISION_98713A) { 1924 sc->dc_type = DC_TYPE_98713A; 1925 sc->dc_flags |= DC_21143_NWAY; 1926 } 1927 sc->dc_flags |= DC_REDUCED_MII_POLL; 1928 sc->dc_flags |= DC_TX_POLL | DC_TX_USE_TX_INTR; 1929 break; 1930 case DC_DEVICEID_987x5: 1931 case DC_DEVICEID_EN1217: 1932 /* 1933 * Macronix MX98715AEC-C/D/E parts have only a 1934 * 128-bit hash table. We need to deal with these 1935 * in the same manner as the PNIC II so that we 1936 * get the right number of bits out of the 1937 * CRC routine. 1938 */ 1939 if (revision >= DC_REVISION_98715AEC_C && 1940 revision < DC_REVISION_98725) 1941 sc->dc_flags |= DC_128BIT_HASH; 1942 sc->dc_type = DC_TYPE_987x5; 1943 sc->dc_flags |= DC_TX_POLL | DC_TX_USE_TX_INTR; 1944 sc->dc_flags |= DC_REDUCED_MII_POLL | DC_21143_NWAY; 1945 break; 1946 case DC_DEVICEID_98727: 1947 sc->dc_type = DC_TYPE_987x5; 1948 sc->dc_flags |= DC_TX_POLL | DC_TX_USE_TX_INTR; 1949 sc->dc_flags |= DC_REDUCED_MII_POLL | DC_21143_NWAY; 1950 break; 1951 case DC_DEVICEID_82C115: 1952 sc->dc_type = DC_TYPE_PNICII; 1953 sc->dc_flags |= DC_TX_POLL | DC_TX_USE_TX_INTR | DC_128BIT_HASH; 1954 sc->dc_flags |= DC_REDUCED_MII_POLL | DC_21143_NWAY; 1955 break; 1956 case DC_DEVICEID_82C168: 1957 sc->dc_type = DC_TYPE_PNIC; 1958 sc->dc_flags |= DC_TX_STORENFWD | DC_TX_INTR_ALWAYS; 1959 sc->dc_flags |= DC_PNIC_RX_BUG_WAR; 1960 sc->dc_pnic_rx_buf = malloc(DC_RXLEN * 5, M_DEVBUF, M_NOWAIT); 1961 if (revision < DC_REVISION_82C169) 1962 sc->dc_pmode = DC_PMODE_SYM; 1963 break; 1964 case DC_DEVICEID_AX88140A: 1965 sc->dc_type = DC_TYPE_ASIX; 1966 sc->dc_flags |= DC_TX_USE_TX_INTR | DC_TX_INTR_FIRSTFRAG; 1967 sc->dc_flags |= DC_REDUCED_MII_POLL; 1968 sc->dc_pmode = DC_PMODE_MII; 1969 break; 1970 case DC_DEVICEID_X3201: 1971 sc->dc_type = DC_TYPE_XIRCOM; 1972 sc->dc_flags |= DC_TX_INTR_ALWAYS | DC_TX_COALESCE | 1973 DC_TX_ALIGN; 1974 /* 1975 * We don't actually need to coalesce, but we're doing 1976 * it to obtain a double word aligned buffer. 1977 * The DC_TX_COALESCE flag is required. 1978 */ 1979 sc->dc_pmode = DC_PMODE_MII; 1980 break; 1981 case DC_DEVICEID_RS7112: 1982 sc->dc_type = DC_TYPE_CONEXANT; 1983 sc->dc_flags |= DC_TX_INTR_ALWAYS; 1984 sc->dc_flags |= DC_REDUCED_MII_POLL; 1985 sc->dc_pmode = DC_PMODE_MII; 1986 dc_read_srom(sc, sc->dc_romwidth); 1987 break; 1988 default: 1989 printf("dc%d: unknown device: %x\n", sc->dc_unit, 1990 sc->dc_info->dc_did); 1991 break; 1992 } 1993 1994 /* Save the cache line size. */ 1995 if (DC_IS_DAVICOM(sc)) 1996 sc->dc_cachesize = 0; 1997 else 1998 sc->dc_cachesize = pci_read_config(dev, 1999 DC_PCI_CFLT, 4) & 0xFF; 2000 2001 /* Reset the adapter. */ 2002 dc_reset(sc); 2003 2004 /* Take 21143 out of snooze mode */ 2005 if (DC_IS_INTEL(sc) || DC_IS_XIRCOM(sc)) { 2006 command = pci_read_config(dev, DC_PCI_CFDD, 4); 2007 command &= ~(DC_CFDD_SNOOZE_MODE | DC_CFDD_SLEEP_MODE); 2008 pci_write_config(dev, DC_PCI_CFDD, command, 4); 2009 } 2010 2011 /* 2012 * Try to learn something about the supported media. 2013 * We know that ASIX and ADMtek and Davicom devices 2014 * will *always* be using MII media, so that's a no-brainer. 2015 * The tricky ones are the Macronix/PNIC II and the 2016 * Intel 21143. 2017 */ 2018 if (DC_IS_INTEL(sc)) 2019 dc_parse_21143_srom(sc); 2020 else if (DC_IS_MACRONIX(sc) || DC_IS_PNICII(sc)) { 2021 if (sc->dc_type == DC_TYPE_98713) 2022 sc->dc_pmode = DC_PMODE_MII; 2023 else 2024 sc->dc_pmode = DC_PMODE_SYM; 2025 } else if (!sc->dc_pmode) 2026 sc->dc_pmode = DC_PMODE_MII; 2027 2028 /* 2029 * Get station address from the EEPROM. 2030 */ 2031 switch(sc->dc_type) { 2032 case DC_TYPE_98713: 2033 case DC_TYPE_98713A: 2034 case DC_TYPE_987x5: 2035 case DC_TYPE_PNICII: 2036 dc_read_eeprom(sc, (caddr_t)&mac_offset, 2037 (DC_EE_NODEADDR_OFFSET / 2), 1, 0); 2038 dc_read_eeprom(sc, (caddr_t)&eaddr, (mac_offset / 2), 3, 0); 2039 break; 2040 case DC_TYPE_PNIC: 2041 dc_read_eeprom(sc, (caddr_t)&eaddr, 0, 3, 1); 2042 break; 2043 case DC_TYPE_DM9102: 2044 case DC_TYPE_21143: 2045 case DC_TYPE_ASIX: 2046 dc_read_eeprom(sc, (caddr_t)&eaddr, DC_EE_NODEADDR, 3, 0); 2047 break; 2048 case DC_TYPE_AL981: 2049 case DC_TYPE_AN985: 2050 bcopy(sc->dc_srom + DC_AL_EE_NODEADDR, &eaddr, 2051 ETHER_ADDR_LEN); 2052 dc_read_eeprom(sc, (caddr_t)&eaddr, DC_AL_EE_NODEADDR, 3, 0); 2053 break; 2054 case DC_TYPE_CONEXANT: 2055 bcopy(sc->dc_srom + DC_CONEXANT_EE_NODEADDR, &eaddr, 2056 ETHER_ADDR_LEN); 2057 break; 2058 case DC_TYPE_XIRCOM: 2059 /* The MAC comes from the CIS. */ 2060 mac = pci_get_ether(dev); 2061 if (!mac) { 2062 device_printf(dev, "No station address in CIS!\n"); 2063 error = ENXIO; 2064 goto fail; 2065 } 2066 bcopy(mac, eaddr, ETHER_ADDR_LEN); 2067 break; 2068 default: 2069 dc_read_eeprom(sc, (caddr_t)&eaddr, DC_EE_NODEADDR, 3, 0); 2070 break; 2071 } 2072 2073 /* 2074 * A 21143 or clone chip was detected. Inform the world. 2075 */ 2076 printf("dc%d: Ethernet address: %6D\n", unit, eaddr, ":"); 2077 2078 sc->dc_unit = unit; 2079 bcopy(eaddr, &sc->arpcom.ac_enaddr, ETHER_ADDR_LEN); 2080 2081 sc->dc_ldata = contigmalloc(sizeof(struct dc_list_data), M_DEVBUF, 2082 M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0); 2083 2084 if (sc->dc_ldata == NULL) { 2085 printf("dc%d: no memory for list buffers!\n", unit); 2086 error = ENXIO; 2087 goto fail; 2088 } 2089 2090 bzero(sc->dc_ldata, sizeof(struct dc_list_data)); 2091 2092 ifp = &sc->arpcom.ac_if; 2093 ifp->if_softc = sc; 2094 ifp->if_unit = unit; 2095 ifp->if_name = "dc"; 2096 /* XXX: bleah, MTU gets overwritten in ether_ifattach() */ 2097 ifp->if_mtu = ETHERMTU; 2098 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 2099 ifp->if_ioctl = dc_ioctl; 2100 ifp->if_start = dc_start; 2101 ifp->if_watchdog = dc_watchdog; 2102 ifp->if_init = dc_init; 2103 ifp->if_baudrate = 10000000; 2104 ifp->if_snd.ifq_maxlen = DC_TX_LIST_CNT - 1; 2105 2106 /* 2107 * Do MII setup. If this is a 21143, check for a PHY on the 2108 * MII bus after applying any necessary fixups to twiddle the 2109 * GPIO bits. If we don't end up finding a PHY, restore the 2110 * old selection (SIA only or SIA/SYM) and attach the dcphy 2111 * driver instead. 2112 */ 2113 if (DC_IS_INTEL(sc)) { 2114 dc_apply_fixup(sc, IFM_AUTO); 2115 tmp = sc->dc_pmode; 2116 sc->dc_pmode = DC_PMODE_MII; 2117 } 2118 2119 error = mii_phy_probe(dev, &sc->dc_miibus, 2120 dc_ifmedia_upd, dc_ifmedia_sts); 2121 2122 if (error && DC_IS_INTEL(sc)) { 2123 sc->dc_pmode = tmp; 2124 if (sc->dc_pmode != DC_PMODE_SIA) 2125 sc->dc_pmode = DC_PMODE_SYM; 2126 sc->dc_flags |= DC_21143_NWAY; 2127 mii_phy_probe(dev, &sc->dc_miibus, 2128 dc_ifmedia_upd, dc_ifmedia_sts); 2129 /* 2130 * For non-MII cards, we need to have the 21143 2131 * drive the LEDs. Except there are some systems 2132 * like the NEC VersaPro NoteBook PC which have no 2133 * LEDs, and twiddling these bits has adverse effects 2134 * on them. (I.e. you suddenly can't get a link.) 2135 */ 2136 if (pci_read_config(dev, DC_PCI_CSID, 4) != 0x80281033) 2137 sc->dc_flags |= DC_TULIP_LEDS; 2138 error = 0; 2139 } 2140 2141 if (error) { 2142 printf("dc%d: MII without any PHY!\n", sc->dc_unit); 2143 goto fail; 2144 } 2145 2146 if (DC_IS_XIRCOM(sc)) { 2147 /* 2148 * setup General Purpose Port mode and data so the tulip 2149 * can talk to the MII. 2150 */ 2151 CSR_WRITE_4(sc, DC_SIAGP, DC_SIAGP_WRITE_EN | DC_SIAGP_INT1_EN | 2152 DC_SIAGP_MD_GP2_OUTPUT | DC_SIAGP_MD_GP0_OUTPUT); 2153 DELAY(10); 2154 CSR_WRITE_4(sc, DC_SIAGP, DC_SIAGP_INT1_EN | 2155 DC_SIAGP_MD_GP2_OUTPUT | DC_SIAGP_MD_GP0_OUTPUT); 2156 DELAY(10); 2157 } 2158 2159 if (DC_IS_ADMTEK(sc)) { 2160 /* 2161 * Set automatic TX underrun recovery for the ADMtek chips 2162 */ 2163 DC_SETBIT(sc, DC_AL_CR, DC_AL_CR_ATUR); 2164 } 2165 2166 /* 2167 * Tell the upper layer(s) we support long frames. 2168 */ 2169 ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header); 2170 ifp->if_capabilities |= IFCAP_VLAN_MTU; 2171 2172 callout_init(&sc->dc_stat_ch, IS_MPSAFE); 2173 2174 #ifdef SRM_MEDIA 2175 sc->dc_srm_media = 0; 2176 2177 /* Remember the SRM console media setting */ 2178 if (DC_IS_INTEL(sc)) { 2179 command = pci_read_config(dev, DC_PCI_CFDD, 4); 2180 command &= ~(DC_CFDD_SNOOZE_MODE | DC_CFDD_SLEEP_MODE); 2181 switch ((command >> 8) & 0xff) { 2182 case 3: 2183 sc->dc_srm_media = IFM_10_T; 2184 break; 2185 case 4: 2186 sc->dc_srm_media = IFM_10_T | IFM_FDX; 2187 break; 2188 case 5: 2189 sc->dc_srm_media = IFM_100_TX; 2190 break; 2191 case 6: 2192 sc->dc_srm_media = IFM_100_TX | IFM_FDX; 2193 break; 2194 } 2195 if (sc->dc_srm_media) 2196 sc->dc_srm_media |= IFM_ACTIVE | IFM_ETHER; 2197 } 2198 #endif 2199 2200 /* 2201 * Call MI attach routine. 2202 */ 2203 ether_ifattach(ifp, eaddr); 2204 2205 /* Hook interrupt last to avoid having to lock softc */ 2206 error = bus_setup_intr(dev, sc->dc_irq, INTR_TYPE_NET | 2207 (IS_MPSAFE ? INTR_MPSAFE : 0), 2208 dc_intr, sc, &sc->dc_intrhand); 2209 2210 if (error) { 2211 printf("dc%d: couldn't set up irq\n", unit); 2212 ether_ifdetach(ifp); 2213 goto fail; 2214 } 2215 2216 fail: 2217 if (error) 2218 dc_detach(dev); 2219 return (error); 2220 } 2221 2222 /* 2223 * Shutdown hardware and free up resources. This can be called any 2224 * time after the mutex has been initialized. It is called in both 2225 * the error case in attach and the normal detach case so it needs 2226 * to be careful about only freeing resources that have actually been 2227 * allocated. 2228 */ 2229 static int 2230 dc_detach(device_t dev) 2231 { 2232 struct dc_softc *sc; 2233 struct ifnet *ifp; 2234 struct dc_mediainfo *m; 2235 2236 sc = device_get_softc(dev); 2237 KASSERT(mtx_initialized(&sc->dc_mtx), ("dc mutex not initialized")); 2238 DC_LOCK(sc); 2239 2240 ifp = &sc->arpcom.ac_if; 2241 2242 /* These should only be active if attach succeeded */ 2243 if (device_is_attached(dev)) { 2244 dc_stop(sc); 2245 ether_ifdetach(ifp); 2246 } 2247 if (sc->dc_miibus) 2248 device_delete_child(dev, sc->dc_miibus); 2249 bus_generic_detach(dev); 2250 2251 if (sc->dc_intrhand) 2252 bus_teardown_intr(dev, sc->dc_irq, sc->dc_intrhand); 2253 if (sc->dc_irq) 2254 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->dc_irq); 2255 if (sc->dc_res) 2256 bus_release_resource(dev, DC_RES, DC_RID, sc->dc_res); 2257 2258 if (sc->dc_ldata) 2259 contigfree(sc->dc_ldata, sizeof(struct dc_list_data), M_DEVBUF); 2260 free(sc->dc_pnic_rx_buf, M_DEVBUF); 2261 2262 while (sc->dc_mi != NULL) { 2263 m = sc->dc_mi->dc_next; 2264 free(sc->dc_mi, M_DEVBUF); 2265 sc->dc_mi = m; 2266 } 2267 free(sc->dc_srom, M_DEVBUF); 2268 2269 DC_UNLOCK(sc); 2270 mtx_destroy(&sc->dc_mtx); 2271 2272 return (0); 2273 } 2274 2275 /* 2276 * Initialize the transmit descriptors. 2277 */ 2278 static int 2279 dc_list_tx_init(struct dc_softc *sc) 2280 { 2281 struct dc_chain_data *cd; 2282 struct dc_list_data *ld; 2283 int i, nexti; 2284 2285 cd = &sc->dc_cdata; 2286 ld = sc->dc_ldata; 2287 for (i = 0; i < DC_TX_LIST_CNT; i++) { 2288 nexti = (i == (DC_TX_LIST_CNT - 1)) ? 0 : i+1; 2289 ld->dc_tx_list[i].dc_next = vtophys(&ld->dc_tx_list[nexti]); 2290 cd->dc_tx_chain[i] = NULL; 2291 ld->dc_tx_list[i].dc_data = 0; 2292 ld->dc_tx_list[i].dc_ctl = 0; 2293 } 2294 2295 cd->dc_tx_prod = cd->dc_tx_cons = cd->dc_tx_cnt = 0; 2296 2297 return (0); 2298 } 2299 2300 2301 /* 2302 * Initialize the RX descriptors and allocate mbufs for them. Note that 2303 * we arrange the descriptors in a closed ring, so that the last descriptor 2304 * points back to the first. 2305 */ 2306 static int 2307 dc_list_rx_init(struct dc_softc *sc) 2308 { 2309 struct dc_chain_data *cd; 2310 struct dc_list_data *ld; 2311 int i, nexti; 2312 2313 cd = &sc->dc_cdata; 2314 ld = sc->dc_ldata; 2315 2316 for (i = 0; i < DC_RX_LIST_CNT; i++) { 2317 if (dc_newbuf(sc, i, NULL) == ENOBUFS) 2318 return (ENOBUFS); 2319 nexti = (i == (DC_RX_LIST_CNT - 1)) ? 0 : i+1; 2320 ld->dc_rx_list[i].dc_next = vtophys(&ld->dc_rx_list[nexti]); 2321 } 2322 2323 cd->dc_rx_prod = 0; 2324 2325 return (0); 2326 } 2327 2328 /* 2329 * Initialize an RX descriptor and attach an MBUF cluster. 2330 */ 2331 static int 2332 dc_newbuf(struct dc_softc *sc, int i, struct mbuf *m) 2333 { 2334 struct mbuf *m_new = NULL; 2335 struct dc_desc *c; 2336 2337 c = &sc->dc_ldata->dc_rx_list[i]; 2338 2339 if (m == NULL) { 2340 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 2341 if (m_new == NULL) 2342 return (ENOBUFS); 2343 2344 MCLGET(m_new, M_DONTWAIT); 2345 if (!(m_new->m_flags & M_EXT)) { 2346 m_freem(m_new); 2347 return (ENOBUFS); 2348 } 2349 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 2350 } else { 2351 m_new = m; 2352 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 2353 m_new->m_data = m_new->m_ext.ext_buf; 2354 } 2355 2356 m_adj(m_new, sizeof(u_int64_t)); 2357 2358 /* 2359 * If this is a PNIC chip, zero the buffer. This is part 2360 * of the workaround for the receive bug in the 82c168 and 2361 * 82c169 chips. 2362 */ 2363 if (sc->dc_flags & DC_PNIC_RX_BUG_WAR) 2364 bzero(mtod(m_new, char *), m_new->m_len); 2365 2366 sc->dc_cdata.dc_rx_chain[i] = m_new; 2367 c->dc_data = vtophys(mtod(m_new, caddr_t)); 2368 c->dc_ctl = DC_RXCTL_RLINK | DC_RXLEN; 2369 c->dc_status = DC_RXSTAT_OWN; 2370 2371 return (0); 2372 } 2373 2374 /* 2375 * Grrrrr. 2376 * The PNIC chip has a terrible bug in it that manifests itself during 2377 * periods of heavy activity. The exact mode of failure if difficult to 2378 * pinpoint: sometimes it only happens in promiscuous mode, sometimes it 2379 * will happen on slow machines. The bug is that sometimes instead of 2380 * uploading one complete frame during reception, it uploads what looks 2381 * like the entire contents of its FIFO memory. The frame we want is at 2382 * the end of the whole mess, but we never know exactly how much data has 2383 * been uploaded, so salvaging the frame is hard. 2384 * 2385 * There is only one way to do it reliably, and it's disgusting. 2386 * Here's what we know: 2387 * 2388 * - We know there will always be somewhere between one and three extra 2389 * descriptors uploaded. 2390 * 2391 * - We know the desired received frame will always be at the end of the 2392 * total data upload. 2393 * 2394 * - We know the size of the desired received frame because it will be 2395 * provided in the length field of the status word in the last descriptor. 2396 * 2397 * Here's what we do: 2398 * 2399 * - When we allocate buffers for the receive ring, we bzero() them. 2400 * This means that we know that the buffer contents should be all 2401 * zeros, except for data uploaded by the chip. 2402 * 2403 * - We also force the PNIC chip to upload frames that include the 2404 * ethernet CRC at the end. 2405 * 2406 * - We gather all of the bogus frame data into a single buffer. 2407 * 2408 * - We then position a pointer at the end of this buffer and scan 2409 * backwards until we encounter the first non-zero byte of data. 2410 * This is the end of the received frame. We know we will encounter 2411 * some data at the end of the frame because the CRC will always be 2412 * there, so even if the sender transmits a packet of all zeros, 2413 * we won't be fooled. 2414 * 2415 * - We know the size of the actual received frame, so we subtract 2416 * that value from the current pointer location. This brings us 2417 * to the start of the actual received packet. 2418 * 2419 * - We copy this into an mbuf and pass it on, along with the actual 2420 * frame length. 2421 * 2422 * The performance hit is tremendous, but it beats dropping frames all 2423 * the time. 2424 */ 2425 2426 #define DC_WHOLEFRAME (DC_RXSTAT_FIRSTFRAG | DC_RXSTAT_LASTFRAG) 2427 static void 2428 dc_pnic_rx_bug_war(struct dc_softc *sc, int idx) 2429 { 2430 struct dc_desc *cur_rx; 2431 struct dc_desc *c = NULL; 2432 struct mbuf *m = NULL; 2433 unsigned char *ptr; 2434 int i, total_len; 2435 u_int32_t rxstat = 0; 2436 2437 i = sc->dc_pnic_rx_bug_save; 2438 cur_rx = &sc->dc_ldata->dc_rx_list[idx]; 2439 ptr = sc->dc_pnic_rx_buf; 2440 bzero(ptr, DC_RXLEN * 5); 2441 2442 /* Copy all the bytes from the bogus buffers. */ 2443 while (1) { 2444 c = &sc->dc_ldata->dc_rx_list[i]; 2445 rxstat = c->dc_status; 2446 m = sc->dc_cdata.dc_rx_chain[i]; 2447 bcopy(mtod(m, char *), ptr, DC_RXLEN); 2448 ptr += DC_RXLEN; 2449 /* If this is the last buffer, break out. */ 2450 if (i == idx || rxstat & DC_RXSTAT_LASTFRAG) 2451 break; 2452 dc_newbuf(sc, i, m); 2453 DC_INC(i, DC_RX_LIST_CNT); 2454 } 2455 2456 /* Find the length of the actual receive frame. */ 2457 total_len = DC_RXBYTES(rxstat); 2458 2459 /* Scan backwards until we hit a non-zero byte. */ 2460 while (*ptr == 0x00) 2461 ptr--; 2462 2463 /* Round off. */ 2464 if ((uintptr_t)(ptr) & 0x3) 2465 ptr -= 1; 2466 2467 /* Now find the start of the frame. */ 2468 ptr -= total_len; 2469 if (ptr < sc->dc_pnic_rx_buf) 2470 ptr = sc->dc_pnic_rx_buf; 2471 2472 /* 2473 * Now copy the salvaged frame to the last mbuf and fake up 2474 * the status word to make it look like a successful 2475 * frame reception. 2476 */ 2477 dc_newbuf(sc, i, m); 2478 bcopy(ptr, mtod(m, char *), total_len); 2479 cur_rx->dc_status = rxstat | DC_RXSTAT_FIRSTFRAG; 2480 } 2481 2482 /* 2483 * This routine searches the RX ring for dirty descriptors in the 2484 * event that the rxeof routine falls out of sync with the chip's 2485 * current descriptor pointer. This may happen sometimes as a result 2486 * of a "no RX buffer available" condition that happens when the chip 2487 * consumes all of the RX buffers before the driver has a chance to 2488 * process the RX ring. This routine may need to be called more than 2489 * once to bring the driver back in sync with the chip, however we 2490 * should still be getting RX DONE interrupts to drive the search 2491 * for new packets in the RX ring, so we should catch up eventually. 2492 */ 2493 static int 2494 dc_rx_resync(struct dc_softc *sc) 2495 { 2496 struct dc_desc *cur_rx; 2497 int i, pos; 2498 2499 pos = sc->dc_cdata.dc_rx_prod; 2500 2501 for (i = 0; i < DC_RX_LIST_CNT; i++) { 2502 cur_rx = &sc->dc_ldata->dc_rx_list[pos]; 2503 if (!(cur_rx->dc_status & DC_RXSTAT_OWN)) 2504 break; 2505 DC_INC(pos, DC_RX_LIST_CNT); 2506 } 2507 2508 /* If the ring really is empty, then just return. */ 2509 if (i == DC_RX_LIST_CNT) 2510 return (0); 2511 2512 /* We've fallen behing the chip: catch it. */ 2513 sc->dc_cdata.dc_rx_prod = pos; 2514 2515 return (EAGAIN); 2516 } 2517 2518 /* 2519 * A frame has been uploaded: pass the resulting mbuf chain up to 2520 * the higher level protocols. 2521 */ 2522 static void 2523 dc_rxeof(struct dc_softc *sc) 2524 { 2525 struct mbuf *m; 2526 struct ifnet *ifp; 2527 struct dc_desc *cur_rx; 2528 int i, total_len = 0; 2529 u_int32_t rxstat; 2530 2531 ifp = &sc->arpcom.ac_if; 2532 i = sc->dc_cdata.dc_rx_prod; 2533 2534 while (!(sc->dc_ldata->dc_rx_list[i].dc_status & DC_RXSTAT_OWN)) { 2535 #ifdef DEVICE_POLLING 2536 if (ifp->if_flags & IFF_POLLING) { 2537 if (sc->rxcycles <= 0) 2538 break; 2539 sc->rxcycles--; 2540 } 2541 #endif 2542 cur_rx = &sc->dc_ldata->dc_rx_list[i]; 2543 rxstat = cur_rx->dc_status; 2544 m = sc->dc_cdata.dc_rx_chain[i]; 2545 total_len = DC_RXBYTES(rxstat); 2546 2547 if (sc->dc_flags & DC_PNIC_RX_BUG_WAR) { 2548 if ((rxstat & DC_WHOLEFRAME) != DC_WHOLEFRAME) { 2549 if (rxstat & DC_RXSTAT_FIRSTFRAG) 2550 sc->dc_pnic_rx_bug_save = i; 2551 if ((rxstat & DC_RXSTAT_LASTFRAG) == 0) { 2552 DC_INC(i, DC_RX_LIST_CNT); 2553 continue; 2554 } 2555 dc_pnic_rx_bug_war(sc, i); 2556 rxstat = cur_rx->dc_status; 2557 total_len = DC_RXBYTES(rxstat); 2558 } 2559 } 2560 2561 sc->dc_cdata.dc_rx_chain[i] = NULL; 2562 2563 /* 2564 * If an error occurs, update stats, clear the 2565 * status word and leave the mbuf cluster in place: 2566 * it should simply get re-used next time this descriptor 2567 * comes up in the ring. However, don't report long 2568 * frames as errors since they could be vlans. 2569 */ 2570 if ((rxstat & DC_RXSTAT_RXERR)) { 2571 if (!(rxstat & DC_RXSTAT_GIANT) || 2572 (rxstat & (DC_RXSTAT_CRCERR | DC_RXSTAT_DRIBBLE | 2573 DC_RXSTAT_MIIERE | DC_RXSTAT_COLLSEEN | 2574 DC_RXSTAT_RUNT | DC_RXSTAT_DE))) { 2575 ifp->if_ierrors++; 2576 if (rxstat & DC_RXSTAT_COLLSEEN) 2577 ifp->if_collisions++; 2578 dc_newbuf(sc, i, m); 2579 if (rxstat & DC_RXSTAT_CRCERR) { 2580 DC_INC(i, DC_RX_LIST_CNT); 2581 continue; 2582 } else { 2583 dc_init(sc); 2584 return; 2585 } 2586 } 2587 } 2588 2589 /* No errors; receive the packet. */ 2590 total_len -= ETHER_CRC_LEN; 2591 #ifdef __i386__ 2592 /* 2593 * On the x86 we do not have alignment problems, so try to 2594 * allocate a new buffer for the receive ring, and pass up 2595 * the one where the packet is already, saving the expensive 2596 * copy done in m_devget(). 2597 * If we are on an architecture with alignment problems, or 2598 * if the allocation fails, then use m_devget and leave the 2599 * existing buffer in the receive ring. 2600 */ 2601 if (dc_quick && dc_newbuf(sc, i, NULL) == 0) { 2602 m->m_pkthdr.rcvif = ifp; 2603 m->m_pkthdr.len = m->m_len = total_len; 2604 DC_INC(i, DC_RX_LIST_CNT); 2605 } else 2606 #endif 2607 { 2608 struct mbuf *m0; 2609 2610 m0 = m_devget(mtod(m, char *), total_len, 2611 ETHER_ALIGN, ifp, NULL); 2612 dc_newbuf(sc, i, m); 2613 DC_INC(i, DC_RX_LIST_CNT); 2614 if (m0 == NULL) { 2615 ifp->if_ierrors++; 2616 continue; 2617 } 2618 m = m0; 2619 } 2620 2621 ifp->if_ipackets++; 2622 (*ifp->if_input)(ifp, m); 2623 } 2624 2625 sc->dc_cdata.dc_rx_prod = i; 2626 } 2627 2628 /* 2629 * A frame was downloaded to the chip. It's safe for us to clean up 2630 * the list buffers. 2631 */ 2632 2633 static void 2634 dc_txeof(struct dc_softc *sc) 2635 { 2636 struct dc_desc *cur_tx = NULL; 2637 struct ifnet *ifp; 2638 int idx; 2639 u_int32_t txstat; 2640 2641 ifp = &sc->arpcom.ac_if; 2642 2643 /* 2644 * Go through our tx list and free mbufs for those 2645 * frames that have been transmitted. 2646 */ 2647 idx = sc->dc_cdata.dc_tx_cons; 2648 while (idx != sc->dc_cdata.dc_tx_prod) { 2649 2650 cur_tx = &sc->dc_ldata->dc_tx_list[idx]; 2651 txstat = cur_tx->dc_status; 2652 2653 if (txstat & DC_TXSTAT_OWN) 2654 break; 2655 2656 if (!(cur_tx->dc_ctl & DC_TXCTL_LASTFRAG) || 2657 cur_tx->dc_ctl & DC_TXCTL_SETUP) { 2658 if (cur_tx->dc_ctl & DC_TXCTL_SETUP) { 2659 /* 2660 * Yes, the PNIC is so brain damaged 2661 * that it will sometimes generate a TX 2662 * underrun error while DMAing the RX 2663 * filter setup frame. If we detect this, 2664 * we have to send the setup frame again, 2665 * or else the filter won't be programmed 2666 * correctly. 2667 */ 2668 if (DC_IS_PNIC(sc)) { 2669 if (txstat & DC_TXSTAT_ERRSUM) 2670 dc_setfilt(sc); 2671 } 2672 sc->dc_cdata.dc_tx_chain[idx] = NULL; 2673 } 2674 sc->dc_cdata.dc_tx_cnt--; 2675 DC_INC(idx, DC_TX_LIST_CNT); 2676 continue; 2677 } 2678 2679 if (DC_IS_XIRCOM(sc) || DC_IS_CONEXANT(sc)) { 2680 /* 2681 * XXX: Why does my Xircom taunt me so? 2682 * For some reason it likes setting the CARRLOST flag 2683 * even when the carrier is there. wtf?!? 2684 * Who knows, but Conexant chips have the 2685 * same problem. Maybe they took lessons 2686 * from Xircom. 2687 */ 2688 if (/*sc->dc_type == DC_TYPE_21143 &&*/ 2689 sc->dc_pmode == DC_PMODE_MII && 2690 ((txstat & 0xFFFF) & ~(DC_TXSTAT_ERRSUM | 2691 DC_TXSTAT_NOCARRIER))) 2692 txstat &= ~DC_TXSTAT_ERRSUM; 2693 } else { 2694 if (/*sc->dc_type == DC_TYPE_21143 &&*/ 2695 sc->dc_pmode == DC_PMODE_MII && 2696 ((txstat & 0xFFFF) & ~(DC_TXSTAT_ERRSUM | 2697 DC_TXSTAT_NOCARRIER | DC_TXSTAT_CARRLOST))) 2698 txstat &= ~DC_TXSTAT_ERRSUM; 2699 } 2700 2701 if (txstat & DC_TXSTAT_ERRSUM) { 2702 ifp->if_oerrors++; 2703 if (txstat & DC_TXSTAT_EXCESSCOLL) 2704 ifp->if_collisions++; 2705 if (txstat & DC_TXSTAT_LATECOLL) 2706 ifp->if_collisions++; 2707 if (!(txstat & DC_TXSTAT_UNDERRUN)) { 2708 dc_init(sc); 2709 return; 2710 } 2711 } 2712 2713 ifp->if_collisions += (txstat & DC_TXSTAT_COLLCNT) >> 3; 2714 2715 ifp->if_opackets++; 2716 if (sc->dc_cdata.dc_tx_chain[idx] != NULL) { 2717 m_freem(sc->dc_cdata.dc_tx_chain[idx]); 2718 sc->dc_cdata.dc_tx_chain[idx] = NULL; 2719 } 2720 2721 sc->dc_cdata.dc_tx_cnt--; 2722 DC_INC(idx, DC_TX_LIST_CNT); 2723 } 2724 2725 if (idx != sc->dc_cdata.dc_tx_cons) { 2726 /* Some buffers have been freed. */ 2727 sc->dc_cdata.dc_tx_cons = idx; 2728 ifp->if_flags &= ~IFF_OACTIVE; 2729 } 2730 ifp->if_timer = (sc->dc_cdata.dc_tx_cnt == 0) ? 0 : 5; 2731 } 2732 2733 static void 2734 dc_tick(void *xsc) 2735 { 2736 struct dc_softc *sc; 2737 struct mii_data *mii; 2738 struct ifnet *ifp; 2739 u_int32_t r; 2740 2741 sc = xsc; 2742 DC_LOCK(sc); 2743 ifp = &sc->arpcom.ac_if; 2744 mii = device_get_softc(sc->dc_miibus); 2745 2746 if (sc->dc_flags & DC_REDUCED_MII_POLL) { 2747 if (sc->dc_flags & DC_21143_NWAY) { 2748 r = CSR_READ_4(sc, DC_10BTSTAT); 2749 if (IFM_SUBTYPE(mii->mii_media_active) == 2750 IFM_100_TX && (r & DC_TSTAT_LS100)) { 2751 sc->dc_link = 0; 2752 mii_mediachg(mii); 2753 } 2754 if (IFM_SUBTYPE(mii->mii_media_active) == 2755 IFM_10_T && (r & DC_TSTAT_LS10)) { 2756 sc->dc_link = 0; 2757 mii_mediachg(mii); 2758 } 2759 if (sc->dc_link == 0) 2760 mii_tick(mii); 2761 } else { 2762 r = CSR_READ_4(sc, DC_ISR); 2763 if ((r & DC_ISR_RX_STATE) == DC_RXSTATE_WAIT && 2764 sc->dc_cdata.dc_tx_cnt == 0) { 2765 mii_tick(mii); 2766 if (!(mii->mii_media_status & IFM_ACTIVE)) 2767 sc->dc_link = 0; 2768 } 2769 } 2770 } else 2771 mii_tick(mii); 2772 2773 /* 2774 * When the init routine completes, we expect to be able to send 2775 * packets right away, and in fact the network code will send a 2776 * gratuitous ARP the moment the init routine marks the interface 2777 * as running. However, even though the MAC may have been initialized, 2778 * there may be a delay of a few seconds before the PHY completes 2779 * autonegotiation and the link is brought up. Any transmissions 2780 * made during that delay will be lost. Dealing with this is tricky: 2781 * we can't just pause in the init routine while waiting for the 2782 * PHY to come ready since that would bring the whole system to 2783 * a screeching halt for several seconds. 2784 * 2785 * What we do here is prevent the TX start routine from sending 2786 * any packets until a link has been established. After the 2787 * interface has been initialized, the tick routine will poll 2788 * the state of the PHY until the IFM_ACTIVE flag is set. Until 2789 * that time, packets will stay in the send queue, and once the 2790 * link comes up, they will be flushed out to the wire. 2791 */ 2792 if (!sc->dc_link && mii->mii_media_status & IFM_ACTIVE && 2793 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) { 2794 sc->dc_link++; 2795 if (ifp->if_snd.ifq_head != NULL) 2796 dc_start(ifp); 2797 } 2798 2799 if (sc->dc_flags & DC_21143_NWAY && !sc->dc_link) 2800 callout_reset(&sc->dc_stat_ch, hz/10, dc_tick, sc); 2801 else 2802 callout_reset(&sc->dc_stat_ch, hz, dc_tick, sc); 2803 2804 DC_UNLOCK(sc); 2805 } 2806 2807 /* 2808 * A transmit underrun has occurred. Back off the transmit threshold, 2809 * or switch to store and forward mode if we have to. 2810 */ 2811 static void 2812 dc_tx_underrun(struct dc_softc *sc) 2813 { 2814 u_int32_t isr; 2815 int i; 2816 2817 if (DC_IS_DAVICOM(sc)) 2818 dc_init(sc); 2819 2820 if (DC_IS_INTEL(sc)) { 2821 /* 2822 * The real 21143 requires that the transmitter be idle 2823 * in order to change the transmit threshold or store 2824 * and forward state. 2825 */ 2826 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_TX_ON); 2827 2828 for (i = 0; i < DC_TIMEOUT; i++) { 2829 isr = CSR_READ_4(sc, DC_ISR); 2830 if (isr & DC_ISR_TX_IDLE) 2831 break; 2832 DELAY(10); 2833 } 2834 if (i == DC_TIMEOUT) { 2835 printf("dc%d: failed to force tx to idle state\n", 2836 sc->dc_unit); 2837 dc_init(sc); 2838 } 2839 } 2840 2841 printf("dc%d: TX underrun -- ", sc->dc_unit); 2842 sc->dc_txthresh += DC_TXTHRESH_INC; 2843 if (sc->dc_txthresh > DC_TXTHRESH_MAX) { 2844 printf("using store and forward mode\n"); 2845 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_STORENFWD); 2846 } else { 2847 printf("increasing TX threshold\n"); 2848 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_TX_THRESH); 2849 DC_SETBIT(sc, DC_NETCFG, sc->dc_txthresh); 2850 } 2851 2852 if (DC_IS_INTEL(sc)) 2853 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_TX_ON); 2854 } 2855 2856 #ifdef DEVICE_POLLING 2857 static poll_handler_t dc_poll; 2858 2859 static void 2860 dc_poll(struct ifnet *ifp, enum poll_cmd cmd, int count) 2861 { 2862 struct dc_softc *sc = ifp->if_softc; 2863 2864 if (cmd == POLL_DEREGISTER) { /* final call, enable interrupts */ 2865 /* Re-enable interrupts. */ 2866 CSR_WRITE_4(sc, DC_IMR, DC_INTRS); 2867 return; 2868 } 2869 sc->rxcycles = count; 2870 dc_rxeof(sc); 2871 dc_txeof(sc); 2872 if (ifp->if_snd.ifq_head != NULL && !(ifp->if_flags & IFF_OACTIVE)) 2873 dc_start(ifp); 2874 2875 if (cmd == POLL_AND_CHECK_STATUS) { /* also check status register */ 2876 u_int32_t status; 2877 2878 status = CSR_READ_4(sc, DC_ISR); 2879 status &= (DC_ISR_RX_WATDOGTIMEO | DC_ISR_RX_NOBUF | 2880 DC_ISR_TX_NOBUF | DC_ISR_TX_IDLE | DC_ISR_TX_UNDERRUN | 2881 DC_ISR_BUS_ERR); 2882 if (!status) 2883 return; 2884 /* ack what we have */ 2885 CSR_WRITE_4(sc, DC_ISR, status); 2886 2887 if (status & (DC_ISR_RX_WATDOGTIMEO | DC_ISR_RX_NOBUF)) { 2888 u_int32_t r = CSR_READ_4(sc, DC_FRAMESDISCARDED); 2889 ifp->if_ierrors += (r & 0xffff) + ((r >> 17) & 0x7ff); 2890 2891 if (dc_rx_resync(sc)) 2892 dc_rxeof(sc); 2893 } 2894 /* restart transmit unit if necessary */ 2895 if (status & DC_ISR_TX_IDLE && sc->dc_cdata.dc_tx_cnt) 2896 CSR_WRITE_4(sc, DC_TXSTART, 0xFFFFFFFF); 2897 2898 if (status & DC_ISR_TX_UNDERRUN) 2899 dc_tx_underrun(sc); 2900 2901 if (status & DC_ISR_BUS_ERR) { 2902 printf("dc_poll: dc%d bus error\n", sc->dc_unit); 2903 dc_reset(sc); 2904 dc_init(sc); 2905 } 2906 } 2907 } 2908 #endif /* DEVICE_POLLING */ 2909 2910 static void 2911 dc_intr(void *arg) 2912 { 2913 struct dc_softc *sc; 2914 struct ifnet *ifp; 2915 u_int32_t status; 2916 2917 sc = arg; 2918 2919 if (sc->suspended) 2920 return; 2921 2922 if ((CSR_READ_4(sc, DC_ISR) & DC_INTRS) == 0) 2923 return; 2924 2925 DC_LOCK(sc); 2926 ifp = &sc->arpcom.ac_if; 2927 #ifdef DEVICE_POLLING 2928 if (ifp->if_flags & IFF_POLLING) 2929 goto done; 2930 if (ether_poll_register(dc_poll, ifp)) { /* ok, disable interrupts */ 2931 CSR_WRITE_4(sc, DC_IMR, 0x00000000); 2932 goto done; 2933 } 2934 #endif 2935 2936 /* Suppress unwanted interrupts */ 2937 if (!(ifp->if_flags & IFF_UP)) { 2938 if (CSR_READ_4(sc, DC_ISR) & DC_INTRS) 2939 dc_stop(sc); 2940 DC_UNLOCK(sc); 2941 return; 2942 } 2943 2944 /* Disable interrupts. */ 2945 CSR_WRITE_4(sc, DC_IMR, 0x00000000); 2946 2947 while (((status = CSR_READ_4(sc, DC_ISR)) & DC_INTRS) 2948 && status != 0xFFFFFFFF) { 2949 2950 CSR_WRITE_4(sc, DC_ISR, status); 2951 2952 if (status & DC_ISR_RX_OK) { 2953 int curpkts; 2954 curpkts = ifp->if_ipackets; 2955 dc_rxeof(sc); 2956 if (curpkts == ifp->if_ipackets) { 2957 while (dc_rx_resync(sc)) 2958 dc_rxeof(sc); 2959 } 2960 } 2961 2962 if (status & (DC_ISR_TX_OK | DC_ISR_TX_NOBUF)) 2963 dc_txeof(sc); 2964 2965 if (status & DC_ISR_TX_IDLE) { 2966 dc_txeof(sc); 2967 if (sc->dc_cdata.dc_tx_cnt) { 2968 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_TX_ON); 2969 CSR_WRITE_4(sc, DC_TXSTART, 0xFFFFFFFF); 2970 } 2971 } 2972 2973 if (status & DC_ISR_TX_UNDERRUN) 2974 dc_tx_underrun(sc); 2975 2976 if ((status & DC_ISR_RX_WATDOGTIMEO) 2977 || (status & DC_ISR_RX_NOBUF)) { 2978 int curpkts; 2979 curpkts = ifp->if_ipackets; 2980 dc_rxeof(sc); 2981 if (curpkts == ifp->if_ipackets) { 2982 while (dc_rx_resync(sc)) 2983 dc_rxeof(sc); 2984 } 2985 } 2986 2987 if (status & DC_ISR_BUS_ERR) { 2988 dc_reset(sc); 2989 dc_init(sc); 2990 } 2991 } 2992 2993 /* Re-enable interrupts. */ 2994 CSR_WRITE_4(sc, DC_IMR, DC_INTRS); 2995 2996 if (ifp->if_snd.ifq_head != NULL) 2997 dc_start(ifp); 2998 2999 #ifdef DEVICE_POLLING 3000 done: 3001 #endif 3002 3003 DC_UNLOCK(sc); 3004 } 3005 3006 /* 3007 * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data 3008 * pointers to the fragment pointers. 3009 */ 3010 static int 3011 dc_encap(struct dc_softc *sc, struct mbuf *m_head, u_int32_t *txidx) 3012 { 3013 struct dc_desc *f = NULL; 3014 struct mbuf *m; 3015 int frag, cur, cnt = 0, chainlen = 0; 3016 3017 /* 3018 * If there's no way we can send any packets, return now. 3019 */ 3020 if (DC_TX_LIST_CNT - sc->dc_cdata.dc_tx_cnt < 6) 3021 return (ENOBUFS); 3022 3023 /* 3024 * Count the number of frags in this chain to see if 3025 * we need to m_defrag. Since the descriptor list is shared 3026 * by all packets, we'll m_defrag long chains so that they 3027 * do not use up the entire list, even if they would fit. 3028 */ 3029 3030 for (m = m_head; m != NULL; m = m->m_next) 3031 chainlen++; 3032 3033 if ((chainlen > DC_TX_LIST_CNT / 4) || 3034 ((DC_TX_LIST_CNT - (chainlen + sc->dc_cdata.dc_tx_cnt)) < 6)) { 3035 m = m_defrag(m_head, M_DONTWAIT); 3036 if (m == NULL) 3037 return (ENOBUFS); 3038 m_head = m; 3039 } 3040 3041 /* 3042 * Start packing the mbufs in this chain into 3043 * the fragment pointers. Stop when we run out 3044 * of fragments or hit the end of the mbuf chain. 3045 */ 3046 m = m_head; 3047 cur = frag = *txidx; 3048 3049 for (m = m_head; m != NULL; m = m->m_next) { 3050 if (m->m_len != 0) { 3051 if (sc->dc_flags & DC_TX_ADMTEK_WAR) { 3052 if (*txidx != sc->dc_cdata.dc_tx_prod && 3053 frag == (DC_TX_LIST_CNT - 1)) 3054 return (ENOBUFS); 3055 } 3056 if ((DC_TX_LIST_CNT - 3057 (sc->dc_cdata.dc_tx_cnt + cnt)) < 5) 3058 return (ENOBUFS); 3059 3060 f = &sc->dc_ldata->dc_tx_list[frag]; 3061 f->dc_ctl = DC_TXCTL_TLINK | m->m_len; 3062 if (cnt == 0) { 3063 f->dc_status = 0; 3064 f->dc_ctl |= DC_TXCTL_FIRSTFRAG; 3065 } else 3066 f->dc_status = DC_TXSTAT_OWN; 3067 f->dc_data = vtophys(mtod(m, vm_offset_t)); 3068 cur = frag; 3069 DC_INC(frag, DC_TX_LIST_CNT); 3070 cnt++; 3071 } 3072 } 3073 3074 if (m != NULL) 3075 return (ENOBUFS); 3076 3077 sc->dc_cdata.dc_tx_cnt += cnt; 3078 sc->dc_cdata.dc_tx_chain[cur] = m_head; 3079 sc->dc_ldata->dc_tx_list[cur].dc_ctl |= DC_TXCTL_LASTFRAG; 3080 if (sc->dc_flags & DC_TX_INTR_FIRSTFRAG) 3081 sc->dc_ldata->dc_tx_list[*txidx].dc_ctl |= DC_TXCTL_FINT; 3082 if (sc->dc_flags & DC_TX_INTR_ALWAYS) 3083 sc->dc_ldata->dc_tx_list[cur].dc_ctl |= DC_TXCTL_FINT; 3084 if (sc->dc_flags & DC_TX_USE_TX_INTR && sc->dc_cdata.dc_tx_cnt > 64) 3085 sc->dc_ldata->dc_tx_list[cur].dc_ctl |= DC_TXCTL_FINT; 3086 sc->dc_ldata->dc_tx_list[*txidx].dc_status = DC_TXSTAT_OWN; 3087 *txidx = frag; 3088 3089 return (0); 3090 } 3091 3092 /* 3093 * Main transmit routine. To avoid having to do mbuf copies, we put pointers 3094 * to the mbuf data regions directly in the transmit lists. We also save a 3095 * copy of the pointers since the transmit list fragment pointers are 3096 * physical addresses. 3097 */ 3098 3099 static void 3100 dc_start(struct ifnet *ifp) 3101 { 3102 struct dc_softc *sc; 3103 struct mbuf *m_head = NULL, *m; 3104 int idx; 3105 3106 sc = ifp->if_softc; 3107 3108 DC_LOCK(sc); 3109 3110 if (!sc->dc_link && ifp->if_snd.ifq_len < 10) { 3111 DC_UNLOCK(sc); 3112 return; 3113 } 3114 3115 if (ifp->if_flags & IFF_OACTIVE) { 3116 DC_UNLOCK(sc); 3117 return; 3118 } 3119 3120 idx = sc->dc_cdata.dc_tx_prod; 3121 3122 while (sc->dc_cdata.dc_tx_chain[idx] == NULL) { 3123 IF_DEQUEUE(&ifp->if_snd, m_head); 3124 if (m_head == NULL) 3125 break; 3126 3127 if (sc->dc_flags & DC_TX_COALESCE && 3128 (m_head->m_next != NULL || 3129 sc->dc_flags & DC_TX_ALIGN)) { 3130 m = m_defrag(m_head, M_DONTWAIT); 3131 if (m == NULL) { 3132 IF_PREPEND(&ifp->if_snd, m_head); 3133 ifp->if_flags |= IFF_OACTIVE; 3134 break; 3135 } else { 3136 m_head = m; 3137 } 3138 } 3139 3140 if (dc_encap(sc, m_head, &idx)) { 3141 IF_PREPEND(&ifp->if_snd, m_head); 3142 ifp->if_flags |= IFF_OACTIVE; 3143 break; 3144 } 3145 3146 /* 3147 * If there's a BPF listener, bounce a copy of this frame 3148 * to him. 3149 */ 3150 BPF_MTAP(ifp, m_head); 3151 3152 if (sc->dc_flags & DC_TX_ONE) { 3153 ifp->if_flags |= IFF_OACTIVE; 3154 break; 3155 } 3156 } 3157 3158 /* Transmit */ 3159 sc->dc_cdata.dc_tx_prod = idx; 3160 if (!(sc->dc_flags & DC_TX_POLL)) 3161 CSR_WRITE_4(sc, DC_TXSTART, 0xFFFFFFFF); 3162 3163 /* 3164 * Set a timeout in case the chip goes out to lunch. 3165 */ 3166 ifp->if_timer = 5; 3167 3168 DC_UNLOCK(sc); 3169 } 3170 3171 static void 3172 dc_init(void *xsc) 3173 { 3174 struct dc_softc *sc = xsc; 3175 struct ifnet *ifp = &sc->arpcom.ac_if; 3176 struct mii_data *mii; 3177 3178 DC_LOCK(sc); 3179 3180 mii = device_get_softc(sc->dc_miibus); 3181 3182 /* 3183 * Cancel pending I/O and free all RX/TX buffers. 3184 */ 3185 dc_stop(sc); 3186 dc_reset(sc); 3187 3188 /* 3189 * Set cache alignment and burst length. 3190 */ 3191 if (DC_IS_ASIX(sc) || DC_IS_DAVICOM(sc)) 3192 CSR_WRITE_4(sc, DC_BUSCTL, 0); 3193 else 3194 CSR_WRITE_4(sc, DC_BUSCTL, DC_BUSCTL_MRME | DC_BUSCTL_MRLE); 3195 /* 3196 * Evenly share the bus between receive and transmit process. 3197 */ 3198 if (DC_IS_INTEL(sc)) 3199 DC_SETBIT(sc, DC_BUSCTL, DC_BUSCTL_ARBITRATION); 3200 if (DC_IS_DAVICOM(sc) || DC_IS_INTEL(sc)) { 3201 DC_SETBIT(sc, DC_BUSCTL, DC_BURSTLEN_USECA); 3202 } else { 3203 DC_SETBIT(sc, DC_BUSCTL, DC_BURSTLEN_16LONG); 3204 } 3205 if (sc->dc_flags & DC_TX_POLL) 3206 DC_SETBIT(sc, DC_BUSCTL, DC_TXPOLL_1); 3207 switch(sc->dc_cachesize) { 3208 case 32: 3209 DC_SETBIT(sc, DC_BUSCTL, DC_CACHEALIGN_32LONG); 3210 break; 3211 case 16: 3212 DC_SETBIT(sc, DC_BUSCTL, DC_CACHEALIGN_16LONG); 3213 break; 3214 case 8: 3215 DC_SETBIT(sc, DC_BUSCTL, DC_CACHEALIGN_8LONG); 3216 break; 3217 case 0: 3218 default: 3219 DC_SETBIT(sc, DC_BUSCTL, DC_CACHEALIGN_NONE); 3220 break; 3221 } 3222 3223 if (sc->dc_flags & DC_TX_STORENFWD) 3224 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_STORENFWD); 3225 else { 3226 if (sc->dc_txthresh > DC_TXTHRESH_MAX) { 3227 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_STORENFWD); 3228 } else { 3229 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_STORENFWD); 3230 DC_SETBIT(sc, DC_NETCFG, sc->dc_txthresh); 3231 } 3232 } 3233 3234 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_NO_RXCRC); 3235 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_TX_BACKOFF); 3236 3237 if (DC_IS_MACRONIX(sc) || DC_IS_PNICII(sc)) { 3238 /* 3239 * The app notes for the 98713 and 98715A say that 3240 * in order to have the chips operate properly, a magic 3241 * number must be written to CSR16. Macronix does not 3242 * document the meaning of these bits so there's no way 3243 * to know exactly what they do. The 98713 has a magic 3244 * number all its own; the rest all use a different one. 3245 */ 3246 DC_CLRBIT(sc, DC_MX_MAGICPACKET, 0xFFFF0000); 3247 if (sc->dc_type == DC_TYPE_98713) 3248 DC_SETBIT(sc, DC_MX_MAGICPACKET, DC_MX_MAGIC_98713); 3249 else 3250 DC_SETBIT(sc, DC_MX_MAGICPACKET, DC_MX_MAGIC_98715); 3251 } 3252 3253 if (DC_IS_XIRCOM(sc)) { 3254 /* 3255 * setup General Purpose Port mode and data so the tulip 3256 * can talk to the MII. 3257 */ 3258 CSR_WRITE_4(sc, DC_SIAGP, DC_SIAGP_WRITE_EN | DC_SIAGP_INT1_EN | 3259 DC_SIAGP_MD_GP2_OUTPUT | DC_SIAGP_MD_GP0_OUTPUT); 3260 DELAY(10); 3261 CSR_WRITE_4(sc, DC_SIAGP, DC_SIAGP_INT1_EN | 3262 DC_SIAGP_MD_GP2_OUTPUT | DC_SIAGP_MD_GP0_OUTPUT); 3263 DELAY(10); 3264 } 3265 3266 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_TX_THRESH); 3267 DC_SETBIT(sc, DC_NETCFG, DC_TXTHRESH_MIN); 3268 3269 /* Init circular RX list. */ 3270 if (dc_list_rx_init(sc) == ENOBUFS) { 3271 printf("dc%d: initialization failed: no " 3272 "memory for rx buffers\n", sc->dc_unit); 3273 dc_stop(sc); 3274 DC_UNLOCK(sc); 3275 return; 3276 } 3277 3278 /* 3279 * Init tx descriptors. 3280 */ 3281 dc_list_tx_init(sc); 3282 3283 /* 3284 * Load the address of the RX list. 3285 */ 3286 CSR_WRITE_4(sc, DC_RXADDR, vtophys(&sc->dc_ldata->dc_rx_list[0])); 3287 CSR_WRITE_4(sc, DC_TXADDR, vtophys(&sc->dc_ldata->dc_tx_list[0])); 3288 3289 /* 3290 * Enable interrupts. 3291 */ 3292 #ifdef DEVICE_POLLING 3293 /* 3294 * ... but only if we are not polling, and make sure they are off in 3295 * the case of polling. Some cards (e.g. fxp) turn interrupts on 3296 * after a reset. 3297 */ 3298 if (ifp->if_flags & IFF_POLLING) 3299 CSR_WRITE_4(sc, DC_IMR, 0x00000000); 3300 else 3301 #endif 3302 CSR_WRITE_4(sc, DC_IMR, DC_INTRS); 3303 CSR_WRITE_4(sc, DC_ISR, 0xFFFFFFFF); 3304 3305 /* Enable transmitter. */ 3306 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_TX_ON); 3307 3308 /* 3309 * If this is an Intel 21143 and we're not using the 3310 * MII port, program the LED control pins so we get 3311 * link and activity indications. 3312 */ 3313 if (sc->dc_flags & DC_TULIP_LEDS) { 3314 CSR_WRITE_4(sc, DC_WATCHDOG, 3315 DC_WDOG_CTLWREN | DC_WDOG_LINK | DC_WDOG_ACTIVITY); 3316 CSR_WRITE_4(sc, DC_WATCHDOG, 0); 3317 } 3318 3319 /* 3320 * Load the RX/multicast filter. We do this sort of late 3321 * because the filter programming scheme on the 21143 and 3322 * some clones requires DMAing a setup frame via the TX 3323 * engine, and we need the transmitter enabled for that. 3324 */ 3325 dc_setfilt(sc); 3326 3327 /* Enable receiver. */ 3328 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_ON); 3329 CSR_WRITE_4(sc, DC_RXSTART, 0xFFFFFFFF); 3330 3331 mii_mediachg(mii); 3332 dc_setcfg(sc, sc->dc_if_media); 3333 3334 ifp->if_flags |= IFF_RUNNING; 3335 ifp->if_flags &= ~IFF_OACTIVE; 3336 3337 /* Don't start the ticker if this is a homePNA link. */ 3338 if (IFM_SUBTYPE(mii->mii_media.ifm_media) == IFM_HPNA_1) 3339 sc->dc_link = 1; 3340 else { 3341 if (sc->dc_flags & DC_21143_NWAY) 3342 callout_reset(&sc->dc_stat_ch, hz/10, dc_tick, sc); 3343 else 3344 callout_reset(&sc->dc_stat_ch, hz, dc_tick, sc); 3345 } 3346 3347 #ifdef SRM_MEDIA 3348 if(sc->dc_srm_media) { 3349 struct ifreq ifr; 3350 3351 ifr.ifr_media = sc->dc_srm_media; 3352 ifmedia_ioctl(ifp, &ifr, &mii->mii_media, SIOCSIFMEDIA); 3353 sc->dc_srm_media = 0; 3354 } 3355 #endif 3356 DC_UNLOCK(sc); 3357 } 3358 3359 /* 3360 * Set media options. 3361 */ 3362 static int 3363 dc_ifmedia_upd(struct ifnet *ifp) 3364 { 3365 struct dc_softc *sc; 3366 struct mii_data *mii; 3367 struct ifmedia *ifm; 3368 3369 sc = ifp->if_softc; 3370 mii = device_get_softc(sc->dc_miibus); 3371 mii_mediachg(mii); 3372 ifm = &mii->mii_media; 3373 3374 if (DC_IS_DAVICOM(sc) && 3375 IFM_SUBTYPE(ifm->ifm_media) == IFM_HPNA_1) 3376 dc_setcfg(sc, ifm->ifm_media); 3377 else 3378 sc->dc_link = 0; 3379 3380 return (0); 3381 } 3382 3383 /* 3384 * Report current media status. 3385 */ 3386 static void 3387 dc_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 3388 { 3389 struct dc_softc *sc; 3390 struct mii_data *mii; 3391 struct ifmedia *ifm; 3392 3393 sc = ifp->if_softc; 3394 mii = device_get_softc(sc->dc_miibus); 3395 mii_pollstat(mii); 3396 ifm = &mii->mii_media; 3397 if (DC_IS_DAVICOM(sc)) { 3398 if (IFM_SUBTYPE(ifm->ifm_media) == IFM_HPNA_1) { 3399 ifmr->ifm_active = ifm->ifm_media; 3400 ifmr->ifm_status = 0; 3401 return; 3402 } 3403 } 3404 ifmr->ifm_active = mii->mii_media_active; 3405 ifmr->ifm_status = mii->mii_media_status; 3406 } 3407 3408 static int 3409 dc_ioctl(struct ifnet *ifp, u_long command, caddr_t data) 3410 { 3411 struct dc_softc *sc = ifp->if_softc; 3412 struct ifreq *ifr = (struct ifreq *)data; 3413 struct mii_data *mii; 3414 int error = 0; 3415 3416 DC_LOCK(sc); 3417 3418 switch (command) { 3419 case SIOCSIFFLAGS: 3420 if (ifp->if_flags & IFF_UP) { 3421 int need_setfilt = (ifp->if_flags ^ sc->dc_if_flags) & 3422 (IFF_PROMISC | IFF_ALLMULTI); 3423 3424 if (ifp->if_flags & IFF_RUNNING) { 3425 if (need_setfilt) 3426 dc_setfilt(sc); 3427 } else { 3428 sc->dc_txthresh = 0; 3429 dc_init(sc); 3430 } 3431 } else { 3432 if (ifp->if_flags & IFF_RUNNING) 3433 dc_stop(sc); 3434 } 3435 sc->dc_if_flags = ifp->if_flags; 3436 error = 0; 3437 break; 3438 case SIOCADDMULTI: 3439 case SIOCDELMULTI: 3440 dc_setfilt(sc); 3441 error = 0; 3442 break; 3443 case SIOCGIFMEDIA: 3444 case SIOCSIFMEDIA: 3445 mii = device_get_softc(sc->dc_miibus); 3446 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 3447 #ifdef SRM_MEDIA 3448 if (sc->dc_srm_media) 3449 sc->dc_srm_media = 0; 3450 #endif 3451 break; 3452 default: 3453 error = ether_ioctl(ifp, command, data); 3454 break; 3455 } 3456 3457 DC_UNLOCK(sc); 3458 3459 return (error); 3460 } 3461 3462 static void 3463 dc_watchdog(struct ifnet *ifp) 3464 { 3465 struct dc_softc *sc; 3466 3467 sc = ifp->if_softc; 3468 3469 DC_LOCK(sc); 3470 3471 ifp->if_oerrors++; 3472 printf("dc%d: watchdog timeout\n", sc->dc_unit); 3473 3474 dc_stop(sc); 3475 dc_reset(sc); 3476 dc_init(sc); 3477 3478 if (ifp->if_snd.ifq_head != NULL) 3479 dc_start(ifp); 3480 3481 DC_UNLOCK(sc); 3482 } 3483 3484 /* 3485 * Stop the adapter and free any mbufs allocated to the 3486 * RX and TX lists. 3487 */ 3488 static void 3489 dc_stop(struct dc_softc *sc) 3490 { 3491 int i; 3492 struct ifnet *ifp; 3493 3494 DC_LOCK(sc); 3495 3496 ifp = &sc->arpcom.ac_if; 3497 ifp->if_timer = 0; 3498 3499 callout_stop(&sc->dc_stat_ch); 3500 3501 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 3502 #ifdef DEVICE_POLLING 3503 ether_poll_deregister(ifp); 3504 #endif 3505 3506 DC_CLRBIT(sc, DC_NETCFG, (DC_NETCFG_RX_ON | DC_NETCFG_TX_ON)); 3507 CSR_WRITE_4(sc, DC_IMR, 0x00000000); 3508 CSR_WRITE_4(sc, DC_TXADDR, 0x00000000); 3509 CSR_WRITE_4(sc, DC_RXADDR, 0x00000000); 3510 sc->dc_link = 0; 3511 3512 /* 3513 * Free data in the RX lists. 3514 */ 3515 for (i = 0; i < DC_RX_LIST_CNT; i++) { 3516 if (sc->dc_cdata.dc_rx_chain[i] != NULL) { 3517 m_freem(sc->dc_cdata.dc_rx_chain[i]); 3518 sc->dc_cdata.dc_rx_chain[i] = NULL; 3519 } 3520 } 3521 bzero(&sc->dc_ldata->dc_rx_list, sizeof(sc->dc_ldata->dc_rx_list)); 3522 3523 /* 3524 * Free the TX list buffers. 3525 */ 3526 for (i = 0; i < DC_TX_LIST_CNT; i++) { 3527 if (sc->dc_cdata.dc_tx_chain[i] != NULL) { 3528 if (sc->dc_ldata->dc_tx_list[i].dc_ctl & 3529 DC_TXCTL_SETUP) { 3530 sc->dc_cdata.dc_tx_chain[i] = NULL; 3531 continue; 3532 } 3533 m_freem(sc->dc_cdata.dc_tx_chain[i]); 3534 sc->dc_cdata.dc_tx_chain[i] = NULL; 3535 } 3536 } 3537 3538 bzero(&sc->dc_ldata->dc_tx_list, sizeof(sc->dc_ldata->dc_tx_list)); 3539 3540 DC_UNLOCK(sc); 3541 } 3542 3543 /* 3544 * Device suspend routine. Stop the interface and save some PCI 3545 * settings in case the BIOS doesn't restore them properly on 3546 * resume. 3547 */ 3548 static int 3549 dc_suspend(device_t dev) 3550 { 3551 struct dc_softc *sc; 3552 int i, s; 3553 3554 s = splimp(); 3555 3556 sc = device_get_softc(dev); 3557 3558 dc_stop(sc); 3559 3560 for (i = 0; i < 5; i++) 3561 sc->saved_maps[i] = pci_read_config(dev, PCIR_MAPS + i * 4, 4); 3562 sc->saved_biosaddr = pci_read_config(dev, PCIR_BIOS, 4); 3563 sc->saved_intline = pci_read_config(dev, PCIR_INTLINE, 1); 3564 sc->saved_cachelnsz = pci_read_config(dev, PCIR_CACHELNSZ, 1); 3565 sc->saved_lattimer = pci_read_config(dev, PCIR_LATTIMER, 1); 3566 3567 sc->suspended = 1; 3568 3569 splx(s); 3570 return (0); 3571 } 3572 3573 /* 3574 * Device resume routine. Restore some PCI settings in case the BIOS 3575 * doesn't, re-enable busmastering, and restart the interface if 3576 * appropriate. 3577 */ 3578 static int 3579 dc_resume(device_t dev) 3580 { 3581 struct dc_softc *sc; 3582 struct ifnet *ifp; 3583 int i, s; 3584 3585 s = splimp(); 3586 3587 sc = device_get_softc(dev); 3588 ifp = &sc->arpcom.ac_if; 3589 3590 dc_acpi(dev); 3591 3592 /* better way to do this? */ 3593 for (i = 0; i < 5; i++) 3594 pci_write_config(dev, PCIR_MAPS + i * 4, sc->saved_maps[i], 4); 3595 pci_write_config(dev, PCIR_BIOS, sc->saved_biosaddr, 4); 3596 pci_write_config(dev, PCIR_INTLINE, sc->saved_intline, 1); 3597 pci_write_config(dev, PCIR_CACHELNSZ, sc->saved_cachelnsz, 1); 3598 pci_write_config(dev, PCIR_LATTIMER, sc->saved_lattimer, 1); 3599 3600 /* reenable busmastering */ 3601 pci_enable_busmaster(dev); 3602 pci_enable_io(dev, DC_RES); 3603 3604 /* reinitialize interface if necessary */ 3605 if (ifp->if_flags & IFF_UP) 3606 dc_init(sc); 3607 3608 sc->suspended = 0; 3609 3610 splx(s); 3611 return (0); 3612 } 3613 3614 /* 3615 * Stop all chip I/O so that the kernel's probe routines don't 3616 * get confused by errant DMAs when rebooting. 3617 */ 3618 static void 3619 dc_shutdown(device_t dev) 3620 { 3621 struct dc_softc *sc; 3622 3623 sc = device_get_softc(dev); 3624 3625 dc_stop(sc); 3626 } 3627