1 /*- 2 * Copyright (c) 1997, 1998, 1999 3 * Bill Paul <wpaul@ee.columbia.edu>. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 3. All advertising materials mentioning features or use of this software 14 * must display the following acknowledgement: 15 * This product includes software developed by Bill Paul. 16 * 4. Neither the name of the author nor the names of any co-contributors 17 * may be used to endorse or promote products derived from this software 18 * without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30 * THE POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33 #include <sys/cdefs.h> 34 __FBSDID("$FreeBSD$"); 35 36 /* 37 * DEC "tulip" clone ethernet driver. Supports the DEC/Intel 21143 38 * series chips and several workalikes including the following: 39 * 40 * Macronix 98713/98715/98725/98727/98732 PMAC (www.macronix.com) 41 * Macronix/Lite-On 82c115 PNIC II (www.macronix.com) 42 * Lite-On 82c168/82c169 PNIC (www.litecom.com) 43 * ASIX Electronics AX88140A (www.asix.com.tw) 44 * ASIX Electronics AX88141 (www.asix.com.tw) 45 * ADMtek AL981 (www.admtek.com.tw) 46 * ADMtek AN985 (www.admtek.com.tw) 47 * Netgear FA511 (www.netgear.com) Appears to be rebadged ADMTek AN985 48 * Davicom DM9100, DM9102, DM9102A (www.davicom8.com) 49 * Accton EN1217 (www.accton.com) 50 * Xircom X3201 (www.xircom.com) 51 * Abocom FE2500 52 * Conexant LANfinity (www.conexant.com) 53 * 3Com OfficeConnect 10/100B 3CSOHO100B (www.3com.com) 54 * 55 * Datasheets for the 21143 are available at developer.intel.com. 56 * Datasheets for the clone parts can be found at their respective sites. 57 * (Except for the PNIC; see www.freebsd.org/~wpaul/PNIC/pnic.ps.gz.) 58 * The PNIC II is essentially a Macronix 98715A chip; the only difference 59 * worth noting is that its multicast hash table is only 128 bits wide 60 * instead of 512. 61 * 62 * Written by Bill Paul <wpaul@ee.columbia.edu> 63 * Electrical Engineering Department 64 * Columbia University, New York City 65 */ 66 /* 67 * The Intel 21143 is the successor to the DEC 21140. It is basically 68 * the same as the 21140 but with a few new features. The 21143 supports 69 * three kinds of media attachments: 70 * 71 * o MII port, for 10Mbps and 100Mbps support and NWAY 72 * autonegotiation provided by an external PHY. 73 * o SYM port, for symbol mode 100Mbps support. 74 * o 10baseT port. 75 * o AUI/BNC port. 76 * 77 * The 100Mbps SYM port and 10baseT port can be used together in 78 * combination with the internal NWAY support to create a 10/100 79 * autosensing configuration. 80 * 81 * Note that not all tulip workalikes are handled in this driver: we only 82 * deal with those which are relatively well behaved. The Winbond is 83 * handled separately due to its different register offsets and the 84 * special handling needed for its various bugs. The PNIC is handled 85 * here, but I'm not thrilled about it. 86 * 87 * All of the workalike chips use some form of MII transceiver support 88 * with the exception of the Macronix chips, which also have a SYM port. 89 * The ASIX AX88140A is also documented to have a SYM port, but all 90 * the cards I've seen use an MII transceiver, probably because the 91 * AX88140A doesn't support internal NWAY. 92 */ 93 94 #include <sys/param.h> 95 #include <sys/endian.h> 96 #include <sys/systm.h> 97 #include <sys/sockio.h> 98 #include <sys/mbuf.h> 99 #include <sys/malloc.h> 100 #include <sys/kernel.h> 101 #include <sys/module.h> 102 #include <sys/socket.h> 103 #include <sys/sysctl.h> 104 105 #include <net/if.h> 106 #include <net/if_arp.h> 107 #include <net/ethernet.h> 108 #include <net/if_dl.h> 109 #include <net/if_media.h> 110 #include <net/if_types.h> 111 #include <net/if_vlan_var.h> 112 113 #include <net/bpf.h> 114 115 #include <machine/bus_pio.h> 116 #include <machine/bus_memio.h> 117 #include <machine/bus.h> 118 #include <machine/resource.h> 119 #include <sys/bus.h> 120 #include <sys/rman.h> 121 122 #include <dev/mii/mii.h> 123 #include <dev/mii/miivar.h> 124 125 #include <dev/pci/pcireg.h> 126 #include <dev/pci/pcivar.h> 127 128 #define DC_USEIOSPACE 129 #ifdef __alpha__ 130 #define SRM_MEDIA 131 #endif 132 133 #include <pci/if_dcreg.h> 134 135 #ifdef __sparc64__ 136 #include <dev/ofw/openfirm.h> 137 #include <machine/ofw_machdep.h> 138 #endif 139 140 MODULE_DEPEND(dc, pci, 1, 1, 1); 141 MODULE_DEPEND(dc, ether, 1, 1, 1); 142 MODULE_DEPEND(dc, miibus, 1, 1, 1); 143 144 /* "controller miibus0" required. See GENERIC if you get errors here. */ 145 #include "miibus_if.h" 146 147 /* 148 * Various supported device vendors/types and their names. 149 */ 150 static struct dc_type dc_devs[] = { 151 { DC_VENDORID_DEC, DC_DEVICEID_21143, 152 "Intel 21143 10/100BaseTX" }, 153 { DC_VENDORID_DAVICOM, DC_DEVICEID_DM9009, 154 "Davicom DM9009 10/100BaseTX" }, 155 { DC_VENDORID_DAVICOM, DC_DEVICEID_DM9100, 156 "Davicom DM9100 10/100BaseTX" }, 157 { DC_VENDORID_DAVICOM, DC_DEVICEID_DM9102, 158 "Davicom DM9102 10/100BaseTX" }, 159 { DC_VENDORID_DAVICOM, DC_DEVICEID_DM9102, 160 "Davicom DM9102A 10/100BaseTX" }, 161 { DC_VENDORID_ADMTEK, DC_DEVICEID_AL981, 162 "ADMtek AL981 10/100BaseTX" }, 163 { DC_VENDORID_ADMTEK, DC_DEVICEID_AN985, 164 "ADMtek AN985 10/100BaseTX" }, 165 { DC_VENDORID_ADMTEK, DC_DEVICEID_ADM9511, 166 "ADMtek ADM9511 10/100BaseTX" }, 167 { DC_VENDORID_ADMTEK, DC_DEVICEID_ADM9513, 168 "ADMtek ADM9513 10/100BaseTX" }, 169 { DC_VENDORID_ADMTEK, DC_DEVICEID_FA511, 170 "Netgear FA511 10/100BaseTX" }, 171 { DC_VENDORID_ASIX, DC_DEVICEID_AX88140A, 172 "ASIX AX88140A 10/100BaseTX" }, 173 { DC_VENDORID_ASIX, DC_DEVICEID_AX88140A, 174 "ASIX AX88141 10/100BaseTX" }, 175 { DC_VENDORID_MX, DC_DEVICEID_98713, 176 "Macronix 98713 10/100BaseTX" }, 177 { DC_VENDORID_MX, DC_DEVICEID_98713, 178 "Macronix 98713A 10/100BaseTX" }, 179 { DC_VENDORID_CP, DC_DEVICEID_98713_CP, 180 "Compex RL100-TX 10/100BaseTX" }, 181 { DC_VENDORID_CP, DC_DEVICEID_98713_CP, 182 "Compex RL100-TX 10/100BaseTX" }, 183 { DC_VENDORID_MX, DC_DEVICEID_987x5, 184 "Macronix 98715/98715A 10/100BaseTX" }, 185 { DC_VENDORID_MX, DC_DEVICEID_987x5, 186 "Macronix 98715AEC-C 10/100BaseTX" }, 187 { DC_VENDORID_MX, DC_DEVICEID_987x5, 188 "Macronix 98725 10/100BaseTX" }, 189 { DC_VENDORID_MX, DC_DEVICEID_98727, 190 "Macronix 98727/98732 10/100BaseTX" }, 191 { DC_VENDORID_LO, DC_DEVICEID_82C115, 192 "LC82C115 PNIC II 10/100BaseTX" }, 193 { DC_VENDORID_LO, DC_DEVICEID_82C168, 194 "82c168 PNIC 10/100BaseTX" }, 195 { DC_VENDORID_LO, DC_DEVICEID_82C168, 196 "82c169 PNIC 10/100BaseTX" }, 197 { DC_VENDORID_ACCTON, DC_DEVICEID_EN1217, 198 "Accton EN1217 10/100BaseTX" }, 199 { DC_VENDORID_ACCTON, DC_DEVICEID_EN2242, 200 "Accton EN2242 MiniPCI 10/100BaseTX" }, 201 { DC_VENDORID_XIRCOM, DC_DEVICEID_X3201, 202 "Xircom X3201 10/100BaseTX" }, 203 { DC_VENDORID_ABOCOM, DC_DEVICEID_FE2500, 204 "Abocom FE2500 10/100BaseTX" }, 205 { DC_VENDORID_ABOCOM, DC_DEVICEID_FE2500MX, 206 "Abocom FE2500MX 10/100BaseTX" }, 207 { DC_VENDORID_CONEXANT, DC_DEVICEID_RS7112, 208 "Conexant LANfinity MiniPCI 10/100BaseTX" }, 209 { DC_VENDORID_HAWKING, DC_DEVICEID_HAWKING_PN672TX, 210 "Hawking CB102 CardBus 10/100" }, 211 { DC_VENDORID_PLANEX, DC_DEVICEID_FNW3602T, 212 "PlaneX FNW-3602-T CardBus 10/100" }, 213 { DC_VENDORID_3COM, DC_DEVICEID_3CSOHOB, 214 "3Com OfficeConnect 10/100B" }, 215 { DC_VENDORID_MICROSOFT, DC_DEVICEID_MSMN120, 216 "Microsoft MN-120 CardBus 10/100" }, 217 { DC_VENDORID_MICROSOFT, DC_DEVICEID_MSMN130, 218 "Microsoft MN-130 10/100" }, 219 { DC_VENDORID_MICROSOFT, DC_DEVICEID_MSMN130_FAKE, 220 "Microsoft MN-130 10/100" }, 221 { 0, 0, NULL } 222 }; 223 224 static int dc_probe(device_t); 225 static int dc_attach(device_t); 226 static int dc_detach(device_t); 227 static int dc_suspend(device_t); 228 static int dc_resume(device_t); 229 static struct dc_type *dc_devtype(device_t); 230 static int dc_newbuf(struct dc_softc *, int, int); 231 static int dc_encap(struct dc_softc *, struct mbuf **); 232 static void dc_pnic_rx_bug_war(struct dc_softc *, int); 233 static int dc_rx_resync(struct dc_softc *); 234 static void dc_rxeof(struct dc_softc *); 235 static void dc_txeof(struct dc_softc *); 236 static void dc_tick(void *); 237 static void dc_tx_underrun(struct dc_softc *); 238 static void dc_intr(void *); 239 static void dc_start(struct ifnet *); 240 static int dc_ioctl(struct ifnet *, u_long, caddr_t); 241 static void dc_init(void *); 242 static void dc_stop(struct dc_softc *); 243 static void dc_watchdog(struct ifnet *); 244 static void dc_shutdown(device_t); 245 static int dc_ifmedia_upd(struct ifnet *); 246 static void dc_ifmedia_sts(struct ifnet *, struct ifmediareq *); 247 248 static void dc_delay(struct dc_softc *); 249 static void dc_eeprom_idle(struct dc_softc *); 250 static void dc_eeprom_putbyte(struct dc_softc *, int); 251 static void dc_eeprom_getword(struct dc_softc *, int, u_int16_t *); 252 static void dc_eeprom_getword_pnic(struct dc_softc *, int, u_int16_t *); 253 static void dc_eeprom_getword_xircom(struct dc_softc *, int, u_int16_t *); 254 static void dc_eeprom_width(struct dc_softc *); 255 static void dc_read_eeprom(struct dc_softc *, caddr_t, int, int, int); 256 257 static void dc_mii_writebit(struct dc_softc *, int); 258 static int dc_mii_readbit(struct dc_softc *); 259 static void dc_mii_sync(struct dc_softc *); 260 static void dc_mii_send(struct dc_softc *, u_int32_t, int); 261 static int dc_mii_readreg(struct dc_softc *, struct dc_mii_frame *); 262 static int dc_mii_writereg(struct dc_softc *, struct dc_mii_frame *); 263 static int dc_miibus_readreg(device_t, int, int); 264 static int dc_miibus_writereg(device_t, int, int, int); 265 static void dc_miibus_statchg(device_t); 266 static void dc_miibus_mediainit(device_t); 267 268 static void dc_setcfg(struct dc_softc *, int); 269 static uint32_t dc_mchash_le(struct dc_softc *, const uint8_t *); 270 static uint32_t dc_mchash_be(const uint8_t *); 271 static void dc_setfilt_21143(struct dc_softc *); 272 static void dc_setfilt_asix(struct dc_softc *); 273 static void dc_setfilt_admtek(struct dc_softc *); 274 static void dc_setfilt_xircom(struct dc_softc *); 275 276 static void dc_setfilt(struct dc_softc *); 277 278 static void dc_reset(struct dc_softc *); 279 static int dc_list_rx_init(struct dc_softc *); 280 static int dc_list_tx_init(struct dc_softc *); 281 282 static void dc_read_srom(struct dc_softc *, int); 283 static void dc_parse_21143_srom(struct dc_softc *); 284 static void dc_decode_leaf_sia(struct dc_softc *, struct dc_eblock_sia *); 285 static void dc_decode_leaf_mii(struct dc_softc *, struct dc_eblock_mii *); 286 static void dc_decode_leaf_sym(struct dc_softc *, struct dc_eblock_sym *); 287 static void dc_apply_fixup(struct dc_softc *, int); 288 289 static void dc_dma_map_txbuf(void *, bus_dma_segment_t *, int, bus_size_t, int); 290 static void dc_dma_map_rxbuf(void *, bus_dma_segment_t *, int, bus_size_t, int); 291 292 #ifdef DC_USEIOSPACE 293 #define DC_RES SYS_RES_IOPORT 294 #define DC_RID DC_PCI_CFBIO 295 #else 296 #define DC_RES SYS_RES_MEMORY 297 #define DC_RID DC_PCI_CFBMA 298 #endif 299 300 static device_method_t dc_methods[] = { 301 /* Device interface */ 302 DEVMETHOD(device_probe, dc_probe), 303 DEVMETHOD(device_attach, dc_attach), 304 DEVMETHOD(device_detach, dc_detach), 305 DEVMETHOD(device_suspend, dc_suspend), 306 DEVMETHOD(device_resume, dc_resume), 307 DEVMETHOD(device_shutdown, dc_shutdown), 308 309 /* bus interface */ 310 DEVMETHOD(bus_print_child, bus_generic_print_child), 311 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 312 313 /* MII interface */ 314 DEVMETHOD(miibus_readreg, dc_miibus_readreg), 315 DEVMETHOD(miibus_writereg, dc_miibus_writereg), 316 DEVMETHOD(miibus_statchg, dc_miibus_statchg), 317 DEVMETHOD(miibus_mediainit, dc_miibus_mediainit), 318 319 { 0, 0 } 320 }; 321 322 static driver_t dc_driver = { 323 "dc", 324 dc_methods, 325 sizeof(struct dc_softc) 326 }; 327 328 static devclass_t dc_devclass; 329 #ifdef __i386__ 330 static int dc_quick = 1; 331 SYSCTL_INT(_hw, OID_AUTO, dc_quick, CTLFLAG_RW, &dc_quick, 0, 332 "do not m_devget() in dc driver"); 333 #endif 334 335 DRIVER_MODULE(dc, cardbus, dc_driver, dc_devclass, 0, 0); 336 DRIVER_MODULE(dc, pci, dc_driver, dc_devclass, 0, 0); 337 DRIVER_MODULE(miibus, dc, miibus_driver, miibus_devclass, 0, 0); 338 339 #define DC_SETBIT(sc, reg, x) \ 340 CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) | (x)) 341 342 #define DC_CLRBIT(sc, reg, x) \ 343 CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) & ~(x)) 344 345 #define SIO_SET(x) DC_SETBIT(sc, DC_SIO, (x)) 346 #define SIO_CLR(x) DC_CLRBIT(sc, DC_SIO, (x)) 347 348 #define IS_MPSAFE 0 349 350 static void 351 dc_delay(struct dc_softc *sc) 352 { 353 int idx; 354 355 for (idx = (300 / 33) + 1; idx > 0; idx--) 356 CSR_READ_4(sc, DC_BUSCTL); 357 } 358 359 static void 360 dc_eeprom_width(struct dc_softc *sc) 361 { 362 int i; 363 364 /* Force EEPROM to idle state. */ 365 dc_eeprom_idle(sc); 366 367 /* Enter EEPROM access mode. */ 368 CSR_WRITE_4(sc, DC_SIO, DC_SIO_EESEL); 369 dc_delay(sc); 370 DC_SETBIT(sc, DC_SIO, DC_SIO_ROMCTL_READ); 371 dc_delay(sc); 372 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); 373 dc_delay(sc); 374 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CS); 375 dc_delay(sc); 376 377 for (i = 3; i--;) { 378 if (6 & (1 << i)) 379 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_DATAIN); 380 else 381 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_DATAIN); 382 dc_delay(sc); 383 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CLK); 384 dc_delay(sc); 385 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); 386 dc_delay(sc); 387 } 388 389 for (i = 1; i <= 12; i++) { 390 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CLK); 391 dc_delay(sc); 392 if (!(CSR_READ_4(sc, DC_SIO) & DC_SIO_EE_DATAOUT)) { 393 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); 394 dc_delay(sc); 395 break; 396 } 397 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); 398 dc_delay(sc); 399 } 400 401 /* Turn off EEPROM access mode. */ 402 dc_eeprom_idle(sc); 403 404 if (i < 4 || i > 12) 405 sc->dc_romwidth = 6; 406 else 407 sc->dc_romwidth = i; 408 409 /* Enter EEPROM access mode. */ 410 CSR_WRITE_4(sc, DC_SIO, DC_SIO_EESEL); 411 dc_delay(sc); 412 DC_SETBIT(sc, DC_SIO, DC_SIO_ROMCTL_READ); 413 dc_delay(sc); 414 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); 415 dc_delay(sc); 416 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CS); 417 dc_delay(sc); 418 419 /* Turn off EEPROM access mode. */ 420 dc_eeprom_idle(sc); 421 } 422 423 static void 424 dc_eeprom_idle(struct dc_softc *sc) 425 { 426 int i; 427 428 CSR_WRITE_4(sc, DC_SIO, DC_SIO_EESEL); 429 dc_delay(sc); 430 DC_SETBIT(sc, DC_SIO, DC_SIO_ROMCTL_READ); 431 dc_delay(sc); 432 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); 433 dc_delay(sc); 434 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CS); 435 dc_delay(sc); 436 437 for (i = 0; i < 25; i++) { 438 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); 439 dc_delay(sc); 440 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CLK); 441 dc_delay(sc); 442 } 443 444 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); 445 dc_delay(sc); 446 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CS); 447 dc_delay(sc); 448 CSR_WRITE_4(sc, DC_SIO, 0x00000000); 449 } 450 451 /* 452 * Send a read command and address to the EEPROM, check for ACK. 453 */ 454 static void 455 dc_eeprom_putbyte(struct dc_softc *sc, int addr) 456 { 457 int d, i; 458 459 d = DC_EECMD_READ >> 6; 460 for (i = 3; i--; ) { 461 if (d & (1 << i)) 462 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_DATAIN); 463 else 464 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_DATAIN); 465 dc_delay(sc); 466 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CLK); 467 dc_delay(sc); 468 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); 469 dc_delay(sc); 470 } 471 472 /* 473 * Feed in each bit and strobe the clock. 474 */ 475 for (i = sc->dc_romwidth; i--;) { 476 if (addr & (1 << i)) { 477 SIO_SET(DC_SIO_EE_DATAIN); 478 } else { 479 SIO_CLR(DC_SIO_EE_DATAIN); 480 } 481 dc_delay(sc); 482 SIO_SET(DC_SIO_EE_CLK); 483 dc_delay(sc); 484 SIO_CLR(DC_SIO_EE_CLK); 485 dc_delay(sc); 486 } 487 } 488 489 /* 490 * Read a word of data stored in the EEPROM at address 'addr.' 491 * The PNIC 82c168/82c169 has its own non-standard way to read 492 * the EEPROM. 493 */ 494 static void 495 dc_eeprom_getword_pnic(struct dc_softc *sc, int addr, u_int16_t *dest) 496 { 497 int i; 498 u_int32_t r; 499 500 CSR_WRITE_4(sc, DC_PN_SIOCTL, DC_PN_EEOPCODE_READ | addr); 501 502 for (i = 0; i < DC_TIMEOUT; i++) { 503 DELAY(1); 504 r = CSR_READ_4(sc, DC_SIO); 505 if (!(r & DC_PN_SIOCTL_BUSY)) { 506 *dest = (u_int16_t)(r & 0xFFFF); 507 return; 508 } 509 } 510 } 511 512 /* 513 * Read a word of data stored in the EEPROM at address 'addr.' 514 * The Xircom X3201 has its own non-standard way to read 515 * the EEPROM, too. 516 */ 517 static void 518 dc_eeprom_getword_xircom(struct dc_softc *sc, int addr, u_int16_t *dest) 519 { 520 521 SIO_SET(DC_SIO_ROMSEL | DC_SIO_ROMCTL_READ); 522 523 addr *= 2; 524 CSR_WRITE_4(sc, DC_ROM, addr | 0x160); 525 *dest = (u_int16_t)CSR_READ_4(sc, DC_SIO) & 0xff; 526 addr += 1; 527 CSR_WRITE_4(sc, DC_ROM, addr | 0x160); 528 *dest |= ((u_int16_t)CSR_READ_4(sc, DC_SIO) & 0xff) << 8; 529 530 SIO_CLR(DC_SIO_ROMSEL | DC_SIO_ROMCTL_READ); 531 } 532 533 /* 534 * Read a word of data stored in the EEPROM at address 'addr.' 535 */ 536 static void 537 dc_eeprom_getword(struct dc_softc *sc, int addr, u_int16_t *dest) 538 { 539 int i; 540 u_int16_t word = 0; 541 542 /* Force EEPROM to idle state. */ 543 dc_eeprom_idle(sc); 544 545 /* Enter EEPROM access mode. */ 546 CSR_WRITE_4(sc, DC_SIO, DC_SIO_EESEL); 547 dc_delay(sc); 548 DC_SETBIT(sc, DC_SIO, DC_SIO_ROMCTL_READ); 549 dc_delay(sc); 550 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); 551 dc_delay(sc); 552 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CS); 553 dc_delay(sc); 554 555 /* 556 * Send address of word we want to read. 557 */ 558 dc_eeprom_putbyte(sc, addr); 559 560 /* 561 * Start reading bits from EEPROM. 562 */ 563 for (i = 0x8000; i; i >>= 1) { 564 SIO_SET(DC_SIO_EE_CLK); 565 dc_delay(sc); 566 if (CSR_READ_4(sc, DC_SIO) & DC_SIO_EE_DATAOUT) 567 word |= i; 568 dc_delay(sc); 569 SIO_CLR(DC_SIO_EE_CLK); 570 dc_delay(sc); 571 } 572 573 /* Turn off EEPROM access mode. */ 574 dc_eeprom_idle(sc); 575 576 *dest = word; 577 } 578 579 /* 580 * Read a sequence of words from the EEPROM. 581 */ 582 static void 583 dc_read_eeprom(struct dc_softc *sc, caddr_t dest, int off, int cnt, int be) 584 { 585 int i; 586 u_int16_t word = 0, *ptr; 587 588 for (i = 0; i < cnt; i++) { 589 if (DC_IS_PNIC(sc)) 590 dc_eeprom_getword_pnic(sc, off + i, &word); 591 else if (DC_IS_XIRCOM(sc)) 592 dc_eeprom_getword_xircom(sc, off + i, &word); 593 else 594 dc_eeprom_getword(sc, off + i, &word); 595 ptr = (u_int16_t *)(dest + (i * 2)); 596 if (be) 597 *ptr = be16toh(word); 598 else 599 *ptr = le16toh(word); 600 } 601 } 602 603 /* 604 * The following two routines are taken from the Macronix 98713 605 * Application Notes pp.19-21. 606 */ 607 /* 608 * Write a bit to the MII bus. 609 */ 610 static void 611 dc_mii_writebit(struct dc_softc *sc, int bit) 612 { 613 614 if (bit) 615 CSR_WRITE_4(sc, DC_SIO, 616 DC_SIO_ROMCTL_WRITE | DC_SIO_MII_DATAOUT); 617 else 618 CSR_WRITE_4(sc, DC_SIO, DC_SIO_ROMCTL_WRITE); 619 620 DC_SETBIT(sc, DC_SIO, DC_SIO_MII_CLK); 621 DC_CLRBIT(sc, DC_SIO, DC_SIO_MII_CLK); 622 } 623 624 /* 625 * Read a bit from the MII bus. 626 */ 627 static int 628 dc_mii_readbit(struct dc_softc *sc) 629 { 630 631 CSR_WRITE_4(sc, DC_SIO, DC_SIO_ROMCTL_READ | DC_SIO_MII_DIR); 632 CSR_READ_4(sc, DC_SIO); 633 DC_SETBIT(sc, DC_SIO, DC_SIO_MII_CLK); 634 DC_CLRBIT(sc, DC_SIO, DC_SIO_MII_CLK); 635 if (CSR_READ_4(sc, DC_SIO) & DC_SIO_MII_DATAIN) 636 return (1); 637 638 return (0); 639 } 640 641 /* 642 * Sync the PHYs by setting data bit and strobing the clock 32 times. 643 */ 644 static void 645 dc_mii_sync(struct dc_softc *sc) 646 { 647 int i; 648 649 CSR_WRITE_4(sc, DC_SIO, DC_SIO_ROMCTL_WRITE); 650 651 for (i = 0; i < 32; i++) 652 dc_mii_writebit(sc, 1); 653 } 654 655 /* 656 * Clock a series of bits through the MII. 657 */ 658 static void 659 dc_mii_send(struct dc_softc *sc, u_int32_t bits, int cnt) 660 { 661 int i; 662 663 for (i = (0x1 << (cnt - 1)); i; i >>= 1) 664 dc_mii_writebit(sc, bits & i); 665 } 666 667 /* 668 * Read an PHY register through the MII. 669 */ 670 static int 671 dc_mii_readreg(struct dc_softc *sc, struct dc_mii_frame *frame) 672 { 673 int i, ack; 674 675 DC_LOCK(sc); 676 677 /* 678 * Set up frame for RX. 679 */ 680 frame->mii_stdelim = DC_MII_STARTDELIM; 681 frame->mii_opcode = DC_MII_READOP; 682 frame->mii_turnaround = 0; 683 frame->mii_data = 0; 684 685 /* 686 * Sync the PHYs. 687 */ 688 dc_mii_sync(sc); 689 690 /* 691 * Send command/address info. 692 */ 693 dc_mii_send(sc, frame->mii_stdelim, 2); 694 dc_mii_send(sc, frame->mii_opcode, 2); 695 dc_mii_send(sc, frame->mii_phyaddr, 5); 696 dc_mii_send(sc, frame->mii_regaddr, 5); 697 698 #ifdef notdef 699 /* Idle bit */ 700 dc_mii_writebit(sc, 1); 701 dc_mii_writebit(sc, 0); 702 #endif 703 704 /* Check for ack. */ 705 ack = dc_mii_readbit(sc); 706 707 /* 708 * Now try reading data bits. If the ack failed, we still 709 * need to clock through 16 cycles to keep the PHY(s) in sync. 710 */ 711 if (ack) { 712 for (i = 0; i < 16; i++) 713 dc_mii_readbit(sc); 714 goto fail; 715 } 716 717 for (i = 0x8000; i; i >>= 1) { 718 if (!ack) { 719 if (dc_mii_readbit(sc)) 720 frame->mii_data |= i; 721 } 722 } 723 724 fail: 725 726 dc_mii_writebit(sc, 0); 727 dc_mii_writebit(sc, 0); 728 729 DC_UNLOCK(sc); 730 731 if (ack) 732 return (1); 733 return (0); 734 } 735 736 /* 737 * Write to a PHY register through the MII. 738 */ 739 static int 740 dc_mii_writereg(struct dc_softc *sc, struct dc_mii_frame *frame) 741 { 742 743 DC_LOCK(sc); 744 /* 745 * Set up frame for TX. 746 */ 747 748 frame->mii_stdelim = DC_MII_STARTDELIM; 749 frame->mii_opcode = DC_MII_WRITEOP; 750 frame->mii_turnaround = DC_MII_TURNAROUND; 751 752 /* 753 * Sync the PHYs. 754 */ 755 dc_mii_sync(sc); 756 757 dc_mii_send(sc, frame->mii_stdelim, 2); 758 dc_mii_send(sc, frame->mii_opcode, 2); 759 dc_mii_send(sc, frame->mii_phyaddr, 5); 760 dc_mii_send(sc, frame->mii_regaddr, 5); 761 dc_mii_send(sc, frame->mii_turnaround, 2); 762 dc_mii_send(sc, frame->mii_data, 16); 763 764 /* Idle bit. */ 765 dc_mii_writebit(sc, 0); 766 dc_mii_writebit(sc, 0); 767 768 DC_UNLOCK(sc); 769 770 return (0); 771 } 772 773 static int 774 dc_miibus_readreg(device_t dev, int phy, int reg) 775 { 776 struct dc_mii_frame frame; 777 struct dc_softc *sc; 778 int i, rval, phy_reg = 0; 779 780 sc = device_get_softc(dev); 781 bzero(&frame, sizeof(frame)); 782 783 /* 784 * Note: both the AL981 and AN985 have internal PHYs, 785 * however the AL981 provides direct access to the PHY 786 * registers while the AN985 uses a serial MII interface. 787 * The AN985's MII interface is also buggy in that you 788 * can read from any MII address (0 to 31), but only address 1 789 * behaves normally. To deal with both cases, we pretend 790 * that the PHY is at MII address 1. 791 */ 792 if (DC_IS_ADMTEK(sc) && phy != DC_ADMTEK_PHYADDR) 793 return (0); 794 795 /* 796 * Note: the ukphy probes of the RS7112 report a PHY at 797 * MII address 0 (possibly HomePNA?) and 1 (ethernet) 798 * so we only respond to correct one. 799 */ 800 if (DC_IS_CONEXANT(sc) && phy != DC_CONEXANT_PHYADDR) 801 return (0); 802 803 if (sc->dc_pmode != DC_PMODE_MII) { 804 if (phy == (MII_NPHY - 1)) { 805 switch (reg) { 806 case MII_BMSR: 807 /* 808 * Fake something to make the probe 809 * code think there's a PHY here. 810 */ 811 return (BMSR_MEDIAMASK); 812 break; 813 case MII_PHYIDR1: 814 if (DC_IS_PNIC(sc)) 815 return (DC_VENDORID_LO); 816 return (DC_VENDORID_DEC); 817 break; 818 case MII_PHYIDR2: 819 if (DC_IS_PNIC(sc)) 820 return (DC_DEVICEID_82C168); 821 return (DC_DEVICEID_21143); 822 break; 823 default: 824 return (0); 825 break; 826 } 827 } else 828 return (0); 829 } 830 831 if (DC_IS_PNIC(sc)) { 832 CSR_WRITE_4(sc, DC_PN_MII, DC_PN_MIIOPCODE_READ | 833 (phy << 23) | (reg << 18)); 834 for (i = 0; i < DC_TIMEOUT; i++) { 835 DELAY(1); 836 rval = CSR_READ_4(sc, DC_PN_MII); 837 if (!(rval & DC_PN_MII_BUSY)) { 838 rval &= 0xFFFF; 839 return (rval == 0xFFFF ? 0 : rval); 840 } 841 } 842 return (0); 843 } 844 845 if (DC_IS_COMET(sc)) { 846 switch (reg) { 847 case MII_BMCR: 848 phy_reg = DC_AL_BMCR; 849 break; 850 case MII_BMSR: 851 phy_reg = DC_AL_BMSR; 852 break; 853 case MII_PHYIDR1: 854 phy_reg = DC_AL_VENID; 855 break; 856 case MII_PHYIDR2: 857 phy_reg = DC_AL_DEVID; 858 break; 859 case MII_ANAR: 860 phy_reg = DC_AL_ANAR; 861 break; 862 case MII_ANLPAR: 863 phy_reg = DC_AL_LPAR; 864 break; 865 case MII_ANER: 866 phy_reg = DC_AL_ANER; 867 break; 868 default: 869 printf("dc%d: phy_read: bad phy register %x\n", 870 sc->dc_unit, reg); 871 return (0); 872 break; 873 } 874 875 rval = CSR_READ_4(sc, phy_reg) & 0x0000FFFF; 876 877 if (rval == 0xFFFF) 878 return (0); 879 return (rval); 880 } 881 882 frame.mii_phyaddr = phy; 883 frame.mii_regaddr = reg; 884 if (sc->dc_type == DC_TYPE_98713) { 885 phy_reg = CSR_READ_4(sc, DC_NETCFG); 886 CSR_WRITE_4(sc, DC_NETCFG, phy_reg & ~DC_NETCFG_PORTSEL); 887 } 888 dc_mii_readreg(sc, &frame); 889 if (sc->dc_type == DC_TYPE_98713) 890 CSR_WRITE_4(sc, DC_NETCFG, phy_reg); 891 892 return (frame.mii_data); 893 } 894 895 static int 896 dc_miibus_writereg(device_t dev, int phy, int reg, int data) 897 { 898 struct dc_softc *sc; 899 struct dc_mii_frame frame; 900 int i, phy_reg = 0; 901 902 sc = device_get_softc(dev); 903 bzero(&frame, sizeof(frame)); 904 905 if (DC_IS_ADMTEK(sc) && phy != DC_ADMTEK_PHYADDR) 906 return (0); 907 908 if (DC_IS_CONEXANT(sc) && phy != DC_CONEXANT_PHYADDR) 909 return (0); 910 911 if (DC_IS_PNIC(sc)) { 912 CSR_WRITE_4(sc, DC_PN_MII, DC_PN_MIIOPCODE_WRITE | 913 (phy << 23) | (reg << 10) | data); 914 for (i = 0; i < DC_TIMEOUT; i++) { 915 if (!(CSR_READ_4(sc, DC_PN_MII) & DC_PN_MII_BUSY)) 916 break; 917 } 918 return (0); 919 } 920 921 if (DC_IS_COMET(sc)) { 922 switch (reg) { 923 case MII_BMCR: 924 phy_reg = DC_AL_BMCR; 925 break; 926 case MII_BMSR: 927 phy_reg = DC_AL_BMSR; 928 break; 929 case MII_PHYIDR1: 930 phy_reg = DC_AL_VENID; 931 break; 932 case MII_PHYIDR2: 933 phy_reg = DC_AL_DEVID; 934 break; 935 case MII_ANAR: 936 phy_reg = DC_AL_ANAR; 937 break; 938 case MII_ANLPAR: 939 phy_reg = DC_AL_LPAR; 940 break; 941 case MII_ANER: 942 phy_reg = DC_AL_ANER; 943 break; 944 default: 945 printf("dc%d: phy_write: bad phy register %x\n", 946 sc->dc_unit, reg); 947 return (0); 948 break; 949 } 950 951 CSR_WRITE_4(sc, phy_reg, data); 952 return (0); 953 } 954 955 frame.mii_phyaddr = phy; 956 frame.mii_regaddr = reg; 957 frame.mii_data = data; 958 959 if (sc->dc_type == DC_TYPE_98713) { 960 phy_reg = CSR_READ_4(sc, DC_NETCFG); 961 CSR_WRITE_4(sc, DC_NETCFG, phy_reg & ~DC_NETCFG_PORTSEL); 962 } 963 dc_mii_writereg(sc, &frame); 964 if (sc->dc_type == DC_TYPE_98713) 965 CSR_WRITE_4(sc, DC_NETCFG, phy_reg); 966 967 return (0); 968 } 969 970 static void 971 dc_miibus_statchg(device_t dev) 972 { 973 struct dc_softc *sc; 974 struct mii_data *mii; 975 struct ifmedia *ifm; 976 977 sc = device_get_softc(dev); 978 if (DC_IS_ADMTEK(sc)) 979 return; 980 981 mii = device_get_softc(sc->dc_miibus); 982 ifm = &mii->mii_media; 983 if (DC_IS_DAVICOM(sc) && 984 IFM_SUBTYPE(ifm->ifm_media) == IFM_HPNA_1) { 985 dc_setcfg(sc, ifm->ifm_media); 986 sc->dc_if_media = ifm->ifm_media; 987 } else { 988 dc_setcfg(sc, mii->mii_media_active); 989 sc->dc_if_media = mii->mii_media_active; 990 } 991 } 992 993 /* 994 * Special support for DM9102A cards with HomePNA PHYs. Note: 995 * with the Davicom DM9102A/DM9801 eval board that I have, it seems 996 * to be impossible to talk to the management interface of the DM9801 997 * PHY (its MDIO pin is not connected to anything). Consequently, 998 * the driver has to just 'know' about the additional mode and deal 999 * with it itself. *sigh* 1000 */ 1001 static void 1002 dc_miibus_mediainit(device_t dev) 1003 { 1004 struct dc_softc *sc; 1005 struct mii_data *mii; 1006 struct ifmedia *ifm; 1007 int rev; 1008 1009 rev = pci_read_config(dev, DC_PCI_CFRV, 4) & 0xFF; 1010 1011 sc = device_get_softc(dev); 1012 mii = device_get_softc(sc->dc_miibus); 1013 ifm = &mii->mii_media; 1014 1015 if (DC_IS_DAVICOM(sc) && rev >= DC_REVISION_DM9102A) 1016 ifmedia_add(ifm, IFM_ETHER | IFM_HPNA_1, 0, NULL); 1017 } 1018 1019 #define DC_BITS_512 9 1020 #define DC_BITS_128 7 1021 #define DC_BITS_64 6 1022 1023 static uint32_t 1024 dc_mchash_le(struct dc_softc *sc, const uint8_t *addr) 1025 { 1026 uint32_t crc; 1027 1028 /* Compute CRC for the address value. */ 1029 crc = ether_crc32_le(addr, ETHER_ADDR_LEN); 1030 1031 /* 1032 * The hash table on the PNIC II and the MX98715AEC-C/D/E 1033 * chips is only 128 bits wide. 1034 */ 1035 if (sc->dc_flags & DC_128BIT_HASH) 1036 return (crc & ((1 << DC_BITS_128) - 1)); 1037 1038 /* The hash table on the MX98715BEC is only 64 bits wide. */ 1039 if (sc->dc_flags & DC_64BIT_HASH) 1040 return (crc & ((1 << DC_BITS_64) - 1)); 1041 1042 /* Xircom's hash filtering table is different (read: weird) */ 1043 /* Xircom uses the LEAST significant bits */ 1044 if (DC_IS_XIRCOM(sc)) { 1045 if ((crc & 0x180) == 0x180) 1046 return ((crc & 0x0F) + (crc & 0x70) * 3 + (14 << 4)); 1047 else 1048 return ((crc & 0x1F) + ((crc >> 1) & 0xF0) * 3 + 1049 (12 << 4)); 1050 } 1051 1052 return (crc & ((1 << DC_BITS_512) - 1)); 1053 } 1054 1055 /* 1056 * Calculate CRC of a multicast group address, return the lower 6 bits. 1057 */ 1058 static uint32_t 1059 dc_mchash_be(const uint8_t *addr) 1060 { 1061 uint32_t crc; 1062 1063 /* Compute CRC for the address value. */ 1064 crc = ether_crc32_be(addr, ETHER_ADDR_LEN); 1065 1066 /* Return the filter bit position. */ 1067 return ((crc >> 26) & 0x0000003F); 1068 } 1069 1070 /* 1071 * 21143-style RX filter setup routine. Filter programming is done by 1072 * downloading a special setup frame into the TX engine. 21143, Macronix, 1073 * PNIC, PNIC II and Davicom chips are programmed this way. 1074 * 1075 * We always program the chip using 'hash perfect' mode, i.e. one perfect 1076 * address (our node address) and a 512-bit hash filter for multicast 1077 * frames. We also sneak the broadcast address into the hash filter since 1078 * we need that too. 1079 */ 1080 static void 1081 dc_setfilt_21143(struct dc_softc *sc) 1082 { 1083 struct dc_desc *sframe; 1084 u_int32_t h, *sp; 1085 struct ifmultiaddr *ifma; 1086 struct ifnet *ifp; 1087 int i; 1088 1089 ifp = &sc->arpcom.ac_if; 1090 1091 i = sc->dc_cdata.dc_tx_prod; 1092 DC_INC(sc->dc_cdata.dc_tx_prod, DC_TX_LIST_CNT); 1093 sc->dc_cdata.dc_tx_cnt++; 1094 sframe = &sc->dc_ldata->dc_tx_list[i]; 1095 sp = sc->dc_cdata.dc_sbuf; 1096 bzero(sp, DC_SFRAME_LEN); 1097 1098 sframe->dc_data = htole32(sc->dc_saddr); 1099 sframe->dc_ctl = htole32(DC_SFRAME_LEN | DC_TXCTL_SETUP | 1100 DC_TXCTL_TLINK | DC_FILTER_HASHPERF | DC_TXCTL_FINT); 1101 1102 sc->dc_cdata.dc_tx_chain[i] = (struct mbuf *)sc->dc_cdata.dc_sbuf; 1103 1104 /* If we want promiscuous mode, set the allframes bit. */ 1105 if (ifp->if_flags & IFF_PROMISC) 1106 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC); 1107 else 1108 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC); 1109 1110 if (ifp->if_flags & IFF_ALLMULTI) 1111 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI); 1112 else 1113 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI); 1114 1115 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 1116 if (ifma->ifma_addr->sa_family != AF_LINK) 1117 continue; 1118 h = dc_mchash_le(sc, 1119 LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 1120 sp[h >> 4] |= htole32(1 << (h & 0xF)); 1121 } 1122 1123 if (ifp->if_flags & IFF_BROADCAST) { 1124 h = dc_mchash_le(sc, ifp->if_broadcastaddr); 1125 sp[h >> 4] |= htole32(1 << (h & 0xF)); 1126 } 1127 1128 /* Set our MAC address */ 1129 sp[39] = DC_SP_MAC(((u_int16_t *)sc->arpcom.ac_enaddr)[0]); 1130 sp[40] = DC_SP_MAC(((u_int16_t *)sc->arpcom.ac_enaddr)[1]); 1131 sp[41] = DC_SP_MAC(((u_int16_t *)sc->arpcom.ac_enaddr)[2]); 1132 1133 sframe->dc_status = htole32(DC_TXSTAT_OWN); 1134 CSR_WRITE_4(sc, DC_TXSTART, 0xFFFFFFFF); 1135 1136 /* 1137 * The PNIC takes an exceedingly long time to process its 1138 * setup frame; wait 10ms after posting the setup frame 1139 * before proceeding, just so it has time to swallow its 1140 * medicine. 1141 */ 1142 DELAY(10000); 1143 1144 ifp->if_timer = 5; 1145 } 1146 1147 static void 1148 dc_setfilt_admtek(struct dc_softc *sc) 1149 { 1150 struct ifnet *ifp; 1151 struct ifmultiaddr *ifma; 1152 int h = 0; 1153 u_int32_t hashes[2] = { 0, 0 }; 1154 1155 ifp = &sc->arpcom.ac_if; 1156 1157 /* Init our MAC address. */ 1158 CSR_WRITE_4(sc, DC_AL_PAR0, *(u_int32_t *)(&sc->arpcom.ac_enaddr[0])); 1159 CSR_WRITE_4(sc, DC_AL_PAR1, *(u_int32_t *)(&sc->arpcom.ac_enaddr[4])); 1160 1161 /* If we want promiscuous mode, set the allframes bit. */ 1162 if (ifp->if_flags & IFF_PROMISC) 1163 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC); 1164 else 1165 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC); 1166 1167 if (ifp->if_flags & IFF_ALLMULTI) 1168 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI); 1169 else 1170 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI); 1171 1172 /* First, zot all the existing hash bits. */ 1173 CSR_WRITE_4(sc, DC_AL_MAR0, 0); 1174 CSR_WRITE_4(sc, DC_AL_MAR1, 0); 1175 1176 /* 1177 * If we're already in promisc or allmulti mode, we 1178 * don't have to bother programming the multicast filter. 1179 */ 1180 if (ifp->if_flags & (IFF_PROMISC | IFF_ALLMULTI)) 1181 return; 1182 1183 /* Now program new ones. */ 1184 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 1185 if (ifma->ifma_addr->sa_family != AF_LINK) 1186 continue; 1187 if (DC_IS_CENTAUR(sc)) 1188 h = dc_mchash_le(sc, 1189 LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 1190 else 1191 h = dc_mchash_be( 1192 LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 1193 if (h < 32) 1194 hashes[0] |= (1 << h); 1195 else 1196 hashes[1] |= (1 << (h - 32)); 1197 } 1198 1199 CSR_WRITE_4(sc, DC_AL_MAR0, hashes[0]); 1200 CSR_WRITE_4(sc, DC_AL_MAR1, hashes[1]); 1201 } 1202 1203 static void 1204 dc_setfilt_asix(struct dc_softc *sc) 1205 { 1206 struct ifnet *ifp; 1207 struct ifmultiaddr *ifma; 1208 int h = 0; 1209 u_int32_t hashes[2] = { 0, 0 }; 1210 1211 ifp = &sc->arpcom.ac_if; 1212 1213 /* Init our MAC address */ 1214 CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_PAR0); 1215 CSR_WRITE_4(sc, DC_AX_FILTDATA, 1216 *(u_int32_t *)(&sc->arpcom.ac_enaddr[0])); 1217 CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_PAR1); 1218 CSR_WRITE_4(sc, DC_AX_FILTDATA, 1219 *(u_int32_t *)(&sc->arpcom.ac_enaddr[4])); 1220 1221 /* If we want promiscuous mode, set the allframes bit. */ 1222 if (ifp->if_flags & IFF_PROMISC) 1223 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC); 1224 else 1225 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC); 1226 1227 if (ifp->if_flags & IFF_ALLMULTI) 1228 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI); 1229 else 1230 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI); 1231 1232 /* 1233 * The ASIX chip has a special bit to enable reception 1234 * of broadcast frames. 1235 */ 1236 if (ifp->if_flags & IFF_BROADCAST) 1237 DC_SETBIT(sc, DC_NETCFG, DC_AX_NETCFG_RX_BROAD); 1238 else 1239 DC_CLRBIT(sc, DC_NETCFG, DC_AX_NETCFG_RX_BROAD); 1240 1241 /* first, zot all the existing hash bits */ 1242 CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_MAR0); 1243 CSR_WRITE_4(sc, DC_AX_FILTDATA, 0); 1244 CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_MAR1); 1245 CSR_WRITE_4(sc, DC_AX_FILTDATA, 0); 1246 1247 /* 1248 * If we're already in promisc or allmulti mode, we 1249 * don't have to bother programming the multicast filter. 1250 */ 1251 if (ifp->if_flags & (IFF_PROMISC | IFF_ALLMULTI)) 1252 return; 1253 1254 /* now program new ones */ 1255 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 1256 if (ifma->ifma_addr->sa_family != AF_LINK) 1257 continue; 1258 h = dc_mchash_be(LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 1259 if (h < 32) 1260 hashes[0] |= (1 << h); 1261 else 1262 hashes[1] |= (1 << (h - 32)); 1263 } 1264 1265 CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_MAR0); 1266 CSR_WRITE_4(sc, DC_AX_FILTDATA, hashes[0]); 1267 CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_MAR1); 1268 CSR_WRITE_4(sc, DC_AX_FILTDATA, hashes[1]); 1269 } 1270 1271 static void 1272 dc_setfilt_xircom(struct dc_softc *sc) 1273 { 1274 struct ifnet *ifp; 1275 struct ifmultiaddr *ifma; 1276 struct dc_desc *sframe; 1277 u_int32_t h, *sp; 1278 int i; 1279 1280 ifp = &sc->arpcom.ac_if; 1281 DC_CLRBIT(sc, DC_NETCFG, (DC_NETCFG_TX_ON | DC_NETCFG_RX_ON)); 1282 1283 i = sc->dc_cdata.dc_tx_prod; 1284 DC_INC(sc->dc_cdata.dc_tx_prod, DC_TX_LIST_CNT); 1285 sc->dc_cdata.dc_tx_cnt++; 1286 sframe = &sc->dc_ldata->dc_tx_list[i]; 1287 sp = sc->dc_cdata.dc_sbuf; 1288 bzero(sp, DC_SFRAME_LEN); 1289 1290 sframe->dc_data = htole32(sc->dc_saddr); 1291 sframe->dc_ctl = htole32(DC_SFRAME_LEN | DC_TXCTL_SETUP | 1292 DC_TXCTL_TLINK | DC_FILTER_HASHPERF | DC_TXCTL_FINT); 1293 1294 sc->dc_cdata.dc_tx_chain[i] = (struct mbuf *)sc->dc_cdata.dc_sbuf; 1295 1296 /* If we want promiscuous mode, set the allframes bit. */ 1297 if (ifp->if_flags & IFF_PROMISC) 1298 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC); 1299 else 1300 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC); 1301 1302 if (ifp->if_flags & IFF_ALLMULTI) 1303 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI); 1304 else 1305 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI); 1306 1307 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 1308 if (ifma->ifma_addr->sa_family != AF_LINK) 1309 continue; 1310 h = dc_mchash_le(sc, 1311 LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 1312 sp[h >> 4] |= htole32(1 << (h & 0xF)); 1313 } 1314 1315 if (ifp->if_flags & IFF_BROADCAST) { 1316 h = dc_mchash_le(sc, ifp->if_broadcastaddr); 1317 sp[h >> 4] |= htole32(1 << (h & 0xF)); 1318 } 1319 1320 /* Set our MAC address */ 1321 sp[0] = DC_SP_MAC(((u_int16_t *)sc->arpcom.ac_enaddr)[0]); 1322 sp[1] = DC_SP_MAC(((u_int16_t *)sc->arpcom.ac_enaddr)[1]); 1323 sp[2] = DC_SP_MAC(((u_int16_t *)sc->arpcom.ac_enaddr)[2]); 1324 1325 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_TX_ON); 1326 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_ON); 1327 ifp->if_flags |= IFF_RUNNING; 1328 sframe->dc_status = htole32(DC_TXSTAT_OWN); 1329 CSR_WRITE_4(sc, DC_TXSTART, 0xFFFFFFFF); 1330 1331 /* 1332 * Wait some time... 1333 */ 1334 DELAY(1000); 1335 1336 ifp->if_timer = 5; 1337 } 1338 1339 static void 1340 dc_setfilt(struct dc_softc *sc) 1341 { 1342 1343 if (DC_IS_INTEL(sc) || DC_IS_MACRONIX(sc) || DC_IS_PNIC(sc) || 1344 DC_IS_PNICII(sc) || DC_IS_DAVICOM(sc) || DC_IS_CONEXANT(sc)) 1345 dc_setfilt_21143(sc); 1346 1347 if (DC_IS_ASIX(sc)) 1348 dc_setfilt_asix(sc); 1349 1350 if (DC_IS_ADMTEK(sc)) 1351 dc_setfilt_admtek(sc); 1352 1353 if (DC_IS_XIRCOM(sc)) 1354 dc_setfilt_xircom(sc); 1355 } 1356 1357 /* 1358 * In order to fiddle with the 'full-duplex' and '100Mbps' bits in 1359 * the netconfig register, we first have to put the transmit and/or 1360 * receive logic in the idle state. 1361 */ 1362 static void 1363 dc_setcfg(struct dc_softc *sc, int media) 1364 { 1365 int i, restart = 0, watchdogreg; 1366 u_int32_t isr; 1367 1368 if (IFM_SUBTYPE(media) == IFM_NONE) 1369 return; 1370 1371 if (CSR_READ_4(sc, DC_NETCFG) & (DC_NETCFG_TX_ON | DC_NETCFG_RX_ON)) { 1372 restart = 1; 1373 DC_CLRBIT(sc, DC_NETCFG, (DC_NETCFG_TX_ON | DC_NETCFG_RX_ON)); 1374 1375 for (i = 0; i < DC_TIMEOUT; i++) { 1376 isr = CSR_READ_4(sc, DC_ISR); 1377 if (isr & DC_ISR_TX_IDLE && 1378 ((isr & DC_ISR_RX_STATE) == DC_RXSTATE_STOPPED || 1379 (isr & DC_ISR_RX_STATE) == DC_RXSTATE_WAIT)) 1380 break; 1381 DELAY(10); 1382 } 1383 1384 if (i == DC_TIMEOUT) 1385 printf("dc%d: failed to force tx and " 1386 "rx to idle state\n", sc->dc_unit); 1387 } 1388 1389 if (IFM_SUBTYPE(media) == IFM_100_TX) { 1390 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_SPEEDSEL); 1391 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_HEARTBEAT); 1392 if (sc->dc_pmode == DC_PMODE_MII) { 1393 if (DC_IS_INTEL(sc)) { 1394 /* There's a write enable bit here that reads as 1. */ 1395 watchdogreg = CSR_READ_4(sc, DC_WATCHDOG); 1396 watchdogreg &= ~DC_WDOG_CTLWREN; 1397 watchdogreg |= DC_WDOG_JABBERDIS; 1398 CSR_WRITE_4(sc, DC_WATCHDOG, watchdogreg); 1399 } else { 1400 DC_SETBIT(sc, DC_WATCHDOG, DC_WDOG_JABBERDIS); 1401 } 1402 DC_CLRBIT(sc, DC_NETCFG, (DC_NETCFG_PCS | 1403 DC_NETCFG_PORTSEL | DC_NETCFG_SCRAMBLER)); 1404 if (sc->dc_type == DC_TYPE_98713) 1405 DC_SETBIT(sc, DC_NETCFG, (DC_NETCFG_PCS | 1406 DC_NETCFG_SCRAMBLER)); 1407 if (!DC_IS_DAVICOM(sc)) 1408 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL); 1409 DC_CLRBIT(sc, DC_10BTCTRL, 0xFFFF); 1410 if (DC_IS_INTEL(sc)) 1411 dc_apply_fixup(sc, IFM_AUTO); 1412 } else { 1413 if (DC_IS_PNIC(sc)) { 1414 DC_PN_GPIO_SETBIT(sc, DC_PN_GPIO_SPEEDSEL); 1415 DC_PN_GPIO_SETBIT(sc, DC_PN_GPIO_100TX_LOOP); 1416 DC_SETBIT(sc, DC_PN_NWAY, DC_PN_NWAY_SPEEDSEL); 1417 } 1418 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL); 1419 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PCS); 1420 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_SCRAMBLER); 1421 if (DC_IS_INTEL(sc)) 1422 dc_apply_fixup(sc, 1423 (media & IFM_GMASK) == IFM_FDX ? 1424 IFM_100_TX | IFM_FDX : IFM_100_TX); 1425 } 1426 } 1427 1428 if (IFM_SUBTYPE(media) == IFM_10_T) { 1429 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_SPEEDSEL); 1430 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_HEARTBEAT); 1431 if (sc->dc_pmode == DC_PMODE_MII) { 1432 /* There's a write enable bit here that reads as 1. */ 1433 if (DC_IS_INTEL(sc)) { 1434 watchdogreg = CSR_READ_4(sc, DC_WATCHDOG); 1435 watchdogreg &= ~DC_WDOG_CTLWREN; 1436 watchdogreg |= DC_WDOG_JABBERDIS; 1437 CSR_WRITE_4(sc, DC_WATCHDOG, watchdogreg); 1438 } else { 1439 DC_SETBIT(sc, DC_WATCHDOG, DC_WDOG_JABBERDIS); 1440 } 1441 DC_CLRBIT(sc, DC_NETCFG, (DC_NETCFG_PCS | 1442 DC_NETCFG_PORTSEL | DC_NETCFG_SCRAMBLER)); 1443 if (sc->dc_type == DC_TYPE_98713) 1444 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PCS); 1445 if (!DC_IS_DAVICOM(sc)) 1446 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL); 1447 DC_CLRBIT(sc, DC_10BTCTRL, 0xFFFF); 1448 if (DC_IS_INTEL(sc)) 1449 dc_apply_fixup(sc, IFM_AUTO); 1450 } else { 1451 if (DC_IS_PNIC(sc)) { 1452 DC_PN_GPIO_CLRBIT(sc, DC_PN_GPIO_SPEEDSEL); 1453 DC_PN_GPIO_SETBIT(sc, DC_PN_GPIO_100TX_LOOP); 1454 DC_CLRBIT(sc, DC_PN_NWAY, DC_PN_NWAY_SPEEDSEL); 1455 } 1456 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL); 1457 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_PCS); 1458 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_SCRAMBLER); 1459 if (DC_IS_INTEL(sc)) { 1460 DC_CLRBIT(sc, DC_SIARESET, DC_SIA_RESET); 1461 DC_CLRBIT(sc, DC_10BTCTRL, 0xFFFF); 1462 if ((media & IFM_GMASK) == IFM_FDX) 1463 DC_SETBIT(sc, DC_10BTCTRL, 0x7F3D); 1464 else 1465 DC_SETBIT(sc, DC_10BTCTRL, 0x7F3F); 1466 DC_SETBIT(sc, DC_SIARESET, DC_SIA_RESET); 1467 DC_CLRBIT(sc, DC_10BTCTRL, 1468 DC_TCTL_AUTONEGENBL); 1469 dc_apply_fixup(sc, 1470 (media & IFM_GMASK) == IFM_FDX ? 1471 IFM_10_T | IFM_FDX : IFM_10_T); 1472 DELAY(20000); 1473 } 1474 } 1475 } 1476 1477 /* 1478 * If this is a Davicom DM9102A card with a DM9801 HomePNA 1479 * PHY and we want HomePNA mode, set the portsel bit to turn 1480 * on the external MII port. 1481 */ 1482 if (DC_IS_DAVICOM(sc)) { 1483 if (IFM_SUBTYPE(media) == IFM_HPNA_1) { 1484 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL); 1485 sc->dc_link = 1; 1486 } else { 1487 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL); 1488 } 1489 } 1490 1491 if ((media & IFM_GMASK) == IFM_FDX) { 1492 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_FULLDUPLEX); 1493 if (sc->dc_pmode == DC_PMODE_SYM && DC_IS_PNIC(sc)) 1494 DC_SETBIT(sc, DC_PN_NWAY, DC_PN_NWAY_DUPLEX); 1495 } else { 1496 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_FULLDUPLEX); 1497 if (sc->dc_pmode == DC_PMODE_SYM && DC_IS_PNIC(sc)) 1498 DC_CLRBIT(sc, DC_PN_NWAY, DC_PN_NWAY_DUPLEX); 1499 } 1500 1501 if (restart) 1502 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_TX_ON | DC_NETCFG_RX_ON); 1503 } 1504 1505 static void 1506 dc_reset(struct dc_softc *sc) 1507 { 1508 int i; 1509 1510 DC_SETBIT(sc, DC_BUSCTL, DC_BUSCTL_RESET); 1511 1512 for (i = 0; i < DC_TIMEOUT; i++) { 1513 DELAY(10); 1514 if (!(CSR_READ_4(sc, DC_BUSCTL) & DC_BUSCTL_RESET)) 1515 break; 1516 } 1517 1518 if (DC_IS_ASIX(sc) || DC_IS_ADMTEK(sc) || DC_IS_CONEXANT(sc) || 1519 DC_IS_XIRCOM(sc) || DC_IS_INTEL(sc)) { 1520 DELAY(10000); 1521 DC_CLRBIT(sc, DC_BUSCTL, DC_BUSCTL_RESET); 1522 i = 0; 1523 } 1524 1525 if (i == DC_TIMEOUT) 1526 printf("dc%d: reset never completed!\n", sc->dc_unit); 1527 1528 /* Wait a little while for the chip to get its brains in order. */ 1529 DELAY(1000); 1530 1531 CSR_WRITE_4(sc, DC_IMR, 0x00000000); 1532 CSR_WRITE_4(sc, DC_BUSCTL, 0x00000000); 1533 CSR_WRITE_4(sc, DC_NETCFG, 0x00000000); 1534 1535 /* 1536 * Bring the SIA out of reset. In some cases, it looks 1537 * like failing to unreset the SIA soon enough gets it 1538 * into a state where it will never come out of reset 1539 * until we reset the whole chip again. 1540 */ 1541 if (DC_IS_INTEL(sc)) { 1542 DC_SETBIT(sc, DC_SIARESET, DC_SIA_RESET); 1543 CSR_WRITE_4(sc, DC_10BTCTRL, 0); 1544 CSR_WRITE_4(sc, DC_WATCHDOG, 0); 1545 } 1546 } 1547 1548 static struct dc_type * 1549 dc_devtype(device_t dev) 1550 { 1551 struct dc_type *t; 1552 u_int32_t rev; 1553 1554 t = dc_devs; 1555 1556 while (t->dc_name != NULL) { 1557 if ((pci_get_vendor(dev) == t->dc_vid) && 1558 (pci_get_device(dev) == t->dc_did)) { 1559 /* Check the PCI revision */ 1560 rev = pci_read_config(dev, DC_PCI_CFRV, 4) & 0xFF; 1561 if (t->dc_did == DC_DEVICEID_98713 && 1562 rev >= DC_REVISION_98713A) 1563 t++; 1564 if (t->dc_did == DC_DEVICEID_98713_CP && 1565 rev >= DC_REVISION_98713A) 1566 t++; 1567 if (t->dc_did == DC_DEVICEID_987x5 && 1568 rev >= DC_REVISION_98715AEC_C) 1569 t++; 1570 if (t->dc_did == DC_DEVICEID_987x5 && 1571 rev >= DC_REVISION_98725) 1572 t++; 1573 if (t->dc_did == DC_DEVICEID_AX88140A && 1574 rev >= DC_REVISION_88141) 1575 t++; 1576 if (t->dc_did == DC_DEVICEID_82C168 && 1577 rev >= DC_REVISION_82C169) 1578 t++; 1579 if (t->dc_did == DC_DEVICEID_DM9102 && 1580 rev >= DC_REVISION_DM9102A) 1581 t++; 1582 /* 1583 * The Microsoft MN-130 has a device ID of 0x0002, 1584 * which happens to be the same as the PNIC 82c168. 1585 * To keep dc_attach() from getting confused, we 1586 * pretend its ID is something different. 1587 * XXX: ideally, dc_attach() should be checking 1588 * vendorid+deviceid together to avoid such 1589 * collisions. 1590 */ 1591 if (t->dc_vid == DC_VENDORID_MICROSOFT && 1592 t->dc_did == DC_DEVICEID_MSMN130) 1593 t++; 1594 return (t); 1595 } 1596 t++; 1597 } 1598 1599 return (NULL); 1600 } 1601 1602 /* 1603 * Probe for a 21143 or clone chip. Check the PCI vendor and device 1604 * IDs against our list and return a device name if we find a match. 1605 * We do a little bit of extra work to identify the exact type of 1606 * chip. The MX98713 and MX98713A have the same PCI vendor/device ID, 1607 * but different revision IDs. The same is true for 98715/98715A 1608 * chips and the 98725, as well as the ASIX and ADMtek chips. In some 1609 * cases, the exact chip revision affects driver behavior. 1610 */ 1611 static int 1612 dc_probe(device_t dev) 1613 { 1614 struct dc_type *t; 1615 1616 t = dc_devtype(dev); 1617 1618 if (t != NULL) { 1619 device_set_desc(dev, t->dc_name); 1620 return (BUS_PROBE_DEFAULT); 1621 } 1622 1623 return (ENXIO); 1624 } 1625 1626 static void 1627 dc_apply_fixup(struct dc_softc *sc, int media) 1628 { 1629 struct dc_mediainfo *m; 1630 u_int8_t *p; 1631 int i; 1632 u_int32_t reg; 1633 1634 m = sc->dc_mi; 1635 1636 while (m != NULL) { 1637 if (m->dc_media == media) 1638 break; 1639 m = m->dc_next; 1640 } 1641 1642 if (m == NULL) 1643 return; 1644 1645 for (i = 0, p = m->dc_reset_ptr; i < m->dc_reset_len; i++, p += 2) { 1646 reg = (p[0] | (p[1] << 8)) << 16; 1647 CSR_WRITE_4(sc, DC_WATCHDOG, reg); 1648 } 1649 1650 for (i = 0, p = m->dc_gp_ptr; i < m->dc_gp_len; i++, p += 2) { 1651 reg = (p[0] | (p[1] << 8)) << 16; 1652 CSR_WRITE_4(sc, DC_WATCHDOG, reg); 1653 } 1654 } 1655 1656 static void 1657 dc_decode_leaf_sia(struct dc_softc *sc, struct dc_eblock_sia *l) 1658 { 1659 struct dc_mediainfo *m; 1660 1661 m = malloc(sizeof(struct dc_mediainfo), M_DEVBUF, M_NOWAIT | M_ZERO); 1662 switch (l->dc_sia_code & ~DC_SIA_CODE_EXT) { 1663 case DC_SIA_CODE_10BT: 1664 m->dc_media = IFM_10_T; 1665 break; 1666 case DC_SIA_CODE_10BT_FDX: 1667 m->dc_media = IFM_10_T | IFM_FDX; 1668 break; 1669 case DC_SIA_CODE_10B2: 1670 m->dc_media = IFM_10_2; 1671 break; 1672 case DC_SIA_CODE_10B5: 1673 m->dc_media = IFM_10_5; 1674 break; 1675 default: 1676 break; 1677 } 1678 1679 /* 1680 * We need to ignore CSR13, CSR14, CSR15 for SIA mode. 1681 * Things apparently already work for cards that do 1682 * supply Media Specific Data. 1683 */ 1684 if (l->dc_sia_code & DC_SIA_CODE_EXT) { 1685 m->dc_gp_len = 2; 1686 m->dc_gp_ptr = 1687 (u_int8_t *)&l->dc_un.dc_sia_ext.dc_sia_gpio_ctl; 1688 } else { 1689 m->dc_gp_len = 2; 1690 m->dc_gp_ptr = 1691 (u_int8_t *)&l->dc_un.dc_sia_noext.dc_sia_gpio_ctl; 1692 } 1693 1694 m->dc_next = sc->dc_mi; 1695 sc->dc_mi = m; 1696 1697 sc->dc_pmode = DC_PMODE_SIA; 1698 } 1699 1700 static void 1701 dc_decode_leaf_sym(struct dc_softc *sc, struct dc_eblock_sym *l) 1702 { 1703 struct dc_mediainfo *m; 1704 1705 m = malloc(sizeof(struct dc_mediainfo), M_DEVBUF, M_NOWAIT | M_ZERO); 1706 if (l->dc_sym_code == DC_SYM_CODE_100BT) 1707 m->dc_media = IFM_100_TX; 1708 1709 if (l->dc_sym_code == DC_SYM_CODE_100BT_FDX) 1710 m->dc_media = IFM_100_TX | IFM_FDX; 1711 1712 m->dc_gp_len = 2; 1713 m->dc_gp_ptr = (u_int8_t *)&l->dc_sym_gpio_ctl; 1714 1715 m->dc_next = sc->dc_mi; 1716 sc->dc_mi = m; 1717 1718 sc->dc_pmode = DC_PMODE_SYM; 1719 } 1720 1721 static void 1722 dc_decode_leaf_mii(struct dc_softc *sc, struct dc_eblock_mii *l) 1723 { 1724 struct dc_mediainfo *m; 1725 u_int8_t *p; 1726 1727 m = malloc(sizeof(struct dc_mediainfo), M_DEVBUF, M_NOWAIT | M_ZERO); 1728 /* We abuse IFM_AUTO to represent MII. */ 1729 m->dc_media = IFM_AUTO; 1730 m->dc_gp_len = l->dc_gpr_len; 1731 1732 p = (u_int8_t *)l; 1733 p += sizeof(struct dc_eblock_mii); 1734 m->dc_gp_ptr = p; 1735 p += 2 * l->dc_gpr_len; 1736 m->dc_reset_len = *p; 1737 p++; 1738 m->dc_reset_ptr = p; 1739 1740 m->dc_next = sc->dc_mi; 1741 sc->dc_mi = m; 1742 } 1743 1744 static void 1745 dc_read_srom(struct dc_softc *sc, int bits) 1746 { 1747 int size; 1748 1749 size = 2 << bits; 1750 sc->dc_srom = malloc(size, M_DEVBUF, M_NOWAIT); 1751 dc_read_eeprom(sc, (caddr_t)sc->dc_srom, 0, (size / 2), 0); 1752 } 1753 1754 static void 1755 dc_parse_21143_srom(struct dc_softc *sc) 1756 { 1757 struct dc_leaf_hdr *lhdr; 1758 struct dc_eblock_hdr *hdr; 1759 int have_mii, i, loff; 1760 char *ptr; 1761 1762 have_mii = 0; 1763 loff = sc->dc_srom[27]; 1764 lhdr = (struct dc_leaf_hdr *)&(sc->dc_srom[loff]); 1765 1766 ptr = (char *)lhdr; 1767 ptr += sizeof(struct dc_leaf_hdr) - 1; 1768 /* 1769 * Look if we got a MII media block. 1770 */ 1771 for (i = 0; i < lhdr->dc_mcnt; i++) { 1772 hdr = (struct dc_eblock_hdr *)ptr; 1773 if (hdr->dc_type == DC_EBLOCK_MII) 1774 have_mii++; 1775 1776 ptr += (hdr->dc_len & 0x7F); 1777 ptr++; 1778 } 1779 1780 /* 1781 * Do the same thing again. Only use SIA and SYM media 1782 * blocks if no MII media block is available. 1783 */ 1784 ptr = (char *)lhdr; 1785 ptr += sizeof(struct dc_leaf_hdr) - 1; 1786 for (i = 0; i < lhdr->dc_mcnt; i++) { 1787 hdr = (struct dc_eblock_hdr *)ptr; 1788 switch (hdr->dc_type) { 1789 case DC_EBLOCK_MII: 1790 dc_decode_leaf_mii(sc, (struct dc_eblock_mii *)hdr); 1791 break; 1792 case DC_EBLOCK_SIA: 1793 if (! have_mii) 1794 dc_decode_leaf_sia(sc, 1795 (struct dc_eblock_sia *)hdr); 1796 break; 1797 case DC_EBLOCK_SYM: 1798 if (! have_mii) 1799 dc_decode_leaf_sym(sc, 1800 (struct dc_eblock_sym *)hdr); 1801 break; 1802 default: 1803 /* Don't care. Yet. */ 1804 break; 1805 } 1806 ptr += (hdr->dc_len & 0x7F); 1807 ptr++; 1808 } 1809 } 1810 1811 static void 1812 dc_dma_map_addr(void *arg, bus_dma_segment_t *segs, int nseg, int error) 1813 { 1814 u_int32_t *paddr; 1815 1816 KASSERT(nseg == 1, ("wrong number of segments, should be 1")); 1817 paddr = arg; 1818 *paddr = segs->ds_addr; 1819 } 1820 1821 /* 1822 * Attach the interface. Allocate softc structures, do ifmedia 1823 * setup and ethernet/BPF attach. 1824 */ 1825 static int 1826 dc_attach(device_t dev) 1827 { 1828 int tmp = 0; 1829 u_char eaddr[ETHER_ADDR_LEN]; 1830 u_int32_t command; 1831 struct dc_softc *sc; 1832 struct ifnet *ifp; 1833 u_int32_t revision; 1834 int unit, error = 0, rid, mac_offset; 1835 int i; 1836 u_int8_t *mac; 1837 1838 sc = device_get_softc(dev); 1839 unit = device_get_unit(dev); 1840 1841 mtx_init(&sc->dc_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 1842 MTX_DEF | MTX_RECURSE); 1843 1844 /* 1845 * Map control/status registers. 1846 */ 1847 pci_enable_busmaster(dev); 1848 1849 rid = DC_RID; 1850 sc->dc_res = bus_alloc_resource_any(dev, DC_RES, &rid, RF_ACTIVE); 1851 1852 if (sc->dc_res == NULL) { 1853 printf("dc%d: couldn't map ports/memory\n", unit); 1854 error = ENXIO; 1855 goto fail; 1856 } 1857 1858 sc->dc_btag = rman_get_bustag(sc->dc_res); 1859 sc->dc_bhandle = rman_get_bushandle(sc->dc_res); 1860 1861 /* Allocate interrupt. */ 1862 rid = 0; 1863 sc->dc_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 1864 RF_SHAREABLE | RF_ACTIVE); 1865 1866 if (sc->dc_irq == NULL) { 1867 printf("dc%d: couldn't map interrupt\n", unit); 1868 error = ENXIO; 1869 goto fail; 1870 } 1871 1872 /* Need this info to decide on a chip type. */ 1873 sc->dc_info = dc_devtype(dev); 1874 revision = pci_read_config(dev, DC_PCI_CFRV, 4) & 0x000000FF; 1875 1876 /* Get the eeprom width, but PNIC and XIRCOM have diff eeprom */ 1877 if (sc->dc_info->dc_did != DC_DEVICEID_82C168 && 1878 sc->dc_info->dc_did != DC_DEVICEID_X3201) 1879 dc_eeprom_width(sc); 1880 1881 switch (sc->dc_info->dc_did) { 1882 case DC_DEVICEID_21143: 1883 sc->dc_type = DC_TYPE_21143; 1884 sc->dc_flags |= DC_TX_POLL | DC_TX_USE_TX_INTR; 1885 sc->dc_flags |= DC_REDUCED_MII_POLL; 1886 /* Save EEPROM contents so we can parse them later. */ 1887 dc_read_srom(sc, sc->dc_romwidth); 1888 break; 1889 case DC_DEVICEID_DM9009: 1890 case DC_DEVICEID_DM9100: 1891 case DC_DEVICEID_DM9102: 1892 sc->dc_type = DC_TYPE_DM9102; 1893 sc->dc_flags |= DC_TX_COALESCE | DC_TX_INTR_ALWAYS; 1894 sc->dc_flags |= DC_REDUCED_MII_POLL | DC_TX_STORENFWD; 1895 sc->dc_flags |= DC_TX_ALIGN; 1896 sc->dc_pmode = DC_PMODE_MII; 1897 /* Increase the latency timer value. */ 1898 command = pci_read_config(dev, DC_PCI_CFLT, 4); 1899 command &= 0xFFFF00FF; 1900 command |= 0x00008000; 1901 pci_write_config(dev, DC_PCI_CFLT, command, 4); 1902 break; 1903 case DC_DEVICEID_AL981: 1904 sc->dc_type = DC_TYPE_AL981; 1905 sc->dc_flags |= DC_TX_USE_TX_INTR; 1906 sc->dc_flags |= DC_TX_ADMTEK_WAR; 1907 sc->dc_pmode = DC_PMODE_MII; 1908 dc_read_srom(sc, sc->dc_romwidth); 1909 break; 1910 case DC_DEVICEID_AN985: 1911 case DC_DEVICEID_ADM9511: 1912 case DC_DEVICEID_ADM9513: 1913 case DC_DEVICEID_FA511: 1914 case DC_DEVICEID_FE2500: 1915 case DC_DEVICEID_EN2242: 1916 case DC_DEVICEID_HAWKING_PN672TX: 1917 case DC_DEVICEID_3CSOHOB: 1918 case DC_DEVICEID_MSMN120: 1919 case DC_DEVICEID_MSMN130_FAKE: /* XXX avoid collision with PNIC*/ 1920 sc->dc_type = DC_TYPE_AN985; 1921 sc->dc_flags |= DC_64BIT_HASH; 1922 sc->dc_flags |= DC_TX_USE_TX_INTR; 1923 sc->dc_flags |= DC_TX_ADMTEK_WAR; 1924 sc->dc_pmode = DC_PMODE_MII; 1925 /* Don't read SROM for - auto-loaded on reset */ 1926 break; 1927 case DC_DEVICEID_98713: 1928 case DC_DEVICEID_98713_CP: 1929 if (revision < DC_REVISION_98713A) { 1930 sc->dc_type = DC_TYPE_98713; 1931 } 1932 if (revision >= DC_REVISION_98713A) { 1933 sc->dc_type = DC_TYPE_98713A; 1934 sc->dc_flags |= DC_21143_NWAY; 1935 } 1936 sc->dc_flags |= DC_REDUCED_MII_POLL; 1937 sc->dc_flags |= DC_TX_POLL | DC_TX_USE_TX_INTR; 1938 break; 1939 case DC_DEVICEID_987x5: 1940 case DC_DEVICEID_EN1217: 1941 /* 1942 * Macronix MX98715AEC-C/D/E parts have only a 1943 * 128-bit hash table. We need to deal with these 1944 * in the same manner as the PNIC II so that we 1945 * get the right number of bits out of the 1946 * CRC routine. 1947 */ 1948 if (revision >= DC_REVISION_98715AEC_C && 1949 revision < DC_REVISION_98725) 1950 sc->dc_flags |= DC_128BIT_HASH; 1951 sc->dc_type = DC_TYPE_987x5; 1952 sc->dc_flags |= DC_TX_POLL | DC_TX_USE_TX_INTR; 1953 sc->dc_flags |= DC_REDUCED_MII_POLL | DC_21143_NWAY; 1954 break; 1955 case DC_DEVICEID_98727: 1956 sc->dc_type = DC_TYPE_987x5; 1957 sc->dc_flags |= DC_TX_POLL | DC_TX_USE_TX_INTR; 1958 sc->dc_flags |= DC_REDUCED_MII_POLL | DC_21143_NWAY; 1959 break; 1960 case DC_DEVICEID_82C115: 1961 sc->dc_type = DC_TYPE_PNICII; 1962 sc->dc_flags |= DC_TX_POLL | DC_TX_USE_TX_INTR | DC_128BIT_HASH; 1963 sc->dc_flags |= DC_REDUCED_MII_POLL | DC_21143_NWAY; 1964 break; 1965 case DC_DEVICEID_82C168: 1966 sc->dc_type = DC_TYPE_PNIC; 1967 sc->dc_flags |= DC_TX_STORENFWD | DC_TX_INTR_ALWAYS; 1968 sc->dc_flags |= DC_PNIC_RX_BUG_WAR; 1969 sc->dc_pnic_rx_buf = malloc(DC_RXLEN * 5, M_DEVBUF, M_NOWAIT); 1970 if (revision < DC_REVISION_82C169) 1971 sc->dc_pmode = DC_PMODE_SYM; 1972 break; 1973 case DC_DEVICEID_AX88140A: 1974 sc->dc_type = DC_TYPE_ASIX; 1975 sc->dc_flags |= DC_TX_USE_TX_INTR | DC_TX_INTR_FIRSTFRAG; 1976 sc->dc_flags |= DC_REDUCED_MII_POLL; 1977 sc->dc_pmode = DC_PMODE_MII; 1978 break; 1979 case DC_DEVICEID_X3201: 1980 sc->dc_type = DC_TYPE_XIRCOM; 1981 sc->dc_flags |= DC_TX_INTR_ALWAYS | DC_TX_COALESCE | 1982 DC_TX_ALIGN; 1983 /* 1984 * We don't actually need to coalesce, but we're doing 1985 * it to obtain a double word aligned buffer. 1986 * The DC_TX_COALESCE flag is required. 1987 */ 1988 sc->dc_pmode = DC_PMODE_MII; 1989 break; 1990 case DC_DEVICEID_RS7112: 1991 sc->dc_type = DC_TYPE_CONEXANT; 1992 sc->dc_flags |= DC_TX_INTR_ALWAYS; 1993 sc->dc_flags |= DC_REDUCED_MII_POLL; 1994 sc->dc_pmode = DC_PMODE_MII; 1995 dc_read_srom(sc, sc->dc_romwidth); 1996 break; 1997 default: 1998 printf("dc%d: unknown device: %x\n", sc->dc_unit, 1999 sc->dc_info->dc_did); 2000 break; 2001 } 2002 2003 /* Save the cache line size. */ 2004 if (DC_IS_DAVICOM(sc)) 2005 sc->dc_cachesize = 0; 2006 else 2007 sc->dc_cachesize = pci_read_config(dev, 2008 DC_PCI_CFLT, 4) & 0xFF; 2009 2010 /* Reset the adapter. */ 2011 dc_reset(sc); 2012 2013 /* Take 21143 out of snooze mode */ 2014 if (DC_IS_INTEL(sc) || DC_IS_XIRCOM(sc)) { 2015 command = pci_read_config(dev, DC_PCI_CFDD, 4); 2016 command &= ~(DC_CFDD_SNOOZE_MODE | DC_CFDD_SLEEP_MODE); 2017 pci_write_config(dev, DC_PCI_CFDD, command, 4); 2018 } 2019 2020 /* 2021 * Try to learn something about the supported media. 2022 * We know that ASIX and ADMtek and Davicom devices 2023 * will *always* be using MII media, so that's a no-brainer. 2024 * The tricky ones are the Macronix/PNIC II and the 2025 * Intel 21143. 2026 */ 2027 if (DC_IS_INTEL(sc)) 2028 dc_parse_21143_srom(sc); 2029 else if (DC_IS_MACRONIX(sc) || DC_IS_PNICII(sc)) { 2030 if (sc->dc_type == DC_TYPE_98713) 2031 sc->dc_pmode = DC_PMODE_MII; 2032 else 2033 sc->dc_pmode = DC_PMODE_SYM; 2034 } else if (!sc->dc_pmode) 2035 sc->dc_pmode = DC_PMODE_MII; 2036 2037 /* 2038 * Get station address from the EEPROM. 2039 */ 2040 switch(sc->dc_type) { 2041 case DC_TYPE_98713: 2042 case DC_TYPE_98713A: 2043 case DC_TYPE_987x5: 2044 case DC_TYPE_PNICII: 2045 dc_read_eeprom(sc, (caddr_t)&mac_offset, 2046 (DC_EE_NODEADDR_OFFSET / 2), 1, 0); 2047 dc_read_eeprom(sc, (caddr_t)&eaddr, (mac_offset / 2), 3, 0); 2048 break; 2049 case DC_TYPE_PNIC: 2050 dc_read_eeprom(sc, (caddr_t)&eaddr, 0, 3, 1); 2051 break; 2052 case DC_TYPE_DM9102: 2053 dc_read_eeprom(sc, (caddr_t)&eaddr, DC_EE_NODEADDR, 3, 0); 2054 #ifdef __sparc64__ 2055 /* 2056 * If this is an onboard dc(4) the station address read from 2057 * the EEPROM is all zero and we have to get it from the fcode. 2058 */ 2059 for (i = 0; i < ETHER_ADDR_LEN; i++) 2060 if (eaddr[i] != 0x00) 2061 break; 2062 if (i >= ETHER_ADDR_LEN) 2063 OF_getetheraddr(dev, eaddr); 2064 #endif 2065 break; 2066 case DC_TYPE_21143: 2067 case DC_TYPE_ASIX: 2068 dc_read_eeprom(sc, (caddr_t)&eaddr, DC_EE_NODEADDR, 3, 0); 2069 break; 2070 case DC_TYPE_AL981: 2071 case DC_TYPE_AN985: 2072 *(u_int32_t *)(&eaddr[0]) = CSR_READ_4(sc, DC_AL_PAR0); 2073 *(u_int16_t *)(&eaddr[4]) = CSR_READ_4(sc, DC_AL_PAR1); 2074 break; 2075 case DC_TYPE_CONEXANT: 2076 bcopy(sc->dc_srom + DC_CONEXANT_EE_NODEADDR, &eaddr, 2077 ETHER_ADDR_LEN); 2078 break; 2079 case DC_TYPE_XIRCOM: 2080 /* The MAC comes from the CIS. */ 2081 mac = pci_get_ether(dev); 2082 if (!mac) { 2083 device_printf(dev, "No station address in CIS!\n"); 2084 error = ENXIO; 2085 goto fail; 2086 } 2087 bcopy(mac, eaddr, ETHER_ADDR_LEN); 2088 break; 2089 default: 2090 dc_read_eeprom(sc, (caddr_t)&eaddr, DC_EE_NODEADDR, 3, 0); 2091 break; 2092 } 2093 2094 sc->dc_unit = unit; 2095 bcopy(eaddr, &sc->arpcom.ac_enaddr, ETHER_ADDR_LEN); 2096 2097 /* Allocate a busdma tag and DMA safe memory for TX/RX descriptors. */ 2098 error = bus_dma_tag_create(NULL, PAGE_SIZE, 0, BUS_SPACE_MAXADDR_32BIT, 2099 BUS_SPACE_MAXADDR, NULL, NULL, sizeof(struct dc_list_data), 1, 2100 sizeof(struct dc_list_data), 0, NULL, NULL, &sc->dc_ltag); 2101 if (error) { 2102 printf("dc%d: failed to allocate busdma tag\n", unit); 2103 error = ENXIO; 2104 goto fail; 2105 } 2106 error = bus_dmamem_alloc(sc->dc_ltag, (void **)&sc->dc_ldata, 2107 BUS_DMA_NOWAIT | BUS_DMA_ZERO, &sc->dc_lmap); 2108 if (error) { 2109 printf("dc%d: failed to allocate DMA safe memory\n", unit); 2110 error = ENXIO; 2111 goto fail; 2112 } 2113 error = bus_dmamap_load(sc->dc_ltag, sc->dc_lmap, sc->dc_ldata, 2114 sizeof(struct dc_list_data), dc_dma_map_addr, &sc->dc_laddr, 2115 BUS_DMA_NOWAIT); 2116 if (error) { 2117 printf("dc%d: cannot get address of the descriptors\n", unit); 2118 error = ENXIO; 2119 goto fail; 2120 } 2121 2122 /* 2123 * Allocate a busdma tag and DMA safe memory for the multicast 2124 * setup frame. 2125 */ 2126 error = bus_dma_tag_create(NULL, PAGE_SIZE, 0, BUS_SPACE_MAXADDR_32BIT, 2127 BUS_SPACE_MAXADDR, NULL, NULL, DC_SFRAME_LEN + DC_MIN_FRAMELEN, 1, 2128 DC_SFRAME_LEN + DC_MIN_FRAMELEN, 0, NULL, NULL, &sc->dc_stag); 2129 if (error) { 2130 printf("dc%d: failed to allocate busdma tag\n", unit); 2131 error = ENXIO; 2132 goto fail; 2133 } 2134 error = bus_dmamem_alloc(sc->dc_stag, (void **)&sc->dc_cdata.dc_sbuf, 2135 BUS_DMA_NOWAIT, &sc->dc_smap); 2136 if (error) { 2137 printf("dc%d: failed to allocate DMA safe memory\n", unit); 2138 error = ENXIO; 2139 goto fail; 2140 } 2141 error = bus_dmamap_load(sc->dc_stag, sc->dc_smap, sc->dc_cdata.dc_sbuf, 2142 DC_SFRAME_LEN, dc_dma_map_addr, &sc->dc_saddr, BUS_DMA_NOWAIT); 2143 if (error) { 2144 printf("dc%d: cannot get address of the descriptors\n", unit); 2145 error = ENXIO; 2146 goto fail; 2147 } 2148 2149 /* Allocate a busdma tag for mbufs. */ 2150 error = bus_dma_tag_create(NULL, 1, 0, BUS_SPACE_MAXADDR_32BIT, 2151 BUS_SPACE_MAXADDR, NULL, NULL, MCLBYTES, DC_TX_LIST_CNT, MCLBYTES, 2152 0, NULL, NULL, &sc->dc_mtag); 2153 if (error) { 2154 printf("dc%d: failed to allocate busdma tag\n", unit); 2155 error = ENXIO; 2156 goto fail; 2157 } 2158 2159 /* Create the TX/RX busdma maps. */ 2160 for (i = 0; i < DC_TX_LIST_CNT; i++) { 2161 error = bus_dmamap_create(sc->dc_mtag, 0, 2162 &sc->dc_cdata.dc_tx_map[i]); 2163 if (error) { 2164 printf("dc%d: failed to init TX ring\n", unit); 2165 error = ENXIO; 2166 goto fail; 2167 } 2168 } 2169 for (i = 0; i < DC_RX_LIST_CNT; i++) { 2170 error = bus_dmamap_create(sc->dc_mtag, 0, 2171 &sc->dc_cdata.dc_rx_map[i]); 2172 if (error) { 2173 printf("dc%d: failed to init RX ring\n", unit); 2174 error = ENXIO; 2175 goto fail; 2176 } 2177 } 2178 error = bus_dmamap_create(sc->dc_mtag, 0, &sc->dc_sparemap); 2179 if (error) { 2180 printf("dc%d: failed to init RX ring\n", unit); 2181 error = ENXIO; 2182 goto fail; 2183 } 2184 2185 ifp = &sc->arpcom.ac_if; 2186 ifp->if_softc = sc; 2187 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 2188 /* XXX: bleah, MTU gets overwritten in ether_ifattach() */ 2189 ifp->if_mtu = ETHERMTU; 2190 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 2191 if (!IS_MPSAFE) 2192 ifp->if_flags |= IFF_NEEDSGIANT; 2193 ifp->if_ioctl = dc_ioctl; 2194 ifp->if_start = dc_start; 2195 ifp->if_watchdog = dc_watchdog; 2196 ifp->if_init = dc_init; 2197 ifp->if_baudrate = 10000000; 2198 IFQ_SET_MAXLEN(&ifp->if_snd, DC_TX_LIST_CNT - 1); 2199 ifp->if_snd.ifq_drv_maxlen = DC_TX_LIST_CNT - 1; 2200 IFQ_SET_READY(&ifp->if_snd); 2201 2202 /* 2203 * Do MII setup. If this is a 21143, check for a PHY on the 2204 * MII bus after applying any necessary fixups to twiddle the 2205 * GPIO bits. If we don't end up finding a PHY, restore the 2206 * old selection (SIA only or SIA/SYM) and attach the dcphy 2207 * driver instead. 2208 */ 2209 if (DC_IS_INTEL(sc)) { 2210 dc_apply_fixup(sc, IFM_AUTO); 2211 tmp = sc->dc_pmode; 2212 sc->dc_pmode = DC_PMODE_MII; 2213 } 2214 2215 error = mii_phy_probe(dev, &sc->dc_miibus, 2216 dc_ifmedia_upd, dc_ifmedia_sts); 2217 2218 if (error && DC_IS_INTEL(sc)) { 2219 sc->dc_pmode = tmp; 2220 if (sc->dc_pmode != DC_PMODE_SIA) 2221 sc->dc_pmode = DC_PMODE_SYM; 2222 sc->dc_flags |= DC_21143_NWAY; 2223 mii_phy_probe(dev, &sc->dc_miibus, 2224 dc_ifmedia_upd, dc_ifmedia_sts); 2225 /* 2226 * For non-MII cards, we need to have the 21143 2227 * drive the LEDs. Except there are some systems 2228 * like the NEC VersaPro NoteBook PC which have no 2229 * LEDs, and twiddling these bits has adverse effects 2230 * on them. (I.e. you suddenly can't get a link.) 2231 */ 2232 if (pci_read_config(dev, DC_PCI_CSID, 4) != 0x80281033) 2233 sc->dc_flags |= DC_TULIP_LEDS; 2234 error = 0; 2235 } 2236 2237 if (error) { 2238 printf("dc%d: MII without any PHY!\n", sc->dc_unit); 2239 goto fail; 2240 } 2241 2242 if (DC_IS_XIRCOM(sc)) { 2243 /* 2244 * setup General Purpose Port mode and data so the tulip 2245 * can talk to the MII. 2246 */ 2247 CSR_WRITE_4(sc, DC_SIAGP, DC_SIAGP_WRITE_EN | DC_SIAGP_INT1_EN | 2248 DC_SIAGP_MD_GP2_OUTPUT | DC_SIAGP_MD_GP0_OUTPUT); 2249 DELAY(10); 2250 CSR_WRITE_4(sc, DC_SIAGP, DC_SIAGP_INT1_EN | 2251 DC_SIAGP_MD_GP2_OUTPUT | DC_SIAGP_MD_GP0_OUTPUT); 2252 DELAY(10); 2253 } 2254 2255 if (DC_IS_ADMTEK(sc)) { 2256 /* 2257 * Set automatic TX underrun recovery for the ADMtek chips 2258 */ 2259 DC_SETBIT(sc, DC_AL_CR, DC_AL_CR_ATUR); 2260 } 2261 2262 /* 2263 * Tell the upper layer(s) we support long frames. 2264 */ 2265 ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header); 2266 ifp->if_capabilities |= IFCAP_VLAN_MTU; 2267 #ifdef DEVICE_POLLING 2268 ifp->if_capabilities |= IFCAP_POLLING; 2269 #endif 2270 ifp->if_capenable = ifp->if_capabilities; 2271 2272 callout_init(&sc->dc_stat_ch, IS_MPSAFE ? CALLOUT_MPSAFE : 0); 2273 2274 #ifdef SRM_MEDIA 2275 sc->dc_srm_media = 0; 2276 2277 /* Remember the SRM console media setting */ 2278 if (DC_IS_INTEL(sc)) { 2279 command = pci_read_config(dev, DC_PCI_CFDD, 4); 2280 command &= ~(DC_CFDD_SNOOZE_MODE | DC_CFDD_SLEEP_MODE); 2281 switch ((command >> 8) & 0xff) { 2282 case 3: 2283 sc->dc_srm_media = IFM_10_T; 2284 break; 2285 case 4: 2286 sc->dc_srm_media = IFM_10_T | IFM_FDX; 2287 break; 2288 case 5: 2289 sc->dc_srm_media = IFM_100_TX; 2290 break; 2291 case 6: 2292 sc->dc_srm_media = IFM_100_TX | IFM_FDX; 2293 break; 2294 } 2295 if (sc->dc_srm_media) 2296 sc->dc_srm_media |= IFM_ACTIVE | IFM_ETHER; 2297 } 2298 #endif 2299 2300 /* 2301 * Call MI attach routine. 2302 */ 2303 ether_ifattach(ifp, eaddr); 2304 2305 /* Hook interrupt last to avoid having to lock softc */ 2306 error = bus_setup_intr(dev, sc->dc_irq, INTR_TYPE_NET | 2307 (IS_MPSAFE ? INTR_MPSAFE : 0), 2308 dc_intr, sc, &sc->dc_intrhand); 2309 2310 if (error) { 2311 printf("dc%d: couldn't set up irq\n", unit); 2312 ether_ifdetach(ifp); 2313 goto fail; 2314 } 2315 2316 fail: 2317 if (error) 2318 dc_detach(dev); 2319 return (error); 2320 } 2321 2322 /* 2323 * Shutdown hardware and free up resources. This can be called any 2324 * time after the mutex has been initialized. It is called in both 2325 * the error case in attach and the normal detach case so it needs 2326 * to be careful about only freeing resources that have actually been 2327 * allocated. 2328 */ 2329 static int 2330 dc_detach(device_t dev) 2331 { 2332 struct dc_softc *sc; 2333 struct ifnet *ifp; 2334 struct dc_mediainfo *m; 2335 int i; 2336 2337 sc = device_get_softc(dev); 2338 KASSERT(mtx_initialized(&sc->dc_mtx), ("dc mutex not initialized")); 2339 DC_LOCK(sc); 2340 2341 ifp = &sc->arpcom.ac_if; 2342 2343 /* These should only be active if attach succeeded */ 2344 if (device_is_attached(dev)) { 2345 dc_stop(sc); 2346 ether_ifdetach(ifp); 2347 } 2348 if (sc->dc_miibus) 2349 device_delete_child(dev, sc->dc_miibus); 2350 bus_generic_detach(dev); 2351 2352 if (sc->dc_intrhand) 2353 bus_teardown_intr(dev, sc->dc_irq, sc->dc_intrhand); 2354 if (sc->dc_irq) 2355 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->dc_irq); 2356 if (sc->dc_res) 2357 bus_release_resource(dev, DC_RES, DC_RID, sc->dc_res); 2358 2359 if (sc->dc_cdata.dc_sbuf != NULL) 2360 bus_dmamem_free(sc->dc_stag, sc->dc_cdata.dc_sbuf, sc->dc_smap); 2361 if (sc->dc_ldata != NULL) 2362 bus_dmamem_free(sc->dc_ltag, sc->dc_ldata, sc->dc_lmap); 2363 for (i = 0; i < DC_TX_LIST_CNT; i++) 2364 bus_dmamap_destroy(sc->dc_mtag, sc->dc_cdata.dc_tx_map[i]); 2365 for (i = 0; i < DC_RX_LIST_CNT; i++) 2366 bus_dmamap_destroy(sc->dc_mtag, sc->dc_cdata.dc_rx_map[i]); 2367 bus_dmamap_destroy(sc->dc_mtag, sc->dc_sparemap); 2368 if (sc->dc_stag) 2369 bus_dma_tag_destroy(sc->dc_stag); 2370 if (sc->dc_mtag) 2371 bus_dma_tag_destroy(sc->dc_mtag); 2372 if (sc->dc_ltag) 2373 bus_dma_tag_destroy(sc->dc_ltag); 2374 2375 free(sc->dc_pnic_rx_buf, M_DEVBUF); 2376 2377 while (sc->dc_mi != NULL) { 2378 m = sc->dc_mi->dc_next; 2379 free(sc->dc_mi, M_DEVBUF); 2380 sc->dc_mi = m; 2381 } 2382 free(sc->dc_srom, M_DEVBUF); 2383 2384 DC_UNLOCK(sc); 2385 mtx_destroy(&sc->dc_mtx); 2386 2387 return (0); 2388 } 2389 2390 /* 2391 * Initialize the transmit descriptors. 2392 */ 2393 static int 2394 dc_list_tx_init(struct dc_softc *sc) 2395 { 2396 struct dc_chain_data *cd; 2397 struct dc_list_data *ld; 2398 int i, nexti; 2399 2400 cd = &sc->dc_cdata; 2401 ld = sc->dc_ldata; 2402 for (i = 0; i < DC_TX_LIST_CNT; i++) { 2403 if (i == DC_TX_LIST_CNT - 1) 2404 nexti = 0; 2405 else 2406 nexti = i + 1; 2407 ld->dc_tx_list[i].dc_next = htole32(DC_TXDESC(sc, nexti)); 2408 cd->dc_tx_chain[i] = NULL; 2409 ld->dc_tx_list[i].dc_data = 0; 2410 ld->dc_tx_list[i].dc_ctl = 0; 2411 } 2412 2413 cd->dc_tx_prod = cd->dc_tx_cons = cd->dc_tx_cnt = 0; 2414 bus_dmamap_sync(sc->dc_ltag, sc->dc_lmap, 2415 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2416 return (0); 2417 } 2418 2419 2420 /* 2421 * Initialize the RX descriptors and allocate mbufs for them. Note that 2422 * we arrange the descriptors in a closed ring, so that the last descriptor 2423 * points back to the first. 2424 */ 2425 static int 2426 dc_list_rx_init(struct dc_softc *sc) 2427 { 2428 struct dc_chain_data *cd; 2429 struct dc_list_data *ld; 2430 int i, nexti; 2431 2432 cd = &sc->dc_cdata; 2433 ld = sc->dc_ldata; 2434 2435 for (i = 0; i < DC_RX_LIST_CNT; i++) { 2436 if (dc_newbuf(sc, i, 1) != 0) 2437 return (ENOBUFS); 2438 if (i == DC_RX_LIST_CNT - 1) 2439 nexti = 0; 2440 else 2441 nexti = i + 1; 2442 ld->dc_rx_list[i].dc_next = htole32(DC_RXDESC(sc, nexti)); 2443 } 2444 2445 cd->dc_rx_prod = 0; 2446 bus_dmamap_sync(sc->dc_ltag, sc->dc_lmap, 2447 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2448 return (0); 2449 } 2450 2451 static void 2452 dc_dma_map_rxbuf(arg, segs, nseg, mapsize, error) 2453 void *arg; 2454 bus_dma_segment_t *segs; 2455 int nseg; 2456 bus_size_t mapsize; 2457 int error; 2458 { 2459 struct dc_softc *sc; 2460 struct dc_desc *c; 2461 2462 sc = arg; 2463 c = &sc->dc_ldata->dc_rx_list[sc->dc_cdata.dc_rx_cur]; 2464 if (error) { 2465 sc->dc_cdata.dc_rx_err = error; 2466 return; 2467 } 2468 2469 KASSERT(nseg == 1, ("wrong number of segments, should be 1")); 2470 sc->dc_cdata.dc_rx_err = 0; 2471 c->dc_data = htole32(segs->ds_addr); 2472 } 2473 2474 /* 2475 * Initialize an RX descriptor and attach an MBUF cluster. 2476 */ 2477 static int 2478 dc_newbuf(struct dc_softc *sc, int i, int alloc) 2479 { 2480 struct mbuf *m_new; 2481 bus_dmamap_t tmp; 2482 int error; 2483 2484 if (alloc) { 2485 m_new = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR); 2486 if (m_new == NULL) 2487 return (ENOBUFS); 2488 } else { 2489 m_new = sc->dc_cdata.dc_rx_chain[i]; 2490 m_new->m_data = m_new->m_ext.ext_buf; 2491 } 2492 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 2493 m_adj(m_new, sizeof(u_int64_t)); 2494 2495 /* 2496 * If this is a PNIC chip, zero the buffer. This is part 2497 * of the workaround for the receive bug in the 82c168 and 2498 * 82c169 chips. 2499 */ 2500 if (sc->dc_flags & DC_PNIC_RX_BUG_WAR) 2501 bzero(mtod(m_new, char *), m_new->m_len); 2502 2503 /* No need to remap the mbuf if we're reusing it. */ 2504 if (alloc) { 2505 sc->dc_cdata.dc_rx_cur = i; 2506 error = bus_dmamap_load_mbuf(sc->dc_mtag, sc->dc_sparemap, 2507 m_new, dc_dma_map_rxbuf, sc, 0); 2508 if (error) { 2509 m_freem(m_new); 2510 return (error); 2511 } 2512 if (sc->dc_cdata.dc_rx_err != 0) { 2513 m_freem(m_new); 2514 return (sc->dc_cdata.dc_rx_err); 2515 } 2516 bus_dmamap_unload(sc->dc_mtag, sc->dc_cdata.dc_rx_map[i]); 2517 tmp = sc->dc_cdata.dc_rx_map[i]; 2518 sc->dc_cdata.dc_rx_map[i] = sc->dc_sparemap; 2519 sc->dc_sparemap = tmp; 2520 sc->dc_cdata.dc_rx_chain[i] = m_new; 2521 } 2522 2523 sc->dc_ldata->dc_rx_list[i].dc_ctl = htole32(DC_RXCTL_RLINK | DC_RXLEN); 2524 sc->dc_ldata->dc_rx_list[i].dc_status = htole32(DC_RXSTAT_OWN); 2525 bus_dmamap_sync(sc->dc_mtag, sc->dc_cdata.dc_rx_map[i], 2526 BUS_DMASYNC_PREREAD); 2527 bus_dmamap_sync(sc->dc_ltag, sc->dc_lmap, 2528 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2529 return (0); 2530 } 2531 2532 /* 2533 * Grrrrr. 2534 * The PNIC chip has a terrible bug in it that manifests itself during 2535 * periods of heavy activity. The exact mode of failure if difficult to 2536 * pinpoint: sometimes it only happens in promiscuous mode, sometimes it 2537 * will happen on slow machines. The bug is that sometimes instead of 2538 * uploading one complete frame during reception, it uploads what looks 2539 * like the entire contents of its FIFO memory. The frame we want is at 2540 * the end of the whole mess, but we never know exactly how much data has 2541 * been uploaded, so salvaging the frame is hard. 2542 * 2543 * There is only one way to do it reliably, and it's disgusting. 2544 * Here's what we know: 2545 * 2546 * - We know there will always be somewhere between one and three extra 2547 * descriptors uploaded. 2548 * 2549 * - We know the desired received frame will always be at the end of the 2550 * total data upload. 2551 * 2552 * - We know the size of the desired received frame because it will be 2553 * provided in the length field of the status word in the last descriptor. 2554 * 2555 * Here's what we do: 2556 * 2557 * - When we allocate buffers for the receive ring, we bzero() them. 2558 * This means that we know that the buffer contents should be all 2559 * zeros, except for data uploaded by the chip. 2560 * 2561 * - We also force the PNIC chip to upload frames that include the 2562 * ethernet CRC at the end. 2563 * 2564 * - We gather all of the bogus frame data into a single buffer. 2565 * 2566 * - We then position a pointer at the end of this buffer and scan 2567 * backwards until we encounter the first non-zero byte of data. 2568 * This is the end of the received frame. We know we will encounter 2569 * some data at the end of the frame because the CRC will always be 2570 * there, so even if the sender transmits a packet of all zeros, 2571 * we won't be fooled. 2572 * 2573 * - We know the size of the actual received frame, so we subtract 2574 * that value from the current pointer location. This brings us 2575 * to the start of the actual received packet. 2576 * 2577 * - We copy this into an mbuf and pass it on, along with the actual 2578 * frame length. 2579 * 2580 * The performance hit is tremendous, but it beats dropping frames all 2581 * the time. 2582 */ 2583 2584 #define DC_WHOLEFRAME (DC_RXSTAT_FIRSTFRAG | DC_RXSTAT_LASTFRAG) 2585 static void 2586 dc_pnic_rx_bug_war(struct dc_softc *sc, int idx) 2587 { 2588 struct dc_desc *cur_rx; 2589 struct dc_desc *c = NULL; 2590 struct mbuf *m = NULL; 2591 unsigned char *ptr; 2592 int i, total_len; 2593 u_int32_t rxstat = 0; 2594 2595 i = sc->dc_pnic_rx_bug_save; 2596 cur_rx = &sc->dc_ldata->dc_rx_list[idx]; 2597 ptr = sc->dc_pnic_rx_buf; 2598 bzero(ptr, DC_RXLEN * 5); 2599 2600 /* Copy all the bytes from the bogus buffers. */ 2601 while (1) { 2602 c = &sc->dc_ldata->dc_rx_list[i]; 2603 rxstat = le32toh(c->dc_status); 2604 m = sc->dc_cdata.dc_rx_chain[i]; 2605 bcopy(mtod(m, char *), ptr, DC_RXLEN); 2606 ptr += DC_RXLEN; 2607 /* If this is the last buffer, break out. */ 2608 if (i == idx || rxstat & DC_RXSTAT_LASTFRAG) 2609 break; 2610 dc_newbuf(sc, i, 0); 2611 DC_INC(i, DC_RX_LIST_CNT); 2612 } 2613 2614 /* Find the length of the actual receive frame. */ 2615 total_len = DC_RXBYTES(rxstat); 2616 2617 /* Scan backwards until we hit a non-zero byte. */ 2618 while (*ptr == 0x00) 2619 ptr--; 2620 2621 /* Round off. */ 2622 if ((uintptr_t)(ptr) & 0x3) 2623 ptr -= 1; 2624 2625 /* Now find the start of the frame. */ 2626 ptr -= total_len; 2627 if (ptr < sc->dc_pnic_rx_buf) 2628 ptr = sc->dc_pnic_rx_buf; 2629 2630 /* 2631 * Now copy the salvaged frame to the last mbuf and fake up 2632 * the status word to make it look like a successful 2633 * frame reception. 2634 */ 2635 dc_newbuf(sc, i, 0); 2636 bcopy(ptr, mtod(m, char *), total_len); 2637 cur_rx->dc_status = htole32(rxstat | DC_RXSTAT_FIRSTFRAG); 2638 } 2639 2640 /* 2641 * This routine searches the RX ring for dirty descriptors in the 2642 * event that the rxeof routine falls out of sync with the chip's 2643 * current descriptor pointer. This may happen sometimes as a result 2644 * of a "no RX buffer available" condition that happens when the chip 2645 * consumes all of the RX buffers before the driver has a chance to 2646 * process the RX ring. This routine may need to be called more than 2647 * once to bring the driver back in sync with the chip, however we 2648 * should still be getting RX DONE interrupts to drive the search 2649 * for new packets in the RX ring, so we should catch up eventually. 2650 */ 2651 static int 2652 dc_rx_resync(struct dc_softc *sc) 2653 { 2654 struct dc_desc *cur_rx; 2655 int i, pos; 2656 2657 pos = sc->dc_cdata.dc_rx_prod; 2658 2659 for (i = 0; i < DC_RX_LIST_CNT; i++) { 2660 cur_rx = &sc->dc_ldata->dc_rx_list[pos]; 2661 if (!(le32toh(cur_rx->dc_status) & DC_RXSTAT_OWN)) 2662 break; 2663 DC_INC(pos, DC_RX_LIST_CNT); 2664 } 2665 2666 /* If the ring really is empty, then just return. */ 2667 if (i == DC_RX_LIST_CNT) 2668 return (0); 2669 2670 /* We've fallen behing the chip: catch it. */ 2671 sc->dc_cdata.dc_rx_prod = pos; 2672 2673 return (EAGAIN); 2674 } 2675 2676 /* 2677 * A frame has been uploaded: pass the resulting mbuf chain up to 2678 * the higher level protocols. 2679 */ 2680 static void 2681 dc_rxeof(struct dc_softc *sc) 2682 { 2683 struct mbuf *m; 2684 struct ifnet *ifp; 2685 struct dc_desc *cur_rx; 2686 int i, total_len = 0; 2687 u_int32_t rxstat; 2688 2689 DC_LOCK_ASSERT(sc); 2690 2691 ifp = &sc->arpcom.ac_if; 2692 i = sc->dc_cdata.dc_rx_prod; 2693 2694 bus_dmamap_sync(sc->dc_ltag, sc->dc_lmap, BUS_DMASYNC_POSTREAD); 2695 while (!(le32toh(sc->dc_ldata->dc_rx_list[i].dc_status) & 2696 DC_RXSTAT_OWN)) { 2697 #ifdef DEVICE_POLLING 2698 if (ifp->if_flags & IFF_POLLING) { 2699 if (sc->rxcycles <= 0) 2700 break; 2701 sc->rxcycles--; 2702 } 2703 #endif 2704 cur_rx = &sc->dc_ldata->dc_rx_list[i]; 2705 rxstat = le32toh(cur_rx->dc_status); 2706 m = sc->dc_cdata.dc_rx_chain[i]; 2707 bus_dmamap_sync(sc->dc_mtag, sc->dc_cdata.dc_rx_map[i], 2708 BUS_DMASYNC_POSTREAD); 2709 total_len = DC_RXBYTES(rxstat); 2710 2711 if (sc->dc_flags & DC_PNIC_RX_BUG_WAR) { 2712 if ((rxstat & DC_WHOLEFRAME) != DC_WHOLEFRAME) { 2713 if (rxstat & DC_RXSTAT_FIRSTFRAG) 2714 sc->dc_pnic_rx_bug_save = i; 2715 if ((rxstat & DC_RXSTAT_LASTFRAG) == 0) { 2716 DC_INC(i, DC_RX_LIST_CNT); 2717 continue; 2718 } 2719 dc_pnic_rx_bug_war(sc, i); 2720 rxstat = le32toh(cur_rx->dc_status); 2721 total_len = DC_RXBYTES(rxstat); 2722 } 2723 } 2724 2725 /* 2726 * If an error occurs, update stats, clear the 2727 * status word and leave the mbuf cluster in place: 2728 * it should simply get re-used next time this descriptor 2729 * comes up in the ring. However, don't report long 2730 * frames as errors since they could be vlans. 2731 */ 2732 if ((rxstat & DC_RXSTAT_RXERR)) { 2733 if (!(rxstat & DC_RXSTAT_GIANT) || 2734 (rxstat & (DC_RXSTAT_CRCERR | DC_RXSTAT_DRIBBLE | 2735 DC_RXSTAT_MIIERE | DC_RXSTAT_COLLSEEN | 2736 DC_RXSTAT_RUNT | DC_RXSTAT_DE))) { 2737 ifp->if_ierrors++; 2738 if (rxstat & DC_RXSTAT_COLLSEEN) 2739 ifp->if_collisions++; 2740 dc_newbuf(sc, i, 0); 2741 if (rxstat & DC_RXSTAT_CRCERR) { 2742 DC_INC(i, DC_RX_LIST_CNT); 2743 continue; 2744 } else { 2745 dc_init(sc); 2746 return; 2747 } 2748 } 2749 } 2750 2751 /* No errors; receive the packet. */ 2752 total_len -= ETHER_CRC_LEN; 2753 #ifdef __i386__ 2754 /* 2755 * On the x86 we do not have alignment problems, so try to 2756 * allocate a new buffer for the receive ring, and pass up 2757 * the one where the packet is already, saving the expensive 2758 * copy done in m_devget(). 2759 * If we are on an architecture with alignment problems, or 2760 * if the allocation fails, then use m_devget and leave the 2761 * existing buffer in the receive ring. 2762 */ 2763 if (dc_quick && dc_newbuf(sc, i, 1) == 0) { 2764 m->m_pkthdr.rcvif = ifp; 2765 m->m_pkthdr.len = m->m_len = total_len; 2766 DC_INC(i, DC_RX_LIST_CNT); 2767 } else 2768 #endif 2769 { 2770 struct mbuf *m0; 2771 2772 m0 = m_devget(mtod(m, char *), total_len, 2773 ETHER_ALIGN, ifp, NULL); 2774 dc_newbuf(sc, i, 0); 2775 DC_INC(i, DC_RX_LIST_CNT); 2776 if (m0 == NULL) { 2777 ifp->if_ierrors++; 2778 continue; 2779 } 2780 m = m0; 2781 } 2782 2783 ifp->if_ipackets++; 2784 DC_UNLOCK(sc); 2785 (*ifp->if_input)(ifp, m); 2786 DC_LOCK(sc); 2787 } 2788 2789 sc->dc_cdata.dc_rx_prod = i; 2790 } 2791 2792 /* 2793 * A frame was downloaded to the chip. It's safe for us to clean up 2794 * the list buffers. 2795 */ 2796 2797 static void 2798 dc_txeof(struct dc_softc *sc) 2799 { 2800 struct dc_desc *cur_tx = NULL; 2801 struct ifnet *ifp; 2802 int idx; 2803 u_int32_t ctl, txstat; 2804 2805 ifp = &sc->arpcom.ac_if; 2806 2807 /* 2808 * Go through our tx list and free mbufs for those 2809 * frames that have been transmitted. 2810 */ 2811 bus_dmamap_sync(sc->dc_ltag, sc->dc_lmap, BUS_DMASYNC_POSTREAD); 2812 idx = sc->dc_cdata.dc_tx_cons; 2813 while (idx != sc->dc_cdata.dc_tx_prod) { 2814 2815 cur_tx = &sc->dc_ldata->dc_tx_list[idx]; 2816 txstat = le32toh(cur_tx->dc_status); 2817 ctl = le32toh(cur_tx->dc_ctl); 2818 2819 if (txstat & DC_TXSTAT_OWN) 2820 break; 2821 2822 if (!(ctl & DC_TXCTL_LASTFRAG) || ctl & DC_TXCTL_SETUP) { 2823 if (ctl & DC_TXCTL_SETUP) { 2824 /* 2825 * Yes, the PNIC is so brain damaged 2826 * that it will sometimes generate a TX 2827 * underrun error while DMAing the RX 2828 * filter setup frame. If we detect this, 2829 * we have to send the setup frame again, 2830 * or else the filter won't be programmed 2831 * correctly. 2832 */ 2833 if (DC_IS_PNIC(sc)) { 2834 if (txstat & DC_TXSTAT_ERRSUM) 2835 dc_setfilt(sc); 2836 } 2837 sc->dc_cdata.dc_tx_chain[idx] = NULL; 2838 } 2839 sc->dc_cdata.dc_tx_cnt--; 2840 DC_INC(idx, DC_TX_LIST_CNT); 2841 continue; 2842 } 2843 2844 if (DC_IS_XIRCOM(sc) || DC_IS_CONEXANT(sc)) { 2845 /* 2846 * XXX: Why does my Xircom taunt me so? 2847 * For some reason it likes setting the CARRLOST flag 2848 * even when the carrier is there. wtf?!? 2849 * Who knows, but Conexant chips have the 2850 * same problem. Maybe they took lessons 2851 * from Xircom. 2852 */ 2853 if (/*sc->dc_type == DC_TYPE_21143 &&*/ 2854 sc->dc_pmode == DC_PMODE_MII && 2855 ((txstat & 0xFFFF) & ~(DC_TXSTAT_ERRSUM | 2856 DC_TXSTAT_NOCARRIER))) 2857 txstat &= ~DC_TXSTAT_ERRSUM; 2858 } else { 2859 if (/*sc->dc_type == DC_TYPE_21143 &&*/ 2860 sc->dc_pmode == DC_PMODE_MII && 2861 ((txstat & 0xFFFF) & ~(DC_TXSTAT_ERRSUM | 2862 DC_TXSTAT_NOCARRIER | DC_TXSTAT_CARRLOST))) 2863 txstat &= ~DC_TXSTAT_ERRSUM; 2864 } 2865 2866 if (txstat & DC_TXSTAT_ERRSUM) { 2867 ifp->if_oerrors++; 2868 if (txstat & DC_TXSTAT_EXCESSCOLL) 2869 ifp->if_collisions++; 2870 if (txstat & DC_TXSTAT_LATECOLL) 2871 ifp->if_collisions++; 2872 if (!(txstat & DC_TXSTAT_UNDERRUN)) { 2873 dc_init(sc); 2874 return; 2875 } 2876 } 2877 2878 ifp->if_collisions += (txstat & DC_TXSTAT_COLLCNT) >> 3; 2879 2880 ifp->if_opackets++; 2881 if (sc->dc_cdata.dc_tx_chain[idx] != NULL) { 2882 bus_dmamap_sync(sc->dc_mtag, 2883 sc->dc_cdata.dc_tx_map[idx], 2884 BUS_DMASYNC_POSTWRITE); 2885 bus_dmamap_unload(sc->dc_mtag, 2886 sc->dc_cdata.dc_tx_map[idx]); 2887 m_freem(sc->dc_cdata.dc_tx_chain[idx]); 2888 sc->dc_cdata.dc_tx_chain[idx] = NULL; 2889 } 2890 2891 sc->dc_cdata.dc_tx_cnt--; 2892 DC_INC(idx, DC_TX_LIST_CNT); 2893 } 2894 2895 if (idx != sc->dc_cdata.dc_tx_cons) { 2896 /* Some buffers have been freed. */ 2897 sc->dc_cdata.dc_tx_cons = idx; 2898 ifp->if_flags &= ~IFF_OACTIVE; 2899 } 2900 ifp->if_timer = (sc->dc_cdata.dc_tx_cnt == 0) ? 0 : 5; 2901 } 2902 2903 static void 2904 dc_tick(void *xsc) 2905 { 2906 struct dc_softc *sc; 2907 struct mii_data *mii; 2908 struct ifnet *ifp; 2909 u_int32_t r; 2910 2911 sc = xsc; 2912 DC_LOCK(sc); 2913 ifp = &sc->arpcom.ac_if; 2914 mii = device_get_softc(sc->dc_miibus); 2915 2916 if (sc->dc_flags & DC_REDUCED_MII_POLL) { 2917 if (sc->dc_flags & DC_21143_NWAY) { 2918 r = CSR_READ_4(sc, DC_10BTSTAT); 2919 if (IFM_SUBTYPE(mii->mii_media_active) == 2920 IFM_100_TX && (r & DC_TSTAT_LS100)) { 2921 sc->dc_link = 0; 2922 mii_mediachg(mii); 2923 } 2924 if (IFM_SUBTYPE(mii->mii_media_active) == 2925 IFM_10_T && (r & DC_TSTAT_LS10)) { 2926 sc->dc_link = 0; 2927 mii_mediachg(mii); 2928 } 2929 if (sc->dc_link == 0) 2930 mii_tick(mii); 2931 } else { 2932 r = CSR_READ_4(sc, DC_ISR); 2933 if ((r & DC_ISR_RX_STATE) == DC_RXSTATE_WAIT && 2934 sc->dc_cdata.dc_tx_cnt == 0) { 2935 mii_tick(mii); 2936 if (!(mii->mii_media_status & IFM_ACTIVE)) 2937 sc->dc_link = 0; 2938 } 2939 } 2940 } else 2941 mii_tick(mii); 2942 2943 /* 2944 * When the init routine completes, we expect to be able to send 2945 * packets right away, and in fact the network code will send a 2946 * gratuitous ARP the moment the init routine marks the interface 2947 * as running. However, even though the MAC may have been initialized, 2948 * there may be a delay of a few seconds before the PHY completes 2949 * autonegotiation and the link is brought up. Any transmissions 2950 * made during that delay will be lost. Dealing with this is tricky: 2951 * we can't just pause in the init routine while waiting for the 2952 * PHY to come ready since that would bring the whole system to 2953 * a screeching halt for several seconds. 2954 * 2955 * What we do here is prevent the TX start routine from sending 2956 * any packets until a link has been established. After the 2957 * interface has been initialized, the tick routine will poll 2958 * the state of the PHY until the IFM_ACTIVE flag is set. Until 2959 * that time, packets will stay in the send queue, and once the 2960 * link comes up, they will be flushed out to the wire. 2961 */ 2962 if (!sc->dc_link && mii->mii_media_status & IFM_ACTIVE && 2963 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) { 2964 sc->dc_link++; 2965 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 2966 dc_start(ifp); 2967 } 2968 2969 if (sc->dc_flags & DC_21143_NWAY && !sc->dc_link) 2970 callout_reset(&sc->dc_stat_ch, hz/10, dc_tick, sc); 2971 else 2972 callout_reset(&sc->dc_stat_ch, hz, dc_tick, sc); 2973 2974 DC_UNLOCK(sc); 2975 } 2976 2977 /* 2978 * A transmit underrun has occurred. Back off the transmit threshold, 2979 * or switch to store and forward mode if we have to. 2980 */ 2981 static void 2982 dc_tx_underrun(struct dc_softc *sc) 2983 { 2984 u_int32_t isr; 2985 int i; 2986 2987 if (DC_IS_DAVICOM(sc)) 2988 dc_init(sc); 2989 2990 if (DC_IS_INTEL(sc)) { 2991 /* 2992 * The real 21143 requires that the transmitter be idle 2993 * in order to change the transmit threshold or store 2994 * and forward state. 2995 */ 2996 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_TX_ON); 2997 2998 for (i = 0; i < DC_TIMEOUT; i++) { 2999 isr = CSR_READ_4(sc, DC_ISR); 3000 if (isr & DC_ISR_TX_IDLE) 3001 break; 3002 DELAY(10); 3003 } 3004 if (i == DC_TIMEOUT) { 3005 printf("dc%d: failed to force tx to idle state\n", 3006 sc->dc_unit); 3007 dc_init(sc); 3008 } 3009 } 3010 3011 printf("dc%d: TX underrun -- ", sc->dc_unit); 3012 sc->dc_txthresh += DC_TXTHRESH_INC; 3013 if (sc->dc_txthresh > DC_TXTHRESH_MAX) { 3014 printf("using store and forward mode\n"); 3015 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_STORENFWD); 3016 } else { 3017 printf("increasing TX threshold\n"); 3018 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_TX_THRESH); 3019 DC_SETBIT(sc, DC_NETCFG, sc->dc_txthresh); 3020 } 3021 3022 if (DC_IS_INTEL(sc)) 3023 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_TX_ON); 3024 } 3025 3026 #ifdef DEVICE_POLLING 3027 static poll_handler_t dc_poll; 3028 3029 static void 3030 dc_poll(struct ifnet *ifp, enum poll_cmd cmd, int count) 3031 { 3032 struct dc_softc *sc = ifp->if_softc; 3033 3034 if (!(ifp->if_capenable & IFCAP_POLLING)) { 3035 ether_poll_deregister(ifp); 3036 cmd = POLL_DEREGISTER; 3037 } 3038 if (cmd == POLL_DEREGISTER) { /* final call, enable interrupts */ 3039 /* Re-enable interrupts. */ 3040 CSR_WRITE_4(sc, DC_IMR, DC_INTRS); 3041 return; 3042 } 3043 DC_LOCK(sc); 3044 sc->rxcycles = count; 3045 dc_rxeof(sc); 3046 dc_txeof(sc); 3047 if (!IFQ_IS_EMPTY(&ifp->if_snd) && !(ifp->if_flags & IFF_OACTIVE)) 3048 dc_start(ifp); 3049 3050 if (cmd == POLL_AND_CHECK_STATUS) { /* also check status register */ 3051 u_int32_t status; 3052 3053 status = CSR_READ_4(sc, DC_ISR); 3054 status &= (DC_ISR_RX_WATDOGTIMEO | DC_ISR_RX_NOBUF | 3055 DC_ISR_TX_NOBUF | DC_ISR_TX_IDLE | DC_ISR_TX_UNDERRUN | 3056 DC_ISR_BUS_ERR); 3057 if (!status) { 3058 DC_UNLOCK(sc); 3059 return; 3060 } 3061 /* ack what we have */ 3062 CSR_WRITE_4(sc, DC_ISR, status); 3063 3064 if (status & (DC_ISR_RX_WATDOGTIMEO | DC_ISR_RX_NOBUF)) { 3065 u_int32_t r = CSR_READ_4(sc, DC_FRAMESDISCARDED); 3066 ifp->if_ierrors += (r & 0xffff) + ((r >> 17) & 0x7ff); 3067 3068 if (dc_rx_resync(sc)) 3069 dc_rxeof(sc); 3070 } 3071 /* restart transmit unit if necessary */ 3072 if (status & DC_ISR_TX_IDLE && sc->dc_cdata.dc_tx_cnt) 3073 CSR_WRITE_4(sc, DC_TXSTART, 0xFFFFFFFF); 3074 3075 if (status & DC_ISR_TX_UNDERRUN) 3076 dc_tx_underrun(sc); 3077 3078 if (status & DC_ISR_BUS_ERR) { 3079 printf("dc_poll: dc%d bus error\n", sc->dc_unit); 3080 dc_reset(sc); 3081 dc_init(sc); 3082 } 3083 } 3084 DC_UNLOCK(sc); 3085 } 3086 #endif /* DEVICE_POLLING */ 3087 3088 static void 3089 dc_intr(void *arg) 3090 { 3091 struct dc_softc *sc; 3092 struct ifnet *ifp; 3093 u_int32_t status; 3094 3095 sc = arg; 3096 3097 if (sc->suspended) 3098 return; 3099 3100 if ((CSR_READ_4(sc, DC_ISR) & DC_INTRS) == 0) 3101 return; 3102 3103 DC_LOCK(sc); 3104 ifp = &sc->arpcom.ac_if; 3105 #ifdef DEVICE_POLLING 3106 if (ifp->if_flags & IFF_POLLING) 3107 goto done; 3108 if ((ifp->if_capenable & IFCAP_POLLING) && 3109 ether_poll_register(dc_poll, ifp)) { /* ok, disable interrupts */ 3110 CSR_WRITE_4(sc, DC_IMR, 0x00000000); 3111 goto done; 3112 } 3113 #endif 3114 3115 /* Suppress unwanted interrupts */ 3116 if (!(ifp->if_flags & IFF_UP)) { 3117 if (CSR_READ_4(sc, DC_ISR) & DC_INTRS) 3118 dc_stop(sc); 3119 DC_UNLOCK(sc); 3120 return; 3121 } 3122 3123 /* Disable interrupts. */ 3124 CSR_WRITE_4(sc, DC_IMR, 0x00000000); 3125 3126 while (((status = CSR_READ_4(sc, DC_ISR)) & DC_INTRS) 3127 && status != 0xFFFFFFFF) { 3128 3129 CSR_WRITE_4(sc, DC_ISR, status); 3130 3131 if (status & DC_ISR_RX_OK) { 3132 int curpkts; 3133 curpkts = ifp->if_ipackets; 3134 dc_rxeof(sc); 3135 if (curpkts == ifp->if_ipackets) { 3136 while (dc_rx_resync(sc)) 3137 dc_rxeof(sc); 3138 } 3139 } 3140 3141 if (status & (DC_ISR_TX_OK | DC_ISR_TX_NOBUF)) 3142 dc_txeof(sc); 3143 3144 if (status & DC_ISR_TX_IDLE) { 3145 dc_txeof(sc); 3146 if (sc->dc_cdata.dc_tx_cnt) { 3147 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_TX_ON); 3148 CSR_WRITE_4(sc, DC_TXSTART, 0xFFFFFFFF); 3149 } 3150 } 3151 3152 if (status & DC_ISR_TX_UNDERRUN) 3153 dc_tx_underrun(sc); 3154 3155 if ((status & DC_ISR_RX_WATDOGTIMEO) 3156 || (status & DC_ISR_RX_NOBUF)) { 3157 int curpkts; 3158 curpkts = ifp->if_ipackets; 3159 dc_rxeof(sc); 3160 if (curpkts == ifp->if_ipackets) { 3161 while (dc_rx_resync(sc)) 3162 dc_rxeof(sc); 3163 } 3164 } 3165 3166 if (status & DC_ISR_BUS_ERR) { 3167 dc_reset(sc); 3168 dc_init(sc); 3169 } 3170 } 3171 3172 /* Re-enable interrupts. */ 3173 CSR_WRITE_4(sc, DC_IMR, DC_INTRS); 3174 3175 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 3176 dc_start(ifp); 3177 3178 #ifdef DEVICE_POLLING 3179 done: 3180 #endif 3181 3182 DC_UNLOCK(sc); 3183 } 3184 3185 static void 3186 dc_dma_map_txbuf(arg, segs, nseg, mapsize, error) 3187 void *arg; 3188 bus_dma_segment_t *segs; 3189 int nseg; 3190 bus_size_t mapsize; 3191 int error; 3192 { 3193 struct dc_softc *sc; 3194 struct dc_desc *f; 3195 int cur, first, frag, i; 3196 3197 sc = arg; 3198 if (error) { 3199 sc->dc_cdata.dc_tx_err = error; 3200 return; 3201 } 3202 3203 first = cur = frag = sc->dc_cdata.dc_tx_prod; 3204 for (i = 0; i < nseg; i++) { 3205 if ((sc->dc_flags & DC_TX_ADMTEK_WAR) && 3206 (frag == (DC_TX_LIST_CNT - 1)) && 3207 (first != sc->dc_cdata.dc_tx_first)) { 3208 bus_dmamap_unload(sc->dc_mtag, 3209 sc->dc_cdata.dc_tx_map[first]); 3210 sc->dc_cdata.dc_tx_err = ENOBUFS; 3211 return; 3212 } 3213 3214 f = &sc->dc_ldata->dc_tx_list[frag]; 3215 f->dc_ctl = htole32(DC_TXCTL_TLINK | segs[i].ds_len); 3216 if (i == 0) { 3217 f->dc_status = 0; 3218 f->dc_ctl |= htole32(DC_TXCTL_FIRSTFRAG); 3219 } else 3220 f->dc_status = htole32(DC_TXSTAT_OWN); 3221 f->dc_data = htole32(segs[i].ds_addr); 3222 cur = frag; 3223 DC_INC(frag, DC_TX_LIST_CNT); 3224 } 3225 3226 sc->dc_cdata.dc_tx_err = 0; 3227 sc->dc_cdata.dc_tx_prod = frag; 3228 sc->dc_cdata.dc_tx_cnt += nseg; 3229 sc->dc_ldata->dc_tx_list[cur].dc_ctl |= htole32(DC_TXCTL_LASTFRAG); 3230 sc->dc_cdata.dc_tx_chain[cur] = sc->dc_cdata.dc_tx_mapping; 3231 if (sc->dc_flags & DC_TX_INTR_FIRSTFRAG) 3232 sc->dc_ldata->dc_tx_list[first].dc_ctl |= 3233 htole32(DC_TXCTL_FINT); 3234 if (sc->dc_flags & DC_TX_INTR_ALWAYS) 3235 sc->dc_ldata->dc_tx_list[cur].dc_ctl |= htole32(DC_TXCTL_FINT); 3236 if (sc->dc_flags & DC_TX_USE_TX_INTR && sc->dc_cdata.dc_tx_cnt > 64) 3237 sc->dc_ldata->dc_tx_list[cur].dc_ctl |= htole32(DC_TXCTL_FINT); 3238 sc->dc_ldata->dc_tx_list[first].dc_status = htole32(DC_TXSTAT_OWN); 3239 } 3240 3241 /* 3242 * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data 3243 * pointers to the fragment pointers. 3244 */ 3245 static int 3246 dc_encap(struct dc_softc *sc, struct mbuf **m_head) 3247 { 3248 struct mbuf *m; 3249 int error, idx, chainlen = 0; 3250 3251 /* 3252 * If there's no way we can send any packets, return now. 3253 */ 3254 if (DC_TX_LIST_CNT - sc->dc_cdata.dc_tx_cnt < 6) 3255 return (ENOBUFS); 3256 3257 /* 3258 * Count the number of frags in this chain to see if 3259 * we need to m_defrag. Since the descriptor list is shared 3260 * by all packets, we'll m_defrag long chains so that they 3261 * do not use up the entire list, even if they would fit. 3262 */ 3263 for (m = *m_head; m != NULL; m = m->m_next) 3264 chainlen++; 3265 3266 if ((chainlen > DC_TX_LIST_CNT / 4) || 3267 ((DC_TX_LIST_CNT - (chainlen + sc->dc_cdata.dc_tx_cnt)) < 6)) { 3268 m = m_defrag(*m_head, M_DONTWAIT); 3269 if (m == NULL) 3270 return (ENOBUFS); 3271 *m_head = m; 3272 } 3273 3274 /* 3275 * Start packing the mbufs in this chain into 3276 * the fragment pointers. Stop when we run out 3277 * of fragments or hit the end of the mbuf chain. 3278 */ 3279 idx = sc->dc_cdata.dc_tx_prod; 3280 sc->dc_cdata.dc_tx_mapping = *m_head; 3281 error = bus_dmamap_load_mbuf(sc->dc_mtag, sc->dc_cdata.dc_tx_map[idx], 3282 *m_head, dc_dma_map_txbuf, sc, 0); 3283 if (error) 3284 return (error); 3285 if (sc->dc_cdata.dc_tx_err != 0) 3286 return (sc->dc_cdata.dc_tx_err); 3287 bus_dmamap_sync(sc->dc_mtag, sc->dc_cdata.dc_tx_map[idx], 3288 BUS_DMASYNC_PREWRITE); 3289 bus_dmamap_sync(sc->dc_ltag, sc->dc_lmap, 3290 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3291 return (0); 3292 } 3293 3294 /* 3295 * Main transmit routine. To avoid having to do mbuf copies, we put pointers 3296 * to the mbuf data regions directly in the transmit lists. We also save a 3297 * copy of the pointers since the transmit list fragment pointers are 3298 * physical addresses. 3299 */ 3300 3301 static void 3302 dc_start(struct ifnet *ifp) 3303 { 3304 struct dc_softc *sc; 3305 struct mbuf *m_head = NULL, *m; 3306 unsigned int queued = 0; 3307 int idx; 3308 3309 sc = ifp->if_softc; 3310 3311 DC_LOCK(sc); 3312 3313 if (!sc->dc_link && ifp->if_snd.ifq_len < 10) { 3314 DC_UNLOCK(sc); 3315 return; 3316 } 3317 3318 if (ifp->if_flags & IFF_OACTIVE) { 3319 DC_UNLOCK(sc); 3320 return; 3321 } 3322 3323 idx = sc->dc_cdata.dc_tx_first = sc->dc_cdata.dc_tx_prod; 3324 3325 while (sc->dc_cdata.dc_tx_chain[idx] == NULL) { 3326 IFQ_DRV_DEQUEUE(&ifp->if_snd, m_head); 3327 if (m_head == NULL) 3328 break; 3329 3330 if (sc->dc_flags & DC_TX_COALESCE && 3331 (m_head->m_next != NULL || 3332 sc->dc_flags & DC_TX_ALIGN)) { 3333 m = m_defrag(m_head, M_DONTWAIT); 3334 if (m == NULL) { 3335 IFQ_DRV_PREPEND(&ifp->if_snd, m_head); 3336 ifp->if_flags |= IFF_OACTIVE; 3337 break; 3338 } else { 3339 m_head = m; 3340 } 3341 } 3342 3343 if (dc_encap(sc, &m_head)) { 3344 IFQ_DRV_PREPEND(&ifp->if_snd, m_head); 3345 ifp->if_flags |= IFF_OACTIVE; 3346 break; 3347 } 3348 idx = sc->dc_cdata.dc_tx_prod; 3349 3350 queued++; 3351 /* 3352 * If there's a BPF listener, bounce a copy of this frame 3353 * to him. 3354 */ 3355 BPF_MTAP(ifp, m_head); 3356 3357 if (sc->dc_flags & DC_TX_ONE) { 3358 ifp->if_flags |= IFF_OACTIVE; 3359 break; 3360 } 3361 } 3362 3363 if (queued > 0) { 3364 /* Transmit */ 3365 if (!(sc->dc_flags & DC_TX_POLL)) 3366 CSR_WRITE_4(sc, DC_TXSTART, 0xFFFFFFFF); 3367 3368 /* 3369 * Set a timeout in case the chip goes out to lunch. 3370 */ 3371 ifp->if_timer = 5; 3372 } 3373 3374 DC_UNLOCK(sc); 3375 } 3376 3377 static void 3378 dc_init(void *xsc) 3379 { 3380 struct dc_softc *sc = xsc; 3381 struct ifnet *ifp = &sc->arpcom.ac_if; 3382 struct mii_data *mii; 3383 3384 DC_LOCK(sc); 3385 3386 mii = device_get_softc(sc->dc_miibus); 3387 3388 /* 3389 * Cancel pending I/O and free all RX/TX buffers. 3390 */ 3391 dc_stop(sc); 3392 dc_reset(sc); 3393 3394 /* 3395 * Set cache alignment and burst length. 3396 */ 3397 if (DC_IS_ASIX(sc) || DC_IS_DAVICOM(sc)) 3398 CSR_WRITE_4(sc, DC_BUSCTL, 0); 3399 else 3400 CSR_WRITE_4(sc, DC_BUSCTL, DC_BUSCTL_MRME | DC_BUSCTL_MRLE); 3401 /* 3402 * Evenly share the bus between receive and transmit process. 3403 */ 3404 if (DC_IS_INTEL(sc)) 3405 DC_SETBIT(sc, DC_BUSCTL, DC_BUSCTL_ARBITRATION); 3406 if (DC_IS_DAVICOM(sc) || DC_IS_INTEL(sc)) { 3407 DC_SETBIT(sc, DC_BUSCTL, DC_BURSTLEN_USECA); 3408 } else { 3409 DC_SETBIT(sc, DC_BUSCTL, DC_BURSTLEN_16LONG); 3410 } 3411 if (sc->dc_flags & DC_TX_POLL) 3412 DC_SETBIT(sc, DC_BUSCTL, DC_TXPOLL_1); 3413 switch(sc->dc_cachesize) { 3414 case 32: 3415 DC_SETBIT(sc, DC_BUSCTL, DC_CACHEALIGN_32LONG); 3416 break; 3417 case 16: 3418 DC_SETBIT(sc, DC_BUSCTL, DC_CACHEALIGN_16LONG); 3419 break; 3420 case 8: 3421 DC_SETBIT(sc, DC_BUSCTL, DC_CACHEALIGN_8LONG); 3422 break; 3423 case 0: 3424 default: 3425 DC_SETBIT(sc, DC_BUSCTL, DC_CACHEALIGN_NONE); 3426 break; 3427 } 3428 3429 if (sc->dc_flags & DC_TX_STORENFWD) 3430 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_STORENFWD); 3431 else { 3432 if (sc->dc_txthresh > DC_TXTHRESH_MAX) { 3433 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_STORENFWD); 3434 } else { 3435 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_STORENFWD); 3436 DC_SETBIT(sc, DC_NETCFG, sc->dc_txthresh); 3437 } 3438 } 3439 3440 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_NO_RXCRC); 3441 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_TX_BACKOFF); 3442 3443 if (DC_IS_MACRONIX(sc) || DC_IS_PNICII(sc)) { 3444 /* 3445 * The app notes for the 98713 and 98715A say that 3446 * in order to have the chips operate properly, a magic 3447 * number must be written to CSR16. Macronix does not 3448 * document the meaning of these bits so there's no way 3449 * to know exactly what they do. The 98713 has a magic 3450 * number all its own; the rest all use a different one. 3451 */ 3452 DC_CLRBIT(sc, DC_MX_MAGICPACKET, 0xFFFF0000); 3453 if (sc->dc_type == DC_TYPE_98713) 3454 DC_SETBIT(sc, DC_MX_MAGICPACKET, DC_MX_MAGIC_98713); 3455 else 3456 DC_SETBIT(sc, DC_MX_MAGICPACKET, DC_MX_MAGIC_98715); 3457 } 3458 3459 if (DC_IS_XIRCOM(sc)) { 3460 /* 3461 * setup General Purpose Port mode and data so the tulip 3462 * can talk to the MII. 3463 */ 3464 CSR_WRITE_4(sc, DC_SIAGP, DC_SIAGP_WRITE_EN | DC_SIAGP_INT1_EN | 3465 DC_SIAGP_MD_GP2_OUTPUT | DC_SIAGP_MD_GP0_OUTPUT); 3466 DELAY(10); 3467 CSR_WRITE_4(sc, DC_SIAGP, DC_SIAGP_INT1_EN | 3468 DC_SIAGP_MD_GP2_OUTPUT | DC_SIAGP_MD_GP0_OUTPUT); 3469 DELAY(10); 3470 } 3471 3472 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_TX_THRESH); 3473 DC_SETBIT(sc, DC_NETCFG, DC_TXTHRESH_MIN); 3474 3475 /* Init circular RX list. */ 3476 if (dc_list_rx_init(sc) == ENOBUFS) { 3477 printf("dc%d: initialization failed: no " 3478 "memory for rx buffers\n", sc->dc_unit); 3479 dc_stop(sc); 3480 DC_UNLOCK(sc); 3481 return; 3482 } 3483 3484 /* 3485 * Init TX descriptors. 3486 */ 3487 dc_list_tx_init(sc); 3488 3489 /* 3490 * Load the address of the RX list. 3491 */ 3492 CSR_WRITE_4(sc, DC_RXADDR, DC_RXDESC(sc, 0)); 3493 CSR_WRITE_4(sc, DC_TXADDR, DC_TXDESC(sc, 0)); 3494 3495 /* 3496 * Enable interrupts. 3497 */ 3498 #ifdef DEVICE_POLLING 3499 /* 3500 * ... but only if we are not polling, and make sure they are off in 3501 * the case of polling. Some cards (e.g. fxp) turn interrupts on 3502 * after a reset. 3503 */ 3504 if (ifp->if_flags & IFF_POLLING) 3505 CSR_WRITE_4(sc, DC_IMR, 0x00000000); 3506 else 3507 #endif 3508 CSR_WRITE_4(sc, DC_IMR, DC_INTRS); 3509 CSR_WRITE_4(sc, DC_ISR, 0xFFFFFFFF); 3510 3511 /* Enable transmitter. */ 3512 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_TX_ON); 3513 3514 /* 3515 * If this is an Intel 21143 and we're not using the 3516 * MII port, program the LED control pins so we get 3517 * link and activity indications. 3518 */ 3519 if (sc->dc_flags & DC_TULIP_LEDS) { 3520 CSR_WRITE_4(sc, DC_WATCHDOG, 3521 DC_WDOG_CTLWREN | DC_WDOG_LINK | DC_WDOG_ACTIVITY); 3522 CSR_WRITE_4(sc, DC_WATCHDOG, 0); 3523 } 3524 3525 /* 3526 * Load the RX/multicast filter. We do this sort of late 3527 * because the filter programming scheme on the 21143 and 3528 * some clones requires DMAing a setup frame via the TX 3529 * engine, and we need the transmitter enabled for that. 3530 */ 3531 dc_setfilt(sc); 3532 3533 /* Enable receiver. */ 3534 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_ON); 3535 CSR_WRITE_4(sc, DC_RXSTART, 0xFFFFFFFF); 3536 3537 mii_mediachg(mii); 3538 dc_setcfg(sc, sc->dc_if_media); 3539 3540 ifp->if_flags |= IFF_RUNNING; 3541 ifp->if_flags &= ~IFF_OACTIVE; 3542 3543 /* Don't start the ticker if this is a homePNA link. */ 3544 if (IFM_SUBTYPE(mii->mii_media.ifm_media) == IFM_HPNA_1) 3545 sc->dc_link = 1; 3546 else { 3547 if (sc->dc_flags & DC_21143_NWAY) 3548 callout_reset(&sc->dc_stat_ch, hz/10, dc_tick, sc); 3549 else 3550 callout_reset(&sc->dc_stat_ch, hz, dc_tick, sc); 3551 } 3552 3553 #ifdef SRM_MEDIA 3554 if(sc->dc_srm_media) { 3555 struct ifreq ifr; 3556 3557 ifr.ifr_media = sc->dc_srm_media; 3558 ifmedia_ioctl(ifp, &ifr, &mii->mii_media, SIOCSIFMEDIA); 3559 sc->dc_srm_media = 0; 3560 } 3561 #endif 3562 DC_UNLOCK(sc); 3563 } 3564 3565 /* 3566 * Set media options. 3567 */ 3568 static int 3569 dc_ifmedia_upd(struct ifnet *ifp) 3570 { 3571 struct dc_softc *sc; 3572 struct mii_data *mii; 3573 struct ifmedia *ifm; 3574 3575 sc = ifp->if_softc; 3576 mii = device_get_softc(sc->dc_miibus); 3577 mii_mediachg(mii); 3578 ifm = &mii->mii_media; 3579 3580 if (DC_IS_DAVICOM(sc) && 3581 IFM_SUBTYPE(ifm->ifm_media) == IFM_HPNA_1) 3582 dc_setcfg(sc, ifm->ifm_media); 3583 else 3584 sc->dc_link = 0; 3585 3586 return (0); 3587 } 3588 3589 /* 3590 * Report current media status. 3591 */ 3592 static void 3593 dc_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 3594 { 3595 struct dc_softc *sc; 3596 struct mii_data *mii; 3597 struct ifmedia *ifm; 3598 3599 sc = ifp->if_softc; 3600 mii = device_get_softc(sc->dc_miibus); 3601 mii_pollstat(mii); 3602 ifm = &mii->mii_media; 3603 if (DC_IS_DAVICOM(sc)) { 3604 if (IFM_SUBTYPE(ifm->ifm_media) == IFM_HPNA_1) { 3605 ifmr->ifm_active = ifm->ifm_media; 3606 ifmr->ifm_status = 0; 3607 return; 3608 } 3609 } 3610 ifmr->ifm_active = mii->mii_media_active; 3611 ifmr->ifm_status = mii->mii_media_status; 3612 } 3613 3614 static int 3615 dc_ioctl(struct ifnet *ifp, u_long command, caddr_t data) 3616 { 3617 struct dc_softc *sc = ifp->if_softc; 3618 struct ifreq *ifr = (struct ifreq *)data; 3619 struct mii_data *mii; 3620 int error = 0; 3621 3622 DC_LOCK(sc); 3623 3624 switch (command) { 3625 case SIOCSIFFLAGS: 3626 if (ifp->if_flags & IFF_UP) { 3627 int need_setfilt = (ifp->if_flags ^ sc->dc_if_flags) & 3628 (IFF_PROMISC | IFF_ALLMULTI); 3629 3630 if (ifp->if_flags & IFF_RUNNING) { 3631 if (need_setfilt) 3632 dc_setfilt(sc); 3633 } else { 3634 sc->dc_txthresh = 0; 3635 dc_init(sc); 3636 } 3637 } else { 3638 if (ifp->if_flags & IFF_RUNNING) 3639 dc_stop(sc); 3640 } 3641 sc->dc_if_flags = ifp->if_flags; 3642 error = 0; 3643 break; 3644 case SIOCADDMULTI: 3645 case SIOCDELMULTI: 3646 dc_setfilt(sc); 3647 error = 0; 3648 break; 3649 case SIOCGIFMEDIA: 3650 case SIOCSIFMEDIA: 3651 mii = device_get_softc(sc->dc_miibus); 3652 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 3653 #ifdef SRM_MEDIA 3654 if (sc->dc_srm_media) 3655 sc->dc_srm_media = 0; 3656 #endif 3657 break; 3658 case SIOCSIFCAP: 3659 ifp->if_capenable &= ~IFCAP_POLLING; 3660 ifp->if_capenable |= ifr->ifr_reqcap & IFCAP_POLLING; 3661 break; 3662 default: 3663 error = ether_ioctl(ifp, command, data); 3664 break; 3665 } 3666 3667 DC_UNLOCK(sc); 3668 3669 return (error); 3670 } 3671 3672 static void 3673 dc_watchdog(struct ifnet *ifp) 3674 { 3675 struct dc_softc *sc; 3676 3677 sc = ifp->if_softc; 3678 3679 DC_LOCK(sc); 3680 3681 ifp->if_oerrors++; 3682 printf("dc%d: watchdog timeout\n", sc->dc_unit); 3683 3684 dc_stop(sc); 3685 dc_reset(sc); 3686 dc_init(sc); 3687 3688 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 3689 dc_start(ifp); 3690 3691 DC_UNLOCK(sc); 3692 } 3693 3694 /* 3695 * Stop the adapter and free any mbufs allocated to the 3696 * RX and TX lists. 3697 */ 3698 static void 3699 dc_stop(struct dc_softc *sc) 3700 { 3701 struct ifnet *ifp; 3702 struct dc_list_data *ld; 3703 struct dc_chain_data *cd; 3704 int i; 3705 u_int32_t ctl; 3706 3707 DC_LOCK(sc); 3708 3709 ifp = &sc->arpcom.ac_if; 3710 ifp->if_timer = 0; 3711 ld = sc->dc_ldata; 3712 cd = &sc->dc_cdata; 3713 3714 callout_stop(&sc->dc_stat_ch); 3715 3716 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 3717 #ifdef DEVICE_POLLING 3718 ether_poll_deregister(ifp); 3719 #endif 3720 3721 DC_CLRBIT(sc, DC_NETCFG, (DC_NETCFG_RX_ON | DC_NETCFG_TX_ON)); 3722 CSR_WRITE_4(sc, DC_IMR, 0x00000000); 3723 CSR_WRITE_4(sc, DC_TXADDR, 0x00000000); 3724 CSR_WRITE_4(sc, DC_RXADDR, 0x00000000); 3725 sc->dc_link = 0; 3726 3727 /* 3728 * Free data in the RX lists. 3729 */ 3730 for (i = 0; i < DC_RX_LIST_CNT; i++) { 3731 if (cd->dc_rx_chain[i] != NULL) { 3732 m_freem(cd->dc_rx_chain[i]); 3733 cd->dc_rx_chain[i] = NULL; 3734 } 3735 } 3736 bzero(&ld->dc_rx_list, sizeof(ld->dc_rx_list)); 3737 3738 /* 3739 * Free the TX list buffers. 3740 */ 3741 for (i = 0; i < DC_TX_LIST_CNT; i++) { 3742 if (cd->dc_tx_chain[i] != NULL) { 3743 ctl = le32toh(ld->dc_tx_list[i].dc_ctl); 3744 if ((ctl & DC_TXCTL_SETUP) || 3745 !(ctl & DC_TXCTL_LASTFRAG)) { 3746 cd->dc_tx_chain[i] = NULL; 3747 continue; 3748 } 3749 bus_dmamap_unload(sc->dc_mtag, cd->dc_tx_map[i]); 3750 m_freem(cd->dc_tx_chain[i]); 3751 cd->dc_tx_chain[i] = NULL; 3752 } 3753 } 3754 bzero(&ld->dc_tx_list, sizeof(ld->dc_tx_list)); 3755 3756 DC_UNLOCK(sc); 3757 } 3758 3759 /* 3760 * Device suspend routine. Stop the interface and save some PCI 3761 * settings in case the BIOS doesn't restore them properly on 3762 * resume. 3763 */ 3764 static int 3765 dc_suspend(device_t dev) 3766 { 3767 struct dc_softc *sc; 3768 int s; 3769 3770 s = splimp(); 3771 3772 sc = device_get_softc(dev); 3773 dc_stop(sc); 3774 sc->suspended = 1; 3775 3776 splx(s); 3777 return (0); 3778 } 3779 3780 /* 3781 * Device resume routine. Restore some PCI settings in case the BIOS 3782 * doesn't, re-enable busmastering, and restart the interface if 3783 * appropriate. 3784 */ 3785 static int 3786 dc_resume(device_t dev) 3787 { 3788 struct dc_softc *sc; 3789 struct ifnet *ifp; 3790 int s; 3791 3792 s = splimp(); 3793 3794 sc = device_get_softc(dev); 3795 ifp = &sc->arpcom.ac_if; 3796 3797 /* reinitialize interface if necessary */ 3798 if (ifp->if_flags & IFF_UP) 3799 dc_init(sc); 3800 3801 sc->suspended = 0; 3802 3803 splx(s); 3804 return (0); 3805 } 3806 3807 /* 3808 * Stop all chip I/O so that the kernel's probe routines don't 3809 * get confused by errant DMAs when rebooting. 3810 */ 3811 static void 3812 dc_shutdown(device_t dev) 3813 { 3814 struct dc_softc *sc; 3815 3816 sc = device_get_softc(dev); 3817 3818 dc_stop(sc); 3819 } 3820