1 /* 2 * Copyright (c) 1997, 1998, 1999 3 * Bill Paul <wpaul@ee.columbia.edu>. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 3. All advertising materials mentioning features or use of this software 14 * must display the following acknowledgement: 15 * This product includes software developed by Bill Paul. 16 * 4. Neither the name of the author nor the names of any co-contributors 17 * may be used to endorse or promote products derived from this software 18 * without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30 * THE POSSIBILITY OF SUCH DAMAGE. 31 * 32 * $FreeBSD$ 33 */ 34 35 /* 36 * DEC "tulip" clone ethernet driver. Supports the DEC/Intel 21143 37 * series chips and several workalikes including the following: 38 * 39 * Macronix 98713/98715/98725/98727/98732 PMAC (www.macronix.com) 40 * Macronix/Lite-On 82c115 PNIC II (www.macronix.com) 41 * Lite-On 82c168/82c169 PNIC (www.litecom.com) 42 * ASIX Electronics AX88140A (www.asix.com.tw) 43 * ASIX Electronics AX88141 (www.asix.com.tw) 44 * ADMtek AL981 (www.admtek.com.tw) 45 * ADMtek AN985 (www.admtek.com.tw) 46 * Davicom DM9100, DM9102, DM9102A (www.davicom8.com) 47 * Accton EN1217 (www.accton.com) 48 * Xircom X3201 (www.xircom.com) 49 * Abocom FE2500 50 * 51 * Datasheets for the 21143 are available at developer.intel.com. 52 * Datasheets for the clone parts can be found at their respective sites. 53 * (Except for the PNIC; see www.freebsd.org/~wpaul/PNIC/pnic.ps.gz.) 54 * The PNIC II is essentially a Macronix 98715A chip; the only difference 55 * worth noting is that its multicast hash table is only 128 bits wide 56 * instead of 512. 57 * 58 * Written by Bill Paul <wpaul@ee.columbia.edu> 59 * Electrical Engineering Department 60 * Columbia University, New York City 61 */ 62 63 /* 64 * The Intel 21143 is the successor to the DEC 21140. It is basically 65 * the same as the 21140 but with a few new features. The 21143 supports 66 * three kinds of media attachments: 67 * 68 * o MII port, for 10Mbps and 100Mbps support and NWAY 69 * autonegotiation provided by an external PHY. 70 * o SYM port, for symbol mode 100Mbps support. 71 * o 10baseT port. 72 * o AUI/BNC port. 73 * 74 * The 100Mbps SYM port and 10baseT port can be used together in 75 * combination with the internal NWAY support to create a 10/100 76 * autosensing configuration. 77 * 78 * Note that not all tulip workalikes are handled in this driver: we only 79 * deal with those which are relatively well behaved. The Winbond is 80 * handled separately due to its different register offsets and the 81 * special handling needed for its various bugs. The PNIC is handled 82 * here, but I'm not thrilled about it. 83 * 84 * All of the workalike chips use some form of MII transceiver support 85 * with the exception of the Macronix chips, which also have a SYM port. 86 * The ASIX AX88140A is also documented to have a SYM port, but all 87 * the cards I've seen use an MII transceiver, probably because the 88 * AX88140A doesn't support internal NWAY. 89 */ 90 91 #include <sys/param.h> 92 #include <sys/systm.h> 93 #include <sys/sockio.h> 94 #include <sys/mbuf.h> 95 #include <sys/malloc.h> 96 #include <sys/kernel.h> 97 #include <sys/socket.h> 98 99 #include <net/if.h> 100 #include <net/if_arp.h> 101 #include <net/ethernet.h> 102 #include <net/if_dl.h> 103 #include <net/if_media.h> 104 105 #include <net/bpf.h> 106 107 #include <vm/vm.h> /* for vtophys */ 108 #include <vm/pmap.h> /* for vtophys */ 109 #include <machine/bus_pio.h> 110 #include <machine/bus_memio.h> 111 #include <machine/bus.h> 112 #include <machine/resource.h> 113 #include <sys/bus.h> 114 #include <sys/rman.h> 115 116 #include <dev/mii/mii.h> 117 #include <dev/mii/miivar.h> 118 119 #include <pci/pcireg.h> 120 #include <pci/pcivar.h> 121 122 #define DC_USEIOSPACE 123 #ifdef __alpha__ 124 #define SRM_MEDIA 125 #endif 126 127 #include <pci/if_dcreg.h> 128 129 MODULE_DEPEND(dc, miibus, 1, 1, 1); 130 131 /* "controller miibus0" required. See GENERIC if you get errors here. */ 132 #include "miibus_if.h" 133 134 #ifndef lint 135 static const char rcsid[] = 136 "$FreeBSD$"; 137 #endif 138 139 /* 140 * Various supported device vendors/types and their names. 141 */ 142 static struct dc_type dc_devs[] = { 143 { DC_VENDORID_DEC, DC_DEVICEID_21143, 144 "Intel 21143 10/100BaseTX" }, 145 { DC_VENDORID_DAVICOM, DC_DEVICEID_DM9100, 146 "Davicom DM9100 10/100BaseTX" }, 147 { DC_VENDORID_DAVICOM, DC_DEVICEID_DM9102, 148 "Davicom DM9102 10/100BaseTX" }, 149 { DC_VENDORID_DAVICOM, DC_DEVICEID_DM9102, 150 "Davicom DM9102A 10/100BaseTX" }, 151 { DC_VENDORID_ADMTEK, DC_DEVICEID_AL981, 152 "ADMtek AL981 10/100BaseTX" }, 153 { DC_VENDORID_ADMTEK, DC_DEVICEID_AN985, 154 "ADMtek AN985 10/100BaseTX" }, 155 { DC_VENDORID_ASIX, DC_DEVICEID_AX88140A, 156 "ASIX AX88140A 10/100BaseTX" }, 157 { DC_VENDORID_ASIX, DC_DEVICEID_AX88140A, 158 "ASIX AX88141 10/100BaseTX" }, 159 { DC_VENDORID_MX, DC_DEVICEID_98713, 160 "Macronix 98713 10/100BaseTX" }, 161 { DC_VENDORID_MX, DC_DEVICEID_98713, 162 "Macronix 98713A 10/100BaseTX" }, 163 { DC_VENDORID_CP, DC_DEVICEID_98713_CP, 164 "Compex RL100-TX 10/100BaseTX" }, 165 { DC_VENDORID_CP, DC_DEVICEID_98713_CP, 166 "Compex RL100-TX 10/100BaseTX" }, 167 { DC_VENDORID_MX, DC_DEVICEID_987x5, 168 "Macronix 98715/98715A 10/100BaseTX" }, 169 { DC_VENDORID_MX, DC_DEVICEID_987x5, 170 "Macronix 98715AEC-C 10/100BaseTX" }, 171 { DC_VENDORID_MX, DC_DEVICEID_987x5, 172 "Macronix 98725 10/100BaseTX" }, 173 { DC_VENDORID_MX, DC_DEVICEID_98727, 174 "Macronix 98727/98732 10/100BaseTX" }, 175 { DC_VENDORID_LO, DC_DEVICEID_82C115, 176 "LC82C115 PNIC II 10/100BaseTX" }, 177 { DC_VENDORID_LO, DC_DEVICEID_82C168, 178 "82c168 PNIC 10/100BaseTX" }, 179 { DC_VENDORID_LO, DC_DEVICEID_82C168, 180 "82c169 PNIC 10/100BaseTX" }, 181 { DC_VENDORID_ACCTON, DC_DEVICEID_EN1217, 182 "Accton EN1217 10/100BaseTX" }, 183 { DC_VENDORID_ACCTON, DC_DEVICEID_EN2242, 184 "Accton EN2242 MiniPCI 10/100BaseTX" }, 185 { DC_VENDORID_XIRCOM, DC_DEVICEID_X3201, 186 "Xircom X3201 10/100BaseTX" }, 187 { DC_VENDORID_ABOCOM, DC_DEVICEID_FE2500, 188 "Abocom FE2500 10/100BaseTX" }, 189 { 0, 0, NULL } 190 }; 191 192 static int dc_probe __P((device_t)); 193 static int dc_attach __P((device_t)); 194 static int dc_detach __P((device_t)); 195 static void dc_acpi __P((device_t)); 196 static struct dc_type *dc_devtype __P((device_t)); 197 static int dc_newbuf __P((struct dc_softc *, int, struct mbuf *)); 198 static int dc_encap __P((struct dc_softc *, struct mbuf *, 199 u_int32_t *)); 200 static int dc_coal __P((struct dc_softc *, struct mbuf **)); 201 static void dc_pnic_rx_bug_war __P((struct dc_softc *, int)); 202 static int dc_rx_resync __P((struct dc_softc *)); 203 static void dc_rxeof __P((struct dc_softc *)); 204 static void dc_txeof __P((struct dc_softc *)); 205 static void dc_tick __P((void *)); 206 static void dc_intr __P((void *)); 207 static void dc_start __P((struct ifnet *)); 208 static int dc_ioctl __P((struct ifnet *, u_long, caddr_t)); 209 static void dc_init __P((void *)); 210 static void dc_stop __P((struct dc_softc *)); 211 static void dc_watchdog __P((struct ifnet *)); 212 static void dc_shutdown __P((device_t)); 213 static int dc_ifmedia_upd __P((struct ifnet *)); 214 static void dc_ifmedia_sts __P((struct ifnet *, struct ifmediareq *)); 215 216 static void dc_delay __P((struct dc_softc *)); 217 static void dc_eeprom_idle __P((struct dc_softc *)); 218 static void dc_eeprom_putbyte __P((struct dc_softc *, int)); 219 static void dc_eeprom_getword __P((struct dc_softc *, int, u_int16_t *)); 220 static void dc_eeprom_getword_pnic 221 __P((struct dc_softc *, int, u_int16_t *)); 222 static void dc_eeprom_getword_xircom 223 __P((struct dc_softc *, int, u_int16_t *)); 224 static void dc_read_eeprom __P((struct dc_softc *, caddr_t, int, 225 int, int)); 226 227 static void dc_mii_writebit __P((struct dc_softc *, int)); 228 static int dc_mii_readbit __P((struct dc_softc *)); 229 static void dc_mii_sync __P((struct dc_softc *)); 230 static void dc_mii_send __P((struct dc_softc *, u_int32_t, int)); 231 static int dc_mii_readreg __P((struct dc_softc *, struct dc_mii_frame *)); 232 static int dc_mii_writereg __P((struct dc_softc *, struct dc_mii_frame *)); 233 static int dc_miibus_readreg __P((device_t, int, int)); 234 static int dc_miibus_writereg __P((device_t, int, int, int)); 235 static void dc_miibus_statchg __P((device_t)); 236 static void dc_miibus_mediainit __P((device_t)); 237 238 static void dc_setcfg __P((struct dc_softc *, int)); 239 static u_int32_t dc_crc_le __P((struct dc_softc *, caddr_t)); 240 static u_int32_t dc_crc_be __P((caddr_t)); 241 static void dc_setfilt_21143 __P((struct dc_softc *)); 242 static void dc_setfilt_asix __P((struct dc_softc *)); 243 static void dc_setfilt_admtek __P((struct dc_softc *)); 244 static void dc_setfilt_xircom __P((struct dc_softc *)); 245 246 static void dc_setfilt __P((struct dc_softc *)); 247 248 static void dc_reset __P((struct dc_softc *)); 249 static int dc_list_rx_init __P((struct dc_softc *)); 250 static int dc_list_tx_init __P((struct dc_softc *)); 251 252 static void dc_parse_21143_srom __P((struct dc_softc *)); 253 static void dc_decode_leaf_sia __P((struct dc_softc *, 254 struct dc_eblock_sia *)); 255 static void dc_decode_leaf_mii __P((struct dc_softc *, 256 struct dc_eblock_mii *)); 257 static void dc_decode_leaf_sym __P((struct dc_softc *, 258 struct dc_eblock_sym *)); 259 static void dc_apply_fixup __P((struct dc_softc *, int)); 260 261 #ifdef DC_USEIOSPACE 262 #define DC_RES SYS_RES_IOPORT 263 #define DC_RID DC_PCI_CFBIO 264 #else 265 #define DC_RES SYS_RES_MEMORY 266 #define DC_RID DC_PCI_CFBMA 267 #endif 268 269 static device_method_t dc_methods[] = { 270 /* Device interface */ 271 DEVMETHOD(device_probe, dc_probe), 272 DEVMETHOD(device_attach, dc_attach), 273 DEVMETHOD(device_detach, dc_detach), 274 DEVMETHOD(device_shutdown, dc_shutdown), 275 276 /* bus interface */ 277 DEVMETHOD(bus_print_child, bus_generic_print_child), 278 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 279 280 /* MII interface */ 281 DEVMETHOD(miibus_readreg, dc_miibus_readreg), 282 DEVMETHOD(miibus_writereg, dc_miibus_writereg), 283 DEVMETHOD(miibus_statchg, dc_miibus_statchg), 284 DEVMETHOD(miibus_mediainit, dc_miibus_mediainit), 285 286 { 0, 0 } 287 }; 288 289 static driver_t dc_driver = { 290 "dc", 291 dc_methods, 292 sizeof(struct dc_softc) 293 }; 294 295 static devclass_t dc_devclass; 296 297 DRIVER_MODULE(if_dc, cardbus, dc_driver, dc_devclass, 0, 0); 298 DRIVER_MODULE(if_dc, pci, dc_driver, dc_devclass, 0, 0); 299 DRIVER_MODULE(miibus, dc, miibus_driver, miibus_devclass, 0, 0); 300 301 #define DC_SETBIT(sc, reg, x) \ 302 CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) | (x)) 303 304 #define DC_CLRBIT(sc, reg, x) \ 305 CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) & ~(x)) 306 307 #define SIO_SET(x) DC_SETBIT(sc, DC_SIO, (x)) 308 #define SIO_CLR(x) DC_CLRBIT(sc, DC_SIO, (x)) 309 310 #define IS_MPSAFE 0 311 312 static void dc_delay(sc) 313 struct dc_softc *sc; 314 { 315 int idx; 316 317 for (idx = (300 / 33) + 1; idx > 0; idx--) 318 CSR_READ_4(sc, DC_BUSCTL); 319 } 320 321 static void dc_eeprom_idle(sc) 322 struct dc_softc *sc; 323 { 324 register int i; 325 326 CSR_WRITE_4(sc, DC_SIO, DC_SIO_EESEL); 327 dc_delay(sc); 328 DC_SETBIT(sc, DC_SIO, DC_SIO_ROMCTL_READ); 329 dc_delay(sc); 330 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); 331 dc_delay(sc); 332 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CS); 333 dc_delay(sc); 334 335 for (i = 0; i < 25; i++) { 336 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); 337 dc_delay(sc); 338 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CLK); 339 dc_delay(sc); 340 } 341 342 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); 343 dc_delay(sc); 344 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CS); 345 dc_delay(sc); 346 CSR_WRITE_4(sc, DC_SIO, 0x00000000); 347 348 return; 349 } 350 351 /* 352 * Send a read command and address to the EEPROM, check for ACK. 353 */ 354 static void dc_eeprom_putbyte(sc, addr) 355 struct dc_softc *sc; 356 int addr; 357 { 358 register int d, i; 359 360 /* 361 * The AN985 has a 93C66 EEPROM on it instead of 362 * a 93C46. It uses a different bit sequence for 363 * specifying the "read" opcode. 364 */ 365 if (DC_IS_CENTAUR(sc)) 366 d = addr | (DC_EECMD_READ << 2); 367 else 368 d = addr | DC_EECMD_READ; 369 370 /* 371 * Feed in each bit and strobe the clock. 372 */ 373 for (i = 0x400; i; i >>= 1) { 374 if (d & i) { 375 SIO_SET(DC_SIO_EE_DATAIN); 376 } else { 377 SIO_CLR(DC_SIO_EE_DATAIN); 378 } 379 dc_delay(sc); 380 SIO_SET(DC_SIO_EE_CLK); 381 dc_delay(sc); 382 SIO_CLR(DC_SIO_EE_CLK); 383 dc_delay(sc); 384 } 385 386 return; 387 } 388 389 /* 390 * Read a word of data stored in the EEPROM at address 'addr.' 391 * The PNIC 82c168/82c169 has its own non-standard way to read 392 * the EEPROM. 393 */ 394 static void dc_eeprom_getword_pnic(sc, addr, dest) 395 struct dc_softc *sc; 396 int addr; 397 u_int16_t *dest; 398 { 399 register int i; 400 u_int32_t r; 401 402 CSR_WRITE_4(sc, DC_PN_SIOCTL, DC_PN_EEOPCODE_READ|addr); 403 404 for (i = 0; i < DC_TIMEOUT; i++) { 405 DELAY(1); 406 r = CSR_READ_4(sc, DC_SIO); 407 if (!(r & DC_PN_SIOCTL_BUSY)) { 408 *dest = (u_int16_t)(r & 0xFFFF); 409 return; 410 } 411 } 412 413 return; 414 } 415 416 /* 417 * Read a word of data stored in the EEPROM at address 'addr.' 418 * The Xircom X3201 has its own non-standard way to read 419 * the EEPROM, too. 420 */ 421 static void dc_eeprom_getword_xircom(sc, addr, dest) 422 struct dc_softc *sc; 423 int addr; 424 u_int16_t *dest; 425 { 426 SIO_SET(DC_SIO_ROMSEL | DC_SIO_ROMCTL_READ); 427 428 addr *= 2; 429 CSR_WRITE_4(sc, DC_ROM, addr | 0x160); 430 *dest = (u_int16_t)CSR_READ_4(sc, DC_SIO)&0xff; 431 addr += 1; 432 CSR_WRITE_4(sc, DC_ROM, addr | 0x160); 433 *dest |= ((u_int16_t)CSR_READ_4(sc, DC_SIO)&0xff) << 8; 434 435 SIO_CLR(DC_SIO_ROMSEL | DC_SIO_ROMCTL_READ); 436 return; 437 } 438 439 /* 440 * Read a word of data stored in the EEPROM at address 'addr.' 441 */ 442 static void dc_eeprom_getword(sc, addr, dest) 443 struct dc_softc *sc; 444 int addr; 445 u_int16_t *dest; 446 { 447 register int i; 448 u_int16_t word = 0; 449 450 /* Force EEPROM to idle state. */ 451 dc_eeprom_idle(sc); 452 453 /* Enter EEPROM access mode. */ 454 CSR_WRITE_4(sc, DC_SIO, DC_SIO_EESEL); 455 dc_delay(sc); 456 DC_SETBIT(sc, DC_SIO, DC_SIO_ROMCTL_READ); 457 dc_delay(sc); 458 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); 459 dc_delay(sc); 460 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CS); 461 dc_delay(sc); 462 463 /* 464 * Send address of word we want to read. 465 */ 466 dc_eeprom_putbyte(sc, addr); 467 468 /* 469 * Start reading bits from EEPROM. 470 */ 471 for (i = 0x8000; i; i >>= 1) { 472 SIO_SET(DC_SIO_EE_CLK); 473 dc_delay(sc); 474 if (CSR_READ_4(sc, DC_SIO) & DC_SIO_EE_DATAOUT) 475 word |= i; 476 dc_delay(sc); 477 SIO_CLR(DC_SIO_EE_CLK); 478 dc_delay(sc); 479 } 480 481 /* Turn off EEPROM access mode. */ 482 dc_eeprom_idle(sc); 483 484 *dest = word; 485 486 return; 487 } 488 489 /* 490 * Read a sequence of words from the EEPROM. 491 */ 492 static void dc_read_eeprom(sc, dest, off, cnt, swap) 493 struct dc_softc *sc; 494 caddr_t dest; 495 int off; 496 int cnt; 497 int swap; 498 { 499 int i; 500 u_int16_t word = 0, *ptr; 501 502 for (i = 0; i < cnt; i++) { 503 if (DC_IS_PNIC(sc)) 504 dc_eeprom_getword_pnic(sc, off + i, &word); 505 else if (DC_IS_XIRCOM(sc)) 506 dc_eeprom_getword_xircom(sc, off + i, &word); 507 else 508 dc_eeprom_getword(sc, off + i, &word); 509 ptr = (u_int16_t *)(dest + (i * 2)); 510 if (swap) 511 *ptr = ntohs(word); 512 else 513 *ptr = word; 514 } 515 516 return; 517 } 518 519 /* 520 * The following two routines are taken from the Macronix 98713 521 * Application Notes pp.19-21. 522 */ 523 /* 524 * Write a bit to the MII bus. 525 */ 526 static void dc_mii_writebit(sc, bit) 527 struct dc_softc *sc; 528 int bit; 529 { 530 if (bit) 531 CSR_WRITE_4(sc, DC_SIO, 532 DC_SIO_ROMCTL_WRITE|DC_SIO_MII_DATAOUT); 533 else 534 CSR_WRITE_4(sc, DC_SIO, DC_SIO_ROMCTL_WRITE); 535 536 DC_SETBIT(sc, DC_SIO, DC_SIO_MII_CLK); 537 DC_CLRBIT(sc, DC_SIO, DC_SIO_MII_CLK); 538 539 return; 540 } 541 542 /* 543 * Read a bit from the MII bus. 544 */ 545 static int dc_mii_readbit(sc) 546 struct dc_softc *sc; 547 { 548 CSR_WRITE_4(sc, DC_SIO, DC_SIO_ROMCTL_READ|DC_SIO_MII_DIR); 549 CSR_READ_4(sc, DC_SIO); 550 DC_SETBIT(sc, DC_SIO, DC_SIO_MII_CLK); 551 DC_CLRBIT(sc, DC_SIO, DC_SIO_MII_CLK); 552 if (CSR_READ_4(sc, DC_SIO) & DC_SIO_MII_DATAIN) 553 return(1); 554 555 return(0); 556 } 557 558 /* 559 * Sync the PHYs by setting data bit and strobing the clock 32 times. 560 */ 561 static void dc_mii_sync(sc) 562 struct dc_softc *sc; 563 { 564 register int i; 565 566 CSR_WRITE_4(sc, DC_SIO, DC_SIO_ROMCTL_WRITE); 567 568 for (i = 0; i < 32; i++) 569 dc_mii_writebit(sc, 1); 570 571 return; 572 } 573 574 /* 575 * Clock a series of bits through the MII. 576 */ 577 static void dc_mii_send(sc, bits, cnt) 578 struct dc_softc *sc; 579 u_int32_t bits; 580 int cnt; 581 { 582 int i; 583 584 for (i = (0x1 << (cnt - 1)); i; i >>= 1) 585 dc_mii_writebit(sc, bits & i); 586 } 587 588 /* 589 * Read an PHY register through the MII. 590 */ 591 static int dc_mii_readreg(sc, frame) 592 struct dc_softc *sc; 593 struct dc_mii_frame *frame; 594 595 { 596 int i, ack; 597 598 DC_LOCK(sc); 599 600 /* 601 * Set up frame for RX. 602 */ 603 frame->mii_stdelim = DC_MII_STARTDELIM; 604 frame->mii_opcode = DC_MII_READOP; 605 frame->mii_turnaround = 0; 606 frame->mii_data = 0; 607 608 /* 609 * Sync the PHYs. 610 */ 611 dc_mii_sync(sc); 612 613 /* 614 * Send command/address info. 615 */ 616 dc_mii_send(sc, frame->mii_stdelim, 2); 617 dc_mii_send(sc, frame->mii_opcode, 2); 618 dc_mii_send(sc, frame->mii_phyaddr, 5); 619 dc_mii_send(sc, frame->mii_regaddr, 5); 620 621 #ifdef notdef 622 /* Idle bit */ 623 dc_mii_writebit(sc, 1); 624 dc_mii_writebit(sc, 0); 625 #endif 626 627 /* Check for ack */ 628 ack = dc_mii_readbit(sc); 629 630 /* 631 * Now try reading data bits. If the ack failed, we still 632 * need to clock through 16 cycles to keep the PHY(s) in sync. 633 */ 634 if (ack) { 635 for(i = 0; i < 16; i++) { 636 dc_mii_readbit(sc); 637 } 638 goto fail; 639 } 640 641 for (i = 0x8000; i; i >>= 1) { 642 if (!ack) { 643 if (dc_mii_readbit(sc)) 644 frame->mii_data |= i; 645 } 646 } 647 648 fail: 649 650 dc_mii_writebit(sc, 0); 651 dc_mii_writebit(sc, 0); 652 653 DC_UNLOCK(sc); 654 655 if (ack) 656 return(1); 657 return(0); 658 } 659 660 /* 661 * Write to a PHY register through the MII. 662 */ 663 static int dc_mii_writereg(sc, frame) 664 struct dc_softc *sc; 665 struct dc_mii_frame *frame; 666 667 { 668 DC_LOCK(sc); 669 /* 670 * Set up frame for TX. 671 */ 672 673 frame->mii_stdelim = DC_MII_STARTDELIM; 674 frame->mii_opcode = DC_MII_WRITEOP; 675 frame->mii_turnaround = DC_MII_TURNAROUND; 676 677 /* 678 * Sync the PHYs. 679 */ 680 dc_mii_sync(sc); 681 682 dc_mii_send(sc, frame->mii_stdelim, 2); 683 dc_mii_send(sc, frame->mii_opcode, 2); 684 dc_mii_send(sc, frame->mii_phyaddr, 5); 685 dc_mii_send(sc, frame->mii_regaddr, 5); 686 dc_mii_send(sc, frame->mii_turnaround, 2); 687 dc_mii_send(sc, frame->mii_data, 16); 688 689 /* Idle bit. */ 690 dc_mii_writebit(sc, 0); 691 dc_mii_writebit(sc, 0); 692 693 DC_UNLOCK(sc); 694 695 return(0); 696 } 697 698 static int dc_miibus_readreg(dev, phy, reg) 699 device_t dev; 700 int phy, reg; 701 { 702 struct dc_mii_frame frame; 703 struct dc_softc *sc; 704 int i, rval, phy_reg; 705 706 sc = device_get_softc(dev); 707 bzero((char *)&frame, sizeof(frame)); 708 709 /* 710 * Note: both the AL981 and AN985 have internal PHYs, 711 * however the AL981 provides direct access to the PHY 712 * registers while the AN985 uses a serial MII interface. 713 * The AN985's MII interface is also buggy in that you 714 * can read from any MII address (0 to 31), but only address 1 715 * behaves normally. To deal with both cases, we pretend 716 * that the PHY is at MII address 1. 717 */ 718 if (DC_IS_ADMTEK(sc) && phy != DC_ADMTEK_PHYADDR) 719 return(0); 720 721 if (sc->dc_pmode != DC_PMODE_MII) { 722 if (phy == (MII_NPHY - 1)) { 723 switch(reg) { 724 case MII_BMSR: 725 /* 726 * Fake something to make the probe 727 * code think there's a PHY here. 728 */ 729 return(BMSR_MEDIAMASK); 730 break; 731 case MII_PHYIDR1: 732 if (DC_IS_PNIC(sc)) 733 return(DC_VENDORID_LO); 734 return(DC_VENDORID_DEC); 735 break; 736 case MII_PHYIDR2: 737 if (DC_IS_PNIC(sc)) 738 return(DC_DEVICEID_82C168); 739 return(DC_DEVICEID_21143); 740 break; 741 default: 742 return(0); 743 break; 744 } 745 } else 746 return(0); 747 } 748 749 if (DC_IS_PNIC(sc)) { 750 CSR_WRITE_4(sc, DC_PN_MII, DC_PN_MIIOPCODE_READ | 751 (phy << 23) | (reg << 18)); 752 for (i = 0; i < DC_TIMEOUT; i++) { 753 DELAY(1); 754 rval = CSR_READ_4(sc, DC_PN_MII); 755 if (!(rval & DC_PN_MII_BUSY)) { 756 rval &= 0xFFFF; 757 return(rval == 0xFFFF ? 0 : rval); 758 } 759 } 760 return(0); 761 } 762 763 if (DC_IS_COMET(sc)) { 764 switch(reg) { 765 case MII_BMCR: 766 phy_reg = DC_AL_BMCR; 767 break; 768 case MII_BMSR: 769 phy_reg = DC_AL_BMSR; 770 break; 771 case MII_PHYIDR1: 772 phy_reg = DC_AL_VENID; 773 break; 774 case MII_PHYIDR2: 775 phy_reg = DC_AL_DEVID; 776 break; 777 case MII_ANAR: 778 phy_reg = DC_AL_ANAR; 779 break; 780 case MII_ANLPAR: 781 phy_reg = DC_AL_LPAR; 782 break; 783 case MII_ANER: 784 phy_reg = DC_AL_ANER; 785 break; 786 default: 787 printf("dc%d: phy_read: bad phy register %x\n", 788 sc->dc_unit, reg); 789 return(0); 790 break; 791 } 792 793 rval = CSR_READ_4(sc, phy_reg) & 0x0000FFFF; 794 795 if (rval == 0xFFFF) 796 return(0); 797 return(rval); 798 } 799 800 frame.mii_phyaddr = phy; 801 frame.mii_regaddr = reg; 802 phy_reg = CSR_READ_4(sc, DC_NETCFG); 803 CSR_WRITE_4(sc, DC_NETCFG, phy_reg & ~DC_NETCFG_PORTSEL); 804 dc_mii_readreg(sc, &frame); 805 CSR_WRITE_4(sc, DC_NETCFG, phy_reg); 806 807 return(frame.mii_data); 808 } 809 810 static int dc_miibus_writereg(dev, phy, reg, data) 811 device_t dev; 812 int phy, reg, data; 813 { 814 struct dc_softc *sc; 815 struct dc_mii_frame frame; 816 int i, phy_reg; 817 818 sc = device_get_softc(dev); 819 bzero((char *)&frame, sizeof(frame)); 820 821 if (DC_IS_ADMTEK(sc) && phy != DC_ADMTEK_PHYADDR) 822 return(0); 823 824 if (DC_IS_PNIC(sc)) { 825 CSR_WRITE_4(sc, DC_PN_MII, DC_PN_MIIOPCODE_WRITE | 826 (phy << 23) | (reg << 10) | data); 827 for (i = 0; i < DC_TIMEOUT; i++) { 828 if (!(CSR_READ_4(sc, DC_PN_MII) & DC_PN_MII_BUSY)) 829 break; 830 } 831 return(0); 832 } 833 834 if (DC_IS_COMET(sc)) { 835 switch(reg) { 836 case MII_BMCR: 837 phy_reg = DC_AL_BMCR; 838 break; 839 case MII_BMSR: 840 phy_reg = DC_AL_BMSR; 841 break; 842 case MII_PHYIDR1: 843 phy_reg = DC_AL_VENID; 844 break; 845 case MII_PHYIDR2: 846 phy_reg = DC_AL_DEVID; 847 break; 848 case MII_ANAR: 849 phy_reg = DC_AL_ANAR; 850 break; 851 case MII_ANLPAR: 852 phy_reg = DC_AL_LPAR; 853 break; 854 case MII_ANER: 855 phy_reg = DC_AL_ANER; 856 break; 857 default: 858 printf("dc%d: phy_write: bad phy register %x\n", 859 sc->dc_unit, reg); 860 return(0); 861 break; 862 } 863 864 CSR_WRITE_4(sc, phy_reg, data); 865 return(0); 866 } 867 868 frame.mii_phyaddr = phy; 869 frame.mii_regaddr = reg; 870 frame.mii_data = data; 871 872 phy_reg = CSR_READ_4(sc, DC_NETCFG); 873 CSR_WRITE_4(sc, DC_NETCFG, phy_reg & ~DC_NETCFG_PORTSEL); 874 dc_mii_writereg(sc, &frame); 875 CSR_WRITE_4(sc, DC_NETCFG, phy_reg); 876 877 return(0); 878 } 879 880 static void dc_miibus_statchg(dev) 881 device_t dev; 882 { 883 struct dc_softc *sc; 884 struct mii_data *mii; 885 struct ifmedia *ifm; 886 887 sc = device_get_softc(dev); 888 if (DC_IS_ADMTEK(sc)) 889 return; 890 891 mii = device_get_softc(sc->dc_miibus); 892 ifm = &mii->mii_media; 893 if (DC_IS_DAVICOM(sc) && 894 IFM_SUBTYPE(ifm->ifm_media) == IFM_homePNA) { 895 dc_setcfg(sc, ifm->ifm_media); 896 sc->dc_if_media = ifm->ifm_media; 897 } else { 898 dc_setcfg(sc, mii->mii_media_active); 899 sc->dc_if_media = mii->mii_media_active; 900 } 901 902 return; 903 } 904 905 /* 906 * Special support for DM9102A cards with HomePNA PHYs. Note: 907 * with the Davicom DM9102A/DM9801 eval board that I have, it seems 908 * to be impossible to talk to the management interface of the DM9801 909 * PHY (its MDIO pin is not connected to anything). Consequently, 910 * the driver has to just 'know' about the additional mode and deal 911 * with it itself. *sigh* 912 */ 913 static void dc_miibus_mediainit(dev) 914 device_t dev; 915 { 916 struct dc_softc *sc; 917 struct mii_data *mii; 918 struct ifmedia *ifm; 919 int rev; 920 921 rev = pci_read_config(dev, DC_PCI_CFRV, 4) & 0xFF; 922 923 sc = device_get_softc(dev); 924 mii = device_get_softc(sc->dc_miibus); 925 ifm = &mii->mii_media; 926 927 if (DC_IS_DAVICOM(sc) && rev >= DC_REVISION_DM9102A) 928 ifmedia_add(ifm, IFM_ETHER|IFM_homePNA, 0, NULL); 929 930 return; 931 } 932 933 #define DC_POLY 0xEDB88320 934 #define DC_BITS_512 9 935 #define DC_BITS_128 7 936 #define DC_BITS_64 6 937 938 static u_int32_t dc_crc_le(sc, addr) 939 struct dc_softc *sc; 940 caddr_t addr; 941 { 942 u_int32_t idx, bit, data, crc; 943 944 /* Compute CRC for the address value. */ 945 crc = 0xFFFFFFFF; /* initial value */ 946 947 for (idx = 0; idx < 6; idx++) { 948 for (data = *addr++, bit = 0; bit < 8; bit++, data >>= 1) 949 crc = (crc >> 1) ^ (((crc ^ data) & 1) ? DC_POLY : 0); 950 } 951 952 /* 953 * The hash table on the PNIC II and the MX98715AEC-C/D/E 954 * chips is only 128 bits wide. 955 */ 956 if (sc->dc_flags & DC_128BIT_HASH) 957 return (crc & ((1 << DC_BITS_128) - 1)); 958 959 /* The hash table on the MX98715BEC is only 64 bits wide. */ 960 if (sc->dc_flags & DC_64BIT_HASH) 961 return (crc & ((1 << DC_BITS_64) - 1)); 962 963 /* Xircom's hash filtering table is different (read: weird) */ 964 /* Xircom uses the LEAST significant bits */ 965 if (DC_IS_XIRCOM(sc)) { 966 if ((crc & 0x180) == 0x180) 967 return (crc & 0x0F) + (crc & 0x70)*3 + (14 << 4); 968 else 969 return (crc & 0x1F) + ((crc>>1) & 0xF0)*3 + (12 << 4); 970 } 971 972 return (crc & ((1 << DC_BITS_512) - 1)); 973 } 974 975 /* 976 * Calculate CRC of a multicast group address, return the lower 6 bits. 977 */ 978 static u_int32_t dc_crc_be(addr) 979 caddr_t addr; 980 { 981 u_int32_t crc, carry; 982 int i, j; 983 u_int8_t c; 984 985 /* Compute CRC for the address value. */ 986 crc = 0xFFFFFFFF; /* initial value */ 987 988 for (i = 0; i < 6; i++) { 989 c = *(addr + i); 990 for (j = 0; j < 8; j++) { 991 carry = ((crc & 0x80000000) ? 1 : 0) ^ (c & 0x01); 992 crc <<= 1; 993 c >>= 1; 994 if (carry) 995 crc = (crc ^ 0x04c11db6) | carry; 996 } 997 } 998 999 /* return the filter bit position */ 1000 return((crc >> 26) & 0x0000003F); 1001 } 1002 1003 /* 1004 * 21143-style RX filter setup routine. Filter programming is done by 1005 * downloading a special setup frame into the TX engine. 21143, Macronix, 1006 * PNIC, PNIC II and Davicom chips are programmed this way. 1007 * 1008 * We always program the chip using 'hash perfect' mode, i.e. one perfect 1009 * address (our node address) and a 512-bit hash filter for multicast 1010 * frames. We also sneak the broadcast address into the hash filter since 1011 * we need that too. 1012 */ 1013 void dc_setfilt_21143(sc) 1014 struct dc_softc *sc; 1015 { 1016 struct dc_desc *sframe; 1017 u_int32_t h, *sp; 1018 struct ifmultiaddr *ifma; 1019 struct ifnet *ifp; 1020 int i; 1021 1022 ifp = &sc->arpcom.ac_if; 1023 1024 i = sc->dc_cdata.dc_tx_prod; 1025 DC_INC(sc->dc_cdata.dc_tx_prod, DC_TX_LIST_CNT); 1026 sc->dc_cdata.dc_tx_cnt++; 1027 sframe = &sc->dc_ldata->dc_tx_list[i]; 1028 sp = (u_int32_t *)&sc->dc_cdata.dc_sbuf; 1029 bzero((char *)sp, DC_SFRAME_LEN); 1030 1031 sframe->dc_data = vtophys(&sc->dc_cdata.dc_sbuf); 1032 sframe->dc_ctl = DC_SFRAME_LEN | DC_TXCTL_SETUP | DC_TXCTL_TLINK | 1033 DC_FILTER_HASHPERF | DC_TXCTL_FINT; 1034 1035 sc->dc_cdata.dc_tx_chain[i] = (struct mbuf *)&sc->dc_cdata.dc_sbuf; 1036 1037 /* If we want promiscuous mode, set the allframes bit. */ 1038 if (ifp->if_flags & IFF_PROMISC) 1039 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC); 1040 else 1041 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC); 1042 1043 if (ifp->if_flags & IFF_ALLMULTI) 1044 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI); 1045 else 1046 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI); 1047 1048 for (ifma = ifp->if_multiaddrs.lh_first; ifma != NULL; 1049 ifma = ifma->ifma_link.le_next) { 1050 if (ifma->ifma_addr->sa_family != AF_LINK) 1051 continue; 1052 h = dc_crc_le(sc, 1053 LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 1054 sp[h >> 4] |= 1 << (h & 0xF); 1055 } 1056 1057 if (ifp->if_flags & IFF_BROADCAST) { 1058 h = dc_crc_le(sc, (caddr_t)ðerbroadcastaddr); 1059 sp[h >> 4] |= 1 << (h & 0xF); 1060 } 1061 1062 /* Set our MAC address */ 1063 sp[39] = ((u_int16_t *)sc->arpcom.ac_enaddr)[0]; 1064 sp[40] = ((u_int16_t *)sc->arpcom.ac_enaddr)[1]; 1065 sp[41] = ((u_int16_t *)sc->arpcom.ac_enaddr)[2]; 1066 1067 sframe->dc_status = DC_TXSTAT_OWN; 1068 CSR_WRITE_4(sc, DC_TXSTART, 0xFFFFFFFF); 1069 1070 /* 1071 * The PNIC takes an exceedingly long time to process its 1072 * setup frame; wait 10ms after posting the setup frame 1073 * before proceeding, just so it has time to swallow its 1074 * medicine. 1075 */ 1076 DELAY(10000); 1077 1078 ifp->if_timer = 5; 1079 1080 return; 1081 } 1082 1083 void dc_setfilt_admtek(sc) 1084 struct dc_softc *sc; 1085 { 1086 struct ifnet *ifp; 1087 int h = 0; 1088 u_int32_t hashes[2] = { 0, 0 }; 1089 struct ifmultiaddr *ifma; 1090 1091 ifp = &sc->arpcom.ac_if; 1092 1093 /* Init our MAC address */ 1094 CSR_WRITE_4(sc, DC_AL_PAR0, *(u_int32_t *)(&sc->arpcom.ac_enaddr[0])); 1095 CSR_WRITE_4(sc, DC_AL_PAR1, *(u_int32_t *)(&sc->arpcom.ac_enaddr[4])); 1096 1097 /* If we want promiscuous mode, set the allframes bit. */ 1098 if (ifp->if_flags & IFF_PROMISC) 1099 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC); 1100 else 1101 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC); 1102 1103 if (ifp->if_flags & IFF_ALLMULTI) 1104 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI); 1105 else 1106 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI); 1107 1108 /* first, zot all the existing hash bits */ 1109 CSR_WRITE_4(sc, DC_AL_MAR0, 0); 1110 CSR_WRITE_4(sc, DC_AL_MAR1, 0); 1111 1112 /* 1113 * If we're already in promisc or allmulti mode, we 1114 * don't have to bother programming the multicast filter. 1115 */ 1116 if (ifp->if_flags & (IFF_PROMISC|IFF_ALLMULTI)) 1117 return; 1118 1119 /* now program new ones */ 1120 for (ifma = ifp->if_multiaddrs.lh_first; ifma != NULL; 1121 ifma = ifma->ifma_link.le_next) { 1122 if (ifma->ifma_addr->sa_family != AF_LINK) 1123 continue; 1124 h = dc_crc_be(LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 1125 if (h < 32) 1126 hashes[0] |= (1 << h); 1127 else 1128 hashes[1] |= (1 << (h - 32)); 1129 } 1130 1131 CSR_WRITE_4(sc, DC_AL_MAR0, hashes[0]); 1132 CSR_WRITE_4(sc, DC_AL_MAR1, hashes[1]); 1133 1134 return; 1135 } 1136 1137 void dc_setfilt_asix(sc) 1138 struct dc_softc *sc; 1139 { 1140 struct ifnet *ifp; 1141 int h = 0; 1142 u_int32_t hashes[2] = { 0, 0 }; 1143 struct ifmultiaddr *ifma; 1144 1145 ifp = &sc->arpcom.ac_if; 1146 1147 /* Init our MAC address */ 1148 CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_PAR0); 1149 CSR_WRITE_4(sc, DC_AX_FILTDATA, 1150 *(u_int32_t *)(&sc->arpcom.ac_enaddr[0])); 1151 CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_PAR1); 1152 CSR_WRITE_4(sc, DC_AX_FILTDATA, 1153 *(u_int32_t *)(&sc->arpcom.ac_enaddr[4])); 1154 1155 /* If we want promiscuous mode, set the allframes bit. */ 1156 if (ifp->if_flags & IFF_PROMISC) 1157 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC); 1158 else 1159 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC); 1160 1161 if (ifp->if_flags & IFF_ALLMULTI) 1162 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI); 1163 else 1164 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI); 1165 1166 /* 1167 * The ASIX chip has a special bit to enable reception 1168 * of broadcast frames. 1169 */ 1170 if (ifp->if_flags & IFF_BROADCAST) 1171 DC_SETBIT(sc, DC_NETCFG, DC_AX_NETCFG_RX_BROAD); 1172 else 1173 DC_CLRBIT(sc, DC_NETCFG, DC_AX_NETCFG_RX_BROAD); 1174 1175 /* first, zot all the existing hash bits */ 1176 CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_MAR0); 1177 CSR_WRITE_4(sc, DC_AX_FILTDATA, 0); 1178 CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_MAR1); 1179 CSR_WRITE_4(sc, DC_AX_FILTDATA, 0); 1180 1181 /* 1182 * If we're already in promisc or allmulti mode, we 1183 * don't have to bother programming the multicast filter. 1184 */ 1185 if (ifp->if_flags & (IFF_PROMISC|IFF_ALLMULTI)) 1186 return; 1187 1188 /* now program new ones */ 1189 for (ifma = ifp->if_multiaddrs.lh_first; ifma != NULL; 1190 ifma = ifma->ifma_link.le_next) { 1191 if (ifma->ifma_addr->sa_family != AF_LINK) 1192 continue; 1193 h = dc_crc_be(LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 1194 if (h < 32) 1195 hashes[0] |= (1 << h); 1196 else 1197 hashes[1] |= (1 << (h - 32)); 1198 } 1199 1200 CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_MAR0); 1201 CSR_WRITE_4(sc, DC_AX_FILTDATA, hashes[0]); 1202 CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_MAR1); 1203 CSR_WRITE_4(sc, DC_AX_FILTDATA, hashes[1]); 1204 1205 return; 1206 } 1207 1208 void dc_setfilt_xircom(sc) 1209 struct dc_softc *sc; 1210 { 1211 struct dc_desc *sframe; 1212 u_int32_t h, *sp; 1213 struct ifmultiaddr *ifma; 1214 struct ifnet *ifp; 1215 int i; 1216 1217 ifp = &sc->arpcom.ac_if; 1218 DC_CLRBIT(sc, DC_NETCFG, (DC_NETCFG_TX_ON|DC_NETCFG_RX_ON)); 1219 1220 i = sc->dc_cdata.dc_tx_prod; 1221 DC_INC(sc->dc_cdata.dc_tx_prod, DC_TX_LIST_CNT); 1222 sc->dc_cdata.dc_tx_cnt++; 1223 sframe = &sc->dc_ldata->dc_tx_list[i]; 1224 sp = (u_int32_t *)&sc->dc_cdata.dc_sbuf; 1225 bzero((char *)sp, DC_SFRAME_LEN); 1226 1227 sframe->dc_data = vtophys(&sc->dc_cdata.dc_sbuf); 1228 sframe->dc_ctl = DC_SFRAME_LEN | DC_TXCTL_SETUP | DC_TXCTL_TLINK | 1229 DC_FILTER_HASHPERF | DC_TXCTL_FINT; 1230 1231 sc->dc_cdata.dc_tx_chain[i] = (struct mbuf *)&sc->dc_cdata.dc_sbuf; 1232 1233 /* If we want promiscuous mode, set the allframes bit. */ 1234 if (ifp->if_flags & IFF_PROMISC) 1235 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC); 1236 else 1237 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC); 1238 1239 if (ifp->if_flags & IFF_ALLMULTI) 1240 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI); 1241 else 1242 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI); 1243 1244 for (ifma = ifp->if_multiaddrs.lh_first; ifma != NULL; 1245 ifma = ifma->ifma_link.le_next) { 1246 if (ifma->ifma_addr->sa_family != AF_LINK) 1247 continue; 1248 h = dc_crc_le(sc, 1249 LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 1250 sp[h >> 4] |= 1 << (h & 0xF); 1251 } 1252 1253 if (ifp->if_flags & IFF_BROADCAST) { 1254 h = dc_crc_le(sc, (caddr_t)ðerbroadcastaddr); 1255 sp[h >> 4] |= 1 << (h & 0xF); 1256 } 1257 1258 /* Set our MAC address */ 1259 sp[0] = ((u_int16_t *)sc->arpcom.ac_enaddr)[0]; 1260 sp[1] = ((u_int16_t *)sc->arpcom.ac_enaddr)[1]; 1261 sp[2] = ((u_int16_t *)sc->arpcom.ac_enaddr)[2]; 1262 1263 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_TX_ON); 1264 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_ON); 1265 ifp->if_flags |= IFF_RUNNING; 1266 sframe->dc_status = DC_TXSTAT_OWN; 1267 CSR_WRITE_4(sc, DC_TXSTART, 0xFFFFFFFF); 1268 1269 /* 1270 * wait some time... 1271 */ 1272 DELAY(1000); 1273 1274 ifp->if_timer = 5; 1275 1276 return; 1277 } 1278 1279 static void dc_setfilt(sc) 1280 struct dc_softc *sc; 1281 { 1282 if (DC_IS_INTEL(sc) || DC_IS_MACRONIX(sc) || DC_IS_PNIC(sc) || 1283 DC_IS_PNICII(sc) || DC_IS_DAVICOM(sc)) 1284 dc_setfilt_21143(sc); 1285 1286 if (DC_IS_ASIX(sc)) 1287 dc_setfilt_asix(sc); 1288 1289 if (DC_IS_ADMTEK(sc)) 1290 dc_setfilt_admtek(sc); 1291 1292 if (DC_IS_XIRCOM(sc)) 1293 dc_setfilt_xircom(sc); 1294 1295 return; 1296 } 1297 1298 /* 1299 * In order to fiddle with the 1300 * 'full-duplex' and '100Mbps' bits in the netconfig register, we 1301 * first have to put the transmit and/or receive logic in the idle state. 1302 */ 1303 static void dc_setcfg(sc, media) 1304 struct dc_softc *sc; 1305 int media; 1306 { 1307 int i, restart = 0; 1308 u_int32_t isr; 1309 1310 if (IFM_SUBTYPE(media) == IFM_NONE) 1311 return; 1312 1313 if (CSR_READ_4(sc, DC_NETCFG) & (DC_NETCFG_TX_ON|DC_NETCFG_RX_ON)) { 1314 restart = 1; 1315 DC_CLRBIT(sc, DC_NETCFG, (DC_NETCFG_TX_ON|DC_NETCFG_RX_ON)); 1316 1317 for (i = 0; i < DC_TIMEOUT; i++) { 1318 DELAY(10); 1319 isr = CSR_READ_4(sc, DC_ISR); 1320 if (isr & DC_ISR_TX_IDLE || 1321 (isr & DC_ISR_RX_STATE) == DC_RXSTATE_STOPPED) 1322 break; 1323 } 1324 1325 if (i == DC_TIMEOUT) 1326 printf("dc%d: failed to force tx and " 1327 "rx to idle state\n", sc->dc_unit); 1328 1329 } 1330 1331 if (IFM_SUBTYPE(media) == IFM_100_TX) { 1332 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_SPEEDSEL); 1333 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_HEARTBEAT); 1334 if (sc->dc_pmode == DC_PMODE_MII) { 1335 int watchdogreg; 1336 1337 if (DC_IS_INTEL(sc)) { 1338 /* there's a write enable bit here that reads as 1 */ 1339 watchdogreg = CSR_READ_4(sc, DC_WATCHDOG); 1340 watchdogreg &= ~DC_WDOG_CTLWREN; 1341 watchdogreg |= DC_WDOG_JABBERDIS; 1342 CSR_WRITE_4(sc, DC_WATCHDOG, watchdogreg); 1343 } else { 1344 DC_SETBIT(sc, DC_WATCHDOG, DC_WDOG_JABBERDIS); 1345 } 1346 DC_CLRBIT(sc, DC_NETCFG, (DC_NETCFG_PCS| 1347 DC_NETCFG_PORTSEL|DC_NETCFG_SCRAMBLER)); 1348 if (sc->dc_type == DC_TYPE_98713) 1349 DC_SETBIT(sc, DC_NETCFG, (DC_NETCFG_PCS| 1350 DC_NETCFG_SCRAMBLER)); 1351 if (!DC_IS_DAVICOM(sc)) 1352 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL); 1353 DC_CLRBIT(sc, DC_10BTCTRL, 0xFFFF); 1354 if (DC_IS_INTEL(sc)) 1355 dc_apply_fixup(sc, IFM_AUTO); 1356 } else { 1357 if (DC_IS_PNIC(sc)) { 1358 DC_PN_GPIO_SETBIT(sc, DC_PN_GPIO_SPEEDSEL); 1359 DC_PN_GPIO_SETBIT(sc, DC_PN_GPIO_100TX_LOOP); 1360 DC_SETBIT(sc, DC_PN_NWAY, DC_PN_NWAY_SPEEDSEL); 1361 } 1362 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL); 1363 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PCS); 1364 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_SCRAMBLER); 1365 if (DC_IS_INTEL(sc)) 1366 dc_apply_fixup(sc, 1367 (media & IFM_GMASK) == IFM_FDX ? 1368 IFM_100_TX|IFM_FDX : IFM_100_TX); 1369 } 1370 } 1371 1372 if (IFM_SUBTYPE(media) == IFM_10_T) { 1373 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_SPEEDSEL); 1374 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_HEARTBEAT); 1375 if (sc->dc_pmode == DC_PMODE_MII) { 1376 int watchdogreg; 1377 1378 /* there's a write enable bit here that reads as 1 */ 1379 if (DC_IS_INTEL(sc)) { 1380 watchdogreg = CSR_READ_4(sc, DC_WATCHDOG); 1381 watchdogreg &= ~DC_WDOG_CTLWREN; 1382 watchdogreg |= DC_WDOG_JABBERDIS; 1383 CSR_WRITE_4(sc, DC_WATCHDOG, watchdogreg); 1384 } else { 1385 DC_SETBIT(sc, DC_WATCHDOG, DC_WDOG_JABBERDIS); 1386 } 1387 DC_CLRBIT(sc, DC_NETCFG, (DC_NETCFG_PCS| 1388 DC_NETCFG_PORTSEL|DC_NETCFG_SCRAMBLER)); 1389 if (sc->dc_type == DC_TYPE_98713) 1390 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PCS); 1391 if (!DC_IS_DAVICOM(sc)) 1392 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL); 1393 DC_CLRBIT(sc, DC_10BTCTRL, 0xFFFF); 1394 if (DC_IS_INTEL(sc)) 1395 dc_apply_fixup(sc, IFM_AUTO); 1396 } else { 1397 if (DC_IS_PNIC(sc)) { 1398 DC_PN_GPIO_CLRBIT(sc, DC_PN_GPIO_SPEEDSEL); 1399 DC_PN_GPIO_SETBIT(sc, DC_PN_GPIO_100TX_LOOP); 1400 DC_CLRBIT(sc, DC_PN_NWAY, DC_PN_NWAY_SPEEDSEL); 1401 } 1402 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL); 1403 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_PCS); 1404 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_SCRAMBLER); 1405 if (DC_IS_INTEL(sc)) { 1406 DC_CLRBIT(sc, DC_SIARESET, DC_SIA_RESET); 1407 DC_CLRBIT(sc, DC_10BTCTRL, 0xFFFF); 1408 if ((media & IFM_GMASK) == IFM_FDX) 1409 DC_SETBIT(sc, DC_10BTCTRL, 0x7F3D); 1410 else 1411 DC_SETBIT(sc, DC_10BTCTRL, 0x7F3F); 1412 DC_SETBIT(sc, DC_SIARESET, DC_SIA_RESET); 1413 DC_CLRBIT(sc, DC_10BTCTRL, 1414 DC_TCTL_AUTONEGENBL); 1415 dc_apply_fixup(sc, 1416 (media & IFM_GMASK) == IFM_FDX ? 1417 IFM_10_T|IFM_FDX : IFM_10_T); 1418 DELAY(20000); 1419 } 1420 } 1421 } 1422 1423 /* 1424 * If this is a Davicom DM9102A card with a DM9801 HomePNA 1425 * PHY and we want HomePNA mode, set the portsel bit to turn 1426 * on the external MII port. 1427 */ 1428 if (DC_IS_DAVICOM(sc)) { 1429 if (IFM_SUBTYPE(media) == IFM_homePNA) { 1430 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL); 1431 sc->dc_link = 1; 1432 } else { 1433 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL); 1434 } 1435 } 1436 1437 if ((media & IFM_GMASK) == IFM_FDX) { 1438 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_FULLDUPLEX); 1439 if (sc->dc_pmode == DC_PMODE_SYM && DC_IS_PNIC(sc)) 1440 DC_SETBIT(sc, DC_PN_NWAY, DC_PN_NWAY_DUPLEX); 1441 } else { 1442 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_FULLDUPLEX); 1443 if (sc->dc_pmode == DC_PMODE_SYM && DC_IS_PNIC(sc)) 1444 DC_CLRBIT(sc, DC_PN_NWAY, DC_PN_NWAY_DUPLEX); 1445 } 1446 1447 if (restart) 1448 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_TX_ON|DC_NETCFG_RX_ON); 1449 1450 return; 1451 } 1452 1453 static void dc_reset(sc) 1454 struct dc_softc *sc; 1455 { 1456 register int i; 1457 1458 DC_SETBIT(sc, DC_BUSCTL, DC_BUSCTL_RESET); 1459 1460 for (i = 0; i < DC_TIMEOUT; i++) { 1461 DELAY(10); 1462 if (!(CSR_READ_4(sc, DC_BUSCTL) & DC_BUSCTL_RESET)) 1463 break; 1464 } 1465 1466 if (DC_IS_ASIX(sc) || DC_IS_ADMTEK(sc) || 1467 DC_IS_XIRCOM(sc) || DC_IS_INTEL(sc)) { 1468 DELAY(10000); 1469 DC_CLRBIT(sc, DC_BUSCTL, DC_BUSCTL_RESET); 1470 i = 0; 1471 } 1472 1473 if (i == DC_TIMEOUT) 1474 printf("dc%d: reset never completed!\n", sc->dc_unit); 1475 1476 /* Wait a little while for the chip to get its brains in order. */ 1477 DELAY(1000); 1478 1479 CSR_WRITE_4(sc, DC_IMR, 0x00000000); 1480 CSR_WRITE_4(sc, DC_BUSCTL, 0x00000000); 1481 CSR_WRITE_4(sc, DC_NETCFG, 0x00000000); 1482 1483 /* 1484 * Bring the SIA out of reset. In some cases, it looks 1485 * like failing to unreset the SIA soon enough gets it 1486 * into a state where it will never come out of reset 1487 * until we reset the whole chip again. 1488 */ 1489 if (DC_IS_INTEL(sc)) { 1490 DC_SETBIT(sc, DC_SIARESET, DC_SIA_RESET); 1491 CSR_WRITE_4(sc, DC_10BTCTRL, 0); 1492 CSR_WRITE_4(sc, DC_WATCHDOG, 0); 1493 } 1494 1495 return; 1496 } 1497 1498 static struct dc_type *dc_devtype(dev) 1499 device_t dev; 1500 { 1501 struct dc_type *t; 1502 u_int32_t rev; 1503 1504 t = dc_devs; 1505 1506 while(t->dc_name != NULL) { 1507 if ((pci_get_vendor(dev) == t->dc_vid) && 1508 (pci_get_device(dev) == t->dc_did)) { 1509 /* Check the PCI revision */ 1510 rev = pci_read_config(dev, DC_PCI_CFRV, 4) & 0xFF; 1511 if (t->dc_did == DC_DEVICEID_98713 && 1512 rev >= DC_REVISION_98713A) 1513 t++; 1514 if (t->dc_did == DC_DEVICEID_98713_CP && 1515 rev >= DC_REVISION_98713A) 1516 t++; 1517 if (t->dc_did == DC_DEVICEID_987x5 && 1518 rev >= DC_REVISION_98715AEC_C) 1519 t++; 1520 if (t->dc_did == DC_DEVICEID_987x5 && 1521 rev >= DC_REVISION_98725) 1522 t++; 1523 if (t->dc_did == DC_DEVICEID_AX88140A && 1524 rev >= DC_REVISION_88141) 1525 t++; 1526 if (t->dc_did == DC_DEVICEID_82C168 && 1527 rev >= DC_REVISION_82C169) 1528 t++; 1529 if (t->dc_did == DC_DEVICEID_DM9102 && 1530 rev >= DC_REVISION_DM9102A) 1531 t++; 1532 return(t); 1533 } 1534 t++; 1535 } 1536 1537 return(NULL); 1538 } 1539 1540 /* 1541 * Probe for a 21143 or clone chip. Check the PCI vendor and device 1542 * IDs against our list and return a device name if we find a match. 1543 * We do a little bit of extra work to identify the exact type of 1544 * chip. The MX98713 and MX98713A have the same PCI vendor/device ID, 1545 * but different revision IDs. The same is true for 98715/98715A 1546 * chips and the 98725, as well as the ASIX and ADMtek chips. In some 1547 * cases, the exact chip revision affects driver behavior. 1548 */ 1549 static int dc_probe(dev) 1550 device_t dev; 1551 { 1552 struct dc_type *t; 1553 1554 t = dc_devtype(dev); 1555 1556 if (t != NULL) { 1557 device_set_desc(dev, t->dc_name); 1558 return(0); 1559 } 1560 1561 return(ENXIO); 1562 } 1563 1564 static void dc_acpi(dev) 1565 device_t dev; 1566 { 1567 int unit; 1568 1569 unit = device_get_unit(dev); 1570 1571 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) { 1572 u_int32_t iobase, membase, irq; 1573 1574 /* Save important PCI config data. */ 1575 iobase = pci_read_config(dev, DC_PCI_CFBIO, 4); 1576 membase = pci_read_config(dev, DC_PCI_CFBMA, 4); 1577 irq = pci_read_config(dev, DC_PCI_CFIT, 4); 1578 1579 /* Reset the power state. */ 1580 printf("dc%d: chip is in D%d power mode " 1581 "-- setting to D0\n", unit, 1582 pci_get_powerstate(dev)); 1583 pci_set_powerstate(dev, PCI_POWERSTATE_D0); 1584 1585 /* Restore PCI config data. */ 1586 pci_write_config(dev, DC_PCI_CFBIO, iobase, 4); 1587 pci_write_config(dev, DC_PCI_CFBMA, membase, 4); 1588 pci_write_config(dev, DC_PCI_CFIT, irq, 4); 1589 } 1590 1591 return; 1592 } 1593 1594 static void dc_apply_fixup(sc, media) 1595 struct dc_softc *sc; 1596 int media; 1597 { 1598 struct dc_mediainfo *m; 1599 u_int8_t *p; 1600 int i; 1601 u_int32_t reg; 1602 1603 m = sc->dc_mi; 1604 1605 while (m != NULL) { 1606 if (m->dc_media == media) 1607 break; 1608 m = m->dc_next; 1609 } 1610 1611 if (m == NULL) 1612 return; 1613 1614 for (i = 0, p = m->dc_reset_ptr; i < m->dc_reset_len; i++, p += 2) { 1615 reg = (p[0] | (p[1] << 8)) << 16; 1616 CSR_WRITE_4(sc, DC_WATCHDOG, reg); 1617 } 1618 1619 for (i = 0, p = m->dc_gp_ptr; i < m->dc_gp_len; i++, p += 2) { 1620 reg = (p[0] | (p[1] << 8)) << 16; 1621 CSR_WRITE_4(sc, DC_WATCHDOG, reg); 1622 } 1623 1624 return; 1625 } 1626 1627 static void dc_decode_leaf_sia(sc, l) 1628 struct dc_softc *sc; 1629 struct dc_eblock_sia *l; 1630 { 1631 struct dc_mediainfo *m; 1632 1633 m = malloc(sizeof(struct dc_mediainfo), M_DEVBUF, M_NOWAIT); 1634 bzero(m, sizeof(struct dc_mediainfo)); 1635 if (l->dc_sia_code == DC_SIA_CODE_10BT) 1636 m->dc_media = IFM_10_T; 1637 1638 if (l->dc_sia_code == DC_SIA_CODE_10BT_FDX) 1639 m->dc_media = IFM_10_T|IFM_FDX; 1640 1641 if (l->dc_sia_code == DC_SIA_CODE_10B2) 1642 m->dc_media = IFM_10_2; 1643 1644 if (l->dc_sia_code == DC_SIA_CODE_10B5) 1645 m->dc_media = IFM_10_5; 1646 1647 m->dc_gp_len = 2; 1648 m->dc_gp_ptr = (u_int8_t *)&l->dc_sia_gpio_ctl; 1649 1650 m->dc_next = sc->dc_mi; 1651 sc->dc_mi = m; 1652 1653 sc->dc_pmode = DC_PMODE_SIA; 1654 1655 return; 1656 } 1657 1658 static void dc_decode_leaf_sym(sc, l) 1659 struct dc_softc *sc; 1660 struct dc_eblock_sym *l; 1661 { 1662 struct dc_mediainfo *m; 1663 1664 m = malloc(sizeof(struct dc_mediainfo), M_DEVBUF, M_NOWAIT); 1665 bzero(m, sizeof(struct dc_mediainfo)); 1666 if (l->dc_sym_code == DC_SYM_CODE_100BT) 1667 m->dc_media = IFM_100_TX; 1668 1669 if (l->dc_sym_code == DC_SYM_CODE_100BT_FDX) 1670 m->dc_media = IFM_100_TX|IFM_FDX; 1671 1672 m->dc_gp_len = 2; 1673 m->dc_gp_ptr = (u_int8_t *)&l->dc_sym_gpio_ctl; 1674 1675 m->dc_next = sc->dc_mi; 1676 sc->dc_mi = m; 1677 1678 sc->dc_pmode = DC_PMODE_SYM; 1679 1680 return; 1681 } 1682 1683 static void dc_decode_leaf_mii(sc, l) 1684 struct dc_softc *sc; 1685 struct dc_eblock_mii *l; 1686 { 1687 u_int8_t *p; 1688 struct dc_mediainfo *m; 1689 1690 m = malloc(sizeof(struct dc_mediainfo), M_DEVBUF, M_NOWAIT); 1691 bzero(m, sizeof(struct dc_mediainfo)); 1692 /* We abuse IFM_AUTO to represent MII. */ 1693 m->dc_media = IFM_AUTO; 1694 m->dc_gp_len = l->dc_gpr_len; 1695 1696 p = (u_int8_t *)l; 1697 p += sizeof(struct dc_eblock_mii); 1698 m->dc_gp_ptr = p; 1699 p += 2 * l->dc_gpr_len; 1700 m->dc_reset_len = *p; 1701 p++; 1702 m->dc_reset_ptr = p; 1703 1704 m->dc_next = sc->dc_mi; 1705 sc->dc_mi = m; 1706 1707 return; 1708 } 1709 1710 static void dc_parse_21143_srom(sc) 1711 struct dc_softc *sc; 1712 { 1713 struct dc_leaf_hdr *lhdr; 1714 struct dc_eblock_hdr *hdr; 1715 int i, loff; 1716 char *ptr; 1717 1718 loff = sc->dc_srom[27]; 1719 lhdr = (struct dc_leaf_hdr *)&(sc->dc_srom[loff]); 1720 1721 ptr = (char *)lhdr; 1722 ptr += sizeof(struct dc_leaf_hdr) - 1; 1723 for (i = 0; i < lhdr->dc_mcnt; i++) { 1724 hdr = (struct dc_eblock_hdr *)ptr; 1725 switch(hdr->dc_type) { 1726 case DC_EBLOCK_MII: 1727 dc_decode_leaf_mii(sc, (struct dc_eblock_mii *)hdr); 1728 break; 1729 case DC_EBLOCK_SIA: 1730 dc_decode_leaf_sia(sc, (struct dc_eblock_sia *)hdr); 1731 break; 1732 case DC_EBLOCK_SYM: 1733 dc_decode_leaf_sym(sc, (struct dc_eblock_sym *)hdr); 1734 break; 1735 default: 1736 /* Don't care. Yet. */ 1737 break; 1738 } 1739 ptr += (hdr->dc_len & 0x7F); 1740 ptr++; 1741 } 1742 1743 return; 1744 } 1745 1746 /* 1747 * Attach the interface. Allocate softc structures, do ifmedia 1748 * setup and ethernet/BPF attach. 1749 */ 1750 static int dc_attach(dev) 1751 device_t dev; 1752 { 1753 int tmp = 0; 1754 u_char eaddr[ETHER_ADDR_LEN]; 1755 u_int32_t command; 1756 struct dc_softc *sc; 1757 struct ifnet *ifp; 1758 u_int32_t revision; 1759 int unit, error = 0, rid, mac_offset; 1760 1761 sc = device_get_softc(dev); 1762 unit = device_get_unit(dev); 1763 bzero(sc, sizeof(struct dc_softc)); 1764 1765 mtx_init(&sc->dc_mtx, device_get_nameunit(dev), MTX_DEF); 1766 DC_LOCK(sc); 1767 1768 /* 1769 * Handle power management nonsense. 1770 */ 1771 dc_acpi(dev); 1772 1773 /* 1774 * Map control/status registers. 1775 */ 1776 command = pci_read_config(dev, PCIR_COMMAND, 4); 1777 command |= (PCIM_CMD_PORTEN|PCIM_CMD_MEMEN|PCIM_CMD_BUSMASTEREN); 1778 pci_write_config(dev, PCIR_COMMAND, command, 4); 1779 command = pci_read_config(dev, PCIR_COMMAND, 4); 1780 1781 #ifdef DC_USEIOSPACE 1782 if (!(command & PCIM_CMD_PORTEN)) { 1783 printf("dc%d: failed to enable I/O ports!\n", unit); 1784 error = ENXIO; 1785 goto fail; 1786 } 1787 #else 1788 if (!(command & PCIM_CMD_MEMEN)) { 1789 printf("dc%d: failed to enable memory mapping!\n", unit); 1790 error = ENXIO; 1791 goto fail; 1792 } 1793 #endif 1794 1795 rid = DC_RID; 1796 sc->dc_res = bus_alloc_resource(dev, DC_RES, &rid, 1797 0, ~0, 1, RF_ACTIVE); 1798 1799 if (sc->dc_res == NULL) { 1800 printf("dc%d: couldn't map ports/memory\n", unit); 1801 error = ENXIO; 1802 goto fail; 1803 } 1804 1805 sc->dc_btag = rman_get_bustag(sc->dc_res); 1806 sc->dc_bhandle = rman_get_bushandle(sc->dc_res); 1807 1808 /* Allocate interrupt */ 1809 rid = 0; 1810 sc->dc_irq = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, 0, ~0, 1, 1811 RF_SHAREABLE | RF_ACTIVE); 1812 1813 if (sc->dc_irq == NULL) { 1814 printf("dc%d: couldn't map interrupt\n", unit); 1815 bus_release_resource(dev, DC_RES, DC_RID, sc->dc_res); 1816 error = ENXIO; 1817 goto fail; 1818 } 1819 1820 error = bus_setup_intr(dev, sc->dc_irq, INTR_TYPE_NET | 1821 (IS_MPSAFE ? INTR_MPSAFE : 0), 1822 dc_intr, sc, &sc->dc_intrhand); 1823 1824 if (error) { 1825 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->dc_irq); 1826 bus_release_resource(dev, DC_RES, DC_RID, sc->dc_res); 1827 printf("dc%d: couldn't set up irq\n", unit); 1828 goto fail; 1829 } 1830 1831 /* Need this info to decide on a chip type. */ 1832 sc->dc_info = dc_devtype(dev); 1833 revision = pci_read_config(dev, DC_PCI_CFRV, 4) & 0x000000FF; 1834 1835 switch(sc->dc_info->dc_did) { 1836 case DC_DEVICEID_21143: 1837 sc->dc_type = DC_TYPE_21143; 1838 sc->dc_flags |= DC_TX_POLL|DC_TX_USE_TX_INTR; 1839 sc->dc_flags |= DC_REDUCED_MII_POLL; 1840 /* Save EEPROM contents so we can parse them later. */ 1841 dc_read_eeprom(sc, (caddr_t)&sc->dc_srom, 0, 512, 0); 1842 break; 1843 case DC_DEVICEID_DM9100: 1844 case DC_DEVICEID_DM9102: 1845 sc->dc_type = DC_TYPE_DM9102; 1846 sc->dc_flags |= DC_TX_COALESCE|DC_TX_INTR_ALWAYS; 1847 sc->dc_flags |= DC_REDUCED_MII_POLL|DC_TX_STORENFWD; 1848 sc->dc_pmode = DC_PMODE_MII; 1849 /* Increase the latency timer value. */ 1850 command = pci_read_config(dev, DC_PCI_CFLT, 4); 1851 command &= 0xFFFF00FF; 1852 command |= 0x00008000; 1853 pci_write_config(dev, DC_PCI_CFLT, command, 4); 1854 break; 1855 case DC_DEVICEID_AL981: 1856 sc->dc_type = DC_TYPE_AL981; 1857 sc->dc_flags |= DC_TX_USE_TX_INTR; 1858 sc->dc_flags |= DC_TX_ADMTEK_WAR; 1859 sc->dc_pmode = DC_PMODE_MII; 1860 break; 1861 case DC_DEVICEID_AN985: 1862 case DC_DEVICEID_FE2500: 1863 case DC_DEVICEID_EN2242: 1864 sc->dc_type = DC_TYPE_AN985; 1865 sc->dc_flags |= DC_TX_USE_TX_INTR; 1866 sc->dc_flags |= DC_TX_ADMTEK_WAR; 1867 sc->dc_pmode = DC_PMODE_MII; 1868 break; 1869 case DC_DEVICEID_98713: 1870 case DC_DEVICEID_98713_CP: 1871 if (revision < DC_REVISION_98713A) { 1872 sc->dc_type = DC_TYPE_98713; 1873 } 1874 if (revision >= DC_REVISION_98713A) { 1875 sc->dc_type = DC_TYPE_98713A; 1876 sc->dc_flags |= DC_21143_NWAY; 1877 } 1878 sc->dc_flags |= DC_REDUCED_MII_POLL; 1879 sc->dc_flags |= DC_TX_POLL|DC_TX_USE_TX_INTR; 1880 break; 1881 case DC_DEVICEID_987x5: 1882 case DC_DEVICEID_EN1217: 1883 /* 1884 * Macronix MX98715AEC-C/D/E parts have only a 1885 * 128-bit hash table. We need to deal with these 1886 * in the same manner as the PNIC II so that we 1887 * get the right number of bits out of the 1888 * CRC routine. 1889 */ 1890 if (revision >= DC_REVISION_98715AEC_C && 1891 revision < DC_REVISION_98725) 1892 sc->dc_flags |= DC_128BIT_HASH; 1893 sc->dc_type = DC_TYPE_987x5; 1894 sc->dc_flags |= DC_TX_POLL|DC_TX_USE_TX_INTR; 1895 sc->dc_flags |= DC_REDUCED_MII_POLL|DC_21143_NWAY; 1896 break; 1897 case DC_DEVICEID_98727: 1898 sc->dc_type = DC_TYPE_987x5; 1899 sc->dc_flags |= DC_TX_POLL|DC_TX_USE_TX_INTR; 1900 sc->dc_flags |= DC_REDUCED_MII_POLL|DC_21143_NWAY; 1901 break; 1902 case DC_DEVICEID_82C115: 1903 sc->dc_type = DC_TYPE_PNICII; 1904 sc->dc_flags |= DC_TX_POLL|DC_TX_USE_TX_INTR|DC_128BIT_HASH; 1905 sc->dc_flags |= DC_REDUCED_MII_POLL|DC_21143_NWAY; 1906 break; 1907 case DC_DEVICEID_82C168: 1908 sc->dc_type = DC_TYPE_PNIC; 1909 sc->dc_flags |= DC_TX_STORENFWD|DC_TX_INTR_ALWAYS; 1910 sc->dc_flags |= DC_PNIC_RX_BUG_WAR; 1911 sc->dc_pnic_rx_buf = malloc(DC_RXLEN * 5, M_DEVBUF, M_NOWAIT); 1912 if (revision < DC_REVISION_82C169) 1913 sc->dc_pmode = DC_PMODE_SYM; 1914 break; 1915 case DC_DEVICEID_AX88140A: 1916 sc->dc_type = DC_TYPE_ASIX; 1917 sc->dc_flags |= DC_TX_USE_TX_INTR|DC_TX_INTR_FIRSTFRAG; 1918 sc->dc_flags |= DC_REDUCED_MII_POLL; 1919 sc->dc_pmode = DC_PMODE_MII; 1920 break; 1921 case DC_DEVICEID_X3201: 1922 sc->dc_type = DC_TYPE_XIRCOM; 1923 sc->dc_flags |= DC_TX_INTR_ALWAYS | DC_TX_COALESCE; 1924 /* 1925 * We don't actually need to coalesce, but we're doing 1926 * it to obtain a double word aligned buffer. 1927 */ 1928 break; 1929 default: 1930 printf("dc%d: unknown device: %x\n", sc->dc_unit, 1931 sc->dc_info->dc_did); 1932 break; 1933 } 1934 1935 /* Save the cache line size. */ 1936 if (DC_IS_DAVICOM(sc)) 1937 sc->dc_cachesize = 0; 1938 else 1939 sc->dc_cachesize = pci_read_config(dev, 1940 DC_PCI_CFLT, 4) & 0xFF; 1941 1942 /* Reset the adapter. */ 1943 dc_reset(sc); 1944 1945 /* Take 21143 out of snooze mode */ 1946 if (DC_IS_INTEL(sc) || DC_IS_XIRCOM(sc)) { 1947 command = pci_read_config(dev, DC_PCI_CFDD, 4); 1948 command &= ~(DC_CFDD_SNOOZE_MODE|DC_CFDD_SLEEP_MODE); 1949 pci_write_config(dev, DC_PCI_CFDD, command, 4); 1950 } 1951 1952 /* 1953 * Try to learn something about the supported media. 1954 * We know that ASIX and ADMtek and Davicom devices 1955 * will *always* be using MII media, so that's a no-brainer. 1956 * The tricky ones are the Macronix/PNIC II and the 1957 * Intel 21143. 1958 */ 1959 if (DC_IS_INTEL(sc)) 1960 dc_parse_21143_srom(sc); 1961 else if (DC_IS_MACRONIX(sc) || DC_IS_PNICII(sc)) { 1962 if (sc->dc_type == DC_TYPE_98713) 1963 sc->dc_pmode = DC_PMODE_MII; 1964 else 1965 sc->dc_pmode = DC_PMODE_SYM; 1966 } else if (!sc->dc_pmode) 1967 sc->dc_pmode = DC_PMODE_MII; 1968 1969 /* 1970 * Get station address from the EEPROM. 1971 */ 1972 switch(sc->dc_type) { 1973 case DC_TYPE_98713: 1974 case DC_TYPE_98713A: 1975 case DC_TYPE_987x5: 1976 case DC_TYPE_PNICII: 1977 dc_read_eeprom(sc, (caddr_t)&mac_offset, 1978 (DC_EE_NODEADDR_OFFSET / 2), 1, 0); 1979 dc_read_eeprom(sc, (caddr_t)&eaddr, (mac_offset / 2), 3, 0); 1980 break; 1981 case DC_TYPE_PNIC: 1982 dc_read_eeprom(sc, (caddr_t)&eaddr, 0, 3, 1); 1983 break; 1984 case DC_TYPE_DM9102: 1985 case DC_TYPE_21143: 1986 case DC_TYPE_ASIX: 1987 dc_read_eeprom(sc, (caddr_t)&eaddr, DC_EE_NODEADDR, 3, 0); 1988 break; 1989 case DC_TYPE_AL981: 1990 case DC_TYPE_AN985: 1991 dc_read_eeprom(sc, (caddr_t)&eaddr, DC_AL_EE_NODEADDR, 3, 0); 1992 break; 1993 case DC_TYPE_XIRCOM: 1994 dc_read_eeprom(sc, (caddr_t)&eaddr, 3, 3, 0); 1995 break; 1996 default: 1997 dc_read_eeprom(sc, (caddr_t)&eaddr, DC_EE_NODEADDR, 3, 0); 1998 break; 1999 } 2000 2001 /* 2002 * A 21143 or clone chip was detected. Inform the world. 2003 */ 2004 printf("dc%d: Ethernet address: %6D\n", unit, eaddr, ":"); 2005 2006 sc->dc_unit = unit; 2007 bcopy(eaddr, (char *)&sc->arpcom.ac_enaddr, ETHER_ADDR_LEN); 2008 2009 sc->dc_ldata = contigmalloc(sizeof(struct dc_list_data), M_DEVBUF, 2010 M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0); 2011 2012 if (sc->dc_ldata == NULL) { 2013 printf("dc%d: no memory for list buffers!\n", unit); 2014 bus_teardown_intr(dev, sc->dc_irq, sc->dc_intrhand); 2015 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->dc_irq); 2016 bus_release_resource(dev, DC_RES, DC_RID, sc->dc_res); 2017 error = ENXIO; 2018 goto fail; 2019 } 2020 2021 bzero(sc->dc_ldata, sizeof(struct dc_list_data)); 2022 2023 ifp = &sc->arpcom.ac_if; 2024 ifp->if_softc = sc; 2025 ifp->if_unit = unit; 2026 ifp->if_name = "dc"; 2027 /* XXX: bleah, MTU gets overwritten in ether_ifattach() */ 2028 ifp->if_mtu = ETHERMTU; 2029 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 2030 ifp->if_ioctl = dc_ioctl; 2031 ifp->if_output = ether_output; 2032 ifp->if_start = dc_start; 2033 ifp->if_watchdog = dc_watchdog; 2034 ifp->if_init = dc_init; 2035 ifp->if_baudrate = 10000000; 2036 ifp->if_snd.ifq_maxlen = DC_TX_LIST_CNT - 1; 2037 ifp->if_mpsafe = IS_MPSAFE; 2038 2039 /* 2040 * Do MII setup. If this is a 21143, check for a PHY on the 2041 * MII bus after applying any necessary fixups to twiddle the 2042 * GPIO bits. If we don't end up finding a PHY, restore the 2043 * old selection (SIA only or SIA/SYM) and attach the dcphy 2044 * driver instead. 2045 */ 2046 if (DC_IS_INTEL(sc)) { 2047 dc_apply_fixup(sc, IFM_AUTO); 2048 tmp = sc->dc_pmode; 2049 sc->dc_pmode = DC_PMODE_MII; 2050 } 2051 2052 error = mii_phy_probe(dev, &sc->dc_miibus, 2053 dc_ifmedia_upd, dc_ifmedia_sts); 2054 2055 if (error && DC_IS_INTEL(sc)) { 2056 sc->dc_pmode = tmp; 2057 if (sc->dc_pmode != DC_PMODE_SIA) 2058 sc->dc_pmode = DC_PMODE_SYM; 2059 sc->dc_flags |= DC_21143_NWAY; 2060 mii_phy_probe(dev, &sc->dc_miibus, 2061 dc_ifmedia_upd, dc_ifmedia_sts); 2062 /* 2063 * For non-MII cards, we need to have the 21143 2064 * drive the LEDs. Except there are some systems 2065 * like the NEC VersaPro NoteBook PC which have no 2066 * LEDs, and twiddling these bits has adverse effects 2067 * on them. (I.e. you suddenly can't get a link.) 2068 */ 2069 if (pci_read_config(dev, DC_PCI_CSID, 4) != 0x80281033) 2070 sc->dc_flags |= DC_TULIP_LEDS; 2071 error = 0; 2072 } 2073 2074 if (error) { 2075 printf("dc%d: MII without any PHY!\n", sc->dc_unit); 2076 bus_teardown_intr(dev, sc->dc_irq, sc->dc_intrhand); 2077 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->dc_irq); 2078 bus_release_resource(dev, DC_RES, DC_RID, sc->dc_res); 2079 error = ENXIO; 2080 goto fail; 2081 } 2082 2083 if (DC_IS_XIRCOM(sc)) { 2084 /* 2085 * setup General Purpose Port mode and data so the tulip 2086 * can talk to the MII. 2087 */ 2088 CSR_WRITE_4(sc, DC_SIAGP, DC_SIAGP_WRITE_EN | DC_SIAGP_INT1_EN | 2089 DC_SIAGP_MD_GP2_OUTPUT | DC_SIAGP_MD_GP0_OUTPUT); 2090 DELAY(10); 2091 CSR_WRITE_4(sc, DC_SIAGP, DC_SIAGP_INT1_EN | 2092 DC_SIAGP_MD_GP2_OUTPUT | DC_SIAGP_MD_GP0_OUTPUT); 2093 DELAY(10); 2094 } 2095 2096 /* 2097 * Call MI attach routine. 2098 */ 2099 ether_ifattach(ifp, ETHER_BPF_SUPPORTED); 2100 callout_init(&sc->dc_stat_ch, IS_MPSAFE); 2101 2102 #ifdef SRM_MEDIA 2103 sc->dc_srm_media = 0; 2104 2105 /* Remember the SRM console media setting */ 2106 if (DC_IS_INTEL(sc)) { 2107 command = pci_read_config(dev, DC_PCI_CFDD, 4); 2108 command &= ~(DC_CFDD_SNOOZE_MODE|DC_CFDD_SLEEP_MODE); 2109 switch ((command >> 8) & 0xff) { 2110 case 3: 2111 sc->dc_srm_media = IFM_10_T; 2112 break; 2113 case 4: 2114 sc->dc_srm_media = IFM_10_T | IFM_FDX; 2115 break; 2116 case 5: 2117 sc->dc_srm_media = IFM_100_TX; 2118 break; 2119 case 6: 2120 sc->dc_srm_media = IFM_100_TX | IFM_FDX; 2121 break; 2122 } 2123 if (sc->dc_srm_media) 2124 sc->dc_srm_media |= IFM_ACTIVE | IFM_ETHER; 2125 } 2126 #endif 2127 2128 DC_UNLOCK(sc); 2129 return(0); 2130 2131 fail: 2132 DC_UNLOCK(sc); 2133 mtx_destroy(&sc->dc_mtx); 2134 return(error); 2135 } 2136 2137 static int dc_detach(dev) 2138 device_t dev; 2139 { 2140 struct dc_softc *sc; 2141 struct ifnet *ifp; 2142 struct dc_mediainfo *m; 2143 2144 sc = device_get_softc(dev); 2145 2146 DC_LOCK(sc); 2147 2148 ifp = &sc->arpcom.ac_if; 2149 2150 dc_stop(sc); 2151 ether_ifdetach(ifp, ETHER_BPF_SUPPORTED); 2152 2153 bus_generic_detach(dev); 2154 device_delete_child(dev, sc->dc_miibus); 2155 2156 bus_teardown_intr(dev, sc->dc_irq, sc->dc_intrhand); 2157 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->dc_irq); 2158 bus_release_resource(dev, DC_RES, DC_RID, sc->dc_res); 2159 2160 contigfree(sc->dc_ldata, sizeof(struct dc_list_data), M_DEVBUF); 2161 if (sc->dc_pnic_rx_buf != NULL) 2162 free(sc->dc_pnic_rx_buf, M_DEVBUF); 2163 2164 while(sc->dc_mi != NULL) { 2165 m = sc->dc_mi->dc_next; 2166 free(sc->dc_mi, M_DEVBUF); 2167 sc->dc_mi = m; 2168 } 2169 2170 DC_UNLOCK(sc); 2171 mtx_destroy(&sc->dc_mtx); 2172 2173 return(0); 2174 } 2175 2176 /* 2177 * Initialize the transmit descriptors. 2178 */ 2179 static int dc_list_tx_init(sc) 2180 struct dc_softc *sc; 2181 { 2182 struct dc_chain_data *cd; 2183 struct dc_list_data *ld; 2184 int i; 2185 2186 cd = &sc->dc_cdata; 2187 ld = sc->dc_ldata; 2188 for (i = 0; i < DC_TX_LIST_CNT; i++) { 2189 if (i == (DC_TX_LIST_CNT - 1)) { 2190 ld->dc_tx_list[i].dc_next = 2191 vtophys(&ld->dc_tx_list[0]); 2192 } else { 2193 ld->dc_tx_list[i].dc_next = 2194 vtophys(&ld->dc_tx_list[i + 1]); 2195 } 2196 cd->dc_tx_chain[i] = NULL; 2197 ld->dc_tx_list[i].dc_data = 0; 2198 ld->dc_tx_list[i].dc_ctl = 0; 2199 } 2200 2201 cd->dc_tx_prod = cd->dc_tx_cons = cd->dc_tx_cnt = 0; 2202 2203 return(0); 2204 } 2205 2206 2207 /* 2208 * Initialize the RX descriptors and allocate mbufs for them. Note that 2209 * we arrange the descriptors in a closed ring, so that the last descriptor 2210 * points back to the first. 2211 */ 2212 static int dc_list_rx_init(sc) 2213 struct dc_softc *sc; 2214 { 2215 struct dc_chain_data *cd; 2216 struct dc_list_data *ld; 2217 int i; 2218 2219 cd = &sc->dc_cdata; 2220 ld = sc->dc_ldata; 2221 2222 for (i = 0; i < DC_RX_LIST_CNT; i++) { 2223 if (dc_newbuf(sc, i, NULL) == ENOBUFS) 2224 return(ENOBUFS); 2225 if (i == (DC_RX_LIST_CNT - 1)) { 2226 ld->dc_rx_list[i].dc_next = 2227 vtophys(&ld->dc_rx_list[0]); 2228 } else { 2229 ld->dc_rx_list[i].dc_next = 2230 vtophys(&ld->dc_rx_list[i + 1]); 2231 } 2232 } 2233 2234 cd->dc_rx_prod = 0; 2235 2236 return(0); 2237 } 2238 2239 /* 2240 * Initialize an RX descriptor and attach an MBUF cluster. 2241 */ 2242 static int dc_newbuf(sc, i, m) 2243 struct dc_softc *sc; 2244 int i; 2245 struct mbuf *m; 2246 { 2247 struct mbuf *m_new = NULL; 2248 struct dc_desc *c; 2249 2250 c = &sc->dc_ldata->dc_rx_list[i]; 2251 2252 if (m == NULL) { 2253 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 2254 if (m_new == NULL) { 2255 printf("dc%d: no memory for rx list " 2256 "-- packet dropped!\n", sc->dc_unit); 2257 return(ENOBUFS); 2258 } 2259 2260 MCLGET(m_new, M_DONTWAIT); 2261 if (!(m_new->m_flags & M_EXT)) { 2262 printf("dc%d: no memory for rx list " 2263 "-- packet dropped!\n", sc->dc_unit); 2264 m_freem(m_new); 2265 return(ENOBUFS); 2266 } 2267 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 2268 } else { 2269 m_new = m; 2270 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 2271 m_new->m_data = m_new->m_ext.ext_buf; 2272 } 2273 2274 m_adj(m_new, sizeof(u_int64_t)); 2275 2276 /* 2277 * If this is a PNIC chip, zero the buffer. This is part 2278 * of the workaround for the receive bug in the 82c168 and 2279 * 82c169 chips. 2280 */ 2281 if (sc->dc_flags & DC_PNIC_RX_BUG_WAR) 2282 bzero((char *)mtod(m_new, char *), m_new->m_len); 2283 2284 sc->dc_cdata.dc_rx_chain[i] = m_new; 2285 c->dc_data = vtophys(mtod(m_new, caddr_t)); 2286 c->dc_ctl = DC_RXCTL_RLINK | DC_RXLEN; 2287 c->dc_status = DC_RXSTAT_OWN; 2288 2289 return(0); 2290 } 2291 2292 /* 2293 * Grrrrr. 2294 * The PNIC chip has a terrible bug in it that manifests itself during 2295 * periods of heavy activity. The exact mode of failure if difficult to 2296 * pinpoint: sometimes it only happens in promiscuous mode, sometimes it 2297 * will happen on slow machines. The bug is that sometimes instead of 2298 * uploading one complete frame during reception, it uploads what looks 2299 * like the entire contents of its FIFO memory. The frame we want is at 2300 * the end of the whole mess, but we never know exactly how much data has 2301 * been uploaded, so salvaging the frame is hard. 2302 * 2303 * There is only one way to do it reliably, and it's disgusting. 2304 * Here's what we know: 2305 * 2306 * - We know there will always be somewhere between one and three extra 2307 * descriptors uploaded. 2308 * 2309 * - We know the desired received frame will always be at the end of the 2310 * total data upload. 2311 * 2312 * - We know the size of the desired received frame because it will be 2313 * provided in the length field of the status word in the last descriptor. 2314 * 2315 * Here's what we do: 2316 * 2317 * - When we allocate buffers for the receive ring, we bzero() them. 2318 * This means that we know that the buffer contents should be all 2319 * zeros, except for data uploaded by the chip. 2320 * 2321 * - We also force the PNIC chip to upload frames that include the 2322 * ethernet CRC at the end. 2323 * 2324 * - We gather all of the bogus frame data into a single buffer. 2325 * 2326 * - We then position a pointer at the end of this buffer and scan 2327 * backwards until we encounter the first non-zero byte of data. 2328 * This is the end of the received frame. We know we will encounter 2329 * some data at the end of the frame because the CRC will always be 2330 * there, so even if the sender transmits a packet of all zeros, 2331 * we won't be fooled. 2332 * 2333 * - We know the size of the actual received frame, so we subtract 2334 * that value from the current pointer location. This brings us 2335 * to the start of the actual received packet. 2336 * 2337 * - We copy this into an mbuf and pass it on, along with the actual 2338 * frame length. 2339 * 2340 * The performance hit is tremendous, but it beats dropping frames all 2341 * the time. 2342 */ 2343 2344 #define DC_WHOLEFRAME (DC_RXSTAT_FIRSTFRAG|DC_RXSTAT_LASTFRAG) 2345 static void dc_pnic_rx_bug_war(sc, idx) 2346 struct dc_softc *sc; 2347 int idx; 2348 { 2349 struct dc_desc *cur_rx; 2350 struct dc_desc *c = NULL; 2351 struct mbuf *m = NULL; 2352 unsigned char *ptr; 2353 int i, total_len; 2354 u_int32_t rxstat = 0; 2355 2356 i = sc->dc_pnic_rx_bug_save; 2357 cur_rx = &sc->dc_ldata->dc_rx_list[idx]; 2358 ptr = sc->dc_pnic_rx_buf; 2359 bzero(ptr, sizeof(DC_RXLEN * 5)); 2360 2361 /* Copy all the bytes from the bogus buffers. */ 2362 while (1) { 2363 c = &sc->dc_ldata->dc_rx_list[i]; 2364 rxstat = c->dc_status; 2365 m = sc->dc_cdata.dc_rx_chain[i]; 2366 bcopy(mtod(m, char *), ptr, DC_RXLEN); 2367 ptr += DC_RXLEN; 2368 /* If this is the last buffer, break out. */ 2369 if (i == idx || rxstat & DC_RXSTAT_LASTFRAG) 2370 break; 2371 dc_newbuf(sc, i, m); 2372 DC_INC(i, DC_RX_LIST_CNT); 2373 } 2374 2375 /* Find the length of the actual receive frame. */ 2376 total_len = DC_RXBYTES(rxstat); 2377 2378 /* Scan backwards until we hit a non-zero byte. */ 2379 while(*ptr == 0x00) 2380 ptr--; 2381 2382 /* Round off. */ 2383 if ((uintptr_t)(ptr) & 0x3) 2384 ptr -= 1; 2385 2386 /* Now find the start of the frame. */ 2387 ptr -= total_len; 2388 if (ptr < sc->dc_pnic_rx_buf) 2389 ptr = sc->dc_pnic_rx_buf; 2390 2391 /* 2392 * Now copy the salvaged frame to the last mbuf and fake up 2393 * the status word to make it look like a successful 2394 * frame reception. 2395 */ 2396 dc_newbuf(sc, i, m); 2397 bcopy(ptr, mtod(m, char *), total_len); 2398 cur_rx->dc_status = rxstat | DC_RXSTAT_FIRSTFRAG; 2399 2400 return; 2401 } 2402 2403 /* 2404 * This routine searches the RX ring for dirty descriptors in the 2405 * event that the rxeof routine falls out of sync with the chip's 2406 * current descriptor pointer. This may happen sometimes as a result 2407 * of a "no RX buffer available" condition that happens when the chip 2408 * consumes all of the RX buffers before the driver has a chance to 2409 * process the RX ring. This routine may need to be called more than 2410 * once to bring the driver back in sync with the chip, however we 2411 * should still be getting RX DONE interrupts to drive the search 2412 * for new packets in the RX ring, so we should catch up eventually. 2413 */ 2414 static int dc_rx_resync(sc) 2415 struct dc_softc *sc; 2416 { 2417 int i, pos; 2418 struct dc_desc *cur_rx; 2419 2420 pos = sc->dc_cdata.dc_rx_prod; 2421 2422 for (i = 0; i < DC_RX_LIST_CNT; i++) { 2423 cur_rx = &sc->dc_ldata->dc_rx_list[pos]; 2424 if (!(cur_rx->dc_status & DC_RXSTAT_OWN)) 2425 break; 2426 DC_INC(pos, DC_RX_LIST_CNT); 2427 } 2428 2429 /* If the ring really is empty, then just return. */ 2430 if (i == DC_RX_LIST_CNT) 2431 return(0); 2432 2433 /* We've fallen behing the chip: catch it. */ 2434 sc->dc_cdata.dc_rx_prod = pos; 2435 2436 return(EAGAIN); 2437 } 2438 2439 /* 2440 * A frame has been uploaded: pass the resulting mbuf chain up to 2441 * the higher level protocols. 2442 */ 2443 static void dc_rxeof(sc) 2444 struct dc_softc *sc; 2445 { 2446 struct ether_header *eh; 2447 struct mbuf *m; 2448 struct ifnet *ifp; 2449 struct dc_desc *cur_rx; 2450 int i, total_len = 0; 2451 u_int32_t rxstat; 2452 2453 ifp = &sc->arpcom.ac_if; 2454 i = sc->dc_cdata.dc_rx_prod; 2455 2456 while(!(sc->dc_ldata->dc_rx_list[i].dc_status & DC_RXSTAT_OWN)) { 2457 struct mbuf *m0 = NULL; 2458 2459 cur_rx = &sc->dc_ldata->dc_rx_list[i]; 2460 rxstat = cur_rx->dc_status; 2461 m = sc->dc_cdata.dc_rx_chain[i]; 2462 total_len = DC_RXBYTES(rxstat); 2463 2464 if (sc->dc_flags & DC_PNIC_RX_BUG_WAR) { 2465 if ((rxstat & DC_WHOLEFRAME) != DC_WHOLEFRAME) { 2466 if (rxstat & DC_RXSTAT_FIRSTFRAG) 2467 sc->dc_pnic_rx_bug_save = i; 2468 if ((rxstat & DC_RXSTAT_LASTFRAG) == 0) { 2469 DC_INC(i, DC_RX_LIST_CNT); 2470 continue; 2471 } 2472 dc_pnic_rx_bug_war(sc, i); 2473 rxstat = cur_rx->dc_status; 2474 total_len = DC_RXBYTES(rxstat); 2475 } 2476 } 2477 2478 sc->dc_cdata.dc_rx_chain[i] = NULL; 2479 2480 /* 2481 * If an error occurs, update stats, clear the 2482 * status word and leave the mbuf cluster in place: 2483 * it should simply get re-used next time this descriptor 2484 * comes up in the ring. 2485 */ 2486 if (rxstat & DC_RXSTAT_RXERR) { 2487 ifp->if_ierrors++; 2488 if (rxstat & DC_RXSTAT_COLLSEEN) 2489 ifp->if_collisions++; 2490 dc_newbuf(sc, i, m); 2491 if (rxstat & DC_RXSTAT_CRCERR) { 2492 DC_INC(i, DC_RX_LIST_CNT); 2493 continue; 2494 } else { 2495 dc_init(sc); 2496 return; 2497 } 2498 } 2499 2500 /* No errors; receive the packet. */ 2501 total_len -= ETHER_CRC_LEN; 2502 2503 m0 = m_devget(mtod(m, char *) - ETHER_ALIGN, 2504 total_len + ETHER_ALIGN, 0, ifp, NULL); 2505 dc_newbuf(sc, i, m); 2506 DC_INC(i, DC_RX_LIST_CNT); 2507 if (m0 == NULL) { 2508 ifp->if_ierrors++; 2509 continue; 2510 } 2511 m_adj(m0, ETHER_ALIGN); 2512 m = m0; 2513 2514 ifp->if_ipackets++; 2515 eh = mtod(m, struct ether_header *); 2516 2517 /* Remove header from mbuf and pass it on. */ 2518 m_adj(m, sizeof(struct ether_header)); 2519 ether_input(ifp, eh, m); 2520 } 2521 2522 sc->dc_cdata.dc_rx_prod = i; 2523 } 2524 2525 /* 2526 * A frame was downloaded to the chip. It's safe for us to clean up 2527 * the list buffers. 2528 */ 2529 2530 static void dc_txeof(sc) 2531 struct dc_softc *sc; 2532 { 2533 struct dc_desc *cur_tx = NULL; 2534 struct ifnet *ifp; 2535 int idx; 2536 2537 ifp = &sc->arpcom.ac_if; 2538 2539 /* Clear the timeout timer. */ 2540 ifp->if_timer = 0; 2541 2542 /* 2543 * Go through our tx list and free mbufs for those 2544 * frames that have been transmitted. 2545 */ 2546 idx = sc->dc_cdata.dc_tx_cons; 2547 while(idx != sc->dc_cdata.dc_tx_prod) { 2548 u_int32_t txstat; 2549 2550 cur_tx = &sc->dc_ldata->dc_tx_list[idx]; 2551 txstat = cur_tx->dc_status; 2552 2553 if (txstat & DC_TXSTAT_OWN) 2554 break; 2555 2556 if (!(cur_tx->dc_ctl & DC_TXCTL_LASTFRAG) || 2557 cur_tx->dc_ctl & DC_TXCTL_SETUP) { 2558 sc->dc_cdata.dc_tx_cnt--; 2559 if (cur_tx->dc_ctl & DC_TXCTL_SETUP) { 2560 /* 2561 * Yes, the PNIC is so brain damaged 2562 * that it will sometimes generate a TX 2563 * underrun error while DMAing the RX 2564 * filter setup frame. If we detect this, 2565 * we have to send the setup frame again, 2566 * or else the filter won't be programmed 2567 * correctly. 2568 */ 2569 if (DC_IS_PNIC(sc)) { 2570 if (txstat & DC_TXSTAT_ERRSUM) 2571 dc_setfilt(sc); 2572 } 2573 sc->dc_cdata.dc_tx_chain[idx] = NULL; 2574 } 2575 DC_INC(idx, DC_TX_LIST_CNT); 2576 continue; 2577 } 2578 2579 if (DC_IS_XIRCOM(sc)) { 2580 /* 2581 * XXX: Why does my Xircom taunt me so? 2582 * For some reason it likes setting the CARRLOST flag 2583 * even when the carrier is there. wtf?!? */ 2584 if (/*sc->dc_type == DC_TYPE_21143 &&*/ 2585 sc->dc_pmode == DC_PMODE_MII && 2586 ((txstat & 0xFFFF) & ~(DC_TXSTAT_ERRSUM| 2587 DC_TXSTAT_NOCARRIER))) 2588 txstat &= ~DC_TXSTAT_ERRSUM; 2589 } else { 2590 if (/*sc->dc_type == DC_TYPE_21143 &&*/ 2591 sc->dc_pmode == DC_PMODE_MII && 2592 ((txstat & 0xFFFF) & ~(DC_TXSTAT_ERRSUM| 2593 DC_TXSTAT_NOCARRIER|DC_TXSTAT_CARRLOST))) 2594 txstat &= ~DC_TXSTAT_ERRSUM; 2595 } 2596 2597 if (txstat & DC_TXSTAT_ERRSUM) { 2598 ifp->if_oerrors++; 2599 if (txstat & DC_TXSTAT_EXCESSCOLL) 2600 ifp->if_collisions++; 2601 if (txstat & DC_TXSTAT_LATECOLL) 2602 ifp->if_collisions++; 2603 if (!(txstat & DC_TXSTAT_UNDERRUN)) { 2604 dc_init(sc); 2605 return; 2606 } 2607 } 2608 2609 ifp->if_collisions += (txstat & DC_TXSTAT_COLLCNT) >> 3; 2610 2611 ifp->if_opackets++; 2612 if (sc->dc_cdata.dc_tx_chain[idx] != NULL) { 2613 m_freem(sc->dc_cdata.dc_tx_chain[idx]); 2614 sc->dc_cdata.dc_tx_chain[idx] = NULL; 2615 } 2616 2617 sc->dc_cdata.dc_tx_cnt--; 2618 DC_INC(idx, DC_TX_LIST_CNT); 2619 } 2620 2621 sc->dc_cdata.dc_tx_cons = idx; 2622 if (cur_tx != NULL) 2623 ifp->if_flags &= ~IFF_OACTIVE; 2624 2625 return; 2626 } 2627 2628 static void dc_tick(xsc) 2629 void *xsc; 2630 { 2631 struct dc_softc *sc; 2632 struct mii_data *mii; 2633 struct ifnet *ifp; 2634 u_int32_t r; 2635 2636 sc = xsc; 2637 DC_LOCK(sc); 2638 ifp = &sc->arpcom.ac_if; 2639 mii = device_get_softc(sc->dc_miibus); 2640 2641 if (sc->dc_flags & DC_REDUCED_MII_POLL) { 2642 if (sc->dc_flags & DC_21143_NWAY) { 2643 r = CSR_READ_4(sc, DC_10BTSTAT); 2644 if (IFM_SUBTYPE(mii->mii_media_active) == 2645 IFM_100_TX && (r & DC_TSTAT_LS100)) { 2646 sc->dc_link = 0; 2647 mii_mediachg(mii); 2648 } 2649 if (IFM_SUBTYPE(mii->mii_media_active) == 2650 IFM_10_T && (r & DC_TSTAT_LS10)) { 2651 sc->dc_link = 0; 2652 mii_mediachg(mii); 2653 } 2654 if (sc->dc_link == 0) 2655 mii_tick(mii); 2656 } else { 2657 r = CSR_READ_4(sc, DC_ISR); 2658 if ((r & DC_ISR_RX_STATE) == DC_RXSTATE_WAIT && 2659 sc->dc_cdata.dc_tx_cnt == 0) 2660 mii_tick(mii); 2661 if (!(mii->mii_media_status & IFM_ACTIVE)) 2662 sc->dc_link = 0; 2663 } 2664 } else 2665 mii_tick(mii); 2666 2667 /* 2668 * When the init routine completes, we expect to be able to send 2669 * packets right away, and in fact the network code will send a 2670 * gratuitous ARP the moment the init routine marks the interface 2671 * as running. However, even though the MAC may have been initialized, 2672 * there may be a delay of a few seconds before the PHY completes 2673 * autonegotiation and the link is brought up. Any transmissions 2674 * made during that delay will be lost. Dealing with this is tricky: 2675 * we can't just pause in the init routine while waiting for the 2676 * PHY to come ready since that would bring the whole system to 2677 * a screeching halt for several seconds. 2678 * 2679 * What we do here is prevent the TX start routine from sending 2680 * any packets until a link has been established. After the 2681 * interface has been initialized, the tick routine will poll 2682 * the state of the PHY until the IFM_ACTIVE flag is set. Until 2683 * that time, packets will stay in the send queue, and once the 2684 * link comes up, they will be flushed out to the wire. 2685 */ 2686 if (!sc->dc_link) { 2687 mii_pollstat(mii); 2688 if (mii->mii_media_status & IFM_ACTIVE && 2689 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) { 2690 sc->dc_link++; 2691 if (ifp->if_snd.ifq_head != NULL) 2692 dc_start(ifp); 2693 } 2694 } 2695 2696 if (sc->dc_flags & DC_21143_NWAY && !sc->dc_link) 2697 callout_reset(&sc->dc_stat_ch, hz/10, dc_tick, sc); 2698 else 2699 callout_reset(&sc->dc_stat_ch, hz, dc_tick, sc); 2700 2701 DC_UNLOCK(sc); 2702 2703 return; 2704 } 2705 2706 static void dc_intr(arg) 2707 void *arg; 2708 { 2709 struct dc_softc *sc; 2710 struct ifnet *ifp; 2711 u_int32_t status; 2712 2713 sc = arg; 2714 DC_LOCK(sc); 2715 ifp = &sc->arpcom.ac_if; 2716 2717 /* Supress unwanted interrupts */ 2718 if (!(ifp->if_flags & IFF_UP)) { 2719 if (CSR_READ_4(sc, DC_ISR) & DC_INTRS) 2720 dc_stop(sc); 2721 DC_UNLOCK(sc); 2722 return; 2723 } 2724 2725 /* Disable interrupts. */ 2726 CSR_WRITE_4(sc, DC_IMR, 0x00000000); 2727 2728 while(((status = CSR_READ_4(sc, DC_ISR)) & DC_INTRS) 2729 && status != 0xFFFFFFFF) { 2730 2731 CSR_WRITE_4(sc, DC_ISR, status); 2732 2733 if (status & DC_ISR_RX_OK) { 2734 int curpkts; 2735 curpkts = ifp->if_ipackets; 2736 dc_rxeof(sc); 2737 if (curpkts == ifp->if_ipackets) { 2738 while(dc_rx_resync(sc)) 2739 dc_rxeof(sc); 2740 } 2741 } 2742 2743 if (status & (DC_ISR_TX_OK|DC_ISR_TX_NOBUF)) 2744 dc_txeof(sc); 2745 2746 if (status & DC_ISR_TX_IDLE) { 2747 dc_txeof(sc); 2748 if (sc->dc_cdata.dc_tx_cnt) { 2749 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_TX_ON); 2750 CSR_WRITE_4(sc, DC_TXSTART, 0xFFFFFFFF); 2751 } 2752 } 2753 2754 if (status & DC_ISR_TX_UNDERRUN) { 2755 u_int32_t cfg; 2756 2757 printf("dc%d: TX underrun -- ", sc->dc_unit); 2758 if (DC_IS_DAVICOM(sc) || DC_IS_INTEL(sc)) 2759 dc_init(sc); 2760 cfg = CSR_READ_4(sc, DC_NETCFG); 2761 cfg &= ~DC_NETCFG_TX_THRESH; 2762 if (sc->dc_txthresh == DC_TXTHRESH_160BYTES) { 2763 printf("using store and forward mode\n"); 2764 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_STORENFWD); 2765 } else if (sc->dc_flags & DC_TX_STORENFWD) { 2766 printf("resetting\n"); 2767 } else { 2768 sc->dc_txthresh += 0x4000; 2769 printf("increasing TX threshold\n"); 2770 CSR_WRITE_4(sc, DC_NETCFG, cfg); 2771 DC_SETBIT(sc, DC_NETCFG, sc->dc_txthresh); 2772 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_STORENFWD); 2773 } 2774 } 2775 2776 if ((status & DC_ISR_RX_WATDOGTIMEO) 2777 || (status & DC_ISR_RX_NOBUF)) { 2778 int curpkts; 2779 curpkts = ifp->if_ipackets; 2780 dc_rxeof(sc); 2781 if (curpkts == ifp->if_ipackets) { 2782 while(dc_rx_resync(sc)) 2783 dc_rxeof(sc); 2784 } 2785 } 2786 2787 if (status & DC_ISR_BUS_ERR) { 2788 dc_reset(sc); 2789 dc_init(sc); 2790 } 2791 } 2792 2793 /* Re-enable interrupts. */ 2794 CSR_WRITE_4(sc, DC_IMR, DC_INTRS); 2795 2796 if (ifp->if_snd.ifq_head != NULL) 2797 dc_start(ifp); 2798 2799 DC_UNLOCK(sc); 2800 2801 return; 2802 } 2803 2804 /* 2805 * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data 2806 * pointers to the fragment pointers. 2807 */ 2808 static int dc_encap(sc, m_head, txidx) 2809 struct dc_softc *sc; 2810 struct mbuf *m_head; 2811 u_int32_t *txidx; 2812 { 2813 struct dc_desc *f = NULL; 2814 struct mbuf *m; 2815 int frag, cur, cnt = 0; 2816 2817 /* 2818 * Start packing the mbufs in this chain into 2819 * the fragment pointers. Stop when we run out 2820 * of fragments or hit the end of the mbuf chain. 2821 */ 2822 m = m_head; 2823 cur = frag = *txidx; 2824 2825 for (m = m_head; m != NULL; m = m->m_next) { 2826 if (m->m_len != 0) { 2827 if (sc->dc_flags & DC_TX_ADMTEK_WAR) { 2828 if (*txidx != sc->dc_cdata.dc_tx_prod && 2829 frag == (DC_TX_LIST_CNT - 1)) 2830 return(ENOBUFS); 2831 } 2832 if ((DC_TX_LIST_CNT - 2833 (sc->dc_cdata.dc_tx_cnt + cnt)) < 5) 2834 return(ENOBUFS); 2835 2836 f = &sc->dc_ldata->dc_tx_list[frag]; 2837 f->dc_ctl = DC_TXCTL_TLINK | m->m_len; 2838 if (cnt == 0) { 2839 f->dc_status = 0; 2840 f->dc_ctl |= DC_TXCTL_FIRSTFRAG; 2841 } else 2842 f->dc_status = DC_TXSTAT_OWN; 2843 f->dc_data = vtophys(mtod(m, vm_offset_t)); 2844 cur = frag; 2845 DC_INC(frag, DC_TX_LIST_CNT); 2846 cnt++; 2847 } 2848 } 2849 2850 if (m != NULL) 2851 return(ENOBUFS); 2852 2853 sc->dc_cdata.dc_tx_cnt += cnt; 2854 sc->dc_cdata.dc_tx_chain[cur] = m_head; 2855 sc->dc_ldata->dc_tx_list[cur].dc_ctl |= DC_TXCTL_LASTFRAG; 2856 if (sc->dc_flags & DC_TX_INTR_FIRSTFRAG) 2857 sc->dc_ldata->dc_tx_list[*txidx].dc_ctl |= DC_TXCTL_FINT; 2858 if (sc->dc_flags & DC_TX_INTR_ALWAYS) 2859 sc->dc_ldata->dc_tx_list[cur].dc_ctl |= DC_TXCTL_FINT; 2860 if (sc->dc_flags & DC_TX_USE_TX_INTR && sc->dc_cdata.dc_tx_cnt > 64) 2861 sc->dc_ldata->dc_tx_list[cur].dc_ctl |= DC_TXCTL_FINT; 2862 sc->dc_ldata->dc_tx_list[*txidx].dc_status = DC_TXSTAT_OWN; 2863 *txidx = frag; 2864 2865 return(0); 2866 } 2867 2868 /* 2869 * Coalesce an mbuf chain into a single mbuf cluster buffer. 2870 * Needed for some really badly behaved chips that just can't 2871 * do scatter/gather correctly. 2872 */ 2873 static int dc_coal(sc, m_head) 2874 struct dc_softc *sc; 2875 struct mbuf **m_head; 2876 { 2877 struct mbuf *m_new, *m; 2878 2879 m = *m_head; 2880 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 2881 if (m_new == NULL) { 2882 printf("dc%d: no memory for tx list", sc->dc_unit); 2883 return(ENOBUFS); 2884 } 2885 if (m->m_pkthdr.len > MHLEN) { 2886 MCLGET(m_new, M_DONTWAIT); 2887 if (!(m_new->m_flags & M_EXT)) { 2888 m_freem(m_new); 2889 printf("dc%d: no memory for tx list", sc->dc_unit); 2890 return(ENOBUFS); 2891 } 2892 } 2893 m_copydata(m, 0, m->m_pkthdr.len, mtod(m_new, caddr_t)); 2894 m_new->m_pkthdr.len = m_new->m_len = m->m_pkthdr.len; 2895 m_freem(m); 2896 *m_head = m_new; 2897 2898 return(0); 2899 } 2900 2901 /* 2902 * Main transmit routine. To avoid having to do mbuf copies, we put pointers 2903 * to the mbuf data regions directly in the transmit lists. We also save a 2904 * copy of the pointers since the transmit list fragment pointers are 2905 * physical addresses. 2906 */ 2907 2908 static void dc_start(ifp) 2909 struct ifnet *ifp; 2910 { 2911 struct dc_softc *sc; 2912 struct mbuf *m_head = NULL; 2913 int idx; 2914 2915 sc = ifp->if_softc; 2916 2917 DC_LOCK(sc); 2918 2919 if (!sc->dc_link) { 2920 DC_UNLOCK(sc); 2921 return; 2922 } 2923 2924 if (ifp->if_flags & IFF_OACTIVE) { 2925 DC_UNLOCK(sc); 2926 return; 2927 } 2928 2929 idx = sc->dc_cdata.dc_tx_prod; 2930 2931 while(sc->dc_cdata.dc_tx_chain[idx] == NULL) { 2932 IF_DEQUEUE(&ifp->if_snd, m_head); 2933 if (m_head == NULL) 2934 break; 2935 2936 if (sc->dc_flags & DC_TX_COALESCE) { 2937 if (dc_coal(sc, &m_head)) { 2938 IF_PREPEND(&ifp->if_snd, m_head); 2939 ifp->if_flags |= IFF_OACTIVE; 2940 break; 2941 } 2942 } 2943 2944 if (dc_encap(sc, m_head, &idx)) { 2945 IF_PREPEND(&ifp->if_snd, m_head); 2946 ifp->if_flags |= IFF_OACTIVE; 2947 break; 2948 } 2949 2950 /* 2951 * If there's a BPF listener, bounce a copy of this frame 2952 * to him. 2953 */ 2954 if (ifp->if_bpf) 2955 bpf_mtap(ifp, m_head); 2956 2957 if (sc->dc_flags & DC_TX_ONE) { 2958 ifp->if_flags |= IFF_OACTIVE; 2959 break; 2960 } 2961 } 2962 2963 /* Transmit */ 2964 sc->dc_cdata.dc_tx_prod = idx; 2965 if (!(sc->dc_flags & DC_TX_POLL)) 2966 CSR_WRITE_4(sc, DC_TXSTART, 0xFFFFFFFF); 2967 2968 /* 2969 * Set a timeout in case the chip goes out to lunch. 2970 */ 2971 ifp->if_timer = 5; 2972 2973 DC_UNLOCK(sc); 2974 2975 return; 2976 } 2977 2978 static void dc_init(xsc) 2979 void *xsc; 2980 { 2981 struct dc_softc *sc = xsc; 2982 struct ifnet *ifp = &sc->arpcom.ac_if; 2983 struct mii_data *mii; 2984 2985 DC_LOCK(sc); 2986 2987 mii = device_get_softc(sc->dc_miibus); 2988 2989 /* 2990 * Cancel pending I/O and free all RX/TX buffers. 2991 */ 2992 dc_stop(sc); 2993 dc_reset(sc); 2994 2995 /* 2996 * Set cache alignment and burst length. 2997 */ 2998 if (DC_IS_ASIX(sc) || DC_IS_DAVICOM(sc)) 2999 CSR_WRITE_4(sc, DC_BUSCTL, 0); 3000 else 3001 CSR_WRITE_4(sc, DC_BUSCTL, DC_BUSCTL_MRME|DC_BUSCTL_MRLE); 3002 if (DC_IS_DAVICOM(sc) || DC_IS_INTEL(sc)) { 3003 DC_SETBIT(sc, DC_BUSCTL, DC_BURSTLEN_USECA); 3004 } else { 3005 DC_SETBIT(sc, DC_BUSCTL, DC_BURSTLEN_16LONG); 3006 } 3007 if (sc->dc_flags & DC_TX_POLL) 3008 DC_SETBIT(sc, DC_BUSCTL, DC_TXPOLL_1); 3009 switch(sc->dc_cachesize) { 3010 case 32: 3011 DC_SETBIT(sc, DC_BUSCTL, DC_CACHEALIGN_32LONG); 3012 break; 3013 case 16: 3014 DC_SETBIT(sc, DC_BUSCTL, DC_CACHEALIGN_16LONG); 3015 break; 3016 case 8: 3017 DC_SETBIT(sc, DC_BUSCTL, DC_CACHEALIGN_8LONG); 3018 break; 3019 case 0: 3020 default: 3021 DC_SETBIT(sc, DC_BUSCTL, DC_CACHEALIGN_NONE); 3022 break; 3023 } 3024 3025 if (sc->dc_flags & DC_TX_STORENFWD) 3026 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_STORENFWD); 3027 else { 3028 if (sc->dc_txthresh == DC_TXTHRESH_160BYTES) { 3029 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_STORENFWD); 3030 } else { 3031 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_STORENFWD); 3032 DC_SETBIT(sc, DC_NETCFG, sc->dc_txthresh); 3033 } 3034 } 3035 3036 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_NO_RXCRC); 3037 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_TX_BACKOFF); 3038 3039 if (DC_IS_MACRONIX(sc) || DC_IS_PNICII(sc)) { 3040 /* 3041 * The app notes for the 98713 and 98715A say that 3042 * in order to have the chips operate properly, a magic 3043 * number must be written to CSR16. Macronix does not 3044 * document the meaning of these bits so there's no way 3045 * to know exactly what they do. The 98713 has a magic 3046 * number all its own; the rest all use a different one. 3047 */ 3048 DC_CLRBIT(sc, DC_MX_MAGICPACKET, 0xFFFF0000); 3049 if (sc->dc_type == DC_TYPE_98713) 3050 DC_SETBIT(sc, DC_MX_MAGICPACKET, DC_MX_MAGIC_98713); 3051 else 3052 DC_SETBIT(sc, DC_MX_MAGICPACKET, DC_MX_MAGIC_98715); 3053 } 3054 3055 if (DC_IS_XIRCOM(sc)) { 3056 /* 3057 * setup General Purpose Port mode and data so the tulip 3058 * can talk to the MII. 3059 */ 3060 CSR_WRITE_4(sc, DC_SIAGP, DC_SIAGP_WRITE_EN | DC_SIAGP_INT1_EN | 3061 DC_SIAGP_MD_GP2_OUTPUT | DC_SIAGP_MD_GP0_OUTPUT); 3062 DELAY(10); 3063 CSR_WRITE_4(sc, DC_SIAGP, DC_SIAGP_INT1_EN | 3064 DC_SIAGP_MD_GP2_OUTPUT | DC_SIAGP_MD_GP0_OUTPUT); 3065 DELAY(10); 3066 } 3067 3068 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_TX_THRESH); 3069 DC_SETBIT(sc, DC_NETCFG, DC_TXTHRESH_72BYTES); 3070 3071 /* Init circular RX list. */ 3072 if (dc_list_rx_init(sc) == ENOBUFS) { 3073 printf("dc%d: initialization failed: no " 3074 "memory for rx buffers\n", sc->dc_unit); 3075 dc_stop(sc); 3076 DC_UNLOCK(sc); 3077 return; 3078 } 3079 3080 /* 3081 * Init tx descriptors. 3082 */ 3083 dc_list_tx_init(sc); 3084 3085 /* 3086 * Load the address of the RX list. 3087 */ 3088 CSR_WRITE_4(sc, DC_RXADDR, vtophys(&sc->dc_ldata->dc_rx_list[0])); 3089 CSR_WRITE_4(sc, DC_TXADDR, vtophys(&sc->dc_ldata->dc_tx_list[0])); 3090 3091 /* 3092 * Enable interrupts. 3093 */ 3094 CSR_WRITE_4(sc, DC_IMR, DC_INTRS); 3095 CSR_WRITE_4(sc, DC_ISR, 0xFFFFFFFF); 3096 3097 /* Enable transmitter. */ 3098 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_TX_ON); 3099 3100 /* 3101 * If this is an Intel 21143 and we're not using the 3102 * MII port, program the LED control pins so we get 3103 * link and activity indications. 3104 */ 3105 if (sc->dc_flags & DC_TULIP_LEDS) { 3106 CSR_WRITE_4(sc, DC_WATCHDOG, 3107 DC_WDOG_CTLWREN|DC_WDOG_LINK|DC_WDOG_ACTIVITY); 3108 CSR_WRITE_4(sc, DC_WATCHDOG, 0); 3109 } 3110 3111 /* 3112 * Load the RX/multicast filter. We do this sort of late 3113 * because the filter programming scheme on the 21143 and 3114 * some clones requires DMAing a setup frame via the TX 3115 * engine, and we need the transmitter enabled for that. 3116 */ 3117 dc_setfilt(sc); 3118 3119 /* Enable receiver. */ 3120 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_ON); 3121 CSR_WRITE_4(sc, DC_RXSTART, 0xFFFFFFFF); 3122 3123 mii_mediachg(mii); 3124 dc_setcfg(sc, sc->dc_if_media); 3125 3126 ifp->if_flags |= IFF_RUNNING; 3127 ifp->if_flags &= ~IFF_OACTIVE; 3128 3129 /* Don't start the ticker if this is a homePNA link. */ 3130 if (IFM_SUBTYPE(mii->mii_media.ifm_media) == IFM_homePNA) 3131 sc->dc_link = 1; 3132 else { 3133 if (sc->dc_flags & DC_21143_NWAY) 3134 callout_reset(&sc->dc_stat_ch, hz/10, dc_tick, sc); 3135 else 3136 callout_reset(&sc->dc_stat_ch, hz, dc_tick, sc); 3137 } 3138 3139 #ifdef SRM_MEDIA 3140 if(sc->dc_srm_media) { 3141 struct ifreq ifr; 3142 3143 ifr.ifr_media = sc->dc_srm_media; 3144 ifmedia_ioctl(ifp, &ifr, &mii->mii_media, SIOCSIFMEDIA); 3145 sc->dc_srm_media = 0; 3146 } 3147 #endif 3148 DC_UNLOCK(sc); 3149 return; 3150 } 3151 3152 /* 3153 * Set media options. 3154 */ 3155 static int dc_ifmedia_upd(ifp) 3156 struct ifnet *ifp; 3157 { 3158 struct dc_softc *sc; 3159 struct mii_data *mii; 3160 struct ifmedia *ifm; 3161 3162 sc = ifp->if_softc; 3163 mii = device_get_softc(sc->dc_miibus); 3164 mii_mediachg(mii); 3165 ifm = &mii->mii_media; 3166 3167 if (DC_IS_DAVICOM(sc) && 3168 IFM_SUBTYPE(ifm->ifm_media) == IFM_homePNA) 3169 dc_setcfg(sc, ifm->ifm_media); 3170 else 3171 sc->dc_link = 0; 3172 3173 return(0); 3174 } 3175 3176 /* 3177 * Report current media status. 3178 */ 3179 static void dc_ifmedia_sts(ifp, ifmr) 3180 struct ifnet *ifp; 3181 struct ifmediareq *ifmr; 3182 { 3183 struct dc_softc *sc; 3184 struct mii_data *mii; 3185 struct ifmedia *ifm; 3186 3187 sc = ifp->if_softc; 3188 mii = device_get_softc(sc->dc_miibus); 3189 mii_pollstat(mii); 3190 ifm = &mii->mii_media; 3191 if (DC_IS_DAVICOM(sc)) { 3192 if (IFM_SUBTYPE(ifm->ifm_media) == IFM_homePNA) { 3193 ifmr->ifm_active = ifm->ifm_media; 3194 ifmr->ifm_status = 0; 3195 return; 3196 } 3197 } 3198 ifmr->ifm_active = mii->mii_media_active; 3199 ifmr->ifm_status = mii->mii_media_status; 3200 3201 return; 3202 } 3203 3204 static int dc_ioctl(ifp, command, data) 3205 struct ifnet *ifp; 3206 u_long command; 3207 caddr_t data; 3208 { 3209 struct dc_softc *sc = ifp->if_softc; 3210 struct ifreq *ifr = (struct ifreq *) data; 3211 struct mii_data *mii; 3212 int error = 0; 3213 3214 DC_LOCK(sc); 3215 3216 switch(command) { 3217 case SIOCSIFADDR: 3218 case SIOCGIFADDR: 3219 case SIOCSIFMTU: 3220 error = ether_ioctl(ifp, command, data); 3221 break; 3222 case SIOCSIFFLAGS: 3223 if (ifp->if_flags & IFF_UP) { 3224 if (ifp->if_flags & IFF_RUNNING && 3225 ifp->if_flags & IFF_PROMISC && 3226 !(sc->dc_if_flags & IFF_PROMISC)) { 3227 dc_setfilt(sc); 3228 } else if (ifp->if_flags & IFF_RUNNING && 3229 !(ifp->if_flags & IFF_PROMISC) && 3230 sc->dc_if_flags & IFF_PROMISC) { 3231 dc_setfilt(sc); 3232 } else if (!(ifp->if_flags & IFF_RUNNING)) { 3233 sc->dc_txthresh = 0; 3234 dc_init(sc); 3235 } 3236 } else { 3237 if (ifp->if_flags & IFF_RUNNING) 3238 dc_stop(sc); 3239 } 3240 sc->dc_if_flags = ifp->if_flags; 3241 error = 0; 3242 break; 3243 case SIOCADDMULTI: 3244 case SIOCDELMULTI: 3245 dc_setfilt(sc); 3246 error = 0; 3247 break; 3248 case SIOCGIFMEDIA: 3249 case SIOCSIFMEDIA: 3250 mii = device_get_softc(sc->dc_miibus); 3251 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 3252 #ifdef SRM_MEDIA 3253 if (sc->dc_srm_media) 3254 sc->dc_srm_media = 0; 3255 #endif 3256 break; 3257 default: 3258 error = EINVAL; 3259 break; 3260 } 3261 3262 DC_UNLOCK(sc); 3263 3264 return(error); 3265 } 3266 3267 static void dc_watchdog(ifp) 3268 struct ifnet *ifp; 3269 { 3270 struct dc_softc *sc; 3271 3272 sc = ifp->if_softc; 3273 3274 DC_LOCK(sc); 3275 3276 ifp->if_oerrors++; 3277 printf("dc%d: watchdog timeout\n", sc->dc_unit); 3278 3279 dc_stop(sc); 3280 dc_reset(sc); 3281 dc_init(sc); 3282 3283 if (ifp->if_snd.ifq_head != NULL) 3284 dc_start(ifp); 3285 3286 DC_UNLOCK(sc); 3287 3288 return; 3289 } 3290 3291 /* 3292 * Stop the adapter and free any mbufs allocated to the 3293 * RX and TX lists. 3294 */ 3295 static void dc_stop(sc) 3296 struct dc_softc *sc; 3297 { 3298 register int i; 3299 struct ifnet *ifp; 3300 3301 DC_LOCK(sc); 3302 3303 ifp = &sc->arpcom.ac_if; 3304 ifp->if_timer = 0; 3305 3306 callout_stop(&sc->dc_stat_ch); 3307 3308 DC_CLRBIT(sc, DC_NETCFG, (DC_NETCFG_RX_ON|DC_NETCFG_TX_ON)); 3309 CSR_WRITE_4(sc, DC_IMR, 0x00000000); 3310 CSR_WRITE_4(sc, DC_TXADDR, 0x00000000); 3311 CSR_WRITE_4(sc, DC_RXADDR, 0x00000000); 3312 sc->dc_link = 0; 3313 3314 /* 3315 * Free data in the RX lists. 3316 */ 3317 for (i = 0; i < DC_RX_LIST_CNT; i++) { 3318 if (sc->dc_cdata.dc_rx_chain[i] != NULL) { 3319 m_freem(sc->dc_cdata.dc_rx_chain[i]); 3320 sc->dc_cdata.dc_rx_chain[i] = NULL; 3321 } 3322 } 3323 bzero((char *)&sc->dc_ldata->dc_rx_list, 3324 sizeof(sc->dc_ldata->dc_rx_list)); 3325 3326 /* 3327 * Free the TX list buffers. 3328 */ 3329 for (i = 0; i < DC_TX_LIST_CNT; i++) { 3330 if (sc->dc_cdata.dc_tx_chain[i] != NULL) { 3331 if (sc->dc_ldata->dc_tx_list[i].dc_ctl & 3332 DC_TXCTL_SETUP) { 3333 sc->dc_cdata.dc_tx_chain[i] = NULL; 3334 continue; 3335 } 3336 m_freem(sc->dc_cdata.dc_tx_chain[i]); 3337 sc->dc_cdata.dc_tx_chain[i] = NULL; 3338 } 3339 } 3340 3341 bzero((char *)&sc->dc_ldata->dc_tx_list, 3342 sizeof(sc->dc_ldata->dc_tx_list)); 3343 3344 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 3345 3346 DC_UNLOCK(sc); 3347 3348 return; 3349 } 3350 3351 /* 3352 * Stop all chip I/O so that the kernel's probe routines don't 3353 * get confused by errant DMAs when rebooting. 3354 */ 3355 static void dc_shutdown(dev) 3356 device_t dev; 3357 { 3358 struct dc_softc *sc; 3359 3360 sc = device_get_softc(dev); 3361 3362 dc_stop(sc); 3363 3364 return; 3365 } 3366