1 /* 2 * Copyright (c) 1997, 1998, 1999 3 * Bill Paul <wpaul@ee.columbia.edu>. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 3. All advertising materials mentioning features or use of this software 14 * must display the following acknowledgement: 15 * This product includes software developed by Bill Paul. 16 * 4. Neither the name of the author nor the names of any co-contributors 17 * may be used to endorse or promote products derived from this software 18 * without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30 * THE POSSIBILITY OF SUCH DAMAGE. 31 * 32 * $FreeBSD$ 33 */ 34 35 /* 36 * DEC "tulip" clone ethernet driver. Supports the DEC/Intel 21143 37 * series chips and several workalikes including the following: 38 * 39 * Macronix 98713/98715/98725/98727/98732 PMAC (www.macronix.com) 40 * Macronix/Lite-On 82c115 PNIC II (www.macronix.com) 41 * Lite-On 82c168/82c169 PNIC (www.litecom.com) 42 * ASIX Electronics AX88140A (www.asix.com.tw) 43 * ASIX Electronics AX88141 (www.asix.com.tw) 44 * ADMtek AL981 (www.admtek.com.tw) 45 * ADMtek AN985 (www.admtek.com.tw) 46 * Davicom DM9100, DM9102, DM9102A (www.davicom8.com) 47 * Accton EN1217 (www.accton.com) 48 * Xircom X3201 (www.xircom.com) 49 * Abocom FE2500 50 * Conexant LANfinity (www.conexant.com) 51 * 52 * Datasheets for the 21143 are available at developer.intel.com. 53 * Datasheets for the clone parts can be found at their respective sites. 54 * (Except for the PNIC; see www.freebsd.org/~wpaul/PNIC/pnic.ps.gz.) 55 * The PNIC II is essentially a Macronix 98715A chip; the only difference 56 * worth noting is that its multicast hash table is only 128 bits wide 57 * instead of 512. 58 * 59 * Written by Bill Paul <wpaul@ee.columbia.edu> 60 * Electrical Engineering Department 61 * Columbia University, New York City 62 */ 63 64 /* 65 * The Intel 21143 is the successor to the DEC 21140. It is basically 66 * the same as the 21140 but with a few new features. The 21143 supports 67 * three kinds of media attachments: 68 * 69 * o MII port, for 10Mbps and 100Mbps support and NWAY 70 * autonegotiation provided by an external PHY. 71 * o SYM port, for symbol mode 100Mbps support. 72 * o 10baseT port. 73 * o AUI/BNC port. 74 * 75 * The 100Mbps SYM port and 10baseT port can be used together in 76 * combination with the internal NWAY support to create a 10/100 77 * autosensing configuration. 78 * 79 * Note that not all tulip workalikes are handled in this driver: we only 80 * deal with those which are relatively well behaved. The Winbond is 81 * handled separately due to its different register offsets and the 82 * special handling needed for its various bugs. The PNIC is handled 83 * here, but I'm not thrilled about it. 84 * 85 * All of the workalike chips use some form of MII transceiver support 86 * with the exception of the Macronix chips, which also have a SYM port. 87 * The ASIX AX88140A is also documented to have a SYM port, but all 88 * the cards I've seen use an MII transceiver, probably because the 89 * AX88140A doesn't support internal NWAY. 90 */ 91 92 #include <sys/param.h> 93 #include <sys/systm.h> 94 #include <sys/sockio.h> 95 #include <sys/mbuf.h> 96 #include <sys/malloc.h> 97 #include <sys/kernel.h> 98 #include <sys/socket.h> 99 #include <sys/sysctl.h> 100 101 #include <net/if.h> 102 #include <net/if_arp.h> 103 #include <net/ethernet.h> 104 #include <net/if_dl.h> 105 #include <net/if_media.h> 106 #include <net/if_types.h> 107 #include <net/if_vlan_var.h> 108 109 #include <net/bpf.h> 110 111 #include <vm/vm.h> /* for vtophys */ 112 #include <vm/pmap.h> /* for vtophys */ 113 #include <machine/bus_pio.h> 114 #include <machine/bus_memio.h> 115 #include <machine/bus.h> 116 #include <machine/resource.h> 117 #include <sys/bus.h> 118 #include <sys/rman.h> 119 120 #include <dev/mii/mii.h> 121 #include <dev/mii/miivar.h> 122 123 #include <pci/pcireg.h> 124 #include <pci/pcivar.h> 125 126 #define DC_USEIOSPACE 127 #ifdef __alpha__ 128 #define SRM_MEDIA 129 #endif 130 131 #include <pci/if_dcreg.h> 132 133 MODULE_DEPEND(dc, miibus, 1, 1, 1); 134 135 /* "controller miibus0" required. See GENERIC if you get errors here. */ 136 #include "miibus_if.h" 137 138 #ifndef lint 139 static const char rcsid[] = 140 "$FreeBSD$"; 141 #endif 142 143 /* 144 * Various supported device vendors/types and their names. 145 */ 146 static struct dc_type dc_devs[] = { 147 { DC_VENDORID_DEC, DC_DEVICEID_21143, 148 "Intel 21143 10/100BaseTX" }, 149 { DC_VENDORID_DAVICOM, DC_DEVICEID_DM9100, 150 "Davicom DM9100 10/100BaseTX" }, 151 { DC_VENDORID_DAVICOM, DC_DEVICEID_DM9102, 152 "Davicom DM9102 10/100BaseTX" }, 153 { DC_VENDORID_DAVICOM, DC_DEVICEID_DM9102, 154 "Davicom DM9102A 10/100BaseTX" }, 155 { DC_VENDORID_ADMTEK, DC_DEVICEID_AL981, 156 "ADMtek AL981 10/100BaseTX" }, 157 { DC_VENDORID_ADMTEK, DC_DEVICEID_AN985, 158 "ADMtek AN985 10/100BaseTX" }, 159 { DC_VENDORID_ASIX, DC_DEVICEID_AX88140A, 160 "ASIX AX88140A 10/100BaseTX" }, 161 { DC_VENDORID_ASIX, DC_DEVICEID_AX88140A, 162 "ASIX AX88141 10/100BaseTX" }, 163 { DC_VENDORID_MX, DC_DEVICEID_98713, 164 "Macronix 98713 10/100BaseTX" }, 165 { DC_VENDORID_MX, DC_DEVICEID_98713, 166 "Macronix 98713A 10/100BaseTX" }, 167 { DC_VENDORID_CP, DC_DEVICEID_98713_CP, 168 "Compex RL100-TX 10/100BaseTX" }, 169 { DC_VENDORID_CP, DC_DEVICEID_98713_CP, 170 "Compex RL100-TX 10/100BaseTX" }, 171 { DC_VENDORID_MX, DC_DEVICEID_987x5, 172 "Macronix 98715/98715A 10/100BaseTX" }, 173 { DC_VENDORID_MX, DC_DEVICEID_987x5, 174 "Macronix 98715AEC-C 10/100BaseTX" }, 175 { DC_VENDORID_MX, DC_DEVICEID_987x5, 176 "Macronix 98725 10/100BaseTX" }, 177 { DC_VENDORID_MX, DC_DEVICEID_98727, 178 "Macronix 98727/98732 10/100BaseTX" }, 179 { DC_VENDORID_LO, DC_DEVICEID_82C115, 180 "LC82C115 PNIC II 10/100BaseTX" }, 181 { DC_VENDORID_LO, DC_DEVICEID_82C168, 182 "82c168 PNIC 10/100BaseTX" }, 183 { DC_VENDORID_LO, DC_DEVICEID_82C168, 184 "82c169 PNIC 10/100BaseTX" }, 185 { DC_VENDORID_ACCTON, DC_DEVICEID_EN1217, 186 "Accton EN1217 10/100BaseTX" }, 187 { DC_VENDORID_ACCTON, DC_DEVICEID_EN2242, 188 "Accton EN2242 MiniPCI 10/100BaseTX" }, 189 { DC_VENDORID_XIRCOM, DC_DEVICEID_X3201, 190 "Xircom X3201 10/100BaseTX" }, 191 { DC_VENDORID_ABOCOM, DC_DEVICEID_FE2500, 192 "Abocom FE2500 10/100BaseTX" }, 193 { DC_VENDORID_CONEXANT, DC_DEVICEID_RS7112, 194 "Conexant LANfinity MiniPCI 10/100BaseTX" }, 195 { 0, 0, NULL } 196 }; 197 198 static int dc_probe (device_t); 199 static int dc_attach (device_t); 200 static int dc_detach (device_t); 201 static int dc_suspend (device_t); 202 static int dc_resume (device_t); 203 static void dc_acpi (device_t); 204 static struct dc_type *dc_devtype (device_t); 205 static int dc_newbuf (struct dc_softc *, int, struct mbuf *); 206 static int dc_encap (struct dc_softc *, struct mbuf *, u_int32_t *); 207 static int dc_coal (struct dc_softc *, struct mbuf **); 208 static void dc_pnic_rx_bug_war (struct dc_softc *, int); 209 static int dc_rx_resync (struct dc_softc *); 210 static void dc_rxeof (struct dc_softc *); 211 static void dc_txeof (struct dc_softc *); 212 static void dc_tick (void *); 213 static void dc_tx_underrun (struct dc_softc *); 214 static void dc_intr (void *); 215 static void dc_start (struct ifnet *); 216 static int dc_ioctl (struct ifnet *, u_long, caddr_t); 217 static void dc_init (void *); 218 static void dc_stop (struct dc_softc *); 219 static void dc_watchdog (struct ifnet *); 220 static void dc_shutdown (device_t); 221 static int dc_ifmedia_upd (struct ifnet *); 222 static void dc_ifmedia_sts (struct ifnet *, struct ifmediareq *); 223 224 static void dc_delay (struct dc_softc *); 225 static void dc_eeprom_idle (struct dc_softc *); 226 static void dc_eeprom_putbyte (struct dc_softc *, int); 227 static void dc_eeprom_getword (struct dc_softc *, int, u_int16_t *); 228 static void dc_eeprom_getword_pnic 229 (struct dc_softc *, int, u_int16_t *); 230 static void dc_eeprom_getword_xircom 231 (struct dc_softc *, int, u_int16_t *); 232 static void dc_read_eeprom (struct dc_softc *, caddr_t, int, int, int); 233 234 static void dc_mii_writebit (struct dc_softc *, int); 235 static int dc_mii_readbit (struct dc_softc *); 236 static void dc_mii_sync (struct dc_softc *); 237 static void dc_mii_send (struct dc_softc *, u_int32_t, int); 238 static int dc_mii_readreg (struct dc_softc *, struct dc_mii_frame *); 239 static int dc_mii_writereg (struct dc_softc *, struct dc_mii_frame *); 240 static int dc_miibus_readreg (device_t, int, int); 241 static int dc_miibus_writereg (device_t, int, int, int); 242 static void dc_miibus_statchg (device_t); 243 static void dc_miibus_mediainit (device_t); 244 245 static void dc_setcfg (struct dc_softc *, int); 246 static u_int32_t dc_crc_le (struct dc_softc *, caddr_t); 247 static u_int32_t dc_crc_be (caddr_t); 248 static void dc_setfilt_21143 (struct dc_softc *); 249 static void dc_setfilt_asix (struct dc_softc *); 250 static void dc_setfilt_admtek (struct dc_softc *); 251 static void dc_setfilt_xircom (struct dc_softc *); 252 253 static void dc_setfilt (struct dc_softc *); 254 255 static void dc_reset (struct dc_softc *); 256 static int dc_list_rx_init (struct dc_softc *); 257 static int dc_list_tx_init (struct dc_softc *); 258 259 static void dc_parse_21143_srom (struct dc_softc *); 260 static void dc_decode_leaf_sia (struct dc_softc *, struct dc_eblock_sia *); 261 static void dc_decode_leaf_mii (struct dc_softc *, struct dc_eblock_mii *); 262 static void dc_decode_leaf_sym (struct dc_softc *, struct dc_eblock_sym *); 263 static void dc_apply_fixup (struct dc_softc *, int); 264 265 #ifdef DC_USEIOSPACE 266 #define DC_RES SYS_RES_IOPORT 267 #define DC_RID DC_PCI_CFBIO 268 #else 269 #define DC_RES SYS_RES_MEMORY 270 #define DC_RID DC_PCI_CFBMA 271 #endif 272 273 static device_method_t dc_methods[] = { 274 /* Device interface */ 275 DEVMETHOD(device_probe, dc_probe), 276 DEVMETHOD(device_attach, dc_attach), 277 DEVMETHOD(device_detach, dc_detach), 278 DEVMETHOD(device_suspend, dc_suspend), 279 DEVMETHOD(device_resume, dc_resume), 280 DEVMETHOD(device_shutdown, dc_shutdown), 281 282 /* bus interface */ 283 DEVMETHOD(bus_print_child, bus_generic_print_child), 284 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 285 286 /* MII interface */ 287 DEVMETHOD(miibus_readreg, dc_miibus_readreg), 288 DEVMETHOD(miibus_writereg, dc_miibus_writereg), 289 DEVMETHOD(miibus_statchg, dc_miibus_statchg), 290 DEVMETHOD(miibus_mediainit, dc_miibus_mediainit), 291 292 { 0, 0 } 293 }; 294 295 static driver_t dc_driver = { 296 "dc", 297 dc_methods, 298 sizeof(struct dc_softc) 299 }; 300 301 static devclass_t dc_devclass; 302 #ifdef __i386__ 303 static int dc_quick=1; 304 SYSCTL_INT(_hw, OID_AUTO, dc_quick, CTLFLAG_RW, 305 &dc_quick,0,"do not mdevget in dc driver"); 306 #endif 307 308 DRIVER_MODULE(if_dc, cardbus, dc_driver, dc_devclass, 0, 0); 309 DRIVER_MODULE(if_dc, pci, dc_driver, dc_devclass, 0, 0); 310 DRIVER_MODULE(miibus, dc, miibus_driver, miibus_devclass, 0, 0); 311 312 #define DC_SETBIT(sc, reg, x) \ 313 CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) | (x)) 314 315 #define DC_CLRBIT(sc, reg, x) \ 316 CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) & ~(x)) 317 318 #define SIO_SET(x) DC_SETBIT(sc, DC_SIO, (x)) 319 #define SIO_CLR(x) DC_CLRBIT(sc, DC_SIO, (x)) 320 321 #define IS_MPSAFE 0 322 323 static void dc_delay(sc) 324 struct dc_softc *sc; 325 { 326 int idx; 327 328 for (idx = (300 / 33) + 1; idx > 0; idx--) 329 CSR_READ_4(sc, DC_BUSCTL); 330 } 331 332 static void dc_eeprom_idle(sc) 333 struct dc_softc *sc; 334 { 335 register int i; 336 337 CSR_WRITE_4(sc, DC_SIO, DC_SIO_EESEL); 338 dc_delay(sc); 339 DC_SETBIT(sc, DC_SIO, DC_SIO_ROMCTL_READ); 340 dc_delay(sc); 341 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); 342 dc_delay(sc); 343 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CS); 344 dc_delay(sc); 345 346 for (i = 0; i < 25; i++) { 347 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); 348 dc_delay(sc); 349 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CLK); 350 dc_delay(sc); 351 } 352 353 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); 354 dc_delay(sc); 355 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CS); 356 dc_delay(sc); 357 CSR_WRITE_4(sc, DC_SIO, 0x00000000); 358 359 return; 360 } 361 362 /* 363 * Send a read command and address to the EEPROM, check for ACK. 364 */ 365 static void dc_eeprom_putbyte(sc, addr) 366 struct dc_softc *sc; 367 int addr; 368 { 369 register int d, i; 370 371 /* 372 * The AN985 has a 93C66 EEPROM on it instead of 373 * a 93C46. It uses a different bit sequence for 374 * specifying the "read" opcode. 375 */ 376 if (DC_IS_CENTAUR(sc) || DC_IS_CONEXANT(sc)) 377 d = addr | (DC_EECMD_READ << 2); 378 else 379 d = addr | DC_EECMD_READ; 380 381 /* 382 * Feed in each bit and strobe the clock. 383 */ 384 for (i = 0x400; i; i >>= 1) { 385 if (d & i) { 386 SIO_SET(DC_SIO_EE_DATAIN); 387 } else { 388 SIO_CLR(DC_SIO_EE_DATAIN); 389 } 390 dc_delay(sc); 391 SIO_SET(DC_SIO_EE_CLK); 392 dc_delay(sc); 393 SIO_CLR(DC_SIO_EE_CLK); 394 dc_delay(sc); 395 } 396 397 return; 398 } 399 400 /* 401 * Read a word of data stored in the EEPROM at address 'addr.' 402 * The PNIC 82c168/82c169 has its own non-standard way to read 403 * the EEPROM. 404 */ 405 static void dc_eeprom_getword_pnic(sc, addr, dest) 406 struct dc_softc *sc; 407 int addr; 408 u_int16_t *dest; 409 { 410 register int i; 411 u_int32_t r; 412 413 CSR_WRITE_4(sc, DC_PN_SIOCTL, DC_PN_EEOPCODE_READ|addr); 414 415 for (i = 0; i < DC_TIMEOUT; i++) { 416 DELAY(1); 417 r = CSR_READ_4(sc, DC_SIO); 418 if (!(r & DC_PN_SIOCTL_BUSY)) { 419 *dest = (u_int16_t)(r & 0xFFFF); 420 return; 421 } 422 } 423 424 return; 425 } 426 427 /* 428 * Read a word of data stored in the EEPROM at address 'addr.' 429 * The Xircom X3201 has its own non-standard way to read 430 * the EEPROM, too. 431 */ 432 static void dc_eeprom_getword_xircom(sc, addr, dest) 433 struct dc_softc *sc; 434 int addr; 435 u_int16_t *dest; 436 { 437 SIO_SET(DC_SIO_ROMSEL | DC_SIO_ROMCTL_READ); 438 439 addr *= 2; 440 CSR_WRITE_4(sc, DC_ROM, addr | 0x160); 441 *dest = (u_int16_t)CSR_READ_4(sc, DC_SIO)&0xff; 442 addr += 1; 443 CSR_WRITE_4(sc, DC_ROM, addr | 0x160); 444 *dest |= ((u_int16_t)CSR_READ_4(sc, DC_SIO)&0xff) << 8; 445 446 SIO_CLR(DC_SIO_ROMSEL | DC_SIO_ROMCTL_READ); 447 return; 448 } 449 450 /* 451 * Read a word of data stored in the EEPROM at address 'addr.' 452 */ 453 static void dc_eeprom_getword(sc, addr, dest) 454 struct dc_softc *sc; 455 int addr; 456 u_int16_t *dest; 457 { 458 register int i; 459 u_int16_t word = 0; 460 461 /* Force EEPROM to idle state. */ 462 dc_eeprom_idle(sc); 463 464 /* Enter EEPROM access mode. */ 465 CSR_WRITE_4(sc, DC_SIO, DC_SIO_EESEL); 466 dc_delay(sc); 467 DC_SETBIT(sc, DC_SIO, DC_SIO_ROMCTL_READ); 468 dc_delay(sc); 469 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); 470 dc_delay(sc); 471 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CS); 472 dc_delay(sc); 473 474 /* 475 * Send address of word we want to read. 476 */ 477 dc_eeprom_putbyte(sc, addr); 478 479 /* 480 * Start reading bits from EEPROM. 481 */ 482 for (i = 0x8000; i; i >>= 1) { 483 SIO_SET(DC_SIO_EE_CLK); 484 dc_delay(sc); 485 if (CSR_READ_4(sc, DC_SIO) & DC_SIO_EE_DATAOUT) 486 word |= i; 487 dc_delay(sc); 488 SIO_CLR(DC_SIO_EE_CLK); 489 dc_delay(sc); 490 } 491 492 /* Turn off EEPROM access mode. */ 493 dc_eeprom_idle(sc); 494 495 *dest = word; 496 497 return; 498 } 499 500 /* 501 * Read a sequence of words from the EEPROM. 502 */ 503 static void dc_read_eeprom(sc, dest, off, cnt, swap) 504 struct dc_softc *sc; 505 caddr_t dest; 506 int off; 507 int cnt; 508 int swap; 509 { 510 int i; 511 u_int16_t word = 0, *ptr; 512 513 for (i = 0; i < cnt; i++) { 514 if (DC_IS_PNIC(sc)) 515 dc_eeprom_getword_pnic(sc, off + i, &word); 516 else if (DC_IS_XIRCOM(sc)) 517 dc_eeprom_getword_xircom(sc, off + i, &word); 518 else 519 dc_eeprom_getword(sc, off + i, &word); 520 ptr = (u_int16_t *)(dest + (i * 2)); 521 if (swap) 522 *ptr = ntohs(word); 523 else 524 *ptr = word; 525 } 526 527 return; 528 } 529 530 /* 531 * The following two routines are taken from the Macronix 98713 532 * Application Notes pp.19-21. 533 */ 534 /* 535 * Write a bit to the MII bus. 536 */ 537 static void dc_mii_writebit(sc, bit) 538 struct dc_softc *sc; 539 int bit; 540 { 541 if (bit) 542 CSR_WRITE_4(sc, DC_SIO, 543 DC_SIO_ROMCTL_WRITE|DC_SIO_MII_DATAOUT); 544 else 545 CSR_WRITE_4(sc, DC_SIO, DC_SIO_ROMCTL_WRITE); 546 547 DC_SETBIT(sc, DC_SIO, DC_SIO_MII_CLK); 548 DC_CLRBIT(sc, DC_SIO, DC_SIO_MII_CLK); 549 550 return; 551 } 552 553 /* 554 * Read a bit from the MII bus. 555 */ 556 static int dc_mii_readbit(sc) 557 struct dc_softc *sc; 558 { 559 CSR_WRITE_4(sc, DC_SIO, DC_SIO_ROMCTL_READ|DC_SIO_MII_DIR); 560 CSR_READ_4(sc, DC_SIO); 561 DC_SETBIT(sc, DC_SIO, DC_SIO_MII_CLK); 562 DC_CLRBIT(sc, DC_SIO, DC_SIO_MII_CLK); 563 if (CSR_READ_4(sc, DC_SIO) & DC_SIO_MII_DATAIN) 564 return(1); 565 566 return(0); 567 } 568 569 /* 570 * Sync the PHYs by setting data bit and strobing the clock 32 times. 571 */ 572 static void dc_mii_sync(sc) 573 struct dc_softc *sc; 574 { 575 register int i; 576 577 CSR_WRITE_4(sc, DC_SIO, DC_SIO_ROMCTL_WRITE); 578 579 for (i = 0; i < 32; i++) 580 dc_mii_writebit(sc, 1); 581 582 return; 583 } 584 585 /* 586 * Clock a series of bits through the MII. 587 */ 588 static void dc_mii_send(sc, bits, cnt) 589 struct dc_softc *sc; 590 u_int32_t bits; 591 int cnt; 592 { 593 int i; 594 595 for (i = (0x1 << (cnt - 1)); i; i >>= 1) 596 dc_mii_writebit(sc, bits & i); 597 } 598 599 /* 600 * Read an PHY register through the MII. 601 */ 602 static int dc_mii_readreg(sc, frame) 603 struct dc_softc *sc; 604 struct dc_mii_frame *frame; 605 606 { 607 int i, ack; 608 609 DC_LOCK(sc); 610 611 /* 612 * Set up frame for RX. 613 */ 614 frame->mii_stdelim = DC_MII_STARTDELIM; 615 frame->mii_opcode = DC_MII_READOP; 616 frame->mii_turnaround = 0; 617 frame->mii_data = 0; 618 619 /* 620 * Sync the PHYs. 621 */ 622 dc_mii_sync(sc); 623 624 /* 625 * Send command/address info. 626 */ 627 dc_mii_send(sc, frame->mii_stdelim, 2); 628 dc_mii_send(sc, frame->mii_opcode, 2); 629 dc_mii_send(sc, frame->mii_phyaddr, 5); 630 dc_mii_send(sc, frame->mii_regaddr, 5); 631 632 #ifdef notdef 633 /* Idle bit */ 634 dc_mii_writebit(sc, 1); 635 dc_mii_writebit(sc, 0); 636 #endif 637 638 /* Check for ack */ 639 ack = dc_mii_readbit(sc); 640 641 /* 642 * Now try reading data bits. If the ack failed, we still 643 * need to clock through 16 cycles to keep the PHY(s) in sync. 644 */ 645 if (ack) { 646 for(i = 0; i < 16; i++) { 647 dc_mii_readbit(sc); 648 } 649 goto fail; 650 } 651 652 for (i = 0x8000; i; i >>= 1) { 653 if (!ack) { 654 if (dc_mii_readbit(sc)) 655 frame->mii_data |= i; 656 } 657 } 658 659 fail: 660 661 dc_mii_writebit(sc, 0); 662 dc_mii_writebit(sc, 0); 663 664 DC_UNLOCK(sc); 665 666 if (ack) 667 return(1); 668 return(0); 669 } 670 671 /* 672 * Write to a PHY register through the MII. 673 */ 674 static int dc_mii_writereg(sc, frame) 675 struct dc_softc *sc; 676 struct dc_mii_frame *frame; 677 678 { 679 DC_LOCK(sc); 680 /* 681 * Set up frame for TX. 682 */ 683 684 frame->mii_stdelim = DC_MII_STARTDELIM; 685 frame->mii_opcode = DC_MII_WRITEOP; 686 frame->mii_turnaround = DC_MII_TURNAROUND; 687 688 /* 689 * Sync the PHYs. 690 */ 691 dc_mii_sync(sc); 692 693 dc_mii_send(sc, frame->mii_stdelim, 2); 694 dc_mii_send(sc, frame->mii_opcode, 2); 695 dc_mii_send(sc, frame->mii_phyaddr, 5); 696 dc_mii_send(sc, frame->mii_regaddr, 5); 697 dc_mii_send(sc, frame->mii_turnaround, 2); 698 dc_mii_send(sc, frame->mii_data, 16); 699 700 /* Idle bit. */ 701 dc_mii_writebit(sc, 0); 702 dc_mii_writebit(sc, 0); 703 704 DC_UNLOCK(sc); 705 706 return(0); 707 } 708 709 static int dc_miibus_readreg(dev, phy, reg) 710 device_t dev; 711 int phy, reg; 712 { 713 struct dc_mii_frame frame; 714 struct dc_softc *sc; 715 int i, rval, phy_reg = 0; 716 717 sc = device_get_softc(dev); 718 bzero((char *)&frame, sizeof(frame)); 719 720 /* 721 * Note: both the AL981 and AN985 have internal PHYs, 722 * however the AL981 provides direct access to the PHY 723 * registers while the AN985 uses a serial MII interface. 724 * The AN985's MII interface is also buggy in that you 725 * can read from any MII address (0 to 31), but only address 1 726 * behaves normally. To deal with both cases, we pretend 727 * that the PHY is at MII address 1. 728 */ 729 if (DC_IS_ADMTEK(sc) && phy != DC_ADMTEK_PHYADDR) 730 return(0); 731 732 /* 733 * Note: the ukphy probes of the RS7112 report a PHY at 734 * MII address 0 (possibly HomePNA?) and 1 (ethernet) 735 * so we only respond to correct one. 736 */ 737 if (DC_IS_CONEXANT(sc) && phy != DC_CONEXANT_PHYADDR) 738 return(0); 739 740 if (sc->dc_pmode != DC_PMODE_MII) { 741 if (phy == (MII_NPHY - 1)) { 742 switch(reg) { 743 case MII_BMSR: 744 /* 745 * Fake something to make the probe 746 * code think there's a PHY here. 747 */ 748 return(BMSR_MEDIAMASK); 749 break; 750 case MII_PHYIDR1: 751 if (DC_IS_PNIC(sc)) 752 return(DC_VENDORID_LO); 753 return(DC_VENDORID_DEC); 754 break; 755 case MII_PHYIDR2: 756 if (DC_IS_PNIC(sc)) 757 return(DC_DEVICEID_82C168); 758 return(DC_DEVICEID_21143); 759 break; 760 default: 761 return(0); 762 break; 763 } 764 } else 765 return(0); 766 } 767 768 if (DC_IS_PNIC(sc)) { 769 CSR_WRITE_4(sc, DC_PN_MII, DC_PN_MIIOPCODE_READ | 770 (phy << 23) | (reg << 18)); 771 for (i = 0; i < DC_TIMEOUT; i++) { 772 DELAY(1); 773 rval = CSR_READ_4(sc, DC_PN_MII); 774 if (!(rval & DC_PN_MII_BUSY)) { 775 rval &= 0xFFFF; 776 return(rval == 0xFFFF ? 0 : rval); 777 } 778 } 779 return(0); 780 } 781 782 if (DC_IS_COMET(sc)) { 783 switch(reg) { 784 case MII_BMCR: 785 phy_reg = DC_AL_BMCR; 786 break; 787 case MII_BMSR: 788 phy_reg = DC_AL_BMSR; 789 break; 790 case MII_PHYIDR1: 791 phy_reg = DC_AL_VENID; 792 break; 793 case MII_PHYIDR2: 794 phy_reg = DC_AL_DEVID; 795 break; 796 case MII_ANAR: 797 phy_reg = DC_AL_ANAR; 798 break; 799 case MII_ANLPAR: 800 phy_reg = DC_AL_LPAR; 801 break; 802 case MII_ANER: 803 phy_reg = DC_AL_ANER; 804 break; 805 default: 806 printf("dc%d: phy_read: bad phy register %x\n", 807 sc->dc_unit, reg); 808 return(0); 809 break; 810 } 811 812 rval = CSR_READ_4(sc, phy_reg) & 0x0000FFFF; 813 814 if (rval == 0xFFFF) 815 return(0); 816 return(rval); 817 } 818 819 frame.mii_phyaddr = phy; 820 frame.mii_regaddr = reg; 821 if (sc->dc_type == DC_TYPE_98713) { 822 phy_reg = CSR_READ_4(sc, DC_NETCFG); 823 CSR_WRITE_4(sc, DC_NETCFG, phy_reg & ~DC_NETCFG_PORTSEL); 824 } 825 dc_mii_readreg(sc, &frame); 826 if (sc->dc_type == DC_TYPE_98713) 827 CSR_WRITE_4(sc, DC_NETCFG, phy_reg); 828 829 return(frame.mii_data); 830 } 831 832 static int dc_miibus_writereg(dev, phy, reg, data) 833 device_t dev; 834 int phy, reg, data; 835 { 836 struct dc_softc *sc; 837 struct dc_mii_frame frame; 838 int i, phy_reg = 0; 839 840 sc = device_get_softc(dev); 841 bzero((char *)&frame, sizeof(frame)); 842 843 if (DC_IS_ADMTEK(sc) && phy != DC_ADMTEK_PHYADDR) 844 return(0); 845 846 if (DC_IS_CONEXANT(sc) && phy != DC_CONEXANT_PHYADDR) 847 return(0); 848 849 if (DC_IS_PNIC(sc)) { 850 CSR_WRITE_4(sc, DC_PN_MII, DC_PN_MIIOPCODE_WRITE | 851 (phy << 23) | (reg << 10) | data); 852 for (i = 0; i < DC_TIMEOUT; i++) { 853 if (!(CSR_READ_4(sc, DC_PN_MII) & DC_PN_MII_BUSY)) 854 break; 855 } 856 return(0); 857 } 858 859 if (DC_IS_COMET(sc)) { 860 switch(reg) { 861 case MII_BMCR: 862 phy_reg = DC_AL_BMCR; 863 break; 864 case MII_BMSR: 865 phy_reg = DC_AL_BMSR; 866 break; 867 case MII_PHYIDR1: 868 phy_reg = DC_AL_VENID; 869 break; 870 case MII_PHYIDR2: 871 phy_reg = DC_AL_DEVID; 872 break; 873 case MII_ANAR: 874 phy_reg = DC_AL_ANAR; 875 break; 876 case MII_ANLPAR: 877 phy_reg = DC_AL_LPAR; 878 break; 879 case MII_ANER: 880 phy_reg = DC_AL_ANER; 881 break; 882 default: 883 printf("dc%d: phy_write: bad phy register %x\n", 884 sc->dc_unit, reg); 885 return(0); 886 break; 887 } 888 889 CSR_WRITE_4(sc, phy_reg, data); 890 return(0); 891 } 892 893 frame.mii_phyaddr = phy; 894 frame.mii_regaddr = reg; 895 frame.mii_data = data; 896 897 if (sc->dc_type == DC_TYPE_98713) { 898 phy_reg = CSR_READ_4(sc, DC_NETCFG); 899 CSR_WRITE_4(sc, DC_NETCFG, phy_reg & ~DC_NETCFG_PORTSEL); 900 } 901 dc_mii_writereg(sc, &frame); 902 if (sc->dc_type == DC_TYPE_98713) 903 CSR_WRITE_4(sc, DC_NETCFG, phy_reg); 904 905 return(0); 906 } 907 908 static void dc_miibus_statchg(dev) 909 device_t dev; 910 { 911 struct dc_softc *sc; 912 struct mii_data *mii; 913 struct ifmedia *ifm; 914 915 sc = device_get_softc(dev); 916 if (DC_IS_ADMTEK(sc)) 917 return; 918 919 mii = device_get_softc(sc->dc_miibus); 920 ifm = &mii->mii_media; 921 if (DC_IS_DAVICOM(sc) && 922 IFM_SUBTYPE(ifm->ifm_media) == IFM_HPNA_1) { 923 dc_setcfg(sc, ifm->ifm_media); 924 sc->dc_if_media = ifm->ifm_media; 925 } else { 926 dc_setcfg(sc, mii->mii_media_active); 927 sc->dc_if_media = mii->mii_media_active; 928 } 929 930 return; 931 } 932 933 /* 934 * Special support for DM9102A cards with HomePNA PHYs. Note: 935 * with the Davicom DM9102A/DM9801 eval board that I have, it seems 936 * to be impossible to talk to the management interface of the DM9801 937 * PHY (its MDIO pin is not connected to anything). Consequently, 938 * the driver has to just 'know' about the additional mode and deal 939 * with it itself. *sigh* 940 */ 941 static void dc_miibus_mediainit(dev) 942 device_t dev; 943 { 944 struct dc_softc *sc; 945 struct mii_data *mii; 946 struct ifmedia *ifm; 947 int rev; 948 949 rev = pci_read_config(dev, DC_PCI_CFRV, 4) & 0xFF; 950 951 sc = device_get_softc(dev); 952 mii = device_get_softc(sc->dc_miibus); 953 ifm = &mii->mii_media; 954 955 if (DC_IS_DAVICOM(sc) && rev >= DC_REVISION_DM9102A) 956 ifmedia_add(ifm, IFM_ETHER|IFM_HPNA_1, 0, NULL); 957 958 return; 959 } 960 961 #define DC_POLY 0xEDB88320 962 #define DC_BITS_512 9 963 #define DC_BITS_128 7 964 #define DC_BITS_64 6 965 966 static u_int32_t dc_crc_le(sc, addr) 967 struct dc_softc *sc; 968 caddr_t addr; 969 { 970 u_int32_t idx, bit, data, crc; 971 972 /* Compute CRC for the address value. */ 973 crc = 0xFFFFFFFF; /* initial value */ 974 975 for (idx = 0; idx < 6; idx++) { 976 for (data = *addr++, bit = 0; bit < 8; bit++, data >>= 1) 977 crc = (crc >> 1) ^ (((crc ^ data) & 1) ? DC_POLY : 0); 978 } 979 980 /* 981 * The hash table on the PNIC II and the MX98715AEC-C/D/E 982 * chips is only 128 bits wide. 983 */ 984 if (sc->dc_flags & DC_128BIT_HASH) 985 return (crc & ((1 << DC_BITS_128) - 1)); 986 987 /* The hash table on the MX98715BEC is only 64 bits wide. */ 988 if (sc->dc_flags & DC_64BIT_HASH) 989 return (crc & ((1 << DC_BITS_64) - 1)); 990 991 /* Xircom's hash filtering table is different (read: weird) */ 992 /* Xircom uses the LEAST significant bits */ 993 if (DC_IS_XIRCOM(sc)) { 994 if ((crc & 0x180) == 0x180) 995 return (crc & 0x0F) + (crc & 0x70)*3 + (14 << 4); 996 else 997 return (crc & 0x1F) + ((crc>>1) & 0xF0)*3 + (12 << 4); 998 } 999 1000 return (crc & ((1 << DC_BITS_512) - 1)); 1001 } 1002 1003 /* 1004 * Calculate CRC of a multicast group address, return the lower 6 bits. 1005 */ 1006 static u_int32_t dc_crc_be(addr) 1007 caddr_t addr; 1008 { 1009 u_int32_t crc, carry; 1010 int i, j; 1011 u_int8_t c; 1012 1013 /* Compute CRC for the address value. */ 1014 crc = 0xFFFFFFFF; /* initial value */ 1015 1016 for (i = 0; i < 6; i++) { 1017 c = *(addr + i); 1018 for (j = 0; j < 8; j++) { 1019 carry = ((crc & 0x80000000) ? 1 : 0) ^ (c & 0x01); 1020 crc <<= 1; 1021 c >>= 1; 1022 if (carry) 1023 crc = (crc ^ 0x04c11db6) | carry; 1024 } 1025 } 1026 1027 /* return the filter bit position */ 1028 return((crc >> 26) & 0x0000003F); 1029 } 1030 1031 /* 1032 * 21143-style RX filter setup routine. Filter programming is done by 1033 * downloading a special setup frame into the TX engine. 21143, Macronix, 1034 * PNIC, PNIC II and Davicom chips are programmed this way. 1035 * 1036 * We always program the chip using 'hash perfect' mode, i.e. one perfect 1037 * address (our node address) and a 512-bit hash filter for multicast 1038 * frames. We also sneak the broadcast address into the hash filter since 1039 * we need that too. 1040 */ 1041 void dc_setfilt_21143(sc) 1042 struct dc_softc *sc; 1043 { 1044 struct dc_desc *sframe; 1045 u_int32_t h, *sp; 1046 struct ifmultiaddr *ifma; 1047 struct ifnet *ifp; 1048 int i; 1049 1050 ifp = &sc->arpcom.ac_if; 1051 1052 i = sc->dc_cdata.dc_tx_prod; 1053 DC_INC(sc->dc_cdata.dc_tx_prod, DC_TX_LIST_CNT); 1054 sc->dc_cdata.dc_tx_cnt++; 1055 sframe = &sc->dc_ldata->dc_tx_list[i]; 1056 sp = (u_int32_t *)&sc->dc_cdata.dc_sbuf; 1057 bzero((char *)sp, DC_SFRAME_LEN); 1058 1059 sframe->dc_data = vtophys(&sc->dc_cdata.dc_sbuf); 1060 sframe->dc_ctl = DC_SFRAME_LEN | DC_TXCTL_SETUP | DC_TXCTL_TLINK | 1061 DC_FILTER_HASHPERF | DC_TXCTL_FINT; 1062 1063 sc->dc_cdata.dc_tx_chain[i] = (struct mbuf *)&sc->dc_cdata.dc_sbuf; 1064 1065 /* If we want promiscuous mode, set the allframes bit. */ 1066 if (ifp->if_flags & IFF_PROMISC) 1067 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC); 1068 else 1069 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC); 1070 1071 if (ifp->if_flags & IFF_ALLMULTI) 1072 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI); 1073 else 1074 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI); 1075 1076 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 1077 if (ifma->ifma_addr->sa_family != AF_LINK) 1078 continue; 1079 h = dc_crc_le(sc, 1080 LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 1081 sp[h >> 4] |= 1 << (h & 0xF); 1082 } 1083 1084 if (ifp->if_flags & IFF_BROADCAST) { 1085 h = dc_crc_le(sc, (caddr_t)ðerbroadcastaddr); 1086 sp[h >> 4] |= 1 << (h & 0xF); 1087 } 1088 1089 /* Set our MAC address */ 1090 sp[39] = ((u_int16_t *)sc->arpcom.ac_enaddr)[0]; 1091 sp[40] = ((u_int16_t *)sc->arpcom.ac_enaddr)[1]; 1092 sp[41] = ((u_int16_t *)sc->arpcom.ac_enaddr)[2]; 1093 1094 sframe->dc_status = DC_TXSTAT_OWN; 1095 CSR_WRITE_4(sc, DC_TXSTART, 0xFFFFFFFF); 1096 1097 /* 1098 * The PNIC takes an exceedingly long time to process its 1099 * setup frame; wait 10ms after posting the setup frame 1100 * before proceeding, just so it has time to swallow its 1101 * medicine. 1102 */ 1103 DELAY(10000); 1104 1105 ifp->if_timer = 5; 1106 1107 return; 1108 } 1109 1110 void dc_setfilt_admtek(sc) 1111 struct dc_softc *sc; 1112 { 1113 struct ifnet *ifp; 1114 int h = 0; 1115 u_int32_t hashes[2] = { 0, 0 }; 1116 struct ifmultiaddr *ifma; 1117 1118 ifp = &sc->arpcom.ac_if; 1119 1120 /* Init our MAC address */ 1121 CSR_WRITE_4(sc, DC_AL_PAR0, *(u_int32_t *)(&sc->arpcom.ac_enaddr[0])); 1122 CSR_WRITE_4(sc, DC_AL_PAR1, *(u_int32_t *)(&sc->arpcom.ac_enaddr[4])); 1123 1124 /* If we want promiscuous mode, set the allframes bit. */ 1125 if (ifp->if_flags & IFF_PROMISC) 1126 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC); 1127 else 1128 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC); 1129 1130 if (ifp->if_flags & IFF_ALLMULTI) 1131 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI); 1132 else 1133 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI); 1134 1135 /* first, zot all the existing hash bits */ 1136 CSR_WRITE_4(sc, DC_AL_MAR0, 0); 1137 CSR_WRITE_4(sc, DC_AL_MAR1, 0); 1138 1139 /* 1140 * If we're already in promisc or allmulti mode, we 1141 * don't have to bother programming the multicast filter. 1142 */ 1143 if (ifp->if_flags & (IFF_PROMISC|IFF_ALLMULTI)) 1144 return; 1145 1146 /* now program new ones */ 1147 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 1148 if (ifma->ifma_addr->sa_family != AF_LINK) 1149 continue; 1150 h = dc_crc_be(LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 1151 if (h < 32) 1152 hashes[0] |= (1 << h); 1153 else 1154 hashes[1] |= (1 << (h - 32)); 1155 } 1156 1157 CSR_WRITE_4(sc, DC_AL_MAR0, hashes[0]); 1158 CSR_WRITE_4(sc, DC_AL_MAR1, hashes[1]); 1159 1160 return; 1161 } 1162 1163 void dc_setfilt_asix(sc) 1164 struct dc_softc *sc; 1165 { 1166 struct ifnet *ifp; 1167 int h = 0; 1168 u_int32_t hashes[2] = { 0, 0 }; 1169 struct ifmultiaddr *ifma; 1170 1171 ifp = &sc->arpcom.ac_if; 1172 1173 /* Init our MAC address */ 1174 CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_PAR0); 1175 CSR_WRITE_4(sc, DC_AX_FILTDATA, 1176 *(u_int32_t *)(&sc->arpcom.ac_enaddr[0])); 1177 CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_PAR1); 1178 CSR_WRITE_4(sc, DC_AX_FILTDATA, 1179 *(u_int32_t *)(&sc->arpcom.ac_enaddr[4])); 1180 1181 /* If we want promiscuous mode, set the allframes bit. */ 1182 if (ifp->if_flags & IFF_PROMISC) 1183 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC); 1184 else 1185 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC); 1186 1187 if (ifp->if_flags & IFF_ALLMULTI) 1188 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI); 1189 else 1190 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI); 1191 1192 /* 1193 * The ASIX chip has a special bit to enable reception 1194 * of broadcast frames. 1195 */ 1196 if (ifp->if_flags & IFF_BROADCAST) 1197 DC_SETBIT(sc, DC_NETCFG, DC_AX_NETCFG_RX_BROAD); 1198 else 1199 DC_CLRBIT(sc, DC_NETCFG, DC_AX_NETCFG_RX_BROAD); 1200 1201 /* first, zot all the existing hash bits */ 1202 CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_MAR0); 1203 CSR_WRITE_4(sc, DC_AX_FILTDATA, 0); 1204 CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_MAR1); 1205 CSR_WRITE_4(sc, DC_AX_FILTDATA, 0); 1206 1207 /* 1208 * If we're already in promisc or allmulti mode, we 1209 * don't have to bother programming the multicast filter. 1210 */ 1211 if (ifp->if_flags & (IFF_PROMISC|IFF_ALLMULTI)) 1212 return; 1213 1214 /* now program new ones */ 1215 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 1216 if (ifma->ifma_addr->sa_family != AF_LINK) 1217 continue; 1218 h = dc_crc_be(LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 1219 if (h < 32) 1220 hashes[0] |= (1 << h); 1221 else 1222 hashes[1] |= (1 << (h - 32)); 1223 } 1224 1225 CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_MAR0); 1226 CSR_WRITE_4(sc, DC_AX_FILTDATA, hashes[0]); 1227 CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_MAR1); 1228 CSR_WRITE_4(sc, DC_AX_FILTDATA, hashes[1]); 1229 1230 return; 1231 } 1232 1233 void dc_setfilt_xircom(sc) 1234 struct dc_softc *sc; 1235 { 1236 struct dc_desc *sframe; 1237 u_int32_t h, *sp; 1238 struct ifmultiaddr *ifma; 1239 struct ifnet *ifp; 1240 int i; 1241 1242 ifp = &sc->arpcom.ac_if; 1243 DC_CLRBIT(sc, DC_NETCFG, (DC_NETCFG_TX_ON|DC_NETCFG_RX_ON)); 1244 1245 i = sc->dc_cdata.dc_tx_prod; 1246 DC_INC(sc->dc_cdata.dc_tx_prod, DC_TX_LIST_CNT); 1247 sc->dc_cdata.dc_tx_cnt++; 1248 sframe = &sc->dc_ldata->dc_tx_list[i]; 1249 sp = (u_int32_t *)&sc->dc_cdata.dc_sbuf; 1250 bzero((char *)sp, DC_SFRAME_LEN); 1251 1252 sframe->dc_data = vtophys(&sc->dc_cdata.dc_sbuf); 1253 sframe->dc_ctl = DC_SFRAME_LEN | DC_TXCTL_SETUP | DC_TXCTL_TLINK | 1254 DC_FILTER_HASHPERF | DC_TXCTL_FINT; 1255 1256 sc->dc_cdata.dc_tx_chain[i] = (struct mbuf *)&sc->dc_cdata.dc_sbuf; 1257 1258 /* If we want promiscuous mode, set the allframes bit. */ 1259 if (ifp->if_flags & IFF_PROMISC) 1260 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC); 1261 else 1262 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC); 1263 1264 if (ifp->if_flags & IFF_ALLMULTI) 1265 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI); 1266 else 1267 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI); 1268 1269 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 1270 if (ifma->ifma_addr->sa_family != AF_LINK) 1271 continue; 1272 h = dc_crc_le(sc, 1273 LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 1274 sp[h >> 4] |= 1 << (h & 0xF); 1275 } 1276 1277 if (ifp->if_flags & IFF_BROADCAST) { 1278 h = dc_crc_le(sc, (caddr_t)ðerbroadcastaddr); 1279 sp[h >> 4] |= 1 << (h & 0xF); 1280 } 1281 1282 /* Set our MAC address */ 1283 sp[0] = ((u_int16_t *)sc->arpcom.ac_enaddr)[0]; 1284 sp[1] = ((u_int16_t *)sc->arpcom.ac_enaddr)[1]; 1285 sp[2] = ((u_int16_t *)sc->arpcom.ac_enaddr)[2]; 1286 1287 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_TX_ON); 1288 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_ON); 1289 ifp->if_flags |= IFF_RUNNING; 1290 sframe->dc_status = DC_TXSTAT_OWN; 1291 CSR_WRITE_4(sc, DC_TXSTART, 0xFFFFFFFF); 1292 1293 /* 1294 * wait some time... 1295 */ 1296 DELAY(1000); 1297 1298 ifp->if_timer = 5; 1299 1300 return; 1301 } 1302 1303 static void dc_setfilt(sc) 1304 struct dc_softc *sc; 1305 { 1306 if (DC_IS_INTEL(sc) || DC_IS_MACRONIX(sc) || DC_IS_PNIC(sc) || 1307 DC_IS_PNICII(sc) || DC_IS_DAVICOM(sc) || DC_IS_CONEXANT(sc)) 1308 dc_setfilt_21143(sc); 1309 1310 if (DC_IS_ASIX(sc)) 1311 dc_setfilt_asix(sc); 1312 1313 if (DC_IS_ADMTEK(sc)) 1314 dc_setfilt_admtek(sc); 1315 1316 if (DC_IS_XIRCOM(sc)) 1317 dc_setfilt_xircom(sc); 1318 1319 return; 1320 } 1321 1322 /* 1323 * In order to fiddle with the 1324 * 'full-duplex' and '100Mbps' bits in the netconfig register, we 1325 * first have to put the transmit and/or receive logic in the idle state. 1326 */ 1327 static void dc_setcfg(sc, media) 1328 struct dc_softc *sc; 1329 int media; 1330 { 1331 int i, restart = 0; 1332 u_int32_t isr; 1333 1334 if (IFM_SUBTYPE(media) == IFM_NONE) 1335 return; 1336 1337 if (CSR_READ_4(sc, DC_NETCFG) & (DC_NETCFG_TX_ON|DC_NETCFG_RX_ON)) { 1338 restart = 1; 1339 DC_CLRBIT(sc, DC_NETCFG, (DC_NETCFG_TX_ON|DC_NETCFG_RX_ON)); 1340 1341 for (i = 0; i < DC_TIMEOUT; i++) { 1342 isr = CSR_READ_4(sc, DC_ISR); 1343 if (isr & DC_ISR_TX_IDLE && 1344 (isr & DC_ISR_RX_STATE) == DC_RXSTATE_STOPPED) 1345 break; 1346 DELAY(10); 1347 } 1348 1349 if (i == DC_TIMEOUT) 1350 printf("dc%d: failed to force tx and " 1351 "rx to idle state\n", sc->dc_unit); 1352 } 1353 1354 if (IFM_SUBTYPE(media) == IFM_100_TX) { 1355 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_SPEEDSEL); 1356 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_HEARTBEAT); 1357 if (sc->dc_pmode == DC_PMODE_MII) { 1358 int watchdogreg; 1359 1360 if (DC_IS_INTEL(sc)) { 1361 /* there's a write enable bit here that reads as 1 */ 1362 watchdogreg = CSR_READ_4(sc, DC_WATCHDOG); 1363 watchdogreg &= ~DC_WDOG_CTLWREN; 1364 watchdogreg |= DC_WDOG_JABBERDIS; 1365 CSR_WRITE_4(sc, DC_WATCHDOG, watchdogreg); 1366 } else { 1367 DC_SETBIT(sc, DC_WATCHDOG, DC_WDOG_JABBERDIS); 1368 } 1369 DC_CLRBIT(sc, DC_NETCFG, (DC_NETCFG_PCS| 1370 DC_NETCFG_PORTSEL|DC_NETCFG_SCRAMBLER)); 1371 if (sc->dc_type == DC_TYPE_98713) 1372 DC_SETBIT(sc, DC_NETCFG, (DC_NETCFG_PCS| 1373 DC_NETCFG_SCRAMBLER)); 1374 if (!DC_IS_DAVICOM(sc)) 1375 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL); 1376 DC_CLRBIT(sc, DC_10BTCTRL, 0xFFFF); 1377 if (DC_IS_INTEL(sc)) 1378 dc_apply_fixup(sc, IFM_AUTO); 1379 } else { 1380 if (DC_IS_PNIC(sc)) { 1381 DC_PN_GPIO_SETBIT(sc, DC_PN_GPIO_SPEEDSEL); 1382 DC_PN_GPIO_SETBIT(sc, DC_PN_GPIO_100TX_LOOP); 1383 DC_SETBIT(sc, DC_PN_NWAY, DC_PN_NWAY_SPEEDSEL); 1384 } 1385 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL); 1386 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PCS); 1387 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_SCRAMBLER); 1388 if (DC_IS_INTEL(sc)) 1389 dc_apply_fixup(sc, 1390 (media & IFM_GMASK) == IFM_FDX ? 1391 IFM_100_TX|IFM_FDX : IFM_100_TX); 1392 } 1393 } 1394 1395 if (IFM_SUBTYPE(media) == IFM_10_T) { 1396 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_SPEEDSEL); 1397 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_HEARTBEAT); 1398 if (sc->dc_pmode == DC_PMODE_MII) { 1399 int watchdogreg; 1400 1401 /* there's a write enable bit here that reads as 1 */ 1402 if (DC_IS_INTEL(sc)) { 1403 watchdogreg = CSR_READ_4(sc, DC_WATCHDOG); 1404 watchdogreg &= ~DC_WDOG_CTLWREN; 1405 watchdogreg |= DC_WDOG_JABBERDIS; 1406 CSR_WRITE_4(sc, DC_WATCHDOG, watchdogreg); 1407 } else { 1408 DC_SETBIT(sc, DC_WATCHDOG, DC_WDOG_JABBERDIS); 1409 } 1410 DC_CLRBIT(sc, DC_NETCFG, (DC_NETCFG_PCS| 1411 DC_NETCFG_PORTSEL|DC_NETCFG_SCRAMBLER)); 1412 if (sc->dc_type == DC_TYPE_98713) 1413 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PCS); 1414 if (!DC_IS_DAVICOM(sc)) 1415 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL); 1416 DC_CLRBIT(sc, DC_10BTCTRL, 0xFFFF); 1417 if (DC_IS_INTEL(sc)) 1418 dc_apply_fixup(sc, IFM_AUTO); 1419 } else { 1420 if (DC_IS_PNIC(sc)) { 1421 DC_PN_GPIO_CLRBIT(sc, DC_PN_GPIO_SPEEDSEL); 1422 DC_PN_GPIO_SETBIT(sc, DC_PN_GPIO_100TX_LOOP); 1423 DC_CLRBIT(sc, DC_PN_NWAY, DC_PN_NWAY_SPEEDSEL); 1424 } 1425 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL); 1426 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_PCS); 1427 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_SCRAMBLER); 1428 if (DC_IS_INTEL(sc)) { 1429 DC_CLRBIT(sc, DC_SIARESET, DC_SIA_RESET); 1430 DC_CLRBIT(sc, DC_10BTCTRL, 0xFFFF); 1431 if ((media & IFM_GMASK) == IFM_FDX) 1432 DC_SETBIT(sc, DC_10BTCTRL, 0x7F3D); 1433 else 1434 DC_SETBIT(sc, DC_10BTCTRL, 0x7F3F); 1435 DC_SETBIT(sc, DC_SIARESET, DC_SIA_RESET); 1436 DC_CLRBIT(sc, DC_10BTCTRL, 1437 DC_TCTL_AUTONEGENBL); 1438 dc_apply_fixup(sc, 1439 (media & IFM_GMASK) == IFM_FDX ? 1440 IFM_10_T|IFM_FDX : IFM_10_T); 1441 DELAY(20000); 1442 } 1443 } 1444 } 1445 1446 /* 1447 * If this is a Davicom DM9102A card with a DM9801 HomePNA 1448 * PHY and we want HomePNA mode, set the portsel bit to turn 1449 * on the external MII port. 1450 */ 1451 if (DC_IS_DAVICOM(sc)) { 1452 if (IFM_SUBTYPE(media) == IFM_HPNA_1) { 1453 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL); 1454 sc->dc_link = 1; 1455 } else { 1456 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL); 1457 } 1458 } 1459 1460 if ((media & IFM_GMASK) == IFM_FDX) { 1461 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_FULLDUPLEX); 1462 if (sc->dc_pmode == DC_PMODE_SYM && DC_IS_PNIC(sc)) 1463 DC_SETBIT(sc, DC_PN_NWAY, DC_PN_NWAY_DUPLEX); 1464 } else { 1465 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_FULLDUPLEX); 1466 if (sc->dc_pmode == DC_PMODE_SYM && DC_IS_PNIC(sc)) 1467 DC_CLRBIT(sc, DC_PN_NWAY, DC_PN_NWAY_DUPLEX); 1468 } 1469 1470 if (restart) 1471 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_TX_ON|DC_NETCFG_RX_ON); 1472 1473 return; 1474 } 1475 1476 static void dc_reset(sc) 1477 struct dc_softc *sc; 1478 { 1479 register int i; 1480 1481 DC_SETBIT(sc, DC_BUSCTL, DC_BUSCTL_RESET); 1482 1483 for (i = 0; i < DC_TIMEOUT; i++) { 1484 DELAY(10); 1485 if (!(CSR_READ_4(sc, DC_BUSCTL) & DC_BUSCTL_RESET)) 1486 break; 1487 } 1488 1489 if (DC_IS_ASIX(sc) || DC_IS_ADMTEK(sc) || DC_IS_CONEXANT(sc) || 1490 DC_IS_XIRCOM(sc) || DC_IS_INTEL(sc)) { 1491 DELAY(10000); 1492 DC_CLRBIT(sc, DC_BUSCTL, DC_BUSCTL_RESET); 1493 i = 0; 1494 } 1495 1496 if (i == DC_TIMEOUT) 1497 printf("dc%d: reset never completed!\n", sc->dc_unit); 1498 1499 /* Wait a little while for the chip to get its brains in order. */ 1500 DELAY(1000); 1501 1502 CSR_WRITE_4(sc, DC_IMR, 0x00000000); 1503 CSR_WRITE_4(sc, DC_BUSCTL, 0x00000000); 1504 CSR_WRITE_4(sc, DC_NETCFG, 0x00000000); 1505 1506 /* 1507 * Bring the SIA out of reset. In some cases, it looks 1508 * like failing to unreset the SIA soon enough gets it 1509 * into a state where it will never come out of reset 1510 * until we reset the whole chip again. 1511 */ 1512 if (DC_IS_INTEL(sc)) { 1513 DC_SETBIT(sc, DC_SIARESET, DC_SIA_RESET); 1514 CSR_WRITE_4(sc, DC_10BTCTRL, 0); 1515 CSR_WRITE_4(sc, DC_WATCHDOG, 0); 1516 } 1517 1518 return; 1519 } 1520 1521 static struct dc_type *dc_devtype(dev) 1522 device_t dev; 1523 { 1524 struct dc_type *t; 1525 u_int32_t rev; 1526 1527 t = dc_devs; 1528 1529 while(t->dc_name != NULL) { 1530 if ((pci_get_vendor(dev) == t->dc_vid) && 1531 (pci_get_device(dev) == t->dc_did)) { 1532 /* Check the PCI revision */ 1533 rev = pci_read_config(dev, DC_PCI_CFRV, 4) & 0xFF; 1534 if (t->dc_did == DC_DEVICEID_98713 && 1535 rev >= DC_REVISION_98713A) 1536 t++; 1537 if (t->dc_did == DC_DEVICEID_98713_CP && 1538 rev >= DC_REVISION_98713A) 1539 t++; 1540 if (t->dc_did == DC_DEVICEID_987x5 && 1541 rev >= DC_REVISION_98715AEC_C) 1542 t++; 1543 if (t->dc_did == DC_DEVICEID_987x5 && 1544 rev >= DC_REVISION_98725) 1545 t++; 1546 if (t->dc_did == DC_DEVICEID_AX88140A && 1547 rev >= DC_REVISION_88141) 1548 t++; 1549 if (t->dc_did == DC_DEVICEID_82C168 && 1550 rev >= DC_REVISION_82C169) 1551 t++; 1552 if (t->dc_did == DC_DEVICEID_DM9102 && 1553 rev >= DC_REVISION_DM9102A) 1554 t++; 1555 return(t); 1556 } 1557 t++; 1558 } 1559 1560 return(NULL); 1561 } 1562 1563 /* 1564 * Probe for a 21143 or clone chip. Check the PCI vendor and device 1565 * IDs against our list and return a device name if we find a match. 1566 * We do a little bit of extra work to identify the exact type of 1567 * chip. The MX98713 and MX98713A have the same PCI vendor/device ID, 1568 * but different revision IDs. The same is true for 98715/98715A 1569 * chips and the 98725, as well as the ASIX and ADMtek chips. In some 1570 * cases, the exact chip revision affects driver behavior. 1571 */ 1572 static int dc_probe(dev) 1573 device_t dev; 1574 { 1575 struct dc_type *t; 1576 1577 t = dc_devtype(dev); 1578 1579 if (t != NULL) { 1580 device_set_desc(dev, t->dc_name); 1581 return(0); 1582 } 1583 1584 return(ENXIO); 1585 } 1586 1587 static void dc_acpi(dev) 1588 device_t dev; 1589 { 1590 int unit; 1591 1592 unit = device_get_unit(dev); 1593 1594 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) { 1595 u_int32_t iobase, membase, irq; 1596 1597 /* Save important PCI config data. */ 1598 iobase = pci_read_config(dev, DC_PCI_CFBIO, 4); 1599 membase = pci_read_config(dev, DC_PCI_CFBMA, 4); 1600 irq = pci_read_config(dev, DC_PCI_CFIT, 4); 1601 1602 /* Reset the power state. */ 1603 printf("dc%d: chip is in D%d power mode " 1604 "-- setting to D0\n", unit, 1605 pci_get_powerstate(dev)); 1606 pci_set_powerstate(dev, PCI_POWERSTATE_D0); 1607 1608 /* Restore PCI config data. */ 1609 pci_write_config(dev, DC_PCI_CFBIO, iobase, 4); 1610 pci_write_config(dev, DC_PCI_CFBMA, membase, 4); 1611 pci_write_config(dev, DC_PCI_CFIT, irq, 4); 1612 } 1613 1614 return; 1615 } 1616 1617 static void dc_apply_fixup(sc, media) 1618 struct dc_softc *sc; 1619 int media; 1620 { 1621 struct dc_mediainfo *m; 1622 u_int8_t *p; 1623 int i; 1624 u_int32_t reg; 1625 1626 m = sc->dc_mi; 1627 1628 while (m != NULL) { 1629 if (m->dc_media == media) 1630 break; 1631 m = m->dc_next; 1632 } 1633 1634 if (m == NULL) 1635 return; 1636 1637 for (i = 0, p = m->dc_reset_ptr; i < m->dc_reset_len; i++, p += 2) { 1638 reg = (p[0] | (p[1] << 8)) << 16; 1639 CSR_WRITE_4(sc, DC_WATCHDOG, reg); 1640 } 1641 1642 for (i = 0, p = m->dc_gp_ptr; i < m->dc_gp_len; i++, p += 2) { 1643 reg = (p[0] | (p[1] << 8)) << 16; 1644 CSR_WRITE_4(sc, DC_WATCHDOG, reg); 1645 } 1646 1647 return; 1648 } 1649 1650 static void dc_decode_leaf_sia(sc, l) 1651 struct dc_softc *sc; 1652 struct dc_eblock_sia *l; 1653 { 1654 struct dc_mediainfo *m; 1655 1656 m = malloc(sizeof(struct dc_mediainfo), M_DEVBUF, M_NOWAIT); 1657 bzero(m, sizeof(struct dc_mediainfo)); 1658 if (l->dc_sia_code == DC_SIA_CODE_10BT) 1659 m->dc_media = IFM_10_T; 1660 1661 if (l->dc_sia_code == DC_SIA_CODE_10BT_FDX) 1662 m->dc_media = IFM_10_T|IFM_FDX; 1663 1664 if (l->dc_sia_code == DC_SIA_CODE_10B2) 1665 m->dc_media = IFM_10_2; 1666 1667 if (l->dc_sia_code == DC_SIA_CODE_10B5) 1668 m->dc_media = IFM_10_5; 1669 1670 m->dc_gp_len = 2; 1671 m->dc_gp_ptr = (u_int8_t *)&l->dc_sia_gpio_ctl; 1672 1673 m->dc_next = sc->dc_mi; 1674 sc->dc_mi = m; 1675 1676 sc->dc_pmode = DC_PMODE_SIA; 1677 1678 return; 1679 } 1680 1681 static void dc_decode_leaf_sym(sc, l) 1682 struct dc_softc *sc; 1683 struct dc_eblock_sym *l; 1684 { 1685 struct dc_mediainfo *m; 1686 1687 m = malloc(sizeof(struct dc_mediainfo), M_DEVBUF, M_NOWAIT); 1688 bzero(m, sizeof(struct dc_mediainfo)); 1689 if (l->dc_sym_code == DC_SYM_CODE_100BT) 1690 m->dc_media = IFM_100_TX; 1691 1692 if (l->dc_sym_code == DC_SYM_CODE_100BT_FDX) 1693 m->dc_media = IFM_100_TX|IFM_FDX; 1694 1695 m->dc_gp_len = 2; 1696 m->dc_gp_ptr = (u_int8_t *)&l->dc_sym_gpio_ctl; 1697 1698 m->dc_next = sc->dc_mi; 1699 sc->dc_mi = m; 1700 1701 sc->dc_pmode = DC_PMODE_SYM; 1702 1703 return; 1704 } 1705 1706 static void dc_decode_leaf_mii(sc, l) 1707 struct dc_softc *sc; 1708 struct dc_eblock_mii *l; 1709 { 1710 u_int8_t *p; 1711 struct dc_mediainfo *m; 1712 1713 m = malloc(sizeof(struct dc_mediainfo), M_DEVBUF, M_NOWAIT); 1714 bzero(m, sizeof(struct dc_mediainfo)); 1715 /* We abuse IFM_AUTO to represent MII. */ 1716 m->dc_media = IFM_AUTO; 1717 m->dc_gp_len = l->dc_gpr_len; 1718 1719 p = (u_int8_t *)l; 1720 p += sizeof(struct dc_eblock_mii); 1721 m->dc_gp_ptr = p; 1722 p += 2 * l->dc_gpr_len; 1723 m->dc_reset_len = *p; 1724 p++; 1725 m->dc_reset_ptr = p; 1726 1727 m->dc_next = sc->dc_mi; 1728 sc->dc_mi = m; 1729 1730 return; 1731 } 1732 1733 static void dc_parse_21143_srom(sc) 1734 struct dc_softc *sc; 1735 { 1736 struct dc_leaf_hdr *lhdr; 1737 struct dc_eblock_hdr *hdr; 1738 int i, loff; 1739 char *ptr; 1740 1741 loff = sc->dc_srom[27]; 1742 lhdr = (struct dc_leaf_hdr *)&(sc->dc_srom[loff]); 1743 1744 ptr = (char *)lhdr; 1745 ptr += sizeof(struct dc_leaf_hdr) - 1; 1746 for (i = 0; i < lhdr->dc_mcnt; i++) { 1747 hdr = (struct dc_eblock_hdr *)ptr; 1748 switch(hdr->dc_type) { 1749 case DC_EBLOCK_MII: 1750 dc_decode_leaf_mii(sc, (struct dc_eblock_mii *)hdr); 1751 break; 1752 case DC_EBLOCK_SIA: 1753 dc_decode_leaf_sia(sc, (struct dc_eblock_sia *)hdr); 1754 break; 1755 case DC_EBLOCK_SYM: 1756 dc_decode_leaf_sym(sc, (struct dc_eblock_sym *)hdr); 1757 break; 1758 default: 1759 /* Don't care. Yet. */ 1760 break; 1761 } 1762 ptr += (hdr->dc_len & 0x7F); 1763 ptr++; 1764 } 1765 1766 return; 1767 } 1768 1769 /* 1770 * Attach the interface. Allocate softc structures, do ifmedia 1771 * setup and ethernet/BPF attach. 1772 */ 1773 static int dc_attach(dev) 1774 device_t dev; 1775 { 1776 int tmp = 0; 1777 u_char eaddr[ETHER_ADDR_LEN]; 1778 u_int32_t command; 1779 struct dc_softc *sc; 1780 struct ifnet *ifp; 1781 u_int32_t revision; 1782 int unit, error = 0, rid, mac_offset; 1783 1784 sc = device_get_softc(dev); 1785 unit = device_get_unit(dev); 1786 bzero(sc, sizeof(struct dc_softc)); 1787 1788 mtx_init(&sc->dc_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 1789 MTX_DEF | MTX_RECURSE); 1790 1791 /* 1792 * Handle power management nonsense. 1793 */ 1794 dc_acpi(dev); 1795 1796 /* 1797 * Map control/status registers. 1798 */ 1799 pci_enable_busmaster(dev); 1800 pci_enable_io(dev, SYS_RES_IOPORT); 1801 pci_enable_io(dev, SYS_RES_MEMORY); 1802 command = pci_read_config(dev, PCIR_COMMAND, 4); 1803 1804 #ifdef DC_USEIOSPACE 1805 if (!(command & PCIM_CMD_PORTEN)) { 1806 printf("dc%d: failed to enable I/O ports!\n", unit); 1807 error = ENXIO; 1808 goto fail_nolock; 1809 } 1810 #else 1811 if (!(command & PCIM_CMD_MEMEN)) { 1812 printf("dc%d: failed to enable memory mapping!\n", unit); 1813 error = ENXIO; 1814 goto fail_nolock; 1815 } 1816 #endif 1817 1818 rid = DC_RID; 1819 sc->dc_res = bus_alloc_resource(dev, DC_RES, &rid, 1820 0, ~0, 1, RF_ACTIVE); 1821 1822 if (sc->dc_res == NULL) { 1823 printf("dc%d: couldn't map ports/memory\n", unit); 1824 error = ENXIO; 1825 goto fail_nolock; 1826 } 1827 1828 sc->dc_btag = rman_get_bustag(sc->dc_res); 1829 sc->dc_bhandle = rman_get_bushandle(sc->dc_res); 1830 1831 /* Allocate interrupt */ 1832 rid = 0; 1833 sc->dc_irq = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, 0, ~0, 1, 1834 RF_SHAREABLE | RF_ACTIVE); 1835 1836 if (sc->dc_irq == NULL) { 1837 printf("dc%d: couldn't map interrupt\n", unit); 1838 bus_release_resource(dev, DC_RES, DC_RID, sc->dc_res); 1839 error = ENXIO; 1840 goto fail_nolock; 1841 } 1842 1843 error = bus_setup_intr(dev, sc->dc_irq, INTR_TYPE_NET | 1844 (IS_MPSAFE ? INTR_MPSAFE : 0), 1845 dc_intr, sc, &sc->dc_intrhand); 1846 1847 if (error) { 1848 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->dc_irq); 1849 bus_release_resource(dev, DC_RES, DC_RID, sc->dc_res); 1850 printf("dc%d: couldn't set up irq\n", unit); 1851 goto fail_nolock; 1852 } 1853 DC_LOCK(sc); 1854 1855 /* Need this info to decide on a chip type. */ 1856 sc->dc_info = dc_devtype(dev); 1857 revision = pci_read_config(dev, DC_PCI_CFRV, 4) & 0x000000FF; 1858 1859 switch(sc->dc_info->dc_did) { 1860 case DC_DEVICEID_21143: 1861 sc->dc_type = DC_TYPE_21143; 1862 sc->dc_flags |= DC_TX_POLL|DC_TX_USE_TX_INTR; 1863 sc->dc_flags |= DC_REDUCED_MII_POLL; 1864 /* Save EEPROM contents so we can parse them later. */ 1865 dc_read_eeprom(sc, (caddr_t)&sc->dc_srom, 0, 512, 0); 1866 break; 1867 case DC_DEVICEID_DM9100: 1868 case DC_DEVICEID_DM9102: 1869 sc->dc_type = DC_TYPE_DM9102; 1870 sc->dc_flags |= DC_TX_COALESCE|DC_TX_INTR_ALWAYS; 1871 sc->dc_flags |= DC_REDUCED_MII_POLL|DC_TX_STORENFWD; 1872 sc->dc_pmode = DC_PMODE_MII; 1873 /* Increase the latency timer value. */ 1874 command = pci_read_config(dev, DC_PCI_CFLT, 4); 1875 command &= 0xFFFF00FF; 1876 command |= 0x00008000; 1877 pci_write_config(dev, DC_PCI_CFLT, command, 4); 1878 break; 1879 case DC_DEVICEID_AL981: 1880 sc->dc_type = DC_TYPE_AL981; 1881 sc->dc_flags |= DC_TX_USE_TX_INTR; 1882 sc->dc_flags |= DC_TX_ADMTEK_WAR; 1883 sc->dc_pmode = DC_PMODE_MII; 1884 break; 1885 case DC_DEVICEID_AN985: 1886 case DC_DEVICEID_FE2500: 1887 case DC_DEVICEID_EN2242: 1888 sc->dc_type = DC_TYPE_AN985; 1889 sc->dc_flags |= DC_TX_USE_TX_INTR; 1890 sc->dc_flags |= DC_TX_ADMTEK_WAR; 1891 sc->dc_pmode = DC_PMODE_MII; 1892 break; 1893 case DC_DEVICEID_98713: 1894 case DC_DEVICEID_98713_CP: 1895 if (revision < DC_REVISION_98713A) { 1896 sc->dc_type = DC_TYPE_98713; 1897 } 1898 if (revision >= DC_REVISION_98713A) { 1899 sc->dc_type = DC_TYPE_98713A; 1900 sc->dc_flags |= DC_21143_NWAY; 1901 } 1902 sc->dc_flags |= DC_REDUCED_MII_POLL; 1903 sc->dc_flags |= DC_TX_POLL|DC_TX_USE_TX_INTR; 1904 break; 1905 case DC_DEVICEID_987x5: 1906 case DC_DEVICEID_EN1217: 1907 /* 1908 * Macronix MX98715AEC-C/D/E parts have only a 1909 * 128-bit hash table. We need to deal with these 1910 * in the same manner as the PNIC II so that we 1911 * get the right number of bits out of the 1912 * CRC routine. 1913 */ 1914 if (revision >= DC_REVISION_98715AEC_C && 1915 revision < DC_REVISION_98725) 1916 sc->dc_flags |= DC_128BIT_HASH; 1917 sc->dc_type = DC_TYPE_987x5; 1918 sc->dc_flags |= DC_TX_POLL|DC_TX_USE_TX_INTR; 1919 sc->dc_flags |= DC_REDUCED_MII_POLL|DC_21143_NWAY; 1920 break; 1921 case DC_DEVICEID_98727: 1922 sc->dc_type = DC_TYPE_987x5; 1923 sc->dc_flags |= DC_TX_POLL|DC_TX_USE_TX_INTR; 1924 sc->dc_flags |= DC_REDUCED_MII_POLL|DC_21143_NWAY; 1925 break; 1926 case DC_DEVICEID_82C115: 1927 sc->dc_type = DC_TYPE_PNICII; 1928 sc->dc_flags |= DC_TX_POLL|DC_TX_USE_TX_INTR|DC_128BIT_HASH; 1929 sc->dc_flags |= DC_REDUCED_MII_POLL|DC_21143_NWAY; 1930 break; 1931 case DC_DEVICEID_82C168: 1932 sc->dc_type = DC_TYPE_PNIC; 1933 sc->dc_flags |= DC_TX_STORENFWD|DC_TX_INTR_ALWAYS; 1934 sc->dc_flags |= DC_PNIC_RX_BUG_WAR; 1935 sc->dc_pnic_rx_buf = malloc(DC_RXLEN * 5, M_DEVBUF, M_NOWAIT); 1936 if (revision < DC_REVISION_82C169) 1937 sc->dc_pmode = DC_PMODE_SYM; 1938 break; 1939 case DC_DEVICEID_AX88140A: 1940 sc->dc_type = DC_TYPE_ASIX; 1941 sc->dc_flags |= DC_TX_USE_TX_INTR|DC_TX_INTR_FIRSTFRAG; 1942 sc->dc_flags |= DC_REDUCED_MII_POLL; 1943 sc->dc_pmode = DC_PMODE_MII; 1944 break; 1945 case DC_DEVICEID_X3201: 1946 sc->dc_type = DC_TYPE_XIRCOM; 1947 sc->dc_flags |= DC_TX_INTR_ALWAYS | DC_TX_COALESCE | 1948 DC_TX_ALIGN; 1949 /* 1950 * We don't actually need to coalesce, but we're doing 1951 * it to obtain a double word aligned buffer. 1952 * The DC_TX_COALESCE flag is required. 1953 */ 1954 break; 1955 case DC_DEVICEID_RS7112: 1956 sc->dc_type = DC_TYPE_CONEXANT; 1957 sc->dc_flags |= DC_TX_INTR_ALWAYS; 1958 sc->dc_flags |= DC_REDUCED_MII_POLL; 1959 sc->dc_pmode = DC_PMODE_MII; 1960 dc_read_eeprom(sc, (caddr_t)&sc->dc_srom, 0, 256, 0); 1961 break; 1962 default: 1963 printf("dc%d: unknown device: %x\n", sc->dc_unit, 1964 sc->dc_info->dc_did); 1965 break; 1966 } 1967 1968 /* Save the cache line size. */ 1969 if (DC_IS_DAVICOM(sc)) 1970 sc->dc_cachesize = 0; 1971 else 1972 sc->dc_cachesize = pci_read_config(dev, 1973 DC_PCI_CFLT, 4) & 0xFF; 1974 1975 /* Reset the adapter. */ 1976 dc_reset(sc); 1977 1978 /* Take 21143 out of snooze mode */ 1979 if (DC_IS_INTEL(sc) || DC_IS_XIRCOM(sc)) { 1980 command = pci_read_config(dev, DC_PCI_CFDD, 4); 1981 command &= ~(DC_CFDD_SNOOZE_MODE|DC_CFDD_SLEEP_MODE); 1982 pci_write_config(dev, DC_PCI_CFDD, command, 4); 1983 } 1984 1985 /* 1986 * Try to learn something about the supported media. 1987 * We know that ASIX and ADMtek and Davicom devices 1988 * will *always* be using MII media, so that's a no-brainer. 1989 * The tricky ones are the Macronix/PNIC II and the 1990 * Intel 21143. 1991 */ 1992 if (DC_IS_INTEL(sc)) 1993 dc_parse_21143_srom(sc); 1994 else if (DC_IS_MACRONIX(sc) || DC_IS_PNICII(sc)) { 1995 if (sc->dc_type == DC_TYPE_98713) 1996 sc->dc_pmode = DC_PMODE_MII; 1997 else 1998 sc->dc_pmode = DC_PMODE_SYM; 1999 } else if (!sc->dc_pmode) 2000 sc->dc_pmode = DC_PMODE_MII; 2001 2002 /* 2003 * Get station address from the EEPROM. 2004 */ 2005 switch(sc->dc_type) { 2006 case DC_TYPE_98713: 2007 case DC_TYPE_98713A: 2008 case DC_TYPE_987x5: 2009 case DC_TYPE_PNICII: 2010 dc_read_eeprom(sc, (caddr_t)&mac_offset, 2011 (DC_EE_NODEADDR_OFFSET / 2), 1, 0); 2012 dc_read_eeprom(sc, (caddr_t)&eaddr, (mac_offset / 2), 3, 0); 2013 break; 2014 case DC_TYPE_PNIC: 2015 dc_read_eeprom(sc, (caddr_t)&eaddr, 0, 3, 1); 2016 break; 2017 case DC_TYPE_DM9102: 2018 case DC_TYPE_21143: 2019 case DC_TYPE_ASIX: 2020 dc_read_eeprom(sc, (caddr_t)&eaddr, DC_EE_NODEADDR, 3, 0); 2021 break; 2022 case DC_TYPE_AL981: 2023 case DC_TYPE_AN985: 2024 dc_read_eeprom(sc, (caddr_t)&eaddr, DC_AL_EE_NODEADDR, 3, 0); 2025 break; 2026 case DC_TYPE_CONEXANT: 2027 bcopy(sc->dc_srom + DC_CONEXANT_EE_NODEADDR, &eaddr, 6); 2028 break; 2029 case DC_TYPE_XIRCOM: 2030 dc_read_eeprom(sc, (caddr_t)&eaddr, 3, 3, 0); 2031 break; 2032 default: 2033 dc_read_eeprom(sc, (caddr_t)&eaddr, DC_EE_NODEADDR, 3, 0); 2034 break; 2035 } 2036 2037 /* 2038 * A 21143 or clone chip was detected. Inform the world. 2039 */ 2040 printf("dc%d: Ethernet address: %6D\n", unit, eaddr, ":"); 2041 2042 sc->dc_unit = unit; 2043 bcopy(eaddr, (char *)&sc->arpcom.ac_enaddr, ETHER_ADDR_LEN); 2044 2045 sc->dc_ldata = contigmalloc(sizeof(struct dc_list_data), M_DEVBUF, 2046 M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0); 2047 2048 if (sc->dc_ldata == NULL) { 2049 printf("dc%d: no memory for list buffers!\n", unit); 2050 bus_teardown_intr(dev, sc->dc_irq, sc->dc_intrhand); 2051 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->dc_irq); 2052 bus_release_resource(dev, DC_RES, DC_RID, sc->dc_res); 2053 error = ENXIO; 2054 goto fail; 2055 } 2056 2057 bzero(sc->dc_ldata, sizeof(struct dc_list_data)); 2058 2059 ifp = &sc->arpcom.ac_if; 2060 ifp->if_softc = sc; 2061 ifp->if_unit = unit; 2062 ifp->if_name = "dc"; 2063 /* XXX: bleah, MTU gets overwritten in ether_ifattach() */ 2064 ifp->if_mtu = ETHERMTU; 2065 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 2066 ifp->if_ioctl = dc_ioctl; 2067 ifp->if_output = ether_output; 2068 ifp->if_start = dc_start; 2069 ifp->if_watchdog = dc_watchdog; 2070 ifp->if_init = dc_init; 2071 ifp->if_baudrate = 10000000; 2072 ifp->if_snd.ifq_maxlen = DC_TX_LIST_CNT - 1; 2073 2074 /* 2075 * Do MII setup. If this is a 21143, check for a PHY on the 2076 * MII bus after applying any necessary fixups to twiddle the 2077 * GPIO bits. If we don't end up finding a PHY, restore the 2078 * old selection (SIA only or SIA/SYM) and attach the dcphy 2079 * driver instead. 2080 */ 2081 if (DC_IS_INTEL(sc)) { 2082 dc_apply_fixup(sc, IFM_AUTO); 2083 tmp = sc->dc_pmode; 2084 sc->dc_pmode = DC_PMODE_MII; 2085 } 2086 2087 error = mii_phy_probe(dev, &sc->dc_miibus, 2088 dc_ifmedia_upd, dc_ifmedia_sts); 2089 2090 if (error && DC_IS_INTEL(sc)) { 2091 sc->dc_pmode = tmp; 2092 if (sc->dc_pmode != DC_PMODE_SIA) 2093 sc->dc_pmode = DC_PMODE_SYM; 2094 sc->dc_flags |= DC_21143_NWAY; 2095 mii_phy_probe(dev, &sc->dc_miibus, 2096 dc_ifmedia_upd, dc_ifmedia_sts); 2097 /* 2098 * For non-MII cards, we need to have the 21143 2099 * drive the LEDs. Except there are some systems 2100 * like the NEC VersaPro NoteBook PC which have no 2101 * LEDs, and twiddling these bits has adverse effects 2102 * on them. (I.e. you suddenly can't get a link.) 2103 */ 2104 if (pci_read_config(dev, DC_PCI_CSID, 4) != 0x80281033) 2105 sc->dc_flags |= DC_TULIP_LEDS; 2106 error = 0; 2107 } 2108 2109 if (error) { 2110 printf("dc%d: MII without any PHY!\n", sc->dc_unit); 2111 bus_teardown_intr(dev, sc->dc_irq, sc->dc_intrhand); 2112 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->dc_irq); 2113 bus_release_resource(dev, DC_RES, DC_RID, sc->dc_res); 2114 error = ENXIO; 2115 goto fail; 2116 } 2117 2118 if (DC_IS_XIRCOM(sc)) { 2119 /* 2120 * setup General Purpose Port mode and data so the tulip 2121 * can talk to the MII. 2122 */ 2123 CSR_WRITE_4(sc, DC_SIAGP, DC_SIAGP_WRITE_EN | DC_SIAGP_INT1_EN | 2124 DC_SIAGP_MD_GP2_OUTPUT | DC_SIAGP_MD_GP0_OUTPUT); 2125 DELAY(10); 2126 CSR_WRITE_4(sc, DC_SIAGP, DC_SIAGP_INT1_EN | 2127 DC_SIAGP_MD_GP2_OUTPUT | DC_SIAGP_MD_GP0_OUTPUT); 2128 DELAY(10); 2129 } 2130 2131 /* 2132 * Call MI attach routine. 2133 */ 2134 ether_ifattach(ifp, ETHER_BPF_SUPPORTED); 2135 2136 /* 2137 * Tell the upper layer(s) we support long frames. 2138 */ 2139 ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header); 2140 2141 callout_init(&sc->dc_stat_ch, IS_MPSAFE); 2142 2143 #ifdef SRM_MEDIA 2144 sc->dc_srm_media = 0; 2145 2146 /* Remember the SRM console media setting */ 2147 if (DC_IS_INTEL(sc)) { 2148 command = pci_read_config(dev, DC_PCI_CFDD, 4); 2149 command &= ~(DC_CFDD_SNOOZE_MODE|DC_CFDD_SLEEP_MODE); 2150 switch ((command >> 8) & 0xff) { 2151 case 3: 2152 sc->dc_srm_media = IFM_10_T; 2153 break; 2154 case 4: 2155 sc->dc_srm_media = IFM_10_T | IFM_FDX; 2156 break; 2157 case 5: 2158 sc->dc_srm_media = IFM_100_TX; 2159 break; 2160 case 6: 2161 sc->dc_srm_media = IFM_100_TX | IFM_FDX; 2162 break; 2163 } 2164 if (sc->dc_srm_media) 2165 sc->dc_srm_media |= IFM_ACTIVE | IFM_ETHER; 2166 } 2167 #endif 2168 2169 DC_UNLOCK(sc); 2170 return(0); 2171 2172 fail: 2173 DC_UNLOCK(sc); 2174 fail_nolock: 2175 mtx_destroy(&sc->dc_mtx); 2176 return(error); 2177 } 2178 2179 static int dc_detach(dev) 2180 device_t dev; 2181 { 2182 struct dc_softc *sc; 2183 struct ifnet *ifp; 2184 struct dc_mediainfo *m; 2185 2186 sc = device_get_softc(dev); 2187 2188 DC_LOCK(sc); 2189 2190 ifp = &sc->arpcom.ac_if; 2191 2192 dc_stop(sc); 2193 ether_ifdetach(ifp, ETHER_BPF_SUPPORTED); 2194 2195 bus_generic_detach(dev); 2196 device_delete_child(dev, sc->dc_miibus); 2197 2198 bus_teardown_intr(dev, sc->dc_irq, sc->dc_intrhand); 2199 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->dc_irq); 2200 bus_release_resource(dev, DC_RES, DC_RID, sc->dc_res); 2201 2202 contigfree(sc->dc_ldata, sizeof(struct dc_list_data), M_DEVBUF); 2203 if (sc->dc_pnic_rx_buf != NULL) 2204 free(sc->dc_pnic_rx_buf, M_DEVBUF); 2205 2206 while(sc->dc_mi != NULL) { 2207 m = sc->dc_mi->dc_next; 2208 free(sc->dc_mi, M_DEVBUF); 2209 sc->dc_mi = m; 2210 } 2211 2212 DC_UNLOCK(sc); 2213 mtx_destroy(&sc->dc_mtx); 2214 2215 return(0); 2216 } 2217 2218 /* 2219 * Initialize the transmit descriptors. 2220 */ 2221 static int dc_list_tx_init(sc) 2222 struct dc_softc *sc; 2223 { 2224 struct dc_chain_data *cd; 2225 struct dc_list_data *ld; 2226 int i, nexti; 2227 2228 cd = &sc->dc_cdata; 2229 ld = sc->dc_ldata; 2230 for (i = 0; i < DC_TX_LIST_CNT; i++) { 2231 nexti = (i == (DC_TX_LIST_CNT - 1)) ? 0 : i+1; 2232 ld->dc_tx_list[i].dc_next = vtophys(&ld->dc_tx_list[nexti]); 2233 cd->dc_tx_chain[i] = NULL; 2234 ld->dc_tx_list[i].dc_data = 0; 2235 ld->dc_tx_list[i].dc_ctl = 0; 2236 } 2237 2238 cd->dc_tx_prod = cd->dc_tx_cons = cd->dc_tx_cnt = 0; 2239 2240 return(0); 2241 } 2242 2243 2244 /* 2245 * Initialize the RX descriptors and allocate mbufs for them. Note that 2246 * we arrange the descriptors in a closed ring, so that the last descriptor 2247 * points back to the first. 2248 */ 2249 static int dc_list_rx_init(sc) 2250 struct dc_softc *sc; 2251 { 2252 struct dc_chain_data *cd; 2253 struct dc_list_data *ld; 2254 int i, nexti; 2255 2256 cd = &sc->dc_cdata; 2257 ld = sc->dc_ldata; 2258 2259 for (i = 0; i < DC_RX_LIST_CNT; i++) { 2260 if (dc_newbuf(sc, i, NULL) == ENOBUFS) 2261 return(ENOBUFS); 2262 nexti = (i == (DC_RX_LIST_CNT - 1)) ? 0 : i+1; 2263 ld->dc_rx_list[i].dc_next = vtophys(&ld->dc_rx_list[nexti]); 2264 } 2265 2266 cd->dc_rx_prod = 0; 2267 2268 return(0); 2269 } 2270 2271 /* 2272 * Initialize an RX descriptor and attach an MBUF cluster. 2273 */ 2274 static int dc_newbuf(sc, i, m) 2275 struct dc_softc *sc; 2276 int i; 2277 struct mbuf *m; 2278 { 2279 struct mbuf *m_new = NULL; 2280 struct dc_desc *c; 2281 2282 c = &sc->dc_ldata->dc_rx_list[i]; 2283 2284 if (m == NULL) { 2285 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 2286 if (m_new == NULL) 2287 return(ENOBUFS); 2288 2289 MCLGET(m_new, M_DONTWAIT); 2290 if (!(m_new->m_flags & M_EXT)) { 2291 m_freem(m_new); 2292 return(ENOBUFS); 2293 } 2294 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 2295 } else { 2296 m_new = m; 2297 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 2298 m_new->m_data = m_new->m_ext.ext_buf; 2299 } 2300 2301 m_adj(m_new, sizeof(u_int64_t)); 2302 2303 /* 2304 * If this is a PNIC chip, zero the buffer. This is part 2305 * of the workaround for the receive bug in the 82c168 and 2306 * 82c169 chips. 2307 */ 2308 if (sc->dc_flags & DC_PNIC_RX_BUG_WAR) 2309 bzero((char *)mtod(m_new, char *), m_new->m_len); 2310 2311 sc->dc_cdata.dc_rx_chain[i] = m_new; 2312 c->dc_data = vtophys(mtod(m_new, caddr_t)); 2313 c->dc_ctl = DC_RXCTL_RLINK | DC_RXLEN; 2314 c->dc_status = DC_RXSTAT_OWN; 2315 2316 return(0); 2317 } 2318 2319 /* 2320 * Grrrrr. 2321 * The PNIC chip has a terrible bug in it that manifests itself during 2322 * periods of heavy activity. The exact mode of failure if difficult to 2323 * pinpoint: sometimes it only happens in promiscuous mode, sometimes it 2324 * will happen on slow machines. The bug is that sometimes instead of 2325 * uploading one complete frame during reception, it uploads what looks 2326 * like the entire contents of its FIFO memory. The frame we want is at 2327 * the end of the whole mess, but we never know exactly how much data has 2328 * been uploaded, so salvaging the frame is hard. 2329 * 2330 * There is only one way to do it reliably, and it's disgusting. 2331 * Here's what we know: 2332 * 2333 * - We know there will always be somewhere between one and three extra 2334 * descriptors uploaded. 2335 * 2336 * - We know the desired received frame will always be at the end of the 2337 * total data upload. 2338 * 2339 * - We know the size of the desired received frame because it will be 2340 * provided in the length field of the status word in the last descriptor. 2341 * 2342 * Here's what we do: 2343 * 2344 * - When we allocate buffers for the receive ring, we bzero() them. 2345 * This means that we know that the buffer contents should be all 2346 * zeros, except for data uploaded by the chip. 2347 * 2348 * - We also force the PNIC chip to upload frames that include the 2349 * ethernet CRC at the end. 2350 * 2351 * - We gather all of the bogus frame data into a single buffer. 2352 * 2353 * - We then position a pointer at the end of this buffer and scan 2354 * backwards until we encounter the first non-zero byte of data. 2355 * This is the end of the received frame. We know we will encounter 2356 * some data at the end of the frame because the CRC will always be 2357 * there, so even if the sender transmits a packet of all zeros, 2358 * we won't be fooled. 2359 * 2360 * - We know the size of the actual received frame, so we subtract 2361 * that value from the current pointer location. This brings us 2362 * to the start of the actual received packet. 2363 * 2364 * - We copy this into an mbuf and pass it on, along with the actual 2365 * frame length. 2366 * 2367 * The performance hit is tremendous, but it beats dropping frames all 2368 * the time. 2369 */ 2370 2371 #define DC_WHOLEFRAME (DC_RXSTAT_FIRSTFRAG|DC_RXSTAT_LASTFRAG) 2372 static void dc_pnic_rx_bug_war(sc, idx) 2373 struct dc_softc *sc; 2374 int idx; 2375 { 2376 struct dc_desc *cur_rx; 2377 struct dc_desc *c = NULL; 2378 struct mbuf *m = NULL; 2379 unsigned char *ptr; 2380 int i, total_len; 2381 u_int32_t rxstat = 0; 2382 2383 i = sc->dc_pnic_rx_bug_save; 2384 cur_rx = &sc->dc_ldata->dc_rx_list[idx]; 2385 ptr = sc->dc_pnic_rx_buf; 2386 bzero(ptr, sizeof(DC_RXLEN * 5)); 2387 2388 /* Copy all the bytes from the bogus buffers. */ 2389 while (1) { 2390 c = &sc->dc_ldata->dc_rx_list[i]; 2391 rxstat = c->dc_status; 2392 m = sc->dc_cdata.dc_rx_chain[i]; 2393 bcopy(mtod(m, char *), ptr, DC_RXLEN); 2394 ptr += DC_RXLEN; 2395 /* If this is the last buffer, break out. */ 2396 if (i == idx || rxstat & DC_RXSTAT_LASTFRAG) 2397 break; 2398 dc_newbuf(sc, i, m); 2399 DC_INC(i, DC_RX_LIST_CNT); 2400 } 2401 2402 /* Find the length of the actual receive frame. */ 2403 total_len = DC_RXBYTES(rxstat); 2404 2405 /* Scan backwards until we hit a non-zero byte. */ 2406 while(*ptr == 0x00) 2407 ptr--; 2408 2409 /* Round off. */ 2410 if ((uintptr_t)(ptr) & 0x3) 2411 ptr -= 1; 2412 2413 /* Now find the start of the frame. */ 2414 ptr -= total_len; 2415 if (ptr < sc->dc_pnic_rx_buf) 2416 ptr = sc->dc_pnic_rx_buf; 2417 2418 /* 2419 * Now copy the salvaged frame to the last mbuf and fake up 2420 * the status word to make it look like a successful 2421 * frame reception. 2422 */ 2423 dc_newbuf(sc, i, m); 2424 bcopy(ptr, mtod(m, char *), total_len); 2425 cur_rx->dc_status = rxstat | DC_RXSTAT_FIRSTFRAG; 2426 2427 return; 2428 } 2429 2430 /* 2431 * This routine searches the RX ring for dirty descriptors in the 2432 * event that the rxeof routine falls out of sync with the chip's 2433 * current descriptor pointer. This may happen sometimes as a result 2434 * of a "no RX buffer available" condition that happens when the chip 2435 * consumes all of the RX buffers before the driver has a chance to 2436 * process the RX ring. This routine may need to be called more than 2437 * once to bring the driver back in sync with the chip, however we 2438 * should still be getting RX DONE interrupts to drive the search 2439 * for new packets in the RX ring, so we should catch up eventually. 2440 */ 2441 static int dc_rx_resync(sc) 2442 struct dc_softc *sc; 2443 { 2444 int i, pos; 2445 struct dc_desc *cur_rx; 2446 2447 pos = sc->dc_cdata.dc_rx_prod; 2448 2449 for (i = 0; i < DC_RX_LIST_CNT; i++) { 2450 cur_rx = &sc->dc_ldata->dc_rx_list[pos]; 2451 if (!(cur_rx->dc_status & DC_RXSTAT_OWN)) 2452 break; 2453 DC_INC(pos, DC_RX_LIST_CNT); 2454 } 2455 2456 /* If the ring really is empty, then just return. */ 2457 if (i == DC_RX_LIST_CNT) 2458 return(0); 2459 2460 /* We've fallen behing the chip: catch it. */ 2461 sc->dc_cdata.dc_rx_prod = pos; 2462 2463 return(EAGAIN); 2464 } 2465 2466 /* 2467 * A frame has been uploaded: pass the resulting mbuf chain up to 2468 * the higher level protocols. 2469 */ 2470 static void dc_rxeof(sc) 2471 struct dc_softc *sc; 2472 { 2473 struct ether_header *eh; 2474 struct mbuf *m; 2475 struct ifnet *ifp; 2476 struct dc_desc *cur_rx; 2477 int i, total_len = 0; 2478 u_int32_t rxstat; 2479 2480 ifp = &sc->arpcom.ac_if; 2481 i = sc->dc_cdata.dc_rx_prod; 2482 2483 while(!(sc->dc_ldata->dc_rx_list[i].dc_status & DC_RXSTAT_OWN)) { 2484 2485 #ifdef DEVICE_POLLING 2486 if (ifp->if_flags & IFF_POLLING) { 2487 if (sc->rxcycles <= 0) 2488 break; 2489 sc->rxcycles--; 2490 } 2491 #endif /* DEVICE_POLLING */ 2492 cur_rx = &sc->dc_ldata->dc_rx_list[i]; 2493 rxstat = cur_rx->dc_status; 2494 m = sc->dc_cdata.dc_rx_chain[i]; 2495 total_len = DC_RXBYTES(rxstat); 2496 2497 if (sc->dc_flags & DC_PNIC_RX_BUG_WAR) { 2498 if ((rxstat & DC_WHOLEFRAME) != DC_WHOLEFRAME) { 2499 if (rxstat & DC_RXSTAT_FIRSTFRAG) 2500 sc->dc_pnic_rx_bug_save = i; 2501 if ((rxstat & DC_RXSTAT_LASTFRAG) == 0) { 2502 DC_INC(i, DC_RX_LIST_CNT); 2503 continue; 2504 } 2505 dc_pnic_rx_bug_war(sc, i); 2506 rxstat = cur_rx->dc_status; 2507 total_len = DC_RXBYTES(rxstat); 2508 } 2509 } 2510 2511 sc->dc_cdata.dc_rx_chain[i] = NULL; 2512 2513 /* 2514 * If an error occurs, update stats, clear the 2515 * status word and leave the mbuf cluster in place: 2516 * it should simply get re-used next time this descriptor 2517 * comes up in the ring. However, don't report long 2518 * frames as errors since they could be vlans 2519 */ 2520 if ((rxstat & DC_RXSTAT_RXERR)){ 2521 if (!(rxstat & DC_RXSTAT_GIANT) || 2522 (rxstat & (DC_RXSTAT_CRCERR | DC_RXSTAT_DRIBBLE | 2523 DC_RXSTAT_MIIERE | DC_RXSTAT_COLLSEEN | 2524 DC_RXSTAT_RUNT | DC_RXSTAT_DE))) { 2525 ifp->if_ierrors++; 2526 if (rxstat & DC_RXSTAT_COLLSEEN) 2527 ifp->if_collisions++; 2528 dc_newbuf(sc, i, m); 2529 if (rxstat & DC_RXSTAT_CRCERR) { 2530 DC_INC(i, DC_RX_LIST_CNT); 2531 continue; 2532 } else { 2533 dc_init(sc); 2534 return; 2535 } 2536 } 2537 } 2538 2539 /* No errors; receive the packet. */ 2540 total_len -= ETHER_CRC_LEN; 2541 #ifdef __i386__ 2542 /* 2543 * On the x86 we do not have alignment problems, so try to 2544 * allocate a new buffer for the receive ring, and pass up 2545 * the one where the packet is already, saving the expensive 2546 * copy done in m_devget(). 2547 * If we are on an architecture with alignment problems, or 2548 * if the allocation fails, then use m_devget and leave the 2549 * existing buffer in the receive ring. 2550 */ 2551 if (dc_quick && dc_newbuf(sc, i, NULL) == 0) { 2552 m->m_pkthdr.rcvif = ifp; 2553 m->m_pkthdr.len = m->m_len = total_len; 2554 DC_INC(i, DC_RX_LIST_CNT); 2555 } else 2556 #endif 2557 { 2558 struct mbuf *m0; 2559 2560 m0 = m_devget(mtod(m, char *), total_len, 2561 ETHER_ALIGN, ifp, NULL); 2562 dc_newbuf(sc, i, m); 2563 DC_INC(i, DC_RX_LIST_CNT); 2564 if (m0 == NULL) { 2565 ifp->if_ierrors++; 2566 continue; 2567 } 2568 m = m0; 2569 } 2570 2571 ifp->if_ipackets++; 2572 eh = mtod(m, struct ether_header *); 2573 2574 /* Remove header from mbuf and pass it on. */ 2575 m_adj(m, sizeof(struct ether_header)); 2576 ether_input(ifp, eh, m); 2577 } 2578 2579 sc->dc_cdata.dc_rx_prod = i; 2580 } 2581 2582 /* 2583 * A frame was downloaded to the chip. It's safe for us to clean up 2584 * the list buffers. 2585 */ 2586 2587 static void dc_txeof(sc) 2588 struct dc_softc *sc; 2589 { 2590 struct dc_desc *cur_tx = NULL; 2591 struct ifnet *ifp; 2592 int idx; 2593 2594 ifp = &sc->arpcom.ac_if; 2595 2596 /* 2597 * Go through our tx list and free mbufs for those 2598 * frames that have been transmitted. 2599 */ 2600 idx = sc->dc_cdata.dc_tx_cons; 2601 while(idx != sc->dc_cdata.dc_tx_prod) { 2602 u_int32_t txstat; 2603 2604 cur_tx = &sc->dc_ldata->dc_tx_list[idx]; 2605 txstat = cur_tx->dc_status; 2606 2607 if (txstat & DC_TXSTAT_OWN) 2608 break; 2609 2610 if (!(cur_tx->dc_ctl & DC_TXCTL_LASTFRAG) || 2611 cur_tx->dc_ctl & DC_TXCTL_SETUP) { 2612 if (cur_tx->dc_ctl & DC_TXCTL_SETUP) { 2613 /* 2614 * Yes, the PNIC is so brain damaged 2615 * that it will sometimes generate a TX 2616 * underrun error while DMAing the RX 2617 * filter setup frame. If we detect this, 2618 * we have to send the setup frame again, 2619 * or else the filter won't be programmed 2620 * correctly. 2621 */ 2622 if (DC_IS_PNIC(sc)) { 2623 if (txstat & DC_TXSTAT_ERRSUM) 2624 dc_setfilt(sc); 2625 } 2626 sc->dc_cdata.dc_tx_chain[idx] = NULL; 2627 } 2628 sc->dc_cdata.dc_tx_cnt--; 2629 DC_INC(idx, DC_TX_LIST_CNT); 2630 continue; 2631 } 2632 2633 if (DC_IS_XIRCOM(sc) || DC_IS_CONEXANT(sc)) { 2634 /* 2635 * XXX: Why does my Xircom taunt me so? 2636 * For some reason it likes setting the CARRLOST flag 2637 * even when the carrier is there. wtf?!? 2638 * Who knows, but Conexant chips have the 2639 * same problem. Maybe they took lessons 2640 * from Xircom. 2641 */ 2642 if (/*sc->dc_type == DC_TYPE_21143 &&*/ 2643 sc->dc_pmode == DC_PMODE_MII && 2644 ((txstat & 0xFFFF) & ~(DC_TXSTAT_ERRSUM| 2645 DC_TXSTAT_NOCARRIER))) 2646 txstat &= ~DC_TXSTAT_ERRSUM; 2647 } else { 2648 if (/*sc->dc_type == DC_TYPE_21143 &&*/ 2649 sc->dc_pmode == DC_PMODE_MII && 2650 ((txstat & 0xFFFF) & ~(DC_TXSTAT_ERRSUM| 2651 DC_TXSTAT_NOCARRIER|DC_TXSTAT_CARRLOST))) 2652 txstat &= ~DC_TXSTAT_ERRSUM; 2653 } 2654 2655 if (txstat & DC_TXSTAT_ERRSUM) { 2656 ifp->if_oerrors++; 2657 if (txstat & DC_TXSTAT_EXCESSCOLL) 2658 ifp->if_collisions++; 2659 if (txstat & DC_TXSTAT_LATECOLL) 2660 ifp->if_collisions++; 2661 if (!(txstat & DC_TXSTAT_UNDERRUN)) { 2662 dc_init(sc); 2663 return; 2664 } 2665 } 2666 2667 ifp->if_collisions += (txstat & DC_TXSTAT_COLLCNT) >> 3; 2668 2669 ifp->if_opackets++; 2670 if (sc->dc_cdata.dc_tx_chain[idx] != NULL) { 2671 m_freem(sc->dc_cdata.dc_tx_chain[idx]); 2672 sc->dc_cdata.dc_tx_chain[idx] = NULL; 2673 } 2674 2675 sc->dc_cdata.dc_tx_cnt--; 2676 DC_INC(idx, DC_TX_LIST_CNT); 2677 } 2678 2679 if (idx != sc->dc_cdata.dc_tx_cons) { 2680 /* some buffers have been freed */ 2681 sc->dc_cdata.dc_tx_cons = idx; 2682 ifp->if_flags &= ~IFF_OACTIVE; 2683 } 2684 ifp->if_timer = (sc->dc_cdata.dc_tx_cnt == 0) ? 0 : 5; 2685 2686 return; 2687 } 2688 2689 static void dc_tick(xsc) 2690 void *xsc; 2691 { 2692 struct dc_softc *sc; 2693 struct mii_data *mii; 2694 struct ifnet *ifp; 2695 u_int32_t r; 2696 2697 sc = xsc; 2698 DC_LOCK(sc); 2699 ifp = &sc->arpcom.ac_if; 2700 mii = device_get_softc(sc->dc_miibus); 2701 2702 if (sc->dc_flags & DC_REDUCED_MII_POLL) { 2703 if (sc->dc_flags & DC_21143_NWAY) { 2704 r = CSR_READ_4(sc, DC_10BTSTAT); 2705 if (IFM_SUBTYPE(mii->mii_media_active) == 2706 IFM_100_TX && (r & DC_TSTAT_LS100)) { 2707 sc->dc_link = 0; 2708 mii_mediachg(mii); 2709 } 2710 if (IFM_SUBTYPE(mii->mii_media_active) == 2711 IFM_10_T && (r & DC_TSTAT_LS10)) { 2712 sc->dc_link = 0; 2713 mii_mediachg(mii); 2714 } 2715 if (sc->dc_link == 0) 2716 mii_tick(mii); 2717 } else { 2718 r = CSR_READ_4(sc, DC_ISR); 2719 if ((r & DC_ISR_RX_STATE) == DC_RXSTATE_WAIT && 2720 sc->dc_cdata.dc_tx_cnt == 0) 2721 mii_tick(mii); 2722 if (!(mii->mii_media_status & IFM_ACTIVE)) 2723 sc->dc_link = 0; 2724 } 2725 } else 2726 mii_tick(mii); 2727 2728 /* 2729 * When the init routine completes, we expect to be able to send 2730 * packets right away, and in fact the network code will send a 2731 * gratuitous ARP the moment the init routine marks the interface 2732 * as running. However, even though the MAC may have been initialized, 2733 * there may be a delay of a few seconds before the PHY completes 2734 * autonegotiation and the link is brought up. Any transmissions 2735 * made during that delay will be lost. Dealing with this is tricky: 2736 * we can't just pause in the init routine while waiting for the 2737 * PHY to come ready since that would bring the whole system to 2738 * a screeching halt for several seconds. 2739 * 2740 * What we do here is prevent the TX start routine from sending 2741 * any packets until a link has been established. After the 2742 * interface has been initialized, the tick routine will poll 2743 * the state of the PHY until the IFM_ACTIVE flag is set. Until 2744 * that time, packets will stay in the send queue, and once the 2745 * link comes up, they will be flushed out to the wire. 2746 */ 2747 if (!sc->dc_link && mii->mii_media_status & IFM_ACTIVE && 2748 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) { 2749 sc->dc_link++; 2750 if (ifp->if_snd.ifq_head != NULL) 2751 dc_start(ifp); 2752 } 2753 2754 if (sc->dc_flags & DC_21143_NWAY && !sc->dc_link) 2755 callout_reset(&sc->dc_stat_ch, hz/10, dc_tick, sc); 2756 else 2757 callout_reset(&sc->dc_stat_ch, hz, dc_tick, sc); 2758 2759 DC_UNLOCK(sc); 2760 2761 return; 2762 } 2763 2764 /* 2765 * A transmit underrun has occurred. Back off the transmit threshold, 2766 * or switch to store and forward mode if we have to. 2767 */ 2768 static void dc_tx_underrun(sc) 2769 struct dc_softc *sc; 2770 { 2771 u_int32_t isr; 2772 int i; 2773 2774 if (DC_IS_DAVICOM(sc)) 2775 dc_init(sc); 2776 2777 if (DC_IS_INTEL(sc)) { 2778 /* 2779 * The real 21143 requires that the transmitter be idle 2780 * in order to change the transmit threshold or store 2781 * and forward state. 2782 */ 2783 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_TX_ON); 2784 2785 for (i = 0; i < DC_TIMEOUT; i++) { 2786 isr = CSR_READ_4(sc, DC_ISR); 2787 if (isr & DC_ISR_TX_IDLE) 2788 break; 2789 DELAY(10); 2790 } 2791 if (i == DC_TIMEOUT) { 2792 printf("dc%d: failed to force tx to idle state\n", 2793 sc->dc_unit); 2794 dc_init(sc); 2795 } 2796 } 2797 2798 printf("dc%d: TX underrun -- ", sc->dc_unit); 2799 sc->dc_txthresh += DC_TXTHRESH_INC; 2800 if (sc->dc_txthresh > DC_TXTHRESH_MAX) { 2801 printf("using store and forward mode\n"); 2802 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_STORENFWD); 2803 } else { 2804 printf("increasing TX threshold\n"); 2805 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_TX_THRESH); 2806 DC_SETBIT(sc, DC_NETCFG, sc->dc_txthresh); 2807 } 2808 2809 if (DC_IS_INTEL(sc)) 2810 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_TX_ON); 2811 2812 return; 2813 } 2814 2815 #ifdef DEVICE_POLLING 2816 static poll_handler_t dc_poll; 2817 2818 static void 2819 dc_poll(struct ifnet *ifp, enum poll_cmd cmd, int count) 2820 { 2821 struct dc_softc *sc = ifp->if_softc; 2822 2823 if (cmd == POLL_DEREGISTER) { /* final call, enable interrupts */ 2824 /* Re-enable interrupts. */ 2825 CSR_WRITE_4(sc, DC_IMR, DC_INTRS); 2826 return; 2827 } 2828 sc->rxcycles = count; 2829 dc_rxeof(sc); 2830 dc_txeof(sc); 2831 if (ifp->if_snd.ifq_head != NULL && !(ifp->if_flags & IFF_OACTIVE)) 2832 dc_start(ifp); 2833 2834 if (cmd == POLL_AND_CHECK_STATUS) { /* also check status register */ 2835 u_int32_t status; 2836 2837 status = CSR_READ_4(sc, DC_ISR); 2838 status &= (DC_ISR_RX_WATDOGTIMEO|DC_ISR_RX_NOBUF| 2839 DC_ISR_TX_NOBUF|DC_ISR_TX_IDLE|DC_ISR_TX_UNDERRUN| 2840 DC_ISR_BUS_ERR); 2841 if (!status) 2842 return; 2843 /* ack what we have */ 2844 CSR_WRITE_4(sc, DC_ISR, status); 2845 2846 if (status & (DC_ISR_RX_WATDOGTIMEO|DC_ISR_RX_NOBUF)) { 2847 u_int32_t r = CSR_READ_4(sc, DC_FRAMESDISCARDED); 2848 ifp->if_ierrors += (r & 0xffff) + ((r >> 17) & 0x7ff); 2849 2850 if (dc_rx_resync(sc)) 2851 dc_rxeof(sc); 2852 } 2853 /* restart transmit unit if necessary */ 2854 if (status & DC_ISR_TX_IDLE && sc->dc_cdata.dc_tx_cnt) 2855 CSR_WRITE_4(sc, DC_TXSTART, 0xFFFFFFFF); 2856 2857 if (status & DC_ISR_TX_UNDERRUN) 2858 dc_tx_underrun(sc); 2859 2860 if (status & DC_ISR_BUS_ERR) { 2861 printf("dc_poll: dc%d bus error\n", sc->dc_unit); 2862 dc_reset(sc); 2863 dc_init(sc); 2864 } 2865 } 2866 } 2867 #endif /* DEVICE_POLLING */ 2868 2869 static void dc_intr(arg) 2870 void *arg; 2871 { 2872 struct dc_softc *sc; 2873 struct ifnet *ifp; 2874 u_int32_t status; 2875 2876 sc = arg; 2877 2878 if (sc->suspended) { 2879 return; 2880 } 2881 2882 if ((CSR_READ_4(sc, DC_ISR) & DC_INTRS) == 0) 2883 return; 2884 2885 DC_LOCK(sc); 2886 ifp = &sc->arpcom.ac_if; 2887 #ifdef DEVICE_POLLING 2888 if (ifp->if_flags & IFF_POLLING) 2889 goto done; 2890 if (ether_poll_register(dc_poll, ifp)) { /* ok, disable interrupts */ 2891 CSR_WRITE_4(sc, DC_IMR, 0x00000000); 2892 goto done; 2893 } 2894 #endif /* DEVICE_POLLING */ 2895 2896 /* Suppress unwanted interrupts */ 2897 if (!(ifp->if_flags & IFF_UP)) { 2898 if (CSR_READ_4(sc, DC_ISR) & DC_INTRS) 2899 dc_stop(sc); 2900 DC_UNLOCK(sc); 2901 return; 2902 } 2903 2904 /* Disable interrupts. */ 2905 CSR_WRITE_4(sc, DC_IMR, 0x00000000); 2906 2907 while(((status = CSR_READ_4(sc, DC_ISR)) & DC_INTRS) 2908 && status != 0xFFFFFFFF) { 2909 2910 CSR_WRITE_4(sc, DC_ISR, status); 2911 2912 if (status & DC_ISR_RX_OK) { 2913 int curpkts; 2914 curpkts = ifp->if_ipackets; 2915 dc_rxeof(sc); 2916 if (curpkts == ifp->if_ipackets) { 2917 while(dc_rx_resync(sc)) 2918 dc_rxeof(sc); 2919 } 2920 } 2921 2922 if (status & (DC_ISR_TX_OK|DC_ISR_TX_NOBUF)) 2923 dc_txeof(sc); 2924 2925 if (status & DC_ISR_TX_IDLE) { 2926 dc_txeof(sc); 2927 if (sc->dc_cdata.dc_tx_cnt) { 2928 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_TX_ON); 2929 CSR_WRITE_4(sc, DC_TXSTART, 0xFFFFFFFF); 2930 } 2931 } 2932 2933 if (status & DC_ISR_TX_UNDERRUN) 2934 dc_tx_underrun(sc); 2935 2936 if ((status & DC_ISR_RX_WATDOGTIMEO) 2937 || (status & DC_ISR_RX_NOBUF)) { 2938 int curpkts; 2939 curpkts = ifp->if_ipackets; 2940 dc_rxeof(sc); 2941 if (curpkts == ifp->if_ipackets) { 2942 while(dc_rx_resync(sc)) 2943 dc_rxeof(sc); 2944 } 2945 } 2946 2947 if (status & DC_ISR_BUS_ERR) { 2948 dc_reset(sc); 2949 dc_init(sc); 2950 } 2951 } 2952 2953 /* Re-enable interrupts. */ 2954 CSR_WRITE_4(sc, DC_IMR, DC_INTRS); 2955 2956 if (ifp->if_snd.ifq_head != NULL) 2957 dc_start(ifp); 2958 2959 #ifdef DEVICE_POLLING 2960 done: 2961 #endif /* DEVICE_POLLING */ 2962 2963 DC_UNLOCK(sc); 2964 2965 return; 2966 } 2967 2968 /* 2969 * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data 2970 * pointers to the fragment pointers. 2971 */ 2972 static int dc_encap(sc, m_head, txidx) 2973 struct dc_softc *sc; 2974 struct mbuf *m_head; 2975 u_int32_t *txidx; 2976 { 2977 struct dc_desc *f = NULL; 2978 struct mbuf *m; 2979 int frag, cur, cnt = 0; 2980 2981 /* 2982 * Start packing the mbufs in this chain into 2983 * the fragment pointers. Stop when we run out 2984 * of fragments or hit the end of the mbuf chain. 2985 */ 2986 m = m_head; 2987 cur = frag = *txidx; 2988 2989 for (m = m_head; m != NULL; m = m->m_next) { 2990 if (m->m_len != 0) { 2991 if (sc->dc_flags & DC_TX_ADMTEK_WAR) { 2992 if (*txidx != sc->dc_cdata.dc_tx_prod && 2993 frag == (DC_TX_LIST_CNT - 1)) 2994 return(ENOBUFS); 2995 } 2996 if ((DC_TX_LIST_CNT - 2997 (sc->dc_cdata.dc_tx_cnt + cnt)) < 5) 2998 return(ENOBUFS); 2999 3000 f = &sc->dc_ldata->dc_tx_list[frag]; 3001 f->dc_ctl = DC_TXCTL_TLINK | m->m_len; 3002 if (cnt == 0) { 3003 f->dc_status = 0; 3004 f->dc_ctl |= DC_TXCTL_FIRSTFRAG; 3005 } else 3006 f->dc_status = DC_TXSTAT_OWN; 3007 f->dc_data = vtophys(mtod(m, vm_offset_t)); 3008 cur = frag; 3009 DC_INC(frag, DC_TX_LIST_CNT); 3010 cnt++; 3011 } 3012 } 3013 3014 if (m != NULL) 3015 return(ENOBUFS); 3016 3017 sc->dc_cdata.dc_tx_cnt += cnt; 3018 sc->dc_cdata.dc_tx_chain[cur] = m_head; 3019 sc->dc_ldata->dc_tx_list[cur].dc_ctl |= DC_TXCTL_LASTFRAG; 3020 if (sc->dc_flags & DC_TX_INTR_FIRSTFRAG) 3021 sc->dc_ldata->dc_tx_list[*txidx].dc_ctl |= DC_TXCTL_FINT; 3022 if (sc->dc_flags & DC_TX_INTR_ALWAYS) 3023 sc->dc_ldata->dc_tx_list[cur].dc_ctl |= DC_TXCTL_FINT; 3024 if (sc->dc_flags & DC_TX_USE_TX_INTR && sc->dc_cdata.dc_tx_cnt > 64) 3025 sc->dc_ldata->dc_tx_list[cur].dc_ctl |= DC_TXCTL_FINT; 3026 sc->dc_ldata->dc_tx_list[*txidx].dc_status = DC_TXSTAT_OWN; 3027 *txidx = frag; 3028 3029 return(0); 3030 } 3031 3032 /* 3033 * Coalesce an mbuf chain into a single mbuf cluster buffer. 3034 * Needed for some really badly behaved chips that just can't 3035 * do scatter/gather correctly. 3036 */ 3037 static int dc_coal(sc, m_head) 3038 struct dc_softc *sc; 3039 struct mbuf **m_head; 3040 { 3041 struct mbuf *m_new, *m; 3042 3043 m = *m_head; 3044 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 3045 if (m_new == NULL) 3046 return(ENOBUFS); 3047 if (m->m_pkthdr.len > MHLEN) { 3048 MCLGET(m_new, M_DONTWAIT); 3049 if (!(m_new->m_flags & M_EXT)) { 3050 m_freem(m_new); 3051 return(ENOBUFS); 3052 } 3053 } 3054 m_copydata(m, 0, m->m_pkthdr.len, mtod(m_new, caddr_t)); 3055 m_new->m_pkthdr.len = m_new->m_len = m->m_pkthdr.len; 3056 m_freem(m); 3057 *m_head = m_new; 3058 3059 return(0); 3060 } 3061 3062 /* 3063 * Main transmit routine. To avoid having to do mbuf copies, we put pointers 3064 * to the mbuf data regions directly in the transmit lists. We also save a 3065 * copy of the pointers since the transmit list fragment pointers are 3066 * physical addresses. 3067 */ 3068 3069 static void dc_start(ifp) 3070 struct ifnet *ifp; 3071 { 3072 struct dc_softc *sc; 3073 struct mbuf *m_head = NULL; 3074 int idx; 3075 3076 sc = ifp->if_softc; 3077 3078 DC_LOCK(sc); 3079 3080 if (!sc->dc_link && ifp->if_snd.ifq_len < 10) { 3081 DC_UNLOCK(sc); 3082 return; 3083 } 3084 3085 if (ifp->if_flags & IFF_OACTIVE) { 3086 DC_UNLOCK(sc); 3087 return; 3088 } 3089 3090 idx = sc->dc_cdata.dc_tx_prod; 3091 3092 while(sc->dc_cdata.dc_tx_chain[idx] == NULL) { 3093 IF_DEQUEUE(&ifp->if_snd, m_head); 3094 if (m_head == NULL) 3095 break; 3096 3097 if (sc->dc_flags & DC_TX_COALESCE && 3098 (m_head->m_next != NULL || 3099 sc->dc_flags & DC_TX_ALIGN)) { 3100 if (dc_coal(sc, &m_head)) { 3101 IF_PREPEND(&ifp->if_snd, m_head); 3102 ifp->if_flags |= IFF_OACTIVE; 3103 break; 3104 } 3105 } 3106 3107 if (dc_encap(sc, m_head, &idx)) { 3108 IF_PREPEND(&ifp->if_snd, m_head); 3109 ifp->if_flags |= IFF_OACTIVE; 3110 break; 3111 } 3112 3113 /* 3114 * If there's a BPF listener, bounce a copy of this frame 3115 * to him. 3116 */ 3117 if (ifp->if_bpf) 3118 bpf_mtap(ifp, m_head); 3119 3120 if (sc->dc_flags & DC_TX_ONE) { 3121 ifp->if_flags |= IFF_OACTIVE; 3122 break; 3123 } 3124 } 3125 3126 /* Transmit */ 3127 sc->dc_cdata.dc_tx_prod = idx; 3128 if (!(sc->dc_flags & DC_TX_POLL)) 3129 CSR_WRITE_4(sc, DC_TXSTART, 0xFFFFFFFF); 3130 3131 /* 3132 * Set a timeout in case the chip goes out to lunch. 3133 */ 3134 ifp->if_timer = 5; 3135 3136 DC_UNLOCK(sc); 3137 3138 return; 3139 } 3140 3141 static void dc_init(xsc) 3142 void *xsc; 3143 { 3144 struct dc_softc *sc = xsc; 3145 struct ifnet *ifp = &sc->arpcom.ac_if; 3146 struct mii_data *mii; 3147 3148 DC_LOCK(sc); 3149 3150 mii = device_get_softc(sc->dc_miibus); 3151 3152 /* 3153 * Cancel pending I/O and free all RX/TX buffers. 3154 */ 3155 dc_stop(sc); 3156 dc_reset(sc); 3157 3158 /* 3159 * Set cache alignment and burst length. 3160 */ 3161 if (DC_IS_ASIX(sc) || DC_IS_DAVICOM(sc)) 3162 CSR_WRITE_4(sc, DC_BUSCTL, 0); 3163 else 3164 CSR_WRITE_4(sc, DC_BUSCTL, DC_BUSCTL_MRME|DC_BUSCTL_MRLE); 3165 /* 3166 * Evenly share the bus between receive and transmit process. 3167 */ 3168 if (DC_IS_INTEL(sc)) 3169 DC_SETBIT(sc, DC_BUSCTL, DC_BUSCTL_ARBITRATION); 3170 if (DC_IS_DAVICOM(sc) || DC_IS_INTEL(sc)) { 3171 DC_SETBIT(sc, DC_BUSCTL, DC_BURSTLEN_USECA); 3172 } else { 3173 DC_SETBIT(sc, DC_BUSCTL, DC_BURSTLEN_16LONG); 3174 } 3175 if (sc->dc_flags & DC_TX_POLL) 3176 DC_SETBIT(sc, DC_BUSCTL, DC_TXPOLL_1); 3177 switch(sc->dc_cachesize) { 3178 case 32: 3179 DC_SETBIT(sc, DC_BUSCTL, DC_CACHEALIGN_32LONG); 3180 break; 3181 case 16: 3182 DC_SETBIT(sc, DC_BUSCTL, DC_CACHEALIGN_16LONG); 3183 break; 3184 case 8: 3185 DC_SETBIT(sc, DC_BUSCTL, DC_CACHEALIGN_8LONG); 3186 break; 3187 case 0: 3188 default: 3189 DC_SETBIT(sc, DC_BUSCTL, DC_CACHEALIGN_NONE); 3190 break; 3191 } 3192 3193 if (sc->dc_flags & DC_TX_STORENFWD) 3194 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_STORENFWD); 3195 else { 3196 if (sc->dc_txthresh > DC_TXTHRESH_MAX) { 3197 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_STORENFWD); 3198 } else { 3199 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_STORENFWD); 3200 DC_SETBIT(sc, DC_NETCFG, sc->dc_txthresh); 3201 } 3202 } 3203 3204 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_NO_RXCRC); 3205 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_TX_BACKOFF); 3206 3207 if (DC_IS_MACRONIX(sc) || DC_IS_PNICII(sc)) { 3208 /* 3209 * The app notes for the 98713 and 98715A say that 3210 * in order to have the chips operate properly, a magic 3211 * number must be written to CSR16. Macronix does not 3212 * document the meaning of these bits so there's no way 3213 * to know exactly what they do. The 98713 has a magic 3214 * number all its own; the rest all use a different one. 3215 */ 3216 DC_CLRBIT(sc, DC_MX_MAGICPACKET, 0xFFFF0000); 3217 if (sc->dc_type == DC_TYPE_98713) 3218 DC_SETBIT(sc, DC_MX_MAGICPACKET, DC_MX_MAGIC_98713); 3219 else 3220 DC_SETBIT(sc, DC_MX_MAGICPACKET, DC_MX_MAGIC_98715); 3221 } 3222 3223 if (DC_IS_XIRCOM(sc)) { 3224 /* 3225 * setup General Purpose Port mode and data so the tulip 3226 * can talk to the MII. 3227 */ 3228 CSR_WRITE_4(sc, DC_SIAGP, DC_SIAGP_WRITE_EN | DC_SIAGP_INT1_EN | 3229 DC_SIAGP_MD_GP2_OUTPUT | DC_SIAGP_MD_GP0_OUTPUT); 3230 DELAY(10); 3231 CSR_WRITE_4(sc, DC_SIAGP, DC_SIAGP_INT1_EN | 3232 DC_SIAGP_MD_GP2_OUTPUT | DC_SIAGP_MD_GP0_OUTPUT); 3233 DELAY(10); 3234 } 3235 3236 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_TX_THRESH); 3237 DC_SETBIT(sc, DC_NETCFG, DC_TXTHRESH_MIN); 3238 3239 /* Init circular RX list. */ 3240 if (dc_list_rx_init(sc) == ENOBUFS) { 3241 printf("dc%d: initialization failed: no " 3242 "memory for rx buffers\n", sc->dc_unit); 3243 dc_stop(sc); 3244 DC_UNLOCK(sc); 3245 return; 3246 } 3247 3248 /* 3249 * Init tx descriptors. 3250 */ 3251 dc_list_tx_init(sc); 3252 3253 /* 3254 * Load the address of the RX list. 3255 */ 3256 CSR_WRITE_4(sc, DC_RXADDR, vtophys(&sc->dc_ldata->dc_rx_list[0])); 3257 CSR_WRITE_4(sc, DC_TXADDR, vtophys(&sc->dc_ldata->dc_tx_list[0])); 3258 3259 /* 3260 * Enable interrupts. 3261 */ 3262 #ifdef DEVICE_POLLING 3263 /* 3264 * ... but only if we are not polling, and make sure they are off in 3265 * the case of polling. Some cards (e.g. fxp) turn interrupts on 3266 * after a reset. 3267 */ 3268 if (ifp->if_flags & IFF_POLLING) 3269 CSR_WRITE_4(sc, DC_IMR, 0x00000000); 3270 else 3271 #endif 3272 CSR_WRITE_4(sc, DC_IMR, DC_INTRS); 3273 CSR_WRITE_4(sc, DC_ISR, 0xFFFFFFFF); 3274 3275 /* Enable transmitter. */ 3276 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_TX_ON); 3277 3278 /* 3279 * If this is an Intel 21143 and we're not using the 3280 * MII port, program the LED control pins so we get 3281 * link and activity indications. 3282 */ 3283 if (sc->dc_flags & DC_TULIP_LEDS) { 3284 CSR_WRITE_4(sc, DC_WATCHDOG, 3285 DC_WDOG_CTLWREN|DC_WDOG_LINK|DC_WDOG_ACTIVITY); 3286 CSR_WRITE_4(sc, DC_WATCHDOG, 0); 3287 } 3288 3289 /* 3290 * Load the RX/multicast filter. We do this sort of late 3291 * because the filter programming scheme on the 21143 and 3292 * some clones requires DMAing a setup frame via the TX 3293 * engine, and we need the transmitter enabled for that. 3294 */ 3295 dc_setfilt(sc); 3296 3297 /* Enable receiver. */ 3298 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_ON); 3299 CSR_WRITE_4(sc, DC_RXSTART, 0xFFFFFFFF); 3300 3301 mii_mediachg(mii); 3302 dc_setcfg(sc, sc->dc_if_media); 3303 3304 ifp->if_flags |= IFF_RUNNING; 3305 ifp->if_flags &= ~IFF_OACTIVE; 3306 3307 /* Don't start the ticker if this is a homePNA link. */ 3308 if (IFM_SUBTYPE(mii->mii_media.ifm_media) == IFM_HPNA_1) 3309 sc->dc_link = 1; 3310 else { 3311 if (sc->dc_flags & DC_21143_NWAY) 3312 callout_reset(&sc->dc_stat_ch, hz/10, dc_tick, sc); 3313 else 3314 callout_reset(&sc->dc_stat_ch, hz, dc_tick, sc); 3315 } 3316 3317 #ifdef SRM_MEDIA 3318 if(sc->dc_srm_media) { 3319 struct ifreq ifr; 3320 3321 ifr.ifr_media = sc->dc_srm_media; 3322 ifmedia_ioctl(ifp, &ifr, &mii->mii_media, SIOCSIFMEDIA); 3323 sc->dc_srm_media = 0; 3324 } 3325 #endif 3326 DC_UNLOCK(sc); 3327 return; 3328 } 3329 3330 /* 3331 * Set media options. 3332 */ 3333 static int dc_ifmedia_upd(ifp) 3334 struct ifnet *ifp; 3335 { 3336 struct dc_softc *sc; 3337 struct mii_data *mii; 3338 struct ifmedia *ifm; 3339 3340 sc = ifp->if_softc; 3341 mii = device_get_softc(sc->dc_miibus); 3342 mii_mediachg(mii); 3343 ifm = &mii->mii_media; 3344 3345 if (DC_IS_DAVICOM(sc) && 3346 IFM_SUBTYPE(ifm->ifm_media) == IFM_HPNA_1) 3347 dc_setcfg(sc, ifm->ifm_media); 3348 else 3349 sc->dc_link = 0; 3350 3351 return(0); 3352 } 3353 3354 /* 3355 * Report current media status. 3356 */ 3357 static void dc_ifmedia_sts(ifp, ifmr) 3358 struct ifnet *ifp; 3359 struct ifmediareq *ifmr; 3360 { 3361 struct dc_softc *sc; 3362 struct mii_data *mii; 3363 struct ifmedia *ifm; 3364 3365 sc = ifp->if_softc; 3366 mii = device_get_softc(sc->dc_miibus); 3367 mii_pollstat(mii); 3368 ifm = &mii->mii_media; 3369 if (DC_IS_DAVICOM(sc)) { 3370 if (IFM_SUBTYPE(ifm->ifm_media) == IFM_HPNA_1) { 3371 ifmr->ifm_active = ifm->ifm_media; 3372 ifmr->ifm_status = 0; 3373 return; 3374 } 3375 } 3376 ifmr->ifm_active = mii->mii_media_active; 3377 ifmr->ifm_status = mii->mii_media_status; 3378 3379 return; 3380 } 3381 3382 static int dc_ioctl(ifp, command, data) 3383 struct ifnet *ifp; 3384 u_long command; 3385 caddr_t data; 3386 { 3387 struct dc_softc *sc = ifp->if_softc; 3388 struct ifreq *ifr = (struct ifreq *) data; 3389 struct mii_data *mii; 3390 int error = 0; 3391 3392 DC_LOCK(sc); 3393 3394 switch(command) { 3395 case SIOCSIFADDR: 3396 case SIOCGIFADDR: 3397 case SIOCSIFMTU: 3398 error = ether_ioctl(ifp, command, data); 3399 break; 3400 case SIOCSIFFLAGS: 3401 if (ifp->if_flags & IFF_UP) { 3402 if (ifp->if_flags & IFF_RUNNING && 3403 ifp->if_flags & IFF_PROMISC && 3404 !(sc->dc_if_flags & IFF_PROMISC)) { 3405 dc_setfilt(sc); 3406 } else if (ifp->if_flags & IFF_RUNNING && 3407 !(ifp->if_flags & IFF_PROMISC) && 3408 sc->dc_if_flags & IFF_PROMISC) { 3409 dc_setfilt(sc); 3410 } else if (!(ifp->if_flags & IFF_RUNNING)) { 3411 sc->dc_txthresh = 0; 3412 dc_init(sc); 3413 } 3414 } else { 3415 if (ifp->if_flags & IFF_RUNNING) 3416 dc_stop(sc); 3417 } 3418 sc->dc_if_flags = ifp->if_flags; 3419 error = 0; 3420 break; 3421 case SIOCADDMULTI: 3422 case SIOCDELMULTI: 3423 dc_setfilt(sc); 3424 error = 0; 3425 break; 3426 case SIOCGIFMEDIA: 3427 case SIOCSIFMEDIA: 3428 mii = device_get_softc(sc->dc_miibus); 3429 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 3430 #ifdef SRM_MEDIA 3431 if (sc->dc_srm_media) 3432 sc->dc_srm_media = 0; 3433 #endif 3434 break; 3435 default: 3436 error = EINVAL; 3437 break; 3438 } 3439 3440 DC_UNLOCK(sc); 3441 3442 return(error); 3443 } 3444 3445 static void dc_watchdog(ifp) 3446 struct ifnet *ifp; 3447 { 3448 struct dc_softc *sc; 3449 3450 sc = ifp->if_softc; 3451 3452 DC_LOCK(sc); 3453 3454 ifp->if_oerrors++; 3455 printf("dc%d: watchdog timeout\n", sc->dc_unit); 3456 3457 dc_stop(sc); 3458 dc_reset(sc); 3459 dc_init(sc); 3460 3461 if (ifp->if_snd.ifq_head != NULL) 3462 dc_start(ifp); 3463 3464 DC_UNLOCK(sc); 3465 3466 return; 3467 } 3468 3469 /* 3470 * Stop the adapter and free any mbufs allocated to the 3471 * RX and TX lists. 3472 */ 3473 static void dc_stop(sc) 3474 struct dc_softc *sc; 3475 { 3476 register int i; 3477 struct ifnet *ifp; 3478 3479 DC_LOCK(sc); 3480 3481 ifp = &sc->arpcom.ac_if; 3482 ifp->if_timer = 0; 3483 3484 callout_stop(&sc->dc_stat_ch); 3485 3486 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 3487 #ifdef DEVICE_POLLING 3488 ether_poll_deregister(ifp); 3489 #endif 3490 3491 DC_CLRBIT(sc, DC_NETCFG, (DC_NETCFG_RX_ON|DC_NETCFG_TX_ON)); 3492 CSR_WRITE_4(sc, DC_IMR, 0x00000000); 3493 CSR_WRITE_4(sc, DC_TXADDR, 0x00000000); 3494 CSR_WRITE_4(sc, DC_RXADDR, 0x00000000); 3495 sc->dc_link = 0; 3496 3497 /* 3498 * Free data in the RX lists. 3499 */ 3500 for (i = 0; i < DC_RX_LIST_CNT; i++) { 3501 if (sc->dc_cdata.dc_rx_chain[i] != NULL) { 3502 m_freem(sc->dc_cdata.dc_rx_chain[i]); 3503 sc->dc_cdata.dc_rx_chain[i] = NULL; 3504 } 3505 } 3506 bzero((char *)&sc->dc_ldata->dc_rx_list, 3507 sizeof(sc->dc_ldata->dc_rx_list)); 3508 3509 /* 3510 * Free the TX list buffers. 3511 */ 3512 for (i = 0; i < DC_TX_LIST_CNT; i++) { 3513 if (sc->dc_cdata.dc_tx_chain[i] != NULL) { 3514 if (sc->dc_ldata->dc_tx_list[i].dc_ctl & 3515 DC_TXCTL_SETUP) { 3516 sc->dc_cdata.dc_tx_chain[i] = NULL; 3517 continue; 3518 } 3519 m_freem(sc->dc_cdata.dc_tx_chain[i]); 3520 sc->dc_cdata.dc_tx_chain[i] = NULL; 3521 } 3522 } 3523 3524 bzero((char *)&sc->dc_ldata->dc_tx_list, 3525 sizeof(sc->dc_ldata->dc_tx_list)); 3526 3527 DC_UNLOCK(sc); 3528 3529 return; 3530 } 3531 3532 /* 3533 * Device suspend routine. Stop the interface and save some PCI 3534 * settings in case the BIOS doesn't restore them properly on 3535 * resume. 3536 */ 3537 static int dc_suspend(dev) 3538 device_t dev; 3539 { 3540 register int i; 3541 int s; 3542 struct dc_softc *sc; 3543 3544 s = splimp(); 3545 3546 sc = device_get_softc(dev); 3547 3548 dc_stop(sc); 3549 3550 for (i = 0; i < 5; i++) 3551 sc->saved_maps[i] = pci_read_config(dev, PCIR_MAPS + i * 4, 4); 3552 sc->saved_biosaddr = pci_read_config(dev, PCIR_BIOS, 4); 3553 sc->saved_intline = pci_read_config(dev, PCIR_INTLINE, 1); 3554 sc->saved_cachelnsz = pci_read_config(dev, PCIR_CACHELNSZ, 1); 3555 sc->saved_lattimer = pci_read_config(dev, PCIR_LATTIMER, 1); 3556 3557 sc->suspended = 1; 3558 3559 splx(s); 3560 return (0); 3561 } 3562 3563 /* 3564 * Device resume routine. Restore some PCI settings in case the BIOS 3565 * doesn't, re-enable busmastering, and restart the interface if 3566 * appropriate. 3567 */ 3568 static int dc_resume(dev) 3569 device_t dev; 3570 { 3571 register int i; 3572 int s; 3573 struct dc_softc *sc; 3574 struct ifnet *ifp; 3575 3576 s = splimp(); 3577 3578 sc = device_get_softc(dev); 3579 ifp = &sc->arpcom.ac_if; 3580 3581 dc_acpi(dev); 3582 3583 /* better way to do this? */ 3584 for (i = 0; i < 5; i++) 3585 pci_write_config(dev, PCIR_MAPS + i * 4, sc->saved_maps[i], 4); 3586 pci_write_config(dev, PCIR_BIOS, sc->saved_biosaddr, 4); 3587 pci_write_config(dev, PCIR_INTLINE, sc->saved_intline, 1); 3588 pci_write_config(dev, PCIR_CACHELNSZ, sc->saved_cachelnsz, 1); 3589 pci_write_config(dev, PCIR_LATTIMER, sc->saved_lattimer, 1); 3590 3591 /* reenable busmastering */ 3592 pci_enable_busmaster(dev); 3593 pci_enable_io(dev, DC_RES); 3594 3595 /* reinitialize interface if necessary */ 3596 if (ifp->if_flags & IFF_UP) 3597 dc_init(sc); 3598 3599 sc->suspended = 0; 3600 3601 splx(s); 3602 return (0); 3603 } 3604 3605 /* 3606 * Stop all chip I/O so that the kernel's probe routines don't 3607 * get confused by errant DMAs when rebooting. 3608 */ 3609 static void dc_shutdown(dev) 3610 device_t dev; 3611 { 3612 struct dc_softc *sc; 3613 3614 sc = device_get_softc(dev); 3615 3616 dc_stop(sc); 3617 3618 return; 3619 } 3620