1 /* 2 * Copyright (c) 1997, 1998, 1999 3 * Bill Paul <wpaul@ee.columbia.edu>. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 3. All advertising materials mentioning features or use of this software 14 * must display the following acknowledgement: 15 * This product includes software developed by Bill Paul. 16 * 4. Neither the name of the author nor the names of any co-contributors 17 * may be used to endorse or promote products derived from this software 18 * without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30 * THE POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33 #include <sys/cdefs.h> 34 __FBSDID("$FreeBSD$"); 35 36 /* 37 * DEC "tulip" clone ethernet driver. Supports the DEC/Intel 21143 38 * series chips and several workalikes including the following: 39 * 40 * Macronix 98713/98715/98725/98727/98732 PMAC (www.macronix.com) 41 * Macronix/Lite-On 82c115 PNIC II (www.macronix.com) 42 * Lite-On 82c168/82c169 PNIC (www.litecom.com) 43 * ASIX Electronics AX88140A (www.asix.com.tw) 44 * ASIX Electronics AX88141 (www.asix.com.tw) 45 * ADMtek AL981 (www.admtek.com.tw) 46 * ADMtek AN985 (www.admtek.com.tw) 47 * Netgear FA511 (www.netgear.com) Appears to be rebadged ADMTek AN985 48 * Davicom DM9100, DM9102, DM9102A (www.davicom8.com) 49 * Accton EN1217 (www.accton.com) 50 * Xircom X3201 (www.xircom.com) 51 * Abocom FE2500 52 * Conexant LANfinity (www.conexant.com) 53 * 3Com OfficeConnect 10/100B 3CSOHO100B (www.3com.com) 54 * 55 * Datasheets for the 21143 are available at developer.intel.com. 56 * Datasheets for the clone parts can be found at their respective sites. 57 * (Except for the PNIC; see www.freebsd.org/~wpaul/PNIC/pnic.ps.gz.) 58 * The PNIC II is essentially a Macronix 98715A chip; the only difference 59 * worth noting is that its multicast hash table is only 128 bits wide 60 * instead of 512. 61 * 62 * Written by Bill Paul <wpaul@ee.columbia.edu> 63 * Electrical Engineering Department 64 * Columbia University, New York City 65 */ 66 /* 67 * The Intel 21143 is the successor to the DEC 21140. It is basically 68 * the same as the 21140 but with a few new features. The 21143 supports 69 * three kinds of media attachments: 70 * 71 * o MII port, for 10Mbps and 100Mbps support and NWAY 72 * autonegotiation provided by an external PHY. 73 * o SYM port, for symbol mode 100Mbps support. 74 * o 10baseT port. 75 * o AUI/BNC port. 76 * 77 * The 100Mbps SYM port and 10baseT port can be used together in 78 * combination with the internal NWAY support to create a 10/100 79 * autosensing configuration. 80 * 81 * Note that not all tulip workalikes are handled in this driver: we only 82 * deal with those which are relatively well behaved. The Winbond is 83 * handled separately due to its different register offsets and the 84 * special handling needed for its various bugs. The PNIC is handled 85 * here, but I'm not thrilled about it. 86 * 87 * All of the workalike chips use some form of MII transceiver support 88 * with the exception of the Macronix chips, which also have a SYM port. 89 * The ASIX AX88140A is also documented to have a SYM port, but all 90 * the cards I've seen use an MII transceiver, probably because the 91 * AX88140A doesn't support internal NWAY. 92 */ 93 94 #include <sys/param.h> 95 #include <sys/endian.h> 96 #include <sys/systm.h> 97 #include <sys/sockio.h> 98 #include <sys/mbuf.h> 99 #include <sys/malloc.h> 100 #include <sys/kernel.h> 101 #include <sys/module.h> 102 #include <sys/socket.h> 103 #include <sys/sysctl.h> 104 105 #include <net/if.h> 106 #include <net/if_arp.h> 107 #include <net/ethernet.h> 108 #include <net/if_dl.h> 109 #include <net/if_media.h> 110 #include <net/if_types.h> 111 #include <net/if_vlan_var.h> 112 113 #include <net/bpf.h> 114 115 #include <machine/bus_pio.h> 116 #include <machine/bus_memio.h> 117 #include <machine/bus.h> 118 #include <machine/resource.h> 119 #include <sys/bus.h> 120 #include <sys/rman.h> 121 122 #include <dev/mii/mii.h> 123 #include <dev/mii/miivar.h> 124 125 #include <dev/pci/pcireg.h> 126 #include <dev/pci/pcivar.h> 127 128 #define DC_USEIOSPACE 129 #ifdef __alpha__ 130 #define SRM_MEDIA 131 #endif 132 133 #include <pci/if_dcreg.h> 134 135 #ifdef __sparc64__ 136 #include <dev/ofw/openfirm.h> 137 #include <machine/ofw_machdep.h> 138 #endif 139 140 MODULE_DEPEND(dc, pci, 1, 1, 1); 141 MODULE_DEPEND(dc, ether, 1, 1, 1); 142 MODULE_DEPEND(dc, miibus, 1, 1, 1); 143 144 /* "controller miibus0" required. See GENERIC if you get errors here. */ 145 #include "miibus_if.h" 146 147 /* 148 * Various supported device vendors/types and their names. 149 */ 150 static struct dc_type dc_devs[] = { 151 { DC_VENDORID_DEC, DC_DEVICEID_21143, 152 "Intel 21143 10/100BaseTX" }, 153 { DC_VENDORID_DAVICOM, DC_DEVICEID_DM9009, 154 "Davicom DM9009 10/100BaseTX" }, 155 { DC_VENDORID_DAVICOM, DC_DEVICEID_DM9100, 156 "Davicom DM9100 10/100BaseTX" }, 157 { DC_VENDORID_DAVICOM, DC_DEVICEID_DM9102, 158 "Davicom DM9102 10/100BaseTX" }, 159 { DC_VENDORID_DAVICOM, DC_DEVICEID_DM9102, 160 "Davicom DM9102A 10/100BaseTX" }, 161 { DC_VENDORID_ADMTEK, DC_DEVICEID_AL981, 162 "ADMtek AL981 10/100BaseTX" }, 163 { DC_VENDORID_ADMTEK, DC_DEVICEID_AN985, 164 "ADMtek AN985 10/100BaseTX" }, 165 { DC_VENDORID_ADMTEK, DC_DEVICEID_ADM9511, 166 "ADMtek ADM9511 10/100BaseTX" }, 167 { DC_VENDORID_ADMTEK, DC_DEVICEID_ADM9513, 168 "ADMtek ADM9513 10/100BaseTX" }, 169 { DC_VENDORID_ADMTEK, DC_DEVICEID_FA511, 170 "Netgear FA511 10/100BaseTX" }, 171 { DC_VENDORID_ASIX, DC_DEVICEID_AX88140A, 172 "ASIX AX88140A 10/100BaseTX" }, 173 { DC_VENDORID_ASIX, DC_DEVICEID_AX88140A, 174 "ASIX AX88141 10/100BaseTX" }, 175 { DC_VENDORID_MX, DC_DEVICEID_98713, 176 "Macronix 98713 10/100BaseTX" }, 177 { DC_VENDORID_MX, DC_DEVICEID_98713, 178 "Macronix 98713A 10/100BaseTX" }, 179 { DC_VENDORID_CP, DC_DEVICEID_98713_CP, 180 "Compex RL100-TX 10/100BaseTX" }, 181 { DC_VENDORID_CP, DC_DEVICEID_98713_CP, 182 "Compex RL100-TX 10/100BaseTX" }, 183 { DC_VENDORID_MX, DC_DEVICEID_987x5, 184 "Macronix 98715/98715A 10/100BaseTX" }, 185 { DC_VENDORID_MX, DC_DEVICEID_987x5, 186 "Macronix 98715AEC-C 10/100BaseTX" }, 187 { DC_VENDORID_MX, DC_DEVICEID_987x5, 188 "Macronix 98725 10/100BaseTX" }, 189 { DC_VENDORID_MX, DC_DEVICEID_98727, 190 "Macronix 98727/98732 10/100BaseTX" }, 191 { DC_VENDORID_LO, DC_DEVICEID_82C115, 192 "LC82C115 PNIC II 10/100BaseTX" }, 193 { DC_VENDORID_LO, DC_DEVICEID_82C168, 194 "82c168 PNIC 10/100BaseTX" }, 195 { DC_VENDORID_LO, DC_DEVICEID_82C168, 196 "82c169 PNIC 10/100BaseTX" }, 197 { DC_VENDORID_ACCTON, DC_DEVICEID_EN1217, 198 "Accton EN1217 10/100BaseTX" }, 199 { DC_VENDORID_ACCTON, DC_DEVICEID_EN2242, 200 "Accton EN2242 MiniPCI 10/100BaseTX" }, 201 { DC_VENDORID_XIRCOM, DC_DEVICEID_X3201, 202 "Xircom X3201 10/100BaseTX" }, 203 { DC_VENDORID_ABOCOM, DC_DEVICEID_FE2500, 204 "Abocom FE2500 10/100BaseTX" }, 205 { DC_VENDORID_ABOCOM, DC_DEVICEID_FE2500MX, 206 "Abocom FE2500MX 10/100BaseTX" }, 207 { DC_VENDORID_CONEXANT, DC_DEVICEID_RS7112, 208 "Conexant LANfinity MiniPCI 10/100BaseTX" }, 209 { DC_VENDORID_HAWKING, DC_DEVICEID_HAWKING_PN672TX, 210 "Hawking CB102 CardBus 10/100" }, 211 { DC_VENDORID_PLANEX, DC_DEVICEID_FNW3602T, 212 "PlaneX FNW-3602-T CardBus 10/100" }, 213 { DC_VENDORID_3COM, DC_DEVICEID_3CSOHOB, 214 "3Com OfficeConnect 10/100B" }, 215 { DC_VENDORID_MICROSOFT, DC_DEVICEID_MSMN120, 216 "Microsoft MN-120 CardBus 10/100" }, 217 { DC_VENDORID_MICROSOFT, DC_DEVICEID_MSMN130, 218 "Microsoft MN-130 10/100" }, 219 { DC_VENDORID_MICROSOFT, DC_DEVICEID_MSMN130_FAKE, 220 "Microsoft MN-130 10/100" }, 221 { 0, 0, NULL } 222 }; 223 224 static int dc_probe (device_t); 225 static int dc_attach (device_t); 226 static int dc_detach (device_t); 227 static int dc_suspend (device_t); 228 static int dc_resume (device_t); 229 static struct dc_type *dc_devtype (device_t); 230 static int dc_newbuf (struct dc_softc *, int, int); 231 static int dc_encap (struct dc_softc *, struct mbuf **); 232 static void dc_pnic_rx_bug_war (struct dc_softc *, int); 233 static int dc_rx_resync (struct dc_softc *); 234 static void dc_rxeof (struct dc_softc *); 235 static void dc_txeof (struct dc_softc *); 236 static void dc_tick (void *); 237 static void dc_tx_underrun (struct dc_softc *); 238 static void dc_intr (void *); 239 static void dc_start (struct ifnet *); 240 static int dc_ioctl (struct ifnet *, u_long, caddr_t); 241 static void dc_init (void *); 242 static void dc_stop (struct dc_softc *); 243 static void dc_watchdog (struct ifnet *); 244 static void dc_shutdown (device_t); 245 static int dc_ifmedia_upd (struct ifnet *); 246 static void dc_ifmedia_sts (struct ifnet *, struct ifmediareq *); 247 248 static void dc_delay (struct dc_softc *); 249 static void dc_eeprom_idle (struct dc_softc *); 250 static void dc_eeprom_putbyte (struct dc_softc *, int); 251 static void dc_eeprom_getword (struct dc_softc *, int, u_int16_t *); 252 static void dc_eeprom_getword_pnic 253 (struct dc_softc *, int, u_int16_t *); 254 static void dc_eeprom_getword_xircom 255 (struct dc_softc *, int, u_int16_t *); 256 static void dc_eeprom_width (struct dc_softc *); 257 static void dc_read_eeprom (struct dc_softc *, caddr_t, int, int, int); 258 259 static void dc_mii_writebit (struct dc_softc *, int); 260 static int dc_mii_readbit (struct dc_softc *); 261 static void dc_mii_sync (struct dc_softc *); 262 static void dc_mii_send (struct dc_softc *, u_int32_t, int); 263 static int dc_mii_readreg (struct dc_softc *, struct dc_mii_frame *); 264 static int dc_mii_writereg (struct dc_softc *, struct dc_mii_frame *); 265 static int dc_miibus_readreg (device_t, int, int); 266 static int dc_miibus_writereg (device_t, int, int, int); 267 static void dc_miibus_statchg (device_t); 268 static void dc_miibus_mediainit (device_t); 269 270 static void dc_setcfg (struct dc_softc *, int); 271 static uint32_t dc_mchash_le (struct dc_softc *, const uint8_t *); 272 static uint32_t dc_mchash_be (const uint8_t *); 273 static void dc_setfilt_21143 (struct dc_softc *); 274 static void dc_setfilt_asix (struct dc_softc *); 275 static void dc_setfilt_admtek (struct dc_softc *); 276 static void dc_setfilt_xircom (struct dc_softc *); 277 278 static void dc_setfilt (struct dc_softc *); 279 280 static void dc_reset (struct dc_softc *); 281 static int dc_list_rx_init (struct dc_softc *); 282 static int dc_list_tx_init (struct dc_softc *); 283 284 static void dc_read_srom (struct dc_softc *, int); 285 static void dc_parse_21143_srom (struct dc_softc *); 286 static void dc_decode_leaf_sia (struct dc_softc *, struct dc_eblock_sia *); 287 static void dc_decode_leaf_mii (struct dc_softc *, struct dc_eblock_mii *); 288 static void dc_decode_leaf_sym (struct dc_softc *, struct dc_eblock_sym *); 289 static void dc_apply_fixup (struct dc_softc *, int); 290 291 static void dc_dma_map_txbuf (void *, bus_dma_segment_t *, int, bus_size_t, 292 int); 293 static void dc_dma_map_rxbuf (void *, bus_dma_segment_t *, int, bus_size_t, 294 int); 295 296 #ifdef DC_USEIOSPACE 297 #define DC_RES SYS_RES_IOPORT 298 #define DC_RID DC_PCI_CFBIO 299 #else 300 #define DC_RES SYS_RES_MEMORY 301 #define DC_RID DC_PCI_CFBMA 302 #endif 303 304 static device_method_t dc_methods[] = { 305 /* Device interface */ 306 DEVMETHOD(device_probe, dc_probe), 307 DEVMETHOD(device_attach, dc_attach), 308 DEVMETHOD(device_detach, dc_detach), 309 DEVMETHOD(device_suspend, dc_suspend), 310 DEVMETHOD(device_resume, dc_resume), 311 DEVMETHOD(device_shutdown, dc_shutdown), 312 313 /* bus interface */ 314 DEVMETHOD(bus_print_child, bus_generic_print_child), 315 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 316 317 /* MII interface */ 318 DEVMETHOD(miibus_readreg, dc_miibus_readreg), 319 DEVMETHOD(miibus_writereg, dc_miibus_writereg), 320 DEVMETHOD(miibus_statchg, dc_miibus_statchg), 321 DEVMETHOD(miibus_mediainit, dc_miibus_mediainit), 322 323 { 0, 0 } 324 }; 325 326 static driver_t dc_driver = { 327 "dc", 328 dc_methods, 329 sizeof(struct dc_softc) 330 }; 331 332 static devclass_t dc_devclass; 333 #ifdef __i386__ 334 static int dc_quick = 1; 335 SYSCTL_INT(_hw, OID_AUTO, dc_quick, CTLFLAG_RW, &dc_quick, 0, 336 "do not m_devget() in dc driver"); 337 #endif 338 339 DRIVER_MODULE(dc, cardbus, dc_driver, dc_devclass, 0, 0); 340 DRIVER_MODULE(dc, pci, dc_driver, dc_devclass, 0, 0); 341 DRIVER_MODULE(miibus, dc, miibus_driver, miibus_devclass, 0, 0); 342 343 #define DC_SETBIT(sc, reg, x) \ 344 CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) | (x)) 345 346 #define DC_CLRBIT(sc, reg, x) \ 347 CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) & ~(x)) 348 349 #define SIO_SET(x) DC_SETBIT(sc, DC_SIO, (x)) 350 #define SIO_CLR(x) DC_CLRBIT(sc, DC_SIO, (x)) 351 352 #define IS_MPSAFE 0 353 354 static void 355 dc_delay(struct dc_softc *sc) 356 { 357 int idx; 358 359 for (idx = (300 / 33) + 1; idx > 0; idx--) 360 CSR_READ_4(sc, DC_BUSCTL); 361 } 362 363 static void 364 dc_eeprom_width(struct dc_softc *sc) 365 { 366 int i; 367 368 /* Force EEPROM to idle state. */ 369 dc_eeprom_idle(sc); 370 371 /* Enter EEPROM access mode. */ 372 CSR_WRITE_4(sc, DC_SIO, DC_SIO_EESEL); 373 dc_delay(sc); 374 DC_SETBIT(sc, DC_SIO, DC_SIO_ROMCTL_READ); 375 dc_delay(sc); 376 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); 377 dc_delay(sc); 378 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CS); 379 dc_delay(sc); 380 381 for (i = 3; i--;) { 382 if (6 & (1 << i)) 383 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_DATAIN); 384 else 385 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_DATAIN); 386 dc_delay(sc); 387 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CLK); 388 dc_delay(sc); 389 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); 390 dc_delay(sc); 391 } 392 393 for (i = 1; i <= 12; i++) { 394 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CLK); 395 dc_delay(sc); 396 if (!(CSR_READ_4(sc, DC_SIO) & DC_SIO_EE_DATAOUT)) { 397 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); 398 dc_delay(sc); 399 break; 400 } 401 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); 402 dc_delay(sc); 403 } 404 405 /* Turn off EEPROM access mode. */ 406 dc_eeprom_idle(sc); 407 408 if (i < 4 || i > 12) 409 sc->dc_romwidth = 6; 410 else 411 sc->dc_romwidth = i; 412 413 /* Enter EEPROM access mode. */ 414 CSR_WRITE_4(sc, DC_SIO, DC_SIO_EESEL); 415 dc_delay(sc); 416 DC_SETBIT(sc, DC_SIO, DC_SIO_ROMCTL_READ); 417 dc_delay(sc); 418 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); 419 dc_delay(sc); 420 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CS); 421 dc_delay(sc); 422 423 /* Turn off EEPROM access mode. */ 424 dc_eeprom_idle(sc); 425 } 426 427 static void 428 dc_eeprom_idle(struct dc_softc *sc) 429 { 430 int i; 431 432 CSR_WRITE_4(sc, DC_SIO, DC_SIO_EESEL); 433 dc_delay(sc); 434 DC_SETBIT(sc, DC_SIO, DC_SIO_ROMCTL_READ); 435 dc_delay(sc); 436 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); 437 dc_delay(sc); 438 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CS); 439 dc_delay(sc); 440 441 for (i = 0; i < 25; i++) { 442 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); 443 dc_delay(sc); 444 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CLK); 445 dc_delay(sc); 446 } 447 448 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); 449 dc_delay(sc); 450 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CS); 451 dc_delay(sc); 452 CSR_WRITE_4(sc, DC_SIO, 0x00000000); 453 } 454 455 /* 456 * Send a read command and address to the EEPROM, check for ACK. 457 */ 458 static void 459 dc_eeprom_putbyte(struct dc_softc *sc, int addr) 460 { 461 int d, i; 462 463 d = DC_EECMD_READ >> 6; 464 for (i = 3; i--; ) { 465 if (d & (1 << i)) 466 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_DATAIN); 467 else 468 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_DATAIN); 469 dc_delay(sc); 470 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CLK); 471 dc_delay(sc); 472 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); 473 dc_delay(sc); 474 } 475 476 /* 477 * Feed in each bit and strobe the clock. 478 */ 479 for (i = sc->dc_romwidth; i--;) { 480 if (addr & (1 << i)) { 481 SIO_SET(DC_SIO_EE_DATAIN); 482 } else { 483 SIO_CLR(DC_SIO_EE_DATAIN); 484 } 485 dc_delay(sc); 486 SIO_SET(DC_SIO_EE_CLK); 487 dc_delay(sc); 488 SIO_CLR(DC_SIO_EE_CLK); 489 dc_delay(sc); 490 } 491 } 492 493 /* 494 * Read a word of data stored in the EEPROM at address 'addr.' 495 * The PNIC 82c168/82c169 has its own non-standard way to read 496 * the EEPROM. 497 */ 498 static void 499 dc_eeprom_getword_pnic(struct dc_softc *sc, int addr, u_int16_t *dest) 500 { 501 int i; 502 u_int32_t r; 503 504 CSR_WRITE_4(sc, DC_PN_SIOCTL, DC_PN_EEOPCODE_READ | addr); 505 506 for (i = 0; i < DC_TIMEOUT; i++) { 507 DELAY(1); 508 r = CSR_READ_4(sc, DC_SIO); 509 if (!(r & DC_PN_SIOCTL_BUSY)) { 510 *dest = (u_int16_t)(r & 0xFFFF); 511 return; 512 } 513 } 514 } 515 516 /* 517 * Read a word of data stored in the EEPROM at address 'addr.' 518 * The Xircom X3201 has its own non-standard way to read 519 * the EEPROM, too. 520 */ 521 static void 522 dc_eeprom_getword_xircom(struct dc_softc *sc, int addr, u_int16_t *dest) 523 { 524 525 SIO_SET(DC_SIO_ROMSEL | DC_SIO_ROMCTL_READ); 526 527 addr *= 2; 528 CSR_WRITE_4(sc, DC_ROM, addr | 0x160); 529 *dest = (u_int16_t)CSR_READ_4(sc, DC_SIO) & 0xff; 530 addr += 1; 531 CSR_WRITE_4(sc, DC_ROM, addr | 0x160); 532 *dest |= ((u_int16_t)CSR_READ_4(sc, DC_SIO) & 0xff) << 8; 533 534 SIO_CLR(DC_SIO_ROMSEL | DC_SIO_ROMCTL_READ); 535 } 536 537 /* 538 * Read a word of data stored in the EEPROM at address 'addr.' 539 */ 540 static void 541 dc_eeprom_getword(struct dc_softc *sc, int addr, u_int16_t *dest) 542 { 543 int i; 544 u_int16_t word = 0; 545 546 /* Force EEPROM to idle state. */ 547 dc_eeprom_idle(sc); 548 549 /* Enter EEPROM access mode. */ 550 CSR_WRITE_4(sc, DC_SIO, DC_SIO_EESEL); 551 dc_delay(sc); 552 DC_SETBIT(sc, DC_SIO, DC_SIO_ROMCTL_READ); 553 dc_delay(sc); 554 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); 555 dc_delay(sc); 556 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CS); 557 dc_delay(sc); 558 559 /* 560 * Send address of word we want to read. 561 */ 562 dc_eeprom_putbyte(sc, addr); 563 564 /* 565 * Start reading bits from EEPROM. 566 */ 567 for (i = 0x8000; i; i >>= 1) { 568 SIO_SET(DC_SIO_EE_CLK); 569 dc_delay(sc); 570 if (CSR_READ_4(sc, DC_SIO) & DC_SIO_EE_DATAOUT) 571 word |= i; 572 dc_delay(sc); 573 SIO_CLR(DC_SIO_EE_CLK); 574 dc_delay(sc); 575 } 576 577 /* Turn off EEPROM access mode. */ 578 dc_eeprom_idle(sc); 579 580 *dest = word; 581 } 582 583 /* 584 * Read a sequence of words from the EEPROM. 585 */ 586 static void 587 dc_read_eeprom(struct dc_softc *sc, caddr_t dest, int off, int cnt, int swap) 588 { 589 int i; 590 u_int16_t word = 0, *ptr; 591 592 for (i = 0; i < cnt; i++) { 593 if (DC_IS_PNIC(sc)) 594 dc_eeprom_getword_pnic(sc, off + i, &word); 595 else if (DC_IS_XIRCOM(sc)) 596 dc_eeprom_getword_xircom(sc, off + i, &word); 597 else 598 dc_eeprom_getword(sc, off + i, &word); 599 ptr = (u_int16_t *)(dest + (i * 2)); 600 if (swap) 601 *ptr = ntohs(word); 602 else 603 *ptr = word; 604 } 605 } 606 607 /* 608 * The following two routines are taken from the Macronix 98713 609 * Application Notes pp.19-21. 610 */ 611 /* 612 * Write a bit to the MII bus. 613 */ 614 static void 615 dc_mii_writebit(struct dc_softc *sc, int bit) 616 { 617 618 if (bit) 619 CSR_WRITE_4(sc, DC_SIO, 620 DC_SIO_ROMCTL_WRITE | DC_SIO_MII_DATAOUT); 621 else 622 CSR_WRITE_4(sc, DC_SIO, DC_SIO_ROMCTL_WRITE); 623 624 DC_SETBIT(sc, DC_SIO, DC_SIO_MII_CLK); 625 DC_CLRBIT(sc, DC_SIO, DC_SIO_MII_CLK); 626 } 627 628 /* 629 * Read a bit from the MII bus. 630 */ 631 static int 632 dc_mii_readbit(struct dc_softc *sc) 633 { 634 635 CSR_WRITE_4(sc, DC_SIO, DC_SIO_ROMCTL_READ | DC_SIO_MII_DIR); 636 CSR_READ_4(sc, DC_SIO); 637 DC_SETBIT(sc, DC_SIO, DC_SIO_MII_CLK); 638 DC_CLRBIT(sc, DC_SIO, DC_SIO_MII_CLK); 639 if (CSR_READ_4(sc, DC_SIO) & DC_SIO_MII_DATAIN) 640 return (1); 641 642 return (0); 643 } 644 645 /* 646 * Sync the PHYs by setting data bit and strobing the clock 32 times. 647 */ 648 static void 649 dc_mii_sync(struct dc_softc *sc) 650 { 651 int i; 652 653 CSR_WRITE_4(sc, DC_SIO, DC_SIO_ROMCTL_WRITE); 654 655 for (i = 0; i < 32; i++) 656 dc_mii_writebit(sc, 1); 657 } 658 659 /* 660 * Clock a series of bits through the MII. 661 */ 662 static void 663 dc_mii_send(struct dc_softc *sc, u_int32_t bits, int cnt) 664 { 665 int i; 666 667 for (i = (0x1 << (cnt - 1)); i; i >>= 1) 668 dc_mii_writebit(sc, bits & i); 669 } 670 671 /* 672 * Read an PHY register through the MII. 673 */ 674 static int 675 dc_mii_readreg(struct dc_softc *sc, struct dc_mii_frame *frame) 676 { 677 int i, ack; 678 679 DC_LOCK(sc); 680 681 /* 682 * Set up frame for RX. 683 */ 684 frame->mii_stdelim = DC_MII_STARTDELIM; 685 frame->mii_opcode = DC_MII_READOP; 686 frame->mii_turnaround = 0; 687 frame->mii_data = 0; 688 689 /* 690 * Sync the PHYs. 691 */ 692 dc_mii_sync(sc); 693 694 /* 695 * Send command/address info. 696 */ 697 dc_mii_send(sc, frame->mii_stdelim, 2); 698 dc_mii_send(sc, frame->mii_opcode, 2); 699 dc_mii_send(sc, frame->mii_phyaddr, 5); 700 dc_mii_send(sc, frame->mii_regaddr, 5); 701 702 #ifdef notdef 703 /* Idle bit */ 704 dc_mii_writebit(sc, 1); 705 dc_mii_writebit(sc, 0); 706 #endif 707 708 /* Check for ack. */ 709 ack = dc_mii_readbit(sc); 710 711 /* 712 * Now try reading data bits. If the ack failed, we still 713 * need to clock through 16 cycles to keep the PHY(s) in sync. 714 */ 715 if (ack) { 716 for (i = 0; i < 16; i++) 717 dc_mii_readbit(sc); 718 goto fail; 719 } 720 721 for (i = 0x8000; i; i >>= 1) { 722 if (!ack) { 723 if (dc_mii_readbit(sc)) 724 frame->mii_data |= i; 725 } 726 } 727 728 fail: 729 730 dc_mii_writebit(sc, 0); 731 dc_mii_writebit(sc, 0); 732 733 DC_UNLOCK(sc); 734 735 if (ack) 736 return (1); 737 return (0); 738 } 739 740 /* 741 * Write to a PHY register through the MII. 742 */ 743 static int 744 dc_mii_writereg(struct dc_softc *sc, struct dc_mii_frame *frame) 745 { 746 747 DC_LOCK(sc); 748 /* 749 * Set up frame for TX. 750 */ 751 752 frame->mii_stdelim = DC_MII_STARTDELIM; 753 frame->mii_opcode = DC_MII_WRITEOP; 754 frame->mii_turnaround = DC_MII_TURNAROUND; 755 756 /* 757 * Sync the PHYs. 758 */ 759 dc_mii_sync(sc); 760 761 dc_mii_send(sc, frame->mii_stdelim, 2); 762 dc_mii_send(sc, frame->mii_opcode, 2); 763 dc_mii_send(sc, frame->mii_phyaddr, 5); 764 dc_mii_send(sc, frame->mii_regaddr, 5); 765 dc_mii_send(sc, frame->mii_turnaround, 2); 766 dc_mii_send(sc, frame->mii_data, 16); 767 768 /* Idle bit. */ 769 dc_mii_writebit(sc, 0); 770 dc_mii_writebit(sc, 0); 771 772 DC_UNLOCK(sc); 773 774 return (0); 775 } 776 777 static int 778 dc_miibus_readreg(device_t dev, int phy, int reg) 779 { 780 struct dc_mii_frame frame; 781 struct dc_softc *sc; 782 int i, rval, phy_reg = 0; 783 784 sc = device_get_softc(dev); 785 bzero(&frame, sizeof(frame)); 786 787 /* 788 * Note: both the AL981 and AN985 have internal PHYs, 789 * however the AL981 provides direct access to the PHY 790 * registers while the AN985 uses a serial MII interface. 791 * The AN985's MII interface is also buggy in that you 792 * can read from any MII address (0 to 31), but only address 1 793 * behaves normally. To deal with both cases, we pretend 794 * that the PHY is at MII address 1. 795 */ 796 if (DC_IS_ADMTEK(sc) && phy != DC_ADMTEK_PHYADDR) 797 return (0); 798 799 /* 800 * Note: the ukphy probes of the RS7112 report a PHY at 801 * MII address 0 (possibly HomePNA?) and 1 (ethernet) 802 * so we only respond to correct one. 803 */ 804 if (DC_IS_CONEXANT(sc) && phy != DC_CONEXANT_PHYADDR) 805 return (0); 806 807 if (sc->dc_pmode != DC_PMODE_MII) { 808 if (phy == (MII_NPHY - 1)) { 809 switch (reg) { 810 case MII_BMSR: 811 /* 812 * Fake something to make the probe 813 * code think there's a PHY here. 814 */ 815 return (BMSR_MEDIAMASK); 816 break; 817 case MII_PHYIDR1: 818 if (DC_IS_PNIC(sc)) 819 return (DC_VENDORID_LO); 820 return (DC_VENDORID_DEC); 821 break; 822 case MII_PHYIDR2: 823 if (DC_IS_PNIC(sc)) 824 return (DC_DEVICEID_82C168); 825 return (DC_DEVICEID_21143); 826 break; 827 default: 828 return (0); 829 break; 830 } 831 } else 832 return (0); 833 } 834 835 if (DC_IS_PNIC(sc)) { 836 CSR_WRITE_4(sc, DC_PN_MII, DC_PN_MIIOPCODE_READ | 837 (phy << 23) | (reg << 18)); 838 for (i = 0; i < DC_TIMEOUT; i++) { 839 DELAY(1); 840 rval = CSR_READ_4(sc, DC_PN_MII); 841 if (!(rval & DC_PN_MII_BUSY)) { 842 rval &= 0xFFFF; 843 return (rval == 0xFFFF ? 0 : rval); 844 } 845 } 846 return (0); 847 } 848 849 if (DC_IS_COMET(sc)) { 850 switch (reg) { 851 case MII_BMCR: 852 phy_reg = DC_AL_BMCR; 853 break; 854 case MII_BMSR: 855 phy_reg = DC_AL_BMSR; 856 break; 857 case MII_PHYIDR1: 858 phy_reg = DC_AL_VENID; 859 break; 860 case MII_PHYIDR2: 861 phy_reg = DC_AL_DEVID; 862 break; 863 case MII_ANAR: 864 phy_reg = DC_AL_ANAR; 865 break; 866 case MII_ANLPAR: 867 phy_reg = DC_AL_LPAR; 868 break; 869 case MII_ANER: 870 phy_reg = DC_AL_ANER; 871 break; 872 default: 873 printf("dc%d: phy_read: bad phy register %x\n", 874 sc->dc_unit, reg); 875 return (0); 876 break; 877 } 878 879 rval = CSR_READ_4(sc, phy_reg) & 0x0000FFFF; 880 881 if (rval == 0xFFFF) 882 return (0); 883 return (rval); 884 } 885 886 frame.mii_phyaddr = phy; 887 frame.mii_regaddr = reg; 888 if (sc->dc_type == DC_TYPE_98713) { 889 phy_reg = CSR_READ_4(sc, DC_NETCFG); 890 CSR_WRITE_4(sc, DC_NETCFG, phy_reg & ~DC_NETCFG_PORTSEL); 891 } 892 dc_mii_readreg(sc, &frame); 893 if (sc->dc_type == DC_TYPE_98713) 894 CSR_WRITE_4(sc, DC_NETCFG, phy_reg); 895 896 return (frame.mii_data); 897 } 898 899 static int 900 dc_miibus_writereg(device_t dev, int phy, int reg, int data) 901 { 902 struct dc_softc *sc; 903 struct dc_mii_frame frame; 904 int i, phy_reg = 0; 905 906 sc = device_get_softc(dev); 907 bzero(&frame, sizeof(frame)); 908 909 if (DC_IS_ADMTEK(sc) && phy != DC_ADMTEK_PHYADDR) 910 return (0); 911 912 if (DC_IS_CONEXANT(sc) && phy != DC_CONEXANT_PHYADDR) 913 return (0); 914 915 if (DC_IS_PNIC(sc)) { 916 CSR_WRITE_4(sc, DC_PN_MII, DC_PN_MIIOPCODE_WRITE | 917 (phy << 23) | (reg << 10) | data); 918 for (i = 0; i < DC_TIMEOUT; i++) { 919 if (!(CSR_READ_4(sc, DC_PN_MII) & DC_PN_MII_BUSY)) 920 break; 921 } 922 return (0); 923 } 924 925 if (DC_IS_COMET(sc)) { 926 switch (reg) { 927 case MII_BMCR: 928 phy_reg = DC_AL_BMCR; 929 break; 930 case MII_BMSR: 931 phy_reg = DC_AL_BMSR; 932 break; 933 case MII_PHYIDR1: 934 phy_reg = DC_AL_VENID; 935 break; 936 case MII_PHYIDR2: 937 phy_reg = DC_AL_DEVID; 938 break; 939 case MII_ANAR: 940 phy_reg = DC_AL_ANAR; 941 break; 942 case MII_ANLPAR: 943 phy_reg = DC_AL_LPAR; 944 break; 945 case MII_ANER: 946 phy_reg = DC_AL_ANER; 947 break; 948 default: 949 printf("dc%d: phy_write: bad phy register %x\n", 950 sc->dc_unit, reg); 951 return (0); 952 break; 953 } 954 955 CSR_WRITE_4(sc, phy_reg, data); 956 return (0); 957 } 958 959 frame.mii_phyaddr = phy; 960 frame.mii_regaddr = reg; 961 frame.mii_data = data; 962 963 if (sc->dc_type == DC_TYPE_98713) { 964 phy_reg = CSR_READ_4(sc, DC_NETCFG); 965 CSR_WRITE_4(sc, DC_NETCFG, phy_reg & ~DC_NETCFG_PORTSEL); 966 } 967 dc_mii_writereg(sc, &frame); 968 if (sc->dc_type == DC_TYPE_98713) 969 CSR_WRITE_4(sc, DC_NETCFG, phy_reg); 970 971 return (0); 972 } 973 974 static void 975 dc_miibus_statchg(device_t dev) 976 { 977 struct dc_softc *sc; 978 struct mii_data *mii; 979 struct ifmedia *ifm; 980 981 sc = device_get_softc(dev); 982 if (DC_IS_ADMTEK(sc)) 983 return; 984 985 mii = device_get_softc(sc->dc_miibus); 986 ifm = &mii->mii_media; 987 if (DC_IS_DAVICOM(sc) && 988 IFM_SUBTYPE(ifm->ifm_media) == IFM_HPNA_1) { 989 dc_setcfg(sc, ifm->ifm_media); 990 sc->dc_if_media = ifm->ifm_media; 991 } else { 992 dc_setcfg(sc, mii->mii_media_active); 993 sc->dc_if_media = mii->mii_media_active; 994 } 995 } 996 997 /* 998 * Special support for DM9102A cards with HomePNA PHYs. Note: 999 * with the Davicom DM9102A/DM9801 eval board that I have, it seems 1000 * to be impossible to talk to the management interface of the DM9801 1001 * PHY (its MDIO pin is not connected to anything). Consequently, 1002 * the driver has to just 'know' about the additional mode and deal 1003 * with it itself. *sigh* 1004 */ 1005 static void 1006 dc_miibus_mediainit(device_t dev) 1007 { 1008 struct dc_softc *sc; 1009 struct mii_data *mii; 1010 struct ifmedia *ifm; 1011 int rev; 1012 1013 rev = pci_read_config(dev, DC_PCI_CFRV, 4) & 0xFF; 1014 1015 sc = device_get_softc(dev); 1016 mii = device_get_softc(sc->dc_miibus); 1017 ifm = &mii->mii_media; 1018 1019 if (DC_IS_DAVICOM(sc) && rev >= DC_REVISION_DM9102A) 1020 ifmedia_add(ifm, IFM_ETHER | IFM_HPNA_1, 0, NULL); 1021 } 1022 1023 #define DC_BITS_512 9 1024 #define DC_BITS_128 7 1025 #define DC_BITS_64 6 1026 1027 static uint32_t 1028 dc_mchash_le(struct dc_softc *sc, const uint8_t *addr) 1029 { 1030 uint32_t crc; 1031 1032 /* Compute CRC for the address value. */ 1033 crc = ether_crc32_le(addr, ETHER_ADDR_LEN); 1034 1035 /* 1036 * The hash table on the PNIC II and the MX98715AEC-C/D/E 1037 * chips is only 128 bits wide. 1038 */ 1039 if (sc->dc_flags & DC_128BIT_HASH) 1040 return (crc & ((1 << DC_BITS_128) - 1)); 1041 1042 /* The hash table on the MX98715BEC is only 64 bits wide. */ 1043 if (sc->dc_flags & DC_64BIT_HASH) 1044 return (crc & ((1 << DC_BITS_64) - 1)); 1045 1046 /* Xircom's hash filtering table is different (read: weird) */ 1047 /* Xircom uses the LEAST significant bits */ 1048 if (DC_IS_XIRCOM(sc)) { 1049 if ((crc & 0x180) == 0x180) 1050 return ((crc & 0x0F) + (crc & 0x70) * 3 + (14 << 4)); 1051 else 1052 return ((crc & 0x1F) + ((crc >> 1) & 0xF0) * 3 + 1053 (12 << 4)); 1054 } 1055 1056 return (crc & ((1 << DC_BITS_512) - 1)); 1057 } 1058 1059 /* 1060 * Calculate CRC of a multicast group address, return the lower 6 bits. 1061 */ 1062 static uint32_t 1063 dc_mchash_be(const uint8_t *addr) 1064 { 1065 uint32_t crc; 1066 1067 /* Compute CRC for the address value. */ 1068 crc = ether_crc32_be(addr, ETHER_ADDR_LEN); 1069 1070 /* Return the filter bit position. */ 1071 return ((crc >> 26) & 0x0000003F); 1072 } 1073 1074 /* 1075 * 21143-style RX filter setup routine. Filter programming is done by 1076 * downloading a special setup frame into the TX engine. 21143, Macronix, 1077 * PNIC, PNIC II and Davicom chips are programmed this way. 1078 * 1079 * We always program the chip using 'hash perfect' mode, i.e. one perfect 1080 * address (our node address) and a 512-bit hash filter for multicast 1081 * frames. We also sneak the broadcast address into the hash filter since 1082 * we need that too. 1083 */ 1084 static void 1085 dc_setfilt_21143(struct dc_softc *sc) 1086 { 1087 struct dc_desc *sframe; 1088 u_int32_t h, *sp; 1089 struct ifmultiaddr *ifma; 1090 struct ifnet *ifp; 1091 int i; 1092 1093 ifp = &sc->arpcom.ac_if; 1094 1095 i = sc->dc_cdata.dc_tx_prod; 1096 DC_INC(sc->dc_cdata.dc_tx_prod, DC_TX_LIST_CNT); 1097 sc->dc_cdata.dc_tx_cnt++; 1098 sframe = &sc->dc_ldata->dc_tx_list[i]; 1099 sp = sc->dc_cdata.dc_sbuf; 1100 bzero(sp, DC_SFRAME_LEN); 1101 1102 sframe->dc_data = htole32(sc->dc_saddr); 1103 sframe->dc_ctl = htole32(DC_SFRAME_LEN | DC_TXCTL_SETUP | 1104 DC_TXCTL_TLINK | DC_FILTER_HASHPERF | DC_TXCTL_FINT); 1105 1106 sc->dc_cdata.dc_tx_chain[i] = (struct mbuf *)sc->dc_cdata.dc_sbuf; 1107 1108 /* If we want promiscuous mode, set the allframes bit. */ 1109 if (ifp->if_flags & IFF_PROMISC) 1110 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC); 1111 else 1112 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC); 1113 1114 if (ifp->if_flags & IFF_ALLMULTI) 1115 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI); 1116 else 1117 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI); 1118 1119 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 1120 if (ifma->ifma_addr->sa_family != AF_LINK) 1121 continue; 1122 h = dc_mchash_le(sc, 1123 LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 1124 sp[h >> 4] |= htole32(1 << (h & 0xF)); 1125 } 1126 1127 if (ifp->if_flags & IFF_BROADCAST) { 1128 h = dc_mchash_le(sc, ifp->if_broadcastaddr); 1129 sp[h >> 4] |= htole32(1 << (h & 0xF)); 1130 } 1131 1132 /* Set our MAC address */ 1133 sp[39] = DC_SP_MAC(((u_int16_t *)sc->arpcom.ac_enaddr)[0]); 1134 sp[40] = DC_SP_MAC(((u_int16_t *)sc->arpcom.ac_enaddr)[1]); 1135 sp[41] = DC_SP_MAC(((u_int16_t *)sc->arpcom.ac_enaddr)[2]); 1136 1137 sframe->dc_status = htole32(DC_TXSTAT_OWN); 1138 CSR_WRITE_4(sc, DC_TXSTART, 0xFFFFFFFF); 1139 1140 /* 1141 * The PNIC takes an exceedingly long time to process its 1142 * setup frame; wait 10ms after posting the setup frame 1143 * before proceeding, just so it has time to swallow its 1144 * medicine. 1145 */ 1146 DELAY(10000); 1147 1148 ifp->if_timer = 5; 1149 } 1150 1151 static void 1152 dc_setfilt_admtek(struct dc_softc *sc) 1153 { 1154 struct ifnet *ifp; 1155 struct ifmultiaddr *ifma; 1156 int h = 0; 1157 u_int32_t hashes[2] = { 0, 0 }; 1158 1159 ifp = &sc->arpcom.ac_if; 1160 1161 /* Init our MAC address. */ 1162 CSR_WRITE_4(sc, DC_AL_PAR0, *(u_int32_t *)(&sc->arpcom.ac_enaddr[0])); 1163 CSR_WRITE_4(sc, DC_AL_PAR1, *(u_int32_t *)(&sc->arpcom.ac_enaddr[4])); 1164 1165 /* If we want promiscuous mode, set the allframes bit. */ 1166 if (ifp->if_flags & IFF_PROMISC) 1167 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC); 1168 else 1169 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC); 1170 1171 if (ifp->if_flags & IFF_ALLMULTI) 1172 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI); 1173 else 1174 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI); 1175 1176 /* First, zot all the existing hash bits. */ 1177 CSR_WRITE_4(sc, DC_AL_MAR0, 0); 1178 CSR_WRITE_4(sc, DC_AL_MAR1, 0); 1179 1180 /* 1181 * If we're already in promisc or allmulti mode, we 1182 * don't have to bother programming the multicast filter. 1183 */ 1184 if (ifp->if_flags & (IFF_PROMISC | IFF_ALLMULTI)) 1185 return; 1186 1187 /* Now program new ones. */ 1188 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 1189 if (ifma->ifma_addr->sa_family != AF_LINK) 1190 continue; 1191 if (DC_IS_CENTAUR(sc)) 1192 h = dc_mchash_le(sc, 1193 LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 1194 else 1195 h = dc_mchash_be( 1196 LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 1197 if (h < 32) 1198 hashes[0] |= (1 << h); 1199 else 1200 hashes[1] |= (1 << (h - 32)); 1201 } 1202 1203 CSR_WRITE_4(sc, DC_AL_MAR0, hashes[0]); 1204 CSR_WRITE_4(sc, DC_AL_MAR1, hashes[1]); 1205 } 1206 1207 static void 1208 dc_setfilt_asix(struct dc_softc *sc) 1209 { 1210 struct ifnet *ifp; 1211 struct ifmultiaddr *ifma; 1212 int h = 0; 1213 u_int32_t hashes[2] = { 0, 0 }; 1214 1215 ifp = &sc->arpcom.ac_if; 1216 1217 /* Init our MAC address */ 1218 CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_PAR0); 1219 CSR_WRITE_4(sc, DC_AX_FILTDATA, 1220 *(u_int32_t *)(&sc->arpcom.ac_enaddr[0])); 1221 CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_PAR1); 1222 CSR_WRITE_4(sc, DC_AX_FILTDATA, 1223 *(u_int32_t *)(&sc->arpcom.ac_enaddr[4])); 1224 1225 /* If we want promiscuous mode, set the allframes bit. */ 1226 if (ifp->if_flags & IFF_PROMISC) 1227 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC); 1228 else 1229 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC); 1230 1231 if (ifp->if_flags & IFF_ALLMULTI) 1232 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI); 1233 else 1234 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI); 1235 1236 /* 1237 * The ASIX chip has a special bit to enable reception 1238 * of broadcast frames. 1239 */ 1240 if (ifp->if_flags & IFF_BROADCAST) 1241 DC_SETBIT(sc, DC_NETCFG, DC_AX_NETCFG_RX_BROAD); 1242 else 1243 DC_CLRBIT(sc, DC_NETCFG, DC_AX_NETCFG_RX_BROAD); 1244 1245 /* first, zot all the existing hash bits */ 1246 CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_MAR0); 1247 CSR_WRITE_4(sc, DC_AX_FILTDATA, 0); 1248 CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_MAR1); 1249 CSR_WRITE_4(sc, DC_AX_FILTDATA, 0); 1250 1251 /* 1252 * If we're already in promisc or allmulti mode, we 1253 * don't have to bother programming the multicast filter. 1254 */ 1255 if (ifp->if_flags & (IFF_PROMISC | IFF_ALLMULTI)) 1256 return; 1257 1258 /* now program new ones */ 1259 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 1260 if (ifma->ifma_addr->sa_family != AF_LINK) 1261 continue; 1262 h = dc_mchash_be(LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 1263 if (h < 32) 1264 hashes[0] |= (1 << h); 1265 else 1266 hashes[1] |= (1 << (h - 32)); 1267 } 1268 1269 CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_MAR0); 1270 CSR_WRITE_4(sc, DC_AX_FILTDATA, hashes[0]); 1271 CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_MAR1); 1272 CSR_WRITE_4(sc, DC_AX_FILTDATA, hashes[1]); 1273 } 1274 1275 static void 1276 dc_setfilt_xircom(struct dc_softc *sc) 1277 { 1278 struct ifnet *ifp; 1279 struct ifmultiaddr *ifma; 1280 struct dc_desc *sframe; 1281 u_int32_t h, *sp; 1282 int i; 1283 1284 ifp = &sc->arpcom.ac_if; 1285 DC_CLRBIT(sc, DC_NETCFG, (DC_NETCFG_TX_ON | DC_NETCFG_RX_ON)); 1286 1287 i = sc->dc_cdata.dc_tx_prod; 1288 DC_INC(sc->dc_cdata.dc_tx_prod, DC_TX_LIST_CNT); 1289 sc->dc_cdata.dc_tx_cnt++; 1290 sframe = &sc->dc_ldata->dc_tx_list[i]; 1291 sp = sc->dc_cdata.dc_sbuf; 1292 bzero(sp, DC_SFRAME_LEN); 1293 1294 sframe->dc_data = htole32(sc->dc_saddr); 1295 sframe->dc_ctl = htole32(DC_SFRAME_LEN | DC_TXCTL_SETUP | 1296 DC_TXCTL_TLINK | DC_FILTER_HASHPERF | DC_TXCTL_FINT); 1297 1298 sc->dc_cdata.dc_tx_chain[i] = (struct mbuf *)sc->dc_cdata.dc_sbuf; 1299 1300 /* If we want promiscuous mode, set the allframes bit. */ 1301 if (ifp->if_flags & IFF_PROMISC) 1302 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC); 1303 else 1304 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC); 1305 1306 if (ifp->if_flags & IFF_ALLMULTI) 1307 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI); 1308 else 1309 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI); 1310 1311 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 1312 if (ifma->ifma_addr->sa_family != AF_LINK) 1313 continue; 1314 h = dc_mchash_le(sc, 1315 LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 1316 sp[h >> 4] |= htole32(1 << (h & 0xF)); 1317 } 1318 1319 if (ifp->if_flags & IFF_BROADCAST) { 1320 h = dc_mchash_le(sc, ifp->if_broadcastaddr); 1321 sp[h >> 4] |= htole32(1 << (h & 0xF)); 1322 } 1323 1324 /* Set our MAC address */ 1325 sp[0] = DC_SP_MAC(((u_int16_t *)sc->arpcom.ac_enaddr)[0]); 1326 sp[1] = DC_SP_MAC(((u_int16_t *)sc->arpcom.ac_enaddr)[1]); 1327 sp[2] = DC_SP_MAC(((u_int16_t *)sc->arpcom.ac_enaddr)[2]); 1328 1329 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_TX_ON); 1330 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_ON); 1331 ifp->if_flags |= IFF_RUNNING; 1332 sframe->dc_status = htole32(DC_TXSTAT_OWN); 1333 CSR_WRITE_4(sc, DC_TXSTART, 0xFFFFFFFF); 1334 1335 /* 1336 * Wait some time... 1337 */ 1338 DELAY(1000); 1339 1340 ifp->if_timer = 5; 1341 } 1342 1343 static void 1344 dc_setfilt(struct dc_softc *sc) 1345 { 1346 1347 if (DC_IS_INTEL(sc) || DC_IS_MACRONIX(sc) || DC_IS_PNIC(sc) || 1348 DC_IS_PNICII(sc) || DC_IS_DAVICOM(sc) || DC_IS_CONEXANT(sc)) 1349 dc_setfilt_21143(sc); 1350 1351 if (DC_IS_ASIX(sc)) 1352 dc_setfilt_asix(sc); 1353 1354 if (DC_IS_ADMTEK(sc)) 1355 dc_setfilt_admtek(sc); 1356 1357 if (DC_IS_XIRCOM(sc)) 1358 dc_setfilt_xircom(sc); 1359 } 1360 1361 /* 1362 * In order to fiddle with the 'full-duplex' and '100Mbps' bits in 1363 * the netconfig register, we first have to put the transmit and/or 1364 * receive logic in the idle state. 1365 */ 1366 static void 1367 dc_setcfg(struct dc_softc *sc, int media) 1368 { 1369 int i, restart = 0, watchdogreg; 1370 u_int32_t isr; 1371 1372 if (IFM_SUBTYPE(media) == IFM_NONE) 1373 return; 1374 1375 if (CSR_READ_4(sc, DC_NETCFG) & (DC_NETCFG_TX_ON | DC_NETCFG_RX_ON)) { 1376 restart = 1; 1377 DC_CLRBIT(sc, DC_NETCFG, (DC_NETCFG_TX_ON | DC_NETCFG_RX_ON)); 1378 1379 for (i = 0; i < DC_TIMEOUT; i++) { 1380 isr = CSR_READ_4(sc, DC_ISR); 1381 if (isr & DC_ISR_TX_IDLE && 1382 ((isr & DC_ISR_RX_STATE) == DC_RXSTATE_STOPPED || 1383 (isr & DC_ISR_RX_STATE) == DC_RXSTATE_WAIT)) 1384 break; 1385 DELAY(10); 1386 } 1387 1388 if (i == DC_TIMEOUT) 1389 printf("dc%d: failed to force tx and " 1390 "rx to idle state\n", sc->dc_unit); 1391 } 1392 1393 if (IFM_SUBTYPE(media) == IFM_100_TX) { 1394 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_SPEEDSEL); 1395 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_HEARTBEAT); 1396 if (sc->dc_pmode == DC_PMODE_MII) { 1397 if (DC_IS_INTEL(sc)) { 1398 /* There's a write enable bit here that reads as 1. */ 1399 watchdogreg = CSR_READ_4(sc, DC_WATCHDOG); 1400 watchdogreg &= ~DC_WDOG_CTLWREN; 1401 watchdogreg |= DC_WDOG_JABBERDIS; 1402 CSR_WRITE_4(sc, DC_WATCHDOG, watchdogreg); 1403 } else { 1404 DC_SETBIT(sc, DC_WATCHDOG, DC_WDOG_JABBERDIS); 1405 } 1406 DC_CLRBIT(sc, DC_NETCFG, (DC_NETCFG_PCS | 1407 DC_NETCFG_PORTSEL | DC_NETCFG_SCRAMBLER)); 1408 if (sc->dc_type == DC_TYPE_98713) 1409 DC_SETBIT(sc, DC_NETCFG, (DC_NETCFG_PCS | 1410 DC_NETCFG_SCRAMBLER)); 1411 if (!DC_IS_DAVICOM(sc)) 1412 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL); 1413 DC_CLRBIT(sc, DC_10BTCTRL, 0xFFFF); 1414 if (DC_IS_INTEL(sc)) 1415 dc_apply_fixup(sc, IFM_AUTO); 1416 } else { 1417 if (DC_IS_PNIC(sc)) { 1418 DC_PN_GPIO_SETBIT(sc, DC_PN_GPIO_SPEEDSEL); 1419 DC_PN_GPIO_SETBIT(sc, DC_PN_GPIO_100TX_LOOP); 1420 DC_SETBIT(sc, DC_PN_NWAY, DC_PN_NWAY_SPEEDSEL); 1421 } 1422 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL); 1423 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PCS); 1424 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_SCRAMBLER); 1425 if (DC_IS_INTEL(sc)) 1426 dc_apply_fixup(sc, 1427 (media & IFM_GMASK) == IFM_FDX ? 1428 IFM_100_TX | IFM_FDX : IFM_100_TX); 1429 } 1430 } 1431 1432 if (IFM_SUBTYPE(media) == IFM_10_T) { 1433 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_SPEEDSEL); 1434 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_HEARTBEAT); 1435 if (sc->dc_pmode == DC_PMODE_MII) { 1436 /* There's a write enable bit here that reads as 1. */ 1437 if (DC_IS_INTEL(sc)) { 1438 watchdogreg = CSR_READ_4(sc, DC_WATCHDOG); 1439 watchdogreg &= ~DC_WDOG_CTLWREN; 1440 watchdogreg |= DC_WDOG_JABBERDIS; 1441 CSR_WRITE_4(sc, DC_WATCHDOG, watchdogreg); 1442 } else { 1443 DC_SETBIT(sc, DC_WATCHDOG, DC_WDOG_JABBERDIS); 1444 } 1445 DC_CLRBIT(sc, DC_NETCFG, (DC_NETCFG_PCS | 1446 DC_NETCFG_PORTSEL | DC_NETCFG_SCRAMBLER)); 1447 if (sc->dc_type == DC_TYPE_98713) 1448 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PCS); 1449 if (!DC_IS_DAVICOM(sc)) 1450 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL); 1451 DC_CLRBIT(sc, DC_10BTCTRL, 0xFFFF); 1452 if (DC_IS_INTEL(sc)) 1453 dc_apply_fixup(sc, IFM_AUTO); 1454 } else { 1455 if (DC_IS_PNIC(sc)) { 1456 DC_PN_GPIO_CLRBIT(sc, DC_PN_GPIO_SPEEDSEL); 1457 DC_PN_GPIO_SETBIT(sc, DC_PN_GPIO_100TX_LOOP); 1458 DC_CLRBIT(sc, DC_PN_NWAY, DC_PN_NWAY_SPEEDSEL); 1459 } 1460 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL); 1461 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_PCS); 1462 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_SCRAMBLER); 1463 if (DC_IS_INTEL(sc)) { 1464 DC_CLRBIT(sc, DC_SIARESET, DC_SIA_RESET); 1465 DC_CLRBIT(sc, DC_10BTCTRL, 0xFFFF); 1466 if ((media & IFM_GMASK) == IFM_FDX) 1467 DC_SETBIT(sc, DC_10BTCTRL, 0x7F3D); 1468 else 1469 DC_SETBIT(sc, DC_10BTCTRL, 0x7F3F); 1470 DC_SETBIT(sc, DC_SIARESET, DC_SIA_RESET); 1471 DC_CLRBIT(sc, DC_10BTCTRL, 1472 DC_TCTL_AUTONEGENBL); 1473 dc_apply_fixup(sc, 1474 (media & IFM_GMASK) == IFM_FDX ? 1475 IFM_10_T | IFM_FDX : IFM_10_T); 1476 DELAY(20000); 1477 } 1478 } 1479 } 1480 1481 /* 1482 * If this is a Davicom DM9102A card with a DM9801 HomePNA 1483 * PHY and we want HomePNA mode, set the portsel bit to turn 1484 * on the external MII port. 1485 */ 1486 if (DC_IS_DAVICOM(sc)) { 1487 if (IFM_SUBTYPE(media) == IFM_HPNA_1) { 1488 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL); 1489 sc->dc_link = 1; 1490 } else { 1491 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL); 1492 } 1493 } 1494 1495 if ((media & IFM_GMASK) == IFM_FDX) { 1496 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_FULLDUPLEX); 1497 if (sc->dc_pmode == DC_PMODE_SYM && DC_IS_PNIC(sc)) 1498 DC_SETBIT(sc, DC_PN_NWAY, DC_PN_NWAY_DUPLEX); 1499 } else { 1500 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_FULLDUPLEX); 1501 if (sc->dc_pmode == DC_PMODE_SYM && DC_IS_PNIC(sc)) 1502 DC_CLRBIT(sc, DC_PN_NWAY, DC_PN_NWAY_DUPLEX); 1503 } 1504 1505 if (restart) 1506 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_TX_ON | DC_NETCFG_RX_ON); 1507 } 1508 1509 static void 1510 dc_reset(struct dc_softc *sc) 1511 { 1512 int i; 1513 1514 DC_SETBIT(sc, DC_BUSCTL, DC_BUSCTL_RESET); 1515 1516 for (i = 0; i < DC_TIMEOUT; i++) { 1517 DELAY(10); 1518 if (!(CSR_READ_4(sc, DC_BUSCTL) & DC_BUSCTL_RESET)) 1519 break; 1520 } 1521 1522 if (DC_IS_ASIX(sc) || DC_IS_ADMTEK(sc) || DC_IS_CONEXANT(sc) || 1523 DC_IS_XIRCOM(sc) || DC_IS_INTEL(sc)) { 1524 DELAY(10000); 1525 DC_CLRBIT(sc, DC_BUSCTL, DC_BUSCTL_RESET); 1526 i = 0; 1527 } 1528 1529 if (i == DC_TIMEOUT) 1530 printf("dc%d: reset never completed!\n", sc->dc_unit); 1531 1532 /* Wait a little while for the chip to get its brains in order. */ 1533 DELAY(1000); 1534 1535 CSR_WRITE_4(sc, DC_IMR, 0x00000000); 1536 CSR_WRITE_4(sc, DC_BUSCTL, 0x00000000); 1537 CSR_WRITE_4(sc, DC_NETCFG, 0x00000000); 1538 1539 /* 1540 * Bring the SIA out of reset. In some cases, it looks 1541 * like failing to unreset the SIA soon enough gets it 1542 * into a state where it will never come out of reset 1543 * until we reset the whole chip again. 1544 */ 1545 if (DC_IS_INTEL(sc)) { 1546 DC_SETBIT(sc, DC_SIARESET, DC_SIA_RESET); 1547 CSR_WRITE_4(sc, DC_10BTCTRL, 0); 1548 CSR_WRITE_4(sc, DC_WATCHDOG, 0); 1549 } 1550 } 1551 1552 static struct dc_type * 1553 dc_devtype(device_t dev) 1554 { 1555 struct dc_type *t; 1556 u_int32_t rev; 1557 1558 t = dc_devs; 1559 1560 while (t->dc_name != NULL) { 1561 if ((pci_get_vendor(dev) == t->dc_vid) && 1562 (pci_get_device(dev) == t->dc_did)) { 1563 /* Check the PCI revision */ 1564 rev = pci_read_config(dev, DC_PCI_CFRV, 4) & 0xFF; 1565 if (t->dc_did == DC_DEVICEID_98713 && 1566 rev >= DC_REVISION_98713A) 1567 t++; 1568 if (t->dc_did == DC_DEVICEID_98713_CP && 1569 rev >= DC_REVISION_98713A) 1570 t++; 1571 if (t->dc_did == DC_DEVICEID_987x5 && 1572 rev >= DC_REVISION_98715AEC_C) 1573 t++; 1574 if (t->dc_did == DC_DEVICEID_987x5 && 1575 rev >= DC_REVISION_98725) 1576 t++; 1577 if (t->dc_did == DC_DEVICEID_AX88140A && 1578 rev >= DC_REVISION_88141) 1579 t++; 1580 if (t->dc_did == DC_DEVICEID_82C168 && 1581 rev >= DC_REVISION_82C169) 1582 t++; 1583 if (t->dc_did == DC_DEVICEID_DM9102 && 1584 rev >= DC_REVISION_DM9102A) 1585 t++; 1586 /* 1587 * The Microsoft MN-130 has a device ID of 0x0002, 1588 * which happens to be the same as the PNIC 82c168. 1589 * To keep dc_attach() from getting confused, we 1590 * pretend its ID is something different. 1591 * XXX: ideally, dc_attach() should be checking 1592 * vendorid+deviceid together to avoid such 1593 * collisions. 1594 */ 1595 if (t->dc_vid == DC_VENDORID_MICROSOFT && 1596 t->dc_did == DC_DEVICEID_MSMN130) 1597 t++; 1598 return (t); 1599 } 1600 t++; 1601 } 1602 1603 return (NULL); 1604 } 1605 1606 /* 1607 * Probe for a 21143 or clone chip. Check the PCI vendor and device 1608 * IDs against our list and return a device name if we find a match. 1609 * We do a little bit of extra work to identify the exact type of 1610 * chip. The MX98713 and MX98713A have the same PCI vendor/device ID, 1611 * but different revision IDs. The same is true for 98715/98715A 1612 * chips and the 98725, as well as the ASIX and ADMtek chips. In some 1613 * cases, the exact chip revision affects driver behavior. 1614 */ 1615 static int 1616 dc_probe(device_t dev) 1617 { 1618 struct dc_type *t; 1619 1620 t = dc_devtype(dev); 1621 1622 if (t != NULL) { 1623 device_set_desc(dev, t->dc_name); 1624 return (0); 1625 } 1626 1627 return (ENXIO); 1628 } 1629 1630 static void 1631 dc_apply_fixup(struct dc_softc *sc, int media) 1632 { 1633 struct dc_mediainfo *m; 1634 u_int8_t *p; 1635 int i; 1636 u_int32_t reg; 1637 1638 m = sc->dc_mi; 1639 1640 while (m != NULL) { 1641 if (m->dc_media == media) 1642 break; 1643 m = m->dc_next; 1644 } 1645 1646 if (m == NULL) 1647 return; 1648 1649 for (i = 0, p = m->dc_reset_ptr; i < m->dc_reset_len; i++, p += 2) { 1650 reg = (p[0] | (p[1] << 8)) << 16; 1651 CSR_WRITE_4(sc, DC_WATCHDOG, reg); 1652 } 1653 1654 for (i = 0, p = m->dc_gp_ptr; i < m->dc_gp_len; i++, p += 2) { 1655 reg = (p[0] | (p[1] << 8)) << 16; 1656 CSR_WRITE_4(sc, DC_WATCHDOG, reg); 1657 } 1658 } 1659 1660 static void 1661 dc_decode_leaf_sia(struct dc_softc *sc, struct dc_eblock_sia *l) 1662 { 1663 struct dc_mediainfo *m; 1664 1665 m = malloc(sizeof(struct dc_mediainfo), M_DEVBUF, M_NOWAIT | M_ZERO); 1666 switch (l->dc_sia_code & ~DC_SIA_CODE_EXT) { 1667 case DC_SIA_CODE_10BT: 1668 m->dc_media = IFM_10_T; 1669 break; 1670 case DC_SIA_CODE_10BT_FDX: 1671 m->dc_media = IFM_10_T | IFM_FDX; 1672 break; 1673 case DC_SIA_CODE_10B2: 1674 m->dc_media = IFM_10_2; 1675 break; 1676 case DC_SIA_CODE_10B5: 1677 m->dc_media = IFM_10_5; 1678 break; 1679 default: 1680 break; 1681 } 1682 1683 /* 1684 * We need to ignore CSR13, CSR14, CSR15 for SIA mode. 1685 * Things apparently already work for cards that do 1686 * supply Media Specific Data. 1687 */ 1688 if (l->dc_sia_code & DC_SIA_CODE_EXT) { 1689 m->dc_gp_len = 2; 1690 m->dc_gp_ptr = 1691 (u_int8_t *)&l->dc_un.dc_sia_ext.dc_sia_gpio_ctl; 1692 } else { 1693 m->dc_gp_len = 2; 1694 m->dc_gp_ptr = 1695 (u_int8_t *)&l->dc_un.dc_sia_noext.dc_sia_gpio_ctl; 1696 } 1697 1698 m->dc_next = sc->dc_mi; 1699 sc->dc_mi = m; 1700 1701 sc->dc_pmode = DC_PMODE_SIA; 1702 } 1703 1704 static void 1705 dc_decode_leaf_sym(struct dc_softc *sc, struct dc_eblock_sym *l) 1706 { 1707 struct dc_mediainfo *m; 1708 1709 m = malloc(sizeof(struct dc_mediainfo), M_DEVBUF, M_NOWAIT | M_ZERO); 1710 if (l->dc_sym_code == DC_SYM_CODE_100BT) 1711 m->dc_media = IFM_100_TX; 1712 1713 if (l->dc_sym_code == DC_SYM_CODE_100BT_FDX) 1714 m->dc_media = IFM_100_TX | IFM_FDX; 1715 1716 m->dc_gp_len = 2; 1717 m->dc_gp_ptr = (u_int8_t *)&l->dc_sym_gpio_ctl; 1718 1719 m->dc_next = sc->dc_mi; 1720 sc->dc_mi = m; 1721 1722 sc->dc_pmode = DC_PMODE_SYM; 1723 } 1724 1725 static void 1726 dc_decode_leaf_mii(struct dc_softc *sc, struct dc_eblock_mii *l) 1727 { 1728 struct dc_mediainfo *m; 1729 u_int8_t *p; 1730 1731 m = malloc(sizeof(struct dc_mediainfo), M_DEVBUF, M_NOWAIT | M_ZERO); 1732 /* We abuse IFM_AUTO to represent MII. */ 1733 m->dc_media = IFM_AUTO; 1734 m->dc_gp_len = l->dc_gpr_len; 1735 1736 p = (u_int8_t *)l; 1737 p += sizeof(struct dc_eblock_mii); 1738 m->dc_gp_ptr = p; 1739 p += 2 * l->dc_gpr_len; 1740 m->dc_reset_len = *p; 1741 p++; 1742 m->dc_reset_ptr = p; 1743 1744 m->dc_next = sc->dc_mi; 1745 sc->dc_mi = m; 1746 } 1747 1748 static void 1749 dc_read_srom(struct dc_softc *sc, int bits) 1750 { 1751 int size; 1752 1753 size = 2 << bits; 1754 sc->dc_srom = malloc(size, M_DEVBUF, M_NOWAIT); 1755 dc_read_eeprom(sc, (caddr_t)sc->dc_srom, 0, (size / 2), 0); 1756 } 1757 1758 static void 1759 dc_parse_21143_srom(struct dc_softc *sc) 1760 { 1761 struct dc_leaf_hdr *lhdr; 1762 struct dc_eblock_hdr *hdr; 1763 int have_mii, i, loff; 1764 char *ptr; 1765 1766 have_mii = 0; 1767 loff = sc->dc_srom[27]; 1768 lhdr = (struct dc_leaf_hdr *)&(sc->dc_srom[loff]); 1769 1770 ptr = (char *)lhdr; 1771 ptr += sizeof(struct dc_leaf_hdr) - 1; 1772 /* 1773 * Look if we got a MII media block. 1774 */ 1775 for (i = 0; i < lhdr->dc_mcnt; i++) { 1776 hdr = (struct dc_eblock_hdr *)ptr; 1777 if (hdr->dc_type == DC_EBLOCK_MII) 1778 have_mii++; 1779 1780 ptr += (hdr->dc_len & 0x7F); 1781 ptr++; 1782 } 1783 1784 /* 1785 * Do the same thing again. Only use SIA and SYM media 1786 * blocks if no MII media block is available. 1787 */ 1788 ptr = (char *)lhdr; 1789 ptr += sizeof(struct dc_leaf_hdr) - 1; 1790 for (i = 0; i < lhdr->dc_mcnt; i++) { 1791 hdr = (struct dc_eblock_hdr *)ptr; 1792 switch (hdr->dc_type) { 1793 case DC_EBLOCK_MII: 1794 dc_decode_leaf_mii(sc, (struct dc_eblock_mii *)hdr); 1795 break; 1796 case DC_EBLOCK_SIA: 1797 if (! have_mii) 1798 dc_decode_leaf_sia(sc, 1799 (struct dc_eblock_sia *)hdr); 1800 break; 1801 case DC_EBLOCK_SYM: 1802 if (! have_mii) 1803 dc_decode_leaf_sym(sc, 1804 (struct dc_eblock_sym *)hdr); 1805 break; 1806 default: 1807 /* Don't care. Yet. */ 1808 break; 1809 } 1810 ptr += (hdr->dc_len & 0x7F); 1811 ptr++; 1812 } 1813 } 1814 1815 static void 1816 dc_dma_map_addr(void *arg, bus_dma_segment_t *segs, int nseg, int error) 1817 { 1818 u_int32_t *paddr; 1819 1820 KASSERT(nseg == 1, ("wrong number of segments, should be 1")); 1821 paddr = arg; 1822 *paddr = segs->ds_addr; 1823 } 1824 1825 /* 1826 * Attach the interface. Allocate softc structures, do ifmedia 1827 * setup and ethernet/BPF attach. 1828 */ 1829 static int 1830 dc_attach(device_t dev) 1831 { 1832 int tmp = 0; 1833 u_char eaddr[ETHER_ADDR_LEN]; 1834 u_int32_t command; 1835 struct dc_softc *sc; 1836 struct ifnet *ifp; 1837 u_int32_t revision; 1838 int unit, error = 0, rid, mac_offset; 1839 int i; 1840 u_int8_t *mac; 1841 1842 sc = device_get_softc(dev); 1843 unit = device_get_unit(dev); 1844 1845 mtx_init(&sc->dc_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 1846 MTX_DEF | MTX_RECURSE); 1847 1848 /* 1849 * Map control/status registers. 1850 */ 1851 pci_enable_busmaster(dev); 1852 1853 rid = DC_RID; 1854 sc->dc_res = bus_alloc_resource_any(dev, DC_RES, &rid, RF_ACTIVE); 1855 1856 if (sc->dc_res == NULL) { 1857 printf("dc%d: couldn't map ports/memory\n", unit); 1858 error = ENXIO; 1859 goto fail; 1860 } 1861 1862 sc->dc_btag = rman_get_bustag(sc->dc_res); 1863 sc->dc_bhandle = rman_get_bushandle(sc->dc_res); 1864 1865 /* Allocate interrupt. */ 1866 rid = 0; 1867 sc->dc_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 1868 RF_SHAREABLE | RF_ACTIVE); 1869 1870 if (sc->dc_irq == NULL) { 1871 printf("dc%d: couldn't map interrupt\n", unit); 1872 error = ENXIO; 1873 goto fail; 1874 } 1875 1876 /* Need this info to decide on a chip type. */ 1877 sc->dc_info = dc_devtype(dev); 1878 revision = pci_read_config(dev, DC_PCI_CFRV, 4) & 0x000000FF; 1879 1880 /* Get the eeprom width, but PNIC and XIRCOM have diff eeprom */ 1881 if (sc->dc_info->dc_did != DC_DEVICEID_82C168 && 1882 sc->dc_info->dc_did != DC_DEVICEID_X3201) 1883 dc_eeprom_width(sc); 1884 1885 switch (sc->dc_info->dc_did) { 1886 case DC_DEVICEID_21143: 1887 sc->dc_type = DC_TYPE_21143; 1888 sc->dc_flags |= DC_TX_POLL | DC_TX_USE_TX_INTR; 1889 sc->dc_flags |= DC_REDUCED_MII_POLL; 1890 /* Save EEPROM contents so we can parse them later. */ 1891 dc_read_srom(sc, sc->dc_romwidth); 1892 break; 1893 case DC_DEVICEID_DM9009: 1894 case DC_DEVICEID_DM9100: 1895 case DC_DEVICEID_DM9102: 1896 sc->dc_type = DC_TYPE_DM9102; 1897 sc->dc_flags |= DC_TX_COALESCE | DC_TX_INTR_ALWAYS; 1898 sc->dc_flags |= DC_REDUCED_MII_POLL | DC_TX_STORENFWD; 1899 sc->dc_flags |= DC_TX_ALIGN; 1900 sc->dc_pmode = DC_PMODE_MII; 1901 /* Increase the latency timer value. */ 1902 command = pci_read_config(dev, DC_PCI_CFLT, 4); 1903 command &= 0xFFFF00FF; 1904 command |= 0x00008000; 1905 pci_write_config(dev, DC_PCI_CFLT, command, 4); 1906 break; 1907 case DC_DEVICEID_AL981: 1908 sc->dc_type = DC_TYPE_AL981; 1909 sc->dc_flags |= DC_TX_USE_TX_INTR; 1910 sc->dc_flags |= DC_TX_ADMTEK_WAR; 1911 sc->dc_pmode = DC_PMODE_MII; 1912 dc_read_srom(sc, sc->dc_romwidth); 1913 break; 1914 case DC_DEVICEID_AN985: 1915 case DC_DEVICEID_ADM9511: 1916 case DC_DEVICEID_ADM9513: 1917 case DC_DEVICEID_FA511: 1918 case DC_DEVICEID_FE2500: 1919 case DC_DEVICEID_EN2242: 1920 case DC_DEVICEID_HAWKING_PN672TX: 1921 case DC_DEVICEID_3CSOHOB: 1922 case DC_DEVICEID_MSMN120: 1923 case DC_DEVICEID_MSMN130_FAKE: /* XXX avoid collision with PNIC*/ 1924 sc->dc_type = DC_TYPE_AN985; 1925 sc->dc_flags |= DC_64BIT_HASH; 1926 sc->dc_flags |= DC_TX_USE_TX_INTR; 1927 sc->dc_flags |= DC_TX_ADMTEK_WAR; 1928 sc->dc_pmode = DC_PMODE_MII; 1929 /* Don't read SROM for - auto-loaded on reset */ 1930 break; 1931 case DC_DEVICEID_98713: 1932 case DC_DEVICEID_98713_CP: 1933 if (revision < DC_REVISION_98713A) { 1934 sc->dc_type = DC_TYPE_98713; 1935 } 1936 if (revision >= DC_REVISION_98713A) { 1937 sc->dc_type = DC_TYPE_98713A; 1938 sc->dc_flags |= DC_21143_NWAY; 1939 } 1940 sc->dc_flags |= DC_REDUCED_MII_POLL; 1941 sc->dc_flags |= DC_TX_POLL | DC_TX_USE_TX_INTR; 1942 break; 1943 case DC_DEVICEID_987x5: 1944 case DC_DEVICEID_EN1217: 1945 /* 1946 * Macronix MX98715AEC-C/D/E parts have only a 1947 * 128-bit hash table. We need to deal with these 1948 * in the same manner as the PNIC II so that we 1949 * get the right number of bits out of the 1950 * CRC routine. 1951 */ 1952 if (revision >= DC_REVISION_98715AEC_C && 1953 revision < DC_REVISION_98725) 1954 sc->dc_flags |= DC_128BIT_HASH; 1955 sc->dc_type = DC_TYPE_987x5; 1956 sc->dc_flags |= DC_TX_POLL | DC_TX_USE_TX_INTR; 1957 sc->dc_flags |= DC_REDUCED_MII_POLL | DC_21143_NWAY; 1958 break; 1959 case DC_DEVICEID_98727: 1960 sc->dc_type = DC_TYPE_987x5; 1961 sc->dc_flags |= DC_TX_POLL | DC_TX_USE_TX_INTR; 1962 sc->dc_flags |= DC_REDUCED_MII_POLL | DC_21143_NWAY; 1963 break; 1964 case DC_DEVICEID_82C115: 1965 sc->dc_type = DC_TYPE_PNICII; 1966 sc->dc_flags |= DC_TX_POLL | DC_TX_USE_TX_INTR | DC_128BIT_HASH; 1967 sc->dc_flags |= DC_REDUCED_MII_POLL | DC_21143_NWAY; 1968 break; 1969 case DC_DEVICEID_82C168: 1970 sc->dc_type = DC_TYPE_PNIC; 1971 sc->dc_flags |= DC_TX_STORENFWD | DC_TX_INTR_ALWAYS; 1972 sc->dc_flags |= DC_PNIC_RX_BUG_WAR; 1973 sc->dc_pnic_rx_buf = malloc(DC_RXLEN * 5, M_DEVBUF, M_NOWAIT); 1974 if (revision < DC_REVISION_82C169) 1975 sc->dc_pmode = DC_PMODE_SYM; 1976 break; 1977 case DC_DEVICEID_AX88140A: 1978 sc->dc_type = DC_TYPE_ASIX; 1979 sc->dc_flags |= DC_TX_USE_TX_INTR | DC_TX_INTR_FIRSTFRAG; 1980 sc->dc_flags |= DC_REDUCED_MII_POLL; 1981 sc->dc_pmode = DC_PMODE_MII; 1982 break; 1983 case DC_DEVICEID_X3201: 1984 sc->dc_type = DC_TYPE_XIRCOM; 1985 sc->dc_flags |= DC_TX_INTR_ALWAYS | DC_TX_COALESCE | 1986 DC_TX_ALIGN; 1987 /* 1988 * We don't actually need to coalesce, but we're doing 1989 * it to obtain a double word aligned buffer. 1990 * The DC_TX_COALESCE flag is required. 1991 */ 1992 sc->dc_pmode = DC_PMODE_MII; 1993 break; 1994 case DC_DEVICEID_RS7112: 1995 sc->dc_type = DC_TYPE_CONEXANT; 1996 sc->dc_flags |= DC_TX_INTR_ALWAYS; 1997 sc->dc_flags |= DC_REDUCED_MII_POLL; 1998 sc->dc_pmode = DC_PMODE_MII; 1999 dc_read_srom(sc, sc->dc_romwidth); 2000 break; 2001 default: 2002 printf("dc%d: unknown device: %x\n", sc->dc_unit, 2003 sc->dc_info->dc_did); 2004 break; 2005 } 2006 2007 /* Save the cache line size. */ 2008 if (DC_IS_DAVICOM(sc)) 2009 sc->dc_cachesize = 0; 2010 else 2011 sc->dc_cachesize = pci_read_config(dev, 2012 DC_PCI_CFLT, 4) & 0xFF; 2013 2014 /* Reset the adapter. */ 2015 dc_reset(sc); 2016 2017 /* Take 21143 out of snooze mode */ 2018 if (DC_IS_INTEL(sc) || DC_IS_XIRCOM(sc)) { 2019 command = pci_read_config(dev, DC_PCI_CFDD, 4); 2020 command &= ~(DC_CFDD_SNOOZE_MODE | DC_CFDD_SLEEP_MODE); 2021 pci_write_config(dev, DC_PCI_CFDD, command, 4); 2022 } 2023 2024 /* 2025 * Try to learn something about the supported media. 2026 * We know that ASIX and ADMtek and Davicom devices 2027 * will *always* be using MII media, so that's a no-brainer. 2028 * The tricky ones are the Macronix/PNIC II and the 2029 * Intel 21143. 2030 */ 2031 if (DC_IS_INTEL(sc)) 2032 dc_parse_21143_srom(sc); 2033 else if (DC_IS_MACRONIX(sc) || DC_IS_PNICII(sc)) { 2034 if (sc->dc_type == DC_TYPE_98713) 2035 sc->dc_pmode = DC_PMODE_MII; 2036 else 2037 sc->dc_pmode = DC_PMODE_SYM; 2038 } else if (!sc->dc_pmode) 2039 sc->dc_pmode = DC_PMODE_MII; 2040 2041 /* 2042 * Get station address from the EEPROM. 2043 */ 2044 switch(sc->dc_type) { 2045 case DC_TYPE_98713: 2046 case DC_TYPE_98713A: 2047 case DC_TYPE_987x5: 2048 case DC_TYPE_PNICII: 2049 dc_read_eeprom(sc, (caddr_t)&mac_offset, 2050 (DC_EE_NODEADDR_OFFSET / 2), 1, 0); 2051 dc_read_eeprom(sc, (caddr_t)&eaddr, (mac_offset / 2), 3, 0); 2052 break; 2053 case DC_TYPE_PNIC: 2054 dc_read_eeprom(sc, (caddr_t)&eaddr, 0, 3, 1); 2055 break; 2056 case DC_TYPE_DM9102: 2057 dc_read_eeprom(sc, (caddr_t)&eaddr, DC_EE_NODEADDR, 3, 0); 2058 #ifdef __sparc64__ 2059 /* 2060 * If this is an onboard dc(4) the station address read from 2061 * the EEPROM is all zero and we have to get it from the fcode. 2062 */ 2063 for (i = 0; i < ETHER_ADDR_LEN; i++) 2064 if (eaddr[i] != 0x00) 2065 break; 2066 if (i >= ETHER_ADDR_LEN) 2067 OF_getetheraddr(dev, eaddr); 2068 #endif 2069 break; 2070 case DC_TYPE_21143: 2071 case DC_TYPE_ASIX: 2072 dc_read_eeprom(sc, (caddr_t)&eaddr, DC_EE_NODEADDR, 3, 0); 2073 break; 2074 case DC_TYPE_AL981: 2075 case DC_TYPE_AN985: 2076 *(u_int32_t *)(&eaddr[0]) = CSR_READ_4(sc, DC_AL_PAR0); 2077 *(u_int16_t *)(&eaddr[4]) = CSR_READ_4(sc, DC_AL_PAR1); 2078 break; 2079 case DC_TYPE_CONEXANT: 2080 bcopy(sc->dc_srom + DC_CONEXANT_EE_NODEADDR, &eaddr, 2081 ETHER_ADDR_LEN); 2082 break; 2083 case DC_TYPE_XIRCOM: 2084 /* The MAC comes from the CIS. */ 2085 mac = pci_get_ether(dev); 2086 if (!mac) { 2087 device_printf(dev, "No station address in CIS!\n"); 2088 error = ENXIO; 2089 goto fail; 2090 } 2091 bcopy(mac, eaddr, ETHER_ADDR_LEN); 2092 break; 2093 default: 2094 dc_read_eeprom(sc, (caddr_t)&eaddr, DC_EE_NODEADDR, 3, 0); 2095 break; 2096 } 2097 2098 sc->dc_unit = unit; 2099 bcopy(eaddr, &sc->arpcom.ac_enaddr, ETHER_ADDR_LEN); 2100 2101 /* Allocate a busdma tag and DMA safe memory for TX/RX descriptors. */ 2102 error = bus_dma_tag_create(NULL, PAGE_SIZE, 0, BUS_SPACE_MAXADDR_32BIT, 2103 BUS_SPACE_MAXADDR, NULL, NULL, sizeof(struct dc_list_data), 1, 2104 sizeof(struct dc_list_data), 0, NULL, NULL, &sc->dc_ltag); 2105 if (error) { 2106 printf("dc%d: failed to allocate busdma tag\n", unit); 2107 error = ENXIO; 2108 goto fail; 2109 } 2110 error = bus_dmamem_alloc(sc->dc_ltag, (void **)&sc->dc_ldata, 2111 BUS_DMA_NOWAIT | BUS_DMA_ZERO, &sc->dc_lmap); 2112 if (error) { 2113 printf("dc%d: failed to allocate DMA safe memory\n", unit); 2114 error = ENXIO; 2115 goto fail; 2116 } 2117 error = bus_dmamap_load(sc->dc_ltag, sc->dc_lmap, sc->dc_ldata, 2118 sizeof(struct dc_list_data), dc_dma_map_addr, &sc->dc_laddr, 2119 BUS_DMA_NOWAIT); 2120 if (error) { 2121 printf("dc%d: cannot get address of the descriptors\n", unit); 2122 error = ENXIO; 2123 goto fail; 2124 } 2125 2126 /* 2127 * Allocate a busdma tag and DMA safe memory for the multicast 2128 * setup frame. 2129 */ 2130 error = bus_dma_tag_create(NULL, PAGE_SIZE, 0, BUS_SPACE_MAXADDR_32BIT, 2131 BUS_SPACE_MAXADDR, NULL, NULL, DC_SFRAME_LEN + DC_MIN_FRAMELEN, 1, 2132 DC_SFRAME_LEN + DC_MIN_FRAMELEN, 0, NULL, NULL, &sc->dc_stag); 2133 if (error) { 2134 printf("dc%d: failed to allocate busdma tag\n", unit); 2135 error = ENXIO; 2136 goto fail; 2137 } 2138 error = bus_dmamem_alloc(sc->dc_stag, (void **)&sc->dc_cdata.dc_sbuf, 2139 BUS_DMA_NOWAIT, &sc->dc_smap); 2140 if (error) { 2141 printf("dc%d: failed to allocate DMA safe memory\n", unit); 2142 error = ENXIO; 2143 goto fail; 2144 } 2145 error = bus_dmamap_load(sc->dc_stag, sc->dc_smap, sc->dc_cdata.dc_sbuf, 2146 DC_SFRAME_LEN, dc_dma_map_addr, &sc->dc_saddr, BUS_DMA_NOWAIT); 2147 if (error) { 2148 printf("dc%d: cannot get address of the descriptors\n", unit); 2149 error = ENXIO; 2150 goto fail; 2151 } 2152 2153 /* Allocate a busdma tag for mbufs. */ 2154 error = bus_dma_tag_create(NULL, PAGE_SIZE, 0, BUS_SPACE_MAXADDR_32BIT, 2155 BUS_SPACE_MAXADDR, NULL, NULL, MCLBYTES * DC_TX_LIST_CNT, 2156 DC_TX_LIST_CNT, MCLBYTES, 0, NULL, NULL, &sc->dc_mtag); 2157 if (error) { 2158 printf("dc%d: failed to allocate busdma tag\n", unit); 2159 error = ENXIO; 2160 goto fail; 2161 } 2162 2163 /* Create the TX/RX busdma maps. */ 2164 for (i = 0; i < DC_TX_LIST_CNT; i++) { 2165 error = bus_dmamap_create(sc->dc_mtag, 0, 2166 &sc->dc_cdata.dc_tx_map[i]); 2167 if (error) { 2168 printf("dc%d: failed to init TX ring\n", unit); 2169 error = ENXIO; 2170 goto fail; 2171 } 2172 } 2173 for (i = 0; i < DC_RX_LIST_CNT; i++) { 2174 error = bus_dmamap_create(sc->dc_mtag, 0, 2175 &sc->dc_cdata.dc_rx_map[i]); 2176 if (error) { 2177 printf("dc%d: failed to init RX ring\n", unit); 2178 error = ENXIO; 2179 goto fail; 2180 } 2181 } 2182 error = bus_dmamap_create(sc->dc_mtag, 0, &sc->dc_sparemap); 2183 if (error) { 2184 printf("dc%d: failed to init RX ring\n", unit); 2185 error = ENXIO; 2186 goto fail; 2187 } 2188 2189 ifp = &sc->arpcom.ac_if; 2190 ifp->if_softc = sc; 2191 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 2192 /* XXX: bleah, MTU gets overwritten in ether_ifattach() */ 2193 ifp->if_mtu = ETHERMTU; 2194 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 2195 ifp->if_ioctl = dc_ioctl; 2196 ifp->if_start = dc_start; 2197 ifp->if_watchdog = dc_watchdog; 2198 ifp->if_init = dc_init; 2199 ifp->if_baudrate = 10000000; 2200 ifp->if_snd.ifq_maxlen = DC_TX_LIST_CNT - 1; 2201 2202 /* 2203 * Do MII setup. If this is a 21143, check for a PHY on the 2204 * MII bus after applying any necessary fixups to twiddle the 2205 * GPIO bits. If we don't end up finding a PHY, restore the 2206 * old selection (SIA only or SIA/SYM) and attach the dcphy 2207 * driver instead. 2208 */ 2209 if (DC_IS_INTEL(sc)) { 2210 dc_apply_fixup(sc, IFM_AUTO); 2211 tmp = sc->dc_pmode; 2212 sc->dc_pmode = DC_PMODE_MII; 2213 } 2214 2215 error = mii_phy_probe(dev, &sc->dc_miibus, 2216 dc_ifmedia_upd, dc_ifmedia_sts); 2217 2218 if (error && DC_IS_INTEL(sc)) { 2219 sc->dc_pmode = tmp; 2220 if (sc->dc_pmode != DC_PMODE_SIA) 2221 sc->dc_pmode = DC_PMODE_SYM; 2222 sc->dc_flags |= DC_21143_NWAY; 2223 mii_phy_probe(dev, &sc->dc_miibus, 2224 dc_ifmedia_upd, dc_ifmedia_sts); 2225 /* 2226 * For non-MII cards, we need to have the 21143 2227 * drive the LEDs. Except there are some systems 2228 * like the NEC VersaPro NoteBook PC which have no 2229 * LEDs, and twiddling these bits has adverse effects 2230 * on them. (I.e. you suddenly can't get a link.) 2231 */ 2232 if (pci_read_config(dev, DC_PCI_CSID, 4) != 0x80281033) 2233 sc->dc_flags |= DC_TULIP_LEDS; 2234 error = 0; 2235 } 2236 2237 if (error) { 2238 printf("dc%d: MII without any PHY!\n", sc->dc_unit); 2239 goto fail; 2240 } 2241 2242 if (DC_IS_XIRCOM(sc)) { 2243 /* 2244 * setup General Purpose Port mode and data so the tulip 2245 * can talk to the MII. 2246 */ 2247 CSR_WRITE_4(sc, DC_SIAGP, DC_SIAGP_WRITE_EN | DC_SIAGP_INT1_EN | 2248 DC_SIAGP_MD_GP2_OUTPUT | DC_SIAGP_MD_GP0_OUTPUT); 2249 DELAY(10); 2250 CSR_WRITE_4(sc, DC_SIAGP, DC_SIAGP_INT1_EN | 2251 DC_SIAGP_MD_GP2_OUTPUT | DC_SIAGP_MD_GP0_OUTPUT); 2252 DELAY(10); 2253 } 2254 2255 if (DC_IS_ADMTEK(sc)) { 2256 /* 2257 * Set automatic TX underrun recovery for the ADMtek chips 2258 */ 2259 DC_SETBIT(sc, DC_AL_CR, DC_AL_CR_ATUR); 2260 } 2261 2262 /* 2263 * Tell the upper layer(s) we support long frames. 2264 */ 2265 ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header); 2266 ifp->if_capabilities |= IFCAP_VLAN_MTU; 2267 #ifdef DEVICE_POLLING 2268 ifp->if_capabilities |= IFCAP_POLLING; 2269 #endif 2270 ifp->if_capenable = ifp->if_capabilities; 2271 2272 callout_init(&sc->dc_stat_ch, IS_MPSAFE ? CALLOUT_MPSAFE : 0); 2273 2274 #ifdef SRM_MEDIA 2275 sc->dc_srm_media = 0; 2276 2277 /* Remember the SRM console media setting */ 2278 if (DC_IS_INTEL(sc)) { 2279 command = pci_read_config(dev, DC_PCI_CFDD, 4); 2280 command &= ~(DC_CFDD_SNOOZE_MODE | DC_CFDD_SLEEP_MODE); 2281 switch ((command >> 8) & 0xff) { 2282 case 3: 2283 sc->dc_srm_media = IFM_10_T; 2284 break; 2285 case 4: 2286 sc->dc_srm_media = IFM_10_T | IFM_FDX; 2287 break; 2288 case 5: 2289 sc->dc_srm_media = IFM_100_TX; 2290 break; 2291 case 6: 2292 sc->dc_srm_media = IFM_100_TX | IFM_FDX; 2293 break; 2294 } 2295 if (sc->dc_srm_media) 2296 sc->dc_srm_media |= IFM_ACTIVE | IFM_ETHER; 2297 } 2298 #endif 2299 2300 /* 2301 * Call MI attach routine. 2302 */ 2303 ether_ifattach(ifp, eaddr); 2304 2305 /* Hook interrupt last to avoid having to lock softc */ 2306 error = bus_setup_intr(dev, sc->dc_irq, INTR_TYPE_NET | 2307 (IS_MPSAFE ? INTR_MPSAFE : 0), 2308 dc_intr, sc, &sc->dc_intrhand); 2309 2310 if (error) { 2311 printf("dc%d: couldn't set up irq\n", unit); 2312 ether_ifdetach(ifp); 2313 goto fail; 2314 } 2315 2316 fail: 2317 if (error) 2318 dc_detach(dev); 2319 return (error); 2320 } 2321 2322 /* 2323 * Shutdown hardware and free up resources. This can be called any 2324 * time after the mutex has been initialized. It is called in both 2325 * the error case in attach and the normal detach case so it needs 2326 * to be careful about only freeing resources that have actually been 2327 * allocated. 2328 */ 2329 static int 2330 dc_detach(device_t dev) 2331 { 2332 struct dc_softc *sc; 2333 struct ifnet *ifp; 2334 struct dc_mediainfo *m; 2335 int i; 2336 2337 sc = device_get_softc(dev); 2338 KASSERT(mtx_initialized(&sc->dc_mtx), ("dc mutex not initialized")); 2339 DC_LOCK(sc); 2340 2341 ifp = &sc->arpcom.ac_if; 2342 2343 /* These should only be active if attach succeeded */ 2344 if (device_is_attached(dev)) { 2345 dc_stop(sc); 2346 ether_ifdetach(ifp); 2347 } 2348 if (sc->dc_miibus) 2349 device_delete_child(dev, sc->dc_miibus); 2350 bus_generic_detach(dev); 2351 2352 if (sc->dc_intrhand) 2353 bus_teardown_intr(dev, sc->dc_irq, sc->dc_intrhand); 2354 if (sc->dc_irq) 2355 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->dc_irq); 2356 if (sc->dc_res) 2357 bus_release_resource(dev, DC_RES, DC_RID, sc->dc_res); 2358 2359 if (sc->dc_cdata.dc_sbuf != NULL) 2360 bus_dmamem_free(sc->dc_stag, sc->dc_cdata.dc_sbuf, sc->dc_smap); 2361 if (sc->dc_ldata != NULL) 2362 bus_dmamem_free(sc->dc_ltag, sc->dc_ldata, sc->dc_lmap); 2363 for (i = 0; i < DC_TX_LIST_CNT; i++) 2364 bus_dmamap_destroy(sc->dc_mtag, sc->dc_cdata.dc_tx_map[i]); 2365 for (i = 0; i < DC_RX_LIST_CNT; i++) 2366 bus_dmamap_destroy(sc->dc_mtag, sc->dc_cdata.dc_rx_map[i]); 2367 bus_dmamap_destroy(sc->dc_mtag, sc->dc_sparemap); 2368 if (sc->dc_stag) 2369 bus_dma_tag_destroy(sc->dc_stag); 2370 if (sc->dc_mtag) 2371 bus_dma_tag_destroy(sc->dc_mtag); 2372 if (sc->dc_ltag) 2373 bus_dma_tag_destroy(sc->dc_ltag); 2374 2375 free(sc->dc_pnic_rx_buf, M_DEVBUF); 2376 2377 while (sc->dc_mi != NULL) { 2378 m = sc->dc_mi->dc_next; 2379 free(sc->dc_mi, M_DEVBUF); 2380 sc->dc_mi = m; 2381 } 2382 free(sc->dc_srom, M_DEVBUF); 2383 2384 DC_UNLOCK(sc); 2385 mtx_destroy(&sc->dc_mtx); 2386 2387 return (0); 2388 } 2389 2390 /* 2391 * Initialize the transmit descriptors. 2392 */ 2393 static int 2394 dc_list_tx_init(struct dc_softc *sc) 2395 { 2396 struct dc_chain_data *cd; 2397 struct dc_list_data *ld; 2398 int i, nexti; 2399 2400 cd = &sc->dc_cdata; 2401 ld = sc->dc_ldata; 2402 for (i = 0; i < DC_TX_LIST_CNT; i++) { 2403 if (i == DC_TX_LIST_CNT - 1) 2404 nexti = 0; 2405 else 2406 nexti = i + 1; 2407 ld->dc_tx_list[i].dc_next = htole32(DC_TXDESC(sc, nexti)); 2408 cd->dc_tx_chain[i] = NULL; 2409 ld->dc_tx_list[i].dc_data = 0; 2410 ld->dc_tx_list[i].dc_ctl = 0; 2411 } 2412 2413 cd->dc_tx_prod = cd->dc_tx_cons = cd->dc_tx_cnt = 0; 2414 bus_dmamap_sync(sc->dc_ltag, sc->dc_lmap, 2415 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2416 return (0); 2417 } 2418 2419 2420 /* 2421 * Initialize the RX descriptors and allocate mbufs for them. Note that 2422 * we arrange the descriptors in a closed ring, so that the last descriptor 2423 * points back to the first. 2424 */ 2425 static int 2426 dc_list_rx_init(struct dc_softc *sc) 2427 { 2428 struct dc_chain_data *cd; 2429 struct dc_list_data *ld; 2430 int i, nexti; 2431 2432 cd = &sc->dc_cdata; 2433 ld = sc->dc_ldata; 2434 2435 for (i = 0; i < DC_RX_LIST_CNT; i++) { 2436 if (dc_newbuf(sc, i, 1) != 0) 2437 return (ENOBUFS); 2438 if (i == DC_RX_LIST_CNT - 1) 2439 nexti = 0; 2440 else 2441 nexti = i + 1; 2442 ld->dc_rx_list[i].dc_next = htole32(DC_RXDESC(sc, nexti)); 2443 } 2444 2445 cd->dc_rx_prod = 0; 2446 bus_dmamap_sync(sc->dc_ltag, sc->dc_lmap, 2447 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2448 return (0); 2449 } 2450 2451 static void 2452 dc_dma_map_rxbuf(arg, segs, nseg, mapsize, error) 2453 void *arg; 2454 bus_dma_segment_t *segs; 2455 int nseg; 2456 bus_size_t mapsize; 2457 int error; 2458 { 2459 struct dc_softc *sc; 2460 struct dc_desc *c; 2461 2462 sc = arg; 2463 c = &sc->dc_ldata->dc_rx_list[sc->dc_cdata.dc_rx_cur]; 2464 if (error) { 2465 sc->dc_cdata.dc_rx_err = error; 2466 return; 2467 } 2468 2469 KASSERT(nseg == 1, ("wrong number of segments, should be 1")); 2470 sc->dc_cdata.dc_rx_err = 0; 2471 c->dc_data = htole32(segs->ds_addr); 2472 } 2473 2474 /* 2475 * Initialize an RX descriptor and attach an MBUF cluster. 2476 */ 2477 static int 2478 dc_newbuf(struct dc_softc *sc, int i, int alloc) 2479 { 2480 struct mbuf *m_new; 2481 bus_dmamap_t tmp; 2482 int error; 2483 2484 if (alloc) { 2485 m_new = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR); 2486 if (m_new == NULL) 2487 return (ENOBUFS); 2488 } else { 2489 m_new = sc->dc_cdata.dc_rx_chain[i]; 2490 m_new->m_data = m_new->m_ext.ext_buf; 2491 } 2492 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 2493 m_adj(m_new, sizeof(u_int64_t)); 2494 2495 /* 2496 * If this is a PNIC chip, zero the buffer. This is part 2497 * of the workaround for the receive bug in the 82c168 and 2498 * 82c169 chips. 2499 */ 2500 if (sc->dc_flags & DC_PNIC_RX_BUG_WAR) 2501 bzero(mtod(m_new, char *), m_new->m_len); 2502 2503 /* No need to remap the mbuf if we're reusing it. */ 2504 if (alloc) { 2505 sc->dc_cdata.dc_rx_cur = i; 2506 error = bus_dmamap_load_mbuf(sc->dc_mtag, sc->dc_sparemap, 2507 m_new, dc_dma_map_rxbuf, sc, 0); 2508 if (error) { 2509 m_freem(m_new); 2510 return (error); 2511 } 2512 if (sc->dc_cdata.dc_rx_err != 0) { 2513 m_freem(m_new); 2514 return (sc->dc_cdata.dc_rx_err); 2515 } 2516 bus_dmamap_unload(sc->dc_mtag, sc->dc_cdata.dc_rx_map[i]); 2517 tmp = sc->dc_cdata.dc_rx_map[i]; 2518 sc->dc_cdata.dc_rx_map[i] = sc->dc_sparemap; 2519 sc->dc_sparemap = tmp; 2520 sc->dc_cdata.dc_rx_chain[i] = m_new; 2521 } 2522 2523 sc->dc_ldata->dc_rx_list[i].dc_ctl = htole32(DC_RXCTL_RLINK | DC_RXLEN); 2524 sc->dc_ldata->dc_rx_list[i].dc_status = htole32(DC_RXSTAT_OWN); 2525 bus_dmamap_sync(sc->dc_mtag, sc->dc_cdata.dc_rx_map[i], 2526 BUS_DMASYNC_PREREAD); 2527 bus_dmamap_sync(sc->dc_ltag, sc->dc_lmap, 2528 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2529 return (0); 2530 } 2531 2532 /* 2533 * Grrrrr. 2534 * The PNIC chip has a terrible bug in it that manifests itself during 2535 * periods of heavy activity. The exact mode of failure if difficult to 2536 * pinpoint: sometimes it only happens in promiscuous mode, sometimes it 2537 * will happen on slow machines. The bug is that sometimes instead of 2538 * uploading one complete frame during reception, it uploads what looks 2539 * like the entire contents of its FIFO memory. The frame we want is at 2540 * the end of the whole mess, but we never know exactly how much data has 2541 * been uploaded, so salvaging the frame is hard. 2542 * 2543 * There is only one way to do it reliably, and it's disgusting. 2544 * Here's what we know: 2545 * 2546 * - We know there will always be somewhere between one and three extra 2547 * descriptors uploaded. 2548 * 2549 * - We know the desired received frame will always be at the end of the 2550 * total data upload. 2551 * 2552 * - We know the size of the desired received frame because it will be 2553 * provided in the length field of the status word in the last descriptor. 2554 * 2555 * Here's what we do: 2556 * 2557 * - When we allocate buffers for the receive ring, we bzero() them. 2558 * This means that we know that the buffer contents should be all 2559 * zeros, except for data uploaded by the chip. 2560 * 2561 * - We also force the PNIC chip to upload frames that include the 2562 * ethernet CRC at the end. 2563 * 2564 * - We gather all of the bogus frame data into a single buffer. 2565 * 2566 * - We then position a pointer at the end of this buffer and scan 2567 * backwards until we encounter the first non-zero byte of data. 2568 * This is the end of the received frame. We know we will encounter 2569 * some data at the end of the frame because the CRC will always be 2570 * there, so even if the sender transmits a packet of all zeros, 2571 * we won't be fooled. 2572 * 2573 * - We know the size of the actual received frame, so we subtract 2574 * that value from the current pointer location. This brings us 2575 * to the start of the actual received packet. 2576 * 2577 * - We copy this into an mbuf and pass it on, along with the actual 2578 * frame length. 2579 * 2580 * The performance hit is tremendous, but it beats dropping frames all 2581 * the time. 2582 */ 2583 2584 #define DC_WHOLEFRAME (DC_RXSTAT_FIRSTFRAG | DC_RXSTAT_LASTFRAG) 2585 static void 2586 dc_pnic_rx_bug_war(struct dc_softc *sc, int idx) 2587 { 2588 struct dc_desc *cur_rx; 2589 struct dc_desc *c = NULL; 2590 struct mbuf *m = NULL; 2591 unsigned char *ptr; 2592 int i, total_len; 2593 u_int32_t rxstat = 0; 2594 2595 i = sc->dc_pnic_rx_bug_save; 2596 cur_rx = &sc->dc_ldata->dc_rx_list[idx]; 2597 ptr = sc->dc_pnic_rx_buf; 2598 bzero(ptr, DC_RXLEN * 5); 2599 2600 /* Copy all the bytes from the bogus buffers. */ 2601 while (1) { 2602 c = &sc->dc_ldata->dc_rx_list[i]; 2603 rxstat = le32toh(c->dc_status); 2604 m = sc->dc_cdata.dc_rx_chain[i]; 2605 bcopy(mtod(m, char *), ptr, DC_RXLEN); 2606 ptr += DC_RXLEN; 2607 /* If this is the last buffer, break out. */ 2608 if (i == idx || rxstat & DC_RXSTAT_LASTFRAG) 2609 break; 2610 dc_newbuf(sc, i, 0); 2611 DC_INC(i, DC_RX_LIST_CNT); 2612 } 2613 2614 /* Find the length of the actual receive frame. */ 2615 total_len = DC_RXBYTES(rxstat); 2616 2617 /* Scan backwards until we hit a non-zero byte. */ 2618 while (*ptr == 0x00) 2619 ptr--; 2620 2621 /* Round off. */ 2622 if ((uintptr_t)(ptr) & 0x3) 2623 ptr -= 1; 2624 2625 /* Now find the start of the frame. */ 2626 ptr -= total_len; 2627 if (ptr < sc->dc_pnic_rx_buf) 2628 ptr = sc->dc_pnic_rx_buf; 2629 2630 /* 2631 * Now copy the salvaged frame to the last mbuf and fake up 2632 * the status word to make it look like a successful 2633 * frame reception. 2634 */ 2635 dc_newbuf(sc, i, 0); 2636 bcopy(ptr, mtod(m, char *), total_len); 2637 cur_rx->dc_status = htole32(rxstat | DC_RXSTAT_FIRSTFRAG); 2638 } 2639 2640 /* 2641 * This routine searches the RX ring for dirty descriptors in the 2642 * event that the rxeof routine falls out of sync with the chip's 2643 * current descriptor pointer. This may happen sometimes as a result 2644 * of a "no RX buffer available" condition that happens when the chip 2645 * consumes all of the RX buffers before the driver has a chance to 2646 * process the RX ring. This routine may need to be called more than 2647 * once to bring the driver back in sync with the chip, however we 2648 * should still be getting RX DONE interrupts to drive the search 2649 * for new packets in the RX ring, so we should catch up eventually. 2650 */ 2651 static int 2652 dc_rx_resync(struct dc_softc *sc) 2653 { 2654 struct dc_desc *cur_rx; 2655 int i, pos; 2656 2657 pos = sc->dc_cdata.dc_rx_prod; 2658 2659 for (i = 0; i < DC_RX_LIST_CNT; i++) { 2660 cur_rx = &sc->dc_ldata->dc_rx_list[pos]; 2661 if (!(le32toh(cur_rx->dc_status) & DC_RXSTAT_OWN)) 2662 break; 2663 DC_INC(pos, DC_RX_LIST_CNT); 2664 } 2665 2666 /* If the ring really is empty, then just return. */ 2667 if (i == DC_RX_LIST_CNT) 2668 return (0); 2669 2670 /* We've fallen behing the chip: catch it. */ 2671 sc->dc_cdata.dc_rx_prod = pos; 2672 2673 return (EAGAIN); 2674 } 2675 2676 /* 2677 * A frame has been uploaded: pass the resulting mbuf chain up to 2678 * the higher level protocols. 2679 */ 2680 static void 2681 dc_rxeof(struct dc_softc *sc) 2682 { 2683 struct mbuf *m; 2684 struct ifnet *ifp; 2685 struct dc_desc *cur_rx; 2686 int i, total_len = 0; 2687 u_int32_t rxstat; 2688 2689 DC_LOCK_ASSERT(sc); 2690 2691 ifp = &sc->arpcom.ac_if; 2692 i = sc->dc_cdata.dc_rx_prod; 2693 2694 bus_dmamap_sync(sc->dc_ltag, sc->dc_lmap, BUS_DMASYNC_POSTREAD); 2695 while (!(le32toh(sc->dc_ldata->dc_rx_list[i].dc_status) & 2696 DC_RXSTAT_OWN)) { 2697 #ifdef DEVICE_POLLING 2698 if (ifp->if_flags & IFF_POLLING) { 2699 if (sc->rxcycles <= 0) 2700 break; 2701 sc->rxcycles--; 2702 } 2703 #endif 2704 cur_rx = &sc->dc_ldata->dc_rx_list[i]; 2705 rxstat = le32toh(cur_rx->dc_status); 2706 m = sc->dc_cdata.dc_rx_chain[i]; 2707 bus_dmamap_sync(sc->dc_mtag, sc->dc_cdata.dc_rx_map[i], 2708 BUS_DMASYNC_POSTREAD); 2709 total_len = DC_RXBYTES(rxstat); 2710 2711 if (sc->dc_flags & DC_PNIC_RX_BUG_WAR) { 2712 if ((rxstat & DC_WHOLEFRAME) != DC_WHOLEFRAME) { 2713 if (rxstat & DC_RXSTAT_FIRSTFRAG) 2714 sc->dc_pnic_rx_bug_save = i; 2715 if ((rxstat & DC_RXSTAT_LASTFRAG) == 0) { 2716 DC_INC(i, DC_RX_LIST_CNT); 2717 continue; 2718 } 2719 dc_pnic_rx_bug_war(sc, i); 2720 rxstat = le32toh(cur_rx->dc_status); 2721 total_len = DC_RXBYTES(rxstat); 2722 } 2723 } 2724 2725 /* 2726 * If an error occurs, update stats, clear the 2727 * status word and leave the mbuf cluster in place: 2728 * it should simply get re-used next time this descriptor 2729 * comes up in the ring. However, don't report long 2730 * frames as errors since they could be vlans. 2731 */ 2732 if ((rxstat & DC_RXSTAT_RXERR)) { 2733 if (!(rxstat & DC_RXSTAT_GIANT) || 2734 (rxstat & (DC_RXSTAT_CRCERR | DC_RXSTAT_DRIBBLE | 2735 DC_RXSTAT_MIIERE | DC_RXSTAT_COLLSEEN | 2736 DC_RXSTAT_RUNT | DC_RXSTAT_DE))) { 2737 ifp->if_ierrors++; 2738 if (rxstat & DC_RXSTAT_COLLSEEN) 2739 ifp->if_collisions++; 2740 dc_newbuf(sc, i, 0); 2741 if (rxstat & DC_RXSTAT_CRCERR) { 2742 DC_INC(i, DC_RX_LIST_CNT); 2743 continue; 2744 } else { 2745 dc_init(sc); 2746 return; 2747 } 2748 } 2749 } 2750 2751 /* No errors; receive the packet. */ 2752 total_len -= ETHER_CRC_LEN; 2753 #ifdef __i386__ 2754 /* 2755 * On the x86 we do not have alignment problems, so try to 2756 * allocate a new buffer for the receive ring, and pass up 2757 * the one where the packet is already, saving the expensive 2758 * copy done in m_devget(). 2759 * If we are on an architecture with alignment problems, or 2760 * if the allocation fails, then use m_devget and leave the 2761 * existing buffer in the receive ring. 2762 */ 2763 if (dc_quick && dc_newbuf(sc, i, 1) == 0) { 2764 m->m_pkthdr.rcvif = ifp; 2765 m->m_pkthdr.len = m->m_len = total_len; 2766 DC_INC(i, DC_RX_LIST_CNT); 2767 } else 2768 #endif 2769 { 2770 struct mbuf *m0; 2771 2772 m0 = m_devget(mtod(m, char *), total_len, 2773 ETHER_ALIGN, ifp, NULL); 2774 dc_newbuf(sc, i, 0); 2775 DC_INC(i, DC_RX_LIST_CNT); 2776 if (m0 == NULL) { 2777 ifp->if_ierrors++; 2778 continue; 2779 } 2780 m = m0; 2781 } 2782 2783 ifp->if_ipackets++; 2784 DC_UNLOCK(sc); 2785 (*ifp->if_input)(ifp, m); 2786 DC_LOCK(sc); 2787 } 2788 2789 sc->dc_cdata.dc_rx_prod = i; 2790 } 2791 2792 /* 2793 * A frame was downloaded to the chip. It's safe for us to clean up 2794 * the list buffers. 2795 */ 2796 2797 static void 2798 dc_txeof(struct dc_softc *sc) 2799 { 2800 struct dc_desc *cur_tx = NULL; 2801 struct ifnet *ifp; 2802 int idx; 2803 u_int32_t ctl, txstat; 2804 2805 ifp = &sc->arpcom.ac_if; 2806 2807 /* 2808 * Go through our tx list and free mbufs for those 2809 * frames that have been transmitted. 2810 */ 2811 bus_dmamap_sync(sc->dc_ltag, sc->dc_lmap, BUS_DMASYNC_POSTREAD); 2812 idx = sc->dc_cdata.dc_tx_cons; 2813 while (idx != sc->dc_cdata.dc_tx_prod) { 2814 2815 cur_tx = &sc->dc_ldata->dc_tx_list[idx]; 2816 txstat = le32toh(cur_tx->dc_status); 2817 ctl = le32toh(cur_tx->dc_ctl); 2818 2819 if (txstat & DC_TXSTAT_OWN) 2820 break; 2821 2822 if (!(ctl & DC_TXCTL_LASTFRAG) || ctl & DC_TXCTL_SETUP) { 2823 if (ctl & DC_TXCTL_SETUP) { 2824 /* 2825 * Yes, the PNIC is so brain damaged 2826 * that it will sometimes generate a TX 2827 * underrun error while DMAing the RX 2828 * filter setup frame. If we detect this, 2829 * we have to send the setup frame again, 2830 * or else the filter won't be programmed 2831 * correctly. 2832 */ 2833 if (DC_IS_PNIC(sc)) { 2834 if (txstat & DC_TXSTAT_ERRSUM) 2835 dc_setfilt(sc); 2836 } 2837 sc->dc_cdata.dc_tx_chain[idx] = NULL; 2838 } 2839 sc->dc_cdata.dc_tx_cnt--; 2840 DC_INC(idx, DC_TX_LIST_CNT); 2841 continue; 2842 } 2843 2844 if (DC_IS_XIRCOM(sc) || DC_IS_CONEXANT(sc)) { 2845 /* 2846 * XXX: Why does my Xircom taunt me so? 2847 * For some reason it likes setting the CARRLOST flag 2848 * even when the carrier is there. wtf?!? 2849 * Who knows, but Conexant chips have the 2850 * same problem. Maybe they took lessons 2851 * from Xircom. 2852 */ 2853 if (/*sc->dc_type == DC_TYPE_21143 &&*/ 2854 sc->dc_pmode == DC_PMODE_MII && 2855 ((txstat & 0xFFFF) & ~(DC_TXSTAT_ERRSUM | 2856 DC_TXSTAT_NOCARRIER))) 2857 txstat &= ~DC_TXSTAT_ERRSUM; 2858 } else { 2859 if (/*sc->dc_type == DC_TYPE_21143 &&*/ 2860 sc->dc_pmode == DC_PMODE_MII && 2861 ((txstat & 0xFFFF) & ~(DC_TXSTAT_ERRSUM | 2862 DC_TXSTAT_NOCARRIER | DC_TXSTAT_CARRLOST))) 2863 txstat &= ~DC_TXSTAT_ERRSUM; 2864 } 2865 2866 if (txstat & DC_TXSTAT_ERRSUM) { 2867 ifp->if_oerrors++; 2868 if (txstat & DC_TXSTAT_EXCESSCOLL) 2869 ifp->if_collisions++; 2870 if (txstat & DC_TXSTAT_LATECOLL) 2871 ifp->if_collisions++; 2872 if (!(txstat & DC_TXSTAT_UNDERRUN)) { 2873 dc_init(sc); 2874 return; 2875 } 2876 } 2877 2878 ifp->if_collisions += (txstat & DC_TXSTAT_COLLCNT) >> 3; 2879 2880 ifp->if_opackets++; 2881 if (sc->dc_cdata.dc_tx_chain[idx] != NULL) { 2882 bus_dmamap_sync(sc->dc_mtag, 2883 sc->dc_cdata.dc_tx_map[idx], 2884 BUS_DMASYNC_POSTWRITE); 2885 bus_dmamap_unload(sc->dc_mtag, 2886 sc->dc_cdata.dc_tx_map[idx]); 2887 m_freem(sc->dc_cdata.dc_tx_chain[idx]); 2888 sc->dc_cdata.dc_tx_chain[idx] = NULL; 2889 } 2890 2891 sc->dc_cdata.dc_tx_cnt--; 2892 DC_INC(idx, DC_TX_LIST_CNT); 2893 } 2894 2895 if (idx != sc->dc_cdata.dc_tx_cons) { 2896 /* Some buffers have been freed. */ 2897 sc->dc_cdata.dc_tx_cons = idx; 2898 ifp->if_flags &= ~IFF_OACTIVE; 2899 } 2900 ifp->if_timer = (sc->dc_cdata.dc_tx_cnt == 0) ? 0 : 5; 2901 } 2902 2903 static void 2904 dc_tick(void *xsc) 2905 { 2906 struct dc_softc *sc; 2907 struct mii_data *mii; 2908 struct ifnet *ifp; 2909 u_int32_t r; 2910 2911 sc = xsc; 2912 DC_LOCK(sc); 2913 ifp = &sc->arpcom.ac_if; 2914 mii = device_get_softc(sc->dc_miibus); 2915 2916 if (sc->dc_flags & DC_REDUCED_MII_POLL) { 2917 if (sc->dc_flags & DC_21143_NWAY) { 2918 r = CSR_READ_4(sc, DC_10BTSTAT); 2919 if (IFM_SUBTYPE(mii->mii_media_active) == 2920 IFM_100_TX && (r & DC_TSTAT_LS100)) { 2921 sc->dc_link = 0; 2922 mii_mediachg(mii); 2923 } 2924 if (IFM_SUBTYPE(mii->mii_media_active) == 2925 IFM_10_T && (r & DC_TSTAT_LS10)) { 2926 sc->dc_link = 0; 2927 mii_mediachg(mii); 2928 } 2929 if (sc->dc_link == 0) 2930 mii_tick(mii); 2931 } else { 2932 r = CSR_READ_4(sc, DC_ISR); 2933 if ((r & DC_ISR_RX_STATE) == DC_RXSTATE_WAIT && 2934 sc->dc_cdata.dc_tx_cnt == 0) { 2935 mii_tick(mii); 2936 if (!(mii->mii_media_status & IFM_ACTIVE)) 2937 sc->dc_link = 0; 2938 } 2939 } 2940 } else 2941 mii_tick(mii); 2942 2943 /* 2944 * When the init routine completes, we expect to be able to send 2945 * packets right away, and in fact the network code will send a 2946 * gratuitous ARP the moment the init routine marks the interface 2947 * as running. However, even though the MAC may have been initialized, 2948 * there may be a delay of a few seconds before the PHY completes 2949 * autonegotiation and the link is brought up. Any transmissions 2950 * made during that delay will be lost. Dealing with this is tricky: 2951 * we can't just pause in the init routine while waiting for the 2952 * PHY to come ready since that would bring the whole system to 2953 * a screeching halt for several seconds. 2954 * 2955 * What we do here is prevent the TX start routine from sending 2956 * any packets until a link has been established. After the 2957 * interface has been initialized, the tick routine will poll 2958 * the state of the PHY until the IFM_ACTIVE flag is set. Until 2959 * that time, packets will stay in the send queue, and once the 2960 * link comes up, they will be flushed out to the wire. 2961 */ 2962 if (!sc->dc_link && mii->mii_media_status & IFM_ACTIVE && 2963 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) { 2964 sc->dc_link++; 2965 if (ifp->if_snd.ifq_head != NULL) 2966 dc_start(ifp); 2967 } 2968 2969 if (sc->dc_flags & DC_21143_NWAY && !sc->dc_link) 2970 callout_reset(&sc->dc_stat_ch, hz/10, dc_tick, sc); 2971 else 2972 callout_reset(&sc->dc_stat_ch, hz, dc_tick, sc); 2973 2974 DC_UNLOCK(sc); 2975 } 2976 2977 /* 2978 * A transmit underrun has occurred. Back off the transmit threshold, 2979 * or switch to store and forward mode if we have to. 2980 */ 2981 static void 2982 dc_tx_underrun(struct dc_softc *sc) 2983 { 2984 u_int32_t isr; 2985 int i; 2986 2987 if (DC_IS_DAVICOM(sc)) 2988 dc_init(sc); 2989 2990 if (DC_IS_INTEL(sc)) { 2991 /* 2992 * The real 21143 requires that the transmitter be idle 2993 * in order to change the transmit threshold or store 2994 * and forward state. 2995 */ 2996 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_TX_ON); 2997 2998 for (i = 0; i < DC_TIMEOUT; i++) { 2999 isr = CSR_READ_4(sc, DC_ISR); 3000 if (isr & DC_ISR_TX_IDLE) 3001 break; 3002 DELAY(10); 3003 } 3004 if (i == DC_TIMEOUT) { 3005 printf("dc%d: failed to force tx to idle state\n", 3006 sc->dc_unit); 3007 dc_init(sc); 3008 } 3009 } 3010 3011 printf("dc%d: TX underrun -- ", sc->dc_unit); 3012 sc->dc_txthresh += DC_TXTHRESH_INC; 3013 if (sc->dc_txthresh > DC_TXTHRESH_MAX) { 3014 printf("using store and forward mode\n"); 3015 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_STORENFWD); 3016 } else { 3017 printf("increasing TX threshold\n"); 3018 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_TX_THRESH); 3019 DC_SETBIT(sc, DC_NETCFG, sc->dc_txthresh); 3020 } 3021 3022 if (DC_IS_INTEL(sc)) 3023 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_TX_ON); 3024 } 3025 3026 #ifdef DEVICE_POLLING 3027 static poll_handler_t dc_poll; 3028 3029 static void 3030 dc_poll(struct ifnet *ifp, enum poll_cmd cmd, int count) 3031 { 3032 struct dc_softc *sc = ifp->if_softc; 3033 3034 if (!(ifp->if_capenable & IFCAP_POLLING)) { 3035 ether_poll_deregister(ifp); 3036 cmd = POLL_DEREGISTER; 3037 } 3038 if (cmd == POLL_DEREGISTER) { /* final call, enable interrupts */ 3039 /* Re-enable interrupts. */ 3040 CSR_WRITE_4(sc, DC_IMR, DC_INTRS); 3041 return; 3042 } 3043 DC_LOCK(sc); 3044 sc->rxcycles = count; 3045 dc_rxeof(sc); 3046 dc_txeof(sc); 3047 if (ifp->if_snd.ifq_head != NULL && !(ifp->if_flags & IFF_OACTIVE)) 3048 dc_start(ifp); 3049 3050 if (cmd == POLL_AND_CHECK_STATUS) { /* also check status register */ 3051 u_int32_t status; 3052 3053 status = CSR_READ_4(sc, DC_ISR); 3054 status &= (DC_ISR_RX_WATDOGTIMEO | DC_ISR_RX_NOBUF | 3055 DC_ISR_TX_NOBUF | DC_ISR_TX_IDLE | DC_ISR_TX_UNDERRUN | 3056 DC_ISR_BUS_ERR); 3057 if (!status) { 3058 DC_UNLOCK(sc); 3059 return; 3060 } 3061 /* ack what we have */ 3062 CSR_WRITE_4(sc, DC_ISR, status); 3063 3064 if (status & (DC_ISR_RX_WATDOGTIMEO | DC_ISR_RX_NOBUF)) { 3065 u_int32_t r = CSR_READ_4(sc, DC_FRAMESDISCARDED); 3066 ifp->if_ierrors += (r & 0xffff) + ((r >> 17) & 0x7ff); 3067 3068 if (dc_rx_resync(sc)) 3069 dc_rxeof(sc); 3070 } 3071 /* restart transmit unit if necessary */ 3072 if (status & DC_ISR_TX_IDLE && sc->dc_cdata.dc_tx_cnt) 3073 CSR_WRITE_4(sc, DC_TXSTART, 0xFFFFFFFF); 3074 3075 if (status & DC_ISR_TX_UNDERRUN) 3076 dc_tx_underrun(sc); 3077 3078 if (status & DC_ISR_BUS_ERR) { 3079 printf("dc_poll: dc%d bus error\n", sc->dc_unit); 3080 dc_reset(sc); 3081 dc_init(sc); 3082 } 3083 } 3084 DC_UNLOCK(sc); 3085 } 3086 #endif /* DEVICE_POLLING */ 3087 3088 static void 3089 dc_intr(void *arg) 3090 { 3091 struct dc_softc *sc; 3092 struct ifnet *ifp; 3093 u_int32_t status; 3094 3095 sc = arg; 3096 3097 if (sc->suspended) 3098 return; 3099 3100 if ((CSR_READ_4(sc, DC_ISR) & DC_INTRS) == 0) 3101 return; 3102 3103 DC_LOCK(sc); 3104 ifp = &sc->arpcom.ac_if; 3105 #ifdef DEVICE_POLLING 3106 if (ifp->if_flags & IFF_POLLING) 3107 goto done; 3108 if ((ifp->if_capenable & IFCAP_POLLING) && 3109 ether_poll_register(dc_poll, ifp)) { /* ok, disable interrupts */ 3110 CSR_WRITE_4(sc, DC_IMR, 0x00000000); 3111 goto done; 3112 } 3113 #endif 3114 3115 /* Suppress unwanted interrupts */ 3116 if (!(ifp->if_flags & IFF_UP)) { 3117 if (CSR_READ_4(sc, DC_ISR) & DC_INTRS) 3118 dc_stop(sc); 3119 DC_UNLOCK(sc); 3120 return; 3121 } 3122 3123 /* Disable interrupts. */ 3124 CSR_WRITE_4(sc, DC_IMR, 0x00000000); 3125 3126 while (((status = CSR_READ_4(sc, DC_ISR)) & DC_INTRS) 3127 && status != 0xFFFFFFFF) { 3128 3129 CSR_WRITE_4(sc, DC_ISR, status); 3130 3131 if (status & DC_ISR_RX_OK) { 3132 int curpkts; 3133 curpkts = ifp->if_ipackets; 3134 dc_rxeof(sc); 3135 if (curpkts == ifp->if_ipackets) { 3136 while (dc_rx_resync(sc)) 3137 dc_rxeof(sc); 3138 } 3139 } 3140 3141 if (status & (DC_ISR_TX_OK | DC_ISR_TX_NOBUF)) 3142 dc_txeof(sc); 3143 3144 if (status & DC_ISR_TX_IDLE) { 3145 dc_txeof(sc); 3146 if (sc->dc_cdata.dc_tx_cnt) { 3147 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_TX_ON); 3148 CSR_WRITE_4(sc, DC_TXSTART, 0xFFFFFFFF); 3149 } 3150 } 3151 3152 if (status & DC_ISR_TX_UNDERRUN) 3153 dc_tx_underrun(sc); 3154 3155 if ((status & DC_ISR_RX_WATDOGTIMEO) 3156 || (status & DC_ISR_RX_NOBUF)) { 3157 int curpkts; 3158 curpkts = ifp->if_ipackets; 3159 dc_rxeof(sc); 3160 if (curpkts == ifp->if_ipackets) { 3161 while (dc_rx_resync(sc)) 3162 dc_rxeof(sc); 3163 } 3164 } 3165 3166 if (status & DC_ISR_BUS_ERR) { 3167 dc_reset(sc); 3168 dc_init(sc); 3169 } 3170 } 3171 3172 /* Re-enable interrupts. */ 3173 CSR_WRITE_4(sc, DC_IMR, DC_INTRS); 3174 3175 if (ifp->if_snd.ifq_head != NULL) 3176 dc_start(ifp); 3177 3178 #ifdef DEVICE_POLLING 3179 done: 3180 #endif 3181 3182 DC_UNLOCK(sc); 3183 } 3184 3185 static void 3186 dc_dma_map_txbuf(arg, segs, nseg, mapsize, error) 3187 void *arg; 3188 bus_dma_segment_t *segs; 3189 int nseg; 3190 bus_size_t mapsize; 3191 int error; 3192 { 3193 struct dc_softc *sc; 3194 struct dc_desc *f; 3195 int cur, first, frag, i; 3196 3197 sc = arg; 3198 if (error) { 3199 sc->dc_cdata.dc_tx_err = error; 3200 return; 3201 } 3202 3203 first = cur = frag = sc->dc_cdata.dc_tx_prod; 3204 for (i = 0; i < nseg; i++) { 3205 if ((sc->dc_flags & DC_TX_ADMTEK_WAR) && 3206 (frag == (DC_TX_LIST_CNT - 1)) && 3207 (first != sc->dc_cdata.dc_tx_first)) { 3208 bus_dmamap_unload(sc->dc_mtag, 3209 sc->dc_cdata.dc_tx_map[first]); 3210 sc->dc_cdata.dc_tx_err = ENOBUFS; 3211 return; 3212 } 3213 3214 f = &sc->dc_ldata->dc_tx_list[frag]; 3215 f->dc_ctl = htole32(DC_TXCTL_TLINK | segs[i].ds_len); 3216 if (i == 0) { 3217 f->dc_status = 0; 3218 f->dc_ctl |= htole32(DC_TXCTL_FIRSTFRAG); 3219 } else 3220 f->dc_status = htole32(DC_TXSTAT_OWN); 3221 f->dc_data = htole32(segs[i].ds_addr); 3222 cur = frag; 3223 DC_INC(frag, DC_TX_LIST_CNT); 3224 } 3225 3226 sc->dc_cdata.dc_tx_err = 0; 3227 sc->dc_cdata.dc_tx_prod = frag; 3228 sc->dc_cdata.dc_tx_cnt += nseg; 3229 sc->dc_ldata->dc_tx_list[cur].dc_ctl |= htole32(DC_TXCTL_LASTFRAG); 3230 sc->dc_cdata.dc_tx_chain[cur] = sc->dc_cdata.dc_tx_mapping; 3231 if (sc->dc_flags & DC_TX_INTR_FIRSTFRAG) 3232 sc->dc_ldata->dc_tx_list[first].dc_ctl |= 3233 htole32(DC_TXCTL_FINT); 3234 if (sc->dc_flags & DC_TX_INTR_ALWAYS) 3235 sc->dc_ldata->dc_tx_list[cur].dc_ctl |= htole32(DC_TXCTL_FINT); 3236 if (sc->dc_flags & DC_TX_USE_TX_INTR && sc->dc_cdata.dc_tx_cnt > 64) 3237 sc->dc_ldata->dc_tx_list[cur].dc_ctl |= htole32(DC_TXCTL_FINT); 3238 sc->dc_ldata->dc_tx_list[first].dc_status = htole32(DC_TXSTAT_OWN); 3239 } 3240 3241 /* 3242 * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data 3243 * pointers to the fragment pointers. 3244 */ 3245 static int 3246 dc_encap(struct dc_softc *sc, struct mbuf **m_head) 3247 { 3248 struct mbuf *m; 3249 int error, idx, chainlen = 0; 3250 3251 /* 3252 * If there's no way we can send any packets, return now. 3253 */ 3254 if (DC_TX_LIST_CNT - sc->dc_cdata.dc_tx_cnt < 6) 3255 return (ENOBUFS); 3256 3257 /* 3258 * Count the number of frags in this chain to see if 3259 * we need to m_defrag. Since the descriptor list is shared 3260 * by all packets, we'll m_defrag long chains so that they 3261 * do not use up the entire list, even if they would fit. 3262 */ 3263 for (m = *m_head; m != NULL; m = m->m_next) 3264 chainlen++; 3265 3266 if ((chainlen > DC_TX_LIST_CNT / 4) || 3267 ((DC_TX_LIST_CNT - (chainlen + sc->dc_cdata.dc_tx_cnt)) < 6)) { 3268 m = m_defrag(*m_head, M_DONTWAIT); 3269 if (m == NULL) 3270 return (ENOBUFS); 3271 *m_head = m; 3272 } 3273 3274 /* 3275 * Start packing the mbufs in this chain into 3276 * the fragment pointers. Stop when we run out 3277 * of fragments or hit the end of the mbuf chain. 3278 */ 3279 idx = sc->dc_cdata.dc_tx_prod; 3280 sc->dc_cdata.dc_tx_mapping = *m_head; 3281 error = bus_dmamap_load_mbuf(sc->dc_mtag, sc->dc_cdata.dc_tx_map[idx], 3282 *m_head, dc_dma_map_txbuf, sc, 0); 3283 if (error) 3284 return (error); 3285 if (sc->dc_cdata.dc_tx_err != 0) 3286 return (sc->dc_cdata.dc_tx_err); 3287 bus_dmamap_sync(sc->dc_mtag, sc->dc_cdata.dc_tx_map[idx], 3288 BUS_DMASYNC_PREWRITE); 3289 bus_dmamap_sync(sc->dc_ltag, sc->dc_lmap, 3290 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3291 return (0); 3292 } 3293 3294 /* 3295 * Main transmit routine. To avoid having to do mbuf copies, we put pointers 3296 * to the mbuf data regions directly in the transmit lists. We also save a 3297 * copy of the pointers since the transmit list fragment pointers are 3298 * physical addresses. 3299 */ 3300 3301 static void 3302 dc_start(struct ifnet *ifp) 3303 { 3304 struct dc_softc *sc; 3305 struct mbuf *m_head = NULL, *m; 3306 int idx; 3307 3308 sc = ifp->if_softc; 3309 3310 DC_LOCK(sc); 3311 3312 if (!sc->dc_link && ifp->if_snd.ifq_len < 10) { 3313 DC_UNLOCK(sc); 3314 return; 3315 } 3316 3317 if (ifp->if_flags & IFF_OACTIVE) { 3318 DC_UNLOCK(sc); 3319 return; 3320 } 3321 3322 idx = sc->dc_cdata.dc_tx_first = sc->dc_cdata.dc_tx_prod; 3323 3324 while (sc->dc_cdata.dc_tx_chain[idx] == NULL) { 3325 IF_DEQUEUE(&ifp->if_snd, m_head); 3326 if (m_head == NULL) 3327 break; 3328 3329 if (sc->dc_flags & DC_TX_COALESCE && 3330 (m_head->m_next != NULL || 3331 sc->dc_flags & DC_TX_ALIGN)) { 3332 m = m_defrag(m_head, M_DONTWAIT); 3333 if (m == NULL) { 3334 IF_PREPEND(&ifp->if_snd, m_head); 3335 ifp->if_flags |= IFF_OACTIVE; 3336 break; 3337 } else { 3338 m_head = m; 3339 } 3340 } 3341 3342 if (dc_encap(sc, &m_head)) { 3343 IF_PREPEND(&ifp->if_snd, m_head); 3344 ifp->if_flags |= IFF_OACTIVE; 3345 break; 3346 } 3347 idx = sc->dc_cdata.dc_tx_prod; 3348 3349 /* 3350 * If there's a BPF listener, bounce a copy of this frame 3351 * to him. 3352 */ 3353 BPF_MTAP(ifp, m_head); 3354 3355 if (sc->dc_flags & DC_TX_ONE) { 3356 ifp->if_flags |= IFF_OACTIVE; 3357 break; 3358 } 3359 } 3360 3361 /* Transmit */ 3362 if (!(sc->dc_flags & DC_TX_POLL)) 3363 CSR_WRITE_4(sc, DC_TXSTART, 0xFFFFFFFF); 3364 3365 /* 3366 * Set a timeout in case the chip goes out to lunch. 3367 */ 3368 ifp->if_timer = 5; 3369 3370 DC_UNLOCK(sc); 3371 } 3372 3373 static void 3374 dc_init(void *xsc) 3375 { 3376 struct dc_softc *sc = xsc; 3377 struct ifnet *ifp = &sc->arpcom.ac_if; 3378 struct mii_data *mii; 3379 3380 DC_LOCK(sc); 3381 3382 mii = device_get_softc(sc->dc_miibus); 3383 3384 /* 3385 * Cancel pending I/O and free all RX/TX buffers. 3386 */ 3387 dc_stop(sc); 3388 dc_reset(sc); 3389 3390 /* 3391 * Set cache alignment and burst length. 3392 */ 3393 if (DC_IS_ASIX(sc) || DC_IS_DAVICOM(sc)) 3394 CSR_WRITE_4(sc, DC_BUSCTL, 0); 3395 else 3396 CSR_WRITE_4(sc, DC_BUSCTL, DC_BUSCTL_MRME | DC_BUSCTL_MRLE); 3397 /* 3398 * Evenly share the bus between receive and transmit process. 3399 */ 3400 if (DC_IS_INTEL(sc)) 3401 DC_SETBIT(sc, DC_BUSCTL, DC_BUSCTL_ARBITRATION); 3402 if (DC_IS_DAVICOM(sc) || DC_IS_INTEL(sc)) { 3403 DC_SETBIT(sc, DC_BUSCTL, DC_BURSTLEN_USECA); 3404 } else { 3405 DC_SETBIT(sc, DC_BUSCTL, DC_BURSTLEN_16LONG); 3406 } 3407 if (sc->dc_flags & DC_TX_POLL) 3408 DC_SETBIT(sc, DC_BUSCTL, DC_TXPOLL_1); 3409 switch(sc->dc_cachesize) { 3410 case 32: 3411 DC_SETBIT(sc, DC_BUSCTL, DC_CACHEALIGN_32LONG); 3412 break; 3413 case 16: 3414 DC_SETBIT(sc, DC_BUSCTL, DC_CACHEALIGN_16LONG); 3415 break; 3416 case 8: 3417 DC_SETBIT(sc, DC_BUSCTL, DC_CACHEALIGN_8LONG); 3418 break; 3419 case 0: 3420 default: 3421 DC_SETBIT(sc, DC_BUSCTL, DC_CACHEALIGN_NONE); 3422 break; 3423 } 3424 3425 if (sc->dc_flags & DC_TX_STORENFWD) 3426 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_STORENFWD); 3427 else { 3428 if (sc->dc_txthresh > DC_TXTHRESH_MAX) { 3429 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_STORENFWD); 3430 } else { 3431 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_STORENFWD); 3432 DC_SETBIT(sc, DC_NETCFG, sc->dc_txthresh); 3433 } 3434 } 3435 3436 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_NO_RXCRC); 3437 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_TX_BACKOFF); 3438 3439 if (DC_IS_MACRONIX(sc) || DC_IS_PNICII(sc)) { 3440 /* 3441 * The app notes for the 98713 and 98715A say that 3442 * in order to have the chips operate properly, a magic 3443 * number must be written to CSR16. Macronix does not 3444 * document the meaning of these bits so there's no way 3445 * to know exactly what they do. The 98713 has a magic 3446 * number all its own; the rest all use a different one. 3447 */ 3448 DC_CLRBIT(sc, DC_MX_MAGICPACKET, 0xFFFF0000); 3449 if (sc->dc_type == DC_TYPE_98713) 3450 DC_SETBIT(sc, DC_MX_MAGICPACKET, DC_MX_MAGIC_98713); 3451 else 3452 DC_SETBIT(sc, DC_MX_MAGICPACKET, DC_MX_MAGIC_98715); 3453 } 3454 3455 if (DC_IS_XIRCOM(sc)) { 3456 /* 3457 * setup General Purpose Port mode and data so the tulip 3458 * can talk to the MII. 3459 */ 3460 CSR_WRITE_4(sc, DC_SIAGP, DC_SIAGP_WRITE_EN | DC_SIAGP_INT1_EN | 3461 DC_SIAGP_MD_GP2_OUTPUT | DC_SIAGP_MD_GP0_OUTPUT); 3462 DELAY(10); 3463 CSR_WRITE_4(sc, DC_SIAGP, DC_SIAGP_INT1_EN | 3464 DC_SIAGP_MD_GP2_OUTPUT | DC_SIAGP_MD_GP0_OUTPUT); 3465 DELAY(10); 3466 } 3467 3468 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_TX_THRESH); 3469 DC_SETBIT(sc, DC_NETCFG, DC_TXTHRESH_MIN); 3470 3471 /* Init circular RX list. */ 3472 if (dc_list_rx_init(sc) == ENOBUFS) { 3473 printf("dc%d: initialization failed: no " 3474 "memory for rx buffers\n", sc->dc_unit); 3475 dc_stop(sc); 3476 DC_UNLOCK(sc); 3477 return; 3478 } 3479 3480 /* 3481 * Init TX descriptors. 3482 */ 3483 dc_list_tx_init(sc); 3484 3485 /* 3486 * Load the address of the RX list. 3487 */ 3488 CSR_WRITE_4(sc, DC_RXADDR, DC_RXDESC(sc, 0)); 3489 CSR_WRITE_4(sc, DC_TXADDR, DC_TXDESC(sc, 0)); 3490 3491 /* 3492 * Enable interrupts. 3493 */ 3494 #ifdef DEVICE_POLLING 3495 /* 3496 * ... but only if we are not polling, and make sure they are off in 3497 * the case of polling. Some cards (e.g. fxp) turn interrupts on 3498 * after a reset. 3499 */ 3500 if (ifp->if_flags & IFF_POLLING) 3501 CSR_WRITE_4(sc, DC_IMR, 0x00000000); 3502 else 3503 #endif 3504 CSR_WRITE_4(sc, DC_IMR, DC_INTRS); 3505 CSR_WRITE_4(sc, DC_ISR, 0xFFFFFFFF); 3506 3507 /* Enable transmitter. */ 3508 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_TX_ON); 3509 3510 /* 3511 * If this is an Intel 21143 and we're not using the 3512 * MII port, program the LED control pins so we get 3513 * link and activity indications. 3514 */ 3515 if (sc->dc_flags & DC_TULIP_LEDS) { 3516 CSR_WRITE_4(sc, DC_WATCHDOG, 3517 DC_WDOG_CTLWREN | DC_WDOG_LINK | DC_WDOG_ACTIVITY); 3518 CSR_WRITE_4(sc, DC_WATCHDOG, 0); 3519 } 3520 3521 /* 3522 * Load the RX/multicast filter. We do this sort of late 3523 * because the filter programming scheme on the 21143 and 3524 * some clones requires DMAing a setup frame via the TX 3525 * engine, and we need the transmitter enabled for that. 3526 */ 3527 dc_setfilt(sc); 3528 3529 /* Enable receiver. */ 3530 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_ON); 3531 CSR_WRITE_4(sc, DC_RXSTART, 0xFFFFFFFF); 3532 3533 mii_mediachg(mii); 3534 dc_setcfg(sc, sc->dc_if_media); 3535 3536 ifp->if_flags |= IFF_RUNNING; 3537 ifp->if_flags &= ~IFF_OACTIVE; 3538 3539 /* Don't start the ticker if this is a homePNA link. */ 3540 if (IFM_SUBTYPE(mii->mii_media.ifm_media) == IFM_HPNA_1) 3541 sc->dc_link = 1; 3542 else { 3543 if (sc->dc_flags & DC_21143_NWAY) 3544 callout_reset(&sc->dc_stat_ch, hz/10, dc_tick, sc); 3545 else 3546 callout_reset(&sc->dc_stat_ch, hz, dc_tick, sc); 3547 } 3548 3549 #ifdef SRM_MEDIA 3550 if(sc->dc_srm_media) { 3551 struct ifreq ifr; 3552 3553 ifr.ifr_media = sc->dc_srm_media; 3554 ifmedia_ioctl(ifp, &ifr, &mii->mii_media, SIOCSIFMEDIA); 3555 sc->dc_srm_media = 0; 3556 } 3557 #endif 3558 DC_UNLOCK(sc); 3559 } 3560 3561 /* 3562 * Set media options. 3563 */ 3564 static int 3565 dc_ifmedia_upd(struct ifnet *ifp) 3566 { 3567 struct dc_softc *sc; 3568 struct mii_data *mii; 3569 struct ifmedia *ifm; 3570 3571 sc = ifp->if_softc; 3572 mii = device_get_softc(sc->dc_miibus); 3573 mii_mediachg(mii); 3574 ifm = &mii->mii_media; 3575 3576 if (DC_IS_DAVICOM(sc) && 3577 IFM_SUBTYPE(ifm->ifm_media) == IFM_HPNA_1) 3578 dc_setcfg(sc, ifm->ifm_media); 3579 else 3580 sc->dc_link = 0; 3581 3582 return (0); 3583 } 3584 3585 /* 3586 * Report current media status. 3587 */ 3588 static void 3589 dc_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 3590 { 3591 struct dc_softc *sc; 3592 struct mii_data *mii; 3593 struct ifmedia *ifm; 3594 3595 sc = ifp->if_softc; 3596 mii = device_get_softc(sc->dc_miibus); 3597 mii_pollstat(mii); 3598 ifm = &mii->mii_media; 3599 if (DC_IS_DAVICOM(sc)) { 3600 if (IFM_SUBTYPE(ifm->ifm_media) == IFM_HPNA_1) { 3601 ifmr->ifm_active = ifm->ifm_media; 3602 ifmr->ifm_status = 0; 3603 return; 3604 } 3605 } 3606 ifmr->ifm_active = mii->mii_media_active; 3607 ifmr->ifm_status = mii->mii_media_status; 3608 } 3609 3610 static int 3611 dc_ioctl(struct ifnet *ifp, u_long command, caddr_t data) 3612 { 3613 struct dc_softc *sc = ifp->if_softc; 3614 struct ifreq *ifr = (struct ifreq *)data; 3615 struct mii_data *mii; 3616 int error = 0; 3617 3618 DC_LOCK(sc); 3619 3620 switch (command) { 3621 case SIOCSIFFLAGS: 3622 if (ifp->if_flags & IFF_UP) { 3623 int need_setfilt = (ifp->if_flags ^ sc->dc_if_flags) & 3624 (IFF_PROMISC | IFF_ALLMULTI); 3625 3626 if (ifp->if_flags & IFF_RUNNING) { 3627 if (need_setfilt) 3628 dc_setfilt(sc); 3629 } else { 3630 sc->dc_txthresh = 0; 3631 dc_init(sc); 3632 } 3633 } else { 3634 if (ifp->if_flags & IFF_RUNNING) 3635 dc_stop(sc); 3636 } 3637 sc->dc_if_flags = ifp->if_flags; 3638 error = 0; 3639 break; 3640 case SIOCADDMULTI: 3641 case SIOCDELMULTI: 3642 dc_setfilt(sc); 3643 error = 0; 3644 break; 3645 case SIOCGIFMEDIA: 3646 case SIOCSIFMEDIA: 3647 mii = device_get_softc(sc->dc_miibus); 3648 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 3649 #ifdef SRM_MEDIA 3650 if (sc->dc_srm_media) 3651 sc->dc_srm_media = 0; 3652 #endif 3653 break; 3654 case SIOCSIFCAP: 3655 ifp->if_capenable &= ~IFCAP_POLLING; 3656 ifp->if_capenable |= ifr->ifr_reqcap & IFCAP_POLLING; 3657 break; 3658 default: 3659 error = ether_ioctl(ifp, command, data); 3660 break; 3661 } 3662 3663 DC_UNLOCK(sc); 3664 3665 return (error); 3666 } 3667 3668 static void 3669 dc_watchdog(struct ifnet *ifp) 3670 { 3671 struct dc_softc *sc; 3672 3673 sc = ifp->if_softc; 3674 3675 DC_LOCK(sc); 3676 3677 ifp->if_oerrors++; 3678 printf("dc%d: watchdog timeout\n", sc->dc_unit); 3679 3680 dc_stop(sc); 3681 dc_reset(sc); 3682 dc_init(sc); 3683 3684 if (ifp->if_snd.ifq_head != NULL) 3685 dc_start(ifp); 3686 3687 DC_UNLOCK(sc); 3688 } 3689 3690 /* 3691 * Stop the adapter and free any mbufs allocated to the 3692 * RX and TX lists. 3693 */ 3694 static void 3695 dc_stop(struct dc_softc *sc) 3696 { 3697 struct ifnet *ifp; 3698 struct dc_list_data *ld; 3699 struct dc_chain_data *cd; 3700 int i; 3701 u_int32_t ctl; 3702 3703 DC_LOCK(sc); 3704 3705 ifp = &sc->arpcom.ac_if; 3706 ifp->if_timer = 0; 3707 ld = sc->dc_ldata; 3708 cd = &sc->dc_cdata; 3709 3710 callout_stop(&sc->dc_stat_ch); 3711 3712 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 3713 #ifdef DEVICE_POLLING 3714 ether_poll_deregister(ifp); 3715 #endif 3716 3717 DC_CLRBIT(sc, DC_NETCFG, (DC_NETCFG_RX_ON | DC_NETCFG_TX_ON)); 3718 CSR_WRITE_4(sc, DC_IMR, 0x00000000); 3719 CSR_WRITE_4(sc, DC_TXADDR, 0x00000000); 3720 CSR_WRITE_4(sc, DC_RXADDR, 0x00000000); 3721 sc->dc_link = 0; 3722 3723 /* 3724 * Free data in the RX lists. 3725 */ 3726 for (i = 0; i < DC_RX_LIST_CNT; i++) { 3727 if (cd->dc_rx_chain[i] != NULL) { 3728 m_freem(cd->dc_rx_chain[i]); 3729 cd->dc_rx_chain[i] = NULL; 3730 } 3731 } 3732 bzero(&ld->dc_rx_list, sizeof(ld->dc_rx_list)); 3733 3734 /* 3735 * Free the TX list buffers. 3736 */ 3737 for (i = 0; i < DC_TX_LIST_CNT; i++) { 3738 if (cd->dc_tx_chain[i] != NULL) { 3739 ctl = le32toh(ld->dc_tx_list[i].dc_ctl); 3740 if ((ctl & DC_TXCTL_SETUP) || 3741 !(ctl & DC_TXCTL_LASTFRAG)) { 3742 cd->dc_tx_chain[i] = NULL; 3743 continue; 3744 } 3745 bus_dmamap_unload(sc->dc_mtag, cd->dc_tx_map[i]); 3746 m_freem(cd->dc_tx_chain[i]); 3747 cd->dc_tx_chain[i] = NULL; 3748 } 3749 } 3750 bzero(&ld->dc_tx_list, sizeof(ld->dc_tx_list)); 3751 3752 DC_UNLOCK(sc); 3753 } 3754 3755 /* 3756 * Device suspend routine. Stop the interface and save some PCI 3757 * settings in case the BIOS doesn't restore them properly on 3758 * resume. 3759 */ 3760 static int 3761 dc_suspend(device_t dev) 3762 { 3763 struct dc_softc *sc; 3764 int s; 3765 3766 s = splimp(); 3767 3768 sc = device_get_softc(dev); 3769 dc_stop(sc); 3770 sc->suspended = 1; 3771 3772 splx(s); 3773 return (0); 3774 } 3775 3776 /* 3777 * Device resume routine. Restore some PCI settings in case the BIOS 3778 * doesn't, re-enable busmastering, and restart the interface if 3779 * appropriate. 3780 */ 3781 static int 3782 dc_resume(device_t dev) 3783 { 3784 struct dc_softc *sc; 3785 struct ifnet *ifp; 3786 int s; 3787 3788 s = splimp(); 3789 3790 sc = device_get_softc(dev); 3791 ifp = &sc->arpcom.ac_if; 3792 3793 /* reinitialize interface if necessary */ 3794 if (ifp->if_flags & IFF_UP) 3795 dc_init(sc); 3796 3797 sc->suspended = 0; 3798 3799 splx(s); 3800 return (0); 3801 } 3802 3803 /* 3804 * Stop all chip I/O so that the kernel's probe routines don't 3805 * get confused by errant DMAs when rebooting. 3806 */ 3807 static void 3808 dc_shutdown(device_t dev) 3809 { 3810 struct dc_softc *sc; 3811 3812 sc = device_get_softc(dev); 3813 3814 dc_stop(sc); 3815 } 3816