1 /* 2 * Copyright (c) 1997, 1998, 1999 3 * Bill Paul <wpaul@ee.columbia.edu>. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 3. All advertising materials mentioning features or use of this software 14 * must display the following acknowledgement: 15 * This product includes software developed by Bill Paul. 16 * 4. Neither the name of the author nor the names of any co-contributors 17 * may be used to endorse or promote products derived from this software 18 * without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30 * THE POSSIBILITY OF SUCH DAMAGE. 31 * 32 * $FreeBSD$ 33 */ 34 35 /* 36 * DEC "tulip" clone ethernet driver. Supports the DEC/Intel 21143 37 * series chips and several workalikes including the following: 38 * 39 * Macronix 98713/98715/98725/98727/98732 PMAC (www.macronix.com) 40 * Macronix/Lite-On 82c115 PNIC II (www.macronix.com) 41 * Lite-On 82c168/82c169 PNIC (www.litecom.com) 42 * ASIX Electronics AX88140A (www.asix.com.tw) 43 * ASIX Electronics AX88141 (www.asix.com.tw) 44 * ADMtek AL981 (www.admtek.com.tw) 45 * ADMtek AN985 (www.admtek.com.tw) 46 * Davicom DM9100, DM9102, DM9102A (www.davicom8.com) 47 * Accton EN1217 (www.accton.com) 48 * Xircom X3201 (www.xircom.com) 49 * Abocom FE2500 50 * Conexant LANfinity (www.conexant.com) 51 * 52 * Datasheets for the 21143 are available at developer.intel.com. 53 * Datasheets for the clone parts can be found at their respective sites. 54 * (Except for the PNIC; see www.freebsd.org/~wpaul/PNIC/pnic.ps.gz.) 55 * The PNIC II is essentially a Macronix 98715A chip; the only difference 56 * worth noting is that its multicast hash table is only 128 bits wide 57 * instead of 512. 58 * 59 * Written by Bill Paul <wpaul@ee.columbia.edu> 60 * Electrical Engineering Department 61 * Columbia University, New York City 62 */ 63 64 /* 65 * The Intel 21143 is the successor to the DEC 21140. It is basically 66 * the same as the 21140 but with a few new features. The 21143 supports 67 * three kinds of media attachments: 68 * 69 * o MII port, for 10Mbps and 100Mbps support and NWAY 70 * autonegotiation provided by an external PHY. 71 * o SYM port, for symbol mode 100Mbps support. 72 * o 10baseT port. 73 * o AUI/BNC port. 74 * 75 * The 100Mbps SYM port and 10baseT port can be used together in 76 * combination with the internal NWAY support to create a 10/100 77 * autosensing configuration. 78 * 79 * Note that not all tulip workalikes are handled in this driver: we only 80 * deal with those which are relatively well behaved. The Winbond is 81 * handled separately due to its different register offsets and the 82 * special handling needed for its various bugs. The PNIC is handled 83 * here, but I'm not thrilled about it. 84 * 85 * All of the workalike chips use some form of MII transceiver support 86 * with the exception of the Macronix chips, which also have a SYM port. 87 * The ASIX AX88140A is also documented to have a SYM port, but all 88 * the cards I've seen use an MII transceiver, probably because the 89 * AX88140A doesn't support internal NWAY. 90 */ 91 92 #include <sys/param.h> 93 #include <sys/systm.h> 94 #include <sys/sockio.h> 95 #include <sys/mbuf.h> 96 #include <sys/malloc.h> 97 #include <sys/kernel.h> 98 #include <sys/socket.h> 99 #include <sys/sysctl.h> 100 101 #include <net/if.h> 102 #include <net/if_arp.h> 103 #include <net/ethernet.h> 104 #include <net/if_dl.h> 105 #include <net/if_media.h> 106 #include <net/if_types.h> 107 #include <net/if_vlan_var.h> 108 109 #include <net/bpf.h> 110 111 #include <vm/vm.h> /* for vtophys */ 112 #include <vm/pmap.h> /* for vtophys */ 113 #include <machine/bus_pio.h> 114 #include <machine/bus_memio.h> 115 #include <machine/bus.h> 116 #include <machine/resource.h> 117 #include <sys/bus.h> 118 #include <sys/rman.h> 119 120 #include <dev/mii/mii.h> 121 #include <dev/mii/miivar.h> 122 123 #include <pci/pcireg.h> 124 #include <pci/pcivar.h> 125 126 #define DC_USEIOSPACE 127 #ifdef __alpha__ 128 #define SRM_MEDIA 129 #endif 130 131 #include <pci/if_dcreg.h> 132 133 MODULE_DEPEND(dc, miibus, 1, 1, 1); 134 135 /* "controller miibus0" required. See GENERIC if you get errors here. */ 136 #include "miibus_if.h" 137 138 #ifndef lint 139 static const char rcsid[] = 140 "$FreeBSD$"; 141 #endif 142 143 /* 144 * Various supported device vendors/types and their names. 145 */ 146 static struct dc_type dc_devs[] = { 147 { DC_VENDORID_DEC, DC_DEVICEID_21143, 148 "Intel 21143 10/100BaseTX" }, 149 { DC_VENDORID_DAVICOM, DC_DEVICEID_DM9100, 150 "Davicom DM9100 10/100BaseTX" }, 151 { DC_VENDORID_DAVICOM, DC_DEVICEID_DM9102, 152 "Davicom DM9102 10/100BaseTX" }, 153 { DC_VENDORID_DAVICOM, DC_DEVICEID_DM9102, 154 "Davicom DM9102A 10/100BaseTX" }, 155 { DC_VENDORID_ADMTEK, DC_DEVICEID_AL981, 156 "ADMtek AL981 10/100BaseTX" }, 157 { DC_VENDORID_ADMTEK, DC_DEVICEID_AN985, 158 "ADMtek AN985 10/100BaseTX" }, 159 { DC_VENDORID_ASIX, DC_DEVICEID_AX88140A, 160 "ASIX AX88140A 10/100BaseTX" }, 161 { DC_VENDORID_ASIX, DC_DEVICEID_AX88140A, 162 "ASIX AX88141 10/100BaseTX" }, 163 { DC_VENDORID_MX, DC_DEVICEID_98713, 164 "Macronix 98713 10/100BaseTX" }, 165 { DC_VENDORID_MX, DC_DEVICEID_98713, 166 "Macronix 98713A 10/100BaseTX" }, 167 { DC_VENDORID_CP, DC_DEVICEID_98713_CP, 168 "Compex RL100-TX 10/100BaseTX" }, 169 { DC_VENDORID_CP, DC_DEVICEID_98713_CP, 170 "Compex RL100-TX 10/100BaseTX" }, 171 { DC_VENDORID_MX, DC_DEVICEID_987x5, 172 "Macronix 98715/98715A 10/100BaseTX" }, 173 { DC_VENDORID_MX, DC_DEVICEID_987x5, 174 "Macronix 98715AEC-C 10/100BaseTX" }, 175 { DC_VENDORID_MX, DC_DEVICEID_987x5, 176 "Macronix 98725 10/100BaseTX" }, 177 { DC_VENDORID_MX, DC_DEVICEID_98727, 178 "Macronix 98727/98732 10/100BaseTX" }, 179 { DC_VENDORID_LO, DC_DEVICEID_82C115, 180 "LC82C115 PNIC II 10/100BaseTX" }, 181 { DC_VENDORID_LO, DC_DEVICEID_82C168, 182 "82c168 PNIC 10/100BaseTX" }, 183 { DC_VENDORID_LO, DC_DEVICEID_82C168, 184 "82c169 PNIC 10/100BaseTX" }, 185 { DC_VENDORID_ACCTON, DC_DEVICEID_EN1217, 186 "Accton EN1217 10/100BaseTX" }, 187 { DC_VENDORID_ACCTON, DC_DEVICEID_EN2242, 188 "Accton EN2242 MiniPCI 10/100BaseTX" }, 189 { DC_VENDORID_XIRCOM, DC_DEVICEID_X3201, 190 "Xircom X3201 10/100BaseTX" }, 191 { DC_VENDORID_ABOCOM, DC_DEVICEID_FE2500, 192 "Abocom FE2500 10/100BaseTX" }, 193 { DC_VENDORID_CONEXANT, DC_DEVICEID_RS7112, 194 "Conexant LANfinity MiniPCI 10/100BaseTX" }, 195 { 0, 0, NULL } 196 }; 197 198 static int dc_probe (device_t); 199 static int dc_attach (device_t); 200 static int dc_detach (device_t); 201 static void dc_acpi (device_t); 202 static struct dc_type *dc_devtype (device_t); 203 static int dc_newbuf (struct dc_softc *, int, struct mbuf *); 204 static int dc_encap (struct dc_softc *, struct mbuf *, u_int32_t *); 205 static int dc_coal (struct dc_softc *, struct mbuf **); 206 static void dc_pnic_rx_bug_war (struct dc_softc *, int); 207 static int dc_rx_resync (struct dc_softc *); 208 static void dc_rxeof (struct dc_softc *); 209 static void dc_txeof (struct dc_softc *); 210 static void dc_tick (void *); 211 static void dc_tx_underrun (struct dc_softc *); 212 static void dc_intr (void *); 213 static void dc_start (struct ifnet *); 214 static int dc_ioctl (struct ifnet *, u_long, caddr_t); 215 static void dc_init (void *); 216 static void dc_stop (struct dc_softc *); 217 static void dc_watchdog (struct ifnet *); 218 static void dc_shutdown (device_t); 219 static int dc_ifmedia_upd (struct ifnet *); 220 static void dc_ifmedia_sts (struct ifnet *, struct ifmediareq *); 221 222 static void dc_delay (struct dc_softc *); 223 static void dc_eeprom_idle (struct dc_softc *); 224 static void dc_eeprom_putbyte (struct dc_softc *, int); 225 static void dc_eeprom_getword (struct dc_softc *, int, u_int16_t *); 226 static void dc_eeprom_getword_pnic 227 (struct dc_softc *, int, u_int16_t *); 228 static void dc_eeprom_getword_xircom 229 (struct dc_softc *, int, u_int16_t *); 230 static void dc_read_eeprom (struct dc_softc *, caddr_t, int, int, int); 231 232 static void dc_mii_writebit (struct dc_softc *, int); 233 static int dc_mii_readbit (struct dc_softc *); 234 static void dc_mii_sync (struct dc_softc *); 235 static void dc_mii_send (struct dc_softc *, u_int32_t, int); 236 static int dc_mii_readreg (struct dc_softc *, struct dc_mii_frame *); 237 static int dc_mii_writereg (struct dc_softc *, struct dc_mii_frame *); 238 static int dc_miibus_readreg (device_t, int, int); 239 static int dc_miibus_writereg (device_t, int, int, int); 240 static void dc_miibus_statchg (device_t); 241 static void dc_miibus_mediainit (device_t); 242 243 static void dc_setcfg (struct dc_softc *, int); 244 static u_int32_t dc_crc_le (struct dc_softc *, caddr_t); 245 static u_int32_t dc_crc_be (caddr_t); 246 static void dc_setfilt_21143 (struct dc_softc *); 247 static void dc_setfilt_asix (struct dc_softc *); 248 static void dc_setfilt_admtek (struct dc_softc *); 249 static void dc_setfilt_xircom (struct dc_softc *); 250 251 static void dc_setfilt (struct dc_softc *); 252 253 static void dc_reset (struct dc_softc *); 254 static int dc_list_rx_init (struct dc_softc *); 255 static int dc_list_tx_init (struct dc_softc *); 256 257 static void dc_parse_21143_srom (struct dc_softc *); 258 static void dc_decode_leaf_sia (struct dc_softc *, struct dc_eblock_sia *); 259 static void dc_decode_leaf_mii (struct dc_softc *, struct dc_eblock_mii *); 260 static void dc_decode_leaf_sym (struct dc_softc *, struct dc_eblock_sym *); 261 static void dc_apply_fixup (struct dc_softc *, int); 262 263 #ifdef DC_USEIOSPACE 264 #define DC_RES SYS_RES_IOPORT 265 #define DC_RID DC_PCI_CFBIO 266 #else 267 #define DC_RES SYS_RES_MEMORY 268 #define DC_RID DC_PCI_CFBMA 269 #endif 270 271 static device_method_t dc_methods[] = { 272 /* Device interface */ 273 DEVMETHOD(device_probe, dc_probe), 274 DEVMETHOD(device_attach, dc_attach), 275 DEVMETHOD(device_detach, dc_detach), 276 DEVMETHOD(device_shutdown, dc_shutdown), 277 278 /* bus interface */ 279 DEVMETHOD(bus_print_child, bus_generic_print_child), 280 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 281 282 /* MII interface */ 283 DEVMETHOD(miibus_readreg, dc_miibus_readreg), 284 DEVMETHOD(miibus_writereg, dc_miibus_writereg), 285 DEVMETHOD(miibus_statchg, dc_miibus_statchg), 286 DEVMETHOD(miibus_mediainit, dc_miibus_mediainit), 287 288 { 0, 0 } 289 }; 290 291 static driver_t dc_driver = { 292 "dc", 293 dc_methods, 294 sizeof(struct dc_softc) 295 }; 296 297 static devclass_t dc_devclass; 298 #ifdef __i386__ 299 static int dc_quick=1; 300 SYSCTL_INT(_hw, OID_AUTO, dc_quick, CTLFLAG_RW, 301 &dc_quick,0,"do not mdevget in dc driver"); 302 #endif 303 304 DRIVER_MODULE(if_dc, cardbus, dc_driver, dc_devclass, 0, 0); 305 DRIVER_MODULE(if_dc, pci, dc_driver, dc_devclass, 0, 0); 306 DRIVER_MODULE(miibus, dc, miibus_driver, miibus_devclass, 0, 0); 307 308 #define DC_SETBIT(sc, reg, x) \ 309 CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) | (x)) 310 311 #define DC_CLRBIT(sc, reg, x) \ 312 CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) & ~(x)) 313 314 #define SIO_SET(x) DC_SETBIT(sc, DC_SIO, (x)) 315 #define SIO_CLR(x) DC_CLRBIT(sc, DC_SIO, (x)) 316 317 #define IS_MPSAFE 0 318 319 static void dc_delay(sc) 320 struct dc_softc *sc; 321 { 322 int idx; 323 324 for (idx = (300 / 33) + 1; idx > 0; idx--) 325 CSR_READ_4(sc, DC_BUSCTL); 326 } 327 328 static void dc_eeprom_idle(sc) 329 struct dc_softc *sc; 330 { 331 register int i; 332 333 CSR_WRITE_4(sc, DC_SIO, DC_SIO_EESEL); 334 dc_delay(sc); 335 DC_SETBIT(sc, DC_SIO, DC_SIO_ROMCTL_READ); 336 dc_delay(sc); 337 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); 338 dc_delay(sc); 339 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CS); 340 dc_delay(sc); 341 342 for (i = 0; i < 25; i++) { 343 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); 344 dc_delay(sc); 345 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CLK); 346 dc_delay(sc); 347 } 348 349 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); 350 dc_delay(sc); 351 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CS); 352 dc_delay(sc); 353 CSR_WRITE_4(sc, DC_SIO, 0x00000000); 354 355 return; 356 } 357 358 /* 359 * Send a read command and address to the EEPROM, check for ACK. 360 */ 361 static void dc_eeprom_putbyte(sc, addr) 362 struct dc_softc *sc; 363 int addr; 364 { 365 register int d, i; 366 367 /* 368 * The AN985 has a 93C66 EEPROM on it instead of 369 * a 93C46. It uses a different bit sequence for 370 * specifying the "read" opcode. 371 */ 372 if (DC_IS_CENTAUR(sc) || DC_IS_CONEXANT(sc)) 373 d = addr | (DC_EECMD_READ << 2); 374 else 375 d = addr | DC_EECMD_READ; 376 377 /* 378 * Feed in each bit and strobe the clock. 379 */ 380 for (i = 0x400; i; i >>= 1) { 381 if (d & i) { 382 SIO_SET(DC_SIO_EE_DATAIN); 383 } else { 384 SIO_CLR(DC_SIO_EE_DATAIN); 385 } 386 dc_delay(sc); 387 SIO_SET(DC_SIO_EE_CLK); 388 dc_delay(sc); 389 SIO_CLR(DC_SIO_EE_CLK); 390 dc_delay(sc); 391 } 392 393 return; 394 } 395 396 /* 397 * Read a word of data stored in the EEPROM at address 'addr.' 398 * The PNIC 82c168/82c169 has its own non-standard way to read 399 * the EEPROM. 400 */ 401 static void dc_eeprom_getword_pnic(sc, addr, dest) 402 struct dc_softc *sc; 403 int addr; 404 u_int16_t *dest; 405 { 406 register int i; 407 u_int32_t r; 408 409 CSR_WRITE_4(sc, DC_PN_SIOCTL, DC_PN_EEOPCODE_READ|addr); 410 411 for (i = 0; i < DC_TIMEOUT; i++) { 412 DELAY(1); 413 r = CSR_READ_4(sc, DC_SIO); 414 if (!(r & DC_PN_SIOCTL_BUSY)) { 415 *dest = (u_int16_t)(r & 0xFFFF); 416 return; 417 } 418 } 419 420 return; 421 } 422 423 /* 424 * Read a word of data stored in the EEPROM at address 'addr.' 425 * The Xircom X3201 has its own non-standard way to read 426 * the EEPROM, too. 427 */ 428 static void dc_eeprom_getword_xircom(sc, addr, dest) 429 struct dc_softc *sc; 430 int addr; 431 u_int16_t *dest; 432 { 433 SIO_SET(DC_SIO_ROMSEL | DC_SIO_ROMCTL_READ); 434 435 addr *= 2; 436 CSR_WRITE_4(sc, DC_ROM, addr | 0x160); 437 *dest = (u_int16_t)CSR_READ_4(sc, DC_SIO)&0xff; 438 addr += 1; 439 CSR_WRITE_4(sc, DC_ROM, addr | 0x160); 440 *dest |= ((u_int16_t)CSR_READ_4(sc, DC_SIO)&0xff) << 8; 441 442 SIO_CLR(DC_SIO_ROMSEL | DC_SIO_ROMCTL_READ); 443 return; 444 } 445 446 /* 447 * Read a word of data stored in the EEPROM at address 'addr.' 448 */ 449 static void dc_eeprom_getword(sc, addr, dest) 450 struct dc_softc *sc; 451 int addr; 452 u_int16_t *dest; 453 { 454 register int i; 455 u_int16_t word = 0; 456 457 /* Force EEPROM to idle state. */ 458 dc_eeprom_idle(sc); 459 460 /* Enter EEPROM access mode. */ 461 CSR_WRITE_4(sc, DC_SIO, DC_SIO_EESEL); 462 dc_delay(sc); 463 DC_SETBIT(sc, DC_SIO, DC_SIO_ROMCTL_READ); 464 dc_delay(sc); 465 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); 466 dc_delay(sc); 467 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CS); 468 dc_delay(sc); 469 470 /* 471 * Send address of word we want to read. 472 */ 473 dc_eeprom_putbyte(sc, addr); 474 475 /* 476 * Start reading bits from EEPROM. 477 */ 478 for (i = 0x8000; i; i >>= 1) { 479 SIO_SET(DC_SIO_EE_CLK); 480 dc_delay(sc); 481 if (CSR_READ_4(sc, DC_SIO) & DC_SIO_EE_DATAOUT) 482 word |= i; 483 dc_delay(sc); 484 SIO_CLR(DC_SIO_EE_CLK); 485 dc_delay(sc); 486 } 487 488 /* Turn off EEPROM access mode. */ 489 dc_eeprom_idle(sc); 490 491 *dest = word; 492 493 return; 494 } 495 496 /* 497 * Read a sequence of words from the EEPROM. 498 */ 499 static void dc_read_eeprom(sc, dest, off, cnt, swap) 500 struct dc_softc *sc; 501 caddr_t dest; 502 int off; 503 int cnt; 504 int swap; 505 { 506 int i; 507 u_int16_t word = 0, *ptr; 508 509 for (i = 0; i < cnt; i++) { 510 if (DC_IS_PNIC(sc)) 511 dc_eeprom_getword_pnic(sc, off + i, &word); 512 else if (DC_IS_XIRCOM(sc)) 513 dc_eeprom_getword_xircom(sc, off + i, &word); 514 else 515 dc_eeprom_getword(sc, off + i, &word); 516 ptr = (u_int16_t *)(dest + (i * 2)); 517 if (swap) 518 *ptr = ntohs(word); 519 else 520 *ptr = word; 521 } 522 523 return; 524 } 525 526 /* 527 * The following two routines are taken from the Macronix 98713 528 * Application Notes pp.19-21. 529 */ 530 /* 531 * Write a bit to the MII bus. 532 */ 533 static void dc_mii_writebit(sc, bit) 534 struct dc_softc *sc; 535 int bit; 536 { 537 if (bit) 538 CSR_WRITE_4(sc, DC_SIO, 539 DC_SIO_ROMCTL_WRITE|DC_SIO_MII_DATAOUT); 540 else 541 CSR_WRITE_4(sc, DC_SIO, DC_SIO_ROMCTL_WRITE); 542 543 DC_SETBIT(sc, DC_SIO, DC_SIO_MII_CLK); 544 DC_CLRBIT(sc, DC_SIO, DC_SIO_MII_CLK); 545 546 return; 547 } 548 549 /* 550 * Read a bit from the MII bus. 551 */ 552 static int dc_mii_readbit(sc) 553 struct dc_softc *sc; 554 { 555 CSR_WRITE_4(sc, DC_SIO, DC_SIO_ROMCTL_READ|DC_SIO_MII_DIR); 556 CSR_READ_4(sc, DC_SIO); 557 DC_SETBIT(sc, DC_SIO, DC_SIO_MII_CLK); 558 DC_CLRBIT(sc, DC_SIO, DC_SIO_MII_CLK); 559 if (CSR_READ_4(sc, DC_SIO) & DC_SIO_MII_DATAIN) 560 return(1); 561 562 return(0); 563 } 564 565 /* 566 * Sync the PHYs by setting data bit and strobing the clock 32 times. 567 */ 568 static void dc_mii_sync(sc) 569 struct dc_softc *sc; 570 { 571 register int i; 572 573 CSR_WRITE_4(sc, DC_SIO, DC_SIO_ROMCTL_WRITE); 574 575 for (i = 0; i < 32; i++) 576 dc_mii_writebit(sc, 1); 577 578 return; 579 } 580 581 /* 582 * Clock a series of bits through the MII. 583 */ 584 static void dc_mii_send(sc, bits, cnt) 585 struct dc_softc *sc; 586 u_int32_t bits; 587 int cnt; 588 { 589 int i; 590 591 for (i = (0x1 << (cnt - 1)); i; i >>= 1) 592 dc_mii_writebit(sc, bits & i); 593 } 594 595 /* 596 * Read an PHY register through the MII. 597 */ 598 static int dc_mii_readreg(sc, frame) 599 struct dc_softc *sc; 600 struct dc_mii_frame *frame; 601 602 { 603 int i, ack; 604 605 DC_LOCK(sc); 606 607 /* 608 * Set up frame for RX. 609 */ 610 frame->mii_stdelim = DC_MII_STARTDELIM; 611 frame->mii_opcode = DC_MII_READOP; 612 frame->mii_turnaround = 0; 613 frame->mii_data = 0; 614 615 /* 616 * Sync the PHYs. 617 */ 618 dc_mii_sync(sc); 619 620 /* 621 * Send command/address info. 622 */ 623 dc_mii_send(sc, frame->mii_stdelim, 2); 624 dc_mii_send(sc, frame->mii_opcode, 2); 625 dc_mii_send(sc, frame->mii_phyaddr, 5); 626 dc_mii_send(sc, frame->mii_regaddr, 5); 627 628 #ifdef notdef 629 /* Idle bit */ 630 dc_mii_writebit(sc, 1); 631 dc_mii_writebit(sc, 0); 632 #endif 633 634 /* Check for ack */ 635 ack = dc_mii_readbit(sc); 636 637 /* 638 * Now try reading data bits. If the ack failed, we still 639 * need to clock through 16 cycles to keep the PHY(s) in sync. 640 */ 641 if (ack) { 642 for(i = 0; i < 16; i++) { 643 dc_mii_readbit(sc); 644 } 645 goto fail; 646 } 647 648 for (i = 0x8000; i; i >>= 1) { 649 if (!ack) { 650 if (dc_mii_readbit(sc)) 651 frame->mii_data |= i; 652 } 653 } 654 655 fail: 656 657 dc_mii_writebit(sc, 0); 658 dc_mii_writebit(sc, 0); 659 660 DC_UNLOCK(sc); 661 662 if (ack) 663 return(1); 664 return(0); 665 } 666 667 /* 668 * Write to a PHY register through the MII. 669 */ 670 static int dc_mii_writereg(sc, frame) 671 struct dc_softc *sc; 672 struct dc_mii_frame *frame; 673 674 { 675 DC_LOCK(sc); 676 /* 677 * Set up frame for TX. 678 */ 679 680 frame->mii_stdelim = DC_MII_STARTDELIM; 681 frame->mii_opcode = DC_MII_WRITEOP; 682 frame->mii_turnaround = DC_MII_TURNAROUND; 683 684 /* 685 * Sync the PHYs. 686 */ 687 dc_mii_sync(sc); 688 689 dc_mii_send(sc, frame->mii_stdelim, 2); 690 dc_mii_send(sc, frame->mii_opcode, 2); 691 dc_mii_send(sc, frame->mii_phyaddr, 5); 692 dc_mii_send(sc, frame->mii_regaddr, 5); 693 dc_mii_send(sc, frame->mii_turnaround, 2); 694 dc_mii_send(sc, frame->mii_data, 16); 695 696 /* Idle bit. */ 697 dc_mii_writebit(sc, 0); 698 dc_mii_writebit(sc, 0); 699 700 DC_UNLOCK(sc); 701 702 return(0); 703 } 704 705 static int dc_miibus_readreg(dev, phy, reg) 706 device_t dev; 707 int phy, reg; 708 { 709 struct dc_mii_frame frame; 710 struct dc_softc *sc; 711 int i, rval, phy_reg = 0; 712 713 sc = device_get_softc(dev); 714 bzero((char *)&frame, sizeof(frame)); 715 716 /* 717 * Note: both the AL981 and AN985 have internal PHYs, 718 * however the AL981 provides direct access to the PHY 719 * registers while the AN985 uses a serial MII interface. 720 * The AN985's MII interface is also buggy in that you 721 * can read from any MII address (0 to 31), but only address 1 722 * behaves normally. To deal with both cases, we pretend 723 * that the PHY is at MII address 1. 724 */ 725 if (DC_IS_ADMTEK(sc) && phy != DC_ADMTEK_PHYADDR) 726 return(0); 727 728 /* 729 * Note: the ukphy probes of the RS7112 report a PHY at 730 * MII address 0 (possibly HomePNA?) and 1 (ethernet) 731 * so we only respond to correct one. 732 */ 733 if (DC_IS_CONEXANT(sc) && phy != DC_CONEXANT_PHYADDR) 734 return(0); 735 736 if (sc->dc_pmode != DC_PMODE_MII) { 737 if (phy == (MII_NPHY - 1)) { 738 switch(reg) { 739 case MII_BMSR: 740 /* 741 * Fake something to make the probe 742 * code think there's a PHY here. 743 */ 744 return(BMSR_MEDIAMASK); 745 break; 746 case MII_PHYIDR1: 747 if (DC_IS_PNIC(sc)) 748 return(DC_VENDORID_LO); 749 return(DC_VENDORID_DEC); 750 break; 751 case MII_PHYIDR2: 752 if (DC_IS_PNIC(sc)) 753 return(DC_DEVICEID_82C168); 754 return(DC_DEVICEID_21143); 755 break; 756 default: 757 return(0); 758 break; 759 } 760 } else 761 return(0); 762 } 763 764 if (DC_IS_PNIC(sc)) { 765 CSR_WRITE_4(sc, DC_PN_MII, DC_PN_MIIOPCODE_READ | 766 (phy << 23) | (reg << 18)); 767 for (i = 0; i < DC_TIMEOUT; i++) { 768 DELAY(1); 769 rval = CSR_READ_4(sc, DC_PN_MII); 770 if (!(rval & DC_PN_MII_BUSY)) { 771 rval &= 0xFFFF; 772 return(rval == 0xFFFF ? 0 : rval); 773 } 774 } 775 return(0); 776 } 777 778 if (DC_IS_COMET(sc)) { 779 switch(reg) { 780 case MII_BMCR: 781 phy_reg = DC_AL_BMCR; 782 break; 783 case MII_BMSR: 784 phy_reg = DC_AL_BMSR; 785 break; 786 case MII_PHYIDR1: 787 phy_reg = DC_AL_VENID; 788 break; 789 case MII_PHYIDR2: 790 phy_reg = DC_AL_DEVID; 791 break; 792 case MII_ANAR: 793 phy_reg = DC_AL_ANAR; 794 break; 795 case MII_ANLPAR: 796 phy_reg = DC_AL_LPAR; 797 break; 798 case MII_ANER: 799 phy_reg = DC_AL_ANER; 800 break; 801 default: 802 printf("dc%d: phy_read: bad phy register %x\n", 803 sc->dc_unit, reg); 804 return(0); 805 break; 806 } 807 808 rval = CSR_READ_4(sc, phy_reg) & 0x0000FFFF; 809 810 if (rval == 0xFFFF) 811 return(0); 812 return(rval); 813 } 814 815 frame.mii_phyaddr = phy; 816 frame.mii_regaddr = reg; 817 if (sc->dc_type == DC_TYPE_98713) { 818 phy_reg = CSR_READ_4(sc, DC_NETCFG); 819 CSR_WRITE_4(sc, DC_NETCFG, phy_reg & ~DC_NETCFG_PORTSEL); 820 } 821 dc_mii_readreg(sc, &frame); 822 if (sc->dc_type == DC_TYPE_98713) 823 CSR_WRITE_4(sc, DC_NETCFG, phy_reg); 824 825 return(frame.mii_data); 826 } 827 828 static int dc_miibus_writereg(dev, phy, reg, data) 829 device_t dev; 830 int phy, reg, data; 831 { 832 struct dc_softc *sc; 833 struct dc_mii_frame frame; 834 int i, phy_reg = 0; 835 836 sc = device_get_softc(dev); 837 bzero((char *)&frame, sizeof(frame)); 838 839 if (DC_IS_ADMTEK(sc) && phy != DC_ADMTEK_PHYADDR) 840 return(0); 841 842 if (DC_IS_CONEXANT(sc) && phy != DC_CONEXANT_PHYADDR) 843 return(0); 844 845 if (DC_IS_PNIC(sc)) { 846 CSR_WRITE_4(sc, DC_PN_MII, DC_PN_MIIOPCODE_WRITE | 847 (phy << 23) | (reg << 10) | data); 848 for (i = 0; i < DC_TIMEOUT; i++) { 849 if (!(CSR_READ_4(sc, DC_PN_MII) & DC_PN_MII_BUSY)) 850 break; 851 } 852 return(0); 853 } 854 855 if (DC_IS_COMET(sc)) { 856 switch(reg) { 857 case MII_BMCR: 858 phy_reg = DC_AL_BMCR; 859 break; 860 case MII_BMSR: 861 phy_reg = DC_AL_BMSR; 862 break; 863 case MII_PHYIDR1: 864 phy_reg = DC_AL_VENID; 865 break; 866 case MII_PHYIDR2: 867 phy_reg = DC_AL_DEVID; 868 break; 869 case MII_ANAR: 870 phy_reg = DC_AL_ANAR; 871 break; 872 case MII_ANLPAR: 873 phy_reg = DC_AL_LPAR; 874 break; 875 case MII_ANER: 876 phy_reg = DC_AL_ANER; 877 break; 878 default: 879 printf("dc%d: phy_write: bad phy register %x\n", 880 sc->dc_unit, reg); 881 return(0); 882 break; 883 } 884 885 CSR_WRITE_4(sc, phy_reg, data); 886 return(0); 887 } 888 889 frame.mii_phyaddr = phy; 890 frame.mii_regaddr = reg; 891 frame.mii_data = data; 892 893 if (sc->dc_type == DC_TYPE_98713) { 894 phy_reg = CSR_READ_4(sc, DC_NETCFG); 895 CSR_WRITE_4(sc, DC_NETCFG, phy_reg & ~DC_NETCFG_PORTSEL); 896 } 897 dc_mii_writereg(sc, &frame); 898 if (sc->dc_type == DC_TYPE_98713) 899 CSR_WRITE_4(sc, DC_NETCFG, phy_reg); 900 901 return(0); 902 } 903 904 static void dc_miibus_statchg(dev) 905 device_t dev; 906 { 907 struct dc_softc *sc; 908 struct mii_data *mii; 909 struct ifmedia *ifm; 910 911 sc = device_get_softc(dev); 912 if (DC_IS_ADMTEK(sc)) 913 return; 914 915 mii = device_get_softc(sc->dc_miibus); 916 ifm = &mii->mii_media; 917 if (DC_IS_DAVICOM(sc) && 918 IFM_SUBTYPE(ifm->ifm_media) == IFM_homePNA) { 919 dc_setcfg(sc, ifm->ifm_media); 920 sc->dc_if_media = ifm->ifm_media; 921 } else { 922 dc_setcfg(sc, mii->mii_media_active); 923 sc->dc_if_media = mii->mii_media_active; 924 } 925 926 return; 927 } 928 929 /* 930 * Special support for DM9102A cards with HomePNA PHYs. Note: 931 * with the Davicom DM9102A/DM9801 eval board that I have, it seems 932 * to be impossible to talk to the management interface of the DM9801 933 * PHY (its MDIO pin is not connected to anything). Consequently, 934 * the driver has to just 'know' about the additional mode and deal 935 * with it itself. *sigh* 936 */ 937 static void dc_miibus_mediainit(dev) 938 device_t dev; 939 { 940 struct dc_softc *sc; 941 struct mii_data *mii; 942 struct ifmedia *ifm; 943 int rev; 944 945 rev = pci_read_config(dev, DC_PCI_CFRV, 4) & 0xFF; 946 947 sc = device_get_softc(dev); 948 mii = device_get_softc(sc->dc_miibus); 949 ifm = &mii->mii_media; 950 951 if (DC_IS_DAVICOM(sc) && rev >= DC_REVISION_DM9102A) 952 ifmedia_add(ifm, IFM_ETHER|IFM_homePNA, 0, NULL); 953 954 return; 955 } 956 957 #define DC_POLY 0xEDB88320 958 #define DC_BITS_512 9 959 #define DC_BITS_128 7 960 #define DC_BITS_64 6 961 962 static u_int32_t dc_crc_le(sc, addr) 963 struct dc_softc *sc; 964 caddr_t addr; 965 { 966 u_int32_t idx, bit, data, crc; 967 968 /* Compute CRC for the address value. */ 969 crc = 0xFFFFFFFF; /* initial value */ 970 971 for (idx = 0; idx < 6; idx++) { 972 for (data = *addr++, bit = 0; bit < 8; bit++, data >>= 1) 973 crc = (crc >> 1) ^ (((crc ^ data) & 1) ? DC_POLY : 0); 974 } 975 976 /* 977 * The hash table on the PNIC II and the MX98715AEC-C/D/E 978 * chips is only 128 bits wide. 979 */ 980 if (sc->dc_flags & DC_128BIT_HASH) 981 return (crc & ((1 << DC_BITS_128) - 1)); 982 983 /* The hash table on the MX98715BEC is only 64 bits wide. */ 984 if (sc->dc_flags & DC_64BIT_HASH) 985 return (crc & ((1 << DC_BITS_64) - 1)); 986 987 /* Xircom's hash filtering table is different (read: weird) */ 988 /* Xircom uses the LEAST significant bits */ 989 if (DC_IS_XIRCOM(sc)) { 990 if ((crc & 0x180) == 0x180) 991 return (crc & 0x0F) + (crc & 0x70)*3 + (14 << 4); 992 else 993 return (crc & 0x1F) + ((crc>>1) & 0xF0)*3 + (12 << 4); 994 } 995 996 return (crc & ((1 << DC_BITS_512) - 1)); 997 } 998 999 /* 1000 * Calculate CRC of a multicast group address, return the lower 6 bits. 1001 */ 1002 static u_int32_t dc_crc_be(addr) 1003 caddr_t addr; 1004 { 1005 u_int32_t crc, carry; 1006 int i, j; 1007 u_int8_t c; 1008 1009 /* Compute CRC for the address value. */ 1010 crc = 0xFFFFFFFF; /* initial value */ 1011 1012 for (i = 0; i < 6; i++) { 1013 c = *(addr + i); 1014 for (j = 0; j < 8; j++) { 1015 carry = ((crc & 0x80000000) ? 1 : 0) ^ (c & 0x01); 1016 crc <<= 1; 1017 c >>= 1; 1018 if (carry) 1019 crc = (crc ^ 0x04c11db6) | carry; 1020 } 1021 } 1022 1023 /* return the filter bit position */ 1024 return((crc >> 26) & 0x0000003F); 1025 } 1026 1027 /* 1028 * 21143-style RX filter setup routine. Filter programming is done by 1029 * downloading a special setup frame into the TX engine. 21143, Macronix, 1030 * PNIC, PNIC II and Davicom chips are programmed this way. 1031 * 1032 * We always program the chip using 'hash perfect' mode, i.e. one perfect 1033 * address (our node address) and a 512-bit hash filter for multicast 1034 * frames. We also sneak the broadcast address into the hash filter since 1035 * we need that too. 1036 */ 1037 void dc_setfilt_21143(sc) 1038 struct dc_softc *sc; 1039 { 1040 struct dc_desc *sframe; 1041 u_int32_t h, *sp; 1042 struct ifmultiaddr *ifma; 1043 struct ifnet *ifp; 1044 int i; 1045 1046 ifp = &sc->arpcom.ac_if; 1047 1048 i = sc->dc_cdata.dc_tx_prod; 1049 DC_INC(sc->dc_cdata.dc_tx_prod, DC_TX_LIST_CNT); 1050 sc->dc_cdata.dc_tx_cnt++; 1051 sframe = &sc->dc_ldata->dc_tx_list[i]; 1052 sp = (u_int32_t *)&sc->dc_cdata.dc_sbuf; 1053 bzero((char *)sp, DC_SFRAME_LEN); 1054 1055 sframe->dc_data = vtophys(&sc->dc_cdata.dc_sbuf); 1056 sframe->dc_ctl = DC_SFRAME_LEN | DC_TXCTL_SETUP | DC_TXCTL_TLINK | 1057 DC_FILTER_HASHPERF | DC_TXCTL_FINT; 1058 1059 sc->dc_cdata.dc_tx_chain[i] = (struct mbuf *)&sc->dc_cdata.dc_sbuf; 1060 1061 /* If we want promiscuous mode, set the allframes bit. */ 1062 if (ifp->if_flags & IFF_PROMISC) 1063 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC); 1064 else 1065 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC); 1066 1067 if (ifp->if_flags & IFF_ALLMULTI) 1068 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI); 1069 else 1070 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI); 1071 1072 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 1073 if (ifma->ifma_addr->sa_family != AF_LINK) 1074 continue; 1075 h = dc_crc_le(sc, 1076 LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 1077 sp[h >> 4] |= 1 << (h & 0xF); 1078 } 1079 1080 if (ifp->if_flags & IFF_BROADCAST) { 1081 h = dc_crc_le(sc, (caddr_t)ðerbroadcastaddr); 1082 sp[h >> 4] |= 1 << (h & 0xF); 1083 } 1084 1085 /* Set our MAC address */ 1086 sp[39] = ((u_int16_t *)sc->arpcom.ac_enaddr)[0]; 1087 sp[40] = ((u_int16_t *)sc->arpcom.ac_enaddr)[1]; 1088 sp[41] = ((u_int16_t *)sc->arpcom.ac_enaddr)[2]; 1089 1090 sframe->dc_status = DC_TXSTAT_OWN; 1091 CSR_WRITE_4(sc, DC_TXSTART, 0xFFFFFFFF); 1092 1093 /* 1094 * The PNIC takes an exceedingly long time to process its 1095 * setup frame; wait 10ms after posting the setup frame 1096 * before proceeding, just so it has time to swallow its 1097 * medicine. 1098 */ 1099 DELAY(10000); 1100 1101 ifp->if_timer = 5; 1102 1103 return; 1104 } 1105 1106 void dc_setfilt_admtek(sc) 1107 struct dc_softc *sc; 1108 { 1109 struct ifnet *ifp; 1110 int h = 0; 1111 u_int32_t hashes[2] = { 0, 0 }; 1112 struct ifmultiaddr *ifma; 1113 1114 ifp = &sc->arpcom.ac_if; 1115 1116 /* Init our MAC address */ 1117 CSR_WRITE_4(sc, DC_AL_PAR0, *(u_int32_t *)(&sc->arpcom.ac_enaddr[0])); 1118 CSR_WRITE_4(sc, DC_AL_PAR1, *(u_int32_t *)(&sc->arpcom.ac_enaddr[4])); 1119 1120 /* If we want promiscuous mode, set the allframes bit. */ 1121 if (ifp->if_flags & IFF_PROMISC) 1122 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC); 1123 else 1124 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC); 1125 1126 if (ifp->if_flags & IFF_ALLMULTI) 1127 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI); 1128 else 1129 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI); 1130 1131 /* first, zot all the existing hash bits */ 1132 CSR_WRITE_4(sc, DC_AL_MAR0, 0); 1133 CSR_WRITE_4(sc, DC_AL_MAR1, 0); 1134 1135 /* 1136 * If we're already in promisc or allmulti mode, we 1137 * don't have to bother programming the multicast filter. 1138 */ 1139 if (ifp->if_flags & (IFF_PROMISC|IFF_ALLMULTI)) 1140 return; 1141 1142 /* now program new ones */ 1143 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 1144 if (ifma->ifma_addr->sa_family != AF_LINK) 1145 continue; 1146 h = dc_crc_be(LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 1147 if (h < 32) 1148 hashes[0] |= (1 << h); 1149 else 1150 hashes[1] |= (1 << (h - 32)); 1151 } 1152 1153 CSR_WRITE_4(sc, DC_AL_MAR0, hashes[0]); 1154 CSR_WRITE_4(sc, DC_AL_MAR1, hashes[1]); 1155 1156 return; 1157 } 1158 1159 void dc_setfilt_asix(sc) 1160 struct dc_softc *sc; 1161 { 1162 struct ifnet *ifp; 1163 int h = 0; 1164 u_int32_t hashes[2] = { 0, 0 }; 1165 struct ifmultiaddr *ifma; 1166 1167 ifp = &sc->arpcom.ac_if; 1168 1169 /* Init our MAC address */ 1170 CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_PAR0); 1171 CSR_WRITE_4(sc, DC_AX_FILTDATA, 1172 *(u_int32_t *)(&sc->arpcom.ac_enaddr[0])); 1173 CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_PAR1); 1174 CSR_WRITE_4(sc, DC_AX_FILTDATA, 1175 *(u_int32_t *)(&sc->arpcom.ac_enaddr[4])); 1176 1177 /* If we want promiscuous mode, set the allframes bit. */ 1178 if (ifp->if_flags & IFF_PROMISC) 1179 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC); 1180 else 1181 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC); 1182 1183 if (ifp->if_flags & IFF_ALLMULTI) 1184 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI); 1185 else 1186 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI); 1187 1188 /* 1189 * The ASIX chip has a special bit to enable reception 1190 * of broadcast frames. 1191 */ 1192 if (ifp->if_flags & IFF_BROADCAST) 1193 DC_SETBIT(sc, DC_NETCFG, DC_AX_NETCFG_RX_BROAD); 1194 else 1195 DC_CLRBIT(sc, DC_NETCFG, DC_AX_NETCFG_RX_BROAD); 1196 1197 /* first, zot all the existing hash bits */ 1198 CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_MAR0); 1199 CSR_WRITE_4(sc, DC_AX_FILTDATA, 0); 1200 CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_MAR1); 1201 CSR_WRITE_4(sc, DC_AX_FILTDATA, 0); 1202 1203 /* 1204 * If we're already in promisc or allmulti mode, we 1205 * don't have to bother programming the multicast filter. 1206 */ 1207 if (ifp->if_flags & (IFF_PROMISC|IFF_ALLMULTI)) 1208 return; 1209 1210 /* now program new ones */ 1211 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 1212 if (ifma->ifma_addr->sa_family != AF_LINK) 1213 continue; 1214 h = dc_crc_be(LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 1215 if (h < 32) 1216 hashes[0] |= (1 << h); 1217 else 1218 hashes[1] |= (1 << (h - 32)); 1219 } 1220 1221 CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_MAR0); 1222 CSR_WRITE_4(sc, DC_AX_FILTDATA, hashes[0]); 1223 CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_MAR1); 1224 CSR_WRITE_4(sc, DC_AX_FILTDATA, hashes[1]); 1225 1226 return; 1227 } 1228 1229 void dc_setfilt_xircom(sc) 1230 struct dc_softc *sc; 1231 { 1232 struct dc_desc *sframe; 1233 u_int32_t h, *sp; 1234 struct ifmultiaddr *ifma; 1235 struct ifnet *ifp; 1236 int i; 1237 1238 ifp = &sc->arpcom.ac_if; 1239 DC_CLRBIT(sc, DC_NETCFG, (DC_NETCFG_TX_ON|DC_NETCFG_RX_ON)); 1240 1241 i = sc->dc_cdata.dc_tx_prod; 1242 DC_INC(sc->dc_cdata.dc_tx_prod, DC_TX_LIST_CNT); 1243 sc->dc_cdata.dc_tx_cnt++; 1244 sframe = &sc->dc_ldata->dc_tx_list[i]; 1245 sp = (u_int32_t *)&sc->dc_cdata.dc_sbuf; 1246 bzero((char *)sp, DC_SFRAME_LEN); 1247 1248 sframe->dc_data = vtophys(&sc->dc_cdata.dc_sbuf); 1249 sframe->dc_ctl = DC_SFRAME_LEN | DC_TXCTL_SETUP | DC_TXCTL_TLINK | 1250 DC_FILTER_HASHPERF | DC_TXCTL_FINT; 1251 1252 sc->dc_cdata.dc_tx_chain[i] = (struct mbuf *)&sc->dc_cdata.dc_sbuf; 1253 1254 /* If we want promiscuous mode, set the allframes bit. */ 1255 if (ifp->if_flags & IFF_PROMISC) 1256 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC); 1257 else 1258 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC); 1259 1260 if (ifp->if_flags & IFF_ALLMULTI) 1261 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI); 1262 else 1263 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI); 1264 1265 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 1266 if (ifma->ifma_addr->sa_family != AF_LINK) 1267 continue; 1268 h = dc_crc_le(sc, 1269 LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 1270 sp[h >> 4] |= 1 << (h & 0xF); 1271 } 1272 1273 if (ifp->if_flags & IFF_BROADCAST) { 1274 h = dc_crc_le(sc, (caddr_t)ðerbroadcastaddr); 1275 sp[h >> 4] |= 1 << (h & 0xF); 1276 } 1277 1278 /* Set our MAC address */ 1279 sp[0] = ((u_int16_t *)sc->arpcom.ac_enaddr)[0]; 1280 sp[1] = ((u_int16_t *)sc->arpcom.ac_enaddr)[1]; 1281 sp[2] = ((u_int16_t *)sc->arpcom.ac_enaddr)[2]; 1282 1283 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_TX_ON); 1284 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_ON); 1285 ifp->if_flags |= IFF_RUNNING; 1286 sframe->dc_status = DC_TXSTAT_OWN; 1287 CSR_WRITE_4(sc, DC_TXSTART, 0xFFFFFFFF); 1288 1289 /* 1290 * wait some time... 1291 */ 1292 DELAY(1000); 1293 1294 ifp->if_timer = 5; 1295 1296 return; 1297 } 1298 1299 static void dc_setfilt(sc) 1300 struct dc_softc *sc; 1301 { 1302 if (DC_IS_INTEL(sc) || DC_IS_MACRONIX(sc) || DC_IS_PNIC(sc) || 1303 DC_IS_PNICII(sc) || DC_IS_DAVICOM(sc) || DC_IS_CONEXANT(sc)) 1304 dc_setfilt_21143(sc); 1305 1306 if (DC_IS_ASIX(sc)) 1307 dc_setfilt_asix(sc); 1308 1309 if (DC_IS_ADMTEK(sc)) 1310 dc_setfilt_admtek(sc); 1311 1312 if (DC_IS_XIRCOM(sc)) 1313 dc_setfilt_xircom(sc); 1314 1315 return; 1316 } 1317 1318 /* 1319 * In order to fiddle with the 1320 * 'full-duplex' and '100Mbps' bits in the netconfig register, we 1321 * first have to put the transmit and/or receive logic in the idle state. 1322 */ 1323 static void dc_setcfg(sc, media) 1324 struct dc_softc *sc; 1325 int media; 1326 { 1327 int i, restart = 0; 1328 u_int32_t isr; 1329 1330 if (IFM_SUBTYPE(media) == IFM_NONE) 1331 return; 1332 1333 if (CSR_READ_4(sc, DC_NETCFG) & (DC_NETCFG_TX_ON|DC_NETCFG_RX_ON)) { 1334 restart = 1; 1335 DC_CLRBIT(sc, DC_NETCFG, (DC_NETCFG_TX_ON|DC_NETCFG_RX_ON)); 1336 1337 for (i = 0; i < DC_TIMEOUT; i++) { 1338 isr = CSR_READ_4(sc, DC_ISR); 1339 if (isr & DC_ISR_TX_IDLE && 1340 (isr & DC_ISR_RX_STATE) == DC_RXSTATE_STOPPED) 1341 break; 1342 DELAY(10); 1343 } 1344 1345 if (i == DC_TIMEOUT) 1346 printf("dc%d: failed to force tx and " 1347 "rx to idle state\n", sc->dc_unit); 1348 } 1349 1350 if (IFM_SUBTYPE(media) == IFM_100_TX) { 1351 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_SPEEDSEL); 1352 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_HEARTBEAT); 1353 if (sc->dc_pmode == DC_PMODE_MII) { 1354 int watchdogreg; 1355 1356 if (DC_IS_INTEL(sc)) { 1357 /* there's a write enable bit here that reads as 1 */ 1358 watchdogreg = CSR_READ_4(sc, DC_WATCHDOG); 1359 watchdogreg &= ~DC_WDOG_CTLWREN; 1360 watchdogreg |= DC_WDOG_JABBERDIS; 1361 CSR_WRITE_4(sc, DC_WATCHDOG, watchdogreg); 1362 } else { 1363 DC_SETBIT(sc, DC_WATCHDOG, DC_WDOG_JABBERDIS); 1364 } 1365 DC_CLRBIT(sc, DC_NETCFG, (DC_NETCFG_PCS| 1366 DC_NETCFG_PORTSEL|DC_NETCFG_SCRAMBLER)); 1367 if (sc->dc_type == DC_TYPE_98713) 1368 DC_SETBIT(sc, DC_NETCFG, (DC_NETCFG_PCS| 1369 DC_NETCFG_SCRAMBLER)); 1370 if (!DC_IS_DAVICOM(sc)) 1371 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL); 1372 DC_CLRBIT(sc, DC_10BTCTRL, 0xFFFF); 1373 if (DC_IS_INTEL(sc)) 1374 dc_apply_fixup(sc, IFM_AUTO); 1375 } else { 1376 if (DC_IS_PNIC(sc)) { 1377 DC_PN_GPIO_SETBIT(sc, DC_PN_GPIO_SPEEDSEL); 1378 DC_PN_GPIO_SETBIT(sc, DC_PN_GPIO_100TX_LOOP); 1379 DC_SETBIT(sc, DC_PN_NWAY, DC_PN_NWAY_SPEEDSEL); 1380 } 1381 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL); 1382 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PCS); 1383 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_SCRAMBLER); 1384 if (DC_IS_INTEL(sc)) 1385 dc_apply_fixup(sc, 1386 (media & IFM_GMASK) == IFM_FDX ? 1387 IFM_100_TX|IFM_FDX : IFM_100_TX); 1388 } 1389 } 1390 1391 if (IFM_SUBTYPE(media) == IFM_10_T) { 1392 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_SPEEDSEL); 1393 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_HEARTBEAT); 1394 if (sc->dc_pmode == DC_PMODE_MII) { 1395 int watchdogreg; 1396 1397 /* there's a write enable bit here that reads as 1 */ 1398 if (DC_IS_INTEL(sc)) { 1399 watchdogreg = CSR_READ_4(sc, DC_WATCHDOG); 1400 watchdogreg &= ~DC_WDOG_CTLWREN; 1401 watchdogreg |= DC_WDOG_JABBERDIS; 1402 CSR_WRITE_4(sc, DC_WATCHDOG, watchdogreg); 1403 } else { 1404 DC_SETBIT(sc, DC_WATCHDOG, DC_WDOG_JABBERDIS); 1405 } 1406 DC_CLRBIT(sc, DC_NETCFG, (DC_NETCFG_PCS| 1407 DC_NETCFG_PORTSEL|DC_NETCFG_SCRAMBLER)); 1408 if (sc->dc_type == DC_TYPE_98713) 1409 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PCS); 1410 if (!DC_IS_DAVICOM(sc)) 1411 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL); 1412 DC_CLRBIT(sc, DC_10BTCTRL, 0xFFFF); 1413 if (DC_IS_INTEL(sc)) 1414 dc_apply_fixup(sc, IFM_AUTO); 1415 } else { 1416 if (DC_IS_PNIC(sc)) { 1417 DC_PN_GPIO_CLRBIT(sc, DC_PN_GPIO_SPEEDSEL); 1418 DC_PN_GPIO_SETBIT(sc, DC_PN_GPIO_100TX_LOOP); 1419 DC_CLRBIT(sc, DC_PN_NWAY, DC_PN_NWAY_SPEEDSEL); 1420 } 1421 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL); 1422 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_PCS); 1423 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_SCRAMBLER); 1424 if (DC_IS_INTEL(sc)) { 1425 DC_CLRBIT(sc, DC_SIARESET, DC_SIA_RESET); 1426 DC_CLRBIT(sc, DC_10BTCTRL, 0xFFFF); 1427 if ((media & IFM_GMASK) == IFM_FDX) 1428 DC_SETBIT(sc, DC_10BTCTRL, 0x7F3D); 1429 else 1430 DC_SETBIT(sc, DC_10BTCTRL, 0x7F3F); 1431 DC_SETBIT(sc, DC_SIARESET, DC_SIA_RESET); 1432 DC_CLRBIT(sc, DC_10BTCTRL, 1433 DC_TCTL_AUTONEGENBL); 1434 dc_apply_fixup(sc, 1435 (media & IFM_GMASK) == IFM_FDX ? 1436 IFM_10_T|IFM_FDX : IFM_10_T); 1437 DELAY(20000); 1438 } 1439 } 1440 } 1441 1442 /* 1443 * If this is a Davicom DM9102A card with a DM9801 HomePNA 1444 * PHY and we want HomePNA mode, set the portsel bit to turn 1445 * on the external MII port. 1446 */ 1447 if (DC_IS_DAVICOM(sc)) { 1448 if (IFM_SUBTYPE(media) == IFM_homePNA) { 1449 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL); 1450 sc->dc_link = 1; 1451 } else { 1452 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL); 1453 } 1454 } 1455 1456 if ((media & IFM_GMASK) == IFM_FDX) { 1457 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_FULLDUPLEX); 1458 if (sc->dc_pmode == DC_PMODE_SYM && DC_IS_PNIC(sc)) 1459 DC_SETBIT(sc, DC_PN_NWAY, DC_PN_NWAY_DUPLEX); 1460 } else { 1461 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_FULLDUPLEX); 1462 if (sc->dc_pmode == DC_PMODE_SYM && DC_IS_PNIC(sc)) 1463 DC_CLRBIT(sc, DC_PN_NWAY, DC_PN_NWAY_DUPLEX); 1464 } 1465 1466 if (restart) 1467 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_TX_ON|DC_NETCFG_RX_ON); 1468 1469 return; 1470 } 1471 1472 static void dc_reset(sc) 1473 struct dc_softc *sc; 1474 { 1475 register int i; 1476 1477 DC_SETBIT(sc, DC_BUSCTL, DC_BUSCTL_RESET); 1478 1479 for (i = 0; i < DC_TIMEOUT; i++) { 1480 DELAY(10); 1481 if (!(CSR_READ_4(sc, DC_BUSCTL) & DC_BUSCTL_RESET)) 1482 break; 1483 } 1484 1485 if (DC_IS_ASIX(sc) || DC_IS_ADMTEK(sc) || DC_IS_CONEXANT(sc) || 1486 DC_IS_XIRCOM(sc) || DC_IS_INTEL(sc)) { 1487 DELAY(10000); 1488 DC_CLRBIT(sc, DC_BUSCTL, DC_BUSCTL_RESET); 1489 i = 0; 1490 } 1491 1492 if (i == DC_TIMEOUT) 1493 printf("dc%d: reset never completed!\n", sc->dc_unit); 1494 1495 /* Wait a little while for the chip to get its brains in order. */ 1496 DELAY(1000); 1497 1498 CSR_WRITE_4(sc, DC_IMR, 0x00000000); 1499 CSR_WRITE_4(sc, DC_BUSCTL, 0x00000000); 1500 CSR_WRITE_4(sc, DC_NETCFG, 0x00000000); 1501 1502 /* 1503 * Bring the SIA out of reset. In some cases, it looks 1504 * like failing to unreset the SIA soon enough gets it 1505 * into a state where it will never come out of reset 1506 * until we reset the whole chip again. 1507 */ 1508 if (DC_IS_INTEL(sc)) { 1509 DC_SETBIT(sc, DC_SIARESET, DC_SIA_RESET); 1510 CSR_WRITE_4(sc, DC_10BTCTRL, 0); 1511 CSR_WRITE_4(sc, DC_WATCHDOG, 0); 1512 } 1513 1514 return; 1515 } 1516 1517 static struct dc_type *dc_devtype(dev) 1518 device_t dev; 1519 { 1520 struct dc_type *t; 1521 u_int32_t rev; 1522 1523 t = dc_devs; 1524 1525 while(t->dc_name != NULL) { 1526 if ((pci_get_vendor(dev) == t->dc_vid) && 1527 (pci_get_device(dev) == t->dc_did)) { 1528 /* Check the PCI revision */ 1529 rev = pci_read_config(dev, DC_PCI_CFRV, 4) & 0xFF; 1530 if (t->dc_did == DC_DEVICEID_98713 && 1531 rev >= DC_REVISION_98713A) 1532 t++; 1533 if (t->dc_did == DC_DEVICEID_98713_CP && 1534 rev >= DC_REVISION_98713A) 1535 t++; 1536 if (t->dc_did == DC_DEVICEID_987x5 && 1537 rev >= DC_REVISION_98715AEC_C) 1538 t++; 1539 if (t->dc_did == DC_DEVICEID_987x5 && 1540 rev >= DC_REVISION_98725) 1541 t++; 1542 if (t->dc_did == DC_DEVICEID_AX88140A && 1543 rev >= DC_REVISION_88141) 1544 t++; 1545 if (t->dc_did == DC_DEVICEID_82C168 && 1546 rev >= DC_REVISION_82C169) 1547 t++; 1548 if (t->dc_did == DC_DEVICEID_DM9102 && 1549 rev >= DC_REVISION_DM9102A) 1550 t++; 1551 return(t); 1552 } 1553 t++; 1554 } 1555 1556 return(NULL); 1557 } 1558 1559 /* 1560 * Probe for a 21143 or clone chip. Check the PCI vendor and device 1561 * IDs against our list and return a device name if we find a match. 1562 * We do a little bit of extra work to identify the exact type of 1563 * chip. The MX98713 and MX98713A have the same PCI vendor/device ID, 1564 * but different revision IDs. The same is true for 98715/98715A 1565 * chips and the 98725, as well as the ASIX and ADMtek chips. In some 1566 * cases, the exact chip revision affects driver behavior. 1567 */ 1568 static int dc_probe(dev) 1569 device_t dev; 1570 { 1571 struct dc_type *t; 1572 1573 t = dc_devtype(dev); 1574 1575 if (t != NULL) { 1576 device_set_desc(dev, t->dc_name); 1577 return(0); 1578 } 1579 1580 return(ENXIO); 1581 } 1582 1583 static void dc_acpi(dev) 1584 device_t dev; 1585 { 1586 int unit; 1587 1588 unit = device_get_unit(dev); 1589 1590 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) { 1591 u_int32_t iobase, membase, irq; 1592 1593 /* Save important PCI config data. */ 1594 iobase = pci_read_config(dev, DC_PCI_CFBIO, 4); 1595 membase = pci_read_config(dev, DC_PCI_CFBMA, 4); 1596 irq = pci_read_config(dev, DC_PCI_CFIT, 4); 1597 1598 /* Reset the power state. */ 1599 printf("dc%d: chip is in D%d power mode " 1600 "-- setting to D0\n", unit, 1601 pci_get_powerstate(dev)); 1602 pci_set_powerstate(dev, PCI_POWERSTATE_D0); 1603 1604 /* Restore PCI config data. */ 1605 pci_write_config(dev, DC_PCI_CFBIO, iobase, 4); 1606 pci_write_config(dev, DC_PCI_CFBMA, membase, 4); 1607 pci_write_config(dev, DC_PCI_CFIT, irq, 4); 1608 } 1609 1610 return; 1611 } 1612 1613 static void dc_apply_fixup(sc, media) 1614 struct dc_softc *sc; 1615 int media; 1616 { 1617 struct dc_mediainfo *m; 1618 u_int8_t *p; 1619 int i; 1620 u_int32_t reg; 1621 1622 m = sc->dc_mi; 1623 1624 while (m != NULL) { 1625 if (m->dc_media == media) 1626 break; 1627 m = m->dc_next; 1628 } 1629 1630 if (m == NULL) 1631 return; 1632 1633 for (i = 0, p = m->dc_reset_ptr; i < m->dc_reset_len; i++, p += 2) { 1634 reg = (p[0] | (p[1] << 8)) << 16; 1635 CSR_WRITE_4(sc, DC_WATCHDOG, reg); 1636 } 1637 1638 for (i = 0, p = m->dc_gp_ptr; i < m->dc_gp_len; i++, p += 2) { 1639 reg = (p[0] | (p[1] << 8)) << 16; 1640 CSR_WRITE_4(sc, DC_WATCHDOG, reg); 1641 } 1642 1643 return; 1644 } 1645 1646 static void dc_decode_leaf_sia(sc, l) 1647 struct dc_softc *sc; 1648 struct dc_eblock_sia *l; 1649 { 1650 struct dc_mediainfo *m; 1651 1652 m = malloc(sizeof(struct dc_mediainfo), M_DEVBUF, M_NOWAIT); 1653 bzero(m, sizeof(struct dc_mediainfo)); 1654 if (l->dc_sia_code == DC_SIA_CODE_10BT) 1655 m->dc_media = IFM_10_T; 1656 1657 if (l->dc_sia_code == DC_SIA_CODE_10BT_FDX) 1658 m->dc_media = IFM_10_T|IFM_FDX; 1659 1660 if (l->dc_sia_code == DC_SIA_CODE_10B2) 1661 m->dc_media = IFM_10_2; 1662 1663 if (l->dc_sia_code == DC_SIA_CODE_10B5) 1664 m->dc_media = IFM_10_5; 1665 1666 m->dc_gp_len = 2; 1667 m->dc_gp_ptr = (u_int8_t *)&l->dc_sia_gpio_ctl; 1668 1669 m->dc_next = sc->dc_mi; 1670 sc->dc_mi = m; 1671 1672 sc->dc_pmode = DC_PMODE_SIA; 1673 1674 return; 1675 } 1676 1677 static void dc_decode_leaf_sym(sc, l) 1678 struct dc_softc *sc; 1679 struct dc_eblock_sym *l; 1680 { 1681 struct dc_mediainfo *m; 1682 1683 m = malloc(sizeof(struct dc_mediainfo), M_DEVBUF, M_NOWAIT); 1684 bzero(m, sizeof(struct dc_mediainfo)); 1685 if (l->dc_sym_code == DC_SYM_CODE_100BT) 1686 m->dc_media = IFM_100_TX; 1687 1688 if (l->dc_sym_code == DC_SYM_CODE_100BT_FDX) 1689 m->dc_media = IFM_100_TX|IFM_FDX; 1690 1691 m->dc_gp_len = 2; 1692 m->dc_gp_ptr = (u_int8_t *)&l->dc_sym_gpio_ctl; 1693 1694 m->dc_next = sc->dc_mi; 1695 sc->dc_mi = m; 1696 1697 sc->dc_pmode = DC_PMODE_SYM; 1698 1699 return; 1700 } 1701 1702 static void dc_decode_leaf_mii(sc, l) 1703 struct dc_softc *sc; 1704 struct dc_eblock_mii *l; 1705 { 1706 u_int8_t *p; 1707 struct dc_mediainfo *m; 1708 1709 m = malloc(sizeof(struct dc_mediainfo), M_DEVBUF, M_NOWAIT); 1710 bzero(m, sizeof(struct dc_mediainfo)); 1711 /* We abuse IFM_AUTO to represent MII. */ 1712 m->dc_media = IFM_AUTO; 1713 m->dc_gp_len = l->dc_gpr_len; 1714 1715 p = (u_int8_t *)l; 1716 p += sizeof(struct dc_eblock_mii); 1717 m->dc_gp_ptr = p; 1718 p += 2 * l->dc_gpr_len; 1719 m->dc_reset_len = *p; 1720 p++; 1721 m->dc_reset_ptr = p; 1722 1723 m->dc_next = sc->dc_mi; 1724 sc->dc_mi = m; 1725 1726 return; 1727 } 1728 1729 static void dc_parse_21143_srom(sc) 1730 struct dc_softc *sc; 1731 { 1732 struct dc_leaf_hdr *lhdr; 1733 struct dc_eblock_hdr *hdr; 1734 int i, loff; 1735 char *ptr; 1736 1737 loff = sc->dc_srom[27]; 1738 lhdr = (struct dc_leaf_hdr *)&(sc->dc_srom[loff]); 1739 1740 ptr = (char *)lhdr; 1741 ptr += sizeof(struct dc_leaf_hdr) - 1; 1742 for (i = 0; i < lhdr->dc_mcnt; i++) { 1743 hdr = (struct dc_eblock_hdr *)ptr; 1744 switch(hdr->dc_type) { 1745 case DC_EBLOCK_MII: 1746 dc_decode_leaf_mii(sc, (struct dc_eblock_mii *)hdr); 1747 break; 1748 case DC_EBLOCK_SIA: 1749 dc_decode_leaf_sia(sc, (struct dc_eblock_sia *)hdr); 1750 break; 1751 case DC_EBLOCK_SYM: 1752 dc_decode_leaf_sym(sc, (struct dc_eblock_sym *)hdr); 1753 break; 1754 default: 1755 /* Don't care. Yet. */ 1756 break; 1757 } 1758 ptr += (hdr->dc_len & 0x7F); 1759 ptr++; 1760 } 1761 1762 return; 1763 } 1764 1765 /* 1766 * Attach the interface. Allocate softc structures, do ifmedia 1767 * setup and ethernet/BPF attach. 1768 */ 1769 static int dc_attach(dev) 1770 device_t dev; 1771 { 1772 int tmp = 0; 1773 u_char eaddr[ETHER_ADDR_LEN]; 1774 u_int32_t command; 1775 struct dc_softc *sc; 1776 struct ifnet *ifp; 1777 u_int32_t revision; 1778 int unit, error = 0, rid, mac_offset; 1779 1780 sc = device_get_softc(dev); 1781 unit = device_get_unit(dev); 1782 bzero(sc, sizeof(struct dc_softc)); 1783 1784 mtx_init(&sc->dc_mtx, device_get_nameunit(dev), MTX_DEF | MTX_RECURSE); 1785 DC_LOCK(sc); 1786 1787 /* 1788 * Handle power management nonsense. 1789 */ 1790 dc_acpi(dev); 1791 1792 /* 1793 * Map control/status registers. 1794 */ 1795 pci_enable_busmaster(dev); 1796 pci_enable_io(dev, SYS_RES_IOPORT); 1797 pci_enable_io(dev, SYS_RES_MEMORY); 1798 command = pci_read_config(dev, PCIR_COMMAND, 4); 1799 1800 #ifdef DC_USEIOSPACE 1801 if (!(command & PCIM_CMD_PORTEN)) { 1802 printf("dc%d: failed to enable I/O ports!\n", unit); 1803 error = ENXIO; 1804 goto fail; 1805 } 1806 #else 1807 if (!(command & PCIM_CMD_MEMEN)) { 1808 printf("dc%d: failed to enable memory mapping!\n", unit); 1809 error = ENXIO; 1810 goto fail; 1811 } 1812 #endif 1813 1814 rid = DC_RID; 1815 sc->dc_res = bus_alloc_resource(dev, DC_RES, &rid, 1816 0, ~0, 1, RF_ACTIVE); 1817 1818 if (sc->dc_res == NULL) { 1819 printf("dc%d: couldn't map ports/memory\n", unit); 1820 error = ENXIO; 1821 goto fail; 1822 } 1823 1824 sc->dc_btag = rman_get_bustag(sc->dc_res); 1825 sc->dc_bhandle = rman_get_bushandle(sc->dc_res); 1826 1827 /* Allocate interrupt */ 1828 rid = 0; 1829 sc->dc_irq = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, 0, ~0, 1, 1830 RF_SHAREABLE | RF_ACTIVE); 1831 1832 if (sc->dc_irq == NULL) { 1833 printf("dc%d: couldn't map interrupt\n", unit); 1834 bus_release_resource(dev, DC_RES, DC_RID, sc->dc_res); 1835 error = ENXIO; 1836 goto fail; 1837 } 1838 1839 error = bus_setup_intr(dev, sc->dc_irq, INTR_TYPE_NET | 1840 (IS_MPSAFE ? INTR_MPSAFE : 0), 1841 dc_intr, sc, &sc->dc_intrhand); 1842 1843 if (error) { 1844 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->dc_irq); 1845 bus_release_resource(dev, DC_RES, DC_RID, sc->dc_res); 1846 printf("dc%d: couldn't set up irq\n", unit); 1847 goto fail; 1848 } 1849 1850 /* Need this info to decide on a chip type. */ 1851 sc->dc_info = dc_devtype(dev); 1852 revision = pci_read_config(dev, DC_PCI_CFRV, 4) & 0x000000FF; 1853 1854 switch(sc->dc_info->dc_did) { 1855 case DC_DEVICEID_21143: 1856 sc->dc_type = DC_TYPE_21143; 1857 sc->dc_flags |= DC_TX_POLL|DC_TX_USE_TX_INTR; 1858 sc->dc_flags |= DC_REDUCED_MII_POLL; 1859 /* Save EEPROM contents so we can parse them later. */ 1860 dc_read_eeprom(sc, (caddr_t)&sc->dc_srom, 0, 512, 0); 1861 break; 1862 case DC_DEVICEID_DM9100: 1863 case DC_DEVICEID_DM9102: 1864 sc->dc_type = DC_TYPE_DM9102; 1865 sc->dc_flags |= DC_TX_COALESCE|DC_TX_INTR_ALWAYS; 1866 sc->dc_flags |= DC_REDUCED_MII_POLL|DC_TX_STORENFWD; 1867 sc->dc_pmode = DC_PMODE_MII; 1868 /* Increase the latency timer value. */ 1869 command = pci_read_config(dev, DC_PCI_CFLT, 4); 1870 command &= 0xFFFF00FF; 1871 command |= 0x00008000; 1872 pci_write_config(dev, DC_PCI_CFLT, command, 4); 1873 break; 1874 case DC_DEVICEID_AL981: 1875 sc->dc_type = DC_TYPE_AL981; 1876 sc->dc_flags |= DC_TX_USE_TX_INTR; 1877 sc->dc_flags |= DC_TX_ADMTEK_WAR; 1878 sc->dc_pmode = DC_PMODE_MII; 1879 break; 1880 case DC_DEVICEID_AN985: 1881 case DC_DEVICEID_FE2500: 1882 case DC_DEVICEID_EN2242: 1883 sc->dc_type = DC_TYPE_AN985; 1884 sc->dc_flags |= DC_TX_USE_TX_INTR; 1885 sc->dc_flags |= DC_TX_ADMTEK_WAR; 1886 sc->dc_pmode = DC_PMODE_MII; 1887 break; 1888 case DC_DEVICEID_98713: 1889 case DC_DEVICEID_98713_CP: 1890 if (revision < DC_REVISION_98713A) { 1891 sc->dc_type = DC_TYPE_98713; 1892 } 1893 if (revision >= DC_REVISION_98713A) { 1894 sc->dc_type = DC_TYPE_98713A; 1895 sc->dc_flags |= DC_21143_NWAY; 1896 } 1897 sc->dc_flags |= DC_REDUCED_MII_POLL; 1898 sc->dc_flags |= DC_TX_POLL|DC_TX_USE_TX_INTR; 1899 break; 1900 case DC_DEVICEID_987x5: 1901 case DC_DEVICEID_EN1217: 1902 /* 1903 * Macronix MX98715AEC-C/D/E parts have only a 1904 * 128-bit hash table. We need to deal with these 1905 * in the same manner as the PNIC II so that we 1906 * get the right number of bits out of the 1907 * CRC routine. 1908 */ 1909 if (revision >= DC_REVISION_98715AEC_C && 1910 revision < DC_REVISION_98725) 1911 sc->dc_flags |= DC_128BIT_HASH; 1912 sc->dc_type = DC_TYPE_987x5; 1913 sc->dc_flags |= DC_TX_POLL|DC_TX_USE_TX_INTR; 1914 sc->dc_flags |= DC_REDUCED_MII_POLL|DC_21143_NWAY; 1915 break; 1916 case DC_DEVICEID_98727: 1917 sc->dc_type = DC_TYPE_987x5; 1918 sc->dc_flags |= DC_TX_POLL|DC_TX_USE_TX_INTR; 1919 sc->dc_flags |= DC_REDUCED_MII_POLL|DC_21143_NWAY; 1920 break; 1921 case DC_DEVICEID_82C115: 1922 sc->dc_type = DC_TYPE_PNICII; 1923 sc->dc_flags |= DC_TX_POLL|DC_TX_USE_TX_INTR|DC_128BIT_HASH; 1924 sc->dc_flags |= DC_REDUCED_MII_POLL|DC_21143_NWAY; 1925 break; 1926 case DC_DEVICEID_82C168: 1927 sc->dc_type = DC_TYPE_PNIC; 1928 sc->dc_flags |= DC_TX_STORENFWD|DC_TX_INTR_ALWAYS; 1929 sc->dc_flags |= DC_PNIC_RX_BUG_WAR; 1930 sc->dc_pnic_rx_buf = malloc(DC_RXLEN * 5, M_DEVBUF, M_NOWAIT); 1931 if (revision < DC_REVISION_82C169) 1932 sc->dc_pmode = DC_PMODE_SYM; 1933 break; 1934 case DC_DEVICEID_AX88140A: 1935 sc->dc_type = DC_TYPE_ASIX; 1936 sc->dc_flags |= DC_TX_USE_TX_INTR|DC_TX_INTR_FIRSTFRAG; 1937 sc->dc_flags |= DC_REDUCED_MII_POLL; 1938 sc->dc_pmode = DC_PMODE_MII; 1939 break; 1940 case DC_DEVICEID_X3201: 1941 sc->dc_type = DC_TYPE_XIRCOM; 1942 sc->dc_flags |= DC_TX_INTR_ALWAYS | DC_TX_COALESCE | 1943 DC_TX_ALIGN; 1944 /* 1945 * We don't actually need to coalesce, but we're doing 1946 * it to obtain a double word aligned buffer. 1947 * The DC_TX_COALESCE flag is required. 1948 */ 1949 break; 1950 case DC_DEVICEID_RS7112: 1951 sc->dc_type = DC_TYPE_CONEXANT; 1952 sc->dc_flags |= DC_TX_INTR_ALWAYS; 1953 sc->dc_flags |= DC_REDUCED_MII_POLL; 1954 sc->dc_pmode = DC_PMODE_MII; 1955 dc_read_eeprom(sc, (caddr_t)&sc->dc_srom, 0, 256, 0); 1956 break; 1957 default: 1958 printf("dc%d: unknown device: %x\n", sc->dc_unit, 1959 sc->dc_info->dc_did); 1960 break; 1961 } 1962 1963 /* Save the cache line size. */ 1964 if (DC_IS_DAVICOM(sc)) 1965 sc->dc_cachesize = 0; 1966 else 1967 sc->dc_cachesize = pci_read_config(dev, 1968 DC_PCI_CFLT, 4) & 0xFF; 1969 1970 /* Reset the adapter. */ 1971 dc_reset(sc); 1972 1973 /* Take 21143 out of snooze mode */ 1974 if (DC_IS_INTEL(sc) || DC_IS_XIRCOM(sc)) { 1975 command = pci_read_config(dev, DC_PCI_CFDD, 4); 1976 command &= ~(DC_CFDD_SNOOZE_MODE|DC_CFDD_SLEEP_MODE); 1977 pci_write_config(dev, DC_PCI_CFDD, command, 4); 1978 } 1979 1980 /* 1981 * Try to learn something about the supported media. 1982 * We know that ASIX and ADMtek and Davicom devices 1983 * will *always* be using MII media, so that's a no-brainer. 1984 * The tricky ones are the Macronix/PNIC II and the 1985 * Intel 21143. 1986 */ 1987 if (DC_IS_INTEL(sc)) 1988 dc_parse_21143_srom(sc); 1989 else if (DC_IS_MACRONIX(sc) || DC_IS_PNICII(sc)) { 1990 if (sc->dc_type == DC_TYPE_98713) 1991 sc->dc_pmode = DC_PMODE_MII; 1992 else 1993 sc->dc_pmode = DC_PMODE_SYM; 1994 } else if (!sc->dc_pmode) 1995 sc->dc_pmode = DC_PMODE_MII; 1996 1997 /* 1998 * Get station address from the EEPROM. 1999 */ 2000 switch(sc->dc_type) { 2001 case DC_TYPE_98713: 2002 case DC_TYPE_98713A: 2003 case DC_TYPE_987x5: 2004 case DC_TYPE_PNICII: 2005 dc_read_eeprom(sc, (caddr_t)&mac_offset, 2006 (DC_EE_NODEADDR_OFFSET / 2), 1, 0); 2007 dc_read_eeprom(sc, (caddr_t)&eaddr, (mac_offset / 2), 3, 0); 2008 break; 2009 case DC_TYPE_PNIC: 2010 dc_read_eeprom(sc, (caddr_t)&eaddr, 0, 3, 1); 2011 break; 2012 case DC_TYPE_DM9102: 2013 case DC_TYPE_21143: 2014 case DC_TYPE_ASIX: 2015 dc_read_eeprom(sc, (caddr_t)&eaddr, DC_EE_NODEADDR, 3, 0); 2016 break; 2017 case DC_TYPE_AL981: 2018 case DC_TYPE_AN985: 2019 dc_read_eeprom(sc, (caddr_t)&eaddr, DC_AL_EE_NODEADDR, 3, 0); 2020 break; 2021 case DC_TYPE_CONEXANT: 2022 bcopy(sc->dc_srom + DC_CONEXANT_EE_NODEADDR, &eaddr, 6); 2023 break; 2024 case DC_TYPE_XIRCOM: 2025 dc_read_eeprom(sc, (caddr_t)&eaddr, 3, 3, 0); 2026 break; 2027 default: 2028 dc_read_eeprom(sc, (caddr_t)&eaddr, DC_EE_NODEADDR, 3, 0); 2029 break; 2030 } 2031 2032 /* 2033 * A 21143 or clone chip was detected. Inform the world. 2034 */ 2035 printf("dc%d: Ethernet address: %6D\n", unit, eaddr, ":"); 2036 2037 sc->dc_unit = unit; 2038 bcopy(eaddr, (char *)&sc->arpcom.ac_enaddr, ETHER_ADDR_LEN); 2039 2040 sc->dc_ldata = contigmalloc(sizeof(struct dc_list_data), M_DEVBUF, 2041 M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0); 2042 2043 if (sc->dc_ldata == NULL) { 2044 printf("dc%d: no memory for list buffers!\n", unit); 2045 bus_teardown_intr(dev, sc->dc_irq, sc->dc_intrhand); 2046 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->dc_irq); 2047 bus_release_resource(dev, DC_RES, DC_RID, sc->dc_res); 2048 error = ENXIO; 2049 goto fail; 2050 } 2051 2052 bzero(sc->dc_ldata, sizeof(struct dc_list_data)); 2053 2054 ifp = &sc->arpcom.ac_if; 2055 ifp->if_softc = sc; 2056 ifp->if_unit = unit; 2057 ifp->if_name = "dc"; 2058 /* XXX: bleah, MTU gets overwritten in ether_ifattach() */ 2059 ifp->if_mtu = ETHERMTU; 2060 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 2061 ifp->if_ioctl = dc_ioctl; 2062 ifp->if_output = ether_output; 2063 ifp->if_start = dc_start; 2064 ifp->if_watchdog = dc_watchdog; 2065 ifp->if_init = dc_init; 2066 ifp->if_baudrate = 10000000; 2067 ifp->if_snd.ifq_maxlen = DC_TX_LIST_CNT - 1; 2068 2069 /* 2070 * Do MII setup. If this is a 21143, check for a PHY on the 2071 * MII bus after applying any necessary fixups to twiddle the 2072 * GPIO bits. If we don't end up finding a PHY, restore the 2073 * old selection (SIA only or SIA/SYM) and attach the dcphy 2074 * driver instead. 2075 */ 2076 if (DC_IS_INTEL(sc)) { 2077 dc_apply_fixup(sc, IFM_AUTO); 2078 tmp = sc->dc_pmode; 2079 sc->dc_pmode = DC_PMODE_MII; 2080 } 2081 2082 error = mii_phy_probe(dev, &sc->dc_miibus, 2083 dc_ifmedia_upd, dc_ifmedia_sts); 2084 2085 if (error && DC_IS_INTEL(sc)) { 2086 sc->dc_pmode = tmp; 2087 if (sc->dc_pmode != DC_PMODE_SIA) 2088 sc->dc_pmode = DC_PMODE_SYM; 2089 sc->dc_flags |= DC_21143_NWAY; 2090 mii_phy_probe(dev, &sc->dc_miibus, 2091 dc_ifmedia_upd, dc_ifmedia_sts); 2092 /* 2093 * For non-MII cards, we need to have the 21143 2094 * drive the LEDs. Except there are some systems 2095 * like the NEC VersaPro NoteBook PC which have no 2096 * LEDs, and twiddling these bits has adverse effects 2097 * on them. (I.e. you suddenly can't get a link.) 2098 */ 2099 if (pci_read_config(dev, DC_PCI_CSID, 4) != 0x80281033) 2100 sc->dc_flags |= DC_TULIP_LEDS; 2101 error = 0; 2102 } 2103 2104 if (error) { 2105 printf("dc%d: MII without any PHY!\n", sc->dc_unit); 2106 bus_teardown_intr(dev, sc->dc_irq, sc->dc_intrhand); 2107 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->dc_irq); 2108 bus_release_resource(dev, DC_RES, DC_RID, sc->dc_res); 2109 error = ENXIO; 2110 goto fail; 2111 } 2112 2113 if (DC_IS_XIRCOM(sc)) { 2114 /* 2115 * setup General Purpose Port mode and data so the tulip 2116 * can talk to the MII. 2117 */ 2118 CSR_WRITE_4(sc, DC_SIAGP, DC_SIAGP_WRITE_EN | DC_SIAGP_INT1_EN | 2119 DC_SIAGP_MD_GP2_OUTPUT | DC_SIAGP_MD_GP0_OUTPUT); 2120 DELAY(10); 2121 CSR_WRITE_4(sc, DC_SIAGP, DC_SIAGP_INT1_EN | 2122 DC_SIAGP_MD_GP2_OUTPUT | DC_SIAGP_MD_GP0_OUTPUT); 2123 DELAY(10); 2124 } 2125 2126 /* 2127 * Call MI attach routine. 2128 */ 2129 ether_ifattach(ifp, ETHER_BPF_SUPPORTED); 2130 2131 /* 2132 * Tell the upper layer(s) we support long frames. 2133 */ 2134 ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header); 2135 2136 callout_init(&sc->dc_stat_ch, IS_MPSAFE); 2137 2138 #ifdef SRM_MEDIA 2139 sc->dc_srm_media = 0; 2140 2141 /* Remember the SRM console media setting */ 2142 if (DC_IS_INTEL(sc)) { 2143 command = pci_read_config(dev, DC_PCI_CFDD, 4); 2144 command &= ~(DC_CFDD_SNOOZE_MODE|DC_CFDD_SLEEP_MODE); 2145 switch ((command >> 8) & 0xff) { 2146 case 3: 2147 sc->dc_srm_media = IFM_10_T; 2148 break; 2149 case 4: 2150 sc->dc_srm_media = IFM_10_T | IFM_FDX; 2151 break; 2152 case 5: 2153 sc->dc_srm_media = IFM_100_TX; 2154 break; 2155 case 6: 2156 sc->dc_srm_media = IFM_100_TX | IFM_FDX; 2157 break; 2158 } 2159 if (sc->dc_srm_media) 2160 sc->dc_srm_media |= IFM_ACTIVE | IFM_ETHER; 2161 } 2162 #endif 2163 2164 DC_UNLOCK(sc); 2165 return(0); 2166 2167 fail: 2168 DC_UNLOCK(sc); 2169 mtx_destroy(&sc->dc_mtx); 2170 return(error); 2171 } 2172 2173 static int dc_detach(dev) 2174 device_t dev; 2175 { 2176 struct dc_softc *sc; 2177 struct ifnet *ifp; 2178 struct dc_mediainfo *m; 2179 2180 sc = device_get_softc(dev); 2181 2182 DC_LOCK(sc); 2183 2184 ifp = &sc->arpcom.ac_if; 2185 2186 dc_stop(sc); 2187 ether_ifdetach(ifp, ETHER_BPF_SUPPORTED); 2188 2189 bus_generic_detach(dev); 2190 device_delete_child(dev, sc->dc_miibus); 2191 2192 bus_teardown_intr(dev, sc->dc_irq, sc->dc_intrhand); 2193 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->dc_irq); 2194 bus_release_resource(dev, DC_RES, DC_RID, sc->dc_res); 2195 2196 contigfree(sc->dc_ldata, sizeof(struct dc_list_data), M_DEVBUF); 2197 if (sc->dc_pnic_rx_buf != NULL) 2198 free(sc->dc_pnic_rx_buf, M_DEVBUF); 2199 2200 while(sc->dc_mi != NULL) { 2201 m = sc->dc_mi->dc_next; 2202 free(sc->dc_mi, M_DEVBUF); 2203 sc->dc_mi = m; 2204 } 2205 2206 DC_UNLOCK(sc); 2207 mtx_destroy(&sc->dc_mtx); 2208 2209 return(0); 2210 } 2211 2212 /* 2213 * Initialize the transmit descriptors. 2214 */ 2215 static int dc_list_tx_init(sc) 2216 struct dc_softc *sc; 2217 { 2218 struct dc_chain_data *cd; 2219 struct dc_list_data *ld; 2220 int i, nexti; 2221 2222 cd = &sc->dc_cdata; 2223 ld = sc->dc_ldata; 2224 for (i = 0; i < DC_TX_LIST_CNT; i++) { 2225 nexti = (i == (DC_TX_LIST_CNT - 1)) ? 0 : i+1; 2226 ld->dc_tx_list[i].dc_next = vtophys(&ld->dc_tx_list[nexti]); 2227 cd->dc_tx_chain[i] = NULL; 2228 ld->dc_tx_list[i].dc_data = 0; 2229 ld->dc_tx_list[i].dc_ctl = 0; 2230 } 2231 2232 cd->dc_tx_prod = cd->dc_tx_cons = cd->dc_tx_cnt = 0; 2233 2234 return(0); 2235 } 2236 2237 2238 /* 2239 * Initialize the RX descriptors and allocate mbufs for them. Note that 2240 * we arrange the descriptors in a closed ring, so that the last descriptor 2241 * points back to the first. 2242 */ 2243 static int dc_list_rx_init(sc) 2244 struct dc_softc *sc; 2245 { 2246 struct dc_chain_data *cd; 2247 struct dc_list_data *ld; 2248 int i, nexti; 2249 2250 cd = &sc->dc_cdata; 2251 ld = sc->dc_ldata; 2252 2253 for (i = 0; i < DC_RX_LIST_CNT; i++) { 2254 if (dc_newbuf(sc, i, NULL) == ENOBUFS) 2255 return(ENOBUFS); 2256 nexti = (i == (DC_RX_LIST_CNT - 1)) ? 0 : i+1; 2257 ld->dc_rx_list[i].dc_next = vtophys(&ld->dc_rx_list[nexti]); 2258 } 2259 2260 cd->dc_rx_prod = 0; 2261 2262 return(0); 2263 } 2264 2265 /* 2266 * Initialize an RX descriptor and attach an MBUF cluster. 2267 */ 2268 static int dc_newbuf(sc, i, m) 2269 struct dc_softc *sc; 2270 int i; 2271 struct mbuf *m; 2272 { 2273 struct mbuf *m_new = NULL; 2274 struct dc_desc *c; 2275 2276 c = &sc->dc_ldata->dc_rx_list[i]; 2277 2278 if (m == NULL) { 2279 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 2280 if (m_new == NULL) 2281 return(ENOBUFS); 2282 2283 MCLGET(m_new, M_DONTWAIT); 2284 if (!(m_new->m_flags & M_EXT)) { 2285 m_freem(m_new); 2286 return(ENOBUFS); 2287 } 2288 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 2289 } else { 2290 m_new = m; 2291 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 2292 m_new->m_data = m_new->m_ext.ext_buf; 2293 } 2294 2295 m_adj(m_new, sizeof(u_int64_t)); 2296 2297 /* 2298 * If this is a PNIC chip, zero the buffer. This is part 2299 * of the workaround for the receive bug in the 82c168 and 2300 * 82c169 chips. 2301 */ 2302 if (sc->dc_flags & DC_PNIC_RX_BUG_WAR) 2303 bzero((char *)mtod(m_new, char *), m_new->m_len); 2304 2305 sc->dc_cdata.dc_rx_chain[i] = m_new; 2306 c->dc_data = vtophys(mtod(m_new, caddr_t)); 2307 c->dc_ctl = DC_RXCTL_RLINK | DC_RXLEN; 2308 c->dc_status = DC_RXSTAT_OWN; 2309 2310 return(0); 2311 } 2312 2313 /* 2314 * Grrrrr. 2315 * The PNIC chip has a terrible bug in it that manifests itself during 2316 * periods of heavy activity. The exact mode of failure if difficult to 2317 * pinpoint: sometimes it only happens in promiscuous mode, sometimes it 2318 * will happen on slow machines. The bug is that sometimes instead of 2319 * uploading one complete frame during reception, it uploads what looks 2320 * like the entire contents of its FIFO memory. The frame we want is at 2321 * the end of the whole mess, but we never know exactly how much data has 2322 * been uploaded, so salvaging the frame is hard. 2323 * 2324 * There is only one way to do it reliably, and it's disgusting. 2325 * Here's what we know: 2326 * 2327 * - We know there will always be somewhere between one and three extra 2328 * descriptors uploaded. 2329 * 2330 * - We know the desired received frame will always be at the end of the 2331 * total data upload. 2332 * 2333 * - We know the size of the desired received frame because it will be 2334 * provided in the length field of the status word in the last descriptor. 2335 * 2336 * Here's what we do: 2337 * 2338 * - When we allocate buffers for the receive ring, we bzero() them. 2339 * This means that we know that the buffer contents should be all 2340 * zeros, except for data uploaded by the chip. 2341 * 2342 * - We also force the PNIC chip to upload frames that include the 2343 * ethernet CRC at the end. 2344 * 2345 * - We gather all of the bogus frame data into a single buffer. 2346 * 2347 * - We then position a pointer at the end of this buffer and scan 2348 * backwards until we encounter the first non-zero byte of data. 2349 * This is the end of the received frame. We know we will encounter 2350 * some data at the end of the frame because the CRC will always be 2351 * there, so even if the sender transmits a packet of all zeros, 2352 * we won't be fooled. 2353 * 2354 * - We know the size of the actual received frame, so we subtract 2355 * that value from the current pointer location. This brings us 2356 * to the start of the actual received packet. 2357 * 2358 * - We copy this into an mbuf and pass it on, along with the actual 2359 * frame length. 2360 * 2361 * The performance hit is tremendous, but it beats dropping frames all 2362 * the time. 2363 */ 2364 2365 #define DC_WHOLEFRAME (DC_RXSTAT_FIRSTFRAG|DC_RXSTAT_LASTFRAG) 2366 static void dc_pnic_rx_bug_war(sc, idx) 2367 struct dc_softc *sc; 2368 int idx; 2369 { 2370 struct dc_desc *cur_rx; 2371 struct dc_desc *c = NULL; 2372 struct mbuf *m = NULL; 2373 unsigned char *ptr; 2374 int i, total_len; 2375 u_int32_t rxstat = 0; 2376 2377 i = sc->dc_pnic_rx_bug_save; 2378 cur_rx = &sc->dc_ldata->dc_rx_list[idx]; 2379 ptr = sc->dc_pnic_rx_buf; 2380 bzero(ptr, sizeof(DC_RXLEN * 5)); 2381 2382 /* Copy all the bytes from the bogus buffers. */ 2383 while (1) { 2384 c = &sc->dc_ldata->dc_rx_list[i]; 2385 rxstat = c->dc_status; 2386 m = sc->dc_cdata.dc_rx_chain[i]; 2387 bcopy(mtod(m, char *), ptr, DC_RXLEN); 2388 ptr += DC_RXLEN; 2389 /* If this is the last buffer, break out. */ 2390 if (i == idx || rxstat & DC_RXSTAT_LASTFRAG) 2391 break; 2392 dc_newbuf(sc, i, m); 2393 DC_INC(i, DC_RX_LIST_CNT); 2394 } 2395 2396 /* Find the length of the actual receive frame. */ 2397 total_len = DC_RXBYTES(rxstat); 2398 2399 /* Scan backwards until we hit a non-zero byte. */ 2400 while(*ptr == 0x00) 2401 ptr--; 2402 2403 /* Round off. */ 2404 if ((uintptr_t)(ptr) & 0x3) 2405 ptr -= 1; 2406 2407 /* Now find the start of the frame. */ 2408 ptr -= total_len; 2409 if (ptr < sc->dc_pnic_rx_buf) 2410 ptr = sc->dc_pnic_rx_buf; 2411 2412 /* 2413 * Now copy the salvaged frame to the last mbuf and fake up 2414 * the status word to make it look like a successful 2415 * frame reception. 2416 */ 2417 dc_newbuf(sc, i, m); 2418 bcopy(ptr, mtod(m, char *), total_len); 2419 cur_rx->dc_status = rxstat | DC_RXSTAT_FIRSTFRAG; 2420 2421 return; 2422 } 2423 2424 /* 2425 * This routine searches the RX ring for dirty descriptors in the 2426 * event that the rxeof routine falls out of sync with the chip's 2427 * current descriptor pointer. This may happen sometimes as a result 2428 * of a "no RX buffer available" condition that happens when the chip 2429 * consumes all of the RX buffers before the driver has a chance to 2430 * process the RX ring. This routine may need to be called more than 2431 * once to bring the driver back in sync with the chip, however we 2432 * should still be getting RX DONE interrupts to drive the search 2433 * for new packets in the RX ring, so we should catch up eventually. 2434 */ 2435 static int dc_rx_resync(sc) 2436 struct dc_softc *sc; 2437 { 2438 int i, pos; 2439 struct dc_desc *cur_rx; 2440 2441 pos = sc->dc_cdata.dc_rx_prod; 2442 2443 for (i = 0; i < DC_RX_LIST_CNT; i++) { 2444 cur_rx = &sc->dc_ldata->dc_rx_list[pos]; 2445 if (!(cur_rx->dc_status & DC_RXSTAT_OWN)) 2446 break; 2447 DC_INC(pos, DC_RX_LIST_CNT); 2448 } 2449 2450 /* If the ring really is empty, then just return. */ 2451 if (i == DC_RX_LIST_CNT) 2452 return(0); 2453 2454 /* We've fallen behing the chip: catch it. */ 2455 sc->dc_cdata.dc_rx_prod = pos; 2456 2457 return(EAGAIN); 2458 } 2459 2460 /* 2461 * A frame has been uploaded: pass the resulting mbuf chain up to 2462 * the higher level protocols. 2463 */ 2464 static void dc_rxeof(sc) 2465 struct dc_softc *sc; 2466 { 2467 struct ether_header *eh; 2468 struct mbuf *m; 2469 struct ifnet *ifp; 2470 struct dc_desc *cur_rx; 2471 int i, total_len = 0; 2472 u_int32_t rxstat; 2473 2474 ifp = &sc->arpcom.ac_if; 2475 i = sc->dc_cdata.dc_rx_prod; 2476 2477 while(!(sc->dc_ldata->dc_rx_list[i].dc_status & DC_RXSTAT_OWN)) { 2478 2479 #ifdef DEVICE_POLLING 2480 if (ifp->if_ipending & IFF_POLLING) { 2481 if (sc->rxcycles <= 0) 2482 break; 2483 sc->rxcycles--; 2484 } 2485 #endif /* DEVICE_POLLING */ 2486 cur_rx = &sc->dc_ldata->dc_rx_list[i]; 2487 rxstat = cur_rx->dc_status; 2488 m = sc->dc_cdata.dc_rx_chain[i]; 2489 total_len = DC_RXBYTES(rxstat); 2490 2491 if (sc->dc_flags & DC_PNIC_RX_BUG_WAR) { 2492 if ((rxstat & DC_WHOLEFRAME) != DC_WHOLEFRAME) { 2493 if (rxstat & DC_RXSTAT_FIRSTFRAG) 2494 sc->dc_pnic_rx_bug_save = i; 2495 if ((rxstat & DC_RXSTAT_LASTFRAG) == 0) { 2496 DC_INC(i, DC_RX_LIST_CNT); 2497 continue; 2498 } 2499 dc_pnic_rx_bug_war(sc, i); 2500 rxstat = cur_rx->dc_status; 2501 total_len = DC_RXBYTES(rxstat); 2502 } 2503 } 2504 2505 sc->dc_cdata.dc_rx_chain[i] = NULL; 2506 2507 /* 2508 * If an error occurs, update stats, clear the 2509 * status word and leave the mbuf cluster in place: 2510 * it should simply get re-used next time this descriptor 2511 * comes up in the ring. However, don't report long 2512 * frames as errors since they could be vlans 2513 */ 2514 if ((rxstat & DC_RXSTAT_RXERR)){ 2515 if (!(rxstat & DC_RXSTAT_GIANT) || 2516 (rxstat & (DC_RXSTAT_CRCERR | DC_RXSTAT_DRIBBLE | 2517 DC_RXSTAT_MIIERE | DC_RXSTAT_COLLSEEN | 2518 DC_RXSTAT_RUNT | DC_RXSTAT_DE))) { 2519 ifp->if_ierrors++; 2520 if (rxstat & DC_RXSTAT_COLLSEEN) 2521 ifp->if_collisions++; 2522 dc_newbuf(sc, i, m); 2523 if (rxstat & DC_RXSTAT_CRCERR) { 2524 DC_INC(i, DC_RX_LIST_CNT); 2525 continue; 2526 } else { 2527 dc_init(sc); 2528 return; 2529 } 2530 } 2531 } 2532 2533 /* No errors; receive the packet. */ 2534 total_len -= ETHER_CRC_LEN; 2535 #ifdef __i386__ 2536 /* 2537 * On the x86 we do not have alignment problems, so try to 2538 * allocate a new buffer for the receive ring, and pass up 2539 * the one where the packet is already, saving the expensive 2540 * copy done in m_devget(). 2541 * If we are on an architecture with alignment problems, or 2542 * if the allocation fails, then use m_devget and leave the 2543 * existing buffer in the receive ring. 2544 */ 2545 if (dc_quick && dc_newbuf(sc, i, NULL) == 0) { 2546 m->m_pkthdr.rcvif = ifp; 2547 m->m_pkthdr.len = m->m_len = total_len; 2548 DC_INC(i, DC_RX_LIST_CNT); 2549 } else 2550 #endif 2551 { 2552 struct mbuf *m0; 2553 2554 m0 = m_devget(mtod(m, char *), total_len, 2555 ETHER_ALIGN, ifp, NULL); 2556 dc_newbuf(sc, i, m); 2557 DC_INC(i, DC_RX_LIST_CNT); 2558 if (m0 == NULL) { 2559 ifp->if_ierrors++; 2560 continue; 2561 } 2562 m = m0; 2563 } 2564 2565 ifp->if_ipackets++; 2566 eh = mtod(m, struct ether_header *); 2567 2568 /* Remove header from mbuf and pass it on. */ 2569 m_adj(m, sizeof(struct ether_header)); 2570 ether_input(ifp, eh, m); 2571 } 2572 2573 sc->dc_cdata.dc_rx_prod = i; 2574 } 2575 2576 /* 2577 * A frame was downloaded to the chip. It's safe for us to clean up 2578 * the list buffers. 2579 */ 2580 2581 static void dc_txeof(sc) 2582 struct dc_softc *sc; 2583 { 2584 struct dc_desc *cur_tx = NULL; 2585 struct ifnet *ifp; 2586 int idx; 2587 2588 ifp = &sc->arpcom.ac_if; 2589 2590 /* Clear the timeout timer. */ 2591 ifp->if_timer = 0; 2592 2593 /* 2594 * Go through our tx list and free mbufs for those 2595 * frames that have been transmitted. 2596 */ 2597 idx = sc->dc_cdata.dc_tx_cons; 2598 while(idx != sc->dc_cdata.dc_tx_prod) { 2599 u_int32_t txstat; 2600 2601 cur_tx = &sc->dc_ldata->dc_tx_list[idx]; 2602 txstat = cur_tx->dc_status; 2603 2604 if (txstat & DC_TXSTAT_OWN) 2605 break; 2606 2607 if (!(cur_tx->dc_ctl & DC_TXCTL_LASTFRAG) || 2608 cur_tx->dc_ctl & DC_TXCTL_SETUP) { 2609 sc->dc_cdata.dc_tx_cnt--; 2610 if (cur_tx->dc_ctl & DC_TXCTL_SETUP) { 2611 /* 2612 * Yes, the PNIC is so brain damaged 2613 * that it will sometimes generate a TX 2614 * underrun error while DMAing the RX 2615 * filter setup frame. If we detect this, 2616 * we have to send the setup frame again, 2617 * or else the filter won't be programmed 2618 * correctly. 2619 */ 2620 if (DC_IS_PNIC(sc)) { 2621 if (txstat & DC_TXSTAT_ERRSUM) 2622 dc_setfilt(sc); 2623 } 2624 sc->dc_cdata.dc_tx_chain[idx] = NULL; 2625 } 2626 DC_INC(idx, DC_TX_LIST_CNT); 2627 continue; 2628 } 2629 2630 if (DC_IS_XIRCOM(sc) || DC_IS_CONEXANT(sc)) { 2631 /* 2632 * XXX: Why does my Xircom taunt me so? 2633 * For some reason it likes setting the CARRLOST flag 2634 * even when the carrier is there. wtf?!? 2635 * Who knows, but Conexant chips have the 2636 * same problem. Maybe they took lessons 2637 * from Xircom. 2638 */ 2639 if (/*sc->dc_type == DC_TYPE_21143 &&*/ 2640 sc->dc_pmode == DC_PMODE_MII && 2641 ((txstat & 0xFFFF) & ~(DC_TXSTAT_ERRSUM| 2642 DC_TXSTAT_NOCARRIER))) 2643 txstat &= ~DC_TXSTAT_ERRSUM; 2644 } else { 2645 if (/*sc->dc_type == DC_TYPE_21143 &&*/ 2646 sc->dc_pmode == DC_PMODE_MII && 2647 ((txstat & 0xFFFF) & ~(DC_TXSTAT_ERRSUM| 2648 DC_TXSTAT_NOCARRIER|DC_TXSTAT_CARRLOST))) 2649 txstat &= ~DC_TXSTAT_ERRSUM; 2650 } 2651 2652 if (txstat & DC_TXSTAT_ERRSUM) { 2653 ifp->if_oerrors++; 2654 if (txstat & DC_TXSTAT_EXCESSCOLL) 2655 ifp->if_collisions++; 2656 if (txstat & DC_TXSTAT_LATECOLL) 2657 ifp->if_collisions++; 2658 if (!(txstat & DC_TXSTAT_UNDERRUN)) { 2659 dc_init(sc); 2660 return; 2661 } 2662 } 2663 2664 ifp->if_collisions += (txstat & DC_TXSTAT_COLLCNT) >> 3; 2665 2666 ifp->if_opackets++; 2667 if (sc->dc_cdata.dc_tx_chain[idx] != NULL) { 2668 m_freem(sc->dc_cdata.dc_tx_chain[idx]); 2669 sc->dc_cdata.dc_tx_chain[idx] = NULL; 2670 } 2671 2672 sc->dc_cdata.dc_tx_cnt--; 2673 DC_INC(idx, DC_TX_LIST_CNT); 2674 } 2675 2676 sc->dc_cdata.dc_tx_cons = idx; 2677 if (cur_tx != NULL) 2678 ifp->if_flags &= ~IFF_OACTIVE; 2679 2680 return; 2681 } 2682 2683 static void dc_tick(xsc) 2684 void *xsc; 2685 { 2686 struct dc_softc *sc; 2687 struct mii_data *mii; 2688 struct ifnet *ifp; 2689 u_int32_t r; 2690 2691 sc = xsc; 2692 DC_LOCK(sc); 2693 ifp = &sc->arpcom.ac_if; 2694 mii = device_get_softc(sc->dc_miibus); 2695 2696 if (sc->dc_flags & DC_REDUCED_MII_POLL) { 2697 if (sc->dc_flags & DC_21143_NWAY) { 2698 r = CSR_READ_4(sc, DC_10BTSTAT); 2699 if (IFM_SUBTYPE(mii->mii_media_active) == 2700 IFM_100_TX && (r & DC_TSTAT_LS100)) { 2701 sc->dc_link = 0; 2702 mii_mediachg(mii); 2703 } 2704 if (IFM_SUBTYPE(mii->mii_media_active) == 2705 IFM_10_T && (r & DC_TSTAT_LS10)) { 2706 sc->dc_link = 0; 2707 mii_mediachg(mii); 2708 } 2709 if (sc->dc_link == 0) 2710 mii_tick(mii); 2711 } else { 2712 r = CSR_READ_4(sc, DC_ISR); 2713 if ((r & DC_ISR_RX_STATE) == DC_RXSTATE_WAIT && 2714 sc->dc_cdata.dc_tx_cnt == 0) 2715 mii_tick(mii); 2716 if (!(mii->mii_media_status & IFM_ACTIVE)) 2717 sc->dc_link = 0; 2718 } 2719 } else 2720 mii_tick(mii); 2721 2722 /* 2723 * When the init routine completes, we expect to be able to send 2724 * packets right away, and in fact the network code will send a 2725 * gratuitous ARP the moment the init routine marks the interface 2726 * as running. However, even though the MAC may have been initialized, 2727 * there may be a delay of a few seconds before the PHY completes 2728 * autonegotiation and the link is brought up. Any transmissions 2729 * made during that delay will be lost. Dealing with this is tricky: 2730 * we can't just pause in the init routine while waiting for the 2731 * PHY to come ready since that would bring the whole system to 2732 * a screeching halt for several seconds. 2733 * 2734 * What we do here is prevent the TX start routine from sending 2735 * any packets until a link has been established. After the 2736 * interface has been initialized, the tick routine will poll 2737 * the state of the PHY until the IFM_ACTIVE flag is set. Until 2738 * that time, packets will stay in the send queue, and once the 2739 * link comes up, they will be flushed out to the wire. 2740 */ 2741 if (!sc->dc_link && mii->mii_media_status & IFM_ACTIVE && 2742 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) { 2743 sc->dc_link++; 2744 if (ifp->if_snd.ifq_head != NULL) 2745 dc_start(ifp); 2746 } 2747 2748 if (sc->dc_flags & DC_21143_NWAY && !sc->dc_link) 2749 callout_reset(&sc->dc_stat_ch, hz/10, dc_tick, sc); 2750 else 2751 callout_reset(&sc->dc_stat_ch, hz, dc_tick, sc); 2752 2753 DC_UNLOCK(sc); 2754 2755 return; 2756 } 2757 2758 /* 2759 * A transmit underrun has occurred. Back off the transmit threshold, 2760 * or switch to store and forward mode if we have to. 2761 */ 2762 static void dc_tx_underrun(sc) 2763 struct dc_softc *sc; 2764 { 2765 u_int32_t isr; 2766 int i; 2767 2768 if (DC_IS_DAVICOM(sc)) 2769 dc_init(sc); 2770 2771 if (DC_IS_INTEL(sc)) { 2772 /* 2773 * The real 21143 requires that the transmitter be idle 2774 * in order to change the transmit threshold or store 2775 * and forward state. 2776 */ 2777 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_TX_ON); 2778 2779 for (i = 0; i < DC_TIMEOUT; i++) { 2780 isr = CSR_READ_4(sc, DC_ISR); 2781 if (isr & DC_ISR_TX_IDLE) 2782 break; 2783 DELAY(10); 2784 } 2785 if (i == DC_TIMEOUT) { 2786 printf("dc%d: failed to force tx to idle state\n", 2787 sc->dc_unit); 2788 dc_init(sc); 2789 } 2790 } 2791 2792 printf("dc%d: TX underrun -- ", sc->dc_unit); 2793 sc->dc_txthresh += DC_TXTHRESH_INC; 2794 if (sc->dc_txthresh > DC_TXTHRESH_MAX) { 2795 printf("using store and forward mode\n"); 2796 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_STORENFWD); 2797 } else { 2798 printf("increasing TX threshold\n"); 2799 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_TX_THRESH); 2800 DC_SETBIT(sc, DC_NETCFG, sc->dc_txthresh); 2801 } 2802 2803 if (DC_IS_INTEL(sc)) 2804 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_TX_ON); 2805 2806 return; 2807 } 2808 2809 #ifdef DEVICE_POLLING 2810 static poll_handler_t dc_poll; 2811 2812 static void 2813 dc_poll(struct ifnet *ifp, enum poll_cmd cmd, int count) 2814 { 2815 struct dc_softc *sc = ifp->if_softc; 2816 2817 if (cmd == POLL_DEREGISTER) { /* final call, enable interrupts */ 2818 /* Re-enable interrupts. */ 2819 CSR_WRITE_4(sc, DC_IMR, DC_INTRS); 2820 return; 2821 } 2822 sc->rxcycles = count; 2823 dc_rxeof(sc); 2824 dc_txeof(sc); 2825 if (ifp->if_snd.ifq_head != NULL && !(ifp->if_flags & IFF_OACTIVE)) 2826 dc_start(ifp); 2827 2828 if (cmd == POLL_AND_CHECK_STATUS) { /* also check status register */ 2829 u_int32_t status; 2830 2831 status = CSR_READ_4(sc, DC_ISR); 2832 status &= (DC_ISR_RX_WATDOGTIMEO|DC_ISR_RX_NOBUF| 2833 DC_ISR_TX_NOBUF|DC_ISR_TX_IDLE|DC_ISR_TX_UNDERRUN| 2834 DC_ISR_BUS_ERR); 2835 if (!status) 2836 return; 2837 /* ack what we have */ 2838 CSR_WRITE_4(sc, DC_ISR, status); 2839 2840 if (status & (DC_ISR_RX_WATDOGTIMEO|DC_ISR_RX_NOBUF)) { 2841 u_int32_t r = CSR_READ_4(sc, DC_FRAMESDISCARDED); 2842 ifp->if_ierrors += (r & 0xffff) + ((r >> 17) & 0x7ff); 2843 2844 if (dc_rx_resync(sc)) 2845 dc_rxeof(sc); 2846 } 2847 /* restart transmit unit if necessary */ 2848 if (status & DC_ISR_TX_IDLE && sc->dc_cdata.dc_tx_cnt) 2849 CSR_WRITE_4(sc, DC_TXSTART, 0xFFFFFFFF); 2850 2851 if (status & DC_ISR_TX_UNDERRUN) 2852 dc_tx_underrun(sc); 2853 2854 if (status & DC_ISR_BUS_ERR) { 2855 printf("dc_poll: dc%d bus error\n", sc->dc_unit); 2856 dc_reset(sc); 2857 dc_init(sc); 2858 } 2859 } 2860 } 2861 #endif /* DEVICE_POLLING */ 2862 2863 static void dc_intr(arg) 2864 void *arg; 2865 { 2866 struct dc_softc *sc; 2867 struct ifnet *ifp; 2868 u_int32_t status; 2869 2870 sc = arg; 2871 2872 if ((CSR_READ_4(sc, DC_ISR) & DC_INTRS) == 0) 2873 return; 2874 2875 DC_LOCK(sc); 2876 ifp = &sc->arpcom.ac_if; 2877 #ifdef DEVICE_POLLING 2878 if (ifp->if_ipending & IFF_POLLING) 2879 goto done; 2880 if (ether_poll_register(dc_poll, ifp)) { /* ok, disable interrupts */ 2881 CSR_WRITE_4(sc, DC_IMR, 0x00000000); 2882 goto done; 2883 } 2884 #endif /* DEVICE_POLLING */ 2885 2886 /* Suppress unwanted interrupts */ 2887 if (!(ifp->if_flags & IFF_UP)) { 2888 if (CSR_READ_4(sc, DC_ISR) & DC_INTRS) 2889 dc_stop(sc); 2890 DC_UNLOCK(sc); 2891 return; 2892 } 2893 2894 /* Disable interrupts. */ 2895 CSR_WRITE_4(sc, DC_IMR, 0x00000000); 2896 2897 while(((status = CSR_READ_4(sc, DC_ISR)) & DC_INTRS) 2898 && status != 0xFFFFFFFF) { 2899 2900 CSR_WRITE_4(sc, DC_ISR, status); 2901 2902 if (status & DC_ISR_RX_OK) { 2903 int curpkts; 2904 curpkts = ifp->if_ipackets; 2905 dc_rxeof(sc); 2906 if (curpkts == ifp->if_ipackets) { 2907 while(dc_rx_resync(sc)) 2908 dc_rxeof(sc); 2909 } 2910 } 2911 2912 if (status & (DC_ISR_TX_OK|DC_ISR_TX_NOBUF)) 2913 dc_txeof(sc); 2914 2915 if (status & DC_ISR_TX_IDLE) { 2916 dc_txeof(sc); 2917 if (sc->dc_cdata.dc_tx_cnt) { 2918 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_TX_ON); 2919 CSR_WRITE_4(sc, DC_TXSTART, 0xFFFFFFFF); 2920 } 2921 } 2922 2923 if (status & DC_ISR_TX_UNDERRUN) 2924 dc_tx_underrun(sc); 2925 2926 if ((status & DC_ISR_RX_WATDOGTIMEO) 2927 || (status & DC_ISR_RX_NOBUF)) { 2928 int curpkts; 2929 curpkts = ifp->if_ipackets; 2930 dc_rxeof(sc); 2931 if (curpkts == ifp->if_ipackets) { 2932 while(dc_rx_resync(sc)) 2933 dc_rxeof(sc); 2934 } 2935 } 2936 2937 if (status & DC_ISR_BUS_ERR) { 2938 dc_reset(sc); 2939 dc_init(sc); 2940 } 2941 } 2942 2943 /* Re-enable interrupts. */ 2944 CSR_WRITE_4(sc, DC_IMR, DC_INTRS); 2945 2946 if (ifp->if_snd.ifq_head != NULL) 2947 dc_start(ifp); 2948 2949 #ifdef DEVICE_POLLING 2950 done: 2951 #endif /* DEVICE_POLLING */ 2952 2953 DC_UNLOCK(sc); 2954 2955 return; 2956 } 2957 2958 /* 2959 * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data 2960 * pointers to the fragment pointers. 2961 */ 2962 static int dc_encap(sc, m_head, txidx) 2963 struct dc_softc *sc; 2964 struct mbuf *m_head; 2965 u_int32_t *txidx; 2966 { 2967 struct dc_desc *f = NULL; 2968 struct mbuf *m; 2969 int frag, cur, cnt = 0; 2970 2971 /* 2972 * Start packing the mbufs in this chain into 2973 * the fragment pointers. Stop when we run out 2974 * of fragments or hit the end of the mbuf chain. 2975 */ 2976 m = m_head; 2977 cur = frag = *txidx; 2978 2979 for (m = m_head; m != NULL; m = m->m_next) { 2980 if (m->m_len != 0) { 2981 if (sc->dc_flags & DC_TX_ADMTEK_WAR) { 2982 if (*txidx != sc->dc_cdata.dc_tx_prod && 2983 frag == (DC_TX_LIST_CNT - 1)) 2984 return(ENOBUFS); 2985 } 2986 if ((DC_TX_LIST_CNT - 2987 (sc->dc_cdata.dc_tx_cnt + cnt)) < 5) 2988 return(ENOBUFS); 2989 2990 f = &sc->dc_ldata->dc_tx_list[frag]; 2991 f->dc_ctl = DC_TXCTL_TLINK | m->m_len; 2992 if (cnt == 0) { 2993 f->dc_status = 0; 2994 f->dc_ctl |= DC_TXCTL_FIRSTFRAG; 2995 } else 2996 f->dc_status = DC_TXSTAT_OWN; 2997 f->dc_data = vtophys(mtod(m, vm_offset_t)); 2998 cur = frag; 2999 DC_INC(frag, DC_TX_LIST_CNT); 3000 cnt++; 3001 } 3002 } 3003 3004 if (m != NULL) 3005 return(ENOBUFS); 3006 3007 sc->dc_cdata.dc_tx_cnt += cnt; 3008 sc->dc_cdata.dc_tx_chain[cur] = m_head; 3009 sc->dc_ldata->dc_tx_list[cur].dc_ctl |= DC_TXCTL_LASTFRAG; 3010 if (sc->dc_flags & DC_TX_INTR_FIRSTFRAG) 3011 sc->dc_ldata->dc_tx_list[*txidx].dc_ctl |= DC_TXCTL_FINT; 3012 if (sc->dc_flags & DC_TX_INTR_ALWAYS) 3013 sc->dc_ldata->dc_tx_list[cur].dc_ctl |= DC_TXCTL_FINT; 3014 if (sc->dc_flags & DC_TX_USE_TX_INTR && sc->dc_cdata.dc_tx_cnt > 64) 3015 sc->dc_ldata->dc_tx_list[cur].dc_ctl |= DC_TXCTL_FINT; 3016 sc->dc_ldata->dc_tx_list[*txidx].dc_status = DC_TXSTAT_OWN; 3017 *txidx = frag; 3018 3019 return(0); 3020 } 3021 3022 /* 3023 * Coalesce an mbuf chain into a single mbuf cluster buffer. 3024 * Needed for some really badly behaved chips that just can't 3025 * do scatter/gather correctly. 3026 */ 3027 static int dc_coal(sc, m_head) 3028 struct dc_softc *sc; 3029 struct mbuf **m_head; 3030 { 3031 struct mbuf *m_new, *m; 3032 3033 m = *m_head; 3034 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 3035 if (m_new == NULL) 3036 return(ENOBUFS); 3037 if (m->m_pkthdr.len > MHLEN) { 3038 MCLGET(m_new, M_DONTWAIT); 3039 if (!(m_new->m_flags & M_EXT)) { 3040 m_freem(m_new); 3041 return(ENOBUFS); 3042 } 3043 } 3044 m_copydata(m, 0, m->m_pkthdr.len, mtod(m_new, caddr_t)); 3045 m_new->m_pkthdr.len = m_new->m_len = m->m_pkthdr.len; 3046 m_freem(m); 3047 *m_head = m_new; 3048 3049 return(0); 3050 } 3051 3052 /* 3053 * Main transmit routine. To avoid having to do mbuf copies, we put pointers 3054 * to the mbuf data regions directly in the transmit lists. We also save a 3055 * copy of the pointers since the transmit list fragment pointers are 3056 * physical addresses. 3057 */ 3058 3059 static void dc_start(ifp) 3060 struct ifnet *ifp; 3061 { 3062 struct dc_softc *sc; 3063 struct mbuf *m_head = NULL; 3064 int idx; 3065 3066 sc = ifp->if_softc; 3067 3068 DC_LOCK(sc); 3069 3070 if (!sc->dc_link && ifp->if_snd.ifq_len < 10) { 3071 DC_UNLOCK(sc); 3072 return; 3073 } 3074 3075 if (ifp->if_flags & IFF_OACTIVE) { 3076 DC_UNLOCK(sc); 3077 return; 3078 } 3079 3080 idx = sc->dc_cdata.dc_tx_prod; 3081 3082 while(sc->dc_cdata.dc_tx_chain[idx] == NULL) { 3083 IF_DEQUEUE(&ifp->if_snd, m_head); 3084 if (m_head == NULL) 3085 break; 3086 3087 if (sc->dc_flags & DC_TX_COALESCE && 3088 (m_head->m_next != NULL || 3089 sc->dc_flags & DC_TX_ALIGN)) { 3090 if (dc_coal(sc, &m_head)) { 3091 IF_PREPEND(&ifp->if_snd, m_head); 3092 ifp->if_flags |= IFF_OACTIVE; 3093 break; 3094 } 3095 } 3096 3097 if (dc_encap(sc, m_head, &idx)) { 3098 IF_PREPEND(&ifp->if_snd, m_head); 3099 ifp->if_flags |= IFF_OACTIVE; 3100 break; 3101 } 3102 3103 /* 3104 * If there's a BPF listener, bounce a copy of this frame 3105 * to him. 3106 */ 3107 if (ifp->if_bpf) 3108 bpf_mtap(ifp, m_head); 3109 3110 if (sc->dc_flags & DC_TX_ONE) { 3111 ifp->if_flags |= IFF_OACTIVE; 3112 break; 3113 } 3114 } 3115 3116 /* Transmit */ 3117 sc->dc_cdata.dc_tx_prod = idx; 3118 if (!(sc->dc_flags & DC_TX_POLL)) 3119 CSR_WRITE_4(sc, DC_TXSTART, 0xFFFFFFFF); 3120 3121 /* 3122 * Set a timeout in case the chip goes out to lunch. 3123 */ 3124 ifp->if_timer = 5; 3125 3126 DC_UNLOCK(sc); 3127 3128 return; 3129 } 3130 3131 static void dc_init(xsc) 3132 void *xsc; 3133 { 3134 struct dc_softc *sc = xsc; 3135 struct ifnet *ifp = &sc->arpcom.ac_if; 3136 struct mii_data *mii; 3137 3138 DC_LOCK(sc); 3139 3140 mii = device_get_softc(sc->dc_miibus); 3141 3142 /* 3143 * Cancel pending I/O and free all RX/TX buffers. 3144 */ 3145 dc_stop(sc); 3146 dc_reset(sc); 3147 3148 /* 3149 * Set cache alignment and burst length. 3150 */ 3151 if (DC_IS_ASIX(sc) || DC_IS_DAVICOM(sc)) 3152 CSR_WRITE_4(sc, DC_BUSCTL, 0); 3153 else 3154 CSR_WRITE_4(sc, DC_BUSCTL, DC_BUSCTL_MRME|DC_BUSCTL_MRLE); 3155 /* 3156 * Evenly share the bus between receive and transmit process. 3157 */ 3158 if (DC_IS_INTEL(sc)) 3159 DC_SETBIT(sc, DC_BUSCTL, DC_BUSCTL_ARBITRATION); 3160 if (DC_IS_DAVICOM(sc) || DC_IS_INTEL(sc)) { 3161 DC_SETBIT(sc, DC_BUSCTL, DC_BURSTLEN_USECA); 3162 } else { 3163 DC_SETBIT(sc, DC_BUSCTL, DC_BURSTLEN_16LONG); 3164 } 3165 if (sc->dc_flags & DC_TX_POLL) 3166 DC_SETBIT(sc, DC_BUSCTL, DC_TXPOLL_1); 3167 switch(sc->dc_cachesize) { 3168 case 32: 3169 DC_SETBIT(sc, DC_BUSCTL, DC_CACHEALIGN_32LONG); 3170 break; 3171 case 16: 3172 DC_SETBIT(sc, DC_BUSCTL, DC_CACHEALIGN_16LONG); 3173 break; 3174 case 8: 3175 DC_SETBIT(sc, DC_BUSCTL, DC_CACHEALIGN_8LONG); 3176 break; 3177 case 0: 3178 default: 3179 DC_SETBIT(sc, DC_BUSCTL, DC_CACHEALIGN_NONE); 3180 break; 3181 } 3182 3183 if (sc->dc_flags & DC_TX_STORENFWD) 3184 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_STORENFWD); 3185 else { 3186 if (sc->dc_txthresh > DC_TXTHRESH_MAX) { 3187 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_STORENFWD); 3188 } else { 3189 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_STORENFWD); 3190 DC_SETBIT(sc, DC_NETCFG, sc->dc_txthresh); 3191 } 3192 } 3193 3194 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_NO_RXCRC); 3195 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_TX_BACKOFF); 3196 3197 if (DC_IS_MACRONIX(sc) || DC_IS_PNICII(sc)) { 3198 /* 3199 * The app notes for the 98713 and 98715A say that 3200 * in order to have the chips operate properly, a magic 3201 * number must be written to CSR16. Macronix does not 3202 * document the meaning of these bits so there's no way 3203 * to know exactly what they do. The 98713 has a magic 3204 * number all its own; the rest all use a different one. 3205 */ 3206 DC_CLRBIT(sc, DC_MX_MAGICPACKET, 0xFFFF0000); 3207 if (sc->dc_type == DC_TYPE_98713) 3208 DC_SETBIT(sc, DC_MX_MAGICPACKET, DC_MX_MAGIC_98713); 3209 else 3210 DC_SETBIT(sc, DC_MX_MAGICPACKET, DC_MX_MAGIC_98715); 3211 } 3212 3213 if (DC_IS_XIRCOM(sc)) { 3214 /* 3215 * setup General Purpose Port mode and data so the tulip 3216 * can talk to the MII. 3217 */ 3218 CSR_WRITE_4(sc, DC_SIAGP, DC_SIAGP_WRITE_EN | DC_SIAGP_INT1_EN | 3219 DC_SIAGP_MD_GP2_OUTPUT | DC_SIAGP_MD_GP0_OUTPUT); 3220 DELAY(10); 3221 CSR_WRITE_4(sc, DC_SIAGP, DC_SIAGP_INT1_EN | 3222 DC_SIAGP_MD_GP2_OUTPUT | DC_SIAGP_MD_GP0_OUTPUT); 3223 DELAY(10); 3224 } 3225 3226 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_TX_THRESH); 3227 DC_SETBIT(sc, DC_NETCFG, DC_TXTHRESH_MIN); 3228 3229 /* Init circular RX list. */ 3230 if (dc_list_rx_init(sc) == ENOBUFS) { 3231 printf("dc%d: initialization failed: no " 3232 "memory for rx buffers\n", sc->dc_unit); 3233 dc_stop(sc); 3234 DC_UNLOCK(sc); 3235 return; 3236 } 3237 3238 /* 3239 * Init tx descriptors. 3240 */ 3241 dc_list_tx_init(sc); 3242 3243 /* 3244 * Load the address of the RX list. 3245 */ 3246 CSR_WRITE_4(sc, DC_RXADDR, vtophys(&sc->dc_ldata->dc_rx_list[0])); 3247 CSR_WRITE_4(sc, DC_TXADDR, vtophys(&sc->dc_ldata->dc_tx_list[0])); 3248 3249 /* 3250 * Enable interrupts. 3251 */ 3252 #ifdef DEVICE_POLLING 3253 /* 3254 * ... but only if we are not polling, and make sure they are off in 3255 * the case of polling. Some cards (e.g. fxp) turn interrupts on 3256 * after a reset. 3257 */ 3258 if (ifp->if_ipending & IFF_POLLING) 3259 CSR_WRITE_4(sc, DC_IMR, 0x00000000); 3260 else 3261 #endif 3262 CSR_WRITE_4(sc, DC_IMR, DC_INTRS); 3263 CSR_WRITE_4(sc, DC_ISR, 0xFFFFFFFF); 3264 3265 /* Enable transmitter. */ 3266 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_TX_ON); 3267 3268 /* 3269 * If this is an Intel 21143 and we're not using the 3270 * MII port, program the LED control pins so we get 3271 * link and activity indications. 3272 */ 3273 if (sc->dc_flags & DC_TULIP_LEDS) { 3274 CSR_WRITE_4(sc, DC_WATCHDOG, 3275 DC_WDOG_CTLWREN|DC_WDOG_LINK|DC_WDOG_ACTIVITY); 3276 CSR_WRITE_4(sc, DC_WATCHDOG, 0); 3277 } 3278 3279 /* 3280 * Load the RX/multicast filter. We do this sort of late 3281 * because the filter programming scheme on the 21143 and 3282 * some clones requires DMAing a setup frame via the TX 3283 * engine, and we need the transmitter enabled for that. 3284 */ 3285 dc_setfilt(sc); 3286 3287 /* Enable receiver. */ 3288 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_ON); 3289 CSR_WRITE_4(sc, DC_RXSTART, 0xFFFFFFFF); 3290 3291 mii_mediachg(mii); 3292 dc_setcfg(sc, sc->dc_if_media); 3293 3294 ifp->if_flags |= IFF_RUNNING; 3295 ifp->if_flags &= ~IFF_OACTIVE; 3296 3297 /* Don't start the ticker if this is a homePNA link. */ 3298 if (IFM_SUBTYPE(mii->mii_media.ifm_media) == IFM_homePNA) 3299 sc->dc_link = 1; 3300 else { 3301 if (sc->dc_flags & DC_21143_NWAY) 3302 callout_reset(&sc->dc_stat_ch, hz/10, dc_tick, sc); 3303 else 3304 callout_reset(&sc->dc_stat_ch, hz, dc_tick, sc); 3305 } 3306 3307 #ifdef SRM_MEDIA 3308 if(sc->dc_srm_media) { 3309 struct ifreq ifr; 3310 3311 ifr.ifr_media = sc->dc_srm_media; 3312 ifmedia_ioctl(ifp, &ifr, &mii->mii_media, SIOCSIFMEDIA); 3313 sc->dc_srm_media = 0; 3314 } 3315 #endif 3316 DC_UNLOCK(sc); 3317 return; 3318 } 3319 3320 /* 3321 * Set media options. 3322 */ 3323 static int dc_ifmedia_upd(ifp) 3324 struct ifnet *ifp; 3325 { 3326 struct dc_softc *sc; 3327 struct mii_data *mii; 3328 struct ifmedia *ifm; 3329 3330 sc = ifp->if_softc; 3331 mii = device_get_softc(sc->dc_miibus); 3332 mii_mediachg(mii); 3333 ifm = &mii->mii_media; 3334 3335 if (DC_IS_DAVICOM(sc) && 3336 IFM_SUBTYPE(ifm->ifm_media) == IFM_homePNA) 3337 dc_setcfg(sc, ifm->ifm_media); 3338 else 3339 sc->dc_link = 0; 3340 3341 return(0); 3342 } 3343 3344 /* 3345 * Report current media status. 3346 */ 3347 static void dc_ifmedia_sts(ifp, ifmr) 3348 struct ifnet *ifp; 3349 struct ifmediareq *ifmr; 3350 { 3351 struct dc_softc *sc; 3352 struct mii_data *mii; 3353 struct ifmedia *ifm; 3354 3355 sc = ifp->if_softc; 3356 mii = device_get_softc(sc->dc_miibus); 3357 mii_pollstat(mii); 3358 ifm = &mii->mii_media; 3359 if (DC_IS_DAVICOM(sc)) { 3360 if (IFM_SUBTYPE(ifm->ifm_media) == IFM_homePNA) { 3361 ifmr->ifm_active = ifm->ifm_media; 3362 ifmr->ifm_status = 0; 3363 return; 3364 } 3365 } 3366 ifmr->ifm_active = mii->mii_media_active; 3367 ifmr->ifm_status = mii->mii_media_status; 3368 3369 return; 3370 } 3371 3372 static int dc_ioctl(ifp, command, data) 3373 struct ifnet *ifp; 3374 u_long command; 3375 caddr_t data; 3376 { 3377 struct dc_softc *sc = ifp->if_softc; 3378 struct ifreq *ifr = (struct ifreq *) data; 3379 struct mii_data *mii; 3380 int error = 0; 3381 3382 DC_LOCK(sc); 3383 3384 switch(command) { 3385 case SIOCSIFADDR: 3386 case SIOCGIFADDR: 3387 case SIOCSIFMTU: 3388 error = ether_ioctl(ifp, command, data); 3389 break; 3390 case SIOCSIFFLAGS: 3391 if (ifp->if_flags & IFF_UP) { 3392 if (ifp->if_flags & IFF_RUNNING && 3393 ifp->if_flags & IFF_PROMISC && 3394 !(sc->dc_if_flags & IFF_PROMISC)) { 3395 dc_setfilt(sc); 3396 } else if (ifp->if_flags & IFF_RUNNING && 3397 !(ifp->if_flags & IFF_PROMISC) && 3398 sc->dc_if_flags & IFF_PROMISC) { 3399 dc_setfilt(sc); 3400 } else if (!(ifp->if_flags & IFF_RUNNING)) { 3401 sc->dc_txthresh = 0; 3402 dc_init(sc); 3403 } 3404 } else { 3405 if (ifp->if_flags & IFF_RUNNING) 3406 dc_stop(sc); 3407 } 3408 sc->dc_if_flags = ifp->if_flags; 3409 error = 0; 3410 break; 3411 case SIOCADDMULTI: 3412 case SIOCDELMULTI: 3413 dc_setfilt(sc); 3414 error = 0; 3415 break; 3416 case SIOCGIFMEDIA: 3417 case SIOCSIFMEDIA: 3418 mii = device_get_softc(sc->dc_miibus); 3419 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 3420 #ifdef SRM_MEDIA 3421 if (sc->dc_srm_media) 3422 sc->dc_srm_media = 0; 3423 #endif 3424 break; 3425 default: 3426 error = EINVAL; 3427 break; 3428 } 3429 3430 DC_UNLOCK(sc); 3431 3432 return(error); 3433 } 3434 3435 static void dc_watchdog(ifp) 3436 struct ifnet *ifp; 3437 { 3438 struct dc_softc *sc; 3439 3440 sc = ifp->if_softc; 3441 3442 DC_LOCK(sc); 3443 3444 ifp->if_oerrors++; 3445 printf("dc%d: watchdog timeout\n", sc->dc_unit); 3446 3447 dc_stop(sc); 3448 dc_reset(sc); 3449 dc_init(sc); 3450 3451 if (ifp->if_snd.ifq_head != NULL) 3452 dc_start(ifp); 3453 3454 DC_UNLOCK(sc); 3455 3456 return; 3457 } 3458 3459 /* 3460 * Stop the adapter and free any mbufs allocated to the 3461 * RX and TX lists. 3462 */ 3463 static void dc_stop(sc) 3464 struct dc_softc *sc; 3465 { 3466 register int i; 3467 struct ifnet *ifp; 3468 3469 DC_LOCK(sc); 3470 3471 ifp = &sc->arpcom.ac_if; 3472 ifp->if_timer = 0; 3473 3474 callout_stop(&sc->dc_stat_ch); 3475 3476 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 3477 #ifdef DEVICE_POLLING 3478 ether_poll_deregister(ifp); 3479 #endif 3480 3481 DC_CLRBIT(sc, DC_NETCFG, (DC_NETCFG_RX_ON|DC_NETCFG_TX_ON)); 3482 CSR_WRITE_4(sc, DC_IMR, 0x00000000); 3483 CSR_WRITE_4(sc, DC_TXADDR, 0x00000000); 3484 CSR_WRITE_4(sc, DC_RXADDR, 0x00000000); 3485 sc->dc_link = 0; 3486 3487 /* 3488 * Free data in the RX lists. 3489 */ 3490 for (i = 0; i < DC_RX_LIST_CNT; i++) { 3491 if (sc->dc_cdata.dc_rx_chain[i] != NULL) { 3492 m_freem(sc->dc_cdata.dc_rx_chain[i]); 3493 sc->dc_cdata.dc_rx_chain[i] = NULL; 3494 } 3495 } 3496 bzero((char *)&sc->dc_ldata->dc_rx_list, 3497 sizeof(sc->dc_ldata->dc_rx_list)); 3498 3499 /* 3500 * Free the TX list buffers. 3501 */ 3502 for (i = 0; i < DC_TX_LIST_CNT; i++) { 3503 if (sc->dc_cdata.dc_tx_chain[i] != NULL) { 3504 if (sc->dc_ldata->dc_tx_list[i].dc_ctl & 3505 DC_TXCTL_SETUP) { 3506 sc->dc_cdata.dc_tx_chain[i] = NULL; 3507 continue; 3508 } 3509 m_freem(sc->dc_cdata.dc_tx_chain[i]); 3510 sc->dc_cdata.dc_tx_chain[i] = NULL; 3511 } 3512 } 3513 3514 bzero((char *)&sc->dc_ldata->dc_tx_list, 3515 sizeof(sc->dc_ldata->dc_tx_list)); 3516 3517 DC_UNLOCK(sc); 3518 3519 return; 3520 } 3521 3522 /* 3523 * Stop all chip I/O so that the kernel's probe routines don't 3524 * get confused by errant DMAs when rebooting. 3525 */ 3526 static void dc_shutdown(dev) 3527 device_t dev; 3528 { 3529 struct dc_softc *sc; 3530 3531 sc = device_get_softc(dev); 3532 3533 dc_stop(sc); 3534 3535 return; 3536 } 3537