1 /* 2 * Copyright (c) 1997, 1998, 1999 3 * Bill Paul <wpaul@ee.columbia.edu>. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 3. All advertising materials mentioning features or use of this software 14 * must display the following acknowledgement: 15 * This product includes software developed by Bill Paul. 16 * 4. Neither the name of the author nor the names of any co-contributors 17 * may be used to endorse or promote products derived from this software 18 * without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30 * THE POSSIBILITY OF SUCH DAMAGE. 31 * 32 * $FreeBSD$ 33 */ 34 35 /* 36 * DEC "tulip" clone ethernet driver. Supports the DEC/Intel 21143 37 * series chips and several workalikes including the following: 38 * 39 * Macronix 98713/98715/98725/98727/98732 PMAC (www.macronix.com) 40 * Macronix/Lite-On 82c115 PNIC II (www.macronix.com) 41 * Lite-On 82c168/82c169 PNIC (www.litecom.com) 42 * ASIX Electronics AX88140A (www.asix.com.tw) 43 * ASIX Electronics AX88141 (www.asix.com.tw) 44 * ADMtek AL981 (www.admtek.com.tw) 45 * ADMtek AN985 (www.admtek.com.tw) 46 * Davicom DM9100, DM9102, DM9102A (www.davicom8.com) 47 * Accton EN1217 (www.accton.com) 48 * 49 * Datasheets for the 21143 are available at developer.intel.com. 50 * Datasheets for the clone parts can be found at their respective sites. 51 * (Except for the PNIC; see www.freebsd.org/~wpaul/PNIC/pnic.ps.gz.) 52 * The PNIC II is essentially a Macronix 98715A chip; the only difference 53 * worth noting is that its multicast hash table is only 128 bits wide 54 * instead of 512. 55 * 56 * Written by Bill Paul <wpaul@ee.columbia.edu> 57 * Electrical Engineering Department 58 * Columbia University, New York City 59 */ 60 61 /* 62 * The Intel 21143 is the successor to the DEC 21140. It is basically 63 * the same as the 21140 but with a few new features. The 21143 supports 64 * three kinds of media attachments: 65 * 66 * o MII port, for 10Mbps and 100Mbps support and NWAY 67 * autonegotiation provided by an external PHY. 68 * o SYM port, for symbol mode 100Mbps support. 69 * o 10baseT port. 70 * o AUI/BNC port. 71 * 72 * The 100Mbps SYM port and 10baseT port can be used together in 73 * combination with the internal NWAY support to create a 10/100 74 * autosensing configuration. 75 * 76 * Knowing which media is available on a given card is tough: you're 77 * supposed to go slogging through the EEPROM looking for media 78 * description structures. Unfortunately, some card vendors that use 79 * the 21143 don't obey the DEC SROM spec correctly, which means that 80 * what you find in the EEPROM may not agree with reality. Fortunately, 81 * the 21143 provides us a way to get around this issue: lurking in 82 * PCI configuration space is the Configuration Wake-Up Command Register. 83 * This register is loaded with a value from the EEPROM when wake on LAN 84 * mode is enabled; this value tells us quite clearly what kind of media 85 * is attached to the NIC. The main purpose of this register is to tell 86 * the NIC what media to scan when in wake on LAN mode, however by 87 * forcibly enabling wake on LAN mode, we can use to learn what kind of 88 * media a given NIC has available and adapt ourselves accordingly. 89 * 90 * Of course, if the media description blocks in the EEPROM are bogus. 91 * what are the odds that the CWUC aren't bogus as well, right? Well, 92 * the CWUC value is more likely to be correct since wake on LAN mode 93 * won't work correctly without it, and wake on LAN is a big selling 94 * point these days. It's also harder to screw up a single byte than 95 * a whole media descriptor block. 96 * 97 * Note that not all tulip workalikes are handled in this driver: we only 98 * deal with those which are relatively well behaved. The Winbond is 99 * handled separately due to its different register offsets and the 100 * special handling needed for its various bugs. The PNIC is handled 101 * here, but I'm not thrilled about it. 102 * 103 * All of the workalike chips use some form of MII transceiver support 104 * with the exception of the Macronix chips, which also have a SYM port. 105 * The ASIX AX88140A is also documented to have a SYM port, but all 106 * the cards I've seen use an MII transceiver, probably because the 107 * AX88140A doesn't support internal NWAY. 108 */ 109 110 #include <sys/param.h> 111 #include <sys/systm.h> 112 #include <sys/sockio.h> 113 #include <sys/mbuf.h> 114 #include <sys/malloc.h> 115 #include <sys/kernel.h> 116 #include <sys/socket.h> 117 118 #include <net/if.h> 119 #include <net/if_arp.h> 120 #include <net/ethernet.h> 121 #include <net/if_dl.h> 122 #include <net/if_media.h> 123 124 #include <net/bpf.h> 125 126 #include <vm/vm.h> /* for vtophys */ 127 #include <vm/pmap.h> /* for vtophys */ 128 #include <machine/clock.h> /* for DELAY */ 129 #include <machine/bus_pio.h> 130 #include <machine/bus_memio.h> 131 #include <machine/bus.h> 132 #include <machine/resource.h> 133 #include <sys/bus.h> 134 #include <sys/rman.h> 135 136 #include <dev/mii/mii.h> 137 #include <dev/mii/miivar.h> 138 139 #include <pci/pcireg.h> 140 #include <pci/pcivar.h> 141 142 #define DC_USEIOSPACE 143 144 #include <pci/if_dcreg.h> 145 146 MODULE_DEPEND(dc, miibus, 1, 1, 1); 147 148 /* "controller miibus0" required. See GENERIC if you get errors here. */ 149 #include "miibus_if.h" 150 151 #ifndef lint 152 static const char rcsid[] = 153 "$FreeBSD$"; 154 #endif 155 156 /* 157 * Various supported device vendors/types and their names. 158 */ 159 static struct dc_type dc_devs[] = { 160 { DC_VENDORID_DEC, DC_DEVICEID_21143, 161 "Intel 21143 10/100BaseTX" }, 162 { DC_VENDORID_DAVICOM, DC_DEVICEID_DM9100, 163 "Davicom DM9100 10/100BaseTX" }, 164 { DC_VENDORID_DAVICOM, DC_DEVICEID_DM9102, 165 "Davicom DM9102 10/100BaseTX" }, 166 { DC_VENDORID_DAVICOM, DC_DEVICEID_DM9102, 167 "Davicom DM9102A 10/100BaseTX" }, 168 { DC_VENDORID_ADMTEK, DC_DEVICEID_AL981, 169 "ADMtek AL981 10/100BaseTX" }, 170 { DC_VENDORID_ADMTEK, DC_DEVICEID_AN985, 171 "ADMtek AN985 10/100BaseTX" }, 172 { DC_VENDORID_ASIX, DC_DEVICEID_AX88140A, 173 "ASIX AX88140A 10/100BaseTX" }, 174 { DC_VENDORID_ASIX, DC_DEVICEID_AX88140A, 175 "ASIX AX88141 10/100BaseTX" }, 176 { DC_VENDORID_MX, DC_DEVICEID_98713, 177 "Macronix 98713 10/100BaseTX" }, 178 { DC_VENDORID_MX, DC_DEVICEID_98713, 179 "Macronix 98713A 10/100BaseTX" }, 180 { DC_VENDORID_CP, DC_DEVICEID_98713_CP, 181 "Compex RL100-TX 10/100BaseTX" }, 182 { DC_VENDORID_CP, DC_DEVICEID_98713_CP, 183 "Compex RL100-TX 10/100BaseTX" }, 184 { DC_VENDORID_MX, DC_DEVICEID_987x5, 185 "Macronix 98715/98715A 10/100BaseTX" }, 186 { DC_VENDORID_MX, DC_DEVICEID_987x5, 187 "Macronix 98715AEC-C 10/100BaseTX" }, 188 { DC_VENDORID_MX, DC_DEVICEID_987x5, 189 "Macronix 98725 10/100BaseTX" }, 190 { DC_VENDORID_MX, DC_DEVICEID_98727, 191 "Macronix 98727/98732 10/100BaseTX" }, 192 { DC_VENDORID_LO, DC_DEVICEID_82C115, 193 "LC82C115 PNIC II 10/100BaseTX" }, 194 { DC_VENDORID_LO, DC_DEVICEID_82C168, 195 "82c168 PNIC 10/100BaseTX" }, 196 { DC_VENDORID_LO, DC_DEVICEID_82C168, 197 "82c169 PNIC 10/100BaseTX" }, 198 { DC_VENDORID_ACCTON, DC_DEVICEID_EN1217, 199 "Accton EN1217 10/100BaseTX" }, 200 { 0, 0, NULL } 201 }; 202 203 static int dc_probe __P((device_t)); 204 static int dc_attach __P((device_t)); 205 static int dc_detach __P((device_t)); 206 static void dc_acpi __P((device_t)); 207 static struct dc_type *dc_devtype __P((device_t)); 208 static int dc_newbuf __P((struct dc_softc *, int, struct mbuf *)); 209 static int dc_encap __P((struct dc_softc *, struct mbuf *, 210 u_int32_t *)); 211 static int dc_coal __P((struct dc_softc *, struct mbuf **)); 212 static void dc_pnic_rx_bug_war __P((struct dc_softc *, int)); 213 static int dc_rx_resync __P((struct dc_softc *)); 214 static void dc_rxeof __P((struct dc_softc *)); 215 static void dc_txeof __P((struct dc_softc *)); 216 static void dc_tick __P((void *)); 217 static void dc_intr __P((void *)); 218 static void dc_start __P((struct ifnet *)); 219 static int dc_ioctl __P((struct ifnet *, u_long, caddr_t)); 220 static void dc_init __P((void *)); 221 static void dc_stop __P((struct dc_softc *)); 222 static void dc_watchdog __P((struct ifnet *)); 223 static void dc_shutdown __P((device_t)); 224 static int dc_ifmedia_upd __P((struct ifnet *)); 225 static void dc_ifmedia_sts __P((struct ifnet *, struct ifmediareq *)); 226 227 static void dc_delay __P((struct dc_softc *)); 228 static void dc_eeprom_idle __P((struct dc_softc *)); 229 static void dc_eeprom_putbyte __P((struct dc_softc *, int)); 230 static void dc_eeprom_getword __P((struct dc_softc *, int, u_int16_t *)); 231 static void dc_eeprom_getword_pnic 232 __P((struct dc_softc *, int, u_int16_t *)); 233 static void dc_read_eeprom __P((struct dc_softc *, caddr_t, int, 234 int, int)); 235 236 static void dc_mii_writebit __P((struct dc_softc *, int)); 237 static int dc_mii_readbit __P((struct dc_softc *)); 238 static void dc_mii_sync __P((struct dc_softc *)); 239 static void dc_mii_send __P((struct dc_softc *, u_int32_t, int)); 240 static int dc_mii_readreg __P((struct dc_softc *, struct dc_mii_frame *)); 241 static int dc_mii_writereg __P((struct dc_softc *, struct dc_mii_frame *)); 242 static int dc_miibus_readreg __P((device_t, int, int)); 243 static int dc_miibus_writereg __P((device_t, int, int, int)); 244 static void dc_miibus_statchg __P((device_t)); 245 static void dc_miibus_mediainit __P((device_t)); 246 247 static void dc_setcfg __P((struct dc_softc *, int)); 248 static u_int32_t dc_crc_le __P((struct dc_softc *, caddr_t)); 249 static u_int32_t dc_crc_be __P((caddr_t)); 250 static void dc_setfilt_21143 __P((struct dc_softc *)); 251 static void dc_setfilt_asix __P((struct dc_softc *)); 252 static void dc_setfilt_admtek __P((struct dc_softc *)); 253 254 static void dc_setfilt __P((struct dc_softc *)); 255 256 static void dc_reset __P((struct dc_softc *)); 257 static int dc_list_rx_init __P((struct dc_softc *)); 258 static int dc_list_tx_init __P((struct dc_softc *)); 259 260 #ifdef DC_USEIOSPACE 261 #define DC_RES SYS_RES_IOPORT 262 #define DC_RID DC_PCI_CFBIO 263 #else 264 #define DC_RES SYS_RES_MEMORY 265 #define DC_RID DC_PCI_CFBMA 266 #endif 267 268 static device_method_t dc_methods[] = { 269 /* Device interface */ 270 DEVMETHOD(device_probe, dc_probe), 271 DEVMETHOD(device_attach, dc_attach), 272 DEVMETHOD(device_detach, dc_detach), 273 DEVMETHOD(device_shutdown, dc_shutdown), 274 275 /* bus interface */ 276 DEVMETHOD(bus_print_child, bus_generic_print_child), 277 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 278 279 /* MII interface */ 280 DEVMETHOD(miibus_readreg, dc_miibus_readreg), 281 DEVMETHOD(miibus_writereg, dc_miibus_writereg), 282 DEVMETHOD(miibus_statchg, dc_miibus_statchg), 283 DEVMETHOD(miibus_mediainit, dc_miibus_mediainit), 284 285 { 0, 0 } 286 }; 287 288 static driver_t dc_driver = { 289 "dc", 290 dc_methods, 291 sizeof(struct dc_softc) 292 }; 293 294 static devclass_t dc_devclass; 295 296 DRIVER_MODULE(if_dc, pci, dc_driver, dc_devclass, 0, 0); 297 DRIVER_MODULE(miibus, dc, miibus_driver, miibus_devclass, 0, 0); 298 299 #define DC_SETBIT(sc, reg, x) \ 300 CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) | (x)) 301 302 #define DC_CLRBIT(sc, reg, x) \ 303 CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) & ~(x)) 304 305 #define SIO_SET(x) DC_SETBIT(sc, DC_SIO, (x)) 306 #define SIO_CLR(x) DC_CLRBIT(sc, DC_SIO, (x)) 307 308 static void dc_delay(sc) 309 struct dc_softc *sc; 310 { 311 int idx; 312 313 for (idx = (300 / 33) + 1; idx > 0; idx--) 314 CSR_READ_4(sc, DC_BUSCTL); 315 } 316 317 static void dc_eeprom_idle(sc) 318 struct dc_softc *sc; 319 { 320 register int i; 321 322 CSR_WRITE_4(sc, DC_SIO, DC_SIO_EESEL); 323 dc_delay(sc); 324 DC_SETBIT(sc, DC_SIO, DC_SIO_ROMCTL_READ); 325 dc_delay(sc); 326 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); 327 dc_delay(sc); 328 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CS); 329 dc_delay(sc); 330 331 for (i = 0; i < 25; i++) { 332 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); 333 dc_delay(sc); 334 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CLK); 335 dc_delay(sc); 336 } 337 338 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); 339 dc_delay(sc); 340 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CS); 341 dc_delay(sc); 342 CSR_WRITE_4(sc, DC_SIO, 0x00000000); 343 344 return; 345 } 346 347 /* 348 * Send a read command and address to the EEPROM, check for ACK. 349 */ 350 static void dc_eeprom_putbyte(sc, addr) 351 struct dc_softc *sc; 352 int addr; 353 { 354 register int d, i; 355 356 /* 357 * The AN985 has a 93C66 EEPROM on it instead of 358 * a 93C46. It uses a different bit sequence for 359 * specifying the "read" opcode. 360 */ 361 if (DC_IS_CENTAUR(sc)) 362 d = addr | (DC_EECMD_READ << 2); 363 else 364 d = addr | DC_EECMD_READ; 365 366 /* 367 * Feed in each bit and strobe the clock. 368 */ 369 for (i = 0x400; i; i >>= 1) { 370 if (d & i) { 371 SIO_SET(DC_SIO_EE_DATAIN); 372 } else { 373 SIO_CLR(DC_SIO_EE_DATAIN); 374 } 375 dc_delay(sc); 376 SIO_SET(DC_SIO_EE_CLK); 377 dc_delay(sc); 378 SIO_CLR(DC_SIO_EE_CLK); 379 dc_delay(sc); 380 } 381 382 return; 383 } 384 385 /* 386 * Read a word of data stored in the EEPROM at address 'addr.' 387 * The PNIC 82c168/82c169 has its own non-standard way to read 388 * the EEPROM. 389 */ 390 static void dc_eeprom_getword_pnic(sc, addr, dest) 391 struct dc_softc *sc; 392 int addr; 393 u_int16_t *dest; 394 { 395 register int i; 396 u_int32_t r; 397 398 CSR_WRITE_4(sc, DC_PN_SIOCTL, DC_PN_EEOPCODE_READ|addr); 399 400 for (i = 0; i < DC_TIMEOUT; i++) { 401 DELAY(1); 402 r = CSR_READ_4(sc, DC_SIO); 403 if (!(r & DC_PN_SIOCTL_BUSY)) { 404 *dest = (u_int16_t)(r & 0xFFFF); 405 return; 406 } 407 } 408 409 return; 410 } 411 412 /* 413 * Read a word of data stored in the EEPROM at address 'addr.' 414 */ 415 static void dc_eeprom_getword(sc, addr, dest) 416 struct dc_softc *sc; 417 int addr; 418 u_int16_t *dest; 419 { 420 register int i; 421 u_int16_t word = 0; 422 423 /* Force EEPROM to idle state. */ 424 dc_eeprom_idle(sc); 425 426 /* Enter EEPROM access mode. */ 427 CSR_WRITE_4(sc, DC_SIO, DC_SIO_EESEL); 428 dc_delay(sc); 429 DC_SETBIT(sc, DC_SIO, DC_SIO_ROMCTL_READ); 430 dc_delay(sc); 431 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); 432 dc_delay(sc); 433 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CS); 434 dc_delay(sc); 435 436 /* 437 * Send address of word we want to read. 438 */ 439 dc_eeprom_putbyte(sc, addr); 440 441 /* 442 * Start reading bits from EEPROM. 443 */ 444 for (i = 0x8000; i; i >>= 1) { 445 SIO_SET(DC_SIO_EE_CLK); 446 dc_delay(sc); 447 if (CSR_READ_4(sc, DC_SIO) & DC_SIO_EE_DATAOUT) 448 word |= i; 449 dc_delay(sc); 450 SIO_CLR(DC_SIO_EE_CLK); 451 dc_delay(sc); 452 } 453 454 /* Turn off EEPROM access mode. */ 455 dc_eeprom_idle(sc); 456 457 *dest = word; 458 459 return; 460 } 461 462 /* 463 * Read a sequence of words from the EEPROM. 464 */ 465 static void dc_read_eeprom(sc, dest, off, cnt, swap) 466 struct dc_softc *sc; 467 caddr_t dest; 468 int off; 469 int cnt; 470 int swap; 471 { 472 int i; 473 u_int16_t word = 0, *ptr; 474 475 for (i = 0; i < cnt; i++) { 476 if (DC_IS_PNIC(sc)) 477 dc_eeprom_getword_pnic(sc, off + i, &word); 478 else 479 dc_eeprom_getword(sc, off + i, &word); 480 ptr = (u_int16_t *)(dest + (i * 2)); 481 if (swap) 482 *ptr = ntohs(word); 483 else 484 *ptr = word; 485 } 486 487 return; 488 } 489 490 /* 491 * The following two routines are taken from the Macronix 98713 492 * Application Notes pp.19-21. 493 */ 494 /* 495 * Write a bit to the MII bus. 496 */ 497 static void dc_mii_writebit(sc, bit) 498 struct dc_softc *sc; 499 int bit; 500 { 501 if (bit) 502 CSR_WRITE_4(sc, DC_SIO, 503 DC_SIO_ROMCTL_WRITE|DC_SIO_MII_DATAOUT); 504 else 505 CSR_WRITE_4(sc, DC_SIO, DC_SIO_ROMCTL_WRITE); 506 507 DC_SETBIT(sc, DC_SIO, DC_SIO_MII_CLK); 508 DC_CLRBIT(sc, DC_SIO, DC_SIO_MII_CLK); 509 510 return; 511 } 512 513 /* 514 * Read a bit from the MII bus. 515 */ 516 static int dc_mii_readbit(sc) 517 struct dc_softc *sc; 518 { 519 CSR_WRITE_4(sc, DC_SIO, DC_SIO_ROMCTL_READ|DC_SIO_MII_DIR); 520 CSR_READ_4(sc, DC_SIO); 521 DC_SETBIT(sc, DC_SIO, DC_SIO_MII_CLK); 522 DC_CLRBIT(sc, DC_SIO, DC_SIO_MII_CLK); 523 if (CSR_READ_4(sc, DC_SIO) & DC_SIO_MII_DATAIN) 524 return(1); 525 526 return(0); 527 } 528 529 /* 530 * Sync the PHYs by setting data bit and strobing the clock 32 times. 531 */ 532 static void dc_mii_sync(sc) 533 struct dc_softc *sc; 534 { 535 register int i; 536 537 CSR_WRITE_4(sc, DC_SIO, DC_SIO_ROMCTL_WRITE); 538 539 for (i = 0; i < 32; i++) 540 dc_mii_writebit(sc, 1); 541 542 return; 543 } 544 545 /* 546 * Clock a series of bits through the MII. 547 */ 548 static void dc_mii_send(sc, bits, cnt) 549 struct dc_softc *sc; 550 u_int32_t bits; 551 int cnt; 552 { 553 int i; 554 555 for (i = (0x1 << (cnt - 1)); i; i >>= 1) 556 dc_mii_writebit(sc, bits & i); 557 } 558 559 /* 560 * Read an PHY register through the MII. 561 */ 562 static int dc_mii_readreg(sc, frame) 563 struct dc_softc *sc; 564 struct dc_mii_frame *frame; 565 566 { 567 int i, ack, s; 568 569 s = splimp(); 570 571 /* 572 * Set up frame for RX. 573 */ 574 frame->mii_stdelim = DC_MII_STARTDELIM; 575 frame->mii_opcode = DC_MII_READOP; 576 frame->mii_turnaround = 0; 577 frame->mii_data = 0; 578 579 /* 580 * Sync the PHYs. 581 */ 582 dc_mii_sync(sc); 583 584 /* 585 * Send command/address info. 586 */ 587 dc_mii_send(sc, frame->mii_stdelim, 2); 588 dc_mii_send(sc, frame->mii_opcode, 2); 589 dc_mii_send(sc, frame->mii_phyaddr, 5); 590 dc_mii_send(sc, frame->mii_regaddr, 5); 591 592 #ifdef notdef 593 /* Idle bit */ 594 dc_mii_writebit(sc, 1); 595 dc_mii_writebit(sc, 0); 596 #endif 597 598 /* Check for ack */ 599 ack = dc_mii_readbit(sc); 600 601 /* 602 * Now try reading data bits. If the ack failed, we still 603 * need to clock through 16 cycles to keep the PHY(s) in sync. 604 */ 605 if (ack) { 606 for(i = 0; i < 16; i++) { 607 dc_mii_readbit(sc); 608 } 609 goto fail; 610 } 611 612 for (i = 0x8000; i; i >>= 1) { 613 if (!ack) { 614 if (dc_mii_readbit(sc)) 615 frame->mii_data |= i; 616 } 617 } 618 619 fail: 620 621 dc_mii_writebit(sc, 0); 622 dc_mii_writebit(sc, 0); 623 624 splx(s); 625 626 if (ack) 627 return(1); 628 return(0); 629 } 630 631 /* 632 * Write to a PHY register through the MII. 633 */ 634 static int dc_mii_writereg(sc, frame) 635 struct dc_softc *sc; 636 struct dc_mii_frame *frame; 637 638 { 639 int s; 640 641 s = splimp(); 642 /* 643 * Set up frame for TX. 644 */ 645 646 frame->mii_stdelim = DC_MII_STARTDELIM; 647 frame->mii_opcode = DC_MII_WRITEOP; 648 frame->mii_turnaround = DC_MII_TURNAROUND; 649 650 /* 651 * Sync the PHYs. 652 */ 653 dc_mii_sync(sc); 654 655 dc_mii_send(sc, frame->mii_stdelim, 2); 656 dc_mii_send(sc, frame->mii_opcode, 2); 657 dc_mii_send(sc, frame->mii_phyaddr, 5); 658 dc_mii_send(sc, frame->mii_regaddr, 5); 659 dc_mii_send(sc, frame->mii_turnaround, 2); 660 dc_mii_send(sc, frame->mii_data, 16); 661 662 /* Idle bit. */ 663 dc_mii_writebit(sc, 0); 664 dc_mii_writebit(sc, 0); 665 666 splx(s); 667 668 return(0); 669 } 670 671 static int dc_miibus_readreg(dev, phy, reg) 672 device_t dev; 673 int phy, reg; 674 { 675 struct dc_mii_frame frame; 676 struct dc_softc *sc; 677 int i, rval, phy_reg; 678 679 sc = device_get_softc(dev); 680 bzero((char *)&frame, sizeof(frame)); 681 682 /* 683 * Note: both the AL981 and AN985 have internal PHYs, 684 * however the AL981 provides direct access to the PHY 685 * registers while the AN985 uses a serial MII interface. 686 * The AN985's MII interface is also buggy in that you 687 * can read from any MII address (0 to 31), but only address 1 688 * behaves normally. To deal with both cases, we pretend 689 * that the PHY is at MII address 1. 690 */ 691 if (DC_IS_ADMTEK(sc) && phy != DC_ADMTEK_PHYADDR) 692 return(0); 693 694 if (sc->dc_pmode == DC_PMODE_SYM) { 695 if (phy == (MII_NPHY - 1)) { 696 switch(reg) { 697 case MII_BMSR: 698 /* 699 * Fake something to make the probe 700 * code think there's a PHY here. 701 */ 702 return(BMSR_MEDIAMASK); 703 break; 704 case MII_PHYIDR1: 705 if (DC_IS_PNIC(sc)) 706 return(DC_VENDORID_LO); 707 return(DC_VENDORID_DEC); 708 break; 709 case MII_PHYIDR2: 710 if (DC_IS_PNIC(sc)) 711 return(DC_DEVICEID_82C168); 712 return(DC_DEVICEID_21143); 713 break; 714 default: 715 return(0); 716 break; 717 } 718 } else 719 return(0); 720 } 721 722 if (DC_IS_PNIC(sc)) { 723 CSR_WRITE_4(sc, DC_PN_MII, DC_PN_MIIOPCODE_READ | 724 (phy << 23) | (reg << 18)); 725 for (i = 0; i < DC_TIMEOUT; i++) { 726 DELAY(1); 727 rval = CSR_READ_4(sc, DC_PN_MII); 728 if (!(rval & DC_PN_MII_BUSY)) { 729 rval &= 0xFFFF; 730 return(rval == 0xFFFF ? 0 : rval); 731 } 732 } 733 return(0); 734 } 735 736 if (DC_IS_COMET(sc)) { 737 switch(reg) { 738 case MII_BMCR: 739 phy_reg = DC_AL_BMCR; 740 break; 741 case MII_BMSR: 742 phy_reg = DC_AL_BMSR; 743 break; 744 case MII_PHYIDR1: 745 phy_reg = DC_AL_VENID; 746 break; 747 case MII_PHYIDR2: 748 phy_reg = DC_AL_DEVID; 749 break; 750 case MII_ANAR: 751 phy_reg = DC_AL_ANAR; 752 break; 753 case MII_ANLPAR: 754 phy_reg = DC_AL_LPAR; 755 break; 756 case MII_ANER: 757 phy_reg = DC_AL_ANER; 758 break; 759 default: 760 printf("dc%d: phy_read: bad phy register %x\n", 761 sc->dc_unit, reg); 762 return(0); 763 break; 764 } 765 766 rval = CSR_READ_4(sc, phy_reg) & 0x0000FFFF; 767 768 if (rval == 0xFFFF) 769 return(0); 770 return(rval); 771 } 772 773 frame.mii_phyaddr = phy; 774 frame.mii_regaddr = reg; 775 phy_reg = CSR_READ_4(sc, DC_NETCFG); 776 CSR_WRITE_4(sc, DC_NETCFG, phy_reg & ~DC_NETCFG_PORTSEL); 777 dc_mii_readreg(sc, &frame); 778 CSR_WRITE_4(sc, DC_NETCFG, phy_reg); 779 780 return(frame.mii_data); 781 } 782 783 static int dc_miibus_writereg(dev, phy, reg, data) 784 device_t dev; 785 int phy, reg, data; 786 { 787 struct dc_softc *sc; 788 struct dc_mii_frame frame; 789 int i, phy_reg; 790 791 sc = device_get_softc(dev); 792 bzero((char *)&frame, sizeof(frame)); 793 794 if (DC_IS_ADMTEK(sc) && phy != DC_ADMTEK_PHYADDR) 795 return(0); 796 797 if (DC_IS_PNIC(sc)) { 798 CSR_WRITE_4(sc, DC_PN_MII, DC_PN_MIIOPCODE_WRITE | 799 (phy << 23) | (reg << 10) | data); 800 for (i = 0; i < DC_TIMEOUT; i++) { 801 if (!(CSR_READ_4(sc, DC_PN_MII) & DC_PN_MII_BUSY)) 802 break; 803 } 804 return(0); 805 } 806 807 if (DC_IS_COMET(sc)) { 808 switch(reg) { 809 case MII_BMCR: 810 phy_reg = DC_AL_BMCR; 811 break; 812 case MII_BMSR: 813 phy_reg = DC_AL_BMSR; 814 break; 815 case MII_PHYIDR1: 816 phy_reg = DC_AL_VENID; 817 break; 818 case MII_PHYIDR2: 819 phy_reg = DC_AL_DEVID; 820 break; 821 case MII_ANAR: 822 phy_reg = DC_AL_ANAR; 823 break; 824 case MII_ANLPAR: 825 phy_reg = DC_AL_LPAR; 826 break; 827 case MII_ANER: 828 phy_reg = DC_AL_ANER; 829 break; 830 default: 831 printf("dc%d: phy_write: bad phy register %x\n", 832 sc->dc_unit, reg); 833 return(0); 834 break; 835 } 836 837 CSR_WRITE_4(sc, phy_reg, data); 838 return(0); 839 } 840 841 frame.mii_phyaddr = phy; 842 frame.mii_regaddr = reg; 843 frame.mii_data = data; 844 845 phy_reg = CSR_READ_4(sc, DC_NETCFG); 846 CSR_WRITE_4(sc, DC_NETCFG, phy_reg & ~DC_NETCFG_PORTSEL); 847 dc_mii_writereg(sc, &frame); 848 CSR_WRITE_4(sc, DC_NETCFG, phy_reg); 849 850 return(0); 851 } 852 853 static void dc_miibus_statchg(dev) 854 device_t dev; 855 { 856 struct dc_softc *sc; 857 struct mii_data *mii; 858 struct ifmedia *ifm; 859 860 sc = device_get_softc(dev); 861 if (DC_IS_ADMTEK(sc)) 862 return; 863 mii = device_get_softc(sc->dc_miibus); 864 ifm = &mii->mii_media; 865 if (DC_IS_DAVICOM(sc) && 866 IFM_SUBTYPE(ifm->ifm_media) == IFM_homePNA) { 867 dc_setcfg(sc, ifm->ifm_media); 868 sc->dc_if_media = ifm->ifm_media; 869 } else { 870 dc_setcfg(sc, mii->mii_media_active); 871 sc->dc_if_media = mii->mii_media_active; 872 } 873 874 return; 875 } 876 877 /* 878 * Special support for DM9102A cards with HomePNA PHYs. Note: 879 * with the Davicom DM9102A/DM9801 eval board that I have, it seems 880 * to be impossible to talk to the management interface of the DM9801 881 * PHY (its MDIO pin is not connected to anything). Consequently, 882 * the driver has to just 'know' about the additional mode and deal 883 * with it itself. *sigh* 884 */ 885 static void dc_miibus_mediainit(dev) 886 device_t dev; 887 { 888 struct dc_softc *sc; 889 struct mii_data *mii; 890 struct ifmedia *ifm; 891 int rev; 892 893 rev = pci_read_config(dev, DC_PCI_CFRV, 4) & 0xFF; 894 895 sc = device_get_softc(dev); 896 mii = device_get_softc(sc->dc_miibus); 897 ifm = &mii->mii_media; 898 899 if (DC_IS_DAVICOM(sc) && rev >= DC_REVISION_DM9102A) 900 ifmedia_add(ifm, IFM_ETHER|IFM_homePNA, 0, NULL); 901 902 return; 903 } 904 905 #define DC_POLY 0xEDB88320 906 #define DC_BITS_512 9 907 #define DC_BITS_128 7 908 #define DC_BITS_64 6 909 910 static u_int32_t dc_crc_le(sc, addr) 911 struct dc_softc *sc; 912 caddr_t addr; 913 { 914 u_int32_t idx, bit, data, crc; 915 916 /* Compute CRC for the address value. */ 917 crc = 0xFFFFFFFF; /* initial value */ 918 919 for (idx = 0; idx < 6; idx++) { 920 for (data = *addr++, bit = 0; bit < 8; bit++, data >>= 1) 921 crc = (crc >> 1) ^ (((crc ^ data) & 1) ? DC_POLY : 0); 922 } 923 924 /* 925 * The hash table on the PNIC II and the MX98715AEC-C/D/E 926 * chips is only 128 bits wide. 927 */ 928 if (sc->dc_flags & DC_128BIT_HASH) 929 return (crc & ((1 << DC_BITS_128) - 1)); 930 931 /* The hash table on the MX98715BEC is only 64 bits wide. */ 932 if (sc->dc_flags & DC_64BIT_HASH) 933 return (crc & ((1 << DC_BITS_64) - 1)); 934 935 return (crc & ((1 << DC_BITS_512) - 1)); 936 } 937 938 /* 939 * Calculate CRC of a multicast group address, return the lower 6 bits. 940 */ 941 static u_int32_t dc_crc_be(addr) 942 caddr_t addr; 943 { 944 u_int32_t crc, carry; 945 int i, j; 946 u_int8_t c; 947 948 /* Compute CRC for the address value. */ 949 crc = 0xFFFFFFFF; /* initial value */ 950 951 for (i = 0; i < 6; i++) { 952 c = *(addr + i); 953 for (j = 0; j < 8; j++) { 954 carry = ((crc & 0x80000000) ? 1 : 0) ^ (c & 0x01); 955 crc <<= 1; 956 c >>= 1; 957 if (carry) 958 crc = (crc ^ 0x04c11db6) | carry; 959 } 960 } 961 962 /* return the filter bit position */ 963 return((crc >> 26) & 0x0000003F); 964 } 965 966 /* 967 * 21143-style RX filter setup routine. Filter programming is done by 968 * downloading a special setup frame into the TX engine. 21143, Macronix, 969 * PNIC, PNIC II and Davicom chips are programmed this way. 970 * 971 * We always program the chip using 'hash perfect' mode, i.e. one perfect 972 * address (our node address) and a 512-bit hash filter for multicast 973 * frames. We also sneak the broadcast address into the hash filter since 974 * we need that too. 975 */ 976 void dc_setfilt_21143(sc) 977 struct dc_softc *sc; 978 { 979 struct dc_desc *sframe; 980 u_int32_t h, *sp; 981 struct ifmultiaddr *ifma; 982 struct ifnet *ifp; 983 int i; 984 985 ifp = &sc->arpcom.ac_if; 986 987 i = sc->dc_cdata.dc_tx_prod; 988 DC_INC(sc->dc_cdata.dc_tx_prod, DC_TX_LIST_CNT); 989 sc->dc_cdata.dc_tx_cnt++; 990 sframe = &sc->dc_ldata->dc_tx_list[i]; 991 sp = (u_int32_t *)&sc->dc_cdata.dc_sbuf; 992 bzero((char *)sp, DC_SFRAME_LEN); 993 994 sframe->dc_data = vtophys(&sc->dc_cdata.dc_sbuf); 995 sframe->dc_ctl = DC_SFRAME_LEN | DC_TXCTL_SETUP | DC_TXCTL_TLINK | 996 DC_FILTER_HASHPERF | DC_TXCTL_FINT; 997 998 sc->dc_cdata.dc_tx_chain[i] = (struct mbuf *)&sc->dc_cdata.dc_sbuf; 999 1000 /* If we want promiscuous mode, set the allframes bit. */ 1001 if (ifp->if_flags & IFF_PROMISC) 1002 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC); 1003 else 1004 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC); 1005 1006 if (ifp->if_flags & IFF_ALLMULTI) 1007 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI); 1008 else 1009 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI); 1010 1011 for (ifma = ifp->if_multiaddrs.lh_first; ifma != NULL; 1012 ifma = ifma->ifma_link.le_next) { 1013 if (ifma->ifma_addr->sa_family != AF_LINK) 1014 continue; 1015 h = dc_crc_le(sc, 1016 LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 1017 sp[h >> 4] |= 1 << (h & 0xF); 1018 } 1019 1020 if (ifp->if_flags & IFF_BROADCAST) { 1021 h = dc_crc_le(sc, (caddr_t)ðerbroadcastaddr); 1022 sp[h >> 4] |= 1 << (h & 0xF); 1023 } 1024 1025 /* Set our MAC address */ 1026 sp[39] = ((u_int16_t *)sc->arpcom.ac_enaddr)[0]; 1027 sp[40] = ((u_int16_t *)sc->arpcom.ac_enaddr)[1]; 1028 sp[41] = ((u_int16_t *)sc->arpcom.ac_enaddr)[2]; 1029 1030 sframe->dc_status = DC_TXSTAT_OWN; 1031 CSR_WRITE_4(sc, DC_TXSTART, 0xFFFFFFFF); 1032 1033 /* 1034 * The PNIC takes an exceedingly long time to process its 1035 * setup frame; wait 10ms after posting the setup frame 1036 * before proceeding, just so it has time to swallow its 1037 * medicine. 1038 */ 1039 DELAY(10000); 1040 1041 ifp->if_timer = 5; 1042 1043 return; 1044 } 1045 1046 void dc_setfilt_admtek(sc) 1047 struct dc_softc *sc; 1048 { 1049 struct ifnet *ifp; 1050 int h = 0; 1051 u_int32_t hashes[2] = { 0, 0 }; 1052 struct ifmultiaddr *ifma; 1053 1054 ifp = &sc->arpcom.ac_if; 1055 1056 /* Init our MAC address */ 1057 CSR_WRITE_4(sc, DC_AL_PAR0, *(u_int32_t *)(&sc->arpcom.ac_enaddr[0])); 1058 CSR_WRITE_4(sc, DC_AL_PAR1, *(u_int32_t *)(&sc->arpcom.ac_enaddr[4])); 1059 1060 /* If we want promiscuous mode, set the allframes bit. */ 1061 if (ifp->if_flags & IFF_PROMISC) 1062 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC); 1063 else 1064 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC); 1065 1066 if (ifp->if_flags & IFF_ALLMULTI) 1067 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI); 1068 else 1069 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI); 1070 1071 /* first, zot all the existing hash bits */ 1072 CSR_WRITE_4(sc, DC_AL_MAR0, 0); 1073 CSR_WRITE_4(sc, DC_AL_MAR1, 0); 1074 1075 /* 1076 * If we're already in promisc or allmulti mode, we 1077 * don't have to bother programming the multicast filter. 1078 */ 1079 if (ifp->if_flags & (IFF_PROMISC|IFF_ALLMULTI)) 1080 return; 1081 1082 /* now program new ones */ 1083 for (ifma = ifp->if_multiaddrs.lh_first; ifma != NULL; 1084 ifma = ifma->ifma_link.le_next) { 1085 if (ifma->ifma_addr->sa_family != AF_LINK) 1086 continue; 1087 h = dc_crc_be(LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 1088 if (h < 32) 1089 hashes[0] |= (1 << h); 1090 else 1091 hashes[1] |= (1 << (h - 32)); 1092 } 1093 1094 CSR_WRITE_4(sc, DC_AL_MAR0, hashes[0]); 1095 CSR_WRITE_4(sc, DC_AL_MAR1, hashes[1]); 1096 1097 return; 1098 } 1099 1100 void dc_setfilt_asix(sc) 1101 struct dc_softc *sc; 1102 { 1103 struct ifnet *ifp; 1104 int h = 0; 1105 u_int32_t hashes[2] = { 0, 0 }; 1106 struct ifmultiaddr *ifma; 1107 1108 ifp = &sc->arpcom.ac_if; 1109 1110 /* Init our MAC address */ 1111 CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_PAR0); 1112 CSR_WRITE_4(sc, DC_AX_FILTDATA, 1113 *(u_int32_t *)(&sc->arpcom.ac_enaddr[0])); 1114 CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_PAR1); 1115 CSR_WRITE_4(sc, DC_AX_FILTDATA, 1116 *(u_int32_t *)(&sc->arpcom.ac_enaddr[4])); 1117 1118 /* If we want promiscuous mode, set the allframes bit. */ 1119 if (ifp->if_flags & IFF_PROMISC) 1120 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC); 1121 else 1122 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC); 1123 1124 if (ifp->if_flags & IFF_ALLMULTI) 1125 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI); 1126 else 1127 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI); 1128 1129 /* 1130 * The ASIX chip has a special bit to enable reception 1131 * of broadcast frames. 1132 */ 1133 if (ifp->if_flags & IFF_BROADCAST) 1134 DC_SETBIT(sc, DC_NETCFG, DC_AX_NETCFG_RX_BROAD); 1135 else 1136 DC_CLRBIT(sc, DC_NETCFG, DC_AX_NETCFG_RX_BROAD); 1137 1138 /* first, zot all the existing hash bits */ 1139 CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_MAR0); 1140 CSR_WRITE_4(sc, DC_AX_FILTDATA, 0); 1141 CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_MAR1); 1142 CSR_WRITE_4(sc, DC_AX_FILTDATA, 0); 1143 1144 /* 1145 * If we're already in promisc or allmulti mode, we 1146 * don't have to bother programming the multicast filter. 1147 */ 1148 if (ifp->if_flags & (IFF_PROMISC|IFF_ALLMULTI)) 1149 return; 1150 1151 /* now program new ones */ 1152 for (ifma = ifp->if_multiaddrs.lh_first; ifma != NULL; 1153 ifma = ifma->ifma_link.le_next) { 1154 if (ifma->ifma_addr->sa_family != AF_LINK) 1155 continue; 1156 h = dc_crc_be(LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 1157 if (h < 32) 1158 hashes[0] |= (1 << h); 1159 else 1160 hashes[1] |= (1 << (h - 32)); 1161 } 1162 1163 CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_MAR0); 1164 CSR_WRITE_4(sc, DC_AX_FILTDATA, hashes[0]); 1165 CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_MAR1); 1166 CSR_WRITE_4(sc, DC_AX_FILTDATA, hashes[1]); 1167 1168 return; 1169 } 1170 1171 static void dc_setfilt(sc) 1172 struct dc_softc *sc; 1173 { 1174 if (DC_IS_INTEL(sc) || DC_IS_MACRONIX(sc) || DC_IS_PNIC(sc) || 1175 DC_IS_PNICII(sc) || DC_IS_DAVICOM(sc)) 1176 dc_setfilt_21143(sc); 1177 1178 if (DC_IS_ASIX(sc)) 1179 dc_setfilt_asix(sc); 1180 1181 if (DC_IS_ADMTEK(sc)) 1182 dc_setfilt_admtek(sc); 1183 1184 return; 1185 } 1186 1187 /* 1188 * In order to fiddle with the 1189 * 'full-duplex' and '100Mbps' bits in the netconfig register, we 1190 * first have to put the transmit and/or receive logic in the idle state. 1191 */ 1192 static void dc_setcfg(sc, media) 1193 struct dc_softc *sc; 1194 int media; 1195 { 1196 int i, restart = 0; 1197 u_int32_t isr; 1198 1199 if (IFM_SUBTYPE(media) == IFM_NONE) 1200 return; 1201 1202 if (CSR_READ_4(sc, DC_NETCFG) & (DC_NETCFG_TX_ON|DC_NETCFG_RX_ON)) { 1203 restart = 1; 1204 DC_CLRBIT(sc, DC_NETCFG, (DC_NETCFG_TX_ON|DC_NETCFG_RX_ON)); 1205 1206 for (i = 0; i < DC_TIMEOUT; i++) { 1207 DELAY(10); 1208 isr = CSR_READ_4(sc, DC_ISR); 1209 if (isr & DC_ISR_TX_IDLE || 1210 (isr & DC_ISR_RX_STATE) == DC_RXSTATE_STOPPED) 1211 break; 1212 } 1213 1214 if (i == DC_TIMEOUT) 1215 printf("dc%d: failed to force tx and " 1216 "rx to idle state\n", sc->dc_unit); 1217 1218 } 1219 1220 if (IFM_SUBTYPE(media) == IFM_100_TX) { 1221 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_SPEEDSEL); 1222 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_HEARTBEAT); 1223 if (sc->dc_pmode == DC_PMODE_MII) { 1224 DC_SETBIT(sc, DC_WATCHDOG, DC_WDOG_JABBERDIS); 1225 DC_CLRBIT(sc, DC_NETCFG, (DC_NETCFG_PCS| 1226 DC_NETCFG_PORTSEL|DC_NETCFG_SCRAMBLER)); 1227 if (sc->dc_type == DC_TYPE_98713) 1228 DC_SETBIT(sc, DC_NETCFG, (DC_NETCFG_PCS| 1229 DC_NETCFG_SCRAMBLER)); 1230 if (!DC_IS_DAVICOM(sc)) 1231 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL); 1232 DC_CLRBIT(sc, DC_10BTCTRL, 0xFFFF); 1233 } else { 1234 if (DC_IS_PNIC(sc)) { 1235 DC_PN_GPIO_SETBIT(sc, DC_PN_GPIO_SPEEDSEL); 1236 DC_PN_GPIO_SETBIT(sc, DC_PN_GPIO_100TX_LOOP); 1237 DC_SETBIT(sc, DC_PN_NWAY, DC_PN_NWAY_SPEEDSEL); 1238 } 1239 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL); 1240 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PCS); 1241 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_SCRAMBLER); 1242 } 1243 } 1244 1245 if (IFM_SUBTYPE(media) == IFM_10_T) { 1246 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_SPEEDSEL); 1247 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_HEARTBEAT); 1248 if (sc->dc_pmode == DC_PMODE_MII) { 1249 DC_SETBIT(sc, DC_WATCHDOG, DC_WDOG_JABBERDIS); 1250 DC_CLRBIT(sc, DC_NETCFG, (DC_NETCFG_PCS| 1251 DC_NETCFG_PORTSEL|DC_NETCFG_SCRAMBLER)); 1252 if (sc->dc_type == DC_TYPE_98713) 1253 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PCS); 1254 if (!DC_IS_DAVICOM(sc)) 1255 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL); 1256 DC_CLRBIT(sc, DC_10BTCTRL, 0xFFFF); 1257 } else { 1258 if (DC_IS_PNIC(sc)) { 1259 DC_PN_GPIO_CLRBIT(sc, DC_PN_GPIO_SPEEDSEL); 1260 DC_PN_GPIO_SETBIT(sc, DC_PN_GPIO_100TX_LOOP); 1261 DC_CLRBIT(sc, DC_PN_NWAY, DC_PN_NWAY_SPEEDSEL); 1262 } 1263 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL); 1264 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_PCS); 1265 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_SCRAMBLER); 1266 } 1267 } 1268 1269 /* 1270 * If this is a Davicom DM9102A card with a DM9801 HomePNA 1271 * PHY and we want HomePNA mode, set the portsel bit to turn 1272 * on the external MII port. 1273 */ 1274 if (DC_IS_DAVICOM(sc)) { 1275 if (IFM_SUBTYPE(media) == IFM_homePNA) { 1276 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL); 1277 sc->dc_link = 1; 1278 } else { 1279 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL); 1280 } 1281 } 1282 1283 if ((media & IFM_GMASK) == IFM_FDX) { 1284 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_FULLDUPLEX); 1285 if (sc->dc_pmode == DC_PMODE_SYM && DC_IS_PNIC(sc)) 1286 DC_SETBIT(sc, DC_PN_NWAY, DC_PN_NWAY_DUPLEX); 1287 } else { 1288 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_FULLDUPLEX); 1289 if (sc->dc_pmode == DC_PMODE_SYM && DC_IS_PNIC(sc)) 1290 DC_CLRBIT(sc, DC_PN_NWAY, DC_PN_NWAY_DUPLEX); 1291 } 1292 1293 if (restart) 1294 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_TX_ON|DC_NETCFG_RX_ON); 1295 1296 return; 1297 } 1298 1299 static void dc_reset(sc) 1300 struct dc_softc *sc; 1301 { 1302 register int i; 1303 1304 DC_SETBIT(sc, DC_BUSCTL, DC_BUSCTL_RESET); 1305 1306 for (i = 0; i < DC_TIMEOUT; i++) { 1307 DELAY(10); 1308 if (!(CSR_READ_4(sc, DC_BUSCTL) & DC_BUSCTL_RESET)) 1309 break; 1310 } 1311 1312 if (DC_IS_ASIX(sc) || DC_IS_ADMTEK(sc)) { 1313 DELAY(10000); 1314 DC_CLRBIT(sc, DC_BUSCTL, DC_BUSCTL_RESET); 1315 i = 0; 1316 } 1317 1318 if (i == DC_TIMEOUT) 1319 printf("dc%d: reset never completed!\n", sc->dc_unit); 1320 1321 /* Wait a little while for the chip to get its brains in order. */ 1322 DELAY(1000); 1323 1324 CSR_WRITE_4(sc, DC_IMR, 0x00000000); 1325 CSR_WRITE_4(sc, DC_BUSCTL, 0x00000000); 1326 CSR_WRITE_4(sc, DC_NETCFG, 0x00000000); 1327 1328 /* 1329 * Bring the SIA out of reset. In some cases, it looks 1330 * like failing to unreset the SIA soon enough gets it 1331 * into a state where it will never come out of reset 1332 * until we reset the whole chip again. 1333 */ 1334 if (DC_IS_INTEL(sc)) 1335 DC_SETBIT(sc, DC_SIARESET, DC_SIA_RESET); 1336 1337 return; 1338 } 1339 1340 static struct dc_type *dc_devtype(dev) 1341 device_t dev; 1342 { 1343 struct dc_type *t; 1344 u_int32_t rev; 1345 1346 t = dc_devs; 1347 1348 while(t->dc_name != NULL) { 1349 if ((pci_get_vendor(dev) == t->dc_vid) && 1350 (pci_get_device(dev) == t->dc_did)) { 1351 /* Check the PCI revision */ 1352 rev = pci_read_config(dev, DC_PCI_CFRV, 4) & 0xFF; 1353 if (t->dc_did == DC_DEVICEID_98713 && 1354 rev >= DC_REVISION_98713A) 1355 t++; 1356 if (t->dc_did == DC_DEVICEID_98713_CP && 1357 rev >= DC_REVISION_98713A) 1358 t++; 1359 if (t->dc_did == DC_DEVICEID_987x5 && 1360 rev >= DC_REVISION_98715AEC_C) 1361 t++; 1362 if (t->dc_did == DC_DEVICEID_987x5 && 1363 rev >= DC_REVISION_98725) 1364 t++; 1365 if (t->dc_did == DC_DEVICEID_AX88140A && 1366 rev >= DC_REVISION_88141) 1367 t++; 1368 if (t->dc_did == DC_DEVICEID_82C168 && 1369 rev >= DC_REVISION_82C169) 1370 t++; 1371 if (t->dc_did == DC_DEVICEID_DM9102 && 1372 rev >= DC_REVISION_DM9102A) 1373 t++; 1374 return(t); 1375 } 1376 t++; 1377 } 1378 1379 return(NULL); 1380 } 1381 1382 /* 1383 * Probe for a 21143 or clone chip. Check the PCI vendor and device 1384 * IDs against our list and return a device name if we find a match. 1385 * We do a little bit of extra work to identify the exact type of 1386 * chip. The MX98713 and MX98713A have the same PCI vendor/device ID, 1387 * but different revision IDs. The same is true for 98715/98715A 1388 * chips and the 98725, as well as the ASIX and ADMtek chips. In some 1389 * cases, the exact chip revision affects driver behavior. 1390 */ 1391 static int dc_probe(dev) 1392 device_t dev; 1393 { 1394 struct dc_type *t; 1395 1396 t = dc_devtype(dev); 1397 1398 if (t != NULL) { 1399 device_set_desc(dev, t->dc_name); 1400 return(0); 1401 } 1402 1403 return(ENXIO); 1404 } 1405 1406 static void dc_acpi(dev) 1407 device_t dev; 1408 { 1409 u_int32_t r, cptr; 1410 int unit; 1411 1412 unit = device_get_unit(dev); 1413 1414 /* Find the location of the capabilities block */ 1415 cptr = pci_read_config(dev, DC_PCI_CCAP, 4) & 0xFF; 1416 1417 r = pci_read_config(dev, cptr, 4) & 0xFF; 1418 if (r == 0x01) { 1419 1420 r = pci_read_config(dev, cptr + 4, 4); 1421 if (r & DC_PSTATE_D3) { 1422 u_int32_t iobase, membase, irq; 1423 1424 /* Save important PCI config data. */ 1425 iobase = pci_read_config(dev, DC_PCI_CFBIO, 4); 1426 membase = pci_read_config(dev, DC_PCI_CFBMA, 4); 1427 irq = pci_read_config(dev, DC_PCI_CFIT, 4); 1428 1429 /* Reset the power state. */ 1430 printf("dc%d: chip is in D%d power mode " 1431 "-- setting to D0\n", unit, r & DC_PSTATE_D3); 1432 r &= 0xFFFFFFFC; 1433 pci_write_config(dev, cptr + 4, r, 4); 1434 1435 /* Restore PCI config data. */ 1436 pci_write_config(dev, DC_PCI_CFBIO, iobase, 4); 1437 pci_write_config(dev, DC_PCI_CFBMA, membase, 4); 1438 pci_write_config(dev, DC_PCI_CFIT, irq, 4); 1439 } 1440 } 1441 return; 1442 } 1443 1444 /* 1445 * Attach the interface. Allocate softc structures, do ifmedia 1446 * setup and ethernet/BPF attach. 1447 */ 1448 static int dc_attach(dev) 1449 device_t dev; 1450 { 1451 int s; 1452 u_char eaddr[ETHER_ADDR_LEN]; 1453 u_int32_t command; 1454 struct dc_softc *sc; 1455 struct ifnet *ifp; 1456 u_int32_t revision; 1457 int unit, error = 0, rid, mac_offset; 1458 1459 s = splimp(); 1460 1461 sc = device_get_softc(dev); 1462 unit = device_get_unit(dev); 1463 bzero(sc, sizeof(struct dc_softc)); 1464 1465 /* 1466 * Handle power management nonsense. 1467 */ 1468 dc_acpi(dev); 1469 1470 /* 1471 * Map control/status registers. 1472 */ 1473 command = pci_read_config(dev, PCIR_COMMAND, 4); 1474 command |= (PCIM_CMD_PORTEN|PCIM_CMD_MEMEN|PCIM_CMD_BUSMASTEREN); 1475 pci_write_config(dev, PCIR_COMMAND, command, 4); 1476 command = pci_read_config(dev, PCIR_COMMAND, 4); 1477 1478 #ifdef DC_USEIOSPACE 1479 if (!(command & PCIM_CMD_PORTEN)) { 1480 printf("dc%d: failed to enable I/O ports!\n", unit); 1481 error = ENXIO; 1482 goto fail; 1483 } 1484 #else 1485 if (!(command & PCIM_CMD_MEMEN)) { 1486 printf("dc%d: failed to enable memory mapping!\n", unit); 1487 error = ENXIO; 1488 goto fail; 1489 } 1490 #endif 1491 1492 rid = DC_RID; 1493 sc->dc_res = bus_alloc_resource(dev, DC_RES, &rid, 1494 0, ~0, 1, RF_ACTIVE); 1495 1496 if (sc->dc_res == NULL) { 1497 printf("dc%d: couldn't map ports/memory\n", unit); 1498 error = ENXIO; 1499 goto fail; 1500 } 1501 1502 sc->dc_btag = rman_get_bustag(sc->dc_res); 1503 sc->dc_bhandle = rman_get_bushandle(sc->dc_res); 1504 1505 /* Allocate interrupt */ 1506 rid = 0; 1507 sc->dc_irq = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, 0, ~0, 1, 1508 RF_SHAREABLE | RF_ACTIVE); 1509 1510 if (sc->dc_irq == NULL) { 1511 printf("dc%d: couldn't map interrupt\n", unit); 1512 bus_release_resource(dev, DC_RES, DC_RID, sc->dc_res); 1513 error = ENXIO; 1514 goto fail; 1515 } 1516 1517 error = bus_setup_intr(dev, sc->dc_irq, INTR_TYPE_NET, 1518 dc_intr, sc, &sc->dc_intrhand); 1519 1520 if (error) { 1521 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->dc_irq); 1522 bus_release_resource(dev, DC_RES, DC_RID, sc->dc_res); 1523 printf("dc%d: couldn't set up irq\n", unit); 1524 goto fail; 1525 } 1526 1527 /* Need this info to decide on a chip type. */ 1528 sc->dc_info = dc_devtype(dev); 1529 revision = pci_read_config(dev, DC_PCI_CFRV, 4) & 0x000000FF; 1530 1531 switch(sc->dc_info->dc_did) { 1532 case DC_DEVICEID_21143: 1533 sc->dc_type = DC_TYPE_21143; 1534 sc->dc_flags |= DC_TX_POLL|DC_TX_USE_TX_INTR; 1535 sc->dc_flags |= DC_REDUCED_MII_POLL; 1536 break; 1537 case DC_DEVICEID_DM9100: 1538 case DC_DEVICEID_DM9102: 1539 sc->dc_type = DC_TYPE_DM9102; 1540 sc->dc_flags |= DC_TX_COALESCE|DC_TX_USE_TX_INTR; 1541 sc->dc_flags |= DC_REDUCED_MII_POLL; 1542 sc->dc_pmode = DC_PMODE_MII; 1543 break; 1544 case DC_DEVICEID_AL981: 1545 sc->dc_type = DC_TYPE_AL981; 1546 sc->dc_flags |= DC_TX_USE_TX_INTR; 1547 sc->dc_flags |= DC_TX_ADMTEK_WAR; 1548 sc->dc_pmode = DC_PMODE_MII; 1549 break; 1550 case DC_DEVICEID_AN985: 1551 sc->dc_type = DC_TYPE_AN985; 1552 sc->dc_flags |= DC_TX_USE_TX_INTR; 1553 sc->dc_flags |= DC_TX_ADMTEK_WAR; 1554 sc->dc_pmode = DC_PMODE_MII; 1555 break; 1556 case DC_DEVICEID_98713: 1557 case DC_DEVICEID_98713_CP: 1558 if (revision < DC_REVISION_98713A) { 1559 sc->dc_type = DC_TYPE_98713; 1560 } 1561 if (revision >= DC_REVISION_98713A) { 1562 sc->dc_type = DC_TYPE_98713A; 1563 sc->dc_flags |= DC_21143_NWAY; 1564 } 1565 sc->dc_flags |= DC_REDUCED_MII_POLL; 1566 sc->dc_flags |= DC_TX_POLL|DC_TX_USE_TX_INTR; 1567 break; 1568 case DC_DEVICEID_987x5: 1569 case DC_DEVICEID_EN1217: 1570 /* 1571 * Macronix MX98715AEC-C/D/E parts have only a 1572 * 128-bit hash table. We need to deal with these 1573 * in the same manner as the PNIC II so that we 1574 * get the right number of bits out of the 1575 * CRC routine. 1576 */ 1577 if (revision >= DC_REVISION_98715AEC_C && 1578 revision < DC_REVISION_98725) 1579 sc->dc_flags |= DC_128BIT_HASH; 1580 sc->dc_type = DC_TYPE_987x5; 1581 sc->dc_flags |= DC_TX_POLL|DC_TX_USE_TX_INTR; 1582 sc->dc_flags |= DC_REDUCED_MII_POLL|DC_21143_NWAY; 1583 break; 1584 case DC_DEVICEID_98727: 1585 sc->dc_type = DC_TYPE_987x5; 1586 sc->dc_flags |= DC_TX_POLL|DC_TX_USE_TX_INTR; 1587 sc->dc_flags |= DC_REDUCED_MII_POLL|DC_21143_NWAY; 1588 break; 1589 case DC_DEVICEID_82C115: 1590 sc->dc_type = DC_TYPE_PNICII; 1591 sc->dc_flags |= DC_TX_POLL|DC_TX_USE_TX_INTR|DC_128BIT_HASH; 1592 sc->dc_flags |= DC_REDUCED_MII_POLL|DC_21143_NWAY; 1593 break; 1594 case DC_DEVICEID_82C168: 1595 sc->dc_type = DC_TYPE_PNIC; 1596 sc->dc_flags |= DC_TX_STORENFWD|DC_TX_INTR_ALWAYS; 1597 sc->dc_flags |= DC_PNIC_RX_BUG_WAR; 1598 sc->dc_pnic_rx_buf = malloc(DC_RXLEN * 5, M_DEVBUF, M_NOWAIT); 1599 if (revision < DC_REVISION_82C169) 1600 sc->dc_pmode = DC_PMODE_SYM; 1601 break; 1602 case DC_DEVICEID_AX88140A: 1603 sc->dc_type = DC_TYPE_ASIX; 1604 sc->dc_flags |= DC_TX_USE_TX_INTR|DC_TX_INTR_FIRSTFRAG; 1605 sc->dc_flags |= DC_REDUCED_MII_POLL; 1606 sc->dc_pmode = DC_PMODE_MII; 1607 break; 1608 default: 1609 printf("dc%d: unknown device: %x\n", sc->dc_unit, 1610 sc->dc_info->dc_did); 1611 break; 1612 } 1613 1614 /* Save the cache line size. */ 1615 if (DC_IS_DAVICOM(sc)) 1616 sc->dc_cachesize = 0; 1617 else 1618 sc->dc_cachesize = pci_read_config(dev, 1619 DC_PCI_CFLT, 4) & 0xFF; 1620 1621 /* Reset the adapter. */ 1622 dc_reset(sc); 1623 1624 /* Take 21143 out of snooze mode */ 1625 if (DC_IS_INTEL(sc)) { 1626 command = pci_read_config(dev, DC_PCI_CFDD, 4); 1627 command &= ~(DC_CFDD_SNOOZE_MODE|DC_CFDD_SLEEP_MODE); 1628 pci_write_config(dev, DC_PCI_CFDD, command, 4); 1629 } 1630 1631 /* 1632 * Try to learn something about the supported media. 1633 * We know that ASIX and ADMtek and Davicom devices 1634 * will *always* be using MII media, so that's a no-brainer. 1635 * The tricky ones are the Macronix/PNIC II and the 1636 * Intel 21143. 1637 */ 1638 if (DC_IS_INTEL(sc)) { 1639 u_int32_t media, cwuc; 1640 cwuc = pci_read_config(dev, DC_PCI_CWUC, 4); 1641 cwuc |= DC_CWUC_FORCE_WUL; 1642 pci_write_config(dev, DC_PCI_CWUC, cwuc, 4); 1643 DELAY(10000); 1644 media = pci_read_config(dev, DC_PCI_CWUC, 4); 1645 cwuc &= ~DC_CWUC_FORCE_WUL; 1646 pci_write_config(dev, DC_PCI_CWUC, cwuc, 4); 1647 DELAY(10000); 1648 if (media & DC_CWUC_MII_ABILITY) 1649 sc->dc_pmode = DC_PMODE_MII; 1650 if (media & DC_CWUC_SYM_ABILITY) { 1651 sc->dc_pmode = DC_PMODE_SYM; 1652 sc->dc_flags |= DC_21143_NWAY; 1653 } 1654 /* 1655 * If none of the bits are set, then this NIC 1656 * isn't meant to support 'wake up LAN' mode. 1657 * This is usually only the case on multiport 1658 * cards, and these cards almost always have 1659 * MII transceivers. 1660 */ 1661 if (media == 0) 1662 sc->dc_pmode = DC_PMODE_MII; 1663 } else if (DC_IS_MACRONIX(sc) || DC_IS_PNICII(sc)) { 1664 if (sc->dc_type == DC_TYPE_98713) 1665 sc->dc_pmode = DC_PMODE_MII; 1666 else 1667 sc->dc_pmode = DC_PMODE_SYM; 1668 } else if (!sc->dc_pmode) 1669 sc->dc_pmode = DC_PMODE_MII; 1670 1671 /* 1672 * Get station address from the EEPROM. 1673 */ 1674 switch(sc->dc_type) { 1675 case DC_TYPE_98713: 1676 case DC_TYPE_98713A: 1677 case DC_TYPE_987x5: 1678 case DC_TYPE_PNICII: 1679 dc_read_eeprom(sc, (caddr_t)&mac_offset, 1680 (DC_EE_NODEADDR_OFFSET / 2), 1, 0); 1681 dc_read_eeprom(sc, (caddr_t)&eaddr, (mac_offset / 2), 3, 0); 1682 break; 1683 case DC_TYPE_PNIC: 1684 dc_read_eeprom(sc, (caddr_t)&eaddr, 0, 3, 1); 1685 break; 1686 case DC_TYPE_DM9102: 1687 case DC_TYPE_21143: 1688 case DC_TYPE_ASIX: 1689 dc_read_eeprom(sc, (caddr_t)&eaddr, DC_EE_NODEADDR, 3, 0); 1690 break; 1691 case DC_TYPE_AL981: 1692 case DC_TYPE_AN985: 1693 dc_read_eeprom(sc, (caddr_t)&eaddr, DC_AL_EE_NODEADDR, 3, 0); 1694 break; 1695 default: 1696 dc_read_eeprom(sc, (caddr_t)&eaddr, DC_EE_NODEADDR, 3, 0); 1697 break; 1698 } 1699 1700 /* 1701 * A 21143 or clone chip was detected. Inform the world. 1702 */ 1703 printf("dc%d: Ethernet address: %6D\n", unit, eaddr, ":"); 1704 1705 sc->dc_unit = unit; 1706 bcopy(eaddr, (char *)&sc->arpcom.ac_enaddr, ETHER_ADDR_LEN); 1707 1708 sc->dc_ldata = contigmalloc(sizeof(struct dc_list_data), M_DEVBUF, 1709 M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0); 1710 1711 if (sc->dc_ldata == NULL) { 1712 printf("dc%d: no memory for list buffers!\n", unit); 1713 bus_teardown_intr(dev, sc->dc_irq, sc->dc_intrhand); 1714 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->dc_irq); 1715 bus_release_resource(dev, DC_RES, DC_RID, sc->dc_res); 1716 error = ENXIO; 1717 goto fail; 1718 } 1719 1720 bzero(sc->dc_ldata, sizeof(struct dc_list_data)); 1721 1722 ifp = &sc->arpcom.ac_if; 1723 ifp->if_softc = sc; 1724 ifp->if_unit = unit; 1725 ifp->if_name = "dc"; 1726 ifp->if_mtu = ETHERMTU; 1727 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 1728 ifp->if_ioctl = dc_ioctl; 1729 ifp->if_output = ether_output; 1730 ifp->if_start = dc_start; 1731 ifp->if_watchdog = dc_watchdog; 1732 ifp->if_init = dc_init; 1733 ifp->if_baudrate = 10000000; 1734 ifp->if_snd.ifq_maxlen = DC_TX_LIST_CNT - 1; 1735 1736 /* 1737 * Do MII setup. 1738 */ 1739 error = mii_phy_probe(dev, &sc->dc_miibus, 1740 dc_ifmedia_upd, dc_ifmedia_sts); 1741 1742 if (error && DC_IS_INTEL(sc)) { 1743 sc->dc_pmode = DC_PMODE_SYM; 1744 sc->dc_flags |= DC_21143_NWAY; 1745 mii_phy_probe(dev, &sc->dc_miibus, 1746 dc_ifmedia_upd, dc_ifmedia_sts); 1747 error = 0; 1748 } 1749 1750 if (error) { 1751 printf("dc%d: MII without any PHY!\n", sc->dc_unit); 1752 bus_teardown_intr(dev, sc->dc_irq, sc->dc_intrhand); 1753 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->dc_irq); 1754 bus_release_resource(dev, DC_RES, DC_RID, sc->dc_res); 1755 error = ENXIO; 1756 goto fail; 1757 } 1758 1759 /* 1760 * Call MI attach routine. 1761 */ 1762 ether_ifattach(ifp, ETHER_BPF_SUPPORTED); 1763 callout_handle_init(&sc->dc_stat_ch); 1764 1765 #ifdef __alpha__ 1766 sc->dc_srm_media = 0; 1767 1768 /* Remember the SRM console media setting */ 1769 if (DC_IS_INTEL(sc)) { 1770 command = pci_read_config(dev, DC_PCI_CFDD, 4); 1771 command &= ~(DC_CFDD_SNOOZE_MODE|DC_CFDD_SLEEP_MODE); 1772 switch ((command >> 8) & 0xff) { 1773 case 3: 1774 sc->dc_srm_media = IFM_10_T; 1775 break; 1776 case 4: 1777 sc->dc_srm_media = IFM_10_T | IFM_FDX; 1778 break; 1779 case 5: 1780 sc->dc_srm_media = IFM_100_TX; 1781 break; 1782 case 6: 1783 sc->dc_srm_media = IFM_100_TX | IFM_FDX; 1784 break; 1785 } 1786 if (sc->dc_srm_media) 1787 sc->dc_srm_media |= IFM_ACTIVE | IFM_ETHER; 1788 } 1789 #endif 1790 1791 1792 fail: 1793 splx(s); 1794 1795 return(error); 1796 } 1797 1798 static int dc_detach(dev) 1799 device_t dev; 1800 { 1801 struct dc_softc *sc; 1802 struct ifnet *ifp; 1803 int s; 1804 1805 s = splimp(); 1806 1807 sc = device_get_softc(dev); 1808 ifp = &sc->arpcom.ac_if; 1809 1810 dc_stop(sc); 1811 ether_ifdetach(ifp, ETHER_BPF_SUPPORTED); 1812 1813 bus_generic_detach(dev); 1814 device_delete_child(dev, sc->dc_miibus); 1815 1816 bus_teardown_intr(dev, sc->dc_irq, sc->dc_intrhand); 1817 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->dc_irq); 1818 bus_release_resource(dev, DC_RES, DC_RID, sc->dc_res); 1819 1820 contigfree(sc->dc_ldata, sizeof(struct dc_list_data), M_DEVBUF); 1821 if (sc->dc_pnic_rx_buf != NULL) 1822 free(sc->dc_pnic_rx_buf, M_DEVBUF); 1823 1824 splx(s); 1825 1826 return(0); 1827 } 1828 1829 /* 1830 * Initialize the transmit descriptors. 1831 */ 1832 static int dc_list_tx_init(sc) 1833 struct dc_softc *sc; 1834 { 1835 struct dc_chain_data *cd; 1836 struct dc_list_data *ld; 1837 int i; 1838 1839 cd = &sc->dc_cdata; 1840 ld = sc->dc_ldata; 1841 for (i = 0; i < DC_TX_LIST_CNT; i++) { 1842 if (i == (DC_TX_LIST_CNT - 1)) { 1843 ld->dc_tx_list[i].dc_next = 1844 vtophys(&ld->dc_tx_list[0]); 1845 } else { 1846 ld->dc_tx_list[i].dc_next = 1847 vtophys(&ld->dc_tx_list[i + 1]); 1848 } 1849 cd->dc_tx_chain[i] = NULL; 1850 ld->dc_tx_list[i].dc_data = 0; 1851 ld->dc_tx_list[i].dc_ctl = 0; 1852 } 1853 1854 cd->dc_tx_prod = cd->dc_tx_cons = cd->dc_tx_cnt = 0; 1855 1856 return(0); 1857 } 1858 1859 1860 /* 1861 * Initialize the RX descriptors and allocate mbufs for them. Note that 1862 * we arrange the descriptors in a closed ring, so that the last descriptor 1863 * points back to the first. 1864 */ 1865 static int dc_list_rx_init(sc) 1866 struct dc_softc *sc; 1867 { 1868 struct dc_chain_data *cd; 1869 struct dc_list_data *ld; 1870 int i; 1871 1872 cd = &sc->dc_cdata; 1873 ld = sc->dc_ldata; 1874 1875 for (i = 0; i < DC_RX_LIST_CNT; i++) { 1876 if (dc_newbuf(sc, i, NULL) == ENOBUFS) 1877 return(ENOBUFS); 1878 if (i == (DC_RX_LIST_CNT - 1)) { 1879 ld->dc_rx_list[i].dc_next = 1880 vtophys(&ld->dc_rx_list[0]); 1881 } else { 1882 ld->dc_rx_list[i].dc_next = 1883 vtophys(&ld->dc_rx_list[i + 1]); 1884 } 1885 } 1886 1887 cd->dc_rx_prod = 0; 1888 1889 return(0); 1890 } 1891 1892 /* 1893 * Initialize an RX descriptor and attach an MBUF cluster. 1894 */ 1895 static int dc_newbuf(sc, i, m) 1896 struct dc_softc *sc; 1897 int i; 1898 struct mbuf *m; 1899 { 1900 struct mbuf *m_new = NULL; 1901 struct dc_desc *c; 1902 1903 c = &sc->dc_ldata->dc_rx_list[i]; 1904 1905 if (m == NULL) { 1906 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 1907 if (m_new == NULL) { 1908 printf("dc%d: no memory for rx list " 1909 "-- packet dropped!\n", sc->dc_unit); 1910 return(ENOBUFS); 1911 } 1912 1913 MCLGET(m_new, M_DONTWAIT); 1914 if (!(m_new->m_flags & M_EXT)) { 1915 printf("dc%d: no memory for rx list " 1916 "-- packet dropped!\n", sc->dc_unit); 1917 m_freem(m_new); 1918 return(ENOBUFS); 1919 } 1920 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 1921 } else { 1922 m_new = m; 1923 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 1924 m_new->m_data = m_new->m_ext.ext_buf; 1925 } 1926 1927 m_adj(m_new, sizeof(u_int64_t)); 1928 1929 /* 1930 * If this is a PNIC chip, zero the buffer. This is part 1931 * of the workaround for the receive bug in the 82c168 and 1932 * 82c169 chips. 1933 */ 1934 if (sc->dc_flags & DC_PNIC_RX_BUG_WAR) 1935 bzero((char *)mtod(m_new, char *), m_new->m_len); 1936 1937 sc->dc_cdata.dc_rx_chain[i] = m_new; 1938 c->dc_data = vtophys(mtod(m_new, caddr_t)); 1939 c->dc_ctl = DC_RXCTL_RLINK | DC_RXLEN; 1940 c->dc_status = DC_RXSTAT_OWN; 1941 1942 return(0); 1943 } 1944 1945 /* 1946 * Grrrrr. 1947 * The PNIC chip has a terrible bug in it that manifests itself during 1948 * periods of heavy activity. The exact mode of failure if difficult to 1949 * pinpoint: sometimes it only happens in promiscuous mode, sometimes it 1950 * will happen on slow machines. The bug is that sometimes instead of 1951 * uploading one complete frame during reception, it uploads what looks 1952 * like the entire contents of its FIFO memory. The frame we want is at 1953 * the end of the whole mess, but we never know exactly how much data has 1954 * been uploaded, so salvaging the frame is hard. 1955 * 1956 * There is only one way to do it reliably, and it's disgusting. 1957 * Here's what we know: 1958 * 1959 * - We know there will always be somewhere between one and three extra 1960 * descriptors uploaded. 1961 * 1962 * - We know the desired received frame will always be at the end of the 1963 * total data upload. 1964 * 1965 * - We know the size of the desired received frame because it will be 1966 * provided in the length field of the status word in the last descriptor. 1967 * 1968 * Here's what we do: 1969 * 1970 * - When we allocate buffers for the receive ring, we bzero() them. 1971 * This means that we know that the buffer contents should be all 1972 * zeros, except for data uploaded by the chip. 1973 * 1974 * - We also force the PNIC chip to upload frames that include the 1975 * ethernet CRC at the end. 1976 * 1977 * - We gather all of the bogus frame data into a single buffer. 1978 * 1979 * - We then position a pointer at the end of this buffer and scan 1980 * backwards until we encounter the first non-zero byte of data. 1981 * This is the end of the received frame. We know we will encounter 1982 * some data at the end of the frame because the CRC will always be 1983 * there, so even if the sender transmits a packet of all zeros, 1984 * we won't be fooled. 1985 * 1986 * - We know the size of the actual received frame, so we subtract 1987 * that value from the current pointer location. This brings us 1988 * to the start of the actual received packet. 1989 * 1990 * - We copy this into an mbuf and pass it on, along with the actual 1991 * frame length. 1992 * 1993 * The performance hit is tremendous, but it beats dropping frames all 1994 * the time. 1995 */ 1996 1997 #define DC_WHOLEFRAME (DC_RXSTAT_FIRSTFRAG|DC_RXSTAT_LASTFRAG) 1998 static void dc_pnic_rx_bug_war(sc, idx) 1999 struct dc_softc *sc; 2000 int idx; 2001 { 2002 struct dc_desc *cur_rx; 2003 struct dc_desc *c = NULL; 2004 struct mbuf *m = NULL; 2005 unsigned char *ptr; 2006 int i, total_len; 2007 u_int32_t rxstat = 0; 2008 2009 i = sc->dc_pnic_rx_bug_save; 2010 cur_rx = &sc->dc_ldata->dc_rx_list[idx]; 2011 ptr = sc->dc_pnic_rx_buf; 2012 bzero(ptr, sizeof(DC_RXLEN * 5)); 2013 2014 /* Copy all the bytes from the bogus buffers. */ 2015 while (1) { 2016 c = &sc->dc_ldata->dc_rx_list[i]; 2017 rxstat = c->dc_status; 2018 m = sc->dc_cdata.dc_rx_chain[i]; 2019 bcopy(mtod(m, char *), ptr, DC_RXLEN); 2020 ptr += DC_RXLEN; 2021 /* If this is the last buffer, break out. */ 2022 if (i == idx || rxstat & DC_RXSTAT_LASTFRAG) 2023 break; 2024 dc_newbuf(sc, i, m); 2025 DC_INC(i, DC_RX_LIST_CNT); 2026 } 2027 2028 /* Find the length of the actual receive frame. */ 2029 total_len = DC_RXBYTES(rxstat); 2030 2031 /* Scan backwards until we hit a non-zero byte. */ 2032 while(*ptr == 0x00) 2033 ptr--; 2034 2035 /* Round off. */ 2036 if ((uintptr_t)(ptr) & 0x3) 2037 ptr -= 1; 2038 2039 /* Now find the start of the frame. */ 2040 ptr -= total_len; 2041 if (ptr < sc->dc_pnic_rx_buf) 2042 ptr = sc->dc_pnic_rx_buf; 2043 2044 /* 2045 * Now copy the salvaged frame to the last mbuf and fake up 2046 * the status word to make it look like a successful 2047 * frame reception. 2048 */ 2049 dc_newbuf(sc, i, m); 2050 bcopy(ptr, mtod(m, char *), total_len); 2051 cur_rx->dc_status = rxstat | DC_RXSTAT_FIRSTFRAG; 2052 2053 return; 2054 } 2055 2056 /* 2057 * This routine searches the RX ring for dirty descriptors in the 2058 * event that the rxeof routine falls out of sync with the chip's 2059 * current descriptor pointer. This may happen sometimes as a result 2060 * of a "no RX buffer available" condition that happens when the chip 2061 * consumes all of the RX buffers before the driver has a chance to 2062 * process the RX ring. This routine may need to be called more than 2063 * once to bring the driver back in sync with the chip, however we 2064 * should still be getting RX DONE interrupts to drive the search 2065 * for new packets in the RX ring, so we should catch up eventually. 2066 */ 2067 static int dc_rx_resync(sc) 2068 struct dc_softc *sc; 2069 { 2070 int i, pos; 2071 struct dc_desc *cur_rx; 2072 2073 pos = sc->dc_cdata.dc_rx_prod; 2074 2075 for (i = 0; i < DC_RX_LIST_CNT; i++) { 2076 cur_rx = &sc->dc_ldata->dc_rx_list[pos]; 2077 if (!(cur_rx->dc_status & DC_RXSTAT_OWN)) 2078 break; 2079 DC_INC(pos, DC_RX_LIST_CNT); 2080 } 2081 2082 /* If the ring really is empty, then just return. */ 2083 if (i == DC_RX_LIST_CNT) 2084 return(0); 2085 2086 /* We've fallen behing the chip: catch it. */ 2087 sc->dc_cdata.dc_rx_prod = pos; 2088 2089 return(EAGAIN); 2090 } 2091 2092 /* 2093 * A frame has been uploaded: pass the resulting mbuf chain up to 2094 * the higher level protocols. 2095 */ 2096 static void dc_rxeof(sc) 2097 struct dc_softc *sc; 2098 { 2099 struct ether_header *eh; 2100 struct mbuf *m; 2101 struct ifnet *ifp; 2102 struct dc_desc *cur_rx; 2103 int i, total_len = 0; 2104 u_int32_t rxstat; 2105 2106 ifp = &sc->arpcom.ac_if; 2107 i = sc->dc_cdata.dc_rx_prod; 2108 2109 while(!(sc->dc_ldata->dc_rx_list[i].dc_status & DC_RXSTAT_OWN)) { 2110 struct mbuf *m0 = NULL; 2111 2112 cur_rx = &sc->dc_ldata->dc_rx_list[i]; 2113 rxstat = cur_rx->dc_status; 2114 m = sc->dc_cdata.dc_rx_chain[i]; 2115 total_len = DC_RXBYTES(rxstat); 2116 2117 if (sc->dc_flags & DC_PNIC_RX_BUG_WAR) { 2118 if ((rxstat & DC_WHOLEFRAME) != DC_WHOLEFRAME) { 2119 if (rxstat & DC_RXSTAT_FIRSTFRAG) 2120 sc->dc_pnic_rx_bug_save = i; 2121 if ((rxstat & DC_RXSTAT_LASTFRAG) == 0) { 2122 DC_INC(i, DC_RX_LIST_CNT); 2123 continue; 2124 } 2125 dc_pnic_rx_bug_war(sc, i); 2126 rxstat = cur_rx->dc_status; 2127 total_len = DC_RXBYTES(rxstat); 2128 } 2129 } 2130 2131 sc->dc_cdata.dc_rx_chain[i] = NULL; 2132 2133 /* 2134 * If an error occurs, update stats, clear the 2135 * status word and leave the mbuf cluster in place: 2136 * it should simply get re-used next time this descriptor 2137 * comes up in the ring. 2138 */ 2139 if (rxstat & DC_RXSTAT_RXERR) { 2140 ifp->if_ierrors++; 2141 if (rxstat & DC_RXSTAT_COLLSEEN) 2142 ifp->if_collisions++; 2143 dc_newbuf(sc, i, m); 2144 if (rxstat & DC_RXSTAT_CRCERR) { 2145 DC_INC(i, DC_RX_LIST_CNT); 2146 continue; 2147 } else { 2148 dc_init(sc); 2149 return; 2150 } 2151 } 2152 2153 /* No errors; receive the packet. */ 2154 total_len -= ETHER_CRC_LEN; 2155 2156 m0 = m_devget(mtod(m, char *) - ETHER_ALIGN, 2157 total_len + ETHER_ALIGN, 0, ifp, NULL); 2158 dc_newbuf(sc, i, m); 2159 DC_INC(i, DC_RX_LIST_CNT); 2160 if (m0 == NULL) { 2161 ifp->if_ierrors++; 2162 continue; 2163 } 2164 m_adj(m0, ETHER_ALIGN); 2165 m = m0; 2166 2167 ifp->if_ipackets++; 2168 eh = mtod(m, struct ether_header *); 2169 2170 /* Remove header from mbuf and pass it on. */ 2171 m_adj(m, sizeof(struct ether_header)); 2172 ether_input(ifp, eh, m); 2173 } 2174 2175 sc->dc_cdata.dc_rx_prod = i; 2176 } 2177 2178 /* 2179 * A frame was downloaded to the chip. It's safe for us to clean up 2180 * the list buffers. 2181 */ 2182 2183 static void dc_txeof(sc) 2184 struct dc_softc *sc; 2185 { 2186 struct dc_desc *cur_tx = NULL; 2187 struct ifnet *ifp; 2188 int idx; 2189 2190 ifp = &sc->arpcom.ac_if; 2191 2192 /* Clear the timeout timer. */ 2193 ifp->if_timer = 0; 2194 2195 /* 2196 * Go through our tx list and free mbufs for those 2197 * frames that have been transmitted. 2198 */ 2199 idx = sc->dc_cdata.dc_tx_cons; 2200 while(idx != sc->dc_cdata.dc_tx_prod) { 2201 u_int32_t txstat; 2202 2203 cur_tx = &sc->dc_ldata->dc_tx_list[idx]; 2204 txstat = cur_tx->dc_status; 2205 2206 if (txstat & DC_TXSTAT_OWN) 2207 break; 2208 2209 if (!(cur_tx->dc_ctl & DC_TXCTL_LASTFRAG) || 2210 cur_tx->dc_ctl & DC_TXCTL_SETUP) { 2211 sc->dc_cdata.dc_tx_cnt--; 2212 if (cur_tx->dc_ctl & DC_TXCTL_SETUP) { 2213 /* 2214 * Yes, the PNIC is so brain damaged 2215 * that it will sometimes generate a TX 2216 * underrun error while DMAing the RX 2217 * filter setup frame. If we detect this, 2218 * we have to send the setup frame again, 2219 * or else the filter won't be programmed 2220 * correctly. 2221 */ 2222 if (DC_IS_PNIC(sc)) { 2223 if (txstat & DC_TXSTAT_ERRSUM) 2224 dc_setfilt(sc); 2225 } 2226 sc->dc_cdata.dc_tx_chain[idx] = NULL; 2227 } 2228 DC_INC(idx, DC_TX_LIST_CNT); 2229 continue; 2230 } 2231 2232 if (/*sc->dc_type == DC_TYPE_21143 &&*/ 2233 sc->dc_pmode == DC_PMODE_MII && 2234 ((txstat & 0xFFFF) & ~(DC_TXSTAT_ERRSUM| 2235 DC_TXSTAT_NOCARRIER|DC_TXSTAT_CARRLOST))) 2236 txstat &= ~DC_TXSTAT_ERRSUM; 2237 2238 if (txstat & DC_TXSTAT_ERRSUM) { 2239 ifp->if_oerrors++; 2240 if (txstat & DC_TXSTAT_EXCESSCOLL) 2241 ifp->if_collisions++; 2242 if (txstat & DC_TXSTAT_LATECOLL) 2243 ifp->if_collisions++; 2244 if (!(txstat & DC_TXSTAT_UNDERRUN)) { 2245 dc_init(sc); 2246 return; 2247 } 2248 } 2249 2250 ifp->if_collisions += (txstat & DC_TXSTAT_COLLCNT) >> 3; 2251 2252 ifp->if_opackets++; 2253 if (sc->dc_cdata.dc_tx_chain[idx] != NULL) { 2254 m_freem(sc->dc_cdata.dc_tx_chain[idx]); 2255 sc->dc_cdata.dc_tx_chain[idx] = NULL; 2256 } 2257 2258 sc->dc_cdata.dc_tx_cnt--; 2259 DC_INC(idx, DC_TX_LIST_CNT); 2260 } 2261 2262 sc->dc_cdata.dc_tx_cons = idx; 2263 if (cur_tx != NULL) 2264 ifp->if_flags &= ~IFF_OACTIVE; 2265 2266 return; 2267 } 2268 2269 static void dc_tick(xsc) 2270 void *xsc; 2271 { 2272 struct dc_softc *sc; 2273 struct mii_data *mii; 2274 struct ifnet *ifp; 2275 int s; 2276 u_int32_t r; 2277 2278 s = splimp(); 2279 2280 sc = xsc; 2281 ifp = &sc->arpcom.ac_if; 2282 mii = device_get_softc(sc->dc_miibus); 2283 2284 if (sc->dc_flags & DC_REDUCED_MII_POLL) { 2285 if (sc->dc_flags & DC_21143_NWAY) { 2286 r = CSR_READ_4(sc, DC_10BTSTAT); 2287 if (IFM_SUBTYPE(mii->mii_media_active) == 2288 IFM_100_TX && (r & DC_TSTAT_LS100)) { 2289 sc->dc_link = 0; 2290 mii_mediachg(mii); 2291 } 2292 if (IFM_SUBTYPE(mii->mii_media_active) == 2293 IFM_10_T && (r & DC_TSTAT_LS10)) { 2294 sc->dc_link = 0; 2295 mii_mediachg(mii); 2296 } 2297 if (sc->dc_link == 0) 2298 mii_tick(mii); 2299 } else { 2300 r = CSR_READ_4(sc, DC_ISR); 2301 if ((r & DC_ISR_RX_STATE) == DC_RXSTATE_WAIT && 2302 sc->dc_cdata.dc_tx_cnt == 0) 2303 mii_tick(mii); 2304 if (!(mii->mii_media_status & IFM_ACTIVE)) 2305 sc->dc_link = 0; 2306 } 2307 } else 2308 mii_tick(mii); 2309 2310 /* 2311 * When the init routine completes, we expect to be able to send 2312 * packets right away, and in fact the network code will send a 2313 * gratuitous ARP the moment the init routine marks the interface 2314 * as running. However, even though the MAC may have been initialized, 2315 * there may be a delay of a few seconds before the PHY completes 2316 * autonegotiation and the link is brought up. Any transmissions 2317 * made during that delay will be lost. Dealing with this is tricky: 2318 * we can't just pause in the init routine while waiting for the 2319 * PHY to come ready since that would bring the whole system to 2320 * a screeching halt for several seconds. 2321 * 2322 * What we do here is prevent the TX start routine from sending 2323 * any packets until a link has been established. After the 2324 * interface has been initialized, the tick routine will poll 2325 * the state of the PHY until the IFM_ACTIVE flag is set. Until 2326 * that time, packets will stay in the send queue, and once the 2327 * link comes up, they will be flushed out to the wire. 2328 */ 2329 if (!sc->dc_link) { 2330 mii_pollstat(mii); 2331 if (mii->mii_media_status & IFM_ACTIVE && 2332 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) { 2333 sc->dc_link++; 2334 if (ifp->if_snd.ifq_head != NULL) 2335 dc_start(ifp); 2336 } 2337 } 2338 2339 if (sc->dc_flags & DC_21143_NWAY && !sc->dc_link) 2340 sc->dc_stat_ch = timeout(dc_tick, sc, hz/10); 2341 else 2342 sc->dc_stat_ch = timeout(dc_tick, sc, hz); 2343 2344 splx(s); 2345 2346 return; 2347 } 2348 2349 static void dc_intr(arg) 2350 void *arg; 2351 { 2352 struct dc_softc *sc; 2353 struct ifnet *ifp; 2354 u_int32_t status; 2355 2356 sc = arg; 2357 ifp = &sc->arpcom.ac_if; 2358 2359 /* Supress unwanted interrupts */ 2360 if (!(ifp->if_flags & IFF_UP)) { 2361 if (CSR_READ_4(sc, DC_ISR) & DC_INTRS) 2362 dc_stop(sc); 2363 return; 2364 } 2365 2366 /* Disable interrupts. */ 2367 CSR_WRITE_4(sc, DC_IMR, 0x00000000); 2368 2369 while((status = CSR_READ_4(sc, DC_ISR)) & DC_INTRS) { 2370 2371 CSR_WRITE_4(sc, DC_ISR, status); 2372 2373 if (status & DC_ISR_RX_OK) { 2374 int curpkts; 2375 curpkts = ifp->if_ipackets; 2376 dc_rxeof(sc); 2377 if (curpkts == ifp->if_ipackets) { 2378 while(dc_rx_resync(sc)) 2379 dc_rxeof(sc); 2380 } 2381 } 2382 2383 if (status & (DC_ISR_TX_OK|DC_ISR_TX_NOBUF)) 2384 dc_txeof(sc); 2385 2386 if (status & DC_ISR_TX_IDLE) { 2387 dc_txeof(sc); 2388 if (sc->dc_cdata.dc_tx_cnt) { 2389 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_TX_ON); 2390 CSR_WRITE_4(sc, DC_TXSTART, 0xFFFFFFFF); 2391 } 2392 } 2393 2394 if (status & DC_ISR_TX_UNDERRUN) { 2395 u_int32_t cfg; 2396 2397 printf("dc%d: TX underrun -- ", sc->dc_unit); 2398 if (DC_IS_DAVICOM(sc) || DC_IS_INTEL(sc)) 2399 dc_init(sc); 2400 cfg = CSR_READ_4(sc, DC_NETCFG); 2401 cfg &= ~DC_NETCFG_TX_THRESH; 2402 if (sc->dc_txthresh == DC_TXTHRESH_160BYTES) { 2403 printf("using store and forward mode\n"); 2404 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_STORENFWD); 2405 } else if (sc->dc_flags & DC_TX_STORENFWD) { 2406 printf("resetting\n"); 2407 } else { 2408 sc->dc_txthresh += 0x4000; 2409 printf("increasing TX threshold\n"); 2410 CSR_WRITE_4(sc, DC_NETCFG, cfg); 2411 DC_SETBIT(sc, DC_NETCFG, sc->dc_txthresh); 2412 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_STORENFWD); 2413 } 2414 } 2415 2416 if ((status & DC_ISR_RX_WATDOGTIMEO) 2417 || (status & DC_ISR_RX_NOBUF)) { 2418 int curpkts; 2419 curpkts = ifp->if_ipackets; 2420 dc_rxeof(sc); 2421 if (curpkts == ifp->if_ipackets) { 2422 while(dc_rx_resync(sc)) 2423 dc_rxeof(sc); 2424 } 2425 } 2426 2427 if (status & DC_ISR_BUS_ERR) { 2428 dc_reset(sc); 2429 dc_init(sc); 2430 } 2431 } 2432 2433 /* Re-enable interrupts. */ 2434 CSR_WRITE_4(sc, DC_IMR, DC_INTRS); 2435 2436 if (ifp->if_snd.ifq_head != NULL) 2437 dc_start(ifp); 2438 2439 return; 2440 } 2441 2442 /* 2443 * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data 2444 * pointers to the fragment pointers. 2445 */ 2446 static int dc_encap(sc, m_head, txidx) 2447 struct dc_softc *sc; 2448 struct mbuf *m_head; 2449 u_int32_t *txidx; 2450 { 2451 struct dc_desc *f = NULL; 2452 struct mbuf *m; 2453 int frag, cur, cnt = 0; 2454 2455 /* 2456 * Start packing the mbufs in this chain into 2457 * the fragment pointers. Stop when we run out 2458 * of fragments or hit the end of the mbuf chain. 2459 */ 2460 m = m_head; 2461 cur = frag = *txidx; 2462 2463 for (m = m_head; m != NULL; m = m->m_next) { 2464 if (m->m_len != 0) { 2465 if (sc->dc_flags & DC_TX_ADMTEK_WAR) { 2466 if (*txidx != sc->dc_cdata.dc_tx_prod && 2467 frag == (DC_TX_LIST_CNT - 1)) 2468 return(ENOBUFS); 2469 } 2470 if ((DC_TX_LIST_CNT - 2471 (sc->dc_cdata.dc_tx_cnt + cnt)) < 5) 2472 return(ENOBUFS); 2473 2474 f = &sc->dc_ldata->dc_tx_list[frag]; 2475 f->dc_ctl = DC_TXCTL_TLINK | m->m_len; 2476 if (cnt == 0) { 2477 f->dc_status = 0; 2478 f->dc_ctl |= DC_TXCTL_FIRSTFRAG; 2479 } else 2480 f->dc_status = DC_TXSTAT_OWN; 2481 f->dc_data = vtophys(mtod(m, vm_offset_t)); 2482 cur = frag; 2483 DC_INC(frag, DC_TX_LIST_CNT); 2484 cnt++; 2485 } 2486 } 2487 2488 if (m != NULL) 2489 return(ENOBUFS); 2490 2491 sc->dc_cdata.dc_tx_cnt += cnt; 2492 sc->dc_cdata.dc_tx_chain[cur] = m_head; 2493 sc->dc_ldata->dc_tx_list[cur].dc_ctl |= DC_TXCTL_LASTFRAG; 2494 if (sc->dc_flags & DC_TX_INTR_FIRSTFRAG) 2495 sc->dc_ldata->dc_tx_list[*txidx].dc_ctl |= DC_TXCTL_FINT; 2496 if (sc->dc_flags & DC_TX_INTR_ALWAYS) 2497 sc->dc_ldata->dc_tx_list[cur].dc_ctl |= DC_TXCTL_FINT; 2498 if (sc->dc_flags & DC_TX_USE_TX_INTR && sc->dc_cdata.dc_tx_cnt > 64) 2499 sc->dc_ldata->dc_tx_list[cur].dc_ctl |= DC_TXCTL_FINT; 2500 sc->dc_ldata->dc_tx_list[*txidx].dc_status = DC_TXSTAT_OWN; 2501 *txidx = frag; 2502 2503 return(0); 2504 } 2505 2506 /* 2507 * Coalesce an mbuf chain into a single mbuf cluster buffer. 2508 * Needed for some really badly behaved chips that just can't 2509 * do scatter/gather correctly. 2510 */ 2511 static int dc_coal(sc, m_head) 2512 struct dc_softc *sc; 2513 struct mbuf **m_head; 2514 { 2515 struct mbuf *m_new, *m; 2516 2517 m = *m_head; 2518 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 2519 if (m_new == NULL) { 2520 printf("dc%d: no memory for tx list", sc->dc_unit); 2521 return(ENOBUFS); 2522 } 2523 if (m->m_pkthdr.len > MHLEN) { 2524 MCLGET(m_new, M_DONTWAIT); 2525 if (!(m_new->m_flags & M_EXT)) { 2526 m_freem(m_new); 2527 printf("dc%d: no memory for tx list", sc->dc_unit); 2528 return(ENOBUFS); 2529 } 2530 } 2531 m_copydata(m, 0, m->m_pkthdr.len, mtod(m_new, caddr_t)); 2532 m_new->m_pkthdr.len = m_new->m_len = m->m_pkthdr.len; 2533 m_freem(m); 2534 *m_head = m_new; 2535 2536 return(0); 2537 } 2538 2539 /* 2540 * Main transmit routine. To avoid having to do mbuf copies, we put pointers 2541 * to the mbuf data regions directly in the transmit lists. We also save a 2542 * copy of the pointers since the transmit list fragment pointers are 2543 * physical addresses. 2544 */ 2545 2546 static void dc_start(ifp) 2547 struct ifnet *ifp; 2548 { 2549 struct dc_softc *sc; 2550 struct mbuf *m_head = NULL; 2551 int idx; 2552 2553 sc = ifp->if_softc; 2554 2555 if (!sc->dc_link) 2556 return; 2557 2558 if (ifp->if_flags & IFF_OACTIVE) 2559 return; 2560 2561 idx = sc->dc_cdata.dc_tx_prod; 2562 2563 while(sc->dc_cdata.dc_tx_chain[idx] == NULL) { 2564 IF_DEQUEUE(&ifp->if_snd, m_head); 2565 if (m_head == NULL) 2566 break; 2567 2568 if (sc->dc_flags & DC_TX_COALESCE) { 2569 if (dc_coal(sc, &m_head)) { 2570 IF_PREPEND(&ifp->if_snd, m_head); 2571 ifp->if_flags |= IFF_OACTIVE; 2572 break; 2573 } 2574 } 2575 2576 if (dc_encap(sc, m_head, &idx)) { 2577 IF_PREPEND(&ifp->if_snd, m_head); 2578 ifp->if_flags |= IFF_OACTIVE; 2579 break; 2580 } 2581 2582 /* 2583 * If there's a BPF listener, bounce a copy of this frame 2584 * to him. 2585 */ 2586 if (ifp->if_bpf) 2587 bpf_mtap(ifp, m_head); 2588 } 2589 2590 /* Transmit */ 2591 sc->dc_cdata.dc_tx_prod = idx; 2592 if (!(sc->dc_flags & DC_TX_POLL)) 2593 CSR_WRITE_4(sc, DC_TXSTART, 0xFFFFFFFF); 2594 2595 /* 2596 * Set a timeout in case the chip goes out to lunch. 2597 */ 2598 ifp->if_timer = 5; 2599 2600 return; 2601 } 2602 2603 static void dc_init(xsc) 2604 void *xsc; 2605 { 2606 struct dc_softc *sc = xsc; 2607 struct ifnet *ifp = &sc->arpcom.ac_if; 2608 struct mii_data *mii; 2609 int s; 2610 2611 s = splimp(); 2612 2613 mii = device_get_softc(sc->dc_miibus); 2614 2615 /* 2616 * Cancel pending I/O and free all RX/TX buffers. 2617 */ 2618 dc_stop(sc); 2619 dc_reset(sc); 2620 2621 /* 2622 * Set cache alignment and burst length. 2623 */ 2624 if (DC_IS_ASIX(sc) || DC_IS_DAVICOM(sc)) 2625 CSR_WRITE_4(sc, DC_BUSCTL, 0); 2626 else 2627 CSR_WRITE_4(sc, DC_BUSCTL, DC_BUSCTL_MRME|DC_BUSCTL_MRLE); 2628 if (DC_IS_DAVICOM(sc) || DC_IS_INTEL(sc)) { 2629 DC_SETBIT(sc, DC_BUSCTL, DC_BURSTLEN_USECA); 2630 } else { 2631 DC_SETBIT(sc, DC_BUSCTL, DC_BURSTLEN_16LONG); 2632 } 2633 if (sc->dc_flags & DC_TX_POLL) 2634 DC_SETBIT(sc, DC_BUSCTL, DC_TXPOLL_1); 2635 switch(sc->dc_cachesize) { 2636 case 32: 2637 DC_SETBIT(sc, DC_BUSCTL, DC_CACHEALIGN_32LONG); 2638 break; 2639 case 16: 2640 DC_SETBIT(sc, DC_BUSCTL, DC_CACHEALIGN_16LONG); 2641 break; 2642 case 8: 2643 DC_SETBIT(sc, DC_BUSCTL, DC_CACHEALIGN_8LONG); 2644 break; 2645 case 0: 2646 default: 2647 DC_SETBIT(sc, DC_BUSCTL, DC_CACHEALIGN_NONE); 2648 break; 2649 } 2650 2651 if (sc->dc_flags & DC_TX_STORENFWD) 2652 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_STORENFWD); 2653 else { 2654 if (sc->dc_txthresh == DC_TXTHRESH_160BYTES) { 2655 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_STORENFWD); 2656 } else { 2657 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_STORENFWD); 2658 DC_SETBIT(sc, DC_NETCFG, sc->dc_txthresh); 2659 } 2660 } 2661 2662 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_NO_RXCRC); 2663 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_TX_BACKOFF); 2664 2665 if (DC_IS_MACRONIX(sc) || DC_IS_PNICII(sc)) { 2666 /* 2667 * The app notes for the 98713 and 98715A say that 2668 * in order to have the chips operate properly, a magic 2669 * number must be written to CSR16. Macronix does not 2670 * document the meaning of these bits so there's no way 2671 * to know exactly what they do. The 98713 has a magic 2672 * number all its own; the rest all use a different one. 2673 */ 2674 DC_CLRBIT(sc, DC_MX_MAGICPACKET, 0xFFFF0000); 2675 if (sc->dc_type == DC_TYPE_98713) 2676 DC_SETBIT(sc, DC_MX_MAGICPACKET, DC_MX_MAGIC_98713); 2677 else 2678 DC_SETBIT(sc, DC_MX_MAGICPACKET, DC_MX_MAGIC_98715); 2679 } 2680 2681 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_TX_THRESH); 2682 DC_SETBIT(sc, DC_NETCFG, DC_TXTHRESH_72BYTES); 2683 2684 /* Init circular RX list. */ 2685 if (dc_list_rx_init(sc) == ENOBUFS) { 2686 printf("dc%d: initialization failed: no " 2687 "memory for rx buffers\n", sc->dc_unit); 2688 dc_stop(sc); 2689 (void)splx(s); 2690 return; 2691 } 2692 2693 /* 2694 * Init tx descriptors. 2695 */ 2696 dc_list_tx_init(sc); 2697 2698 /* 2699 * Load the address of the RX list. 2700 */ 2701 CSR_WRITE_4(sc, DC_RXADDR, vtophys(&sc->dc_ldata->dc_rx_list[0])); 2702 CSR_WRITE_4(sc, DC_TXADDR, vtophys(&sc->dc_ldata->dc_tx_list[0])); 2703 2704 /* 2705 * Enable interrupts. 2706 */ 2707 CSR_WRITE_4(sc, DC_IMR, DC_INTRS); 2708 CSR_WRITE_4(sc, DC_ISR, 0xFFFFFFFF); 2709 2710 /* Enable transmitter. */ 2711 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_TX_ON); 2712 2713 /* 2714 * Load the RX/multicast filter. We do this sort of late 2715 * because the filter programming scheme on the 21143 and 2716 * some clones requires DMAing a setup frame via the TX 2717 * engine, and we need the transmitter enabled for that. 2718 */ 2719 dc_setfilt(sc); 2720 2721 /* Enable receiver. */ 2722 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_ON); 2723 CSR_WRITE_4(sc, DC_RXSTART, 0xFFFFFFFF); 2724 2725 mii_mediachg(mii); 2726 dc_setcfg(sc, sc->dc_if_media); 2727 2728 ifp->if_flags |= IFF_RUNNING; 2729 ifp->if_flags &= ~IFF_OACTIVE; 2730 2731 (void)splx(s); 2732 2733 if (sc->dc_flags & DC_21143_NWAY) 2734 sc->dc_stat_ch = timeout(dc_tick, sc, hz/10); 2735 else 2736 sc->dc_stat_ch = timeout(dc_tick, sc, hz); 2737 2738 #ifdef __alpha__ 2739 if(sc->dc_srm_media) { 2740 struct ifreq ifr; 2741 2742 ifr.ifr_media = sc->dc_srm_media; 2743 ifmedia_ioctl(ifp, &ifr, &mii->mii_media, SIOCSIFMEDIA); 2744 sc->dc_srm_media = 0; 2745 } 2746 #endif 2747 return; 2748 } 2749 2750 /* 2751 * Set media options. 2752 */ 2753 static int dc_ifmedia_upd(ifp) 2754 struct ifnet *ifp; 2755 { 2756 struct dc_softc *sc; 2757 struct mii_data *mii; 2758 struct ifmedia *ifm; 2759 2760 sc = ifp->if_softc; 2761 mii = device_get_softc(sc->dc_miibus); 2762 mii_mediachg(mii); 2763 ifm = &mii->mii_media; 2764 2765 if (DC_IS_DAVICOM(sc) && 2766 IFM_SUBTYPE(ifm->ifm_media) == IFM_homePNA) 2767 dc_setcfg(sc, ifm->ifm_media); 2768 else 2769 sc->dc_link = 0; 2770 2771 return(0); 2772 } 2773 2774 /* 2775 * Report current media status. 2776 */ 2777 static void dc_ifmedia_sts(ifp, ifmr) 2778 struct ifnet *ifp; 2779 struct ifmediareq *ifmr; 2780 { 2781 struct dc_softc *sc; 2782 struct mii_data *mii; 2783 struct ifmedia *ifm; 2784 2785 sc = ifp->if_softc; 2786 mii = device_get_softc(sc->dc_miibus); 2787 mii_pollstat(mii); 2788 ifm = &mii->mii_media; 2789 if (DC_IS_DAVICOM(sc)) { 2790 if (IFM_SUBTYPE(ifm->ifm_media) == IFM_homePNA) { 2791 ifmr->ifm_active = ifm->ifm_media; 2792 ifmr->ifm_status = 0; 2793 return; 2794 } 2795 } 2796 ifmr->ifm_active = mii->mii_media_active; 2797 ifmr->ifm_status = mii->mii_media_status; 2798 2799 return; 2800 } 2801 2802 static int dc_ioctl(ifp, command, data) 2803 struct ifnet *ifp; 2804 u_long command; 2805 caddr_t data; 2806 { 2807 struct dc_softc *sc = ifp->if_softc; 2808 struct ifreq *ifr = (struct ifreq *) data; 2809 struct mii_data *mii; 2810 int s, error = 0; 2811 2812 s = splimp(); 2813 2814 switch(command) { 2815 case SIOCSIFADDR: 2816 case SIOCGIFADDR: 2817 case SIOCSIFMTU: 2818 error = ether_ioctl(ifp, command, data); 2819 break; 2820 case SIOCSIFFLAGS: 2821 if (ifp->if_flags & IFF_UP) { 2822 if (ifp->if_flags & IFF_RUNNING && 2823 ifp->if_flags & IFF_PROMISC && 2824 !(sc->dc_if_flags & IFF_PROMISC)) { 2825 dc_setfilt(sc); 2826 } else if (ifp->if_flags & IFF_RUNNING && 2827 !(ifp->if_flags & IFF_PROMISC) && 2828 sc->dc_if_flags & IFF_PROMISC) { 2829 dc_setfilt(sc); 2830 } else if (!(ifp->if_flags & IFF_RUNNING)) { 2831 sc->dc_txthresh = 0; 2832 dc_init(sc); 2833 } 2834 } else { 2835 if (ifp->if_flags & IFF_RUNNING) 2836 dc_stop(sc); 2837 } 2838 sc->dc_if_flags = ifp->if_flags; 2839 error = 0; 2840 break; 2841 case SIOCADDMULTI: 2842 case SIOCDELMULTI: 2843 dc_setfilt(sc); 2844 error = 0; 2845 break; 2846 case SIOCGIFMEDIA: 2847 case SIOCSIFMEDIA: 2848 mii = device_get_softc(sc->dc_miibus); 2849 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 2850 #ifdef __alpha__ 2851 if (sc->dc_srm_media) 2852 sc->dc_srm_media = 0; 2853 #endif 2854 break; 2855 default: 2856 error = EINVAL; 2857 break; 2858 } 2859 2860 (void)splx(s); 2861 2862 return(error); 2863 } 2864 2865 static void dc_watchdog(ifp) 2866 struct ifnet *ifp; 2867 { 2868 struct dc_softc *sc; 2869 2870 sc = ifp->if_softc; 2871 2872 ifp->if_oerrors++; 2873 printf("dc%d: watchdog timeout\n", sc->dc_unit); 2874 2875 dc_stop(sc); 2876 dc_reset(sc); 2877 dc_init(sc); 2878 2879 if (ifp->if_snd.ifq_head != NULL) 2880 dc_start(ifp); 2881 2882 return; 2883 } 2884 2885 /* 2886 * Stop the adapter and free any mbufs allocated to the 2887 * RX and TX lists. 2888 */ 2889 static void dc_stop(sc) 2890 struct dc_softc *sc; 2891 { 2892 register int i; 2893 struct ifnet *ifp; 2894 2895 ifp = &sc->arpcom.ac_if; 2896 ifp->if_timer = 0; 2897 2898 untimeout(dc_tick, sc, sc->dc_stat_ch); 2899 2900 DC_CLRBIT(sc, DC_NETCFG, (DC_NETCFG_RX_ON|DC_NETCFG_TX_ON)); 2901 CSR_WRITE_4(sc, DC_IMR, 0x00000000); 2902 CSR_WRITE_4(sc, DC_TXADDR, 0x00000000); 2903 CSR_WRITE_4(sc, DC_RXADDR, 0x00000000); 2904 sc->dc_link = 0; 2905 2906 /* 2907 * Free data in the RX lists. 2908 */ 2909 for (i = 0; i < DC_RX_LIST_CNT; i++) { 2910 if (sc->dc_cdata.dc_rx_chain[i] != NULL) { 2911 m_freem(sc->dc_cdata.dc_rx_chain[i]); 2912 sc->dc_cdata.dc_rx_chain[i] = NULL; 2913 } 2914 } 2915 bzero((char *)&sc->dc_ldata->dc_rx_list, 2916 sizeof(sc->dc_ldata->dc_rx_list)); 2917 2918 /* 2919 * Free the TX list buffers. 2920 */ 2921 for (i = 0; i < DC_TX_LIST_CNT; i++) { 2922 if (sc->dc_cdata.dc_tx_chain[i] != NULL) { 2923 if (sc->dc_ldata->dc_tx_list[i].dc_ctl & 2924 DC_TXCTL_SETUP) { 2925 sc->dc_cdata.dc_tx_chain[i] = NULL; 2926 continue; 2927 } 2928 m_freem(sc->dc_cdata.dc_tx_chain[i]); 2929 sc->dc_cdata.dc_tx_chain[i] = NULL; 2930 } 2931 } 2932 2933 bzero((char *)&sc->dc_ldata->dc_tx_list, 2934 sizeof(sc->dc_ldata->dc_tx_list)); 2935 2936 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 2937 2938 return; 2939 } 2940 2941 /* 2942 * Stop all chip I/O so that the kernel's probe routines don't 2943 * get confused by errant DMAs when rebooting. 2944 */ 2945 static void dc_shutdown(dev) 2946 device_t dev; 2947 { 2948 struct dc_softc *sc; 2949 2950 sc = device_get_softc(dev); 2951 2952 dc_stop(sc); 2953 2954 return; 2955 } 2956