1 /*- 2 * Copyright (c) 1997, 1998, 1999 3 * Bill Paul <wpaul@ee.columbia.edu>. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 3. All advertising materials mentioning features or use of this software 14 * must display the following acknowledgement: 15 * This product includes software developed by Bill Paul. 16 * 4. Neither the name of the author nor the names of any co-contributors 17 * may be used to endorse or promote products derived from this software 18 * without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30 * THE POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33 #include <sys/cdefs.h> 34 __FBSDID("$FreeBSD$"); 35 36 /* 37 * DEC "tulip" clone ethernet driver. Supports the DEC/Intel 21143 38 * series chips and several workalikes including the following: 39 * 40 * Macronix 98713/98715/98725/98727/98732 PMAC (www.macronix.com) 41 * Macronix/Lite-On 82c115 PNIC II (www.macronix.com) 42 * Lite-On 82c168/82c169 PNIC (www.litecom.com) 43 * ASIX Electronics AX88140A (www.asix.com.tw) 44 * ASIX Electronics AX88141 (www.asix.com.tw) 45 * ADMtek AL981 (www.admtek.com.tw) 46 * ADMtek AN985 (www.admtek.com.tw) 47 * Netgear FA511 (www.netgear.com) Appears to be rebadged ADMTek AN985 48 * Davicom DM9100, DM9102, DM9102A (www.davicom8.com) 49 * Accton EN1217 (www.accton.com) 50 * Xircom X3201 (www.xircom.com) 51 * Abocom FE2500 52 * Conexant LANfinity (www.conexant.com) 53 * 3Com OfficeConnect 10/100B 3CSOHO100B (www.3com.com) 54 * 55 * Datasheets for the 21143 are available at developer.intel.com. 56 * Datasheets for the clone parts can be found at their respective sites. 57 * (Except for the PNIC; see www.freebsd.org/~wpaul/PNIC/pnic.ps.gz.) 58 * The PNIC II is essentially a Macronix 98715A chip; the only difference 59 * worth noting is that its multicast hash table is only 128 bits wide 60 * instead of 512. 61 * 62 * Written by Bill Paul <wpaul@ee.columbia.edu> 63 * Electrical Engineering Department 64 * Columbia University, New York City 65 */ 66 /* 67 * The Intel 21143 is the successor to the DEC 21140. It is basically 68 * the same as the 21140 but with a few new features. The 21143 supports 69 * three kinds of media attachments: 70 * 71 * o MII port, for 10Mbps and 100Mbps support and NWAY 72 * autonegotiation provided by an external PHY. 73 * o SYM port, for symbol mode 100Mbps support. 74 * o 10baseT port. 75 * o AUI/BNC port. 76 * 77 * The 100Mbps SYM port and 10baseT port can be used together in 78 * combination with the internal NWAY support to create a 10/100 79 * autosensing configuration. 80 * 81 * Note that not all tulip workalikes are handled in this driver: we only 82 * deal with those which are relatively well behaved. The Winbond is 83 * handled separately due to its different register offsets and the 84 * special handling needed for its various bugs. The PNIC is handled 85 * here, but I'm not thrilled about it. 86 * 87 * All of the workalike chips use some form of MII transceiver support 88 * with the exception of the Macronix chips, which also have a SYM port. 89 * The ASIX AX88140A is also documented to have a SYM port, but all 90 * the cards I've seen use an MII transceiver, probably because the 91 * AX88140A doesn't support internal NWAY. 92 */ 93 94 #ifdef HAVE_KERNEL_OPTION_HEADERS 95 #include "opt_device_polling.h" 96 #endif 97 98 #include <sys/param.h> 99 #include <sys/endian.h> 100 #include <sys/systm.h> 101 #include <sys/sockio.h> 102 #include <sys/mbuf.h> 103 #include <sys/malloc.h> 104 #include <sys/kernel.h> 105 #include <sys/module.h> 106 #include <sys/socket.h> 107 108 #include <net/if.h> 109 #include <net/if_arp.h> 110 #include <net/ethernet.h> 111 #include <net/if_dl.h> 112 #include <net/if_media.h> 113 #include <net/if_types.h> 114 #include <net/if_vlan_var.h> 115 116 #include <net/bpf.h> 117 118 #include <machine/bus.h> 119 #include <machine/resource.h> 120 #include <sys/bus.h> 121 #include <sys/rman.h> 122 123 #include <dev/mii/mii.h> 124 #include <dev/mii/miivar.h> 125 126 #include <dev/pci/pcireg.h> 127 #include <dev/pci/pcivar.h> 128 129 #define DC_USEIOSPACE 130 131 #include <dev/dc/if_dcreg.h> 132 133 #ifdef __sparc64__ 134 #include <dev/ofw/openfirm.h> 135 #include <machine/ofw_machdep.h> 136 #endif 137 138 MODULE_DEPEND(dc, pci, 1, 1, 1); 139 MODULE_DEPEND(dc, ether, 1, 1, 1); 140 MODULE_DEPEND(dc, miibus, 1, 1, 1); 141 142 /* 143 * "device miibus" is required in kernel config. See GENERIC if you get 144 * errors here. 145 */ 146 #include "miibus_if.h" 147 148 /* 149 * Various supported device vendors/types and their names. 150 */ 151 static struct dc_type dc_devs[] = { 152 { DC_DEVID(DC_VENDORID_DEC, DC_DEVICEID_21143), 0, 153 "Intel 21143 10/100BaseTX" }, 154 { DC_DEVID(DC_VENDORID_DAVICOM, DC_DEVICEID_DM9009), 0, 155 "Davicom DM9009 10/100BaseTX" }, 156 { DC_DEVID(DC_VENDORID_DAVICOM, DC_DEVICEID_DM9100), 0, 157 "Davicom DM9100 10/100BaseTX" }, 158 { DC_DEVID(DC_VENDORID_DAVICOM, DC_DEVICEID_DM9102), DC_REVISION_DM9102A, 159 "Davicom DM9102A 10/100BaseTX" }, 160 { DC_DEVID(DC_VENDORID_DAVICOM, DC_DEVICEID_DM9102), 0, 161 "Davicom DM9102 10/100BaseTX" }, 162 { DC_DEVID(DC_VENDORID_ADMTEK, DC_DEVICEID_AL981), 0, 163 "ADMtek AL981 10/100BaseTX" }, 164 { DC_DEVID(DC_VENDORID_ADMTEK, DC_DEVICEID_AN985), 0, 165 "ADMtek AN985 10/100BaseTX" }, 166 { DC_DEVID(DC_VENDORID_ADMTEK, DC_DEVICEID_ADM9511), 0, 167 "ADMtek ADM9511 10/100BaseTX" }, 168 { DC_DEVID(DC_VENDORID_ADMTEK, DC_DEVICEID_ADM9513), 0, 169 "ADMtek ADM9513 10/100BaseTX" }, 170 { DC_DEVID(DC_VENDORID_ADMTEK, DC_DEVICEID_FA511), 0, 171 "Netgear FA511 10/100BaseTX" }, 172 { DC_DEVID(DC_VENDORID_ASIX, DC_DEVICEID_AX88140A), DC_REVISION_88141, 173 "ASIX AX88141 10/100BaseTX" }, 174 { DC_DEVID(DC_VENDORID_ASIX, DC_DEVICEID_AX88140A), 0, 175 "ASIX AX88140A 10/100BaseTX" }, 176 { DC_DEVID(DC_VENDORID_MX, DC_DEVICEID_98713), DC_REVISION_98713A, 177 "Macronix 98713A 10/100BaseTX" }, 178 { DC_DEVID(DC_VENDORID_MX, DC_DEVICEID_98713), 0, 179 "Macronix 98713 10/100BaseTX" }, 180 { DC_DEVID(DC_VENDORID_CP, DC_DEVICEID_98713_CP), DC_REVISION_98713A, 181 "Compex RL100-TX 10/100BaseTX" }, 182 { DC_DEVID(DC_VENDORID_CP, DC_DEVICEID_98713_CP), 0, 183 "Compex RL100-TX 10/100BaseTX" }, 184 { DC_DEVID(DC_VENDORID_MX, DC_DEVICEID_987x5), DC_REVISION_98725, 185 "Macronix 98725 10/100BaseTX" }, 186 { DC_DEVID(DC_VENDORID_MX, DC_DEVICEID_987x5), DC_REVISION_98715AEC_C, 187 "Macronix 98715AEC-C 10/100BaseTX" }, 188 { DC_DEVID(DC_VENDORID_MX, DC_DEVICEID_987x5), 0, 189 "Macronix 98715/98715A 10/100BaseTX" }, 190 { DC_DEVID(DC_VENDORID_MX, DC_DEVICEID_98727), 0, 191 "Macronix 98727/98732 10/100BaseTX" }, 192 { DC_DEVID(DC_VENDORID_LO, DC_DEVICEID_82C115), 0, 193 "LC82C115 PNIC II 10/100BaseTX" }, 194 { DC_DEVID(DC_VENDORID_LO, DC_DEVICEID_82C168), DC_REVISION_82C169, 195 "82c169 PNIC 10/100BaseTX" }, 196 { DC_DEVID(DC_VENDORID_LO, DC_DEVICEID_82C168), 0, 197 "82c168 PNIC 10/100BaseTX" }, 198 { DC_DEVID(DC_VENDORID_ACCTON, DC_DEVICEID_EN1217), 0, 199 "Accton EN1217 10/100BaseTX" }, 200 { DC_DEVID(DC_VENDORID_ACCTON, DC_DEVICEID_EN2242), 0, 201 "Accton EN2242 MiniPCI 10/100BaseTX" }, 202 { DC_DEVID(DC_VENDORID_XIRCOM, DC_DEVICEID_X3201), 0, 203 "Xircom X3201 10/100BaseTX" }, 204 { DC_DEVID(DC_VENDORID_DLINK, DC_DEVICEID_DRP32TXD), 0, 205 "Neteasy DRP-32TXD Cardbus 10/100" }, 206 { DC_DEVID(DC_VENDORID_ABOCOM, DC_DEVICEID_FE2500), 0, 207 "Abocom FE2500 10/100BaseTX" }, 208 { DC_DEVID(DC_VENDORID_ABOCOM, DC_DEVICEID_FE2500MX), 0, 209 "Abocom FE2500MX 10/100BaseTX" }, 210 { DC_DEVID(DC_VENDORID_CONEXANT, DC_DEVICEID_RS7112), 0, 211 "Conexant LANfinity MiniPCI 10/100BaseTX" }, 212 { DC_DEVID(DC_VENDORID_HAWKING, DC_DEVICEID_HAWKING_PN672TX), 0, 213 "Hawking CB102 CardBus 10/100" }, 214 { DC_DEVID(DC_VENDORID_PLANEX, DC_DEVICEID_FNW3602T), 0, 215 "PlaneX FNW-3602-T CardBus 10/100" }, 216 { DC_DEVID(DC_VENDORID_3COM, DC_DEVICEID_3CSOHOB), 0, 217 "3Com OfficeConnect 10/100B" }, 218 { DC_DEVID(DC_VENDORID_MICROSOFT, DC_DEVICEID_MSMN120), 0, 219 "Microsoft MN-120 CardBus 10/100" }, 220 { DC_DEVID(DC_VENDORID_MICROSOFT, DC_DEVICEID_MSMN130), 0, 221 "Microsoft MN-130 10/100" }, 222 { DC_DEVID(DC_VENDORID_LINKSYS, DC_DEVICEID_PCMPC200_AB08), 0, 223 "Linksys PCMPC200 CardBus 10/100" }, 224 { DC_DEVID(DC_VENDORID_LINKSYS, DC_DEVICEID_PCMPC200_AB09), 0, 225 "Linksys PCMPC200 CardBus 10/100" }, 226 { 0, 0, NULL } 227 }; 228 229 static int dc_probe(device_t); 230 static int dc_attach(device_t); 231 static int dc_detach(device_t); 232 static int dc_suspend(device_t); 233 static int dc_resume(device_t); 234 static struct dc_type *dc_devtype(device_t); 235 static int dc_newbuf(struct dc_softc *, int, int); 236 static int dc_encap(struct dc_softc *, struct mbuf **); 237 static void dc_pnic_rx_bug_war(struct dc_softc *, int); 238 static int dc_rx_resync(struct dc_softc *); 239 static void dc_rxeof(struct dc_softc *); 240 static void dc_txeof(struct dc_softc *); 241 static void dc_tick(void *); 242 static void dc_tx_underrun(struct dc_softc *); 243 static void dc_intr(void *); 244 static void dc_start(struct ifnet *); 245 static void dc_start_locked(struct ifnet *); 246 static int dc_ioctl(struct ifnet *, u_long, caddr_t); 247 static void dc_init(void *); 248 static void dc_init_locked(struct dc_softc *); 249 static void dc_stop(struct dc_softc *); 250 static void dc_watchdog(struct ifnet *); 251 static void dc_shutdown(device_t); 252 static int dc_ifmedia_upd(struct ifnet *); 253 static void dc_ifmedia_sts(struct ifnet *, struct ifmediareq *); 254 255 static void dc_delay(struct dc_softc *); 256 static void dc_eeprom_idle(struct dc_softc *); 257 static void dc_eeprom_putbyte(struct dc_softc *, int); 258 static void dc_eeprom_getword(struct dc_softc *, int, u_int16_t *); 259 static void dc_eeprom_getword_pnic(struct dc_softc *, int, u_int16_t *); 260 static void dc_eeprom_getword_xircom(struct dc_softc *, int, u_int16_t *); 261 static void dc_eeprom_width(struct dc_softc *); 262 static void dc_read_eeprom(struct dc_softc *, caddr_t, int, int, int); 263 264 static void dc_mii_writebit(struct dc_softc *, int); 265 static int dc_mii_readbit(struct dc_softc *); 266 static void dc_mii_sync(struct dc_softc *); 267 static void dc_mii_send(struct dc_softc *, u_int32_t, int); 268 static int dc_mii_readreg(struct dc_softc *, struct dc_mii_frame *); 269 static int dc_mii_writereg(struct dc_softc *, struct dc_mii_frame *); 270 static int dc_miibus_readreg(device_t, int, int); 271 static int dc_miibus_writereg(device_t, int, int, int); 272 static void dc_miibus_statchg(device_t); 273 static void dc_miibus_mediainit(device_t); 274 275 static void dc_setcfg(struct dc_softc *, int); 276 static uint32_t dc_mchash_le(struct dc_softc *, const uint8_t *); 277 static uint32_t dc_mchash_be(const uint8_t *); 278 static void dc_setfilt_21143(struct dc_softc *); 279 static void dc_setfilt_asix(struct dc_softc *); 280 static void dc_setfilt_admtek(struct dc_softc *); 281 static void dc_setfilt_xircom(struct dc_softc *); 282 283 static void dc_setfilt(struct dc_softc *); 284 285 static void dc_reset(struct dc_softc *); 286 static int dc_list_rx_init(struct dc_softc *); 287 static int dc_list_tx_init(struct dc_softc *); 288 289 static void dc_read_srom(struct dc_softc *, int); 290 static void dc_parse_21143_srom(struct dc_softc *); 291 static void dc_decode_leaf_sia(struct dc_softc *, struct dc_eblock_sia *); 292 static void dc_decode_leaf_mii(struct dc_softc *, struct dc_eblock_mii *); 293 static void dc_decode_leaf_sym(struct dc_softc *, struct dc_eblock_sym *); 294 static void dc_apply_fixup(struct dc_softc *, int); 295 296 static void dc_dma_map_txbuf(void *, bus_dma_segment_t *, int, bus_size_t, int); 297 static void dc_dma_map_rxbuf(void *, bus_dma_segment_t *, int, bus_size_t, int); 298 299 #ifdef DC_USEIOSPACE 300 #define DC_RES SYS_RES_IOPORT 301 #define DC_RID DC_PCI_CFBIO 302 #else 303 #define DC_RES SYS_RES_MEMORY 304 #define DC_RID DC_PCI_CFBMA 305 #endif 306 307 static device_method_t dc_methods[] = { 308 /* Device interface */ 309 DEVMETHOD(device_probe, dc_probe), 310 DEVMETHOD(device_attach, dc_attach), 311 DEVMETHOD(device_detach, dc_detach), 312 DEVMETHOD(device_suspend, dc_suspend), 313 DEVMETHOD(device_resume, dc_resume), 314 DEVMETHOD(device_shutdown, dc_shutdown), 315 316 /* bus interface */ 317 DEVMETHOD(bus_print_child, bus_generic_print_child), 318 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 319 320 /* MII interface */ 321 DEVMETHOD(miibus_readreg, dc_miibus_readreg), 322 DEVMETHOD(miibus_writereg, dc_miibus_writereg), 323 DEVMETHOD(miibus_statchg, dc_miibus_statchg), 324 DEVMETHOD(miibus_mediainit, dc_miibus_mediainit), 325 326 { 0, 0 } 327 }; 328 329 static driver_t dc_driver = { 330 "dc", 331 dc_methods, 332 sizeof(struct dc_softc) 333 }; 334 335 static devclass_t dc_devclass; 336 337 DRIVER_MODULE(dc, cardbus, dc_driver, dc_devclass, 0, 0); 338 DRIVER_MODULE(dc, pci, dc_driver, dc_devclass, 0, 0); 339 DRIVER_MODULE(miibus, dc, miibus_driver, miibus_devclass, 0, 0); 340 341 #define DC_SETBIT(sc, reg, x) \ 342 CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) | (x)) 343 344 #define DC_CLRBIT(sc, reg, x) \ 345 CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) & ~(x)) 346 347 #define SIO_SET(x) DC_SETBIT(sc, DC_SIO, (x)) 348 #define SIO_CLR(x) DC_CLRBIT(sc, DC_SIO, (x)) 349 350 static void 351 dc_delay(struct dc_softc *sc) 352 { 353 int idx; 354 355 for (idx = (300 / 33) + 1; idx > 0; idx--) 356 CSR_READ_4(sc, DC_BUSCTL); 357 } 358 359 static void 360 dc_eeprom_width(struct dc_softc *sc) 361 { 362 int i; 363 364 /* Force EEPROM to idle state. */ 365 dc_eeprom_idle(sc); 366 367 /* Enter EEPROM access mode. */ 368 CSR_WRITE_4(sc, DC_SIO, DC_SIO_EESEL); 369 dc_delay(sc); 370 DC_SETBIT(sc, DC_SIO, DC_SIO_ROMCTL_READ); 371 dc_delay(sc); 372 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); 373 dc_delay(sc); 374 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CS); 375 dc_delay(sc); 376 377 for (i = 3; i--;) { 378 if (6 & (1 << i)) 379 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_DATAIN); 380 else 381 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_DATAIN); 382 dc_delay(sc); 383 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CLK); 384 dc_delay(sc); 385 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); 386 dc_delay(sc); 387 } 388 389 for (i = 1; i <= 12; i++) { 390 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CLK); 391 dc_delay(sc); 392 if (!(CSR_READ_4(sc, DC_SIO) & DC_SIO_EE_DATAOUT)) { 393 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); 394 dc_delay(sc); 395 break; 396 } 397 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); 398 dc_delay(sc); 399 } 400 401 /* Turn off EEPROM access mode. */ 402 dc_eeprom_idle(sc); 403 404 if (i < 4 || i > 12) 405 sc->dc_romwidth = 6; 406 else 407 sc->dc_romwidth = i; 408 409 /* Enter EEPROM access mode. */ 410 CSR_WRITE_4(sc, DC_SIO, DC_SIO_EESEL); 411 dc_delay(sc); 412 DC_SETBIT(sc, DC_SIO, DC_SIO_ROMCTL_READ); 413 dc_delay(sc); 414 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); 415 dc_delay(sc); 416 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CS); 417 dc_delay(sc); 418 419 /* Turn off EEPROM access mode. */ 420 dc_eeprom_idle(sc); 421 } 422 423 static void 424 dc_eeprom_idle(struct dc_softc *sc) 425 { 426 int i; 427 428 CSR_WRITE_4(sc, DC_SIO, DC_SIO_EESEL); 429 dc_delay(sc); 430 DC_SETBIT(sc, DC_SIO, DC_SIO_ROMCTL_READ); 431 dc_delay(sc); 432 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); 433 dc_delay(sc); 434 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CS); 435 dc_delay(sc); 436 437 for (i = 0; i < 25; i++) { 438 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); 439 dc_delay(sc); 440 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CLK); 441 dc_delay(sc); 442 } 443 444 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); 445 dc_delay(sc); 446 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CS); 447 dc_delay(sc); 448 CSR_WRITE_4(sc, DC_SIO, 0x00000000); 449 } 450 451 /* 452 * Send a read command and address to the EEPROM, check for ACK. 453 */ 454 static void 455 dc_eeprom_putbyte(struct dc_softc *sc, int addr) 456 { 457 int d, i; 458 459 d = DC_EECMD_READ >> 6; 460 for (i = 3; i--; ) { 461 if (d & (1 << i)) 462 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_DATAIN); 463 else 464 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_DATAIN); 465 dc_delay(sc); 466 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CLK); 467 dc_delay(sc); 468 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); 469 dc_delay(sc); 470 } 471 472 /* 473 * Feed in each bit and strobe the clock. 474 */ 475 for (i = sc->dc_romwidth; i--;) { 476 if (addr & (1 << i)) { 477 SIO_SET(DC_SIO_EE_DATAIN); 478 } else { 479 SIO_CLR(DC_SIO_EE_DATAIN); 480 } 481 dc_delay(sc); 482 SIO_SET(DC_SIO_EE_CLK); 483 dc_delay(sc); 484 SIO_CLR(DC_SIO_EE_CLK); 485 dc_delay(sc); 486 } 487 } 488 489 /* 490 * Read a word of data stored in the EEPROM at address 'addr.' 491 * The PNIC 82c168/82c169 has its own non-standard way to read 492 * the EEPROM. 493 */ 494 static void 495 dc_eeprom_getword_pnic(struct dc_softc *sc, int addr, u_int16_t *dest) 496 { 497 int i; 498 u_int32_t r; 499 500 CSR_WRITE_4(sc, DC_PN_SIOCTL, DC_PN_EEOPCODE_READ | addr); 501 502 for (i = 0; i < DC_TIMEOUT; i++) { 503 DELAY(1); 504 r = CSR_READ_4(sc, DC_SIO); 505 if (!(r & DC_PN_SIOCTL_BUSY)) { 506 *dest = (u_int16_t)(r & 0xFFFF); 507 return; 508 } 509 } 510 } 511 512 /* 513 * Read a word of data stored in the EEPROM at address 'addr.' 514 * The Xircom X3201 has its own non-standard way to read 515 * the EEPROM, too. 516 */ 517 static void 518 dc_eeprom_getword_xircom(struct dc_softc *sc, int addr, u_int16_t *dest) 519 { 520 521 SIO_SET(DC_SIO_ROMSEL | DC_SIO_ROMCTL_READ); 522 523 addr *= 2; 524 CSR_WRITE_4(sc, DC_ROM, addr | 0x160); 525 *dest = (u_int16_t)CSR_READ_4(sc, DC_SIO) & 0xff; 526 addr += 1; 527 CSR_WRITE_4(sc, DC_ROM, addr | 0x160); 528 *dest |= ((u_int16_t)CSR_READ_4(sc, DC_SIO) & 0xff) << 8; 529 530 SIO_CLR(DC_SIO_ROMSEL | DC_SIO_ROMCTL_READ); 531 } 532 533 /* 534 * Read a word of data stored in the EEPROM at address 'addr.' 535 */ 536 static void 537 dc_eeprom_getword(struct dc_softc *sc, int addr, u_int16_t *dest) 538 { 539 int i; 540 u_int16_t word = 0; 541 542 /* Force EEPROM to idle state. */ 543 dc_eeprom_idle(sc); 544 545 /* Enter EEPROM access mode. */ 546 CSR_WRITE_4(sc, DC_SIO, DC_SIO_EESEL); 547 dc_delay(sc); 548 DC_SETBIT(sc, DC_SIO, DC_SIO_ROMCTL_READ); 549 dc_delay(sc); 550 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); 551 dc_delay(sc); 552 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CS); 553 dc_delay(sc); 554 555 /* 556 * Send address of word we want to read. 557 */ 558 dc_eeprom_putbyte(sc, addr); 559 560 /* 561 * Start reading bits from EEPROM. 562 */ 563 for (i = 0x8000; i; i >>= 1) { 564 SIO_SET(DC_SIO_EE_CLK); 565 dc_delay(sc); 566 if (CSR_READ_4(sc, DC_SIO) & DC_SIO_EE_DATAOUT) 567 word |= i; 568 dc_delay(sc); 569 SIO_CLR(DC_SIO_EE_CLK); 570 dc_delay(sc); 571 } 572 573 /* Turn off EEPROM access mode. */ 574 dc_eeprom_idle(sc); 575 576 *dest = word; 577 } 578 579 /* 580 * Read a sequence of words from the EEPROM. 581 */ 582 static void 583 dc_read_eeprom(struct dc_softc *sc, caddr_t dest, int off, int cnt, int be) 584 { 585 int i; 586 u_int16_t word = 0, *ptr; 587 588 for (i = 0; i < cnt; i++) { 589 if (DC_IS_PNIC(sc)) 590 dc_eeprom_getword_pnic(sc, off + i, &word); 591 else if (DC_IS_XIRCOM(sc)) 592 dc_eeprom_getword_xircom(sc, off + i, &word); 593 else 594 dc_eeprom_getword(sc, off + i, &word); 595 ptr = (u_int16_t *)(dest + (i * 2)); 596 if (be) 597 *ptr = be16toh(word); 598 else 599 *ptr = le16toh(word); 600 } 601 } 602 603 /* 604 * The following two routines are taken from the Macronix 98713 605 * Application Notes pp.19-21. 606 */ 607 /* 608 * Write a bit to the MII bus. 609 */ 610 static void 611 dc_mii_writebit(struct dc_softc *sc, int bit) 612 { 613 614 if (bit) 615 CSR_WRITE_4(sc, DC_SIO, 616 DC_SIO_ROMCTL_WRITE | DC_SIO_MII_DATAOUT); 617 else 618 CSR_WRITE_4(sc, DC_SIO, DC_SIO_ROMCTL_WRITE); 619 620 DC_SETBIT(sc, DC_SIO, DC_SIO_MII_CLK); 621 DC_CLRBIT(sc, DC_SIO, DC_SIO_MII_CLK); 622 } 623 624 /* 625 * Read a bit from the MII bus. 626 */ 627 static int 628 dc_mii_readbit(struct dc_softc *sc) 629 { 630 631 CSR_WRITE_4(sc, DC_SIO, DC_SIO_ROMCTL_READ | DC_SIO_MII_DIR); 632 CSR_READ_4(sc, DC_SIO); 633 DC_SETBIT(sc, DC_SIO, DC_SIO_MII_CLK); 634 DC_CLRBIT(sc, DC_SIO, DC_SIO_MII_CLK); 635 if (CSR_READ_4(sc, DC_SIO) & DC_SIO_MII_DATAIN) 636 return (1); 637 638 return (0); 639 } 640 641 /* 642 * Sync the PHYs by setting data bit and strobing the clock 32 times. 643 */ 644 static void 645 dc_mii_sync(struct dc_softc *sc) 646 { 647 int i; 648 649 CSR_WRITE_4(sc, DC_SIO, DC_SIO_ROMCTL_WRITE); 650 651 for (i = 0; i < 32; i++) 652 dc_mii_writebit(sc, 1); 653 } 654 655 /* 656 * Clock a series of bits through the MII. 657 */ 658 static void 659 dc_mii_send(struct dc_softc *sc, u_int32_t bits, int cnt) 660 { 661 int i; 662 663 for (i = (0x1 << (cnt - 1)); i; i >>= 1) 664 dc_mii_writebit(sc, bits & i); 665 } 666 667 /* 668 * Read an PHY register through the MII. 669 */ 670 static int 671 dc_mii_readreg(struct dc_softc *sc, struct dc_mii_frame *frame) 672 { 673 int i, ack; 674 675 /* 676 * Set up frame for RX. 677 */ 678 frame->mii_stdelim = DC_MII_STARTDELIM; 679 frame->mii_opcode = DC_MII_READOP; 680 frame->mii_turnaround = 0; 681 frame->mii_data = 0; 682 683 /* 684 * Sync the PHYs. 685 */ 686 dc_mii_sync(sc); 687 688 /* 689 * Send command/address info. 690 */ 691 dc_mii_send(sc, frame->mii_stdelim, 2); 692 dc_mii_send(sc, frame->mii_opcode, 2); 693 dc_mii_send(sc, frame->mii_phyaddr, 5); 694 dc_mii_send(sc, frame->mii_regaddr, 5); 695 696 #ifdef notdef 697 /* Idle bit */ 698 dc_mii_writebit(sc, 1); 699 dc_mii_writebit(sc, 0); 700 #endif 701 702 /* Check for ack. */ 703 ack = dc_mii_readbit(sc); 704 705 /* 706 * Now try reading data bits. If the ack failed, we still 707 * need to clock through 16 cycles to keep the PHY(s) in sync. 708 */ 709 if (ack) { 710 for (i = 0; i < 16; i++) 711 dc_mii_readbit(sc); 712 goto fail; 713 } 714 715 for (i = 0x8000; i; i >>= 1) { 716 if (!ack) { 717 if (dc_mii_readbit(sc)) 718 frame->mii_data |= i; 719 } 720 } 721 722 fail: 723 724 dc_mii_writebit(sc, 0); 725 dc_mii_writebit(sc, 0); 726 727 if (ack) 728 return (1); 729 return (0); 730 } 731 732 /* 733 * Write to a PHY register through the MII. 734 */ 735 static int 736 dc_mii_writereg(struct dc_softc *sc, struct dc_mii_frame *frame) 737 { 738 739 /* 740 * Set up frame for TX. 741 */ 742 743 frame->mii_stdelim = DC_MII_STARTDELIM; 744 frame->mii_opcode = DC_MII_WRITEOP; 745 frame->mii_turnaround = DC_MII_TURNAROUND; 746 747 /* 748 * Sync the PHYs. 749 */ 750 dc_mii_sync(sc); 751 752 dc_mii_send(sc, frame->mii_stdelim, 2); 753 dc_mii_send(sc, frame->mii_opcode, 2); 754 dc_mii_send(sc, frame->mii_phyaddr, 5); 755 dc_mii_send(sc, frame->mii_regaddr, 5); 756 dc_mii_send(sc, frame->mii_turnaround, 2); 757 dc_mii_send(sc, frame->mii_data, 16); 758 759 /* Idle bit. */ 760 dc_mii_writebit(sc, 0); 761 dc_mii_writebit(sc, 0); 762 763 return (0); 764 } 765 766 static int 767 dc_miibus_readreg(device_t dev, int phy, int reg) 768 { 769 struct dc_mii_frame frame; 770 struct dc_softc *sc; 771 int i, rval, phy_reg = 0; 772 773 sc = device_get_softc(dev); 774 bzero(&frame, sizeof(frame)); 775 776 /* 777 * Note: both the AL981 and AN985 have internal PHYs, 778 * however the AL981 provides direct access to the PHY 779 * registers while the AN985 uses a serial MII interface. 780 * The AN985's MII interface is also buggy in that you 781 * can read from any MII address (0 to 31), but only address 1 782 * behaves normally. To deal with both cases, we pretend 783 * that the PHY is at MII address 1. 784 */ 785 if (DC_IS_ADMTEK(sc) && phy != DC_ADMTEK_PHYADDR) 786 return (0); 787 788 /* 789 * Note: the ukphy probes of the RS7112 report a PHY at 790 * MII address 0 (possibly HomePNA?) and 1 (ethernet) 791 * so we only respond to correct one. 792 */ 793 if (DC_IS_CONEXANT(sc) && phy != DC_CONEXANT_PHYADDR) 794 return (0); 795 796 if (sc->dc_pmode != DC_PMODE_MII) { 797 if (phy == (MII_NPHY - 1)) { 798 switch (reg) { 799 case MII_BMSR: 800 /* 801 * Fake something to make the probe 802 * code think there's a PHY here. 803 */ 804 return (BMSR_MEDIAMASK); 805 break; 806 case MII_PHYIDR1: 807 if (DC_IS_PNIC(sc)) 808 return (DC_VENDORID_LO); 809 return (DC_VENDORID_DEC); 810 break; 811 case MII_PHYIDR2: 812 if (DC_IS_PNIC(sc)) 813 return (DC_DEVICEID_82C168); 814 return (DC_DEVICEID_21143); 815 break; 816 default: 817 return (0); 818 break; 819 } 820 } else 821 return (0); 822 } 823 824 if (DC_IS_PNIC(sc)) { 825 CSR_WRITE_4(sc, DC_PN_MII, DC_PN_MIIOPCODE_READ | 826 (phy << 23) | (reg << 18)); 827 for (i = 0; i < DC_TIMEOUT; i++) { 828 DELAY(1); 829 rval = CSR_READ_4(sc, DC_PN_MII); 830 if (!(rval & DC_PN_MII_BUSY)) { 831 rval &= 0xFFFF; 832 return (rval == 0xFFFF ? 0 : rval); 833 } 834 } 835 return (0); 836 } 837 838 if (DC_IS_COMET(sc)) { 839 switch (reg) { 840 case MII_BMCR: 841 phy_reg = DC_AL_BMCR; 842 break; 843 case MII_BMSR: 844 phy_reg = DC_AL_BMSR; 845 break; 846 case MII_PHYIDR1: 847 phy_reg = DC_AL_VENID; 848 break; 849 case MII_PHYIDR2: 850 phy_reg = DC_AL_DEVID; 851 break; 852 case MII_ANAR: 853 phy_reg = DC_AL_ANAR; 854 break; 855 case MII_ANLPAR: 856 phy_reg = DC_AL_LPAR; 857 break; 858 case MII_ANER: 859 phy_reg = DC_AL_ANER; 860 break; 861 default: 862 device_printf(dev, "phy_read: bad phy register %x\n", 863 reg); 864 return (0); 865 break; 866 } 867 868 rval = CSR_READ_4(sc, phy_reg) & 0x0000FFFF; 869 870 if (rval == 0xFFFF) 871 return (0); 872 return (rval); 873 } 874 875 frame.mii_phyaddr = phy; 876 frame.mii_regaddr = reg; 877 if (sc->dc_type == DC_TYPE_98713) { 878 phy_reg = CSR_READ_4(sc, DC_NETCFG); 879 CSR_WRITE_4(sc, DC_NETCFG, phy_reg & ~DC_NETCFG_PORTSEL); 880 } 881 dc_mii_readreg(sc, &frame); 882 if (sc->dc_type == DC_TYPE_98713) 883 CSR_WRITE_4(sc, DC_NETCFG, phy_reg); 884 885 return (frame.mii_data); 886 } 887 888 static int 889 dc_miibus_writereg(device_t dev, int phy, int reg, int data) 890 { 891 struct dc_softc *sc; 892 struct dc_mii_frame frame; 893 int i, phy_reg = 0; 894 895 sc = device_get_softc(dev); 896 bzero(&frame, sizeof(frame)); 897 898 if (DC_IS_ADMTEK(sc) && phy != DC_ADMTEK_PHYADDR) 899 return (0); 900 901 if (DC_IS_CONEXANT(sc) && phy != DC_CONEXANT_PHYADDR) 902 return (0); 903 904 if (DC_IS_PNIC(sc)) { 905 CSR_WRITE_4(sc, DC_PN_MII, DC_PN_MIIOPCODE_WRITE | 906 (phy << 23) | (reg << 10) | data); 907 for (i = 0; i < DC_TIMEOUT; i++) { 908 if (!(CSR_READ_4(sc, DC_PN_MII) & DC_PN_MII_BUSY)) 909 break; 910 } 911 return (0); 912 } 913 914 if (DC_IS_COMET(sc)) { 915 switch (reg) { 916 case MII_BMCR: 917 phy_reg = DC_AL_BMCR; 918 break; 919 case MII_BMSR: 920 phy_reg = DC_AL_BMSR; 921 break; 922 case MII_PHYIDR1: 923 phy_reg = DC_AL_VENID; 924 break; 925 case MII_PHYIDR2: 926 phy_reg = DC_AL_DEVID; 927 break; 928 case MII_ANAR: 929 phy_reg = DC_AL_ANAR; 930 break; 931 case MII_ANLPAR: 932 phy_reg = DC_AL_LPAR; 933 break; 934 case MII_ANER: 935 phy_reg = DC_AL_ANER; 936 break; 937 default: 938 device_printf(dev, "phy_write: bad phy register %x\n", 939 reg); 940 return (0); 941 break; 942 } 943 944 CSR_WRITE_4(sc, phy_reg, data); 945 return (0); 946 } 947 948 frame.mii_phyaddr = phy; 949 frame.mii_regaddr = reg; 950 frame.mii_data = data; 951 952 if (sc->dc_type == DC_TYPE_98713) { 953 phy_reg = CSR_READ_4(sc, DC_NETCFG); 954 CSR_WRITE_4(sc, DC_NETCFG, phy_reg & ~DC_NETCFG_PORTSEL); 955 } 956 dc_mii_writereg(sc, &frame); 957 if (sc->dc_type == DC_TYPE_98713) 958 CSR_WRITE_4(sc, DC_NETCFG, phy_reg); 959 960 return (0); 961 } 962 963 static void 964 dc_miibus_statchg(device_t dev) 965 { 966 struct dc_softc *sc; 967 struct mii_data *mii; 968 struct ifmedia *ifm; 969 970 sc = device_get_softc(dev); 971 if (DC_IS_ADMTEK(sc)) 972 return; 973 974 mii = device_get_softc(sc->dc_miibus); 975 ifm = &mii->mii_media; 976 if (DC_IS_DAVICOM(sc) && 977 IFM_SUBTYPE(ifm->ifm_media) == IFM_HPNA_1) { 978 dc_setcfg(sc, ifm->ifm_media); 979 sc->dc_if_media = ifm->ifm_media; 980 } else { 981 dc_setcfg(sc, mii->mii_media_active); 982 sc->dc_if_media = mii->mii_media_active; 983 } 984 } 985 986 /* 987 * Special support for DM9102A cards with HomePNA PHYs. Note: 988 * with the Davicom DM9102A/DM9801 eval board that I have, it seems 989 * to be impossible to talk to the management interface of the DM9801 990 * PHY (its MDIO pin is not connected to anything). Consequently, 991 * the driver has to just 'know' about the additional mode and deal 992 * with it itself. *sigh* 993 */ 994 static void 995 dc_miibus_mediainit(device_t dev) 996 { 997 struct dc_softc *sc; 998 struct mii_data *mii; 999 struct ifmedia *ifm; 1000 int rev; 1001 1002 rev = pci_get_revid(dev); 1003 1004 sc = device_get_softc(dev); 1005 mii = device_get_softc(sc->dc_miibus); 1006 ifm = &mii->mii_media; 1007 1008 if (DC_IS_DAVICOM(sc) && rev >= DC_REVISION_DM9102A) 1009 ifmedia_add(ifm, IFM_ETHER | IFM_HPNA_1, 0, NULL); 1010 } 1011 1012 #define DC_BITS_512 9 1013 #define DC_BITS_128 7 1014 #define DC_BITS_64 6 1015 1016 static uint32_t 1017 dc_mchash_le(struct dc_softc *sc, const uint8_t *addr) 1018 { 1019 uint32_t crc; 1020 1021 /* Compute CRC for the address value. */ 1022 crc = ether_crc32_le(addr, ETHER_ADDR_LEN); 1023 1024 /* 1025 * The hash table on the PNIC II and the MX98715AEC-C/D/E 1026 * chips is only 128 bits wide. 1027 */ 1028 if (sc->dc_flags & DC_128BIT_HASH) 1029 return (crc & ((1 << DC_BITS_128) - 1)); 1030 1031 /* The hash table on the MX98715BEC is only 64 bits wide. */ 1032 if (sc->dc_flags & DC_64BIT_HASH) 1033 return (crc & ((1 << DC_BITS_64) - 1)); 1034 1035 /* Xircom's hash filtering table is different (read: weird) */ 1036 /* Xircom uses the LEAST significant bits */ 1037 if (DC_IS_XIRCOM(sc)) { 1038 if ((crc & 0x180) == 0x180) 1039 return ((crc & 0x0F) + (crc & 0x70) * 3 + (14 << 4)); 1040 else 1041 return ((crc & 0x1F) + ((crc >> 1) & 0xF0) * 3 + 1042 (12 << 4)); 1043 } 1044 1045 return (crc & ((1 << DC_BITS_512) - 1)); 1046 } 1047 1048 /* 1049 * Calculate CRC of a multicast group address, return the lower 6 bits. 1050 */ 1051 static uint32_t 1052 dc_mchash_be(const uint8_t *addr) 1053 { 1054 uint32_t crc; 1055 1056 /* Compute CRC for the address value. */ 1057 crc = ether_crc32_be(addr, ETHER_ADDR_LEN); 1058 1059 /* Return the filter bit position. */ 1060 return ((crc >> 26) & 0x0000003F); 1061 } 1062 1063 /* 1064 * 21143-style RX filter setup routine. Filter programming is done by 1065 * downloading a special setup frame into the TX engine. 21143, Macronix, 1066 * PNIC, PNIC II and Davicom chips are programmed this way. 1067 * 1068 * We always program the chip using 'hash perfect' mode, i.e. one perfect 1069 * address (our node address) and a 512-bit hash filter for multicast 1070 * frames. We also sneak the broadcast address into the hash filter since 1071 * we need that too. 1072 */ 1073 static void 1074 dc_setfilt_21143(struct dc_softc *sc) 1075 { 1076 uint16_t eaddr[(ETHER_ADDR_LEN+1)/2]; 1077 struct dc_desc *sframe; 1078 u_int32_t h, *sp; 1079 struct ifmultiaddr *ifma; 1080 struct ifnet *ifp; 1081 int i; 1082 1083 ifp = sc->dc_ifp; 1084 1085 i = sc->dc_cdata.dc_tx_prod; 1086 DC_INC(sc->dc_cdata.dc_tx_prod, DC_TX_LIST_CNT); 1087 sc->dc_cdata.dc_tx_cnt++; 1088 sframe = &sc->dc_ldata->dc_tx_list[i]; 1089 sp = sc->dc_cdata.dc_sbuf; 1090 bzero(sp, DC_SFRAME_LEN); 1091 1092 sframe->dc_data = htole32(sc->dc_saddr); 1093 sframe->dc_ctl = htole32(DC_SFRAME_LEN | DC_TXCTL_SETUP | 1094 DC_TXCTL_TLINK | DC_FILTER_HASHPERF | DC_TXCTL_FINT); 1095 1096 sc->dc_cdata.dc_tx_chain[i] = (struct mbuf *)sc->dc_cdata.dc_sbuf; 1097 1098 /* If we want promiscuous mode, set the allframes bit. */ 1099 if (ifp->if_flags & IFF_PROMISC) 1100 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC); 1101 else 1102 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC); 1103 1104 if (ifp->if_flags & IFF_ALLMULTI) 1105 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI); 1106 else 1107 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI); 1108 1109 IF_ADDR_LOCK(ifp); 1110 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 1111 if (ifma->ifma_addr->sa_family != AF_LINK) 1112 continue; 1113 h = dc_mchash_le(sc, 1114 LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 1115 sp[h >> 4] |= htole32(1 << (h & 0xF)); 1116 } 1117 IF_ADDR_UNLOCK(ifp); 1118 1119 if (ifp->if_flags & IFF_BROADCAST) { 1120 h = dc_mchash_le(sc, ifp->if_broadcastaddr); 1121 sp[h >> 4] |= htole32(1 << (h & 0xF)); 1122 } 1123 1124 /* Set our MAC address. */ 1125 bcopy(IF_LLADDR(sc->dc_ifp), eaddr, ETHER_ADDR_LEN); 1126 sp[39] = DC_SP_MAC(eaddr[0]); 1127 sp[40] = DC_SP_MAC(eaddr[1]); 1128 sp[41] = DC_SP_MAC(eaddr[2]); 1129 1130 sframe->dc_status = htole32(DC_TXSTAT_OWN); 1131 CSR_WRITE_4(sc, DC_TXSTART, 0xFFFFFFFF); 1132 1133 /* 1134 * The PNIC takes an exceedingly long time to process its 1135 * setup frame; wait 10ms after posting the setup frame 1136 * before proceeding, just so it has time to swallow its 1137 * medicine. 1138 */ 1139 DELAY(10000); 1140 1141 ifp->if_timer = 5; 1142 } 1143 1144 static void 1145 dc_setfilt_admtek(struct dc_softc *sc) 1146 { 1147 uint32_t eaddr[(ETHER_ADDR_LEN+3)/4]; 1148 struct ifnet *ifp; 1149 struct ifmultiaddr *ifma; 1150 int h = 0; 1151 u_int32_t hashes[2] = { 0, 0 }; 1152 1153 ifp = sc->dc_ifp; 1154 1155 /* Init our MAC address. */ 1156 bcopy(IF_LLADDR(sc->dc_ifp), eaddr, ETHER_ADDR_LEN); 1157 CSR_WRITE_4(sc, DC_AL_PAR0, eaddr[0]); 1158 CSR_WRITE_4(sc, DC_AL_PAR1, eaddr[1]); 1159 1160 /* If we want promiscuous mode, set the allframes bit. */ 1161 if (ifp->if_flags & IFF_PROMISC) 1162 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC); 1163 else 1164 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC); 1165 1166 if (ifp->if_flags & IFF_ALLMULTI) 1167 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI); 1168 else 1169 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI); 1170 1171 /* First, zot all the existing hash bits. */ 1172 CSR_WRITE_4(sc, DC_AL_MAR0, 0); 1173 CSR_WRITE_4(sc, DC_AL_MAR1, 0); 1174 1175 /* 1176 * If we're already in promisc or allmulti mode, we 1177 * don't have to bother programming the multicast filter. 1178 */ 1179 if (ifp->if_flags & (IFF_PROMISC | IFF_ALLMULTI)) 1180 return; 1181 1182 /* Now program new ones. */ 1183 IF_ADDR_LOCK(ifp); 1184 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 1185 if (ifma->ifma_addr->sa_family != AF_LINK) 1186 continue; 1187 if (DC_IS_CENTAUR(sc)) 1188 h = dc_mchash_le(sc, 1189 LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 1190 else 1191 h = dc_mchash_be( 1192 LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 1193 if (h < 32) 1194 hashes[0] |= (1 << h); 1195 else 1196 hashes[1] |= (1 << (h - 32)); 1197 } 1198 IF_ADDR_UNLOCK(ifp); 1199 1200 CSR_WRITE_4(sc, DC_AL_MAR0, hashes[0]); 1201 CSR_WRITE_4(sc, DC_AL_MAR1, hashes[1]); 1202 } 1203 1204 static void 1205 dc_setfilt_asix(struct dc_softc *sc) 1206 { 1207 uint32_t eaddr[(ETHER_ADDR_LEN+3)/4]; 1208 struct ifnet *ifp; 1209 struct ifmultiaddr *ifma; 1210 int h = 0; 1211 u_int32_t hashes[2] = { 0, 0 }; 1212 1213 ifp = sc->dc_ifp; 1214 1215 /* Init our MAC address. */ 1216 bcopy(IF_LLADDR(sc->dc_ifp), eaddr, ETHER_ADDR_LEN); 1217 CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_PAR0); 1218 CSR_WRITE_4(sc, DC_AX_FILTDATA, eaddr[0]); 1219 CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_PAR1); 1220 CSR_WRITE_4(sc, DC_AX_FILTDATA, eaddr[1]); 1221 1222 /* If we want promiscuous mode, set the allframes bit. */ 1223 if (ifp->if_flags & IFF_PROMISC) 1224 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC); 1225 else 1226 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC); 1227 1228 if (ifp->if_flags & IFF_ALLMULTI) 1229 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI); 1230 else 1231 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI); 1232 1233 /* 1234 * The ASIX chip has a special bit to enable reception 1235 * of broadcast frames. 1236 */ 1237 if (ifp->if_flags & IFF_BROADCAST) 1238 DC_SETBIT(sc, DC_NETCFG, DC_AX_NETCFG_RX_BROAD); 1239 else 1240 DC_CLRBIT(sc, DC_NETCFG, DC_AX_NETCFG_RX_BROAD); 1241 1242 /* first, zot all the existing hash bits */ 1243 CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_MAR0); 1244 CSR_WRITE_4(sc, DC_AX_FILTDATA, 0); 1245 CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_MAR1); 1246 CSR_WRITE_4(sc, DC_AX_FILTDATA, 0); 1247 1248 /* 1249 * If we're already in promisc or allmulti mode, we 1250 * don't have to bother programming the multicast filter. 1251 */ 1252 if (ifp->if_flags & (IFF_PROMISC | IFF_ALLMULTI)) 1253 return; 1254 1255 /* now program new ones */ 1256 IF_ADDR_LOCK(ifp); 1257 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 1258 if (ifma->ifma_addr->sa_family != AF_LINK) 1259 continue; 1260 h = dc_mchash_be(LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 1261 if (h < 32) 1262 hashes[0] |= (1 << h); 1263 else 1264 hashes[1] |= (1 << (h - 32)); 1265 } 1266 IF_ADDR_UNLOCK(ifp); 1267 1268 CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_MAR0); 1269 CSR_WRITE_4(sc, DC_AX_FILTDATA, hashes[0]); 1270 CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_MAR1); 1271 CSR_WRITE_4(sc, DC_AX_FILTDATA, hashes[1]); 1272 } 1273 1274 static void 1275 dc_setfilt_xircom(struct dc_softc *sc) 1276 { 1277 uint16_t eaddr[(ETHER_ADDR_LEN+1)/2]; 1278 struct ifnet *ifp; 1279 struct ifmultiaddr *ifma; 1280 struct dc_desc *sframe; 1281 u_int32_t h, *sp; 1282 int i; 1283 1284 ifp = sc->dc_ifp; 1285 DC_CLRBIT(sc, DC_NETCFG, (DC_NETCFG_TX_ON | DC_NETCFG_RX_ON)); 1286 1287 i = sc->dc_cdata.dc_tx_prod; 1288 DC_INC(sc->dc_cdata.dc_tx_prod, DC_TX_LIST_CNT); 1289 sc->dc_cdata.dc_tx_cnt++; 1290 sframe = &sc->dc_ldata->dc_tx_list[i]; 1291 sp = sc->dc_cdata.dc_sbuf; 1292 bzero(sp, DC_SFRAME_LEN); 1293 1294 sframe->dc_data = htole32(sc->dc_saddr); 1295 sframe->dc_ctl = htole32(DC_SFRAME_LEN | DC_TXCTL_SETUP | 1296 DC_TXCTL_TLINK | DC_FILTER_HASHPERF | DC_TXCTL_FINT); 1297 1298 sc->dc_cdata.dc_tx_chain[i] = (struct mbuf *)sc->dc_cdata.dc_sbuf; 1299 1300 /* If we want promiscuous mode, set the allframes bit. */ 1301 if (ifp->if_flags & IFF_PROMISC) 1302 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC); 1303 else 1304 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC); 1305 1306 if (ifp->if_flags & IFF_ALLMULTI) 1307 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI); 1308 else 1309 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI); 1310 1311 IF_ADDR_LOCK(ifp); 1312 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 1313 if (ifma->ifma_addr->sa_family != AF_LINK) 1314 continue; 1315 h = dc_mchash_le(sc, 1316 LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 1317 sp[h >> 4] |= htole32(1 << (h & 0xF)); 1318 } 1319 IF_ADDR_UNLOCK(ifp); 1320 1321 if (ifp->if_flags & IFF_BROADCAST) { 1322 h = dc_mchash_le(sc, ifp->if_broadcastaddr); 1323 sp[h >> 4] |= htole32(1 << (h & 0xF)); 1324 } 1325 1326 /* Set our MAC address. */ 1327 bcopy(IF_LLADDR(sc->dc_ifp), eaddr, ETHER_ADDR_LEN); 1328 sp[0] = DC_SP_MAC(eaddr[0]); 1329 sp[1] = DC_SP_MAC(eaddr[1]); 1330 sp[2] = DC_SP_MAC(eaddr[2]); 1331 1332 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_TX_ON); 1333 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_ON); 1334 ifp->if_drv_flags |= IFF_DRV_RUNNING; 1335 sframe->dc_status = htole32(DC_TXSTAT_OWN); 1336 CSR_WRITE_4(sc, DC_TXSTART, 0xFFFFFFFF); 1337 1338 /* 1339 * Wait some time... 1340 */ 1341 DELAY(1000); 1342 1343 ifp->if_timer = 5; 1344 } 1345 1346 static void 1347 dc_setfilt(struct dc_softc *sc) 1348 { 1349 1350 if (DC_IS_INTEL(sc) || DC_IS_MACRONIX(sc) || DC_IS_PNIC(sc) || 1351 DC_IS_PNICII(sc) || DC_IS_DAVICOM(sc) || DC_IS_CONEXANT(sc)) 1352 dc_setfilt_21143(sc); 1353 1354 if (DC_IS_ASIX(sc)) 1355 dc_setfilt_asix(sc); 1356 1357 if (DC_IS_ADMTEK(sc)) 1358 dc_setfilt_admtek(sc); 1359 1360 if (DC_IS_XIRCOM(sc)) 1361 dc_setfilt_xircom(sc); 1362 } 1363 1364 /* 1365 * In order to fiddle with the 'full-duplex' and '100Mbps' bits in 1366 * the netconfig register, we first have to put the transmit and/or 1367 * receive logic in the idle state. 1368 */ 1369 static void 1370 dc_setcfg(struct dc_softc *sc, int media) 1371 { 1372 int i, restart = 0, watchdogreg; 1373 u_int32_t isr; 1374 1375 if (IFM_SUBTYPE(media) == IFM_NONE) 1376 return; 1377 1378 if (CSR_READ_4(sc, DC_NETCFG) & (DC_NETCFG_TX_ON | DC_NETCFG_RX_ON)) { 1379 restart = 1; 1380 DC_CLRBIT(sc, DC_NETCFG, (DC_NETCFG_TX_ON | DC_NETCFG_RX_ON)); 1381 1382 for (i = 0; i < DC_TIMEOUT; i++) { 1383 isr = CSR_READ_4(sc, DC_ISR); 1384 if (isr & DC_ISR_TX_IDLE && 1385 ((isr & DC_ISR_RX_STATE) == DC_RXSTATE_STOPPED || 1386 (isr & DC_ISR_RX_STATE) == DC_RXSTATE_WAIT)) 1387 break; 1388 DELAY(10); 1389 } 1390 1391 if (i == DC_TIMEOUT) { 1392 if (!(isr & DC_ISR_TX_IDLE) && !DC_IS_ASIX(sc)) 1393 device_printf(sc->dc_dev, 1394 "%s: failed to force tx to idle state\n", 1395 __func__); 1396 if (!((isr & DC_ISR_RX_STATE) == DC_RXSTATE_STOPPED || 1397 (isr & DC_ISR_RX_STATE) == DC_RXSTATE_WAIT) && 1398 !(DC_IS_CENTAUR(sc) || DC_IS_CONEXANT(sc) || 1399 (DC_IS_DAVICOM(sc) && pci_get_revid(sc->dc_dev) >= 1400 DC_REVISION_DM9102A))) 1401 device_printf(sc->dc_dev, 1402 "%s: failed to force rx to idle state\n", 1403 __func__); 1404 } 1405 } 1406 1407 if (IFM_SUBTYPE(media) == IFM_100_TX) { 1408 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_SPEEDSEL); 1409 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_HEARTBEAT); 1410 if (sc->dc_pmode == DC_PMODE_MII) { 1411 if (DC_IS_INTEL(sc)) { 1412 /* There's a write enable bit here that reads as 1. */ 1413 watchdogreg = CSR_READ_4(sc, DC_WATCHDOG); 1414 watchdogreg &= ~DC_WDOG_CTLWREN; 1415 watchdogreg |= DC_WDOG_JABBERDIS; 1416 CSR_WRITE_4(sc, DC_WATCHDOG, watchdogreg); 1417 } else { 1418 DC_SETBIT(sc, DC_WATCHDOG, DC_WDOG_JABBERDIS); 1419 } 1420 DC_CLRBIT(sc, DC_NETCFG, (DC_NETCFG_PCS | 1421 DC_NETCFG_PORTSEL | DC_NETCFG_SCRAMBLER)); 1422 if (sc->dc_type == DC_TYPE_98713) 1423 DC_SETBIT(sc, DC_NETCFG, (DC_NETCFG_PCS | 1424 DC_NETCFG_SCRAMBLER)); 1425 if (!DC_IS_DAVICOM(sc)) 1426 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL); 1427 DC_CLRBIT(sc, DC_10BTCTRL, 0xFFFF); 1428 if (DC_IS_INTEL(sc)) 1429 dc_apply_fixup(sc, IFM_AUTO); 1430 } else { 1431 if (DC_IS_PNIC(sc)) { 1432 DC_PN_GPIO_SETBIT(sc, DC_PN_GPIO_SPEEDSEL); 1433 DC_PN_GPIO_SETBIT(sc, DC_PN_GPIO_100TX_LOOP); 1434 DC_SETBIT(sc, DC_PN_NWAY, DC_PN_NWAY_SPEEDSEL); 1435 } 1436 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL); 1437 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PCS); 1438 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_SCRAMBLER); 1439 if (DC_IS_INTEL(sc)) 1440 dc_apply_fixup(sc, 1441 (media & IFM_GMASK) == IFM_FDX ? 1442 IFM_100_TX | IFM_FDX : IFM_100_TX); 1443 } 1444 } 1445 1446 if (IFM_SUBTYPE(media) == IFM_10_T) { 1447 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_SPEEDSEL); 1448 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_HEARTBEAT); 1449 if (sc->dc_pmode == DC_PMODE_MII) { 1450 /* There's a write enable bit here that reads as 1. */ 1451 if (DC_IS_INTEL(sc)) { 1452 watchdogreg = CSR_READ_4(sc, DC_WATCHDOG); 1453 watchdogreg &= ~DC_WDOG_CTLWREN; 1454 watchdogreg |= DC_WDOG_JABBERDIS; 1455 CSR_WRITE_4(sc, DC_WATCHDOG, watchdogreg); 1456 } else { 1457 DC_SETBIT(sc, DC_WATCHDOG, DC_WDOG_JABBERDIS); 1458 } 1459 DC_CLRBIT(sc, DC_NETCFG, (DC_NETCFG_PCS | 1460 DC_NETCFG_PORTSEL | DC_NETCFG_SCRAMBLER)); 1461 if (sc->dc_type == DC_TYPE_98713) 1462 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PCS); 1463 if (!DC_IS_DAVICOM(sc)) 1464 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL); 1465 DC_CLRBIT(sc, DC_10BTCTRL, 0xFFFF); 1466 if (DC_IS_INTEL(sc)) 1467 dc_apply_fixup(sc, IFM_AUTO); 1468 } else { 1469 if (DC_IS_PNIC(sc)) { 1470 DC_PN_GPIO_CLRBIT(sc, DC_PN_GPIO_SPEEDSEL); 1471 DC_PN_GPIO_SETBIT(sc, DC_PN_GPIO_100TX_LOOP); 1472 DC_CLRBIT(sc, DC_PN_NWAY, DC_PN_NWAY_SPEEDSEL); 1473 } 1474 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL); 1475 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_PCS); 1476 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_SCRAMBLER); 1477 if (DC_IS_INTEL(sc)) { 1478 DC_CLRBIT(sc, DC_SIARESET, DC_SIA_RESET); 1479 DC_CLRBIT(sc, DC_10BTCTRL, 0xFFFF); 1480 if ((media & IFM_GMASK) == IFM_FDX) 1481 DC_SETBIT(sc, DC_10BTCTRL, 0x7F3D); 1482 else 1483 DC_SETBIT(sc, DC_10BTCTRL, 0x7F3F); 1484 DC_SETBIT(sc, DC_SIARESET, DC_SIA_RESET); 1485 DC_CLRBIT(sc, DC_10BTCTRL, 1486 DC_TCTL_AUTONEGENBL); 1487 dc_apply_fixup(sc, 1488 (media & IFM_GMASK) == IFM_FDX ? 1489 IFM_10_T | IFM_FDX : IFM_10_T); 1490 DELAY(20000); 1491 } 1492 } 1493 } 1494 1495 /* 1496 * If this is a Davicom DM9102A card with a DM9801 HomePNA 1497 * PHY and we want HomePNA mode, set the portsel bit to turn 1498 * on the external MII port. 1499 */ 1500 if (DC_IS_DAVICOM(sc)) { 1501 if (IFM_SUBTYPE(media) == IFM_HPNA_1) { 1502 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL); 1503 sc->dc_link = 1; 1504 } else { 1505 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL); 1506 } 1507 } 1508 1509 if ((media & IFM_GMASK) == IFM_FDX) { 1510 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_FULLDUPLEX); 1511 if (sc->dc_pmode == DC_PMODE_SYM && DC_IS_PNIC(sc)) 1512 DC_SETBIT(sc, DC_PN_NWAY, DC_PN_NWAY_DUPLEX); 1513 } else { 1514 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_FULLDUPLEX); 1515 if (sc->dc_pmode == DC_PMODE_SYM && DC_IS_PNIC(sc)) 1516 DC_CLRBIT(sc, DC_PN_NWAY, DC_PN_NWAY_DUPLEX); 1517 } 1518 1519 if (restart) 1520 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_TX_ON | DC_NETCFG_RX_ON); 1521 } 1522 1523 static void 1524 dc_reset(struct dc_softc *sc) 1525 { 1526 int i; 1527 1528 DC_SETBIT(sc, DC_BUSCTL, DC_BUSCTL_RESET); 1529 1530 for (i = 0; i < DC_TIMEOUT; i++) { 1531 DELAY(10); 1532 if (!(CSR_READ_4(sc, DC_BUSCTL) & DC_BUSCTL_RESET)) 1533 break; 1534 } 1535 1536 if (DC_IS_ASIX(sc) || DC_IS_ADMTEK(sc) || DC_IS_CONEXANT(sc) || 1537 DC_IS_XIRCOM(sc) || DC_IS_INTEL(sc)) { 1538 DELAY(10000); 1539 DC_CLRBIT(sc, DC_BUSCTL, DC_BUSCTL_RESET); 1540 i = 0; 1541 } 1542 1543 if (i == DC_TIMEOUT) 1544 device_printf(sc->dc_dev, "reset never completed!\n"); 1545 1546 /* Wait a little while for the chip to get its brains in order. */ 1547 DELAY(1000); 1548 1549 CSR_WRITE_4(sc, DC_IMR, 0x00000000); 1550 CSR_WRITE_4(sc, DC_BUSCTL, 0x00000000); 1551 CSR_WRITE_4(sc, DC_NETCFG, 0x00000000); 1552 1553 /* 1554 * Bring the SIA out of reset. In some cases, it looks 1555 * like failing to unreset the SIA soon enough gets it 1556 * into a state where it will never come out of reset 1557 * until we reset the whole chip again. 1558 */ 1559 if (DC_IS_INTEL(sc)) { 1560 DC_SETBIT(sc, DC_SIARESET, DC_SIA_RESET); 1561 CSR_WRITE_4(sc, DC_10BTCTRL, 0); 1562 CSR_WRITE_4(sc, DC_WATCHDOG, 0); 1563 } 1564 } 1565 1566 static struct dc_type * 1567 dc_devtype(device_t dev) 1568 { 1569 struct dc_type *t; 1570 u_int32_t devid; 1571 u_int8_t rev; 1572 1573 t = dc_devs; 1574 devid = pci_get_devid(dev); 1575 rev = pci_get_revid(dev); 1576 1577 while (t->dc_name != NULL) { 1578 if (devid == t->dc_devid && rev >= t->dc_minrev) 1579 return (t); 1580 t++; 1581 } 1582 1583 return (NULL); 1584 } 1585 1586 /* 1587 * Probe for a 21143 or clone chip. Check the PCI vendor and device 1588 * IDs against our list and return a device name if we find a match. 1589 * We do a little bit of extra work to identify the exact type of 1590 * chip. The MX98713 and MX98713A have the same PCI vendor/device ID, 1591 * but different revision IDs. The same is true for 98715/98715A 1592 * chips and the 98725, as well as the ASIX and ADMtek chips. In some 1593 * cases, the exact chip revision affects driver behavior. 1594 */ 1595 static int 1596 dc_probe(device_t dev) 1597 { 1598 struct dc_type *t; 1599 1600 t = dc_devtype(dev); 1601 1602 if (t != NULL) { 1603 device_set_desc(dev, t->dc_name); 1604 return (BUS_PROBE_DEFAULT); 1605 } 1606 1607 return (ENXIO); 1608 } 1609 1610 static void 1611 dc_apply_fixup(struct dc_softc *sc, int media) 1612 { 1613 struct dc_mediainfo *m; 1614 u_int8_t *p; 1615 int i; 1616 u_int32_t reg; 1617 1618 m = sc->dc_mi; 1619 1620 while (m != NULL) { 1621 if (m->dc_media == media) 1622 break; 1623 m = m->dc_next; 1624 } 1625 1626 if (m == NULL) 1627 return; 1628 1629 for (i = 0, p = m->dc_reset_ptr; i < m->dc_reset_len; i++, p += 2) { 1630 reg = (p[0] | (p[1] << 8)) << 16; 1631 CSR_WRITE_4(sc, DC_WATCHDOG, reg); 1632 } 1633 1634 for (i = 0, p = m->dc_gp_ptr; i < m->dc_gp_len; i++, p += 2) { 1635 reg = (p[0] | (p[1] << 8)) << 16; 1636 CSR_WRITE_4(sc, DC_WATCHDOG, reg); 1637 } 1638 } 1639 1640 static void 1641 dc_decode_leaf_sia(struct dc_softc *sc, struct dc_eblock_sia *l) 1642 { 1643 struct dc_mediainfo *m; 1644 1645 m = malloc(sizeof(struct dc_mediainfo), M_DEVBUF, M_NOWAIT | M_ZERO); 1646 switch (l->dc_sia_code & ~DC_SIA_CODE_EXT) { 1647 case DC_SIA_CODE_10BT: 1648 m->dc_media = IFM_10_T; 1649 break; 1650 case DC_SIA_CODE_10BT_FDX: 1651 m->dc_media = IFM_10_T | IFM_FDX; 1652 break; 1653 case DC_SIA_CODE_10B2: 1654 m->dc_media = IFM_10_2; 1655 break; 1656 case DC_SIA_CODE_10B5: 1657 m->dc_media = IFM_10_5; 1658 break; 1659 default: 1660 break; 1661 } 1662 1663 /* 1664 * We need to ignore CSR13, CSR14, CSR15 for SIA mode. 1665 * Things apparently already work for cards that do 1666 * supply Media Specific Data. 1667 */ 1668 if (l->dc_sia_code & DC_SIA_CODE_EXT) { 1669 m->dc_gp_len = 2; 1670 m->dc_gp_ptr = 1671 (u_int8_t *)&l->dc_un.dc_sia_ext.dc_sia_gpio_ctl; 1672 } else { 1673 m->dc_gp_len = 2; 1674 m->dc_gp_ptr = 1675 (u_int8_t *)&l->dc_un.dc_sia_noext.dc_sia_gpio_ctl; 1676 } 1677 1678 m->dc_next = sc->dc_mi; 1679 sc->dc_mi = m; 1680 1681 sc->dc_pmode = DC_PMODE_SIA; 1682 } 1683 1684 static void 1685 dc_decode_leaf_sym(struct dc_softc *sc, struct dc_eblock_sym *l) 1686 { 1687 struct dc_mediainfo *m; 1688 1689 m = malloc(sizeof(struct dc_mediainfo), M_DEVBUF, M_NOWAIT | M_ZERO); 1690 if (l->dc_sym_code == DC_SYM_CODE_100BT) 1691 m->dc_media = IFM_100_TX; 1692 1693 if (l->dc_sym_code == DC_SYM_CODE_100BT_FDX) 1694 m->dc_media = IFM_100_TX | IFM_FDX; 1695 1696 m->dc_gp_len = 2; 1697 m->dc_gp_ptr = (u_int8_t *)&l->dc_sym_gpio_ctl; 1698 1699 m->dc_next = sc->dc_mi; 1700 sc->dc_mi = m; 1701 1702 sc->dc_pmode = DC_PMODE_SYM; 1703 } 1704 1705 static void 1706 dc_decode_leaf_mii(struct dc_softc *sc, struct dc_eblock_mii *l) 1707 { 1708 struct dc_mediainfo *m; 1709 u_int8_t *p; 1710 1711 m = malloc(sizeof(struct dc_mediainfo), M_DEVBUF, M_NOWAIT | M_ZERO); 1712 /* We abuse IFM_AUTO to represent MII. */ 1713 m->dc_media = IFM_AUTO; 1714 m->dc_gp_len = l->dc_gpr_len; 1715 1716 p = (u_int8_t *)l; 1717 p += sizeof(struct dc_eblock_mii); 1718 m->dc_gp_ptr = p; 1719 p += 2 * l->dc_gpr_len; 1720 m->dc_reset_len = *p; 1721 p++; 1722 m->dc_reset_ptr = p; 1723 1724 m->dc_next = sc->dc_mi; 1725 sc->dc_mi = m; 1726 } 1727 1728 static void 1729 dc_read_srom(struct dc_softc *sc, int bits) 1730 { 1731 int size; 1732 1733 size = 2 << bits; 1734 sc->dc_srom = malloc(size, M_DEVBUF, M_NOWAIT); 1735 dc_read_eeprom(sc, (caddr_t)sc->dc_srom, 0, (size / 2), 0); 1736 } 1737 1738 static void 1739 dc_parse_21143_srom(struct dc_softc *sc) 1740 { 1741 struct dc_leaf_hdr *lhdr; 1742 struct dc_eblock_hdr *hdr; 1743 int have_mii, i, loff; 1744 char *ptr; 1745 1746 have_mii = 0; 1747 loff = sc->dc_srom[27]; 1748 lhdr = (struct dc_leaf_hdr *)&(sc->dc_srom[loff]); 1749 1750 ptr = (char *)lhdr; 1751 ptr += sizeof(struct dc_leaf_hdr) - 1; 1752 /* 1753 * Look if we got a MII media block. 1754 */ 1755 for (i = 0; i < lhdr->dc_mcnt; i++) { 1756 hdr = (struct dc_eblock_hdr *)ptr; 1757 if (hdr->dc_type == DC_EBLOCK_MII) 1758 have_mii++; 1759 1760 ptr += (hdr->dc_len & 0x7F); 1761 ptr++; 1762 } 1763 1764 /* 1765 * Do the same thing again. Only use SIA and SYM media 1766 * blocks if no MII media block is available. 1767 */ 1768 ptr = (char *)lhdr; 1769 ptr += sizeof(struct dc_leaf_hdr) - 1; 1770 for (i = 0; i < lhdr->dc_mcnt; i++) { 1771 hdr = (struct dc_eblock_hdr *)ptr; 1772 switch (hdr->dc_type) { 1773 case DC_EBLOCK_MII: 1774 dc_decode_leaf_mii(sc, (struct dc_eblock_mii *)hdr); 1775 break; 1776 case DC_EBLOCK_SIA: 1777 if (! have_mii) 1778 dc_decode_leaf_sia(sc, 1779 (struct dc_eblock_sia *)hdr); 1780 break; 1781 case DC_EBLOCK_SYM: 1782 if (! have_mii) 1783 dc_decode_leaf_sym(sc, 1784 (struct dc_eblock_sym *)hdr); 1785 break; 1786 default: 1787 /* Don't care. Yet. */ 1788 break; 1789 } 1790 ptr += (hdr->dc_len & 0x7F); 1791 ptr++; 1792 } 1793 } 1794 1795 static void 1796 dc_dma_map_addr(void *arg, bus_dma_segment_t *segs, int nseg, int error) 1797 { 1798 u_int32_t *paddr; 1799 1800 KASSERT(nseg == 1, ("wrong number of segments, should be 1")); 1801 paddr = arg; 1802 *paddr = segs->ds_addr; 1803 } 1804 1805 /* 1806 * Attach the interface. Allocate softc structures, do ifmedia 1807 * setup and ethernet/BPF attach. 1808 */ 1809 static int 1810 dc_attach(device_t dev) 1811 { 1812 int tmp = 0; 1813 uint32_t eaddr[(ETHER_ADDR_LEN+3)/4]; 1814 u_int32_t command; 1815 struct dc_softc *sc; 1816 struct ifnet *ifp; 1817 u_int32_t revision; 1818 int error = 0, rid, mac_offset; 1819 int i; 1820 u_int8_t *mac; 1821 1822 sc = device_get_softc(dev); 1823 sc->dc_dev = dev; 1824 1825 mtx_init(&sc->dc_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 1826 MTX_DEF); 1827 1828 /* 1829 * Map control/status registers. 1830 */ 1831 pci_enable_busmaster(dev); 1832 1833 rid = DC_RID; 1834 sc->dc_res = bus_alloc_resource_any(dev, DC_RES, &rid, RF_ACTIVE); 1835 1836 if (sc->dc_res == NULL) { 1837 device_printf(dev, "couldn't map ports/memory\n"); 1838 error = ENXIO; 1839 goto fail; 1840 } 1841 1842 sc->dc_btag = rman_get_bustag(sc->dc_res); 1843 sc->dc_bhandle = rman_get_bushandle(sc->dc_res); 1844 1845 /* Allocate interrupt. */ 1846 rid = 0; 1847 sc->dc_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 1848 RF_SHAREABLE | RF_ACTIVE); 1849 1850 if (sc->dc_irq == NULL) { 1851 device_printf(dev, "couldn't map interrupt\n"); 1852 error = ENXIO; 1853 goto fail; 1854 } 1855 1856 /* Need this info to decide on a chip type. */ 1857 sc->dc_info = dc_devtype(dev); 1858 revision = pci_get_revid(dev); 1859 1860 /* Get the eeprom width, but PNIC and XIRCOM have diff eeprom */ 1861 if (sc->dc_info->dc_devid != 1862 DC_DEVID(DC_VENDORID_LO, DC_DEVICEID_82C168) && 1863 sc->dc_info->dc_devid != 1864 DC_DEVID(DC_VENDORID_XIRCOM, DC_DEVICEID_X3201)) 1865 dc_eeprom_width(sc); 1866 1867 switch (sc->dc_info->dc_devid) { 1868 case DC_DEVID(DC_VENDORID_DEC, DC_DEVICEID_21143): 1869 sc->dc_type = DC_TYPE_21143; 1870 sc->dc_flags |= DC_TX_POLL | DC_TX_USE_TX_INTR; 1871 sc->dc_flags |= DC_REDUCED_MII_POLL; 1872 /* Save EEPROM contents so we can parse them later. */ 1873 dc_read_srom(sc, sc->dc_romwidth); 1874 break; 1875 case DC_DEVID(DC_VENDORID_DAVICOM, DC_DEVICEID_DM9009): 1876 case DC_DEVID(DC_VENDORID_DAVICOM, DC_DEVICEID_DM9100): 1877 case DC_DEVID(DC_VENDORID_DAVICOM, DC_DEVICEID_DM9102): 1878 sc->dc_type = DC_TYPE_DM9102; 1879 sc->dc_flags |= DC_TX_COALESCE | DC_TX_INTR_ALWAYS; 1880 sc->dc_flags |= DC_REDUCED_MII_POLL | DC_TX_STORENFWD; 1881 sc->dc_flags |= DC_TX_ALIGN; 1882 sc->dc_pmode = DC_PMODE_MII; 1883 1884 /* Increase the latency timer value. */ 1885 pci_write_config(dev, PCIR_LATTIMER, 0x80, 1); 1886 break; 1887 case DC_DEVID(DC_VENDORID_ADMTEK, DC_DEVICEID_AL981): 1888 sc->dc_type = DC_TYPE_AL981; 1889 sc->dc_flags |= DC_TX_USE_TX_INTR; 1890 sc->dc_flags |= DC_TX_ADMTEK_WAR; 1891 sc->dc_pmode = DC_PMODE_MII; 1892 dc_read_srom(sc, sc->dc_romwidth); 1893 break; 1894 case DC_DEVID(DC_VENDORID_ADMTEK, DC_DEVICEID_AN985): 1895 case DC_DEVID(DC_VENDORID_ADMTEK, DC_DEVICEID_ADM9511): 1896 case DC_DEVID(DC_VENDORID_ADMTEK, DC_DEVICEID_ADM9513): 1897 case DC_DEVID(DC_VENDORID_DLINK, DC_DEVICEID_DRP32TXD): 1898 case DC_DEVID(DC_VENDORID_ADMTEK, DC_DEVICEID_FA511): 1899 case DC_DEVID(DC_VENDORID_ABOCOM, DC_DEVICEID_FE2500): 1900 case DC_DEVID(DC_VENDORID_ABOCOM, DC_DEVICEID_FE2500MX): 1901 case DC_DEVID(DC_VENDORID_ACCTON, DC_DEVICEID_EN2242): 1902 case DC_DEVID(DC_VENDORID_HAWKING, DC_DEVICEID_HAWKING_PN672TX): 1903 case DC_DEVID(DC_VENDORID_PLANEX, DC_DEVICEID_FNW3602T): 1904 case DC_DEVID(DC_VENDORID_3COM, DC_DEVICEID_3CSOHOB): 1905 case DC_DEVID(DC_VENDORID_MICROSOFT, DC_DEVICEID_MSMN120): 1906 case DC_DEVID(DC_VENDORID_MICROSOFT, DC_DEVICEID_MSMN130): 1907 case DC_DEVID(DC_VENDORID_LINKSYS, DC_DEVICEID_PCMPC200_AB08): 1908 case DC_DEVID(DC_VENDORID_LINKSYS, DC_DEVICEID_PCMPC200_AB09): 1909 sc->dc_type = DC_TYPE_AN985; 1910 sc->dc_flags |= DC_64BIT_HASH; 1911 sc->dc_flags |= DC_TX_USE_TX_INTR; 1912 sc->dc_flags |= DC_TX_ADMTEK_WAR; 1913 sc->dc_pmode = DC_PMODE_MII; 1914 /* Don't read SROM for - auto-loaded on reset */ 1915 break; 1916 case DC_DEVID(DC_VENDORID_MX, DC_DEVICEID_98713): 1917 case DC_DEVID(DC_VENDORID_CP, DC_DEVICEID_98713_CP): 1918 if (revision < DC_REVISION_98713A) { 1919 sc->dc_type = DC_TYPE_98713; 1920 } 1921 if (revision >= DC_REVISION_98713A) { 1922 sc->dc_type = DC_TYPE_98713A; 1923 sc->dc_flags |= DC_21143_NWAY; 1924 } 1925 sc->dc_flags |= DC_REDUCED_MII_POLL; 1926 sc->dc_flags |= DC_TX_POLL | DC_TX_USE_TX_INTR; 1927 break; 1928 case DC_DEVID(DC_VENDORID_MX, DC_DEVICEID_987x5): 1929 case DC_DEVID(DC_VENDORID_ACCTON, DC_DEVICEID_EN1217): 1930 /* 1931 * Macronix MX98715AEC-C/D/E parts have only a 1932 * 128-bit hash table. We need to deal with these 1933 * in the same manner as the PNIC II so that we 1934 * get the right number of bits out of the 1935 * CRC routine. 1936 */ 1937 if (revision >= DC_REVISION_98715AEC_C && 1938 revision < DC_REVISION_98725) 1939 sc->dc_flags |= DC_128BIT_HASH; 1940 sc->dc_type = DC_TYPE_987x5; 1941 sc->dc_flags |= DC_TX_POLL | DC_TX_USE_TX_INTR; 1942 sc->dc_flags |= DC_REDUCED_MII_POLL | DC_21143_NWAY; 1943 break; 1944 case DC_DEVID(DC_VENDORID_MX, DC_DEVICEID_98727): 1945 sc->dc_type = DC_TYPE_987x5; 1946 sc->dc_flags |= DC_TX_POLL | DC_TX_USE_TX_INTR; 1947 sc->dc_flags |= DC_REDUCED_MII_POLL | DC_21143_NWAY; 1948 break; 1949 case DC_DEVID(DC_VENDORID_LO, DC_DEVICEID_82C115): 1950 sc->dc_type = DC_TYPE_PNICII; 1951 sc->dc_flags |= DC_TX_POLL | DC_TX_USE_TX_INTR | DC_128BIT_HASH; 1952 sc->dc_flags |= DC_REDUCED_MII_POLL | DC_21143_NWAY; 1953 break; 1954 case DC_DEVID(DC_VENDORID_LO, DC_DEVICEID_82C168): 1955 sc->dc_type = DC_TYPE_PNIC; 1956 sc->dc_flags |= DC_TX_STORENFWD | DC_TX_INTR_ALWAYS; 1957 sc->dc_flags |= DC_PNIC_RX_BUG_WAR; 1958 sc->dc_pnic_rx_buf = malloc(DC_RXLEN * 5, M_DEVBUF, M_NOWAIT); 1959 if (revision < DC_REVISION_82C169) 1960 sc->dc_pmode = DC_PMODE_SYM; 1961 break; 1962 case DC_DEVID(DC_VENDORID_ASIX, DC_DEVICEID_AX88140A): 1963 sc->dc_type = DC_TYPE_ASIX; 1964 sc->dc_flags |= DC_TX_USE_TX_INTR | DC_TX_INTR_FIRSTFRAG; 1965 sc->dc_flags |= DC_REDUCED_MII_POLL; 1966 sc->dc_pmode = DC_PMODE_MII; 1967 break; 1968 case DC_DEVID(DC_VENDORID_XIRCOM, DC_DEVICEID_X3201): 1969 sc->dc_type = DC_TYPE_XIRCOM; 1970 sc->dc_flags |= DC_TX_INTR_ALWAYS | DC_TX_COALESCE | 1971 DC_TX_ALIGN; 1972 /* 1973 * We don't actually need to coalesce, but we're doing 1974 * it to obtain a double word aligned buffer. 1975 * The DC_TX_COALESCE flag is required. 1976 */ 1977 sc->dc_pmode = DC_PMODE_MII; 1978 break; 1979 case DC_DEVID(DC_VENDORID_CONEXANT, DC_DEVICEID_RS7112): 1980 sc->dc_type = DC_TYPE_CONEXANT; 1981 sc->dc_flags |= DC_TX_INTR_ALWAYS; 1982 sc->dc_flags |= DC_REDUCED_MII_POLL; 1983 sc->dc_pmode = DC_PMODE_MII; 1984 dc_read_srom(sc, sc->dc_romwidth); 1985 break; 1986 default: 1987 device_printf(dev, "unknown device: %x\n", 1988 sc->dc_info->dc_devid); 1989 break; 1990 } 1991 1992 /* Save the cache line size. */ 1993 if (DC_IS_DAVICOM(sc)) 1994 sc->dc_cachesize = 0; 1995 else 1996 sc->dc_cachesize = pci_get_cachelnsz(dev); 1997 1998 /* Reset the adapter. */ 1999 dc_reset(sc); 2000 2001 /* Take 21143 out of snooze mode */ 2002 if (DC_IS_INTEL(sc) || DC_IS_XIRCOM(sc)) { 2003 command = pci_read_config(dev, DC_PCI_CFDD, 4); 2004 command &= ~(DC_CFDD_SNOOZE_MODE | DC_CFDD_SLEEP_MODE); 2005 pci_write_config(dev, DC_PCI_CFDD, command, 4); 2006 } 2007 2008 /* 2009 * Try to learn something about the supported media. 2010 * We know that ASIX and ADMtek and Davicom devices 2011 * will *always* be using MII media, so that's a no-brainer. 2012 * The tricky ones are the Macronix/PNIC II and the 2013 * Intel 21143. 2014 */ 2015 if (DC_IS_INTEL(sc)) 2016 dc_parse_21143_srom(sc); 2017 else if (DC_IS_MACRONIX(sc) || DC_IS_PNICII(sc)) { 2018 if (sc->dc_type == DC_TYPE_98713) 2019 sc->dc_pmode = DC_PMODE_MII; 2020 else 2021 sc->dc_pmode = DC_PMODE_SYM; 2022 } else if (!sc->dc_pmode) 2023 sc->dc_pmode = DC_PMODE_MII; 2024 2025 /* 2026 * Get station address from the EEPROM. 2027 */ 2028 switch(sc->dc_type) { 2029 case DC_TYPE_98713: 2030 case DC_TYPE_98713A: 2031 case DC_TYPE_987x5: 2032 case DC_TYPE_PNICII: 2033 dc_read_eeprom(sc, (caddr_t)&mac_offset, 2034 (DC_EE_NODEADDR_OFFSET / 2), 1, 0); 2035 dc_read_eeprom(sc, (caddr_t)&eaddr, (mac_offset / 2), 3, 0); 2036 break; 2037 case DC_TYPE_PNIC: 2038 dc_read_eeprom(sc, (caddr_t)&eaddr, 0, 3, 1); 2039 break; 2040 case DC_TYPE_DM9102: 2041 dc_read_eeprom(sc, (caddr_t)&eaddr, DC_EE_NODEADDR, 3, 0); 2042 #ifdef __sparc64__ 2043 /* 2044 * If this is an onboard dc(4) the station address read from 2045 * the EEPROM is all zero and we have to get it from the FCode. 2046 */ 2047 if (eaddr[0] == 0 && (eaddr[1] & ~0xffff) == 0) 2048 OF_getetheraddr(dev, (caddr_t)&eaddr); 2049 #endif 2050 break; 2051 case DC_TYPE_21143: 2052 case DC_TYPE_ASIX: 2053 dc_read_eeprom(sc, (caddr_t)&eaddr, DC_EE_NODEADDR, 3, 0); 2054 break; 2055 case DC_TYPE_AL981: 2056 case DC_TYPE_AN985: 2057 eaddr[0] = CSR_READ_4(sc, DC_AL_PAR0); 2058 eaddr[1] = CSR_READ_4(sc, DC_AL_PAR1); 2059 break; 2060 case DC_TYPE_CONEXANT: 2061 bcopy(sc->dc_srom + DC_CONEXANT_EE_NODEADDR, &eaddr, 2062 ETHER_ADDR_LEN); 2063 break; 2064 case DC_TYPE_XIRCOM: 2065 /* The MAC comes from the CIS. */ 2066 mac = pci_get_ether(dev); 2067 if (!mac) { 2068 device_printf(dev, "No station address in CIS!\n"); 2069 error = ENXIO; 2070 goto fail; 2071 } 2072 bcopy(mac, eaddr, ETHER_ADDR_LEN); 2073 break; 2074 default: 2075 dc_read_eeprom(sc, (caddr_t)&eaddr, DC_EE_NODEADDR, 3, 0); 2076 break; 2077 } 2078 2079 /* Allocate a busdma tag and DMA safe memory for TX/RX descriptors. */ 2080 error = bus_dma_tag_create(NULL, PAGE_SIZE, 0, BUS_SPACE_MAXADDR_32BIT, 2081 BUS_SPACE_MAXADDR, NULL, NULL, sizeof(struct dc_list_data), 1, 2082 sizeof(struct dc_list_data), 0, NULL, NULL, &sc->dc_ltag); 2083 if (error) { 2084 device_printf(dev, "failed to allocate busdma tag\n"); 2085 error = ENXIO; 2086 goto fail; 2087 } 2088 error = bus_dmamem_alloc(sc->dc_ltag, (void **)&sc->dc_ldata, 2089 BUS_DMA_NOWAIT | BUS_DMA_ZERO, &sc->dc_lmap); 2090 if (error) { 2091 device_printf(dev, "failed to allocate DMA safe memory\n"); 2092 error = ENXIO; 2093 goto fail; 2094 } 2095 error = bus_dmamap_load(sc->dc_ltag, sc->dc_lmap, sc->dc_ldata, 2096 sizeof(struct dc_list_data), dc_dma_map_addr, &sc->dc_laddr, 2097 BUS_DMA_NOWAIT); 2098 if (error) { 2099 device_printf(dev, "cannot get address of the descriptors\n"); 2100 error = ENXIO; 2101 goto fail; 2102 } 2103 2104 /* 2105 * Allocate a busdma tag and DMA safe memory for the multicast 2106 * setup frame. 2107 */ 2108 error = bus_dma_tag_create(NULL, PAGE_SIZE, 0, BUS_SPACE_MAXADDR_32BIT, 2109 BUS_SPACE_MAXADDR, NULL, NULL, DC_SFRAME_LEN + DC_MIN_FRAMELEN, 1, 2110 DC_SFRAME_LEN + DC_MIN_FRAMELEN, 0, NULL, NULL, &sc->dc_stag); 2111 if (error) { 2112 device_printf(dev, "failed to allocate busdma tag\n"); 2113 error = ENXIO; 2114 goto fail; 2115 } 2116 error = bus_dmamem_alloc(sc->dc_stag, (void **)&sc->dc_cdata.dc_sbuf, 2117 BUS_DMA_NOWAIT, &sc->dc_smap); 2118 if (error) { 2119 device_printf(dev, "failed to allocate DMA safe memory\n"); 2120 error = ENXIO; 2121 goto fail; 2122 } 2123 error = bus_dmamap_load(sc->dc_stag, sc->dc_smap, sc->dc_cdata.dc_sbuf, 2124 DC_SFRAME_LEN, dc_dma_map_addr, &sc->dc_saddr, BUS_DMA_NOWAIT); 2125 if (error) { 2126 device_printf(dev, "cannot get address of the descriptors\n"); 2127 error = ENXIO; 2128 goto fail; 2129 } 2130 2131 /* Allocate a busdma tag for mbufs. */ 2132 error = bus_dma_tag_create(NULL, 1, 0, BUS_SPACE_MAXADDR_32BIT, 2133 BUS_SPACE_MAXADDR, NULL, NULL, MCLBYTES, DC_TX_LIST_CNT, MCLBYTES, 2134 0, NULL, NULL, &sc->dc_mtag); 2135 if (error) { 2136 device_printf(dev, "failed to allocate busdma tag\n"); 2137 error = ENXIO; 2138 goto fail; 2139 } 2140 2141 /* Create the TX/RX busdma maps. */ 2142 for (i = 0; i < DC_TX_LIST_CNT; i++) { 2143 error = bus_dmamap_create(sc->dc_mtag, 0, 2144 &sc->dc_cdata.dc_tx_map[i]); 2145 if (error) { 2146 device_printf(dev, "failed to init TX ring\n"); 2147 error = ENXIO; 2148 goto fail; 2149 } 2150 } 2151 for (i = 0; i < DC_RX_LIST_CNT; i++) { 2152 error = bus_dmamap_create(sc->dc_mtag, 0, 2153 &sc->dc_cdata.dc_rx_map[i]); 2154 if (error) { 2155 device_printf(dev, "failed to init RX ring\n"); 2156 error = ENXIO; 2157 goto fail; 2158 } 2159 } 2160 error = bus_dmamap_create(sc->dc_mtag, 0, &sc->dc_sparemap); 2161 if (error) { 2162 device_printf(dev, "failed to init RX ring\n"); 2163 error = ENXIO; 2164 goto fail; 2165 } 2166 2167 ifp = sc->dc_ifp = if_alloc(IFT_ETHER); 2168 if (ifp == NULL) { 2169 device_printf(dev, "can not if_alloc()\n"); 2170 error = ENOSPC; 2171 goto fail; 2172 } 2173 ifp->if_softc = sc; 2174 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 2175 /* XXX: bleah, MTU gets overwritten in ether_ifattach() */ 2176 ifp->if_mtu = ETHERMTU; 2177 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 2178 ifp->if_ioctl = dc_ioctl; 2179 ifp->if_start = dc_start; 2180 ifp->if_watchdog = dc_watchdog; 2181 ifp->if_init = dc_init; 2182 IFQ_SET_MAXLEN(&ifp->if_snd, DC_TX_LIST_CNT - 1); 2183 ifp->if_snd.ifq_drv_maxlen = DC_TX_LIST_CNT - 1; 2184 IFQ_SET_READY(&ifp->if_snd); 2185 2186 /* 2187 * Do MII setup. If this is a 21143, check for a PHY on the 2188 * MII bus after applying any necessary fixups to twiddle the 2189 * GPIO bits. If we don't end up finding a PHY, restore the 2190 * old selection (SIA only or SIA/SYM) and attach the dcphy 2191 * driver instead. 2192 */ 2193 if (DC_IS_INTEL(sc)) { 2194 dc_apply_fixup(sc, IFM_AUTO); 2195 tmp = sc->dc_pmode; 2196 sc->dc_pmode = DC_PMODE_MII; 2197 } 2198 2199 /* 2200 * Setup General Purpose port mode and data so the tulip can talk 2201 * to the MII. This needs to be done before mii_phy_probe so that 2202 * we can actually see them. 2203 */ 2204 if (DC_IS_XIRCOM(sc)) { 2205 CSR_WRITE_4(sc, DC_SIAGP, DC_SIAGP_WRITE_EN | DC_SIAGP_INT1_EN | 2206 DC_SIAGP_MD_GP2_OUTPUT | DC_SIAGP_MD_GP0_OUTPUT); 2207 DELAY(10); 2208 CSR_WRITE_4(sc, DC_SIAGP, DC_SIAGP_INT1_EN | 2209 DC_SIAGP_MD_GP2_OUTPUT | DC_SIAGP_MD_GP0_OUTPUT); 2210 DELAY(10); 2211 } 2212 2213 error = mii_phy_probe(dev, &sc->dc_miibus, 2214 dc_ifmedia_upd, dc_ifmedia_sts); 2215 2216 if (error && DC_IS_INTEL(sc)) { 2217 sc->dc_pmode = tmp; 2218 if (sc->dc_pmode != DC_PMODE_SIA) 2219 sc->dc_pmode = DC_PMODE_SYM; 2220 sc->dc_flags |= DC_21143_NWAY; 2221 mii_phy_probe(dev, &sc->dc_miibus, 2222 dc_ifmedia_upd, dc_ifmedia_sts); 2223 /* 2224 * For non-MII cards, we need to have the 21143 2225 * drive the LEDs. Except there are some systems 2226 * like the NEC VersaPro NoteBook PC which have no 2227 * LEDs, and twiddling these bits has adverse effects 2228 * on them. (I.e. you suddenly can't get a link.) 2229 */ 2230 if (!(pci_get_subvendor(dev) == 0x1033 && 2231 pci_get_subdevice(dev) == 0x8028)) 2232 sc->dc_flags |= DC_TULIP_LEDS; 2233 error = 0; 2234 } 2235 2236 if (error) { 2237 device_printf(dev, "MII without any PHY!\n"); 2238 goto fail; 2239 } 2240 2241 if (DC_IS_ADMTEK(sc)) { 2242 /* 2243 * Set automatic TX underrun recovery for the ADMtek chips 2244 */ 2245 DC_SETBIT(sc, DC_AL_CR, DC_AL_CR_ATUR); 2246 } 2247 2248 /* 2249 * Tell the upper layer(s) we support long frames. 2250 */ 2251 ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header); 2252 ifp->if_capabilities |= IFCAP_VLAN_MTU; 2253 ifp->if_capenable = ifp->if_capabilities; 2254 #ifdef DEVICE_POLLING 2255 ifp->if_capabilities |= IFCAP_POLLING; 2256 #endif 2257 2258 callout_init_mtx(&sc->dc_stat_ch, &sc->dc_mtx, 0); 2259 2260 /* 2261 * Call MI attach routine. 2262 */ 2263 ether_ifattach(ifp, (caddr_t)eaddr); 2264 2265 /* Hook interrupt last to avoid having to lock softc */ 2266 error = bus_setup_intr(dev, sc->dc_irq, INTR_TYPE_NET | INTR_MPSAFE, 2267 dc_intr, sc, &sc->dc_intrhand); 2268 2269 if (error) { 2270 device_printf(dev, "couldn't set up irq\n"); 2271 ether_ifdetach(ifp); 2272 goto fail; 2273 } 2274 2275 fail: 2276 if (error) 2277 dc_detach(dev); 2278 return (error); 2279 } 2280 2281 /* 2282 * Shutdown hardware and free up resources. This can be called any 2283 * time after the mutex has been initialized. It is called in both 2284 * the error case in attach and the normal detach case so it needs 2285 * to be careful about only freeing resources that have actually been 2286 * allocated. 2287 */ 2288 static int 2289 dc_detach(device_t dev) 2290 { 2291 struct dc_softc *sc; 2292 struct ifnet *ifp; 2293 struct dc_mediainfo *m; 2294 int i; 2295 2296 sc = device_get_softc(dev); 2297 KASSERT(mtx_initialized(&sc->dc_mtx), ("dc mutex not initialized")); 2298 2299 ifp = sc->dc_ifp; 2300 2301 #ifdef DEVICE_POLLING 2302 if (ifp->if_capenable & IFCAP_POLLING) 2303 ether_poll_deregister(ifp); 2304 #endif 2305 2306 /* These should only be active if attach succeeded */ 2307 if (device_is_attached(dev)) { 2308 DC_LOCK(sc); 2309 dc_stop(sc); 2310 DC_UNLOCK(sc); 2311 callout_drain(&sc->dc_stat_ch); 2312 ether_ifdetach(ifp); 2313 } 2314 if (sc->dc_miibus) 2315 device_delete_child(dev, sc->dc_miibus); 2316 bus_generic_detach(dev); 2317 2318 if (sc->dc_intrhand) 2319 bus_teardown_intr(dev, sc->dc_irq, sc->dc_intrhand); 2320 if (sc->dc_irq) 2321 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->dc_irq); 2322 if (sc->dc_res) 2323 bus_release_resource(dev, DC_RES, DC_RID, sc->dc_res); 2324 2325 if (ifp) 2326 if_free(ifp); 2327 2328 if (sc->dc_cdata.dc_sbuf != NULL) 2329 bus_dmamem_free(sc->dc_stag, sc->dc_cdata.dc_sbuf, sc->dc_smap); 2330 if (sc->dc_ldata != NULL) 2331 bus_dmamem_free(sc->dc_ltag, sc->dc_ldata, sc->dc_lmap); 2332 if (sc->dc_mtag) { 2333 for (i = 0; i < DC_TX_LIST_CNT; i++) 2334 if (sc->dc_cdata.dc_tx_map[i] != NULL) 2335 bus_dmamap_destroy(sc->dc_mtag, 2336 sc->dc_cdata.dc_tx_map[i]); 2337 for (i = 0; i < DC_RX_LIST_CNT; i++) 2338 if (sc->dc_cdata.dc_rx_map[i] != NULL) 2339 bus_dmamap_destroy(sc->dc_mtag, 2340 sc->dc_cdata.dc_rx_map[i]); 2341 bus_dmamap_destroy(sc->dc_mtag, sc->dc_sparemap); 2342 } 2343 if (sc->dc_stag) 2344 bus_dma_tag_destroy(sc->dc_stag); 2345 if (sc->dc_mtag) 2346 bus_dma_tag_destroy(sc->dc_mtag); 2347 if (sc->dc_ltag) 2348 bus_dma_tag_destroy(sc->dc_ltag); 2349 2350 free(sc->dc_pnic_rx_buf, M_DEVBUF); 2351 2352 while (sc->dc_mi != NULL) { 2353 m = sc->dc_mi->dc_next; 2354 free(sc->dc_mi, M_DEVBUF); 2355 sc->dc_mi = m; 2356 } 2357 free(sc->dc_srom, M_DEVBUF); 2358 2359 mtx_destroy(&sc->dc_mtx); 2360 2361 return (0); 2362 } 2363 2364 /* 2365 * Initialize the transmit descriptors. 2366 */ 2367 static int 2368 dc_list_tx_init(struct dc_softc *sc) 2369 { 2370 struct dc_chain_data *cd; 2371 struct dc_list_data *ld; 2372 int i, nexti; 2373 2374 cd = &sc->dc_cdata; 2375 ld = sc->dc_ldata; 2376 for (i = 0; i < DC_TX_LIST_CNT; i++) { 2377 if (i == DC_TX_LIST_CNT - 1) 2378 nexti = 0; 2379 else 2380 nexti = i + 1; 2381 ld->dc_tx_list[i].dc_next = htole32(DC_TXDESC(sc, nexti)); 2382 cd->dc_tx_chain[i] = NULL; 2383 ld->dc_tx_list[i].dc_data = 0; 2384 ld->dc_tx_list[i].dc_ctl = 0; 2385 } 2386 2387 cd->dc_tx_prod = cd->dc_tx_cons = cd->dc_tx_cnt = 0; 2388 bus_dmamap_sync(sc->dc_ltag, sc->dc_lmap, 2389 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2390 return (0); 2391 } 2392 2393 2394 /* 2395 * Initialize the RX descriptors and allocate mbufs for them. Note that 2396 * we arrange the descriptors in a closed ring, so that the last descriptor 2397 * points back to the first. 2398 */ 2399 static int 2400 dc_list_rx_init(struct dc_softc *sc) 2401 { 2402 struct dc_chain_data *cd; 2403 struct dc_list_data *ld; 2404 int i, nexti; 2405 2406 cd = &sc->dc_cdata; 2407 ld = sc->dc_ldata; 2408 2409 for (i = 0; i < DC_RX_LIST_CNT; i++) { 2410 if (dc_newbuf(sc, i, 1) != 0) 2411 return (ENOBUFS); 2412 if (i == DC_RX_LIST_CNT - 1) 2413 nexti = 0; 2414 else 2415 nexti = i + 1; 2416 ld->dc_rx_list[i].dc_next = htole32(DC_RXDESC(sc, nexti)); 2417 } 2418 2419 cd->dc_rx_prod = 0; 2420 bus_dmamap_sync(sc->dc_ltag, sc->dc_lmap, 2421 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2422 return (0); 2423 } 2424 2425 static void 2426 dc_dma_map_rxbuf(arg, segs, nseg, mapsize, error) 2427 void *arg; 2428 bus_dma_segment_t *segs; 2429 int nseg; 2430 bus_size_t mapsize; 2431 int error; 2432 { 2433 struct dc_softc *sc; 2434 struct dc_desc *c; 2435 2436 sc = arg; 2437 c = &sc->dc_ldata->dc_rx_list[sc->dc_cdata.dc_rx_cur]; 2438 if (error) { 2439 sc->dc_cdata.dc_rx_err = error; 2440 return; 2441 } 2442 2443 KASSERT(nseg == 1, ("wrong number of segments, should be 1")); 2444 sc->dc_cdata.dc_rx_err = 0; 2445 c->dc_data = htole32(segs->ds_addr); 2446 } 2447 2448 /* 2449 * Initialize an RX descriptor and attach an MBUF cluster. 2450 */ 2451 static int 2452 dc_newbuf(struct dc_softc *sc, int i, int alloc) 2453 { 2454 struct mbuf *m_new; 2455 bus_dmamap_t tmp; 2456 int error; 2457 2458 if (alloc) { 2459 m_new = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR); 2460 if (m_new == NULL) 2461 return (ENOBUFS); 2462 } else { 2463 m_new = sc->dc_cdata.dc_rx_chain[i]; 2464 m_new->m_data = m_new->m_ext.ext_buf; 2465 } 2466 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 2467 m_adj(m_new, sizeof(u_int64_t)); 2468 2469 /* 2470 * If this is a PNIC chip, zero the buffer. This is part 2471 * of the workaround for the receive bug in the 82c168 and 2472 * 82c169 chips. 2473 */ 2474 if (sc->dc_flags & DC_PNIC_RX_BUG_WAR) 2475 bzero(mtod(m_new, char *), m_new->m_len); 2476 2477 /* No need to remap the mbuf if we're reusing it. */ 2478 if (alloc) { 2479 sc->dc_cdata.dc_rx_cur = i; 2480 error = bus_dmamap_load_mbuf(sc->dc_mtag, sc->dc_sparemap, 2481 m_new, dc_dma_map_rxbuf, sc, 0); 2482 if (error) { 2483 m_freem(m_new); 2484 return (error); 2485 } 2486 if (sc->dc_cdata.dc_rx_err != 0) { 2487 m_freem(m_new); 2488 return (sc->dc_cdata.dc_rx_err); 2489 } 2490 bus_dmamap_unload(sc->dc_mtag, sc->dc_cdata.dc_rx_map[i]); 2491 tmp = sc->dc_cdata.dc_rx_map[i]; 2492 sc->dc_cdata.dc_rx_map[i] = sc->dc_sparemap; 2493 sc->dc_sparemap = tmp; 2494 sc->dc_cdata.dc_rx_chain[i] = m_new; 2495 } 2496 2497 sc->dc_ldata->dc_rx_list[i].dc_ctl = htole32(DC_RXCTL_RLINK | DC_RXLEN); 2498 sc->dc_ldata->dc_rx_list[i].dc_status = htole32(DC_RXSTAT_OWN); 2499 bus_dmamap_sync(sc->dc_mtag, sc->dc_cdata.dc_rx_map[i], 2500 BUS_DMASYNC_PREREAD); 2501 bus_dmamap_sync(sc->dc_ltag, sc->dc_lmap, 2502 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2503 return (0); 2504 } 2505 2506 /* 2507 * Grrrrr. 2508 * The PNIC chip has a terrible bug in it that manifests itself during 2509 * periods of heavy activity. The exact mode of failure if difficult to 2510 * pinpoint: sometimes it only happens in promiscuous mode, sometimes it 2511 * will happen on slow machines. The bug is that sometimes instead of 2512 * uploading one complete frame during reception, it uploads what looks 2513 * like the entire contents of its FIFO memory. The frame we want is at 2514 * the end of the whole mess, but we never know exactly how much data has 2515 * been uploaded, so salvaging the frame is hard. 2516 * 2517 * There is only one way to do it reliably, and it's disgusting. 2518 * Here's what we know: 2519 * 2520 * - We know there will always be somewhere between one and three extra 2521 * descriptors uploaded. 2522 * 2523 * - We know the desired received frame will always be at the end of the 2524 * total data upload. 2525 * 2526 * - We know the size of the desired received frame because it will be 2527 * provided in the length field of the status word in the last descriptor. 2528 * 2529 * Here's what we do: 2530 * 2531 * - When we allocate buffers for the receive ring, we bzero() them. 2532 * This means that we know that the buffer contents should be all 2533 * zeros, except for data uploaded by the chip. 2534 * 2535 * - We also force the PNIC chip to upload frames that include the 2536 * ethernet CRC at the end. 2537 * 2538 * - We gather all of the bogus frame data into a single buffer. 2539 * 2540 * - We then position a pointer at the end of this buffer and scan 2541 * backwards until we encounter the first non-zero byte of data. 2542 * This is the end of the received frame. We know we will encounter 2543 * some data at the end of the frame because the CRC will always be 2544 * there, so even if the sender transmits a packet of all zeros, 2545 * we won't be fooled. 2546 * 2547 * - We know the size of the actual received frame, so we subtract 2548 * that value from the current pointer location. This brings us 2549 * to the start of the actual received packet. 2550 * 2551 * - We copy this into an mbuf and pass it on, along with the actual 2552 * frame length. 2553 * 2554 * The performance hit is tremendous, but it beats dropping frames all 2555 * the time. 2556 */ 2557 2558 #define DC_WHOLEFRAME (DC_RXSTAT_FIRSTFRAG | DC_RXSTAT_LASTFRAG) 2559 static void 2560 dc_pnic_rx_bug_war(struct dc_softc *sc, int idx) 2561 { 2562 struct dc_desc *cur_rx; 2563 struct dc_desc *c = NULL; 2564 struct mbuf *m = NULL; 2565 unsigned char *ptr; 2566 int i, total_len; 2567 u_int32_t rxstat = 0; 2568 2569 i = sc->dc_pnic_rx_bug_save; 2570 cur_rx = &sc->dc_ldata->dc_rx_list[idx]; 2571 ptr = sc->dc_pnic_rx_buf; 2572 bzero(ptr, DC_RXLEN * 5); 2573 2574 /* Copy all the bytes from the bogus buffers. */ 2575 while (1) { 2576 c = &sc->dc_ldata->dc_rx_list[i]; 2577 rxstat = le32toh(c->dc_status); 2578 m = sc->dc_cdata.dc_rx_chain[i]; 2579 bcopy(mtod(m, char *), ptr, DC_RXLEN); 2580 ptr += DC_RXLEN; 2581 /* If this is the last buffer, break out. */ 2582 if (i == idx || rxstat & DC_RXSTAT_LASTFRAG) 2583 break; 2584 dc_newbuf(sc, i, 0); 2585 DC_INC(i, DC_RX_LIST_CNT); 2586 } 2587 2588 /* Find the length of the actual receive frame. */ 2589 total_len = DC_RXBYTES(rxstat); 2590 2591 /* Scan backwards until we hit a non-zero byte. */ 2592 while (*ptr == 0x00) 2593 ptr--; 2594 2595 /* Round off. */ 2596 if ((uintptr_t)(ptr) & 0x3) 2597 ptr -= 1; 2598 2599 /* Now find the start of the frame. */ 2600 ptr -= total_len; 2601 if (ptr < sc->dc_pnic_rx_buf) 2602 ptr = sc->dc_pnic_rx_buf; 2603 2604 /* 2605 * Now copy the salvaged frame to the last mbuf and fake up 2606 * the status word to make it look like a successful 2607 * frame reception. 2608 */ 2609 dc_newbuf(sc, i, 0); 2610 bcopy(ptr, mtod(m, char *), total_len); 2611 cur_rx->dc_status = htole32(rxstat | DC_RXSTAT_FIRSTFRAG); 2612 } 2613 2614 /* 2615 * This routine searches the RX ring for dirty descriptors in the 2616 * event that the rxeof routine falls out of sync with the chip's 2617 * current descriptor pointer. This may happen sometimes as a result 2618 * of a "no RX buffer available" condition that happens when the chip 2619 * consumes all of the RX buffers before the driver has a chance to 2620 * process the RX ring. This routine may need to be called more than 2621 * once to bring the driver back in sync with the chip, however we 2622 * should still be getting RX DONE interrupts to drive the search 2623 * for new packets in the RX ring, so we should catch up eventually. 2624 */ 2625 static int 2626 dc_rx_resync(struct dc_softc *sc) 2627 { 2628 struct dc_desc *cur_rx; 2629 int i, pos; 2630 2631 pos = sc->dc_cdata.dc_rx_prod; 2632 2633 for (i = 0; i < DC_RX_LIST_CNT; i++) { 2634 cur_rx = &sc->dc_ldata->dc_rx_list[pos]; 2635 if (!(le32toh(cur_rx->dc_status) & DC_RXSTAT_OWN)) 2636 break; 2637 DC_INC(pos, DC_RX_LIST_CNT); 2638 } 2639 2640 /* If the ring really is empty, then just return. */ 2641 if (i == DC_RX_LIST_CNT) 2642 return (0); 2643 2644 /* We've fallen behing the chip: catch it. */ 2645 sc->dc_cdata.dc_rx_prod = pos; 2646 2647 return (EAGAIN); 2648 } 2649 2650 /* 2651 * A frame has been uploaded: pass the resulting mbuf chain up to 2652 * the higher level protocols. 2653 */ 2654 static void 2655 dc_rxeof(struct dc_softc *sc) 2656 { 2657 struct mbuf *m, *m0; 2658 struct ifnet *ifp; 2659 struct dc_desc *cur_rx; 2660 int i, total_len = 0; 2661 u_int32_t rxstat; 2662 2663 DC_LOCK_ASSERT(sc); 2664 2665 ifp = sc->dc_ifp; 2666 i = sc->dc_cdata.dc_rx_prod; 2667 2668 bus_dmamap_sync(sc->dc_ltag, sc->dc_lmap, BUS_DMASYNC_POSTREAD); 2669 while (!(le32toh(sc->dc_ldata->dc_rx_list[i].dc_status) & 2670 DC_RXSTAT_OWN)) { 2671 #ifdef DEVICE_POLLING 2672 if (ifp->if_capenable & IFCAP_POLLING) { 2673 if (sc->rxcycles <= 0) 2674 break; 2675 sc->rxcycles--; 2676 } 2677 #endif 2678 cur_rx = &sc->dc_ldata->dc_rx_list[i]; 2679 rxstat = le32toh(cur_rx->dc_status); 2680 m = sc->dc_cdata.dc_rx_chain[i]; 2681 bus_dmamap_sync(sc->dc_mtag, sc->dc_cdata.dc_rx_map[i], 2682 BUS_DMASYNC_POSTREAD); 2683 total_len = DC_RXBYTES(rxstat); 2684 2685 if (sc->dc_flags & DC_PNIC_RX_BUG_WAR) { 2686 if ((rxstat & DC_WHOLEFRAME) != DC_WHOLEFRAME) { 2687 if (rxstat & DC_RXSTAT_FIRSTFRAG) 2688 sc->dc_pnic_rx_bug_save = i; 2689 if ((rxstat & DC_RXSTAT_LASTFRAG) == 0) { 2690 DC_INC(i, DC_RX_LIST_CNT); 2691 continue; 2692 } 2693 dc_pnic_rx_bug_war(sc, i); 2694 rxstat = le32toh(cur_rx->dc_status); 2695 total_len = DC_RXBYTES(rxstat); 2696 } 2697 } 2698 2699 /* 2700 * If an error occurs, update stats, clear the 2701 * status word and leave the mbuf cluster in place: 2702 * it should simply get re-used next time this descriptor 2703 * comes up in the ring. However, don't report long 2704 * frames as errors since they could be vlans. 2705 */ 2706 if ((rxstat & DC_RXSTAT_RXERR)) { 2707 if (!(rxstat & DC_RXSTAT_GIANT) || 2708 (rxstat & (DC_RXSTAT_CRCERR | DC_RXSTAT_DRIBBLE | 2709 DC_RXSTAT_MIIERE | DC_RXSTAT_COLLSEEN | 2710 DC_RXSTAT_RUNT | DC_RXSTAT_DE))) { 2711 ifp->if_ierrors++; 2712 if (rxstat & DC_RXSTAT_COLLSEEN) 2713 ifp->if_collisions++; 2714 dc_newbuf(sc, i, 0); 2715 if (rxstat & DC_RXSTAT_CRCERR) { 2716 DC_INC(i, DC_RX_LIST_CNT); 2717 continue; 2718 } else { 2719 dc_init_locked(sc); 2720 return; 2721 } 2722 } 2723 } 2724 2725 /* No errors; receive the packet. */ 2726 total_len -= ETHER_CRC_LEN; 2727 #ifdef __NO_STRICT_ALIGNMENT 2728 /* 2729 * On architectures without alignment problems we try to 2730 * allocate a new buffer for the receive ring, and pass up 2731 * the one where the packet is already, saving the expensive 2732 * copy done in m_devget(). 2733 * If we are on an architecture with alignment problems, or 2734 * if the allocation fails, then use m_devget and leave the 2735 * existing buffer in the receive ring. 2736 */ 2737 if (dc_newbuf(sc, i, 1) == 0) { 2738 m->m_pkthdr.rcvif = ifp; 2739 m->m_pkthdr.len = m->m_len = total_len; 2740 DC_INC(i, DC_RX_LIST_CNT); 2741 } else 2742 #endif 2743 { 2744 m0 = m_devget(mtod(m, char *), total_len, 2745 ETHER_ALIGN, ifp, NULL); 2746 dc_newbuf(sc, i, 0); 2747 DC_INC(i, DC_RX_LIST_CNT); 2748 if (m0 == NULL) { 2749 ifp->if_ierrors++; 2750 continue; 2751 } 2752 m = m0; 2753 } 2754 2755 ifp->if_ipackets++; 2756 DC_UNLOCK(sc); 2757 (*ifp->if_input)(ifp, m); 2758 DC_LOCK(sc); 2759 } 2760 2761 sc->dc_cdata.dc_rx_prod = i; 2762 } 2763 2764 /* 2765 * A frame was downloaded to the chip. It's safe for us to clean up 2766 * the list buffers. 2767 */ 2768 2769 static void 2770 dc_txeof(struct dc_softc *sc) 2771 { 2772 struct dc_desc *cur_tx = NULL; 2773 struct ifnet *ifp; 2774 int idx; 2775 u_int32_t ctl, txstat; 2776 2777 ifp = sc->dc_ifp; 2778 2779 /* 2780 * Go through our tx list and free mbufs for those 2781 * frames that have been transmitted. 2782 */ 2783 bus_dmamap_sync(sc->dc_ltag, sc->dc_lmap, BUS_DMASYNC_POSTREAD); 2784 idx = sc->dc_cdata.dc_tx_cons; 2785 while (idx != sc->dc_cdata.dc_tx_prod) { 2786 2787 cur_tx = &sc->dc_ldata->dc_tx_list[idx]; 2788 txstat = le32toh(cur_tx->dc_status); 2789 ctl = le32toh(cur_tx->dc_ctl); 2790 2791 if (txstat & DC_TXSTAT_OWN) 2792 break; 2793 2794 if (!(ctl & DC_TXCTL_LASTFRAG) || ctl & DC_TXCTL_SETUP) { 2795 if (ctl & DC_TXCTL_SETUP) { 2796 /* 2797 * Yes, the PNIC is so brain damaged 2798 * that it will sometimes generate a TX 2799 * underrun error while DMAing the RX 2800 * filter setup frame. If we detect this, 2801 * we have to send the setup frame again, 2802 * or else the filter won't be programmed 2803 * correctly. 2804 */ 2805 if (DC_IS_PNIC(sc)) { 2806 if (txstat & DC_TXSTAT_ERRSUM) 2807 dc_setfilt(sc); 2808 } 2809 sc->dc_cdata.dc_tx_chain[idx] = NULL; 2810 } 2811 sc->dc_cdata.dc_tx_cnt--; 2812 DC_INC(idx, DC_TX_LIST_CNT); 2813 continue; 2814 } 2815 2816 if (DC_IS_XIRCOM(sc) || DC_IS_CONEXANT(sc)) { 2817 /* 2818 * XXX: Why does my Xircom taunt me so? 2819 * For some reason it likes setting the CARRLOST flag 2820 * even when the carrier is there. wtf?!? 2821 * Who knows, but Conexant chips have the 2822 * same problem. Maybe they took lessons 2823 * from Xircom. 2824 */ 2825 if (/*sc->dc_type == DC_TYPE_21143 &&*/ 2826 sc->dc_pmode == DC_PMODE_MII && 2827 ((txstat & 0xFFFF) & ~(DC_TXSTAT_ERRSUM | 2828 DC_TXSTAT_NOCARRIER))) 2829 txstat &= ~DC_TXSTAT_ERRSUM; 2830 } else { 2831 if (/*sc->dc_type == DC_TYPE_21143 &&*/ 2832 sc->dc_pmode == DC_PMODE_MII && 2833 ((txstat & 0xFFFF) & ~(DC_TXSTAT_ERRSUM | 2834 DC_TXSTAT_NOCARRIER | DC_TXSTAT_CARRLOST))) 2835 txstat &= ~DC_TXSTAT_ERRSUM; 2836 } 2837 2838 if (txstat & DC_TXSTAT_ERRSUM) { 2839 ifp->if_oerrors++; 2840 if (txstat & DC_TXSTAT_EXCESSCOLL) 2841 ifp->if_collisions++; 2842 if (txstat & DC_TXSTAT_LATECOLL) 2843 ifp->if_collisions++; 2844 if (!(txstat & DC_TXSTAT_UNDERRUN)) { 2845 dc_init_locked(sc); 2846 return; 2847 } 2848 } 2849 2850 ifp->if_collisions += (txstat & DC_TXSTAT_COLLCNT) >> 3; 2851 2852 ifp->if_opackets++; 2853 if (sc->dc_cdata.dc_tx_chain[idx] != NULL) { 2854 bus_dmamap_sync(sc->dc_mtag, 2855 sc->dc_cdata.dc_tx_map[idx], 2856 BUS_DMASYNC_POSTWRITE); 2857 bus_dmamap_unload(sc->dc_mtag, 2858 sc->dc_cdata.dc_tx_map[idx]); 2859 m_freem(sc->dc_cdata.dc_tx_chain[idx]); 2860 sc->dc_cdata.dc_tx_chain[idx] = NULL; 2861 } 2862 2863 sc->dc_cdata.dc_tx_cnt--; 2864 DC_INC(idx, DC_TX_LIST_CNT); 2865 } 2866 2867 if (idx != sc->dc_cdata.dc_tx_cons) { 2868 /* Some buffers have been freed. */ 2869 sc->dc_cdata.dc_tx_cons = idx; 2870 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 2871 } 2872 ifp->if_timer = (sc->dc_cdata.dc_tx_cnt == 0) ? 0 : 5; 2873 } 2874 2875 static void 2876 dc_tick(void *xsc) 2877 { 2878 struct dc_softc *sc; 2879 struct mii_data *mii; 2880 struct ifnet *ifp; 2881 u_int32_t r; 2882 2883 sc = xsc; 2884 DC_LOCK_ASSERT(sc); 2885 ifp = sc->dc_ifp; 2886 mii = device_get_softc(sc->dc_miibus); 2887 2888 if (sc->dc_flags & DC_REDUCED_MII_POLL) { 2889 if (sc->dc_flags & DC_21143_NWAY) { 2890 r = CSR_READ_4(sc, DC_10BTSTAT); 2891 if (IFM_SUBTYPE(mii->mii_media_active) == 2892 IFM_100_TX && (r & DC_TSTAT_LS100)) { 2893 sc->dc_link = 0; 2894 mii_mediachg(mii); 2895 } 2896 if (IFM_SUBTYPE(mii->mii_media_active) == 2897 IFM_10_T && (r & DC_TSTAT_LS10)) { 2898 sc->dc_link = 0; 2899 mii_mediachg(mii); 2900 } 2901 if (sc->dc_link == 0) 2902 mii_tick(mii); 2903 } else { 2904 r = CSR_READ_4(sc, DC_ISR); 2905 if ((r & DC_ISR_RX_STATE) == DC_RXSTATE_WAIT && 2906 sc->dc_cdata.dc_tx_cnt == 0) { 2907 mii_tick(mii); 2908 if (!(mii->mii_media_status & IFM_ACTIVE)) 2909 sc->dc_link = 0; 2910 } 2911 } 2912 } else 2913 mii_tick(mii); 2914 2915 /* 2916 * When the init routine completes, we expect to be able to send 2917 * packets right away, and in fact the network code will send a 2918 * gratuitous ARP the moment the init routine marks the interface 2919 * as running. However, even though the MAC may have been initialized, 2920 * there may be a delay of a few seconds before the PHY completes 2921 * autonegotiation and the link is brought up. Any transmissions 2922 * made during that delay will be lost. Dealing with this is tricky: 2923 * we can't just pause in the init routine while waiting for the 2924 * PHY to come ready since that would bring the whole system to 2925 * a screeching halt for several seconds. 2926 * 2927 * What we do here is prevent the TX start routine from sending 2928 * any packets until a link has been established. After the 2929 * interface has been initialized, the tick routine will poll 2930 * the state of the PHY until the IFM_ACTIVE flag is set. Until 2931 * that time, packets will stay in the send queue, and once the 2932 * link comes up, they will be flushed out to the wire. 2933 */ 2934 if (!sc->dc_link && mii->mii_media_status & IFM_ACTIVE && 2935 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) { 2936 sc->dc_link++; 2937 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 2938 dc_start_locked(ifp); 2939 } 2940 2941 if (sc->dc_flags & DC_21143_NWAY && !sc->dc_link) 2942 callout_reset(&sc->dc_stat_ch, hz/10, dc_tick, sc); 2943 else 2944 callout_reset(&sc->dc_stat_ch, hz, dc_tick, sc); 2945 } 2946 2947 /* 2948 * A transmit underrun has occurred. Back off the transmit threshold, 2949 * or switch to store and forward mode if we have to. 2950 */ 2951 static void 2952 dc_tx_underrun(struct dc_softc *sc) 2953 { 2954 u_int32_t isr; 2955 int i; 2956 2957 if (DC_IS_DAVICOM(sc)) 2958 dc_init_locked(sc); 2959 2960 if (DC_IS_INTEL(sc)) { 2961 /* 2962 * The real 21143 requires that the transmitter be idle 2963 * in order to change the transmit threshold or store 2964 * and forward state. 2965 */ 2966 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_TX_ON); 2967 2968 for (i = 0; i < DC_TIMEOUT; i++) { 2969 isr = CSR_READ_4(sc, DC_ISR); 2970 if (isr & DC_ISR_TX_IDLE) 2971 break; 2972 DELAY(10); 2973 } 2974 if (i == DC_TIMEOUT) { 2975 device_printf(sc->dc_dev, 2976 "%s: failed to force tx to idle state\n", 2977 __func__); 2978 dc_init_locked(sc); 2979 } 2980 } 2981 2982 device_printf(sc->dc_dev, "TX underrun -- "); 2983 sc->dc_txthresh += DC_TXTHRESH_INC; 2984 if (sc->dc_txthresh > DC_TXTHRESH_MAX) { 2985 printf("using store and forward mode\n"); 2986 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_STORENFWD); 2987 } else { 2988 printf("increasing TX threshold\n"); 2989 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_TX_THRESH); 2990 DC_SETBIT(sc, DC_NETCFG, sc->dc_txthresh); 2991 } 2992 2993 if (DC_IS_INTEL(sc)) 2994 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_TX_ON); 2995 } 2996 2997 #ifdef DEVICE_POLLING 2998 static poll_handler_t dc_poll; 2999 3000 static void 3001 dc_poll(struct ifnet *ifp, enum poll_cmd cmd, int count) 3002 { 3003 struct dc_softc *sc = ifp->if_softc; 3004 3005 DC_LOCK(sc); 3006 3007 if (!(ifp->if_drv_flags & IFF_DRV_RUNNING)) { 3008 DC_UNLOCK(sc); 3009 return; 3010 } 3011 3012 sc->rxcycles = count; 3013 dc_rxeof(sc); 3014 dc_txeof(sc); 3015 if (!IFQ_IS_EMPTY(&ifp->if_snd) && 3016 !(ifp->if_drv_flags & IFF_DRV_OACTIVE)) 3017 dc_start_locked(ifp); 3018 3019 if (cmd == POLL_AND_CHECK_STATUS) { /* also check status register */ 3020 u_int32_t status; 3021 3022 status = CSR_READ_4(sc, DC_ISR); 3023 status &= (DC_ISR_RX_WATDOGTIMEO | DC_ISR_RX_NOBUF | 3024 DC_ISR_TX_NOBUF | DC_ISR_TX_IDLE | DC_ISR_TX_UNDERRUN | 3025 DC_ISR_BUS_ERR); 3026 if (!status) { 3027 DC_UNLOCK(sc); 3028 return; 3029 } 3030 /* ack what we have */ 3031 CSR_WRITE_4(sc, DC_ISR, status); 3032 3033 if (status & (DC_ISR_RX_WATDOGTIMEO | DC_ISR_RX_NOBUF)) { 3034 u_int32_t r = CSR_READ_4(sc, DC_FRAMESDISCARDED); 3035 ifp->if_ierrors += (r & 0xffff) + ((r >> 17) & 0x7ff); 3036 3037 if (dc_rx_resync(sc)) 3038 dc_rxeof(sc); 3039 } 3040 /* restart transmit unit if necessary */ 3041 if (status & DC_ISR_TX_IDLE && sc->dc_cdata.dc_tx_cnt) 3042 CSR_WRITE_4(sc, DC_TXSTART, 0xFFFFFFFF); 3043 3044 if (status & DC_ISR_TX_UNDERRUN) 3045 dc_tx_underrun(sc); 3046 3047 if (status & DC_ISR_BUS_ERR) { 3048 if_printf(ifp, "%s: bus error\n", __func__); 3049 dc_reset(sc); 3050 dc_init_locked(sc); 3051 } 3052 } 3053 DC_UNLOCK(sc); 3054 } 3055 #endif /* DEVICE_POLLING */ 3056 3057 static void 3058 dc_intr(void *arg) 3059 { 3060 struct dc_softc *sc; 3061 struct ifnet *ifp; 3062 u_int32_t status; 3063 3064 sc = arg; 3065 3066 if (sc->suspended) 3067 return; 3068 3069 if ((CSR_READ_4(sc, DC_ISR) & DC_INTRS) == 0) 3070 return; 3071 3072 DC_LOCK(sc); 3073 ifp = sc->dc_ifp; 3074 #ifdef DEVICE_POLLING 3075 if (ifp->if_capenable & IFCAP_POLLING) { 3076 DC_UNLOCK(sc); 3077 return; 3078 } 3079 #endif 3080 3081 /* Suppress unwanted interrupts */ 3082 if (!(ifp->if_flags & IFF_UP)) { 3083 if (CSR_READ_4(sc, DC_ISR) & DC_INTRS) 3084 dc_stop(sc); 3085 DC_UNLOCK(sc); 3086 return; 3087 } 3088 3089 /* Disable interrupts. */ 3090 CSR_WRITE_4(sc, DC_IMR, 0x00000000); 3091 3092 while (((status = CSR_READ_4(sc, DC_ISR)) & DC_INTRS) && 3093 status != 0xFFFFFFFF && 3094 (ifp->if_drv_flags & IFF_DRV_RUNNING)) { 3095 3096 CSR_WRITE_4(sc, DC_ISR, status); 3097 3098 if (status & DC_ISR_RX_OK) { 3099 int curpkts; 3100 curpkts = ifp->if_ipackets; 3101 dc_rxeof(sc); 3102 if (curpkts == ifp->if_ipackets) { 3103 while (dc_rx_resync(sc)) 3104 dc_rxeof(sc); 3105 } 3106 } 3107 3108 if (status & (DC_ISR_TX_OK | DC_ISR_TX_NOBUF)) 3109 dc_txeof(sc); 3110 3111 if (status & DC_ISR_TX_IDLE) { 3112 dc_txeof(sc); 3113 if (sc->dc_cdata.dc_tx_cnt) { 3114 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_TX_ON); 3115 CSR_WRITE_4(sc, DC_TXSTART, 0xFFFFFFFF); 3116 } 3117 } 3118 3119 if (status & DC_ISR_TX_UNDERRUN) 3120 dc_tx_underrun(sc); 3121 3122 if ((status & DC_ISR_RX_WATDOGTIMEO) 3123 || (status & DC_ISR_RX_NOBUF)) { 3124 int curpkts; 3125 curpkts = ifp->if_ipackets; 3126 dc_rxeof(sc); 3127 if (curpkts == ifp->if_ipackets) { 3128 while (dc_rx_resync(sc)) 3129 dc_rxeof(sc); 3130 } 3131 } 3132 3133 if (status & DC_ISR_BUS_ERR) { 3134 dc_reset(sc); 3135 dc_init_locked(sc); 3136 } 3137 } 3138 3139 /* Re-enable interrupts. */ 3140 CSR_WRITE_4(sc, DC_IMR, DC_INTRS); 3141 3142 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 3143 dc_start_locked(ifp); 3144 3145 DC_UNLOCK(sc); 3146 } 3147 3148 static void 3149 dc_dma_map_txbuf(arg, segs, nseg, mapsize, error) 3150 void *arg; 3151 bus_dma_segment_t *segs; 3152 int nseg; 3153 bus_size_t mapsize; 3154 int error; 3155 { 3156 struct dc_softc *sc; 3157 struct dc_desc *f; 3158 int cur, first, frag, i; 3159 3160 sc = arg; 3161 if (error) { 3162 sc->dc_cdata.dc_tx_err = error; 3163 return; 3164 } 3165 3166 first = cur = frag = sc->dc_cdata.dc_tx_prod; 3167 for (i = 0; i < nseg; i++) { 3168 if ((sc->dc_flags & DC_TX_ADMTEK_WAR) && 3169 (frag == (DC_TX_LIST_CNT - 1)) && 3170 (first != sc->dc_cdata.dc_tx_first)) { 3171 bus_dmamap_unload(sc->dc_mtag, 3172 sc->dc_cdata.dc_tx_map[first]); 3173 sc->dc_cdata.dc_tx_err = ENOBUFS; 3174 return; 3175 } 3176 3177 f = &sc->dc_ldata->dc_tx_list[frag]; 3178 f->dc_ctl = htole32(DC_TXCTL_TLINK | segs[i].ds_len); 3179 if (i == 0) { 3180 f->dc_status = 0; 3181 f->dc_ctl |= htole32(DC_TXCTL_FIRSTFRAG); 3182 } else 3183 f->dc_status = htole32(DC_TXSTAT_OWN); 3184 f->dc_data = htole32(segs[i].ds_addr); 3185 cur = frag; 3186 DC_INC(frag, DC_TX_LIST_CNT); 3187 } 3188 3189 sc->dc_cdata.dc_tx_err = 0; 3190 sc->dc_cdata.dc_tx_prod = frag; 3191 sc->dc_cdata.dc_tx_cnt += nseg; 3192 sc->dc_ldata->dc_tx_list[cur].dc_ctl |= htole32(DC_TXCTL_LASTFRAG); 3193 sc->dc_cdata.dc_tx_chain[cur] = sc->dc_cdata.dc_tx_mapping; 3194 if (sc->dc_flags & DC_TX_INTR_FIRSTFRAG) 3195 sc->dc_ldata->dc_tx_list[first].dc_ctl |= 3196 htole32(DC_TXCTL_FINT); 3197 if (sc->dc_flags & DC_TX_INTR_ALWAYS) 3198 sc->dc_ldata->dc_tx_list[cur].dc_ctl |= htole32(DC_TXCTL_FINT); 3199 if (sc->dc_flags & DC_TX_USE_TX_INTR && sc->dc_cdata.dc_tx_cnt > 64) 3200 sc->dc_ldata->dc_tx_list[cur].dc_ctl |= htole32(DC_TXCTL_FINT); 3201 sc->dc_ldata->dc_tx_list[first].dc_status = htole32(DC_TXSTAT_OWN); 3202 } 3203 3204 /* 3205 * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data 3206 * pointers to the fragment pointers. 3207 */ 3208 static int 3209 dc_encap(struct dc_softc *sc, struct mbuf **m_head) 3210 { 3211 struct mbuf *m; 3212 int error, idx, chainlen = 0; 3213 3214 /* 3215 * If there's no way we can send any packets, return now. 3216 */ 3217 if (DC_TX_LIST_CNT - sc->dc_cdata.dc_tx_cnt < 6) 3218 return (ENOBUFS); 3219 3220 /* 3221 * Count the number of frags in this chain to see if 3222 * we need to m_defrag. Since the descriptor list is shared 3223 * by all packets, we'll m_defrag long chains so that they 3224 * do not use up the entire list, even if they would fit. 3225 */ 3226 for (m = *m_head; m != NULL; m = m->m_next) 3227 chainlen++; 3228 3229 if ((chainlen > DC_TX_LIST_CNT / 4) || 3230 ((DC_TX_LIST_CNT - (chainlen + sc->dc_cdata.dc_tx_cnt)) < 6)) { 3231 m = m_defrag(*m_head, M_DONTWAIT); 3232 if (m == NULL) 3233 return (ENOBUFS); 3234 *m_head = m; 3235 } 3236 3237 /* 3238 * Start packing the mbufs in this chain into 3239 * the fragment pointers. Stop when we run out 3240 * of fragments or hit the end of the mbuf chain. 3241 */ 3242 idx = sc->dc_cdata.dc_tx_prod; 3243 sc->dc_cdata.dc_tx_mapping = *m_head; 3244 error = bus_dmamap_load_mbuf(sc->dc_mtag, sc->dc_cdata.dc_tx_map[idx], 3245 *m_head, dc_dma_map_txbuf, sc, 0); 3246 if (error) 3247 return (error); 3248 if (sc->dc_cdata.dc_tx_err != 0) 3249 return (sc->dc_cdata.dc_tx_err); 3250 bus_dmamap_sync(sc->dc_mtag, sc->dc_cdata.dc_tx_map[idx], 3251 BUS_DMASYNC_PREWRITE); 3252 bus_dmamap_sync(sc->dc_ltag, sc->dc_lmap, 3253 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3254 return (0); 3255 } 3256 3257 /* 3258 * Main transmit routine. To avoid having to do mbuf copies, we put pointers 3259 * to the mbuf data regions directly in the transmit lists. We also save a 3260 * copy of the pointers since the transmit list fragment pointers are 3261 * physical addresses. 3262 */ 3263 3264 static void 3265 dc_start(struct ifnet *ifp) 3266 { 3267 struct dc_softc *sc; 3268 3269 sc = ifp->if_softc; 3270 DC_LOCK(sc); 3271 dc_start_locked(ifp); 3272 DC_UNLOCK(sc); 3273 } 3274 3275 static void 3276 dc_start_locked(struct ifnet *ifp) 3277 { 3278 struct dc_softc *sc; 3279 struct mbuf *m_head = NULL, *m; 3280 unsigned int queued = 0; 3281 int idx; 3282 3283 sc = ifp->if_softc; 3284 3285 DC_LOCK_ASSERT(sc); 3286 3287 if (!sc->dc_link && ifp->if_snd.ifq_len < 10) 3288 return; 3289 3290 if (ifp->if_drv_flags & IFF_DRV_OACTIVE) 3291 return; 3292 3293 idx = sc->dc_cdata.dc_tx_first = sc->dc_cdata.dc_tx_prod; 3294 3295 while (sc->dc_cdata.dc_tx_chain[idx] == NULL) { 3296 IFQ_DRV_DEQUEUE(&ifp->if_snd, m_head); 3297 if (m_head == NULL) 3298 break; 3299 3300 if (sc->dc_flags & DC_TX_COALESCE && 3301 (m_head->m_next != NULL || 3302 sc->dc_flags & DC_TX_ALIGN)) { 3303 m = m_defrag(m_head, M_DONTWAIT); 3304 if (m == NULL) { 3305 IFQ_DRV_PREPEND(&ifp->if_snd, m_head); 3306 ifp->if_drv_flags |= IFF_DRV_OACTIVE; 3307 break; 3308 } else { 3309 m_head = m; 3310 } 3311 } 3312 3313 if (dc_encap(sc, &m_head)) { 3314 IFQ_DRV_PREPEND(&ifp->if_snd, m_head); 3315 ifp->if_drv_flags |= IFF_DRV_OACTIVE; 3316 break; 3317 } 3318 idx = sc->dc_cdata.dc_tx_prod; 3319 3320 queued++; 3321 /* 3322 * If there's a BPF listener, bounce a copy of this frame 3323 * to him. 3324 */ 3325 BPF_MTAP(ifp, m_head); 3326 3327 if (sc->dc_flags & DC_TX_ONE) { 3328 ifp->if_drv_flags |= IFF_DRV_OACTIVE; 3329 break; 3330 } 3331 } 3332 3333 if (queued > 0) { 3334 /* Transmit */ 3335 if (!(sc->dc_flags & DC_TX_POLL)) 3336 CSR_WRITE_4(sc, DC_TXSTART, 0xFFFFFFFF); 3337 3338 /* 3339 * Set a timeout in case the chip goes out to lunch. 3340 */ 3341 ifp->if_timer = 5; 3342 } 3343 } 3344 3345 static void 3346 dc_init(void *xsc) 3347 { 3348 struct dc_softc *sc = xsc; 3349 3350 DC_LOCK(sc); 3351 dc_init_locked(sc); 3352 DC_UNLOCK(sc); 3353 } 3354 3355 static void 3356 dc_init_locked(struct dc_softc *sc) 3357 { 3358 struct ifnet *ifp = sc->dc_ifp; 3359 struct mii_data *mii; 3360 3361 DC_LOCK_ASSERT(sc); 3362 3363 mii = device_get_softc(sc->dc_miibus); 3364 3365 /* 3366 * Cancel pending I/O and free all RX/TX buffers. 3367 */ 3368 dc_stop(sc); 3369 dc_reset(sc); 3370 3371 /* 3372 * Set cache alignment and burst length. 3373 */ 3374 if (DC_IS_ASIX(sc) || DC_IS_DAVICOM(sc)) 3375 CSR_WRITE_4(sc, DC_BUSCTL, 0); 3376 else 3377 CSR_WRITE_4(sc, DC_BUSCTL, DC_BUSCTL_MRME | DC_BUSCTL_MRLE); 3378 /* 3379 * Evenly share the bus between receive and transmit process. 3380 */ 3381 if (DC_IS_INTEL(sc)) 3382 DC_SETBIT(sc, DC_BUSCTL, DC_BUSCTL_ARBITRATION); 3383 if (DC_IS_DAVICOM(sc) || DC_IS_INTEL(sc)) { 3384 DC_SETBIT(sc, DC_BUSCTL, DC_BURSTLEN_USECA); 3385 } else { 3386 DC_SETBIT(sc, DC_BUSCTL, DC_BURSTLEN_16LONG); 3387 } 3388 if (sc->dc_flags & DC_TX_POLL) 3389 DC_SETBIT(sc, DC_BUSCTL, DC_TXPOLL_1); 3390 switch(sc->dc_cachesize) { 3391 case 32: 3392 DC_SETBIT(sc, DC_BUSCTL, DC_CACHEALIGN_32LONG); 3393 break; 3394 case 16: 3395 DC_SETBIT(sc, DC_BUSCTL, DC_CACHEALIGN_16LONG); 3396 break; 3397 case 8: 3398 DC_SETBIT(sc, DC_BUSCTL, DC_CACHEALIGN_8LONG); 3399 break; 3400 case 0: 3401 default: 3402 DC_SETBIT(sc, DC_BUSCTL, DC_CACHEALIGN_NONE); 3403 break; 3404 } 3405 3406 if (sc->dc_flags & DC_TX_STORENFWD) 3407 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_STORENFWD); 3408 else { 3409 if (sc->dc_txthresh > DC_TXTHRESH_MAX) { 3410 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_STORENFWD); 3411 } else { 3412 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_STORENFWD); 3413 DC_SETBIT(sc, DC_NETCFG, sc->dc_txthresh); 3414 } 3415 } 3416 3417 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_NO_RXCRC); 3418 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_TX_BACKOFF); 3419 3420 if (DC_IS_MACRONIX(sc) || DC_IS_PNICII(sc)) { 3421 /* 3422 * The app notes for the 98713 and 98715A say that 3423 * in order to have the chips operate properly, a magic 3424 * number must be written to CSR16. Macronix does not 3425 * document the meaning of these bits so there's no way 3426 * to know exactly what they do. The 98713 has a magic 3427 * number all its own; the rest all use a different one. 3428 */ 3429 DC_CLRBIT(sc, DC_MX_MAGICPACKET, 0xFFFF0000); 3430 if (sc->dc_type == DC_TYPE_98713) 3431 DC_SETBIT(sc, DC_MX_MAGICPACKET, DC_MX_MAGIC_98713); 3432 else 3433 DC_SETBIT(sc, DC_MX_MAGICPACKET, DC_MX_MAGIC_98715); 3434 } 3435 3436 if (DC_IS_XIRCOM(sc)) { 3437 /* 3438 * setup General Purpose Port mode and data so the tulip 3439 * can talk to the MII. 3440 */ 3441 CSR_WRITE_4(sc, DC_SIAGP, DC_SIAGP_WRITE_EN | DC_SIAGP_INT1_EN | 3442 DC_SIAGP_MD_GP2_OUTPUT | DC_SIAGP_MD_GP0_OUTPUT); 3443 DELAY(10); 3444 CSR_WRITE_4(sc, DC_SIAGP, DC_SIAGP_INT1_EN | 3445 DC_SIAGP_MD_GP2_OUTPUT | DC_SIAGP_MD_GP0_OUTPUT); 3446 DELAY(10); 3447 } 3448 3449 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_TX_THRESH); 3450 DC_SETBIT(sc, DC_NETCFG, DC_TXTHRESH_MIN); 3451 3452 /* Init circular RX list. */ 3453 if (dc_list_rx_init(sc) == ENOBUFS) { 3454 device_printf(sc->dc_dev, 3455 "initialization failed: no memory for rx buffers\n"); 3456 dc_stop(sc); 3457 return; 3458 } 3459 3460 /* 3461 * Init TX descriptors. 3462 */ 3463 dc_list_tx_init(sc); 3464 3465 /* 3466 * Load the address of the RX list. 3467 */ 3468 CSR_WRITE_4(sc, DC_RXADDR, DC_RXDESC(sc, 0)); 3469 CSR_WRITE_4(sc, DC_TXADDR, DC_TXDESC(sc, 0)); 3470 3471 /* 3472 * Enable interrupts. 3473 */ 3474 #ifdef DEVICE_POLLING 3475 /* 3476 * ... but only if we are not polling, and make sure they are off in 3477 * the case of polling. Some cards (e.g. fxp) turn interrupts on 3478 * after a reset. 3479 */ 3480 if (ifp->if_capenable & IFCAP_POLLING) 3481 CSR_WRITE_4(sc, DC_IMR, 0x00000000); 3482 else 3483 #endif 3484 CSR_WRITE_4(sc, DC_IMR, DC_INTRS); 3485 CSR_WRITE_4(sc, DC_ISR, 0xFFFFFFFF); 3486 3487 /* Enable transmitter. */ 3488 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_TX_ON); 3489 3490 /* 3491 * If this is an Intel 21143 and we're not using the 3492 * MII port, program the LED control pins so we get 3493 * link and activity indications. 3494 */ 3495 if (sc->dc_flags & DC_TULIP_LEDS) { 3496 CSR_WRITE_4(sc, DC_WATCHDOG, 3497 DC_WDOG_CTLWREN | DC_WDOG_LINK | DC_WDOG_ACTIVITY); 3498 CSR_WRITE_4(sc, DC_WATCHDOG, 0); 3499 } 3500 3501 /* 3502 * Load the RX/multicast filter. We do this sort of late 3503 * because the filter programming scheme on the 21143 and 3504 * some clones requires DMAing a setup frame via the TX 3505 * engine, and we need the transmitter enabled for that. 3506 */ 3507 dc_setfilt(sc); 3508 3509 /* Enable receiver. */ 3510 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_ON); 3511 CSR_WRITE_4(sc, DC_RXSTART, 0xFFFFFFFF); 3512 3513 mii_mediachg(mii); 3514 dc_setcfg(sc, sc->dc_if_media); 3515 3516 ifp->if_drv_flags |= IFF_DRV_RUNNING; 3517 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 3518 3519 /* Don't start the ticker if this is a homePNA link. */ 3520 if (IFM_SUBTYPE(mii->mii_media.ifm_media) == IFM_HPNA_1) 3521 sc->dc_link = 1; 3522 else { 3523 if (sc->dc_flags & DC_21143_NWAY) 3524 callout_reset(&sc->dc_stat_ch, hz/10, dc_tick, sc); 3525 else 3526 callout_reset(&sc->dc_stat_ch, hz, dc_tick, sc); 3527 } 3528 } 3529 3530 /* 3531 * Set media options. 3532 */ 3533 static int 3534 dc_ifmedia_upd(struct ifnet *ifp) 3535 { 3536 struct dc_softc *sc; 3537 struct mii_data *mii; 3538 struct ifmedia *ifm; 3539 3540 sc = ifp->if_softc; 3541 mii = device_get_softc(sc->dc_miibus); 3542 DC_LOCK(sc); 3543 mii_mediachg(mii); 3544 ifm = &mii->mii_media; 3545 3546 if (DC_IS_DAVICOM(sc) && 3547 IFM_SUBTYPE(ifm->ifm_media) == IFM_HPNA_1) 3548 dc_setcfg(sc, ifm->ifm_media); 3549 else 3550 sc->dc_link = 0; 3551 DC_UNLOCK(sc); 3552 3553 return (0); 3554 } 3555 3556 /* 3557 * Report current media status. 3558 */ 3559 static void 3560 dc_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 3561 { 3562 struct dc_softc *sc; 3563 struct mii_data *mii; 3564 struct ifmedia *ifm; 3565 3566 sc = ifp->if_softc; 3567 mii = device_get_softc(sc->dc_miibus); 3568 DC_LOCK(sc); 3569 mii_pollstat(mii); 3570 ifm = &mii->mii_media; 3571 if (DC_IS_DAVICOM(sc)) { 3572 if (IFM_SUBTYPE(ifm->ifm_media) == IFM_HPNA_1) { 3573 ifmr->ifm_active = ifm->ifm_media; 3574 ifmr->ifm_status = 0; 3575 DC_UNLOCK(sc); 3576 return; 3577 } 3578 } 3579 ifmr->ifm_active = mii->mii_media_active; 3580 ifmr->ifm_status = mii->mii_media_status; 3581 DC_UNLOCK(sc); 3582 } 3583 3584 static int 3585 dc_ioctl(struct ifnet *ifp, u_long command, caddr_t data) 3586 { 3587 struct dc_softc *sc = ifp->if_softc; 3588 struct ifreq *ifr = (struct ifreq *)data; 3589 struct mii_data *mii; 3590 int error = 0; 3591 3592 switch (command) { 3593 case SIOCSIFFLAGS: 3594 DC_LOCK(sc); 3595 if (ifp->if_flags & IFF_UP) { 3596 int need_setfilt = (ifp->if_flags ^ sc->dc_if_flags) & 3597 (IFF_PROMISC | IFF_ALLMULTI); 3598 3599 if (ifp->if_drv_flags & IFF_DRV_RUNNING) { 3600 if (need_setfilt) 3601 dc_setfilt(sc); 3602 } else { 3603 sc->dc_txthresh = 0; 3604 dc_init_locked(sc); 3605 } 3606 } else { 3607 if (ifp->if_drv_flags & IFF_DRV_RUNNING) 3608 dc_stop(sc); 3609 } 3610 sc->dc_if_flags = ifp->if_flags; 3611 DC_UNLOCK(sc); 3612 error = 0; 3613 break; 3614 case SIOCADDMULTI: 3615 case SIOCDELMULTI: 3616 DC_LOCK(sc); 3617 dc_setfilt(sc); 3618 DC_UNLOCK(sc); 3619 error = 0; 3620 break; 3621 case SIOCGIFMEDIA: 3622 case SIOCSIFMEDIA: 3623 mii = device_get_softc(sc->dc_miibus); 3624 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 3625 break; 3626 case SIOCSIFCAP: 3627 #ifdef DEVICE_POLLING 3628 if (ifr->ifr_reqcap & IFCAP_POLLING && 3629 !(ifp->if_capenable & IFCAP_POLLING)) { 3630 error = ether_poll_register(dc_poll, ifp); 3631 if (error) 3632 return(error); 3633 DC_LOCK(sc); 3634 /* Disable interrupts */ 3635 CSR_WRITE_4(sc, DC_IMR, 0x00000000); 3636 ifp->if_capenable |= IFCAP_POLLING; 3637 DC_UNLOCK(sc); 3638 return (error); 3639 3640 } 3641 if (!(ifr->ifr_reqcap & IFCAP_POLLING) && 3642 ifp->if_capenable & IFCAP_POLLING) { 3643 error = ether_poll_deregister(ifp); 3644 /* Enable interrupts. */ 3645 DC_LOCK(sc); 3646 CSR_WRITE_4(sc, DC_IMR, DC_INTRS); 3647 ifp->if_capenable &= ~IFCAP_POLLING; 3648 DC_UNLOCK(sc); 3649 return (error); 3650 } 3651 #endif /* DEVICE_POLLING */ 3652 break; 3653 default: 3654 error = ether_ioctl(ifp, command, data); 3655 break; 3656 } 3657 3658 return (error); 3659 } 3660 3661 static void 3662 dc_watchdog(struct ifnet *ifp) 3663 { 3664 struct dc_softc *sc; 3665 3666 sc = ifp->if_softc; 3667 3668 DC_LOCK(sc); 3669 3670 ifp->if_oerrors++; 3671 if_printf(ifp, "watchdog timeout\n"); 3672 3673 dc_stop(sc); 3674 dc_reset(sc); 3675 dc_init_locked(sc); 3676 3677 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 3678 dc_start_locked(ifp); 3679 3680 DC_UNLOCK(sc); 3681 } 3682 3683 /* 3684 * Stop the adapter and free any mbufs allocated to the 3685 * RX and TX lists. 3686 */ 3687 static void 3688 dc_stop(struct dc_softc *sc) 3689 { 3690 struct ifnet *ifp; 3691 struct dc_list_data *ld; 3692 struct dc_chain_data *cd; 3693 int i; 3694 u_int32_t ctl; 3695 3696 DC_LOCK_ASSERT(sc); 3697 3698 ifp = sc->dc_ifp; 3699 ifp->if_timer = 0; 3700 ld = sc->dc_ldata; 3701 cd = &sc->dc_cdata; 3702 3703 callout_stop(&sc->dc_stat_ch); 3704 3705 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE); 3706 3707 DC_CLRBIT(sc, DC_NETCFG, (DC_NETCFG_RX_ON | DC_NETCFG_TX_ON)); 3708 CSR_WRITE_4(sc, DC_IMR, 0x00000000); 3709 CSR_WRITE_4(sc, DC_TXADDR, 0x00000000); 3710 CSR_WRITE_4(sc, DC_RXADDR, 0x00000000); 3711 sc->dc_link = 0; 3712 3713 /* 3714 * Free data in the RX lists. 3715 */ 3716 for (i = 0; i < DC_RX_LIST_CNT; i++) { 3717 if (cd->dc_rx_chain[i] != NULL) { 3718 m_freem(cd->dc_rx_chain[i]); 3719 cd->dc_rx_chain[i] = NULL; 3720 } 3721 } 3722 bzero(&ld->dc_rx_list, sizeof(ld->dc_rx_list)); 3723 3724 /* 3725 * Free the TX list buffers. 3726 */ 3727 for (i = 0; i < DC_TX_LIST_CNT; i++) { 3728 if (cd->dc_tx_chain[i] != NULL) { 3729 ctl = le32toh(ld->dc_tx_list[i].dc_ctl); 3730 if ((ctl & DC_TXCTL_SETUP) || 3731 !(ctl & DC_TXCTL_LASTFRAG)) { 3732 cd->dc_tx_chain[i] = NULL; 3733 continue; 3734 } 3735 bus_dmamap_unload(sc->dc_mtag, cd->dc_tx_map[i]); 3736 m_freem(cd->dc_tx_chain[i]); 3737 cd->dc_tx_chain[i] = NULL; 3738 } 3739 } 3740 bzero(&ld->dc_tx_list, sizeof(ld->dc_tx_list)); 3741 } 3742 3743 /* 3744 * Device suspend routine. Stop the interface and save some PCI 3745 * settings in case the BIOS doesn't restore them properly on 3746 * resume. 3747 */ 3748 static int 3749 dc_suspend(device_t dev) 3750 { 3751 struct dc_softc *sc; 3752 3753 sc = device_get_softc(dev); 3754 DC_LOCK(sc); 3755 dc_stop(sc); 3756 sc->suspended = 1; 3757 DC_UNLOCK(sc); 3758 3759 return (0); 3760 } 3761 3762 /* 3763 * Device resume routine. Restore some PCI settings in case the BIOS 3764 * doesn't, re-enable busmastering, and restart the interface if 3765 * appropriate. 3766 */ 3767 static int 3768 dc_resume(device_t dev) 3769 { 3770 struct dc_softc *sc; 3771 struct ifnet *ifp; 3772 3773 sc = device_get_softc(dev); 3774 ifp = sc->dc_ifp; 3775 3776 /* reinitialize interface if necessary */ 3777 DC_LOCK(sc); 3778 if (ifp->if_flags & IFF_UP) 3779 dc_init_locked(sc); 3780 3781 sc->suspended = 0; 3782 DC_UNLOCK(sc); 3783 3784 return (0); 3785 } 3786 3787 /* 3788 * Stop all chip I/O so that the kernel's probe routines don't 3789 * get confused by errant DMAs when rebooting. 3790 */ 3791 static void 3792 dc_shutdown(device_t dev) 3793 { 3794 struct dc_softc *sc; 3795 3796 sc = device_get_softc(dev); 3797 3798 DC_LOCK(sc); 3799 dc_stop(sc); 3800 DC_UNLOCK(sc); 3801 } 3802