1 /*- 2 * Copyright (c) 1997, 1998, 1999 3 * Bill Paul <wpaul@ee.columbia.edu>. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 3. All advertising materials mentioning features or use of this software 14 * must display the following acknowledgement: 15 * This product includes software developed by Bill Paul. 16 * 4. Neither the name of the author nor the names of any co-contributors 17 * may be used to endorse or promote products derived from this software 18 * without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30 * THE POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33 #include <sys/cdefs.h> 34 __FBSDID("$FreeBSD$"); 35 36 /* 37 * DEC "tulip" clone ethernet driver. Supports the DEC/Intel 21143 38 * series chips and several workalikes including the following: 39 * 40 * Macronix 98713/98715/98725/98727/98732 PMAC (www.macronix.com) 41 * Macronix/Lite-On 82c115 PNIC II (www.macronix.com) 42 * Lite-On 82c168/82c169 PNIC (www.litecom.com) 43 * ASIX Electronics AX88140A (www.asix.com.tw) 44 * ASIX Electronics AX88141 (www.asix.com.tw) 45 * ADMtek AL981 (www.admtek.com.tw) 46 * ADMtek AN983 (www.admtek.com.tw) 47 * ADMtek CardBus AN985 (www.admtek.com.tw) 48 * Netgear FA511 (www.netgear.com) Appears to be rebadged ADMTek CardBus AN985 49 * Davicom DM9100, DM9102, DM9102A (www.davicom8.com) 50 * Accton EN1217 (www.accton.com) 51 * Xircom X3201 (www.xircom.com) 52 * Abocom FE2500 53 * Conexant LANfinity (www.conexant.com) 54 * 3Com OfficeConnect 10/100B 3CSOHO100B (www.3com.com) 55 * 56 * Datasheets for the 21143 are available at developer.intel.com. 57 * Datasheets for the clone parts can be found at their respective sites. 58 * (Except for the PNIC; see www.freebsd.org/~wpaul/PNIC/pnic.ps.gz.) 59 * The PNIC II is essentially a Macronix 98715A chip; the only difference 60 * worth noting is that its multicast hash table is only 128 bits wide 61 * instead of 512. 62 * 63 * Written by Bill Paul <wpaul@ee.columbia.edu> 64 * Electrical Engineering Department 65 * Columbia University, New York City 66 */ 67 /* 68 * The Intel 21143 is the successor to the DEC 21140. It is basically 69 * the same as the 21140 but with a few new features. The 21143 supports 70 * three kinds of media attachments: 71 * 72 * o MII port, for 10Mbps and 100Mbps support and NWAY 73 * autonegotiation provided by an external PHY. 74 * o SYM port, for symbol mode 100Mbps support. 75 * o 10baseT port. 76 * o AUI/BNC port. 77 * 78 * The 100Mbps SYM port and 10baseT port can be used together in 79 * combination with the internal NWAY support to create a 10/100 80 * autosensing configuration. 81 * 82 * Note that not all tulip workalikes are handled in this driver: we only 83 * deal with those which are relatively well behaved. The Winbond is 84 * handled separately due to its different register offsets and the 85 * special handling needed for its various bugs. The PNIC is handled 86 * here, but I'm not thrilled about it. 87 * 88 * All of the workalike chips use some form of MII transceiver support 89 * with the exception of the Macronix chips, which also have a SYM port. 90 * The ASIX AX88140A is also documented to have a SYM port, but all 91 * the cards I've seen use an MII transceiver, probably because the 92 * AX88140A doesn't support internal NWAY. 93 */ 94 95 #ifdef HAVE_KERNEL_OPTION_HEADERS 96 #include "opt_device_polling.h" 97 #endif 98 99 #include <sys/param.h> 100 #include <sys/endian.h> 101 #include <sys/systm.h> 102 #include <sys/sockio.h> 103 #include <sys/mbuf.h> 104 #include <sys/malloc.h> 105 #include <sys/kernel.h> 106 #include <sys/module.h> 107 #include <sys/socket.h> 108 109 #include <net/if.h> 110 #include <net/if_arp.h> 111 #include <net/ethernet.h> 112 #include <net/if_dl.h> 113 #include <net/if_media.h> 114 #include <net/if_types.h> 115 #include <net/if_vlan_var.h> 116 117 #include <net/bpf.h> 118 119 #include <machine/bus.h> 120 #include <machine/resource.h> 121 #include <sys/bus.h> 122 #include <sys/rman.h> 123 124 #include <dev/mii/mii.h> 125 #include <dev/mii/miivar.h> 126 127 #include <dev/pci/pcireg.h> 128 #include <dev/pci/pcivar.h> 129 130 #define DC_USEIOSPACE 131 132 #include <dev/dc/if_dcreg.h> 133 134 #ifdef __sparc64__ 135 #include <dev/ofw/openfirm.h> 136 #include <machine/ofw_machdep.h> 137 #endif 138 139 MODULE_DEPEND(dc, pci, 1, 1, 1); 140 MODULE_DEPEND(dc, ether, 1, 1, 1); 141 MODULE_DEPEND(dc, miibus, 1, 1, 1); 142 143 /* 144 * "device miibus" is required in kernel config. See GENERIC if you get 145 * errors here. 146 */ 147 #include "miibus_if.h" 148 149 /* 150 * Various supported device vendors/types and their names. 151 */ 152 static const struct dc_type dc_devs[] = { 153 { DC_DEVID(DC_VENDORID_DEC, DC_DEVICEID_21143), 0, 154 "Intel 21143 10/100BaseTX" }, 155 { DC_DEVID(DC_VENDORID_DAVICOM, DC_DEVICEID_DM9009), 0, 156 "Davicom DM9009 10/100BaseTX" }, 157 { DC_DEVID(DC_VENDORID_DAVICOM, DC_DEVICEID_DM9100), 0, 158 "Davicom DM9100 10/100BaseTX" }, 159 { DC_DEVID(DC_VENDORID_DAVICOM, DC_DEVICEID_DM9102), DC_REVISION_DM9102A, 160 "Davicom DM9102A 10/100BaseTX" }, 161 { DC_DEVID(DC_VENDORID_DAVICOM, DC_DEVICEID_DM9102), 0, 162 "Davicom DM9102 10/100BaseTX" }, 163 { DC_DEVID(DC_VENDORID_ADMTEK, DC_DEVICEID_AL981), 0, 164 "ADMtek AL981 10/100BaseTX" }, 165 { DC_DEVID(DC_VENDORID_ADMTEK, DC_DEVICEID_AN983), 0, 166 "ADMtek AN983 10/100BaseTX" }, 167 { DC_DEVID(DC_VENDORID_ADMTEK, DC_DEVICEID_AN985), 0, 168 "ADMtek AN985 CardBus 10/100BaseTX or clone" }, 169 { DC_DEVID(DC_VENDORID_ADMTEK, DC_DEVICEID_ADM9511), 0, 170 "ADMtek ADM9511 10/100BaseTX" }, 171 { DC_DEVID(DC_VENDORID_ADMTEK, DC_DEVICEID_ADM9513), 0, 172 "ADMtek ADM9513 10/100BaseTX" }, 173 { DC_DEVID(DC_VENDORID_ASIX, DC_DEVICEID_AX88140A), DC_REVISION_88141, 174 "ASIX AX88141 10/100BaseTX" }, 175 { DC_DEVID(DC_VENDORID_ASIX, DC_DEVICEID_AX88140A), 0, 176 "ASIX AX88140A 10/100BaseTX" }, 177 { DC_DEVID(DC_VENDORID_MX, DC_DEVICEID_98713), DC_REVISION_98713A, 178 "Macronix 98713A 10/100BaseTX" }, 179 { DC_DEVID(DC_VENDORID_MX, DC_DEVICEID_98713), 0, 180 "Macronix 98713 10/100BaseTX" }, 181 { DC_DEVID(DC_VENDORID_CP, DC_DEVICEID_98713_CP), DC_REVISION_98713A, 182 "Compex RL100-TX 10/100BaseTX" }, 183 { DC_DEVID(DC_VENDORID_CP, DC_DEVICEID_98713_CP), 0, 184 "Compex RL100-TX 10/100BaseTX" }, 185 { DC_DEVID(DC_VENDORID_MX, DC_DEVICEID_987x5), DC_REVISION_98725, 186 "Macronix 98725 10/100BaseTX" }, 187 { DC_DEVID(DC_VENDORID_MX, DC_DEVICEID_987x5), DC_REVISION_98715AEC_C, 188 "Macronix 98715AEC-C 10/100BaseTX" }, 189 { DC_DEVID(DC_VENDORID_MX, DC_DEVICEID_987x5), 0, 190 "Macronix 98715/98715A 10/100BaseTX" }, 191 { DC_DEVID(DC_VENDORID_MX, DC_DEVICEID_98727), 0, 192 "Macronix 98727/98732 10/100BaseTX" }, 193 { DC_DEVID(DC_VENDORID_LO, DC_DEVICEID_82C115), 0, 194 "LC82C115 PNIC II 10/100BaseTX" }, 195 { DC_DEVID(DC_VENDORID_LO, DC_DEVICEID_82C168), DC_REVISION_82C169, 196 "82c169 PNIC 10/100BaseTX" }, 197 { DC_DEVID(DC_VENDORID_LO, DC_DEVICEID_82C168), 0, 198 "82c168 PNIC 10/100BaseTX" }, 199 { DC_DEVID(DC_VENDORID_ACCTON, DC_DEVICEID_EN1217), 0, 200 "Accton EN1217 10/100BaseTX" }, 201 { DC_DEVID(DC_VENDORID_ACCTON, DC_DEVICEID_EN2242), 0, 202 "Accton EN2242 MiniPCI 10/100BaseTX" }, 203 { DC_DEVID(DC_VENDORID_XIRCOM, DC_DEVICEID_X3201), 0, 204 "Xircom X3201 10/100BaseTX" }, 205 { DC_DEVID(DC_VENDORID_DLINK, DC_DEVICEID_DRP32TXD), 0, 206 "Neteasy DRP-32TXD Cardbus 10/100" }, 207 { DC_DEVID(DC_VENDORID_ABOCOM, DC_DEVICEID_FE2500), 0, 208 "Abocom FE2500 10/100BaseTX" }, 209 { DC_DEVID(DC_VENDORID_ABOCOM, DC_DEVICEID_FE2500MX), 0, 210 "Abocom FE2500MX 10/100BaseTX" }, 211 { DC_DEVID(DC_VENDORID_CONEXANT, DC_DEVICEID_RS7112), 0, 212 "Conexant LANfinity MiniPCI 10/100BaseTX" }, 213 { DC_DEVID(DC_VENDORID_HAWKING, DC_DEVICEID_HAWKING_PN672TX), 0, 214 "Hawking CB102 CardBus 10/100" }, 215 { DC_DEVID(DC_VENDORID_PLANEX, DC_DEVICEID_FNW3602T), 0, 216 "PlaneX FNW-3602-T CardBus 10/100" }, 217 { DC_DEVID(DC_VENDORID_3COM, DC_DEVICEID_3CSOHOB), 0, 218 "3Com OfficeConnect 10/100B" }, 219 { DC_DEVID(DC_VENDORID_MICROSOFT, DC_DEVICEID_MSMN120), 0, 220 "Microsoft MN-120 CardBus 10/100" }, 221 { DC_DEVID(DC_VENDORID_MICROSOFT, DC_DEVICEID_MSMN130), 0, 222 "Microsoft MN-130 10/100" }, 223 { DC_DEVID(DC_VENDORID_LINKSYS, DC_DEVICEID_PCMPC200_AB08), 0, 224 "Linksys PCMPC200 CardBus 10/100" }, 225 { DC_DEVID(DC_VENDORID_LINKSYS, DC_DEVICEID_PCMPC200_AB09), 0, 226 "Linksys PCMPC200 CardBus 10/100" }, 227 { 0, 0, NULL } 228 }; 229 230 static int dc_probe(device_t); 231 static int dc_attach(device_t); 232 static int dc_detach(device_t); 233 static int dc_suspend(device_t); 234 static int dc_resume(device_t); 235 static const struct dc_type *dc_devtype(device_t); 236 static void dc_discard_rxbuf(struct dc_softc *, int); 237 static int dc_newbuf(struct dc_softc *, int); 238 static int dc_encap(struct dc_softc *, struct mbuf **); 239 static void dc_pnic_rx_bug_war(struct dc_softc *, int); 240 static int dc_rx_resync(struct dc_softc *); 241 static int dc_rxeof(struct dc_softc *); 242 static void dc_txeof(struct dc_softc *); 243 static void dc_tick(void *); 244 static void dc_tx_underrun(struct dc_softc *); 245 static void dc_intr(void *); 246 static void dc_start(struct ifnet *); 247 static void dc_start_locked(struct ifnet *); 248 static int dc_ioctl(struct ifnet *, u_long, caddr_t); 249 static void dc_init(void *); 250 static void dc_init_locked(struct dc_softc *); 251 static void dc_stop(struct dc_softc *); 252 static void dc_watchdog(void *); 253 static int dc_shutdown(device_t); 254 static int dc_ifmedia_upd(struct ifnet *); 255 static void dc_ifmedia_sts(struct ifnet *, struct ifmediareq *); 256 257 static int dc_dma_alloc(struct dc_softc *); 258 static void dc_dma_free(struct dc_softc *); 259 static void dc_dma_map_addr(void *, bus_dma_segment_t *, int, int); 260 261 static void dc_delay(struct dc_softc *); 262 static void dc_eeprom_idle(struct dc_softc *); 263 static void dc_eeprom_putbyte(struct dc_softc *, int); 264 static void dc_eeprom_getword(struct dc_softc *, int, uint16_t *); 265 static void dc_eeprom_getword_pnic(struct dc_softc *, int, uint16_t *); 266 static void dc_eeprom_getword_xircom(struct dc_softc *, int, uint16_t *); 267 static void dc_eeprom_width(struct dc_softc *); 268 static void dc_read_eeprom(struct dc_softc *, caddr_t, int, int, int); 269 270 static void dc_mii_writebit(struct dc_softc *, int); 271 static int dc_mii_readbit(struct dc_softc *); 272 static void dc_mii_sync(struct dc_softc *); 273 static void dc_mii_send(struct dc_softc *, uint32_t, int); 274 static int dc_mii_readreg(struct dc_softc *, struct dc_mii_frame *); 275 static int dc_mii_writereg(struct dc_softc *, struct dc_mii_frame *); 276 static int dc_miibus_readreg(device_t, int, int); 277 static int dc_miibus_writereg(device_t, int, int, int); 278 static void dc_miibus_statchg(device_t); 279 static void dc_miibus_mediainit(device_t); 280 281 static void dc_setcfg(struct dc_softc *, int); 282 static uint32_t dc_mchash_le(struct dc_softc *, const uint8_t *); 283 static uint32_t dc_mchash_be(const uint8_t *); 284 static void dc_setfilt_21143(struct dc_softc *); 285 static void dc_setfilt_asix(struct dc_softc *); 286 static void dc_setfilt_admtek(struct dc_softc *); 287 static void dc_setfilt_xircom(struct dc_softc *); 288 289 static void dc_setfilt(struct dc_softc *); 290 291 static void dc_reset(struct dc_softc *); 292 static int dc_list_rx_init(struct dc_softc *); 293 static int dc_list_tx_init(struct dc_softc *); 294 295 static int dc_read_srom(struct dc_softc *, int); 296 static int dc_parse_21143_srom(struct dc_softc *); 297 static int dc_decode_leaf_sia(struct dc_softc *, struct dc_eblock_sia *); 298 static int dc_decode_leaf_mii(struct dc_softc *, struct dc_eblock_mii *); 299 static int dc_decode_leaf_sym(struct dc_softc *, struct dc_eblock_sym *); 300 static void dc_apply_fixup(struct dc_softc *, int); 301 static int dc_check_multiport(struct dc_softc *); 302 303 #ifdef DC_USEIOSPACE 304 #define DC_RES SYS_RES_IOPORT 305 #define DC_RID DC_PCI_CFBIO 306 #else 307 #define DC_RES SYS_RES_MEMORY 308 #define DC_RID DC_PCI_CFBMA 309 #endif 310 311 static device_method_t dc_methods[] = { 312 /* Device interface */ 313 DEVMETHOD(device_probe, dc_probe), 314 DEVMETHOD(device_attach, dc_attach), 315 DEVMETHOD(device_detach, dc_detach), 316 DEVMETHOD(device_suspend, dc_suspend), 317 DEVMETHOD(device_resume, dc_resume), 318 DEVMETHOD(device_shutdown, dc_shutdown), 319 320 /* bus interface */ 321 DEVMETHOD(bus_print_child, bus_generic_print_child), 322 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 323 324 /* MII interface */ 325 DEVMETHOD(miibus_readreg, dc_miibus_readreg), 326 DEVMETHOD(miibus_writereg, dc_miibus_writereg), 327 DEVMETHOD(miibus_statchg, dc_miibus_statchg), 328 DEVMETHOD(miibus_mediainit, dc_miibus_mediainit), 329 330 { 0, 0 } 331 }; 332 333 static driver_t dc_driver = { 334 "dc", 335 dc_methods, 336 sizeof(struct dc_softc) 337 }; 338 339 static devclass_t dc_devclass; 340 341 DRIVER_MODULE(dc, pci, dc_driver, dc_devclass, 0, 0); 342 DRIVER_MODULE(miibus, dc, miibus_driver, miibus_devclass, 0, 0); 343 344 #define DC_SETBIT(sc, reg, x) \ 345 CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) | (x)) 346 347 #define DC_CLRBIT(sc, reg, x) \ 348 CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) & ~(x)) 349 350 #define SIO_SET(x) DC_SETBIT(sc, DC_SIO, (x)) 351 #define SIO_CLR(x) DC_CLRBIT(sc, DC_SIO, (x)) 352 353 static void 354 dc_delay(struct dc_softc *sc) 355 { 356 int idx; 357 358 for (idx = (300 / 33) + 1; idx > 0; idx--) 359 CSR_READ_4(sc, DC_BUSCTL); 360 } 361 362 static void 363 dc_eeprom_width(struct dc_softc *sc) 364 { 365 int i; 366 367 /* Force EEPROM to idle state. */ 368 dc_eeprom_idle(sc); 369 370 /* Enter EEPROM access mode. */ 371 CSR_WRITE_4(sc, DC_SIO, DC_SIO_EESEL); 372 dc_delay(sc); 373 DC_SETBIT(sc, DC_SIO, DC_SIO_ROMCTL_READ); 374 dc_delay(sc); 375 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); 376 dc_delay(sc); 377 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CS); 378 dc_delay(sc); 379 380 for (i = 3; i--;) { 381 if (6 & (1 << i)) 382 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_DATAIN); 383 else 384 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_DATAIN); 385 dc_delay(sc); 386 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CLK); 387 dc_delay(sc); 388 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); 389 dc_delay(sc); 390 } 391 392 for (i = 1; i <= 12; i++) { 393 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CLK); 394 dc_delay(sc); 395 if (!(CSR_READ_4(sc, DC_SIO) & DC_SIO_EE_DATAOUT)) { 396 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); 397 dc_delay(sc); 398 break; 399 } 400 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); 401 dc_delay(sc); 402 } 403 404 /* Turn off EEPROM access mode. */ 405 dc_eeprom_idle(sc); 406 407 if (i < 4 || i > 12) 408 sc->dc_romwidth = 6; 409 else 410 sc->dc_romwidth = i; 411 412 /* Enter EEPROM access mode. */ 413 CSR_WRITE_4(sc, DC_SIO, DC_SIO_EESEL); 414 dc_delay(sc); 415 DC_SETBIT(sc, DC_SIO, DC_SIO_ROMCTL_READ); 416 dc_delay(sc); 417 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); 418 dc_delay(sc); 419 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CS); 420 dc_delay(sc); 421 422 /* Turn off EEPROM access mode. */ 423 dc_eeprom_idle(sc); 424 } 425 426 static void 427 dc_eeprom_idle(struct dc_softc *sc) 428 { 429 int i; 430 431 CSR_WRITE_4(sc, DC_SIO, DC_SIO_EESEL); 432 dc_delay(sc); 433 DC_SETBIT(sc, DC_SIO, DC_SIO_ROMCTL_READ); 434 dc_delay(sc); 435 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); 436 dc_delay(sc); 437 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CS); 438 dc_delay(sc); 439 440 for (i = 0; i < 25; i++) { 441 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); 442 dc_delay(sc); 443 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CLK); 444 dc_delay(sc); 445 } 446 447 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); 448 dc_delay(sc); 449 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CS); 450 dc_delay(sc); 451 CSR_WRITE_4(sc, DC_SIO, 0x00000000); 452 } 453 454 /* 455 * Send a read command and address to the EEPROM, check for ACK. 456 */ 457 static void 458 dc_eeprom_putbyte(struct dc_softc *sc, int addr) 459 { 460 int d, i; 461 462 d = DC_EECMD_READ >> 6; 463 for (i = 3; i--; ) { 464 if (d & (1 << i)) 465 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_DATAIN); 466 else 467 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_DATAIN); 468 dc_delay(sc); 469 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CLK); 470 dc_delay(sc); 471 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); 472 dc_delay(sc); 473 } 474 475 /* 476 * Feed in each bit and strobe the clock. 477 */ 478 for (i = sc->dc_romwidth; i--;) { 479 if (addr & (1 << i)) { 480 SIO_SET(DC_SIO_EE_DATAIN); 481 } else { 482 SIO_CLR(DC_SIO_EE_DATAIN); 483 } 484 dc_delay(sc); 485 SIO_SET(DC_SIO_EE_CLK); 486 dc_delay(sc); 487 SIO_CLR(DC_SIO_EE_CLK); 488 dc_delay(sc); 489 } 490 } 491 492 /* 493 * Read a word of data stored in the EEPROM at address 'addr.' 494 * The PNIC 82c168/82c169 has its own non-standard way to read 495 * the EEPROM. 496 */ 497 static void 498 dc_eeprom_getword_pnic(struct dc_softc *sc, int addr, uint16_t *dest) 499 { 500 int i; 501 uint32_t r; 502 503 CSR_WRITE_4(sc, DC_PN_SIOCTL, DC_PN_EEOPCODE_READ | addr); 504 505 for (i = 0; i < DC_TIMEOUT; i++) { 506 DELAY(1); 507 r = CSR_READ_4(sc, DC_SIO); 508 if (!(r & DC_PN_SIOCTL_BUSY)) { 509 *dest = (uint16_t)(r & 0xFFFF); 510 return; 511 } 512 } 513 } 514 515 /* 516 * Read a word of data stored in the EEPROM at address 'addr.' 517 * The Xircom X3201 has its own non-standard way to read 518 * the EEPROM, too. 519 */ 520 static void 521 dc_eeprom_getword_xircom(struct dc_softc *sc, int addr, uint16_t *dest) 522 { 523 524 SIO_SET(DC_SIO_ROMSEL | DC_SIO_ROMCTL_READ); 525 526 addr *= 2; 527 CSR_WRITE_4(sc, DC_ROM, addr | 0x160); 528 *dest = (uint16_t)CSR_READ_4(sc, DC_SIO) & 0xff; 529 addr += 1; 530 CSR_WRITE_4(sc, DC_ROM, addr | 0x160); 531 *dest |= ((uint16_t)CSR_READ_4(sc, DC_SIO) & 0xff) << 8; 532 533 SIO_CLR(DC_SIO_ROMSEL | DC_SIO_ROMCTL_READ); 534 } 535 536 /* 537 * Read a word of data stored in the EEPROM at address 'addr.' 538 */ 539 static void 540 dc_eeprom_getword(struct dc_softc *sc, int addr, uint16_t *dest) 541 { 542 int i; 543 uint16_t word = 0; 544 545 /* Force EEPROM to idle state. */ 546 dc_eeprom_idle(sc); 547 548 /* Enter EEPROM access mode. */ 549 CSR_WRITE_4(sc, DC_SIO, DC_SIO_EESEL); 550 dc_delay(sc); 551 DC_SETBIT(sc, DC_SIO, DC_SIO_ROMCTL_READ); 552 dc_delay(sc); 553 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); 554 dc_delay(sc); 555 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CS); 556 dc_delay(sc); 557 558 /* 559 * Send address of word we want to read. 560 */ 561 dc_eeprom_putbyte(sc, addr); 562 563 /* 564 * Start reading bits from EEPROM. 565 */ 566 for (i = 0x8000; i; i >>= 1) { 567 SIO_SET(DC_SIO_EE_CLK); 568 dc_delay(sc); 569 if (CSR_READ_4(sc, DC_SIO) & DC_SIO_EE_DATAOUT) 570 word |= i; 571 dc_delay(sc); 572 SIO_CLR(DC_SIO_EE_CLK); 573 dc_delay(sc); 574 } 575 576 /* Turn off EEPROM access mode. */ 577 dc_eeprom_idle(sc); 578 579 *dest = word; 580 } 581 582 /* 583 * Read a sequence of words from the EEPROM. 584 */ 585 static void 586 dc_read_eeprom(struct dc_softc *sc, caddr_t dest, int off, int cnt, int be) 587 { 588 int i; 589 uint16_t word = 0, *ptr; 590 591 for (i = 0; i < cnt; i++) { 592 if (DC_IS_PNIC(sc)) 593 dc_eeprom_getword_pnic(sc, off + i, &word); 594 else if (DC_IS_XIRCOM(sc)) 595 dc_eeprom_getword_xircom(sc, off + i, &word); 596 else 597 dc_eeprom_getword(sc, off + i, &word); 598 ptr = (uint16_t *)(dest + (i * 2)); 599 if (be) 600 *ptr = be16toh(word); 601 else 602 *ptr = le16toh(word); 603 } 604 } 605 606 /* 607 * The following two routines are taken from the Macronix 98713 608 * Application Notes pp.19-21. 609 */ 610 /* 611 * Write a bit to the MII bus. 612 */ 613 static void 614 dc_mii_writebit(struct dc_softc *sc, int bit) 615 { 616 uint32_t reg; 617 618 reg = DC_SIO_ROMCTL_WRITE | (bit != 0 ? DC_SIO_MII_DATAOUT : 0); 619 CSR_WRITE_4(sc, DC_SIO, reg); 620 CSR_BARRIER_4(sc, DC_SIO, 621 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 622 DELAY(1); 623 624 CSR_WRITE_4(sc, DC_SIO, reg | DC_SIO_MII_CLK); 625 CSR_BARRIER_4(sc, DC_SIO, 626 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 627 DELAY(1); 628 CSR_WRITE_4(sc, DC_SIO, reg); 629 CSR_BARRIER_4(sc, DC_SIO, 630 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 631 DELAY(1); 632 } 633 634 /* 635 * Read a bit from the MII bus. 636 */ 637 static int 638 dc_mii_readbit(struct dc_softc *sc) 639 { 640 uint32_t reg; 641 642 reg = DC_SIO_ROMCTL_READ | DC_SIO_MII_DIR; 643 CSR_WRITE_4(sc, DC_SIO, reg); 644 CSR_BARRIER_4(sc, DC_SIO, 645 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 646 DELAY(1); 647 (void)CSR_READ_4(sc, DC_SIO); 648 CSR_WRITE_4(sc, DC_SIO, reg | DC_SIO_MII_CLK); 649 CSR_BARRIER_4(sc, DC_SIO, 650 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 651 DELAY(1); 652 CSR_WRITE_4(sc, DC_SIO, reg); 653 CSR_BARRIER_4(sc, DC_SIO, 654 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 655 DELAY(1); 656 if (CSR_READ_4(sc, DC_SIO) & DC_SIO_MII_DATAIN) 657 return (1); 658 659 return (0); 660 } 661 662 /* 663 * Sync the PHYs by setting data bit and strobing the clock 32 times. 664 */ 665 static void 666 dc_mii_sync(struct dc_softc *sc) 667 { 668 int i; 669 670 CSR_WRITE_4(sc, DC_SIO, DC_SIO_ROMCTL_WRITE); 671 CSR_BARRIER_4(sc, DC_SIO, 672 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 673 DELAY(1); 674 675 for (i = 0; i < 32; i++) 676 dc_mii_writebit(sc, 1); 677 } 678 679 /* 680 * Clock a series of bits through the MII. 681 */ 682 static void 683 dc_mii_send(struct dc_softc *sc, uint32_t bits, int cnt) 684 { 685 int i; 686 687 for (i = (0x1 << (cnt - 1)); i; i >>= 1) 688 dc_mii_writebit(sc, bits & i); 689 } 690 691 /* 692 * Read an PHY register through the MII. 693 */ 694 static int 695 dc_mii_readreg(struct dc_softc *sc, struct dc_mii_frame *frame) 696 { 697 int i; 698 699 /* 700 * Set up frame for RX. 701 */ 702 frame->mii_stdelim = DC_MII_STARTDELIM; 703 frame->mii_opcode = DC_MII_READOP; 704 705 /* 706 * Sync the PHYs. 707 */ 708 dc_mii_sync(sc); 709 710 /* 711 * Send command/address info. 712 */ 713 dc_mii_send(sc, frame->mii_stdelim, 2); 714 dc_mii_send(sc, frame->mii_opcode, 2); 715 dc_mii_send(sc, frame->mii_phyaddr, 5); 716 dc_mii_send(sc, frame->mii_regaddr, 5); 717 718 /* 719 * Now try reading data bits. If the turnaround failed, we still 720 * need to clock through 16 cycles to keep the PHY(s) in sync. 721 */ 722 frame->mii_turnaround = dc_mii_readbit(sc); 723 if (frame->mii_turnaround != 0) { 724 for (i = 0; i < 16; i++) 725 dc_mii_readbit(sc); 726 goto fail; 727 } 728 for (i = 0x8000; i; i >>= 1) { 729 if (dc_mii_readbit(sc)) 730 frame->mii_data |= i; 731 } 732 733 fail: 734 735 /* Clock the idle bits. */ 736 dc_mii_writebit(sc, 0); 737 dc_mii_writebit(sc, 0); 738 739 if (frame->mii_turnaround != 0) 740 return (1); 741 return (0); 742 } 743 744 /* 745 * Write to a PHY register through the MII. 746 */ 747 static int 748 dc_mii_writereg(struct dc_softc *sc, struct dc_mii_frame *frame) 749 { 750 751 /* 752 * Set up frame for TX. 753 */ 754 frame->mii_stdelim = DC_MII_STARTDELIM; 755 frame->mii_opcode = DC_MII_WRITEOP; 756 frame->mii_turnaround = DC_MII_TURNAROUND; 757 758 /* 759 * Sync the PHYs. 760 */ 761 dc_mii_sync(sc); 762 763 dc_mii_send(sc, frame->mii_stdelim, 2); 764 dc_mii_send(sc, frame->mii_opcode, 2); 765 dc_mii_send(sc, frame->mii_phyaddr, 5); 766 dc_mii_send(sc, frame->mii_regaddr, 5); 767 dc_mii_send(sc, frame->mii_turnaround, 2); 768 dc_mii_send(sc, frame->mii_data, 16); 769 770 /* Clock the idle bits. */ 771 dc_mii_writebit(sc, 0); 772 dc_mii_writebit(sc, 0); 773 774 return (0); 775 } 776 777 static int 778 dc_miibus_readreg(device_t dev, int phy, int reg) 779 { 780 struct dc_mii_frame frame; 781 struct dc_softc *sc; 782 int i, rval, phy_reg = 0; 783 784 sc = device_get_softc(dev); 785 bzero(&frame, sizeof(frame)); 786 787 if (sc->dc_pmode != DC_PMODE_MII) { 788 if (phy == (MII_NPHY - 1)) { 789 switch (reg) { 790 case MII_BMSR: 791 /* 792 * Fake something to make the probe 793 * code think there's a PHY here. 794 */ 795 return (BMSR_MEDIAMASK); 796 break; 797 case MII_PHYIDR1: 798 if (DC_IS_PNIC(sc)) 799 return (DC_VENDORID_LO); 800 return (DC_VENDORID_DEC); 801 break; 802 case MII_PHYIDR2: 803 if (DC_IS_PNIC(sc)) 804 return (DC_DEVICEID_82C168); 805 return (DC_DEVICEID_21143); 806 break; 807 default: 808 return (0); 809 break; 810 } 811 } else 812 return (0); 813 } 814 815 if (DC_IS_PNIC(sc)) { 816 CSR_WRITE_4(sc, DC_PN_MII, DC_PN_MIIOPCODE_READ | 817 (phy << 23) | (reg << 18)); 818 for (i = 0; i < DC_TIMEOUT; i++) { 819 DELAY(1); 820 rval = CSR_READ_4(sc, DC_PN_MII); 821 if (!(rval & DC_PN_MII_BUSY)) { 822 rval &= 0xFFFF; 823 return (rval == 0xFFFF ? 0 : rval); 824 } 825 } 826 return (0); 827 } 828 829 if (DC_IS_COMET(sc)) { 830 switch (reg) { 831 case MII_BMCR: 832 phy_reg = DC_AL_BMCR; 833 break; 834 case MII_BMSR: 835 phy_reg = DC_AL_BMSR; 836 break; 837 case MII_PHYIDR1: 838 phy_reg = DC_AL_VENID; 839 break; 840 case MII_PHYIDR2: 841 phy_reg = DC_AL_DEVID; 842 break; 843 case MII_ANAR: 844 phy_reg = DC_AL_ANAR; 845 break; 846 case MII_ANLPAR: 847 phy_reg = DC_AL_LPAR; 848 break; 849 case MII_ANER: 850 phy_reg = DC_AL_ANER; 851 break; 852 default: 853 device_printf(dev, "phy_read: bad phy register %x\n", 854 reg); 855 return (0); 856 break; 857 } 858 859 rval = CSR_READ_4(sc, phy_reg) & 0x0000FFFF; 860 861 if (rval == 0xFFFF) 862 return (0); 863 return (rval); 864 } 865 866 frame.mii_phyaddr = phy; 867 frame.mii_regaddr = reg; 868 if (sc->dc_type == DC_TYPE_98713) { 869 phy_reg = CSR_READ_4(sc, DC_NETCFG); 870 CSR_WRITE_4(sc, DC_NETCFG, phy_reg & ~DC_NETCFG_PORTSEL); 871 } 872 dc_mii_readreg(sc, &frame); 873 if (sc->dc_type == DC_TYPE_98713) 874 CSR_WRITE_4(sc, DC_NETCFG, phy_reg); 875 876 return (frame.mii_data); 877 } 878 879 static int 880 dc_miibus_writereg(device_t dev, int phy, int reg, int data) 881 { 882 struct dc_softc *sc; 883 struct dc_mii_frame frame; 884 int i, phy_reg = 0; 885 886 sc = device_get_softc(dev); 887 bzero(&frame, sizeof(frame)); 888 889 if (DC_IS_PNIC(sc)) { 890 CSR_WRITE_4(sc, DC_PN_MII, DC_PN_MIIOPCODE_WRITE | 891 (phy << 23) | (reg << 10) | data); 892 for (i = 0; i < DC_TIMEOUT; i++) { 893 if (!(CSR_READ_4(sc, DC_PN_MII) & DC_PN_MII_BUSY)) 894 break; 895 } 896 return (0); 897 } 898 899 if (DC_IS_COMET(sc)) { 900 switch (reg) { 901 case MII_BMCR: 902 phy_reg = DC_AL_BMCR; 903 break; 904 case MII_BMSR: 905 phy_reg = DC_AL_BMSR; 906 break; 907 case MII_PHYIDR1: 908 phy_reg = DC_AL_VENID; 909 break; 910 case MII_PHYIDR2: 911 phy_reg = DC_AL_DEVID; 912 break; 913 case MII_ANAR: 914 phy_reg = DC_AL_ANAR; 915 break; 916 case MII_ANLPAR: 917 phy_reg = DC_AL_LPAR; 918 break; 919 case MII_ANER: 920 phy_reg = DC_AL_ANER; 921 break; 922 default: 923 device_printf(dev, "phy_write: bad phy register %x\n", 924 reg); 925 return (0); 926 break; 927 } 928 929 CSR_WRITE_4(sc, phy_reg, data); 930 return (0); 931 } 932 933 frame.mii_phyaddr = phy; 934 frame.mii_regaddr = reg; 935 frame.mii_data = data; 936 937 if (sc->dc_type == DC_TYPE_98713) { 938 phy_reg = CSR_READ_4(sc, DC_NETCFG); 939 CSR_WRITE_4(sc, DC_NETCFG, phy_reg & ~DC_NETCFG_PORTSEL); 940 } 941 dc_mii_writereg(sc, &frame); 942 if (sc->dc_type == DC_TYPE_98713) 943 CSR_WRITE_4(sc, DC_NETCFG, phy_reg); 944 945 return (0); 946 } 947 948 static void 949 dc_miibus_statchg(device_t dev) 950 { 951 struct dc_softc *sc; 952 struct ifnet *ifp; 953 struct mii_data *mii; 954 struct ifmedia *ifm; 955 956 sc = device_get_softc(dev); 957 958 mii = device_get_softc(sc->dc_miibus); 959 ifp = sc->dc_ifp; 960 if (mii == NULL || ifp == NULL || 961 (ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) 962 return; 963 964 ifm = &mii->mii_media; 965 if (DC_IS_DAVICOM(sc) && 966 IFM_SUBTYPE(ifm->ifm_media) == IFM_HPNA_1) { 967 dc_setcfg(sc, ifm->ifm_media); 968 sc->dc_if_media = ifm->ifm_media; 969 return; 970 } 971 972 sc->dc_link = 0; 973 if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) == 974 (IFM_ACTIVE | IFM_AVALID)) { 975 switch (IFM_SUBTYPE(mii->mii_media_active)) { 976 case IFM_10_T: 977 case IFM_100_TX: 978 sc->dc_link = 1; 979 break; 980 default: 981 break; 982 } 983 } 984 if (sc->dc_link == 0) 985 return; 986 987 sc->dc_if_media = mii->mii_media_active; 988 if (DC_IS_ADMTEK(sc)) 989 return; 990 dc_setcfg(sc, mii->mii_media_active); 991 } 992 993 /* 994 * Special support for DM9102A cards with HomePNA PHYs. Note: 995 * with the Davicom DM9102A/DM9801 eval board that I have, it seems 996 * to be impossible to talk to the management interface of the DM9801 997 * PHY (its MDIO pin is not connected to anything). Consequently, 998 * the driver has to just 'know' about the additional mode and deal 999 * with it itself. *sigh* 1000 */ 1001 static void 1002 dc_miibus_mediainit(device_t dev) 1003 { 1004 struct dc_softc *sc; 1005 struct mii_data *mii; 1006 struct ifmedia *ifm; 1007 int rev; 1008 1009 rev = pci_get_revid(dev); 1010 1011 sc = device_get_softc(dev); 1012 mii = device_get_softc(sc->dc_miibus); 1013 ifm = &mii->mii_media; 1014 1015 if (DC_IS_DAVICOM(sc) && rev >= DC_REVISION_DM9102A) 1016 ifmedia_add(ifm, IFM_ETHER | IFM_HPNA_1, 0, NULL); 1017 } 1018 1019 #define DC_BITS_512 9 1020 #define DC_BITS_128 7 1021 #define DC_BITS_64 6 1022 1023 static uint32_t 1024 dc_mchash_le(struct dc_softc *sc, const uint8_t *addr) 1025 { 1026 uint32_t crc; 1027 1028 /* Compute CRC for the address value. */ 1029 crc = ether_crc32_le(addr, ETHER_ADDR_LEN); 1030 1031 /* 1032 * The hash table on the PNIC II and the MX98715AEC-C/D/E 1033 * chips is only 128 bits wide. 1034 */ 1035 if (sc->dc_flags & DC_128BIT_HASH) 1036 return (crc & ((1 << DC_BITS_128) - 1)); 1037 1038 /* The hash table on the MX98715BEC is only 64 bits wide. */ 1039 if (sc->dc_flags & DC_64BIT_HASH) 1040 return (crc & ((1 << DC_BITS_64) - 1)); 1041 1042 /* Xircom's hash filtering table is different (read: weird) */ 1043 /* Xircom uses the LEAST significant bits */ 1044 if (DC_IS_XIRCOM(sc)) { 1045 if ((crc & 0x180) == 0x180) 1046 return ((crc & 0x0F) + (crc & 0x70) * 3 + (14 << 4)); 1047 else 1048 return ((crc & 0x1F) + ((crc >> 1) & 0xF0) * 3 + 1049 (12 << 4)); 1050 } 1051 1052 return (crc & ((1 << DC_BITS_512) - 1)); 1053 } 1054 1055 /* 1056 * Calculate CRC of a multicast group address, return the lower 6 bits. 1057 */ 1058 static uint32_t 1059 dc_mchash_be(const uint8_t *addr) 1060 { 1061 uint32_t crc; 1062 1063 /* Compute CRC for the address value. */ 1064 crc = ether_crc32_be(addr, ETHER_ADDR_LEN); 1065 1066 /* Return the filter bit position. */ 1067 return ((crc >> 26) & 0x0000003F); 1068 } 1069 1070 /* 1071 * 21143-style RX filter setup routine. Filter programming is done by 1072 * downloading a special setup frame into the TX engine. 21143, Macronix, 1073 * PNIC, PNIC II and Davicom chips are programmed this way. 1074 * 1075 * We always program the chip using 'hash perfect' mode, i.e. one perfect 1076 * address (our node address) and a 512-bit hash filter for multicast 1077 * frames. We also sneak the broadcast address into the hash filter since 1078 * we need that too. 1079 */ 1080 static void 1081 dc_setfilt_21143(struct dc_softc *sc) 1082 { 1083 uint16_t eaddr[(ETHER_ADDR_LEN+1)/2]; 1084 struct dc_desc *sframe; 1085 uint32_t h, *sp; 1086 struct ifmultiaddr *ifma; 1087 struct ifnet *ifp; 1088 int i; 1089 1090 ifp = sc->dc_ifp; 1091 1092 i = sc->dc_cdata.dc_tx_prod; 1093 DC_INC(sc->dc_cdata.dc_tx_prod, DC_TX_LIST_CNT); 1094 sc->dc_cdata.dc_tx_cnt++; 1095 sframe = &sc->dc_ldata.dc_tx_list[i]; 1096 sp = sc->dc_cdata.dc_sbuf; 1097 bzero(sp, DC_SFRAME_LEN); 1098 1099 sframe->dc_data = htole32(DC_ADDR_LO(sc->dc_saddr)); 1100 sframe->dc_ctl = htole32(DC_SFRAME_LEN | DC_TXCTL_SETUP | 1101 DC_TXCTL_TLINK | DC_FILTER_HASHPERF | DC_TXCTL_FINT); 1102 1103 sc->dc_cdata.dc_tx_chain[i] = (struct mbuf *)sc->dc_cdata.dc_sbuf; 1104 1105 /* If we want promiscuous mode, set the allframes bit. */ 1106 if (ifp->if_flags & IFF_PROMISC) 1107 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC); 1108 else 1109 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC); 1110 1111 if (ifp->if_flags & IFF_ALLMULTI) 1112 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI); 1113 else 1114 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI); 1115 1116 if_maddr_rlock(ifp); 1117 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 1118 if (ifma->ifma_addr->sa_family != AF_LINK) 1119 continue; 1120 h = dc_mchash_le(sc, 1121 LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 1122 sp[h >> 4] |= htole32(1 << (h & 0xF)); 1123 } 1124 if_maddr_runlock(ifp); 1125 1126 if (ifp->if_flags & IFF_BROADCAST) { 1127 h = dc_mchash_le(sc, ifp->if_broadcastaddr); 1128 sp[h >> 4] |= htole32(1 << (h & 0xF)); 1129 } 1130 1131 /* Set our MAC address. */ 1132 bcopy(IF_LLADDR(sc->dc_ifp), eaddr, ETHER_ADDR_LEN); 1133 sp[39] = DC_SP_MAC(eaddr[0]); 1134 sp[40] = DC_SP_MAC(eaddr[1]); 1135 sp[41] = DC_SP_MAC(eaddr[2]); 1136 1137 sframe->dc_status = htole32(DC_TXSTAT_OWN); 1138 bus_dmamap_sync(sc->dc_stag, sc->dc_smap, BUS_DMASYNC_PREWRITE); 1139 CSR_WRITE_4(sc, DC_TXSTART, 0xFFFFFFFF); 1140 1141 /* 1142 * The PNIC takes an exceedingly long time to process its 1143 * setup frame; wait 10ms after posting the setup frame 1144 * before proceeding, just so it has time to swallow its 1145 * medicine. 1146 */ 1147 DELAY(10000); 1148 1149 sc->dc_wdog_timer = 5; 1150 } 1151 1152 static void 1153 dc_setfilt_admtek(struct dc_softc *sc) 1154 { 1155 uint8_t eaddr[ETHER_ADDR_LEN]; 1156 struct ifnet *ifp; 1157 struct ifmultiaddr *ifma; 1158 int h = 0; 1159 uint32_t hashes[2] = { 0, 0 }; 1160 1161 ifp = sc->dc_ifp; 1162 1163 /* Init our MAC address. */ 1164 bcopy(IF_LLADDR(sc->dc_ifp), eaddr, ETHER_ADDR_LEN); 1165 CSR_WRITE_4(sc, DC_AL_PAR0, eaddr[3] << 24 | eaddr[2] << 16 | 1166 eaddr[1] << 8 | eaddr[0]); 1167 CSR_WRITE_4(sc, DC_AL_PAR1, eaddr[5] << 8 | eaddr[4]); 1168 1169 /* If we want promiscuous mode, set the allframes bit. */ 1170 if (ifp->if_flags & IFF_PROMISC) 1171 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC); 1172 else 1173 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC); 1174 1175 if (ifp->if_flags & IFF_ALLMULTI) 1176 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI); 1177 else 1178 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI); 1179 1180 /* First, zot all the existing hash bits. */ 1181 CSR_WRITE_4(sc, DC_AL_MAR0, 0); 1182 CSR_WRITE_4(sc, DC_AL_MAR1, 0); 1183 1184 /* 1185 * If we're already in promisc or allmulti mode, we 1186 * don't have to bother programming the multicast filter. 1187 */ 1188 if (ifp->if_flags & (IFF_PROMISC | IFF_ALLMULTI)) 1189 return; 1190 1191 /* Now program new ones. */ 1192 if_maddr_rlock(ifp); 1193 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 1194 if (ifma->ifma_addr->sa_family != AF_LINK) 1195 continue; 1196 if (DC_IS_CENTAUR(sc)) 1197 h = dc_mchash_le(sc, 1198 LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 1199 else 1200 h = dc_mchash_be( 1201 LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 1202 if (h < 32) 1203 hashes[0] |= (1 << h); 1204 else 1205 hashes[1] |= (1 << (h - 32)); 1206 } 1207 if_maddr_runlock(ifp); 1208 1209 CSR_WRITE_4(sc, DC_AL_MAR0, hashes[0]); 1210 CSR_WRITE_4(sc, DC_AL_MAR1, hashes[1]); 1211 } 1212 1213 static void 1214 dc_setfilt_asix(struct dc_softc *sc) 1215 { 1216 uint32_t eaddr[(ETHER_ADDR_LEN+3)/4]; 1217 struct ifnet *ifp; 1218 struct ifmultiaddr *ifma; 1219 int h = 0; 1220 uint32_t hashes[2] = { 0, 0 }; 1221 1222 ifp = sc->dc_ifp; 1223 1224 /* Init our MAC address. */ 1225 bcopy(IF_LLADDR(sc->dc_ifp), eaddr, ETHER_ADDR_LEN); 1226 CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_PAR0); 1227 CSR_WRITE_4(sc, DC_AX_FILTDATA, eaddr[0]); 1228 CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_PAR1); 1229 CSR_WRITE_4(sc, DC_AX_FILTDATA, eaddr[1]); 1230 1231 /* If we want promiscuous mode, set the allframes bit. */ 1232 if (ifp->if_flags & IFF_PROMISC) 1233 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC); 1234 else 1235 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC); 1236 1237 if (ifp->if_flags & IFF_ALLMULTI) 1238 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI); 1239 else 1240 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI); 1241 1242 /* 1243 * The ASIX chip has a special bit to enable reception 1244 * of broadcast frames. 1245 */ 1246 if (ifp->if_flags & IFF_BROADCAST) 1247 DC_SETBIT(sc, DC_NETCFG, DC_AX_NETCFG_RX_BROAD); 1248 else 1249 DC_CLRBIT(sc, DC_NETCFG, DC_AX_NETCFG_RX_BROAD); 1250 1251 /* first, zot all the existing hash bits */ 1252 CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_MAR0); 1253 CSR_WRITE_4(sc, DC_AX_FILTDATA, 0); 1254 CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_MAR1); 1255 CSR_WRITE_4(sc, DC_AX_FILTDATA, 0); 1256 1257 /* 1258 * If we're already in promisc or allmulti mode, we 1259 * don't have to bother programming the multicast filter. 1260 */ 1261 if (ifp->if_flags & (IFF_PROMISC | IFF_ALLMULTI)) 1262 return; 1263 1264 /* now program new ones */ 1265 if_maddr_rlock(ifp); 1266 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 1267 if (ifma->ifma_addr->sa_family != AF_LINK) 1268 continue; 1269 h = dc_mchash_be(LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 1270 if (h < 32) 1271 hashes[0] |= (1 << h); 1272 else 1273 hashes[1] |= (1 << (h - 32)); 1274 } 1275 if_maddr_runlock(ifp); 1276 1277 CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_MAR0); 1278 CSR_WRITE_4(sc, DC_AX_FILTDATA, hashes[0]); 1279 CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_MAR1); 1280 CSR_WRITE_4(sc, DC_AX_FILTDATA, hashes[1]); 1281 } 1282 1283 static void 1284 dc_setfilt_xircom(struct dc_softc *sc) 1285 { 1286 uint16_t eaddr[(ETHER_ADDR_LEN+1)/2]; 1287 struct ifnet *ifp; 1288 struct ifmultiaddr *ifma; 1289 struct dc_desc *sframe; 1290 uint32_t h, *sp; 1291 int i; 1292 1293 ifp = sc->dc_ifp; 1294 DC_CLRBIT(sc, DC_NETCFG, (DC_NETCFG_TX_ON | DC_NETCFG_RX_ON)); 1295 1296 i = sc->dc_cdata.dc_tx_prod; 1297 DC_INC(sc->dc_cdata.dc_tx_prod, DC_TX_LIST_CNT); 1298 sc->dc_cdata.dc_tx_cnt++; 1299 sframe = &sc->dc_ldata.dc_tx_list[i]; 1300 sp = sc->dc_cdata.dc_sbuf; 1301 bzero(sp, DC_SFRAME_LEN); 1302 1303 sframe->dc_data = htole32(DC_ADDR_LO(sc->dc_saddr)); 1304 sframe->dc_ctl = htole32(DC_SFRAME_LEN | DC_TXCTL_SETUP | 1305 DC_TXCTL_TLINK | DC_FILTER_HASHPERF | DC_TXCTL_FINT); 1306 1307 sc->dc_cdata.dc_tx_chain[i] = (struct mbuf *)sc->dc_cdata.dc_sbuf; 1308 1309 /* If we want promiscuous mode, set the allframes bit. */ 1310 if (ifp->if_flags & IFF_PROMISC) 1311 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC); 1312 else 1313 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC); 1314 1315 if (ifp->if_flags & IFF_ALLMULTI) 1316 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI); 1317 else 1318 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI); 1319 1320 if_maddr_rlock(ifp); 1321 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 1322 if (ifma->ifma_addr->sa_family != AF_LINK) 1323 continue; 1324 h = dc_mchash_le(sc, 1325 LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 1326 sp[h >> 4] |= htole32(1 << (h & 0xF)); 1327 } 1328 if_maddr_runlock(ifp); 1329 1330 if (ifp->if_flags & IFF_BROADCAST) { 1331 h = dc_mchash_le(sc, ifp->if_broadcastaddr); 1332 sp[h >> 4] |= htole32(1 << (h & 0xF)); 1333 } 1334 1335 /* Set our MAC address. */ 1336 bcopy(IF_LLADDR(sc->dc_ifp), eaddr, ETHER_ADDR_LEN); 1337 sp[0] = DC_SP_MAC(eaddr[0]); 1338 sp[1] = DC_SP_MAC(eaddr[1]); 1339 sp[2] = DC_SP_MAC(eaddr[2]); 1340 1341 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_TX_ON); 1342 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_ON); 1343 sframe->dc_status = htole32(DC_TXSTAT_OWN); 1344 bus_dmamap_sync(sc->dc_stag, sc->dc_smap, BUS_DMASYNC_PREWRITE); 1345 CSR_WRITE_4(sc, DC_TXSTART, 0xFFFFFFFF); 1346 1347 /* 1348 * Wait some time... 1349 */ 1350 DELAY(1000); 1351 1352 sc->dc_wdog_timer = 5; 1353 } 1354 1355 static void 1356 dc_setfilt(struct dc_softc *sc) 1357 { 1358 1359 if (DC_IS_INTEL(sc) || DC_IS_MACRONIX(sc) || DC_IS_PNIC(sc) || 1360 DC_IS_PNICII(sc) || DC_IS_DAVICOM(sc) || DC_IS_CONEXANT(sc)) 1361 dc_setfilt_21143(sc); 1362 1363 if (DC_IS_ASIX(sc)) 1364 dc_setfilt_asix(sc); 1365 1366 if (DC_IS_ADMTEK(sc)) 1367 dc_setfilt_admtek(sc); 1368 1369 if (DC_IS_XIRCOM(sc)) 1370 dc_setfilt_xircom(sc); 1371 } 1372 1373 /* 1374 * In order to fiddle with the 'full-duplex' and '100Mbps' bits in 1375 * the netconfig register, we first have to put the transmit and/or 1376 * receive logic in the idle state. 1377 */ 1378 static void 1379 dc_setcfg(struct dc_softc *sc, int media) 1380 { 1381 int i, restart = 0, watchdogreg; 1382 uint32_t isr; 1383 1384 if (IFM_SUBTYPE(media) == IFM_NONE) 1385 return; 1386 1387 if (CSR_READ_4(sc, DC_NETCFG) & (DC_NETCFG_TX_ON | DC_NETCFG_RX_ON)) { 1388 restart = 1; 1389 DC_CLRBIT(sc, DC_NETCFG, (DC_NETCFG_TX_ON | DC_NETCFG_RX_ON)); 1390 1391 for (i = 0; i < DC_TIMEOUT; i++) { 1392 isr = CSR_READ_4(sc, DC_ISR); 1393 if (isr & DC_ISR_TX_IDLE && 1394 ((isr & DC_ISR_RX_STATE) == DC_RXSTATE_STOPPED || 1395 (isr & DC_ISR_RX_STATE) == DC_RXSTATE_WAIT)) 1396 break; 1397 DELAY(10); 1398 } 1399 1400 if (i == DC_TIMEOUT) { 1401 if (!(isr & DC_ISR_TX_IDLE) && !DC_IS_ASIX(sc)) 1402 device_printf(sc->dc_dev, 1403 "%s: failed to force tx to idle state\n", 1404 __func__); 1405 if (!((isr & DC_ISR_RX_STATE) == DC_RXSTATE_STOPPED || 1406 (isr & DC_ISR_RX_STATE) == DC_RXSTATE_WAIT) && 1407 !DC_HAS_BROKEN_RXSTATE(sc)) 1408 device_printf(sc->dc_dev, 1409 "%s: failed to force rx to idle state\n", 1410 __func__); 1411 } 1412 } 1413 1414 if (IFM_SUBTYPE(media) == IFM_100_TX) { 1415 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_SPEEDSEL); 1416 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_HEARTBEAT); 1417 if (sc->dc_pmode == DC_PMODE_MII) { 1418 if (DC_IS_INTEL(sc)) { 1419 /* There's a write enable bit here that reads as 1. */ 1420 watchdogreg = CSR_READ_4(sc, DC_WATCHDOG); 1421 watchdogreg &= ~DC_WDOG_CTLWREN; 1422 watchdogreg |= DC_WDOG_JABBERDIS; 1423 CSR_WRITE_4(sc, DC_WATCHDOG, watchdogreg); 1424 } else { 1425 DC_SETBIT(sc, DC_WATCHDOG, DC_WDOG_JABBERDIS); 1426 } 1427 DC_CLRBIT(sc, DC_NETCFG, (DC_NETCFG_PCS | 1428 DC_NETCFG_PORTSEL | DC_NETCFG_SCRAMBLER)); 1429 if (sc->dc_type == DC_TYPE_98713) 1430 DC_SETBIT(sc, DC_NETCFG, (DC_NETCFG_PCS | 1431 DC_NETCFG_SCRAMBLER)); 1432 if (!DC_IS_DAVICOM(sc)) 1433 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL); 1434 DC_CLRBIT(sc, DC_10BTCTRL, 0xFFFF); 1435 } else { 1436 if (DC_IS_PNIC(sc)) { 1437 DC_PN_GPIO_SETBIT(sc, DC_PN_GPIO_SPEEDSEL); 1438 DC_PN_GPIO_SETBIT(sc, DC_PN_GPIO_100TX_LOOP); 1439 DC_SETBIT(sc, DC_PN_NWAY, DC_PN_NWAY_SPEEDSEL); 1440 } 1441 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL); 1442 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PCS); 1443 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_SCRAMBLER); 1444 } 1445 } 1446 1447 if (IFM_SUBTYPE(media) == IFM_10_T) { 1448 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_SPEEDSEL); 1449 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_HEARTBEAT); 1450 if (sc->dc_pmode == DC_PMODE_MII) { 1451 /* There's a write enable bit here that reads as 1. */ 1452 if (DC_IS_INTEL(sc)) { 1453 watchdogreg = CSR_READ_4(sc, DC_WATCHDOG); 1454 watchdogreg &= ~DC_WDOG_CTLWREN; 1455 watchdogreg |= DC_WDOG_JABBERDIS; 1456 CSR_WRITE_4(sc, DC_WATCHDOG, watchdogreg); 1457 } else { 1458 DC_SETBIT(sc, DC_WATCHDOG, DC_WDOG_JABBERDIS); 1459 } 1460 DC_CLRBIT(sc, DC_NETCFG, (DC_NETCFG_PCS | 1461 DC_NETCFG_PORTSEL | DC_NETCFG_SCRAMBLER)); 1462 if (sc->dc_type == DC_TYPE_98713) 1463 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PCS); 1464 if (!DC_IS_DAVICOM(sc)) 1465 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL); 1466 DC_CLRBIT(sc, DC_10BTCTRL, 0xFFFF); 1467 } else { 1468 if (DC_IS_PNIC(sc)) { 1469 DC_PN_GPIO_CLRBIT(sc, DC_PN_GPIO_SPEEDSEL); 1470 DC_PN_GPIO_SETBIT(sc, DC_PN_GPIO_100TX_LOOP); 1471 DC_CLRBIT(sc, DC_PN_NWAY, DC_PN_NWAY_SPEEDSEL); 1472 } 1473 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL); 1474 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_PCS); 1475 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_SCRAMBLER); 1476 if (DC_IS_INTEL(sc)) { 1477 DC_CLRBIT(sc, DC_SIARESET, DC_SIA_RESET); 1478 DC_CLRBIT(sc, DC_10BTCTRL, 0xFFFF); 1479 if ((media & IFM_GMASK) == IFM_FDX) 1480 DC_SETBIT(sc, DC_10BTCTRL, 0x7F3D); 1481 else 1482 DC_SETBIT(sc, DC_10BTCTRL, 0x7F3F); 1483 DC_SETBIT(sc, DC_SIARESET, DC_SIA_RESET); 1484 DC_CLRBIT(sc, DC_10BTCTRL, 1485 DC_TCTL_AUTONEGENBL); 1486 DELAY(20000); 1487 } 1488 } 1489 } 1490 1491 /* 1492 * If this is a Davicom DM9102A card with a DM9801 HomePNA 1493 * PHY and we want HomePNA mode, set the portsel bit to turn 1494 * on the external MII port. 1495 */ 1496 if (DC_IS_DAVICOM(sc)) { 1497 if (IFM_SUBTYPE(media) == IFM_HPNA_1) { 1498 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL); 1499 sc->dc_link = 1; 1500 } else { 1501 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL); 1502 } 1503 } 1504 1505 if ((media & IFM_GMASK) == IFM_FDX) { 1506 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_FULLDUPLEX); 1507 if (sc->dc_pmode == DC_PMODE_SYM && DC_IS_PNIC(sc)) 1508 DC_SETBIT(sc, DC_PN_NWAY, DC_PN_NWAY_DUPLEX); 1509 } else { 1510 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_FULLDUPLEX); 1511 if (sc->dc_pmode == DC_PMODE_SYM && DC_IS_PNIC(sc)) 1512 DC_CLRBIT(sc, DC_PN_NWAY, DC_PN_NWAY_DUPLEX); 1513 } 1514 1515 if (restart) 1516 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_TX_ON | DC_NETCFG_RX_ON); 1517 } 1518 1519 static void 1520 dc_reset(struct dc_softc *sc) 1521 { 1522 int i; 1523 1524 DC_SETBIT(sc, DC_BUSCTL, DC_BUSCTL_RESET); 1525 1526 for (i = 0; i < DC_TIMEOUT; i++) { 1527 DELAY(10); 1528 if (!(CSR_READ_4(sc, DC_BUSCTL) & DC_BUSCTL_RESET)) 1529 break; 1530 } 1531 1532 if (DC_IS_ASIX(sc) || DC_IS_ADMTEK(sc) || DC_IS_CONEXANT(sc) || 1533 DC_IS_XIRCOM(sc) || DC_IS_INTEL(sc)) { 1534 DELAY(10000); 1535 DC_CLRBIT(sc, DC_BUSCTL, DC_BUSCTL_RESET); 1536 i = 0; 1537 } 1538 1539 if (i == DC_TIMEOUT) 1540 device_printf(sc->dc_dev, "reset never completed!\n"); 1541 1542 /* Wait a little while for the chip to get its brains in order. */ 1543 DELAY(1000); 1544 1545 CSR_WRITE_4(sc, DC_IMR, 0x00000000); 1546 CSR_WRITE_4(sc, DC_BUSCTL, 0x00000000); 1547 CSR_WRITE_4(sc, DC_NETCFG, 0x00000000); 1548 1549 /* 1550 * Bring the SIA out of reset. In some cases, it looks 1551 * like failing to unreset the SIA soon enough gets it 1552 * into a state where it will never come out of reset 1553 * until we reset the whole chip again. 1554 */ 1555 if (DC_IS_INTEL(sc)) { 1556 DC_SETBIT(sc, DC_SIARESET, DC_SIA_RESET); 1557 CSR_WRITE_4(sc, DC_10BTCTRL, 0xFFFFFFFF); 1558 CSR_WRITE_4(sc, DC_WATCHDOG, 0); 1559 } 1560 } 1561 1562 static const struct dc_type * 1563 dc_devtype(device_t dev) 1564 { 1565 const struct dc_type *t; 1566 uint32_t devid; 1567 uint8_t rev; 1568 1569 t = dc_devs; 1570 devid = pci_get_devid(dev); 1571 rev = pci_get_revid(dev); 1572 1573 while (t->dc_name != NULL) { 1574 if (devid == t->dc_devid && rev >= t->dc_minrev) 1575 return (t); 1576 t++; 1577 } 1578 1579 return (NULL); 1580 } 1581 1582 /* 1583 * Probe for a 21143 or clone chip. Check the PCI vendor and device 1584 * IDs against our list and return a device name if we find a match. 1585 * We do a little bit of extra work to identify the exact type of 1586 * chip. The MX98713 and MX98713A have the same PCI vendor/device ID, 1587 * but different revision IDs. The same is true for 98715/98715A 1588 * chips and the 98725, as well as the ASIX and ADMtek chips. In some 1589 * cases, the exact chip revision affects driver behavior. 1590 */ 1591 static int 1592 dc_probe(device_t dev) 1593 { 1594 const struct dc_type *t; 1595 1596 t = dc_devtype(dev); 1597 1598 if (t != NULL) { 1599 device_set_desc(dev, t->dc_name); 1600 return (BUS_PROBE_DEFAULT); 1601 } 1602 1603 return (ENXIO); 1604 } 1605 1606 static void 1607 dc_apply_fixup(struct dc_softc *sc, int media) 1608 { 1609 struct dc_mediainfo *m; 1610 uint8_t *p; 1611 int i; 1612 uint32_t reg; 1613 1614 m = sc->dc_mi; 1615 1616 while (m != NULL) { 1617 if (m->dc_media == media) 1618 break; 1619 m = m->dc_next; 1620 } 1621 1622 if (m == NULL) 1623 return; 1624 1625 for (i = 0, p = m->dc_reset_ptr; i < m->dc_reset_len; i++, p += 2) { 1626 reg = (p[0] | (p[1] << 8)) << 16; 1627 CSR_WRITE_4(sc, DC_WATCHDOG, reg); 1628 } 1629 1630 for (i = 0, p = m->dc_gp_ptr; i < m->dc_gp_len; i++, p += 2) { 1631 reg = (p[0] | (p[1] << 8)) << 16; 1632 CSR_WRITE_4(sc, DC_WATCHDOG, reg); 1633 } 1634 } 1635 1636 static int 1637 dc_decode_leaf_sia(struct dc_softc *sc, struct dc_eblock_sia *l) 1638 { 1639 struct dc_mediainfo *m; 1640 1641 m = malloc(sizeof(struct dc_mediainfo), M_DEVBUF, M_NOWAIT | M_ZERO); 1642 if (m == NULL) { 1643 device_printf(sc->dc_dev, "Could not allocate mediainfo\n"); 1644 return (ENOMEM); 1645 } 1646 switch (l->dc_sia_code & ~DC_SIA_CODE_EXT) { 1647 case DC_SIA_CODE_10BT: 1648 m->dc_media = IFM_10_T; 1649 break; 1650 case DC_SIA_CODE_10BT_FDX: 1651 m->dc_media = IFM_10_T | IFM_FDX; 1652 break; 1653 case DC_SIA_CODE_10B2: 1654 m->dc_media = IFM_10_2; 1655 break; 1656 case DC_SIA_CODE_10B5: 1657 m->dc_media = IFM_10_5; 1658 break; 1659 default: 1660 break; 1661 } 1662 1663 /* 1664 * We need to ignore CSR13, CSR14, CSR15 for SIA mode. 1665 * Things apparently already work for cards that do 1666 * supply Media Specific Data. 1667 */ 1668 if (l->dc_sia_code & DC_SIA_CODE_EXT) { 1669 m->dc_gp_len = 2; 1670 m->dc_gp_ptr = 1671 (uint8_t *)&l->dc_un.dc_sia_ext.dc_sia_gpio_ctl; 1672 } else { 1673 m->dc_gp_len = 2; 1674 m->dc_gp_ptr = 1675 (uint8_t *)&l->dc_un.dc_sia_noext.dc_sia_gpio_ctl; 1676 } 1677 1678 m->dc_next = sc->dc_mi; 1679 sc->dc_mi = m; 1680 1681 sc->dc_pmode = DC_PMODE_SIA; 1682 return (0); 1683 } 1684 1685 static int 1686 dc_decode_leaf_sym(struct dc_softc *sc, struct dc_eblock_sym *l) 1687 { 1688 struct dc_mediainfo *m; 1689 1690 m = malloc(sizeof(struct dc_mediainfo), M_DEVBUF, M_NOWAIT | M_ZERO); 1691 if (m == NULL) { 1692 device_printf(sc->dc_dev, "Could not allocate mediainfo\n"); 1693 return (ENOMEM); 1694 } 1695 if (l->dc_sym_code == DC_SYM_CODE_100BT) 1696 m->dc_media = IFM_100_TX; 1697 1698 if (l->dc_sym_code == DC_SYM_CODE_100BT_FDX) 1699 m->dc_media = IFM_100_TX | IFM_FDX; 1700 1701 m->dc_gp_len = 2; 1702 m->dc_gp_ptr = (uint8_t *)&l->dc_sym_gpio_ctl; 1703 1704 m->dc_next = sc->dc_mi; 1705 sc->dc_mi = m; 1706 1707 sc->dc_pmode = DC_PMODE_SYM; 1708 return (0); 1709 } 1710 1711 static int 1712 dc_decode_leaf_mii(struct dc_softc *sc, struct dc_eblock_mii *l) 1713 { 1714 struct dc_mediainfo *m; 1715 uint8_t *p; 1716 1717 m = malloc(sizeof(struct dc_mediainfo), M_DEVBUF, M_NOWAIT | M_ZERO); 1718 if (m == NULL) { 1719 device_printf(sc->dc_dev, "Could not allocate mediainfo\n"); 1720 return (ENOMEM); 1721 } 1722 /* We abuse IFM_AUTO to represent MII. */ 1723 m->dc_media = IFM_AUTO; 1724 m->dc_gp_len = l->dc_gpr_len; 1725 1726 p = (uint8_t *)l; 1727 p += sizeof(struct dc_eblock_mii); 1728 m->dc_gp_ptr = p; 1729 p += 2 * l->dc_gpr_len; 1730 m->dc_reset_len = *p; 1731 p++; 1732 m->dc_reset_ptr = p; 1733 1734 m->dc_next = sc->dc_mi; 1735 sc->dc_mi = m; 1736 return (0); 1737 } 1738 1739 static int 1740 dc_read_srom(struct dc_softc *sc, int bits) 1741 { 1742 int size; 1743 1744 size = DC_ROM_SIZE(bits); 1745 sc->dc_srom = malloc(size, M_DEVBUF, M_NOWAIT); 1746 if (sc->dc_srom == NULL) { 1747 device_printf(sc->dc_dev, "Could not allocate SROM buffer\n"); 1748 return (ENOMEM); 1749 } 1750 dc_read_eeprom(sc, (caddr_t)sc->dc_srom, 0, (size / 2), 0); 1751 return (0); 1752 } 1753 1754 static int 1755 dc_parse_21143_srom(struct dc_softc *sc) 1756 { 1757 struct dc_leaf_hdr *lhdr; 1758 struct dc_eblock_hdr *hdr; 1759 int error, have_mii, i, loff; 1760 char *ptr; 1761 1762 have_mii = 0; 1763 loff = sc->dc_srom[27]; 1764 lhdr = (struct dc_leaf_hdr *)&(sc->dc_srom[loff]); 1765 1766 ptr = (char *)lhdr; 1767 ptr += sizeof(struct dc_leaf_hdr) - 1; 1768 /* 1769 * Look if we got a MII media block. 1770 */ 1771 for (i = 0; i < lhdr->dc_mcnt; i++) { 1772 hdr = (struct dc_eblock_hdr *)ptr; 1773 if (hdr->dc_type == DC_EBLOCK_MII) 1774 have_mii++; 1775 1776 ptr += (hdr->dc_len & 0x7F); 1777 ptr++; 1778 } 1779 1780 /* 1781 * Do the same thing again. Only use SIA and SYM media 1782 * blocks if no MII media block is available. 1783 */ 1784 ptr = (char *)lhdr; 1785 ptr += sizeof(struct dc_leaf_hdr) - 1; 1786 error = 0; 1787 for (i = 0; i < lhdr->dc_mcnt; i++) { 1788 hdr = (struct dc_eblock_hdr *)ptr; 1789 switch (hdr->dc_type) { 1790 case DC_EBLOCK_MII: 1791 error = dc_decode_leaf_mii(sc, (struct dc_eblock_mii *)hdr); 1792 break; 1793 case DC_EBLOCK_SIA: 1794 if (! have_mii) 1795 error = dc_decode_leaf_sia(sc, 1796 (struct dc_eblock_sia *)hdr); 1797 break; 1798 case DC_EBLOCK_SYM: 1799 if (! have_mii) 1800 error = dc_decode_leaf_sym(sc, 1801 (struct dc_eblock_sym *)hdr); 1802 break; 1803 default: 1804 /* Don't care. Yet. */ 1805 break; 1806 } 1807 ptr += (hdr->dc_len & 0x7F); 1808 ptr++; 1809 } 1810 return (error); 1811 } 1812 1813 static void 1814 dc_dma_map_addr(void *arg, bus_dma_segment_t *segs, int nseg, int error) 1815 { 1816 bus_addr_t *paddr; 1817 1818 KASSERT(nseg == 1, 1819 ("%s: wrong number of segments (%d)", __func__, nseg)); 1820 paddr = arg; 1821 *paddr = segs->ds_addr; 1822 } 1823 1824 static int 1825 dc_dma_alloc(struct dc_softc *sc) 1826 { 1827 int error, i; 1828 1829 error = bus_dma_tag_create(bus_get_dma_tag(sc->dc_dev), 1, 0, 1830 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL, 1831 BUS_SPACE_MAXSIZE_32BIT, 0, BUS_SPACE_MAXSIZE_32BIT, 0, 1832 NULL, NULL, &sc->dc_ptag); 1833 if (error) { 1834 device_printf(sc->dc_dev, 1835 "failed to allocate parent DMA tag\n"); 1836 goto fail; 1837 } 1838 1839 /* Allocate a busdma tag and DMA safe memory for TX/RX descriptors. */ 1840 error = bus_dma_tag_create(sc->dc_ptag, DC_LIST_ALIGN, 0, 1841 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL, DC_RX_LIST_SZ, 1, 1842 DC_RX_LIST_SZ, 0, NULL, NULL, &sc->dc_rx_ltag); 1843 if (error) { 1844 device_printf(sc->dc_dev, "failed to create RX list DMA tag\n"); 1845 goto fail; 1846 } 1847 1848 error = bus_dma_tag_create(sc->dc_ptag, DC_LIST_ALIGN, 0, 1849 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL, DC_TX_LIST_SZ, 1, 1850 DC_TX_LIST_SZ, 0, NULL, NULL, &sc->dc_tx_ltag); 1851 if (error) { 1852 device_printf(sc->dc_dev, "failed to create TX list DMA tag\n"); 1853 goto fail; 1854 } 1855 1856 /* RX descriptor list. */ 1857 error = bus_dmamem_alloc(sc->dc_rx_ltag, 1858 (void **)&sc->dc_ldata.dc_rx_list, BUS_DMA_NOWAIT | 1859 BUS_DMA_ZERO | BUS_DMA_COHERENT, &sc->dc_rx_lmap); 1860 if (error) { 1861 device_printf(sc->dc_dev, 1862 "failed to allocate DMA'able memory for RX list\n"); 1863 goto fail; 1864 } 1865 error = bus_dmamap_load(sc->dc_rx_ltag, sc->dc_rx_lmap, 1866 sc->dc_ldata.dc_rx_list, DC_RX_LIST_SZ, dc_dma_map_addr, 1867 &sc->dc_ldata.dc_rx_list_paddr, BUS_DMA_NOWAIT); 1868 if (error) { 1869 device_printf(sc->dc_dev, 1870 "failed to load DMA'able memory for RX list\n"); 1871 goto fail; 1872 } 1873 /* TX descriptor list. */ 1874 error = bus_dmamem_alloc(sc->dc_tx_ltag, 1875 (void **)&sc->dc_ldata.dc_tx_list, BUS_DMA_NOWAIT | 1876 BUS_DMA_ZERO | BUS_DMA_COHERENT, &sc->dc_tx_lmap); 1877 if (error) { 1878 device_printf(sc->dc_dev, 1879 "failed to allocate DMA'able memory for TX list\n"); 1880 goto fail; 1881 } 1882 error = bus_dmamap_load(sc->dc_tx_ltag, sc->dc_tx_lmap, 1883 sc->dc_ldata.dc_tx_list, DC_TX_LIST_SZ, dc_dma_map_addr, 1884 &sc->dc_ldata.dc_tx_list_paddr, BUS_DMA_NOWAIT); 1885 if (error) { 1886 device_printf(sc->dc_dev, 1887 "cannot load DMA'able memory for TX list\n"); 1888 goto fail; 1889 } 1890 1891 /* 1892 * Allocate a busdma tag and DMA safe memory for the multicast 1893 * setup frame. 1894 */ 1895 error = bus_dma_tag_create(sc->dc_ptag, DC_LIST_ALIGN, 0, 1896 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL, 1897 DC_SFRAME_LEN + DC_MIN_FRAMELEN, 1, DC_SFRAME_LEN + DC_MIN_FRAMELEN, 1898 0, NULL, NULL, &sc->dc_stag); 1899 if (error) { 1900 device_printf(sc->dc_dev, 1901 "failed to create DMA tag for setup frame\n"); 1902 goto fail; 1903 } 1904 error = bus_dmamem_alloc(sc->dc_stag, (void **)&sc->dc_cdata.dc_sbuf, 1905 BUS_DMA_NOWAIT, &sc->dc_smap); 1906 if (error) { 1907 device_printf(sc->dc_dev, 1908 "failed to allocate DMA'able memory for setup frame\n"); 1909 goto fail; 1910 } 1911 error = bus_dmamap_load(sc->dc_stag, sc->dc_smap, sc->dc_cdata.dc_sbuf, 1912 DC_SFRAME_LEN, dc_dma_map_addr, &sc->dc_saddr, BUS_DMA_NOWAIT); 1913 if (error) { 1914 device_printf(sc->dc_dev, 1915 "cannot load DMA'able memory for setup frame\n"); 1916 goto fail; 1917 } 1918 1919 /* Allocate a busdma tag for RX mbufs. */ 1920 error = bus_dma_tag_create(sc->dc_ptag, DC_RXBUF_ALIGN, 0, 1921 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL, 1922 MCLBYTES, 1, MCLBYTES, 0, NULL, NULL, &sc->dc_rx_mtag); 1923 if (error) { 1924 device_printf(sc->dc_dev, "failed to create RX mbuf tag\n"); 1925 goto fail; 1926 } 1927 1928 /* Allocate a busdma tag for TX mbufs. */ 1929 error = bus_dma_tag_create(sc->dc_ptag, 1, 0, 1930 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL, 1931 MCLBYTES * DC_MAXFRAGS, DC_MAXFRAGS, MCLBYTES, 1932 0, NULL, NULL, &sc->dc_tx_mtag); 1933 if (error) { 1934 device_printf(sc->dc_dev, "failed to create TX mbuf tag\n"); 1935 goto fail; 1936 } 1937 1938 /* Create the TX/RX busdma maps. */ 1939 for (i = 0; i < DC_TX_LIST_CNT; i++) { 1940 error = bus_dmamap_create(sc->dc_tx_mtag, 0, 1941 &sc->dc_cdata.dc_tx_map[i]); 1942 if (error) { 1943 device_printf(sc->dc_dev, 1944 "failed to create TX mbuf dmamap\n"); 1945 goto fail; 1946 } 1947 } 1948 for (i = 0; i < DC_RX_LIST_CNT; i++) { 1949 error = bus_dmamap_create(sc->dc_rx_mtag, 0, 1950 &sc->dc_cdata.dc_rx_map[i]); 1951 if (error) { 1952 device_printf(sc->dc_dev, 1953 "failed to create RX mbuf dmamap\n"); 1954 goto fail; 1955 } 1956 } 1957 error = bus_dmamap_create(sc->dc_rx_mtag, 0, &sc->dc_sparemap); 1958 if (error) { 1959 device_printf(sc->dc_dev, 1960 "failed to create spare RX mbuf dmamap\n"); 1961 goto fail; 1962 } 1963 1964 fail: 1965 return (error); 1966 } 1967 1968 static void 1969 dc_dma_free(struct dc_softc *sc) 1970 { 1971 int i; 1972 1973 /* RX buffers. */ 1974 if (sc->dc_rx_mtag != NULL) { 1975 for (i = 0; i < DC_RX_LIST_CNT; i++) { 1976 if (sc->dc_cdata.dc_rx_map[i] != NULL) 1977 bus_dmamap_destroy(sc->dc_rx_mtag, 1978 sc->dc_cdata.dc_rx_map[i]); 1979 } 1980 if (sc->dc_sparemap != NULL) 1981 bus_dmamap_destroy(sc->dc_rx_mtag, sc->dc_sparemap); 1982 bus_dma_tag_destroy(sc->dc_rx_mtag); 1983 } 1984 1985 /* TX buffers. */ 1986 if (sc->dc_rx_mtag != NULL) { 1987 for (i = 0; i < DC_TX_LIST_CNT; i++) { 1988 if (sc->dc_cdata.dc_tx_map[i] != NULL) 1989 bus_dmamap_destroy(sc->dc_tx_mtag, 1990 sc->dc_cdata.dc_tx_map[i]); 1991 } 1992 bus_dma_tag_destroy(sc->dc_tx_mtag); 1993 } 1994 1995 /* RX descriptor list. */ 1996 if (sc->dc_rx_ltag) { 1997 if (sc->dc_rx_lmap != NULL) 1998 bus_dmamap_unload(sc->dc_rx_ltag, sc->dc_rx_lmap); 1999 if (sc->dc_rx_lmap != NULL && sc->dc_ldata.dc_rx_list != NULL) 2000 bus_dmamem_free(sc->dc_rx_ltag, sc->dc_ldata.dc_rx_list, 2001 sc->dc_rx_lmap); 2002 bus_dma_tag_destroy(sc->dc_rx_ltag); 2003 } 2004 2005 /* TX descriptor list. */ 2006 if (sc->dc_tx_ltag) { 2007 if (sc->dc_tx_lmap != NULL) 2008 bus_dmamap_unload(sc->dc_tx_ltag, sc->dc_tx_lmap); 2009 if (sc->dc_tx_lmap != NULL && sc->dc_ldata.dc_tx_list != NULL) 2010 bus_dmamem_free(sc->dc_tx_ltag, sc->dc_ldata.dc_tx_list, 2011 sc->dc_tx_lmap); 2012 bus_dma_tag_destroy(sc->dc_tx_ltag); 2013 } 2014 2015 /* multicast setup frame. */ 2016 if (sc->dc_stag) { 2017 if (sc->dc_smap != NULL) 2018 bus_dmamap_unload(sc->dc_stag, sc->dc_smap); 2019 if (sc->dc_smap != NULL && sc->dc_cdata.dc_sbuf != NULL) 2020 bus_dmamem_free(sc->dc_stag, sc->dc_cdata.dc_sbuf, 2021 sc->dc_smap); 2022 bus_dma_tag_destroy(sc->dc_stag); 2023 } 2024 } 2025 2026 /* 2027 * Attach the interface. Allocate softc structures, do ifmedia 2028 * setup and ethernet/BPF attach. 2029 */ 2030 static int 2031 dc_attach(device_t dev) 2032 { 2033 uint32_t eaddr[(ETHER_ADDR_LEN+3)/4]; 2034 uint32_t command; 2035 struct dc_softc *sc; 2036 struct ifnet *ifp; 2037 struct dc_mediainfo *m; 2038 uint32_t reg, revision; 2039 int error, mac_offset, phy, rid, tmp; 2040 uint8_t *mac; 2041 2042 sc = device_get_softc(dev); 2043 sc->dc_dev = dev; 2044 2045 mtx_init(&sc->dc_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 2046 MTX_DEF); 2047 2048 /* 2049 * Map control/status registers. 2050 */ 2051 pci_enable_busmaster(dev); 2052 2053 rid = DC_RID; 2054 sc->dc_res = bus_alloc_resource_any(dev, DC_RES, &rid, RF_ACTIVE); 2055 2056 if (sc->dc_res == NULL) { 2057 device_printf(dev, "couldn't map ports/memory\n"); 2058 error = ENXIO; 2059 goto fail; 2060 } 2061 2062 sc->dc_btag = rman_get_bustag(sc->dc_res); 2063 sc->dc_bhandle = rman_get_bushandle(sc->dc_res); 2064 2065 /* Allocate interrupt. */ 2066 rid = 0; 2067 sc->dc_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 2068 RF_SHAREABLE | RF_ACTIVE); 2069 2070 if (sc->dc_irq == NULL) { 2071 device_printf(dev, "couldn't map interrupt\n"); 2072 error = ENXIO; 2073 goto fail; 2074 } 2075 2076 /* Need this info to decide on a chip type. */ 2077 sc->dc_info = dc_devtype(dev); 2078 revision = pci_get_revid(dev); 2079 2080 error = 0; 2081 /* Get the eeprom width, but PNIC and XIRCOM have diff eeprom */ 2082 if (sc->dc_info->dc_devid != 2083 DC_DEVID(DC_VENDORID_LO, DC_DEVICEID_82C168) && 2084 sc->dc_info->dc_devid != 2085 DC_DEVID(DC_VENDORID_XIRCOM, DC_DEVICEID_X3201)) 2086 dc_eeprom_width(sc); 2087 2088 switch (sc->dc_info->dc_devid) { 2089 case DC_DEVID(DC_VENDORID_DEC, DC_DEVICEID_21143): 2090 sc->dc_type = DC_TYPE_21143; 2091 sc->dc_flags |= DC_TX_POLL | DC_TX_USE_TX_INTR; 2092 sc->dc_flags |= DC_REDUCED_MII_POLL; 2093 /* Save EEPROM contents so we can parse them later. */ 2094 error = dc_read_srom(sc, sc->dc_romwidth); 2095 if (error != 0) 2096 goto fail; 2097 break; 2098 case DC_DEVID(DC_VENDORID_DAVICOM, DC_DEVICEID_DM9009): 2099 case DC_DEVID(DC_VENDORID_DAVICOM, DC_DEVICEID_DM9100): 2100 case DC_DEVID(DC_VENDORID_DAVICOM, DC_DEVICEID_DM9102): 2101 sc->dc_type = DC_TYPE_DM9102; 2102 sc->dc_flags |= DC_TX_COALESCE | DC_TX_INTR_ALWAYS; 2103 sc->dc_flags |= DC_REDUCED_MII_POLL | DC_TX_STORENFWD; 2104 sc->dc_flags |= DC_TX_ALIGN; 2105 sc->dc_pmode = DC_PMODE_MII; 2106 2107 /* Increase the latency timer value. */ 2108 pci_write_config(dev, PCIR_LATTIMER, 0x80, 1); 2109 break; 2110 case DC_DEVID(DC_VENDORID_ADMTEK, DC_DEVICEID_AL981): 2111 sc->dc_type = DC_TYPE_AL981; 2112 sc->dc_flags |= DC_TX_USE_TX_INTR; 2113 sc->dc_flags |= DC_TX_ADMTEK_WAR; 2114 sc->dc_pmode = DC_PMODE_MII; 2115 error = dc_read_srom(sc, sc->dc_romwidth); 2116 if (error != 0) 2117 goto fail; 2118 break; 2119 case DC_DEVID(DC_VENDORID_ADMTEK, DC_DEVICEID_AN983): 2120 case DC_DEVID(DC_VENDORID_ADMTEK, DC_DEVICEID_AN985): 2121 case DC_DEVID(DC_VENDORID_ADMTEK, DC_DEVICEID_ADM9511): 2122 case DC_DEVID(DC_VENDORID_ADMTEK, DC_DEVICEID_ADM9513): 2123 case DC_DEVID(DC_VENDORID_DLINK, DC_DEVICEID_DRP32TXD): 2124 case DC_DEVID(DC_VENDORID_ABOCOM, DC_DEVICEID_FE2500): 2125 case DC_DEVID(DC_VENDORID_ABOCOM, DC_DEVICEID_FE2500MX): 2126 case DC_DEVID(DC_VENDORID_ACCTON, DC_DEVICEID_EN2242): 2127 case DC_DEVID(DC_VENDORID_HAWKING, DC_DEVICEID_HAWKING_PN672TX): 2128 case DC_DEVID(DC_VENDORID_PLANEX, DC_DEVICEID_FNW3602T): 2129 case DC_DEVID(DC_VENDORID_3COM, DC_DEVICEID_3CSOHOB): 2130 case DC_DEVID(DC_VENDORID_MICROSOFT, DC_DEVICEID_MSMN120): 2131 case DC_DEVID(DC_VENDORID_MICROSOFT, DC_DEVICEID_MSMN130): 2132 case DC_DEVID(DC_VENDORID_LINKSYS, DC_DEVICEID_PCMPC200_AB08): 2133 case DC_DEVID(DC_VENDORID_LINKSYS, DC_DEVICEID_PCMPC200_AB09): 2134 sc->dc_type = DC_TYPE_AN983; 2135 sc->dc_flags |= DC_64BIT_HASH; 2136 sc->dc_flags |= DC_TX_USE_TX_INTR; 2137 sc->dc_flags |= DC_TX_ADMTEK_WAR; 2138 sc->dc_pmode = DC_PMODE_MII; 2139 /* Don't read SROM for - auto-loaded on reset */ 2140 break; 2141 case DC_DEVID(DC_VENDORID_MX, DC_DEVICEID_98713): 2142 case DC_DEVID(DC_VENDORID_CP, DC_DEVICEID_98713_CP): 2143 if (revision < DC_REVISION_98713A) { 2144 sc->dc_type = DC_TYPE_98713; 2145 } 2146 if (revision >= DC_REVISION_98713A) { 2147 sc->dc_type = DC_TYPE_98713A; 2148 sc->dc_flags |= DC_21143_NWAY; 2149 } 2150 sc->dc_flags |= DC_REDUCED_MII_POLL; 2151 sc->dc_flags |= DC_TX_POLL | DC_TX_USE_TX_INTR; 2152 break; 2153 case DC_DEVID(DC_VENDORID_MX, DC_DEVICEID_987x5): 2154 case DC_DEVID(DC_VENDORID_ACCTON, DC_DEVICEID_EN1217): 2155 /* 2156 * Macronix MX98715AEC-C/D/E parts have only a 2157 * 128-bit hash table. We need to deal with these 2158 * in the same manner as the PNIC II so that we 2159 * get the right number of bits out of the 2160 * CRC routine. 2161 */ 2162 if (revision >= DC_REVISION_98715AEC_C && 2163 revision < DC_REVISION_98725) 2164 sc->dc_flags |= DC_128BIT_HASH; 2165 sc->dc_type = DC_TYPE_987x5; 2166 sc->dc_flags |= DC_TX_POLL | DC_TX_USE_TX_INTR; 2167 sc->dc_flags |= DC_REDUCED_MII_POLL | DC_21143_NWAY; 2168 break; 2169 case DC_DEVID(DC_VENDORID_MX, DC_DEVICEID_98727): 2170 sc->dc_type = DC_TYPE_987x5; 2171 sc->dc_flags |= DC_TX_POLL | DC_TX_USE_TX_INTR; 2172 sc->dc_flags |= DC_REDUCED_MII_POLL | DC_21143_NWAY; 2173 break; 2174 case DC_DEVID(DC_VENDORID_LO, DC_DEVICEID_82C115): 2175 sc->dc_type = DC_TYPE_PNICII; 2176 sc->dc_flags |= DC_TX_POLL | DC_TX_USE_TX_INTR | DC_128BIT_HASH; 2177 sc->dc_flags |= DC_REDUCED_MII_POLL | DC_21143_NWAY; 2178 break; 2179 case DC_DEVID(DC_VENDORID_LO, DC_DEVICEID_82C168): 2180 sc->dc_type = DC_TYPE_PNIC; 2181 sc->dc_flags |= DC_TX_STORENFWD | DC_TX_INTR_ALWAYS; 2182 sc->dc_flags |= DC_PNIC_RX_BUG_WAR; 2183 sc->dc_pnic_rx_buf = malloc(DC_RXLEN * 5, M_DEVBUF, M_NOWAIT); 2184 if (sc->dc_pnic_rx_buf == NULL) { 2185 device_printf(sc->dc_dev, 2186 "Could not allocate PNIC RX buffer\n"); 2187 error = ENOMEM; 2188 goto fail; 2189 } 2190 if (revision < DC_REVISION_82C169) 2191 sc->dc_pmode = DC_PMODE_SYM; 2192 break; 2193 case DC_DEVID(DC_VENDORID_ASIX, DC_DEVICEID_AX88140A): 2194 sc->dc_type = DC_TYPE_ASIX; 2195 sc->dc_flags |= DC_TX_USE_TX_INTR | DC_TX_INTR_FIRSTFRAG; 2196 sc->dc_flags |= DC_REDUCED_MII_POLL; 2197 sc->dc_pmode = DC_PMODE_MII; 2198 break; 2199 case DC_DEVID(DC_VENDORID_XIRCOM, DC_DEVICEID_X3201): 2200 sc->dc_type = DC_TYPE_XIRCOM; 2201 sc->dc_flags |= DC_TX_INTR_ALWAYS | DC_TX_COALESCE | 2202 DC_TX_ALIGN; 2203 /* 2204 * We don't actually need to coalesce, but we're doing 2205 * it to obtain a double word aligned buffer. 2206 * The DC_TX_COALESCE flag is required. 2207 */ 2208 sc->dc_pmode = DC_PMODE_MII; 2209 break; 2210 case DC_DEVID(DC_VENDORID_CONEXANT, DC_DEVICEID_RS7112): 2211 sc->dc_type = DC_TYPE_CONEXANT; 2212 sc->dc_flags |= DC_TX_INTR_ALWAYS; 2213 sc->dc_flags |= DC_REDUCED_MII_POLL; 2214 sc->dc_pmode = DC_PMODE_MII; 2215 error = dc_read_srom(sc, sc->dc_romwidth); 2216 if (error != 0) 2217 goto fail; 2218 break; 2219 default: 2220 device_printf(dev, "unknown device: %x\n", 2221 sc->dc_info->dc_devid); 2222 break; 2223 } 2224 2225 /* Save the cache line size. */ 2226 if (DC_IS_DAVICOM(sc)) 2227 sc->dc_cachesize = 0; 2228 else 2229 sc->dc_cachesize = pci_get_cachelnsz(dev); 2230 2231 /* Reset the adapter. */ 2232 dc_reset(sc); 2233 2234 /* Take 21143 out of snooze mode */ 2235 if (DC_IS_INTEL(sc) || DC_IS_XIRCOM(sc)) { 2236 command = pci_read_config(dev, DC_PCI_CFDD, 4); 2237 command &= ~(DC_CFDD_SNOOZE_MODE | DC_CFDD_SLEEP_MODE); 2238 pci_write_config(dev, DC_PCI_CFDD, command, 4); 2239 } 2240 2241 /* 2242 * Try to learn something about the supported media. 2243 * We know that ASIX and ADMtek and Davicom devices 2244 * will *always* be using MII media, so that's a no-brainer. 2245 * The tricky ones are the Macronix/PNIC II and the 2246 * Intel 21143. 2247 */ 2248 if (DC_IS_INTEL(sc)) { 2249 error = dc_parse_21143_srom(sc); 2250 if (error != 0) 2251 goto fail; 2252 } else if (DC_IS_MACRONIX(sc) || DC_IS_PNICII(sc)) { 2253 if (sc->dc_type == DC_TYPE_98713) 2254 sc->dc_pmode = DC_PMODE_MII; 2255 else 2256 sc->dc_pmode = DC_PMODE_SYM; 2257 } else if (!sc->dc_pmode) 2258 sc->dc_pmode = DC_PMODE_MII; 2259 2260 /* 2261 * Get station address from the EEPROM. 2262 */ 2263 switch(sc->dc_type) { 2264 case DC_TYPE_98713: 2265 case DC_TYPE_98713A: 2266 case DC_TYPE_987x5: 2267 case DC_TYPE_PNICII: 2268 dc_read_eeprom(sc, (caddr_t)&mac_offset, 2269 (DC_EE_NODEADDR_OFFSET / 2), 1, 0); 2270 dc_read_eeprom(sc, (caddr_t)&eaddr, (mac_offset / 2), 3, 0); 2271 break; 2272 case DC_TYPE_PNIC: 2273 dc_read_eeprom(sc, (caddr_t)&eaddr, 0, 3, 1); 2274 break; 2275 case DC_TYPE_DM9102: 2276 dc_read_eeprom(sc, (caddr_t)&eaddr, DC_EE_NODEADDR, 3, 0); 2277 #ifdef __sparc64__ 2278 /* 2279 * If this is an onboard dc(4) the station address read from 2280 * the EEPROM is all zero and we have to get it from the FCode. 2281 */ 2282 if (eaddr[0] == 0 && (eaddr[1] & ~0xffff) == 0) 2283 OF_getetheraddr(dev, (caddr_t)&eaddr); 2284 #endif 2285 break; 2286 case DC_TYPE_21143: 2287 case DC_TYPE_ASIX: 2288 dc_read_eeprom(sc, (caddr_t)&eaddr, DC_EE_NODEADDR, 3, 0); 2289 break; 2290 case DC_TYPE_AL981: 2291 case DC_TYPE_AN983: 2292 reg = CSR_READ_4(sc, DC_AL_PAR0); 2293 mac = (uint8_t *)&eaddr[0]; 2294 mac[0] = (reg >> 0) & 0xff; 2295 mac[1] = (reg >> 8) & 0xff; 2296 mac[2] = (reg >> 16) & 0xff; 2297 mac[3] = (reg >> 24) & 0xff; 2298 reg = CSR_READ_4(sc, DC_AL_PAR1); 2299 mac[4] = (reg >> 0) & 0xff; 2300 mac[5] = (reg >> 8) & 0xff; 2301 break; 2302 case DC_TYPE_CONEXANT: 2303 bcopy(sc->dc_srom + DC_CONEXANT_EE_NODEADDR, &eaddr, 2304 ETHER_ADDR_LEN); 2305 break; 2306 case DC_TYPE_XIRCOM: 2307 /* The MAC comes from the CIS. */ 2308 mac = pci_get_ether(dev); 2309 if (!mac) { 2310 device_printf(dev, "No station address in CIS!\n"); 2311 error = ENXIO; 2312 goto fail; 2313 } 2314 bcopy(mac, eaddr, ETHER_ADDR_LEN); 2315 break; 2316 default: 2317 dc_read_eeprom(sc, (caddr_t)&eaddr, DC_EE_NODEADDR, 3, 0); 2318 break; 2319 } 2320 2321 bcopy(eaddr, sc->dc_eaddr, sizeof(eaddr)); 2322 /* 2323 * If we still have invalid station address, see whether we can 2324 * find station address for chip 0. Some multi-port controllers 2325 * just store station address for chip 0 if they have a shared 2326 * SROM. 2327 */ 2328 if ((sc->dc_eaddr[0] == 0 && (sc->dc_eaddr[1] & ~0xffff) == 0) || 2329 (sc->dc_eaddr[0] == 0xffffffff && 2330 (sc->dc_eaddr[1] & 0xffff) == 0xffff)) { 2331 error = dc_check_multiport(sc); 2332 if (error == 0) { 2333 bcopy(sc->dc_eaddr, eaddr, sizeof(eaddr)); 2334 /* Extract media information. */ 2335 if (DC_IS_INTEL(sc) && sc->dc_srom != NULL) { 2336 while (sc->dc_mi != NULL) { 2337 m = sc->dc_mi->dc_next; 2338 free(sc->dc_mi, M_DEVBUF); 2339 sc->dc_mi = m; 2340 } 2341 error = dc_parse_21143_srom(sc); 2342 if (error != 0) 2343 goto fail; 2344 } 2345 } else if (error == ENOMEM) 2346 goto fail; 2347 else 2348 error = 0; 2349 } 2350 2351 if ((error = dc_dma_alloc(sc)) != 0) 2352 goto fail; 2353 2354 ifp = sc->dc_ifp = if_alloc(IFT_ETHER); 2355 if (ifp == NULL) { 2356 device_printf(dev, "can not if_alloc()\n"); 2357 error = ENOSPC; 2358 goto fail; 2359 } 2360 ifp->if_softc = sc; 2361 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 2362 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 2363 ifp->if_ioctl = dc_ioctl; 2364 ifp->if_start = dc_start; 2365 ifp->if_init = dc_init; 2366 IFQ_SET_MAXLEN(&ifp->if_snd, DC_TX_LIST_CNT - 1); 2367 ifp->if_snd.ifq_drv_maxlen = DC_TX_LIST_CNT - 1; 2368 IFQ_SET_READY(&ifp->if_snd); 2369 2370 /* 2371 * Do MII setup. If this is a 21143, check for a PHY on the 2372 * MII bus after applying any necessary fixups to twiddle the 2373 * GPIO bits. If we don't end up finding a PHY, restore the 2374 * old selection (SIA only or SIA/SYM) and attach the dcphy 2375 * driver instead. 2376 */ 2377 tmp = 0; 2378 if (DC_IS_INTEL(sc)) { 2379 dc_apply_fixup(sc, IFM_AUTO); 2380 tmp = sc->dc_pmode; 2381 sc->dc_pmode = DC_PMODE_MII; 2382 } 2383 2384 /* 2385 * Setup General Purpose port mode and data so the tulip can talk 2386 * to the MII. This needs to be done before mii_attach so that 2387 * we can actually see them. 2388 */ 2389 if (DC_IS_XIRCOM(sc)) { 2390 CSR_WRITE_4(sc, DC_SIAGP, DC_SIAGP_WRITE_EN | DC_SIAGP_INT1_EN | 2391 DC_SIAGP_MD_GP2_OUTPUT | DC_SIAGP_MD_GP0_OUTPUT); 2392 DELAY(10); 2393 CSR_WRITE_4(sc, DC_SIAGP, DC_SIAGP_INT1_EN | 2394 DC_SIAGP_MD_GP2_OUTPUT | DC_SIAGP_MD_GP0_OUTPUT); 2395 DELAY(10); 2396 } 2397 2398 phy = MII_PHY_ANY; 2399 /* 2400 * Note: both the AL981 and AN983 have internal PHYs, however the 2401 * AL981 provides direct access to the PHY registers while the AN983 2402 * uses a serial MII interface. The AN983's MII interface is also 2403 * buggy in that you can read from any MII address (0 to 31), but 2404 * only address 1 behaves normally. To deal with both cases, we 2405 * pretend that the PHY is at MII address 1. 2406 */ 2407 if (DC_IS_ADMTEK(sc)) 2408 phy = DC_ADMTEK_PHYADDR; 2409 2410 /* 2411 * Note: the ukphy probes of the RS7112 report a PHY at MII address 2412 * 0 (possibly HomePNA?) and 1 (ethernet) so we only respond to the 2413 * correct one. 2414 */ 2415 if (DC_IS_CONEXANT(sc)) 2416 phy = DC_CONEXANT_PHYADDR; 2417 2418 error = mii_attach(dev, &sc->dc_miibus, ifp, dc_ifmedia_upd, 2419 dc_ifmedia_sts, BMSR_DEFCAPMASK, phy, MII_OFFSET_ANY, 0); 2420 2421 if (error && DC_IS_INTEL(sc)) { 2422 sc->dc_pmode = tmp; 2423 if (sc->dc_pmode != DC_PMODE_SIA) 2424 sc->dc_pmode = DC_PMODE_SYM; 2425 sc->dc_flags |= DC_21143_NWAY; 2426 mii_attach(dev, &sc->dc_miibus, ifp, dc_ifmedia_upd, 2427 dc_ifmedia_sts, BMSR_DEFCAPMASK, MII_PHY_ANY, 2428 MII_OFFSET_ANY, 0); 2429 /* 2430 * For non-MII cards, we need to have the 21143 2431 * drive the LEDs. Except there are some systems 2432 * like the NEC VersaPro NoteBook PC which have no 2433 * LEDs, and twiddling these bits has adverse effects 2434 * on them. (I.e. you suddenly can't get a link.) 2435 */ 2436 if (!(pci_get_subvendor(dev) == 0x1033 && 2437 pci_get_subdevice(dev) == 0x8028)) 2438 sc->dc_flags |= DC_TULIP_LEDS; 2439 error = 0; 2440 } 2441 2442 if (error) { 2443 device_printf(dev, "attaching PHYs failed\n"); 2444 goto fail; 2445 } 2446 2447 if (DC_IS_ADMTEK(sc)) { 2448 /* 2449 * Set automatic TX underrun recovery for the ADMtek chips 2450 */ 2451 DC_SETBIT(sc, DC_AL_CR, DC_AL_CR_ATUR); 2452 } 2453 2454 /* 2455 * Tell the upper layer(s) we support long frames. 2456 */ 2457 ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header); 2458 ifp->if_capabilities |= IFCAP_VLAN_MTU; 2459 ifp->if_capenable = ifp->if_capabilities; 2460 #ifdef DEVICE_POLLING 2461 ifp->if_capabilities |= IFCAP_POLLING; 2462 #endif 2463 2464 callout_init_mtx(&sc->dc_stat_ch, &sc->dc_mtx, 0); 2465 callout_init_mtx(&sc->dc_wdog_ch, &sc->dc_mtx, 0); 2466 2467 /* 2468 * Call MI attach routine. 2469 */ 2470 ether_ifattach(ifp, (caddr_t)eaddr); 2471 2472 /* Hook interrupt last to avoid having to lock softc */ 2473 error = bus_setup_intr(dev, sc->dc_irq, INTR_TYPE_NET | INTR_MPSAFE, 2474 NULL, dc_intr, sc, &sc->dc_intrhand); 2475 2476 if (error) { 2477 device_printf(dev, "couldn't set up irq\n"); 2478 ether_ifdetach(ifp); 2479 goto fail; 2480 } 2481 2482 fail: 2483 if (error) 2484 dc_detach(dev); 2485 return (error); 2486 } 2487 2488 /* 2489 * Shutdown hardware and free up resources. This can be called any 2490 * time after the mutex has been initialized. It is called in both 2491 * the error case in attach and the normal detach case so it needs 2492 * to be careful about only freeing resources that have actually been 2493 * allocated. 2494 */ 2495 static int 2496 dc_detach(device_t dev) 2497 { 2498 struct dc_softc *sc; 2499 struct ifnet *ifp; 2500 struct dc_mediainfo *m; 2501 2502 sc = device_get_softc(dev); 2503 KASSERT(mtx_initialized(&sc->dc_mtx), ("dc mutex not initialized")); 2504 2505 ifp = sc->dc_ifp; 2506 2507 #ifdef DEVICE_POLLING 2508 if (ifp->if_capenable & IFCAP_POLLING) 2509 ether_poll_deregister(ifp); 2510 #endif 2511 2512 /* These should only be active if attach succeeded */ 2513 if (device_is_attached(dev)) { 2514 DC_LOCK(sc); 2515 dc_stop(sc); 2516 DC_UNLOCK(sc); 2517 callout_drain(&sc->dc_stat_ch); 2518 callout_drain(&sc->dc_wdog_ch); 2519 ether_ifdetach(ifp); 2520 } 2521 if (sc->dc_miibus) 2522 device_delete_child(dev, sc->dc_miibus); 2523 bus_generic_detach(dev); 2524 2525 if (sc->dc_intrhand) 2526 bus_teardown_intr(dev, sc->dc_irq, sc->dc_intrhand); 2527 if (sc->dc_irq) 2528 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->dc_irq); 2529 if (sc->dc_res) 2530 bus_release_resource(dev, DC_RES, DC_RID, sc->dc_res); 2531 2532 if (ifp) 2533 if_free(ifp); 2534 2535 dc_dma_free(sc); 2536 2537 free(sc->dc_pnic_rx_buf, M_DEVBUF); 2538 2539 while (sc->dc_mi != NULL) { 2540 m = sc->dc_mi->dc_next; 2541 free(sc->dc_mi, M_DEVBUF); 2542 sc->dc_mi = m; 2543 } 2544 free(sc->dc_srom, M_DEVBUF); 2545 2546 mtx_destroy(&sc->dc_mtx); 2547 2548 return (0); 2549 } 2550 2551 /* 2552 * Initialize the transmit descriptors. 2553 */ 2554 static int 2555 dc_list_tx_init(struct dc_softc *sc) 2556 { 2557 struct dc_chain_data *cd; 2558 struct dc_list_data *ld; 2559 int i, nexti; 2560 2561 cd = &sc->dc_cdata; 2562 ld = &sc->dc_ldata; 2563 for (i = 0; i < DC_TX_LIST_CNT; i++) { 2564 if (i == DC_TX_LIST_CNT - 1) 2565 nexti = 0; 2566 else 2567 nexti = i + 1; 2568 ld->dc_tx_list[i].dc_status = 0; 2569 ld->dc_tx_list[i].dc_ctl = 0; 2570 ld->dc_tx_list[i].dc_data = 0; 2571 ld->dc_tx_list[i].dc_next = htole32(DC_TXDESC(sc, nexti)); 2572 cd->dc_tx_chain[i] = NULL; 2573 } 2574 2575 cd->dc_tx_prod = cd->dc_tx_cons = cd->dc_tx_cnt = 0; 2576 cd->dc_tx_pkts = 0; 2577 bus_dmamap_sync(sc->dc_tx_ltag, sc->dc_tx_lmap, 2578 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2579 return (0); 2580 } 2581 2582 2583 /* 2584 * Initialize the RX descriptors and allocate mbufs for them. Note that 2585 * we arrange the descriptors in a closed ring, so that the last descriptor 2586 * points back to the first. 2587 */ 2588 static int 2589 dc_list_rx_init(struct dc_softc *sc) 2590 { 2591 struct dc_chain_data *cd; 2592 struct dc_list_data *ld; 2593 int i, nexti; 2594 2595 cd = &sc->dc_cdata; 2596 ld = &sc->dc_ldata; 2597 2598 for (i = 0; i < DC_RX_LIST_CNT; i++) { 2599 if (dc_newbuf(sc, i) != 0) 2600 return (ENOBUFS); 2601 if (i == DC_RX_LIST_CNT - 1) 2602 nexti = 0; 2603 else 2604 nexti = i + 1; 2605 ld->dc_rx_list[i].dc_next = htole32(DC_RXDESC(sc, nexti)); 2606 } 2607 2608 cd->dc_rx_prod = 0; 2609 bus_dmamap_sync(sc->dc_rx_ltag, sc->dc_rx_lmap, 2610 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2611 return (0); 2612 } 2613 2614 /* 2615 * Initialize an RX descriptor and attach an MBUF cluster. 2616 */ 2617 static int 2618 dc_newbuf(struct dc_softc *sc, int i) 2619 { 2620 struct mbuf *m; 2621 bus_dmamap_t map; 2622 bus_dma_segment_t segs[1]; 2623 int error, nseg; 2624 2625 m = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR); 2626 if (m == NULL) 2627 return (ENOBUFS); 2628 m->m_len = m->m_pkthdr.len = MCLBYTES; 2629 m_adj(m, sizeof(u_int64_t)); 2630 2631 /* 2632 * If this is a PNIC chip, zero the buffer. This is part 2633 * of the workaround for the receive bug in the 82c168 and 2634 * 82c169 chips. 2635 */ 2636 if (sc->dc_flags & DC_PNIC_RX_BUG_WAR) 2637 bzero(mtod(m, char *), m->m_len); 2638 2639 error = bus_dmamap_load_mbuf_sg(sc->dc_rx_mtag, sc->dc_sparemap, 2640 m, segs, &nseg, 0); 2641 if (error) { 2642 m_freem(m); 2643 return (error); 2644 } 2645 KASSERT(nseg == 1, ("%s: wrong number of segments (%d)", __func__, 2646 nseg)); 2647 if (sc->dc_cdata.dc_rx_chain[i] != NULL) 2648 bus_dmamap_unload(sc->dc_rx_mtag, sc->dc_cdata.dc_rx_map[i]); 2649 2650 map = sc->dc_cdata.dc_rx_map[i]; 2651 sc->dc_cdata.dc_rx_map[i] = sc->dc_sparemap; 2652 sc->dc_sparemap = map; 2653 sc->dc_cdata.dc_rx_chain[i] = m; 2654 bus_dmamap_sync(sc->dc_rx_mtag, sc->dc_cdata.dc_rx_map[i], 2655 BUS_DMASYNC_PREREAD); 2656 2657 sc->dc_ldata.dc_rx_list[i].dc_ctl = htole32(DC_RXCTL_RLINK | DC_RXLEN); 2658 sc->dc_ldata.dc_rx_list[i].dc_data = 2659 htole32(DC_ADDR_LO(segs[0].ds_addr)); 2660 sc->dc_ldata.dc_rx_list[i].dc_status = htole32(DC_RXSTAT_OWN); 2661 bus_dmamap_sync(sc->dc_rx_ltag, sc->dc_rx_lmap, 2662 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2663 return (0); 2664 } 2665 2666 /* 2667 * Grrrrr. 2668 * The PNIC chip has a terrible bug in it that manifests itself during 2669 * periods of heavy activity. The exact mode of failure if difficult to 2670 * pinpoint: sometimes it only happens in promiscuous mode, sometimes it 2671 * will happen on slow machines. The bug is that sometimes instead of 2672 * uploading one complete frame during reception, it uploads what looks 2673 * like the entire contents of its FIFO memory. The frame we want is at 2674 * the end of the whole mess, but we never know exactly how much data has 2675 * been uploaded, so salvaging the frame is hard. 2676 * 2677 * There is only one way to do it reliably, and it's disgusting. 2678 * Here's what we know: 2679 * 2680 * - We know there will always be somewhere between one and three extra 2681 * descriptors uploaded. 2682 * 2683 * - We know the desired received frame will always be at the end of the 2684 * total data upload. 2685 * 2686 * - We know the size of the desired received frame because it will be 2687 * provided in the length field of the status word in the last descriptor. 2688 * 2689 * Here's what we do: 2690 * 2691 * - When we allocate buffers for the receive ring, we bzero() them. 2692 * This means that we know that the buffer contents should be all 2693 * zeros, except for data uploaded by the chip. 2694 * 2695 * - We also force the PNIC chip to upload frames that include the 2696 * ethernet CRC at the end. 2697 * 2698 * - We gather all of the bogus frame data into a single buffer. 2699 * 2700 * - We then position a pointer at the end of this buffer and scan 2701 * backwards until we encounter the first non-zero byte of data. 2702 * This is the end of the received frame. We know we will encounter 2703 * some data at the end of the frame because the CRC will always be 2704 * there, so even if the sender transmits a packet of all zeros, 2705 * we won't be fooled. 2706 * 2707 * - We know the size of the actual received frame, so we subtract 2708 * that value from the current pointer location. This brings us 2709 * to the start of the actual received packet. 2710 * 2711 * - We copy this into an mbuf and pass it on, along with the actual 2712 * frame length. 2713 * 2714 * The performance hit is tremendous, but it beats dropping frames all 2715 * the time. 2716 */ 2717 2718 #define DC_WHOLEFRAME (DC_RXSTAT_FIRSTFRAG | DC_RXSTAT_LASTFRAG) 2719 static void 2720 dc_pnic_rx_bug_war(struct dc_softc *sc, int idx) 2721 { 2722 struct dc_desc *cur_rx; 2723 struct dc_desc *c = NULL; 2724 struct mbuf *m = NULL; 2725 unsigned char *ptr; 2726 int i, total_len; 2727 uint32_t rxstat = 0; 2728 2729 i = sc->dc_pnic_rx_bug_save; 2730 cur_rx = &sc->dc_ldata.dc_rx_list[idx]; 2731 ptr = sc->dc_pnic_rx_buf; 2732 bzero(ptr, DC_RXLEN * 5); 2733 2734 /* Copy all the bytes from the bogus buffers. */ 2735 while (1) { 2736 c = &sc->dc_ldata.dc_rx_list[i]; 2737 rxstat = le32toh(c->dc_status); 2738 m = sc->dc_cdata.dc_rx_chain[i]; 2739 bcopy(mtod(m, char *), ptr, DC_RXLEN); 2740 ptr += DC_RXLEN; 2741 /* If this is the last buffer, break out. */ 2742 if (i == idx || rxstat & DC_RXSTAT_LASTFRAG) 2743 break; 2744 dc_discard_rxbuf(sc, i); 2745 DC_INC(i, DC_RX_LIST_CNT); 2746 } 2747 2748 /* Find the length of the actual receive frame. */ 2749 total_len = DC_RXBYTES(rxstat); 2750 2751 /* Scan backwards until we hit a non-zero byte. */ 2752 while (*ptr == 0x00) 2753 ptr--; 2754 2755 /* Round off. */ 2756 if ((uintptr_t)(ptr) & 0x3) 2757 ptr -= 1; 2758 2759 /* Now find the start of the frame. */ 2760 ptr -= total_len; 2761 if (ptr < sc->dc_pnic_rx_buf) 2762 ptr = sc->dc_pnic_rx_buf; 2763 2764 /* 2765 * Now copy the salvaged frame to the last mbuf and fake up 2766 * the status word to make it look like a successful 2767 * frame reception. 2768 */ 2769 bcopy(ptr, mtod(m, char *), total_len); 2770 cur_rx->dc_status = htole32(rxstat | DC_RXSTAT_FIRSTFRAG); 2771 } 2772 2773 /* 2774 * This routine searches the RX ring for dirty descriptors in the 2775 * event that the rxeof routine falls out of sync with the chip's 2776 * current descriptor pointer. This may happen sometimes as a result 2777 * of a "no RX buffer available" condition that happens when the chip 2778 * consumes all of the RX buffers before the driver has a chance to 2779 * process the RX ring. This routine may need to be called more than 2780 * once to bring the driver back in sync with the chip, however we 2781 * should still be getting RX DONE interrupts to drive the search 2782 * for new packets in the RX ring, so we should catch up eventually. 2783 */ 2784 static int 2785 dc_rx_resync(struct dc_softc *sc) 2786 { 2787 struct dc_desc *cur_rx; 2788 int i, pos; 2789 2790 pos = sc->dc_cdata.dc_rx_prod; 2791 2792 for (i = 0; i < DC_RX_LIST_CNT; i++) { 2793 cur_rx = &sc->dc_ldata.dc_rx_list[pos]; 2794 if (!(le32toh(cur_rx->dc_status) & DC_RXSTAT_OWN)) 2795 break; 2796 DC_INC(pos, DC_RX_LIST_CNT); 2797 } 2798 2799 /* If the ring really is empty, then just return. */ 2800 if (i == DC_RX_LIST_CNT) 2801 return (0); 2802 2803 /* We've fallen behing the chip: catch it. */ 2804 sc->dc_cdata.dc_rx_prod = pos; 2805 2806 return (EAGAIN); 2807 } 2808 2809 static void 2810 dc_discard_rxbuf(struct dc_softc *sc, int i) 2811 { 2812 struct mbuf *m; 2813 2814 if (sc->dc_flags & DC_PNIC_RX_BUG_WAR) { 2815 m = sc->dc_cdata.dc_rx_chain[i]; 2816 bzero(mtod(m, char *), m->m_len); 2817 } 2818 2819 sc->dc_ldata.dc_rx_list[i].dc_ctl = htole32(DC_RXCTL_RLINK | DC_RXLEN); 2820 sc->dc_ldata.dc_rx_list[i].dc_status = htole32(DC_RXSTAT_OWN); 2821 bus_dmamap_sync(sc->dc_rx_ltag, sc->dc_rx_lmap, BUS_DMASYNC_PREREAD | 2822 BUS_DMASYNC_PREWRITE); 2823 } 2824 2825 /* 2826 * A frame has been uploaded: pass the resulting mbuf chain up to 2827 * the higher level protocols. 2828 */ 2829 static int 2830 dc_rxeof(struct dc_softc *sc) 2831 { 2832 struct mbuf *m; 2833 struct ifnet *ifp; 2834 struct dc_desc *cur_rx; 2835 int i, total_len, rx_npkts; 2836 uint32_t rxstat; 2837 2838 DC_LOCK_ASSERT(sc); 2839 2840 ifp = sc->dc_ifp; 2841 rx_npkts = 0; 2842 2843 bus_dmamap_sync(sc->dc_rx_ltag, sc->dc_rx_lmap, BUS_DMASYNC_POSTREAD | 2844 BUS_DMASYNC_POSTWRITE); 2845 for (i = sc->dc_cdata.dc_rx_prod; 2846 (ifp->if_drv_flags & IFF_DRV_RUNNING) != 0; 2847 DC_INC(i, DC_RX_LIST_CNT)) { 2848 #ifdef DEVICE_POLLING 2849 if (ifp->if_capenable & IFCAP_POLLING) { 2850 if (sc->rxcycles <= 0) 2851 break; 2852 sc->rxcycles--; 2853 } 2854 #endif 2855 cur_rx = &sc->dc_ldata.dc_rx_list[i]; 2856 rxstat = le32toh(cur_rx->dc_status); 2857 if ((rxstat & DC_RXSTAT_OWN) != 0) 2858 break; 2859 m = sc->dc_cdata.dc_rx_chain[i]; 2860 bus_dmamap_sync(sc->dc_rx_mtag, sc->dc_cdata.dc_rx_map[i], 2861 BUS_DMASYNC_POSTREAD); 2862 total_len = DC_RXBYTES(rxstat); 2863 rx_npkts++; 2864 2865 if (sc->dc_flags & DC_PNIC_RX_BUG_WAR) { 2866 if ((rxstat & DC_WHOLEFRAME) != DC_WHOLEFRAME) { 2867 if (rxstat & DC_RXSTAT_FIRSTFRAG) 2868 sc->dc_pnic_rx_bug_save = i; 2869 if ((rxstat & DC_RXSTAT_LASTFRAG) == 0) 2870 continue; 2871 dc_pnic_rx_bug_war(sc, i); 2872 rxstat = le32toh(cur_rx->dc_status); 2873 total_len = DC_RXBYTES(rxstat); 2874 } 2875 } 2876 2877 /* 2878 * If an error occurs, update stats, clear the 2879 * status word and leave the mbuf cluster in place: 2880 * it should simply get re-used next time this descriptor 2881 * comes up in the ring. However, don't report long 2882 * frames as errors since they could be vlans. 2883 */ 2884 if ((rxstat & DC_RXSTAT_RXERR)) { 2885 if (!(rxstat & DC_RXSTAT_GIANT) || 2886 (rxstat & (DC_RXSTAT_CRCERR | DC_RXSTAT_DRIBBLE | 2887 DC_RXSTAT_MIIERE | DC_RXSTAT_COLLSEEN | 2888 DC_RXSTAT_RUNT | DC_RXSTAT_DE))) { 2889 ifp->if_ierrors++; 2890 if (rxstat & DC_RXSTAT_COLLSEEN) 2891 ifp->if_collisions++; 2892 dc_discard_rxbuf(sc, i); 2893 if (rxstat & DC_RXSTAT_CRCERR) 2894 continue; 2895 else { 2896 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 2897 dc_init_locked(sc); 2898 return (rx_npkts); 2899 } 2900 } 2901 } 2902 2903 /* No errors; receive the packet. */ 2904 total_len -= ETHER_CRC_LEN; 2905 #ifdef __NO_STRICT_ALIGNMENT 2906 /* 2907 * On architectures without alignment problems we try to 2908 * allocate a new buffer for the receive ring, and pass up 2909 * the one where the packet is already, saving the expensive 2910 * copy done in m_devget(). 2911 * If we are on an architecture with alignment problems, or 2912 * if the allocation fails, then use m_devget and leave the 2913 * existing buffer in the receive ring. 2914 */ 2915 if (dc_newbuf(sc, i) != 0) { 2916 dc_discard_rxbuf(sc, i); 2917 ifp->if_iqdrops++; 2918 continue; 2919 } 2920 m->m_pkthdr.rcvif = ifp; 2921 m->m_pkthdr.len = m->m_len = total_len; 2922 #else 2923 { 2924 struct mbuf *m0; 2925 2926 m0 = m_devget(mtod(m, char *), total_len, 2927 ETHER_ALIGN, ifp, NULL); 2928 dc_discard_rxbuf(sc, i); 2929 if (m0 == NULL) { 2930 ifp->if_iqdrops++; 2931 continue; 2932 } 2933 m = m0; 2934 } 2935 #endif 2936 2937 ifp->if_ipackets++; 2938 DC_UNLOCK(sc); 2939 (*ifp->if_input)(ifp, m); 2940 DC_LOCK(sc); 2941 } 2942 2943 sc->dc_cdata.dc_rx_prod = i; 2944 return (rx_npkts); 2945 } 2946 2947 /* 2948 * A frame was downloaded to the chip. It's safe for us to clean up 2949 * the list buffers. 2950 */ 2951 static void 2952 dc_txeof(struct dc_softc *sc) 2953 { 2954 struct dc_desc *cur_tx; 2955 struct ifnet *ifp; 2956 int idx, setup; 2957 uint32_t ctl, txstat; 2958 2959 if (sc->dc_cdata.dc_tx_cnt == 0) 2960 return; 2961 2962 ifp = sc->dc_ifp; 2963 2964 /* 2965 * Go through our tx list and free mbufs for those 2966 * frames that have been transmitted. 2967 */ 2968 bus_dmamap_sync(sc->dc_rx_ltag, sc->dc_tx_lmap, BUS_DMASYNC_POSTREAD | 2969 BUS_DMASYNC_POSTWRITE); 2970 setup = 0; 2971 for (idx = sc->dc_cdata.dc_tx_cons; idx != sc->dc_cdata.dc_tx_prod; 2972 DC_INC(idx, DC_TX_LIST_CNT), sc->dc_cdata.dc_tx_cnt--) { 2973 cur_tx = &sc->dc_ldata.dc_tx_list[idx]; 2974 txstat = le32toh(cur_tx->dc_status); 2975 ctl = le32toh(cur_tx->dc_ctl); 2976 2977 if (txstat & DC_TXSTAT_OWN) 2978 break; 2979 2980 if (sc->dc_cdata.dc_tx_chain[idx] == NULL) 2981 continue; 2982 2983 if (ctl & DC_TXCTL_SETUP) { 2984 cur_tx->dc_ctl = htole32(ctl & ~DC_TXCTL_SETUP); 2985 setup++; 2986 bus_dmamap_sync(sc->dc_stag, sc->dc_smap, 2987 BUS_DMASYNC_POSTWRITE); 2988 /* 2989 * Yes, the PNIC is so brain damaged 2990 * that it will sometimes generate a TX 2991 * underrun error while DMAing the RX 2992 * filter setup frame. If we detect this, 2993 * we have to send the setup frame again, 2994 * or else the filter won't be programmed 2995 * correctly. 2996 */ 2997 if (DC_IS_PNIC(sc)) { 2998 if (txstat & DC_TXSTAT_ERRSUM) 2999 dc_setfilt(sc); 3000 } 3001 sc->dc_cdata.dc_tx_chain[idx] = NULL; 3002 continue; 3003 } 3004 3005 if (DC_IS_XIRCOM(sc) || DC_IS_CONEXANT(sc)) { 3006 /* 3007 * XXX: Why does my Xircom taunt me so? 3008 * For some reason it likes setting the CARRLOST flag 3009 * even when the carrier is there. wtf?!? 3010 * Who knows, but Conexant chips have the 3011 * same problem. Maybe they took lessons 3012 * from Xircom. 3013 */ 3014 if (/*sc->dc_type == DC_TYPE_21143 &&*/ 3015 sc->dc_pmode == DC_PMODE_MII && 3016 ((txstat & 0xFFFF) & ~(DC_TXSTAT_ERRSUM | 3017 DC_TXSTAT_NOCARRIER))) 3018 txstat &= ~DC_TXSTAT_ERRSUM; 3019 } else { 3020 if (/*sc->dc_type == DC_TYPE_21143 &&*/ 3021 sc->dc_pmode == DC_PMODE_MII && 3022 ((txstat & 0xFFFF) & ~(DC_TXSTAT_ERRSUM | 3023 DC_TXSTAT_NOCARRIER | DC_TXSTAT_CARRLOST))) 3024 txstat &= ~DC_TXSTAT_ERRSUM; 3025 } 3026 3027 if (txstat & DC_TXSTAT_ERRSUM) { 3028 ifp->if_oerrors++; 3029 if (txstat & DC_TXSTAT_EXCESSCOLL) 3030 ifp->if_collisions++; 3031 if (txstat & DC_TXSTAT_LATECOLL) 3032 ifp->if_collisions++; 3033 if (!(txstat & DC_TXSTAT_UNDERRUN)) { 3034 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 3035 dc_init_locked(sc); 3036 return; 3037 } 3038 } else 3039 ifp->if_opackets++; 3040 ifp->if_collisions += (txstat & DC_TXSTAT_COLLCNT) >> 3; 3041 3042 bus_dmamap_sync(sc->dc_tx_mtag, sc->dc_cdata.dc_tx_map[idx], 3043 BUS_DMASYNC_POSTWRITE); 3044 bus_dmamap_unload(sc->dc_tx_mtag, sc->dc_cdata.dc_tx_map[idx]); 3045 m_freem(sc->dc_cdata.dc_tx_chain[idx]); 3046 sc->dc_cdata.dc_tx_chain[idx] = NULL; 3047 } 3048 sc->dc_cdata.dc_tx_cons = idx; 3049 3050 if (sc->dc_cdata.dc_tx_cnt <= DC_TX_LIST_CNT - DC_TX_LIST_RSVD) { 3051 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 3052 if (sc->dc_cdata.dc_tx_cnt == 0) 3053 sc->dc_wdog_timer = 0; 3054 } 3055 if (setup > 0) 3056 bus_dmamap_sync(sc->dc_tx_ltag, sc->dc_tx_lmap, 3057 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 3058 } 3059 3060 static void 3061 dc_tick(void *xsc) 3062 { 3063 struct dc_softc *sc; 3064 struct mii_data *mii; 3065 struct ifnet *ifp; 3066 uint32_t r; 3067 3068 sc = xsc; 3069 DC_LOCK_ASSERT(sc); 3070 ifp = sc->dc_ifp; 3071 mii = device_get_softc(sc->dc_miibus); 3072 3073 /* 3074 * Reclaim transmitted frames for controllers that do 3075 * not generate TX completion interrupt for every frame. 3076 */ 3077 if (sc->dc_flags & DC_TX_USE_TX_INTR) 3078 dc_txeof(sc); 3079 3080 if (sc->dc_flags & DC_REDUCED_MII_POLL) { 3081 if (sc->dc_flags & DC_21143_NWAY) { 3082 r = CSR_READ_4(sc, DC_10BTSTAT); 3083 if (IFM_SUBTYPE(mii->mii_media_active) == 3084 IFM_100_TX && (r & DC_TSTAT_LS100)) { 3085 sc->dc_link = 0; 3086 mii_mediachg(mii); 3087 } 3088 if (IFM_SUBTYPE(mii->mii_media_active) == 3089 IFM_10_T && (r & DC_TSTAT_LS10)) { 3090 sc->dc_link = 0; 3091 mii_mediachg(mii); 3092 } 3093 if (sc->dc_link == 0) 3094 mii_tick(mii); 3095 } else { 3096 /* 3097 * For NICs which never report DC_RXSTATE_WAIT, we 3098 * have to bite the bullet... 3099 */ 3100 if ((DC_HAS_BROKEN_RXSTATE(sc) || (CSR_READ_4(sc, 3101 DC_ISR) & DC_ISR_RX_STATE) == DC_RXSTATE_WAIT) && 3102 sc->dc_cdata.dc_tx_cnt == 0) 3103 mii_tick(mii); 3104 } 3105 } else 3106 mii_tick(mii); 3107 3108 /* 3109 * When the init routine completes, we expect to be able to send 3110 * packets right away, and in fact the network code will send a 3111 * gratuitous ARP the moment the init routine marks the interface 3112 * as running. However, even though the MAC may have been initialized, 3113 * there may be a delay of a few seconds before the PHY completes 3114 * autonegotiation and the link is brought up. Any transmissions 3115 * made during that delay will be lost. Dealing with this is tricky: 3116 * we can't just pause in the init routine while waiting for the 3117 * PHY to come ready since that would bring the whole system to 3118 * a screeching halt for several seconds. 3119 * 3120 * What we do here is prevent the TX start routine from sending 3121 * any packets until a link has been established. After the 3122 * interface has been initialized, the tick routine will poll 3123 * the state of the PHY until the IFM_ACTIVE flag is set. Until 3124 * that time, packets will stay in the send queue, and once the 3125 * link comes up, they will be flushed out to the wire. 3126 */ 3127 if (sc->dc_link != 0 && !IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 3128 dc_start_locked(ifp); 3129 3130 if (sc->dc_flags & DC_21143_NWAY && !sc->dc_link) 3131 callout_reset(&sc->dc_stat_ch, hz/10, dc_tick, sc); 3132 else 3133 callout_reset(&sc->dc_stat_ch, hz, dc_tick, sc); 3134 } 3135 3136 /* 3137 * A transmit underrun has occurred. Back off the transmit threshold, 3138 * or switch to store and forward mode if we have to. 3139 */ 3140 static void 3141 dc_tx_underrun(struct dc_softc *sc) 3142 { 3143 uint32_t netcfg, isr; 3144 int i, reinit; 3145 3146 reinit = 0; 3147 netcfg = CSR_READ_4(sc, DC_NETCFG); 3148 device_printf(sc->dc_dev, "TX underrun -- "); 3149 if ((sc->dc_flags & DC_TX_STORENFWD) == 0) { 3150 if (sc->dc_txthresh + DC_TXTHRESH_INC > DC_TXTHRESH_MAX) { 3151 printf("using store and forward mode\n"); 3152 netcfg |= DC_NETCFG_STORENFWD; 3153 } else { 3154 printf("increasing TX threshold\n"); 3155 sc->dc_txthresh += DC_TXTHRESH_INC; 3156 netcfg &= ~DC_NETCFG_TX_THRESH; 3157 netcfg |= sc->dc_txthresh; 3158 } 3159 3160 if (DC_IS_INTEL(sc)) { 3161 /* 3162 * The real 21143 requires that the transmitter be idle 3163 * in order to change the transmit threshold or store 3164 * and forward state. 3165 */ 3166 CSR_WRITE_4(sc, DC_NETCFG, netcfg & ~DC_NETCFG_TX_ON); 3167 3168 for (i = 0; i < DC_TIMEOUT; i++) { 3169 isr = CSR_READ_4(sc, DC_ISR); 3170 if (isr & DC_ISR_TX_IDLE) 3171 break; 3172 DELAY(10); 3173 } 3174 if (i == DC_TIMEOUT) { 3175 device_printf(sc->dc_dev, 3176 "%s: failed to force tx to idle state\n", 3177 __func__); 3178 reinit++; 3179 } 3180 } 3181 } else { 3182 printf("resetting\n"); 3183 reinit++; 3184 } 3185 3186 if (reinit == 0) { 3187 CSR_WRITE_4(sc, DC_NETCFG, netcfg); 3188 if (DC_IS_INTEL(sc)) 3189 CSR_WRITE_4(sc, DC_NETCFG, netcfg | DC_NETCFG_TX_ON); 3190 } else { 3191 sc->dc_ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 3192 dc_init_locked(sc); 3193 } 3194 } 3195 3196 #ifdef DEVICE_POLLING 3197 static poll_handler_t dc_poll; 3198 3199 static int 3200 dc_poll(struct ifnet *ifp, enum poll_cmd cmd, int count) 3201 { 3202 struct dc_softc *sc = ifp->if_softc; 3203 int rx_npkts = 0; 3204 3205 DC_LOCK(sc); 3206 3207 if (!(ifp->if_drv_flags & IFF_DRV_RUNNING)) { 3208 DC_UNLOCK(sc); 3209 return (rx_npkts); 3210 } 3211 3212 sc->rxcycles = count; 3213 rx_npkts = dc_rxeof(sc); 3214 dc_txeof(sc); 3215 if (!IFQ_IS_EMPTY(&ifp->if_snd) && 3216 !(ifp->if_drv_flags & IFF_DRV_OACTIVE)) 3217 dc_start_locked(ifp); 3218 3219 if (cmd == POLL_AND_CHECK_STATUS) { /* also check status register */ 3220 uint32_t status; 3221 3222 status = CSR_READ_4(sc, DC_ISR); 3223 status &= (DC_ISR_RX_WATDOGTIMEO | DC_ISR_RX_NOBUF | 3224 DC_ISR_TX_NOBUF | DC_ISR_TX_IDLE | DC_ISR_TX_UNDERRUN | 3225 DC_ISR_BUS_ERR); 3226 if (!status) { 3227 DC_UNLOCK(sc); 3228 return (rx_npkts); 3229 } 3230 /* ack what we have */ 3231 CSR_WRITE_4(sc, DC_ISR, status); 3232 3233 if (status & (DC_ISR_RX_WATDOGTIMEO | DC_ISR_RX_NOBUF)) { 3234 uint32_t r = CSR_READ_4(sc, DC_FRAMESDISCARDED); 3235 ifp->if_ierrors += (r & 0xffff) + ((r >> 17) & 0x7ff); 3236 3237 if (dc_rx_resync(sc)) 3238 dc_rxeof(sc); 3239 } 3240 /* restart transmit unit if necessary */ 3241 if (status & DC_ISR_TX_IDLE && sc->dc_cdata.dc_tx_cnt) 3242 CSR_WRITE_4(sc, DC_TXSTART, 0xFFFFFFFF); 3243 3244 if (status & DC_ISR_TX_UNDERRUN) 3245 dc_tx_underrun(sc); 3246 3247 if (status & DC_ISR_BUS_ERR) { 3248 if_printf(ifp, "%s: bus error\n", __func__); 3249 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 3250 dc_init_locked(sc); 3251 } 3252 } 3253 DC_UNLOCK(sc); 3254 return (rx_npkts); 3255 } 3256 #endif /* DEVICE_POLLING */ 3257 3258 static void 3259 dc_intr(void *arg) 3260 { 3261 struct dc_softc *sc; 3262 struct ifnet *ifp; 3263 uint32_t r, status; 3264 int n; 3265 3266 sc = arg; 3267 3268 if (sc->suspended) 3269 return; 3270 3271 DC_LOCK(sc); 3272 status = CSR_READ_4(sc, DC_ISR); 3273 if (status == 0xFFFFFFFF || (status & DC_INTRS) == 0) { 3274 DC_UNLOCK(sc); 3275 return; 3276 } 3277 ifp = sc->dc_ifp; 3278 #ifdef DEVICE_POLLING 3279 if (ifp->if_capenable & IFCAP_POLLING) { 3280 DC_UNLOCK(sc); 3281 return; 3282 } 3283 #endif 3284 /* Disable interrupts. */ 3285 CSR_WRITE_4(sc, DC_IMR, 0x00000000); 3286 3287 for (n = 16; n > 0; n--) { 3288 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) 3289 break; 3290 /* Ack interrupts. */ 3291 CSR_WRITE_4(sc, DC_ISR, status); 3292 3293 if (status & DC_ISR_RX_OK) { 3294 if (dc_rxeof(sc) == 0) { 3295 while (dc_rx_resync(sc)) 3296 dc_rxeof(sc); 3297 } 3298 } 3299 3300 if (status & (DC_ISR_TX_OK | DC_ISR_TX_NOBUF)) 3301 dc_txeof(sc); 3302 3303 if (status & DC_ISR_TX_IDLE) { 3304 dc_txeof(sc); 3305 if (sc->dc_cdata.dc_tx_cnt) { 3306 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_TX_ON); 3307 CSR_WRITE_4(sc, DC_TXSTART, 0xFFFFFFFF); 3308 } 3309 } 3310 3311 if (status & DC_ISR_TX_UNDERRUN) 3312 dc_tx_underrun(sc); 3313 3314 if ((status & DC_ISR_RX_WATDOGTIMEO) 3315 || (status & DC_ISR_RX_NOBUF)) { 3316 r = CSR_READ_4(sc, DC_FRAMESDISCARDED); 3317 ifp->if_ierrors += (r & 0xffff) + ((r >> 17) & 0x7ff); 3318 if (dc_rxeof(sc) == 0) { 3319 while (dc_rx_resync(sc)) 3320 dc_rxeof(sc); 3321 } 3322 } 3323 3324 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 3325 dc_start_locked(ifp); 3326 3327 if (status & DC_ISR_BUS_ERR) { 3328 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 3329 dc_init_locked(sc); 3330 DC_UNLOCK(sc); 3331 return; 3332 } 3333 status = CSR_READ_4(sc, DC_ISR); 3334 if (status == 0xFFFFFFFF || (status & DC_INTRS) == 0) 3335 break; 3336 } 3337 3338 /* Re-enable interrupts. */ 3339 if (ifp->if_drv_flags & IFF_DRV_RUNNING) 3340 CSR_WRITE_4(sc, DC_IMR, DC_INTRS); 3341 3342 DC_UNLOCK(sc); 3343 } 3344 3345 /* 3346 * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data 3347 * pointers to the fragment pointers. 3348 */ 3349 static int 3350 dc_encap(struct dc_softc *sc, struct mbuf **m_head) 3351 { 3352 bus_dma_segment_t segs[DC_MAXFRAGS]; 3353 bus_dmamap_t map; 3354 struct dc_desc *f; 3355 struct mbuf *m; 3356 int cur, defragged, error, first, frag, i, idx, nseg; 3357 3358 m = NULL; 3359 defragged = 0; 3360 if (sc->dc_flags & DC_TX_COALESCE && 3361 ((*m_head)->m_next != NULL || sc->dc_flags & DC_TX_ALIGN)) { 3362 m = m_defrag(*m_head, M_DONTWAIT); 3363 defragged = 1; 3364 } else { 3365 /* 3366 * Count the number of frags in this chain to see if we 3367 * need to m_collapse. Since the descriptor list is shared 3368 * by all packets, we'll m_collapse long chains so that they 3369 * do not use up the entire list, even if they would fit. 3370 */ 3371 i = 0; 3372 for (m = *m_head; m != NULL; m = m->m_next) 3373 i++; 3374 if (i > DC_TX_LIST_CNT / 4 || 3375 DC_TX_LIST_CNT - i + sc->dc_cdata.dc_tx_cnt <= 3376 DC_TX_LIST_RSVD) { 3377 m = m_collapse(*m_head, M_DONTWAIT, DC_MAXFRAGS); 3378 defragged = 1; 3379 } 3380 } 3381 if (defragged != 0) { 3382 if (m == NULL) { 3383 m_freem(*m_head); 3384 *m_head = NULL; 3385 return (ENOBUFS); 3386 } 3387 *m_head = m; 3388 } 3389 3390 idx = sc->dc_cdata.dc_tx_prod; 3391 error = bus_dmamap_load_mbuf_sg(sc->dc_tx_mtag, 3392 sc->dc_cdata.dc_tx_map[idx], *m_head, segs, &nseg, 0); 3393 if (error == EFBIG) { 3394 if (defragged != 0 || (m = m_collapse(*m_head, M_DONTWAIT, 3395 DC_MAXFRAGS)) == NULL) { 3396 m_freem(*m_head); 3397 *m_head = NULL; 3398 return (defragged != 0 ? error : ENOBUFS); 3399 } 3400 *m_head = m; 3401 error = bus_dmamap_load_mbuf_sg(sc->dc_tx_mtag, 3402 sc->dc_cdata.dc_tx_map[idx], *m_head, segs, &nseg, 0); 3403 if (error != 0) { 3404 m_freem(*m_head); 3405 *m_head = NULL; 3406 return (error); 3407 } 3408 } else if (error != 0) 3409 return (error); 3410 KASSERT(nseg <= DC_MAXFRAGS, 3411 ("%s: wrong number of segments (%d)", __func__, nseg)); 3412 if (nseg == 0) { 3413 m_freem(*m_head); 3414 *m_head = NULL; 3415 return (EIO); 3416 } 3417 3418 /* Check descriptor overruns. */ 3419 if (sc->dc_cdata.dc_tx_cnt + nseg > DC_TX_LIST_CNT - DC_TX_LIST_RSVD) { 3420 bus_dmamap_unload(sc->dc_tx_mtag, sc->dc_cdata.dc_tx_map[idx]); 3421 return (ENOBUFS); 3422 } 3423 bus_dmamap_sync(sc->dc_tx_mtag, sc->dc_cdata.dc_tx_map[idx], 3424 BUS_DMASYNC_PREWRITE); 3425 3426 first = cur = frag = sc->dc_cdata.dc_tx_prod; 3427 for (i = 0; i < nseg; i++) { 3428 if ((sc->dc_flags & DC_TX_ADMTEK_WAR) && 3429 (frag == (DC_TX_LIST_CNT - 1)) && 3430 (first != sc->dc_cdata.dc_tx_first)) { 3431 bus_dmamap_unload(sc->dc_tx_mtag, 3432 sc->dc_cdata.dc_tx_map[first]); 3433 m_freem(*m_head); 3434 *m_head = NULL; 3435 return (ENOBUFS); 3436 } 3437 3438 f = &sc->dc_ldata.dc_tx_list[frag]; 3439 f->dc_ctl = htole32(DC_TXCTL_TLINK | segs[i].ds_len); 3440 if (i == 0) { 3441 f->dc_status = 0; 3442 f->dc_ctl |= htole32(DC_TXCTL_FIRSTFRAG); 3443 } else 3444 f->dc_status = htole32(DC_TXSTAT_OWN); 3445 f->dc_data = htole32(DC_ADDR_LO(segs[i].ds_addr)); 3446 cur = frag; 3447 DC_INC(frag, DC_TX_LIST_CNT); 3448 } 3449 3450 sc->dc_cdata.dc_tx_prod = frag; 3451 sc->dc_cdata.dc_tx_cnt += nseg; 3452 sc->dc_cdata.dc_tx_chain[cur] = *m_head; 3453 sc->dc_ldata.dc_tx_list[cur].dc_ctl |= htole32(DC_TXCTL_LASTFRAG); 3454 if (sc->dc_flags & DC_TX_INTR_FIRSTFRAG) 3455 sc->dc_ldata.dc_tx_list[first].dc_ctl |= 3456 htole32(DC_TXCTL_FINT); 3457 if (sc->dc_flags & DC_TX_INTR_ALWAYS) 3458 sc->dc_ldata.dc_tx_list[cur].dc_ctl |= htole32(DC_TXCTL_FINT); 3459 if (sc->dc_flags & DC_TX_USE_TX_INTR && 3460 ++sc->dc_cdata.dc_tx_pkts >= 8) { 3461 sc->dc_cdata.dc_tx_pkts = 0; 3462 sc->dc_ldata.dc_tx_list[cur].dc_ctl |= htole32(DC_TXCTL_FINT); 3463 } 3464 sc->dc_ldata.dc_tx_list[first].dc_status = htole32(DC_TXSTAT_OWN); 3465 3466 bus_dmamap_sync(sc->dc_tx_ltag, sc->dc_tx_lmap, 3467 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 3468 3469 /* 3470 * Swap the last and the first dmamaps to ensure the map for 3471 * this transmission is placed at the last descriptor. 3472 */ 3473 map = sc->dc_cdata.dc_tx_map[cur]; 3474 sc->dc_cdata.dc_tx_map[cur] = sc->dc_cdata.dc_tx_map[first]; 3475 sc->dc_cdata.dc_tx_map[first] = map; 3476 3477 return (0); 3478 } 3479 3480 static void 3481 dc_start(struct ifnet *ifp) 3482 { 3483 struct dc_softc *sc; 3484 3485 sc = ifp->if_softc; 3486 DC_LOCK(sc); 3487 dc_start_locked(ifp); 3488 DC_UNLOCK(sc); 3489 } 3490 3491 /* 3492 * Main transmit routine 3493 * To avoid having to do mbuf copies, we put pointers to the mbuf data 3494 * regions directly in the transmit lists. We also save a copy of the 3495 * pointers since the transmit list fragment pointers are physical 3496 * addresses. 3497 */ 3498 static void 3499 dc_start_locked(struct ifnet *ifp) 3500 { 3501 struct dc_softc *sc; 3502 struct mbuf *m_head; 3503 int queued; 3504 3505 sc = ifp->if_softc; 3506 3507 DC_LOCK_ASSERT(sc); 3508 3509 if ((ifp->if_drv_flags & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) != 3510 IFF_DRV_RUNNING || sc->dc_link == 0) 3511 return; 3512 3513 sc->dc_cdata.dc_tx_first = sc->dc_cdata.dc_tx_prod; 3514 3515 for (queued = 0; !IFQ_DRV_IS_EMPTY(&ifp->if_snd); ) { 3516 /* 3517 * If there's no way we can send any packets, return now. 3518 */ 3519 if (sc->dc_cdata.dc_tx_cnt > DC_TX_LIST_CNT - DC_TX_LIST_RSVD) { 3520 ifp->if_drv_flags |= IFF_DRV_OACTIVE; 3521 break; 3522 } 3523 IFQ_DRV_DEQUEUE(&ifp->if_snd, m_head); 3524 if (m_head == NULL) 3525 break; 3526 3527 if (dc_encap(sc, &m_head)) { 3528 if (m_head == NULL) 3529 break; 3530 IFQ_DRV_PREPEND(&ifp->if_snd, m_head); 3531 ifp->if_drv_flags |= IFF_DRV_OACTIVE; 3532 break; 3533 } 3534 3535 queued++; 3536 /* 3537 * If there's a BPF listener, bounce a copy of this frame 3538 * to him. 3539 */ 3540 BPF_MTAP(ifp, m_head); 3541 } 3542 3543 if (queued > 0) { 3544 /* Transmit */ 3545 if (!(sc->dc_flags & DC_TX_POLL)) 3546 CSR_WRITE_4(sc, DC_TXSTART, 0xFFFFFFFF); 3547 3548 /* 3549 * Set a timeout in case the chip goes out to lunch. 3550 */ 3551 sc->dc_wdog_timer = 5; 3552 } 3553 } 3554 3555 static void 3556 dc_init(void *xsc) 3557 { 3558 struct dc_softc *sc = xsc; 3559 3560 DC_LOCK(sc); 3561 dc_init_locked(sc); 3562 DC_UNLOCK(sc); 3563 } 3564 3565 static void 3566 dc_init_locked(struct dc_softc *sc) 3567 { 3568 struct ifnet *ifp = sc->dc_ifp; 3569 struct mii_data *mii; 3570 struct ifmedia *ifm; 3571 3572 DC_LOCK_ASSERT(sc); 3573 3574 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) 3575 return; 3576 3577 mii = device_get_softc(sc->dc_miibus); 3578 3579 /* 3580 * Cancel pending I/O and free all RX/TX buffers. 3581 */ 3582 dc_stop(sc); 3583 dc_reset(sc); 3584 if (DC_IS_INTEL(sc)) { 3585 ifm = &mii->mii_media; 3586 dc_apply_fixup(sc, ifm->ifm_media); 3587 } 3588 3589 /* 3590 * Set cache alignment and burst length. 3591 */ 3592 if (DC_IS_ASIX(sc) || DC_IS_DAVICOM(sc)) 3593 CSR_WRITE_4(sc, DC_BUSCTL, 0); 3594 else 3595 CSR_WRITE_4(sc, DC_BUSCTL, DC_BUSCTL_MRME | DC_BUSCTL_MRLE); 3596 /* 3597 * Evenly share the bus between receive and transmit process. 3598 */ 3599 if (DC_IS_INTEL(sc)) 3600 DC_SETBIT(sc, DC_BUSCTL, DC_BUSCTL_ARBITRATION); 3601 if (DC_IS_DAVICOM(sc) || DC_IS_INTEL(sc)) { 3602 DC_SETBIT(sc, DC_BUSCTL, DC_BURSTLEN_USECA); 3603 } else { 3604 DC_SETBIT(sc, DC_BUSCTL, DC_BURSTLEN_16LONG); 3605 } 3606 if (sc->dc_flags & DC_TX_POLL) 3607 DC_SETBIT(sc, DC_BUSCTL, DC_TXPOLL_1); 3608 switch(sc->dc_cachesize) { 3609 case 32: 3610 DC_SETBIT(sc, DC_BUSCTL, DC_CACHEALIGN_32LONG); 3611 break; 3612 case 16: 3613 DC_SETBIT(sc, DC_BUSCTL, DC_CACHEALIGN_16LONG); 3614 break; 3615 case 8: 3616 DC_SETBIT(sc, DC_BUSCTL, DC_CACHEALIGN_8LONG); 3617 break; 3618 case 0: 3619 default: 3620 DC_SETBIT(sc, DC_BUSCTL, DC_CACHEALIGN_NONE); 3621 break; 3622 } 3623 3624 if (sc->dc_flags & DC_TX_STORENFWD) 3625 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_STORENFWD); 3626 else { 3627 if (sc->dc_txthresh > DC_TXTHRESH_MAX) { 3628 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_STORENFWD); 3629 } else { 3630 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_STORENFWD); 3631 DC_SETBIT(sc, DC_NETCFG, sc->dc_txthresh); 3632 } 3633 } 3634 3635 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_NO_RXCRC); 3636 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_TX_BACKOFF); 3637 3638 if (DC_IS_MACRONIX(sc) || DC_IS_PNICII(sc)) { 3639 /* 3640 * The app notes for the 98713 and 98715A say that 3641 * in order to have the chips operate properly, a magic 3642 * number must be written to CSR16. Macronix does not 3643 * document the meaning of these bits so there's no way 3644 * to know exactly what they do. The 98713 has a magic 3645 * number all its own; the rest all use a different one. 3646 */ 3647 DC_CLRBIT(sc, DC_MX_MAGICPACKET, 0xFFFF0000); 3648 if (sc->dc_type == DC_TYPE_98713) 3649 DC_SETBIT(sc, DC_MX_MAGICPACKET, DC_MX_MAGIC_98713); 3650 else 3651 DC_SETBIT(sc, DC_MX_MAGICPACKET, DC_MX_MAGIC_98715); 3652 } 3653 3654 if (DC_IS_XIRCOM(sc)) { 3655 /* 3656 * setup General Purpose Port mode and data so the tulip 3657 * can talk to the MII. 3658 */ 3659 CSR_WRITE_4(sc, DC_SIAGP, DC_SIAGP_WRITE_EN | DC_SIAGP_INT1_EN | 3660 DC_SIAGP_MD_GP2_OUTPUT | DC_SIAGP_MD_GP0_OUTPUT); 3661 DELAY(10); 3662 CSR_WRITE_4(sc, DC_SIAGP, DC_SIAGP_INT1_EN | 3663 DC_SIAGP_MD_GP2_OUTPUT | DC_SIAGP_MD_GP0_OUTPUT); 3664 DELAY(10); 3665 } 3666 3667 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_TX_THRESH); 3668 DC_SETBIT(sc, DC_NETCFG, DC_TXTHRESH_MIN); 3669 3670 /* Init circular RX list. */ 3671 if (dc_list_rx_init(sc) == ENOBUFS) { 3672 device_printf(sc->dc_dev, 3673 "initialization failed: no memory for rx buffers\n"); 3674 dc_stop(sc); 3675 return; 3676 } 3677 3678 /* 3679 * Init TX descriptors. 3680 */ 3681 dc_list_tx_init(sc); 3682 3683 /* 3684 * Load the address of the RX list. 3685 */ 3686 CSR_WRITE_4(sc, DC_RXADDR, DC_RXDESC(sc, 0)); 3687 CSR_WRITE_4(sc, DC_TXADDR, DC_TXDESC(sc, 0)); 3688 3689 /* 3690 * Enable interrupts. 3691 */ 3692 #ifdef DEVICE_POLLING 3693 /* 3694 * ... but only if we are not polling, and make sure they are off in 3695 * the case of polling. Some cards (e.g. fxp) turn interrupts on 3696 * after a reset. 3697 */ 3698 if (ifp->if_capenable & IFCAP_POLLING) 3699 CSR_WRITE_4(sc, DC_IMR, 0x00000000); 3700 else 3701 #endif 3702 CSR_WRITE_4(sc, DC_IMR, DC_INTRS); 3703 CSR_WRITE_4(sc, DC_ISR, 0xFFFFFFFF); 3704 3705 /* Enable transmitter. */ 3706 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_TX_ON); 3707 3708 /* 3709 * If this is an Intel 21143 and we're not using the 3710 * MII port, program the LED control pins so we get 3711 * link and activity indications. 3712 */ 3713 if (sc->dc_flags & DC_TULIP_LEDS) { 3714 CSR_WRITE_4(sc, DC_WATCHDOG, 3715 DC_WDOG_CTLWREN | DC_WDOG_LINK | DC_WDOG_ACTIVITY); 3716 CSR_WRITE_4(sc, DC_WATCHDOG, 0); 3717 } 3718 3719 /* 3720 * Load the RX/multicast filter. We do this sort of late 3721 * because the filter programming scheme on the 21143 and 3722 * some clones requires DMAing a setup frame via the TX 3723 * engine, and we need the transmitter enabled for that. 3724 */ 3725 dc_setfilt(sc); 3726 3727 /* Enable receiver. */ 3728 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_ON); 3729 CSR_WRITE_4(sc, DC_RXSTART, 0xFFFFFFFF); 3730 3731 ifp->if_drv_flags |= IFF_DRV_RUNNING; 3732 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 3733 3734 mii_mediachg(mii); 3735 dc_setcfg(sc, sc->dc_if_media); 3736 3737 /* Clear missed frames and overflow counter. */ 3738 CSR_READ_4(sc, DC_FRAMESDISCARDED); 3739 3740 /* Don't start the ticker if this is a homePNA link. */ 3741 if (IFM_SUBTYPE(mii->mii_media.ifm_media) == IFM_HPNA_1) 3742 sc->dc_link = 1; 3743 else { 3744 if (sc->dc_flags & DC_21143_NWAY) 3745 callout_reset(&sc->dc_stat_ch, hz/10, dc_tick, sc); 3746 else 3747 callout_reset(&sc->dc_stat_ch, hz, dc_tick, sc); 3748 } 3749 3750 sc->dc_wdog_timer = 0; 3751 callout_reset(&sc->dc_wdog_ch, hz, dc_watchdog, sc); 3752 } 3753 3754 /* 3755 * Set media options. 3756 */ 3757 static int 3758 dc_ifmedia_upd(struct ifnet *ifp) 3759 { 3760 struct dc_softc *sc; 3761 struct mii_data *mii; 3762 struct ifmedia *ifm; 3763 3764 sc = ifp->if_softc; 3765 mii = device_get_softc(sc->dc_miibus); 3766 DC_LOCK(sc); 3767 mii_mediachg(mii); 3768 ifm = &mii->mii_media; 3769 3770 if (DC_IS_INTEL(sc)) 3771 dc_setcfg(sc, ifm->ifm_media); 3772 else if (DC_IS_DAVICOM(sc) && 3773 IFM_SUBTYPE(ifm->ifm_media) == IFM_HPNA_1) 3774 dc_setcfg(sc, ifm->ifm_media); 3775 else 3776 sc->dc_link = 0; 3777 DC_UNLOCK(sc); 3778 3779 return (0); 3780 } 3781 3782 /* 3783 * Report current media status. 3784 */ 3785 static void 3786 dc_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 3787 { 3788 struct dc_softc *sc; 3789 struct mii_data *mii; 3790 struct ifmedia *ifm; 3791 3792 sc = ifp->if_softc; 3793 mii = device_get_softc(sc->dc_miibus); 3794 DC_LOCK(sc); 3795 mii_pollstat(mii); 3796 ifm = &mii->mii_media; 3797 if (DC_IS_DAVICOM(sc)) { 3798 if (IFM_SUBTYPE(ifm->ifm_media) == IFM_HPNA_1) { 3799 ifmr->ifm_active = ifm->ifm_media; 3800 ifmr->ifm_status = 0; 3801 DC_UNLOCK(sc); 3802 return; 3803 } 3804 } 3805 ifmr->ifm_active = mii->mii_media_active; 3806 ifmr->ifm_status = mii->mii_media_status; 3807 DC_UNLOCK(sc); 3808 } 3809 3810 static int 3811 dc_ioctl(struct ifnet *ifp, u_long command, caddr_t data) 3812 { 3813 struct dc_softc *sc = ifp->if_softc; 3814 struct ifreq *ifr = (struct ifreq *)data; 3815 struct mii_data *mii; 3816 int error = 0; 3817 3818 switch (command) { 3819 case SIOCSIFFLAGS: 3820 DC_LOCK(sc); 3821 if (ifp->if_flags & IFF_UP) { 3822 int need_setfilt = (ifp->if_flags ^ sc->dc_if_flags) & 3823 (IFF_PROMISC | IFF_ALLMULTI); 3824 3825 if (ifp->if_drv_flags & IFF_DRV_RUNNING) { 3826 if (need_setfilt) 3827 dc_setfilt(sc); 3828 } else { 3829 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 3830 dc_init_locked(sc); 3831 } 3832 } else { 3833 if (ifp->if_drv_flags & IFF_DRV_RUNNING) 3834 dc_stop(sc); 3835 } 3836 sc->dc_if_flags = ifp->if_flags; 3837 DC_UNLOCK(sc); 3838 break; 3839 case SIOCADDMULTI: 3840 case SIOCDELMULTI: 3841 DC_LOCK(sc); 3842 if (ifp->if_drv_flags & IFF_DRV_RUNNING) 3843 dc_setfilt(sc); 3844 DC_UNLOCK(sc); 3845 break; 3846 case SIOCGIFMEDIA: 3847 case SIOCSIFMEDIA: 3848 mii = device_get_softc(sc->dc_miibus); 3849 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 3850 break; 3851 case SIOCSIFCAP: 3852 #ifdef DEVICE_POLLING 3853 if (ifr->ifr_reqcap & IFCAP_POLLING && 3854 !(ifp->if_capenable & IFCAP_POLLING)) { 3855 error = ether_poll_register(dc_poll, ifp); 3856 if (error) 3857 return(error); 3858 DC_LOCK(sc); 3859 /* Disable interrupts */ 3860 CSR_WRITE_4(sc, DC_IMR, 0x00000000); 3861 ifp->if_capenable |= IFCAP_POLLING; 3862 DC_UNLOCK(sc); 3863 return (error); 3864 } 3865 if (!(ifr->ifr_reqcap & IFCAP_POLLING) && 3866 ifp->if_capenable & IFCAP_POLLING) { 3867 error = ether_poll_deregister(ifp); 3868 /* Enable interrupts. */ 3869 DC_LOCK(sc); 3870 CSR_WRITE_4(sc, DC_IMR, DC_INTRS); 3871 ifp->if_capenable &= ~IFCAP_POLLING; 3872 DC_UNLOCK(sc); 3873 return (error); 3874 } 3875 #endif /* DEVICE_POLLING */ 3876 break; 3877 default: 3878 error = ether_ioctl(ifp, command, data); 3879 break; 3880 } 3881 3882 return (error); 3883 } 3884 3885 static void 3886 dc_watchdog(void *xsc) 3887 { 3888 struct dc_softc *sc = xsc; 3889 struct ifnet *ifp; 3890 3891 DC_LOCK_ASSERT(sc); 3892 3893 if (sc->dc_wdog_timer == 0 || --sc->dc_wdog_timer != 0) { 3894 callout_reset(&sc->dc_wdog_ch, hz, dc_watchdog, sc); 3895 return; 3896 } 3897 3898 ifp = sc->dc_ifp; 3899 ifp->if_oerrors++; 3900 device_printf(sc->dc_dev, "watchdog timeout\n"); 3901 3902 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 3903 dc_init_locked(sc); 3904 3905 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 3906 dc_start_locked(ifp); 3907 } 3908 3909 /* 3910 * Stop the adapter and free any mbufs allocated to the 3911 * RX and TX lists. 3912 */ 3913 static void 3914 dc_stop(struct dc_softc *sc) 3915 { 3916 struct ifnet *ifp; 3917 struct dc_list_data *ld; 3918 struct dc_chain_data *cd; 3919 int i; 3920 uint32_t ctl; 3921 3922 DC_LOCK_ASSERT(sc); 3923 3924 ifp = sc->dc_ifp; 3925 ld = &sc->dc_ldata; 3926 cd = &sc->dc_cdata; 3927 3928 callout_stop(&sc->dc_stat_ch); 3929 callout_stop(&sc->dc_wdog_ch); 3930 sc->dc_wdog_timer = 0; 3931 3932 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE); 3933 3934 DC_CLRBIT(sc, DC_NETCFG, (DC_NETCFG_RX_ON | DC_NETCFG_TX_ON)); 3935 CSR_WRITE_4(sc, DC_IMR, 0x00000000); 3936 CSR_WRITE_4(sc, DC_TXADDR, 0x00000000); 3937 CSR_WRITE_4(sc, DC_RXADDR, 0x00000000); 3938 sc->dc_link = 0; 3939 3940 /* 3941 * Free data in the RX lists. 3942 */ 3943 for (i = 0; i < DC_RX_LIST_CNT; i++) { 3944 if (cd->dc_rx_chain[i] != NULL) { 3945 bus_dmamap_sync(sc->dc_rx_mtag, 3946 cd->dc_rx_map[i], BUS_DMASYNC_POSTREAD); 3947 bus_dmamap_unload(sc->dc_rx_mtag, 3948 cd->dc_rx_map[i]); 3949 m_freem(cd->dc_rx_chain[i]); 3950 cd->dc_rx_chain[i] = NULL; 3951 } 3952 } 3953 bzero(ld->dc_rx_list, DC_RX_LIST_SZ); 3954 bus_dmamap_sync(sc->dc_rx_ltag, sc->dc_rx_lmap, 3955 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 3956 3957 /* 3958 * Free the TX list buffers. 3959 */ 3960 for (i = 0; i < DC_TX_LIST_CNT; i++) { 3961 if (cd->dc_tx_chain[i] != NULL) { 3962 ctl = le32toh(ld->dc_tx_list[i].dc_ctl); 3963 if (ctl & DC_TXCTL_SETUP) { 3964 bus_dmamap_sync(sc->dc_stag, sc->dc_smap, 3965 BUS_DMASYNC_POSTWRITE); 3966 } else { 3967 bus_dmamap_sync(sc->dc_tx_mtag, 3968 cd->dc_tx_map[i], BUS_DMASYNC_POSTWRITE); 3969 bus_dmamap_unload(sc->dc_tx_mtag, 3970 cd->dc_tx_map[i]); 3971 m_freem(cd->dc_tx_chain[i]); 3972 } 3973 cd->dc_tx_chain[i] = NULL; 3974 } 3975 } 3976 bzero(ld->dc_tx_list, DC_TX_LIST_SZ); 3977 bus_dmamap_sync(sc->dc_tx_ltag, sc->dc_tx_lmap, 3978 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 3979 } 3980 3981 /* 3982 * Device suspend routine. Stop the interface and save some PCI 3983 * settings in case the BIOS doesn't restore them properly on 3984 * resume. 3985 */ 3986 static int 3987 dc_suspend(device_t dev) 3988 { 3989 struct dc_softc *sc; 3990 3991 sc = device_get_softc(dev); 3992 DC_LOCK(sc); 3993 dc_stop(sc); 3994 sc->suspended = 1; 3995 DC_UNLOCK(sc); 3996 3997 return (0); 3998 } 3999 4000 /* 4001 * Device resume routine. Restore some PCI settings in case the BIOS 4002 * doesn't, re-enable busmastering, and restart the interface if 4003 * appropriate. 4004 */ 4005 static int 4006 dc_resume(device_t dev) 4007 { 4008 struct dc_softc *sc; 4009 struct ifnet *ifp; 4010 4011 sc = device_get_softc(dev); 4012 ifp = sc->dc_ifp; 4013 4014 /* reinitialize interface if necessary */ 4015 DC_LOCK(sc); 4016 if (ifp->if_flags & IFF_UP) 4017 dc_init_locked(sc); 4018 4019 sc->suspended = 0; 4020 DC_UNLOCK(sc); 4021 4022 return (0); 4023 } 4024 4025 /* 4026 * Stop all chip I/O so that the kernel's probe routines don't 4027 * get confused by errant DMAs when rebooting. 4028 */ 4029 static int 4030 dc_shutdown(device_t dev) 4031 { 4032 struct dc_softc *sc; 4033 4034 sc = device_get_softc(dev); 4035 4036 DC_LOCK(sc); 4037 dc_stop(sc); 4038 DC_UNLOCK(sc); 4039 4040 return (0); 4041 } 4042 4043 static int 4044 dc_check_multiport(struct dc_softc *sc) 4045 { 4046 struct dc_softc *dsc; 4047 devclass_t dc; 4048 device_t child; 4049 uint8_t *eaddr; 4050 int unit; 4051 4052 dc = devclass_find("dc"); 4053 for (unit = 0; unit < devclass_get_maxunit(dc); unit++) { 4054 child = devclass_get_device(dc, unit); 4055 if (child == NULL) 4056 continue; 4057 if (child == sc->dc_dev) 4058 continue; 4059 if (device_get_parent(child) != device_get_parent(sc->dc_dev)) 4060 continue; 4061 if (unit > device_get_unit(sc->dc_dev)) 4062 continue; 4063 if (device_is_attached(child) == 0) 4064 continue; 4065 dsc = device_get_softc(child); 4066 device_printf(sc->dc_dev, 4067 "Using station address of %s as base\n", 4068 device_get_nameunit(child)); 4069 bcopy(dsc->dc_eaddr, sc->dc_eaddr, ETHER_ADDR_LEN); 4070 eaddr = (uint8_t *)sc->dc_eaddr; 4071 eaddr[5]++; 4072 /* Prepare SROM to parse again. */ 4073 if (DC_IS_INTEL(sc) && dsc->dc_srom != NULL && 4074 sc->dc_romwidth != 0) { 4075 free(sc->dc_srom, M_DEVBUF); 4076 sc->dc_romwidth = dsc->dc_romwidth; 4077 sc->dc_srom = malloc(DC_ROM_SIZE(sc->dc_romwidth), 4078 M_DEVBUF, M_NOWAIT); 4079 if (sc->dc_srom == NULL) { 4080 device_printf(sc->dc_dev, 4081 "Could not allocate SROM buffer\n"); 4082 return (ENOMEM); 4083 } 4084 bcopy(dsc->dc_srom, sc->dc_srom, 4085 DC_ROM_SIZE(sc->dc_romwidth)); 4086 } 4087 return (0); 4088 } 4089 return (ENOENT); 4090 } 4091