1 /* 2 * Copyright (c) 1997, 1998, 1999 3 * Bill Paul <wpaul@ee.columbia.edu>. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 3. All advertising materials mentioning features or use of this software 14 * must display the following acknowledgement: 15 * This product includes software developed by Bill Paul. 16 * 4. Neither the name of the author nor the names of any co-contributors 17 * may be used to endorse or promote products derived from this software 18 * without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30 * THE POSSIBILITY OF SUCH DAMAGE. 31 * 32 * $FreeBSD$ 33 */ 34 35 /* 36 * DEC "tulip" clone ethernet driver. Supports the DEC/Intel 21143 37 * series chips and several workalikes including the following: 38 * 39 * Macronix 98713/98715/98725 PMAC (www.macronix.com) 40 * Macronix/Lite-On 82c115 PNIC II (www.macronix.com) 41 * Lite-On 82c168/82c169 PNIC (www.litecom.com) 42 * ASIX Electronics AX88140A (www.asix.com.tw) 43 * ASIX Electronics AX88141 (www.asix.com.tw) 44 * ADMtek AL981 (www.admtek.com.tw) 45 * ADMtek AN985 (www.admtek.com.tw) 46 * Davicom DM9100, DM9102, DM9102A (www.davicom8.com) 47 * Accton EN1217 (www.accton.com) 48 * 49 * Datasheets for the 21143 are available at developer.intel.com. 50 * Datasheets for the clone parts can be found at their respective sites. 51 * (Except for the PNIC; see www.freebsd.org/~wpaul/PNIC/pnic.ps.gz.) 52 * The PNIC II is essentially a Macronix 98715A chip; the only difference 53 * worth noting is that its multicast hash table is only 128 bits wide 54 * instead of 512. 55 * 56 * Written by Bill Paul <wpaul@ee.columbia.edu> 57 * Electrical Engineering Department 58 * Columbia University, New York City 59 */ 60 61 /* 62 * The Intel 21143 is the successor to the DEC 21140. It is basically 63 * the same as the 21140 but with a few new features. The 21143 supports 64 * three kinds of media attachments: 65 * 66 * o MII port, for 10Mbps and 100Mbps support and NWAY 67 * autonegotiation provided by an external PHY. 68 * o SYM port, for symbol mode 100Mbps support. 69 * o 10baseT port. 70 * o AUI/BNC port. 71 * 72 * The 100Mbps SYM port and 10baseT port can be used together in 73 * combination with the internal NWAY support to create a 10/100 74 * autosensing configuration. 75 * 76 * Knowing which media is available on a given card is tough: you're 77 * supposed to go slogging through the EEPROM looking for media 78 * description structures. Unfortunately, some card vendors that use 79 * the 21143 don't obey the DEC SROM spec correctly, which means that 80 * what you find in the EEPROM may not agree with reality. Fortunately, 81 * the 21143 provides us a way to get around this issue: lurking in 82 * PCI configuration space is the Configuration Wake-Up Command Register. 83 * This register is loaded with a value from the EEPROM when wake on LAN 84 * mode is enabled; this value tells us quite clearly what kind of media 85 * is attached to the NIC. The main purpose of this register is to tell 86 * the NIC what media to scan when in wake on LAN mode, however by 87 * forcibly enabling wake on LAN mode, we can use to learn what kind of 88 * media a given NIC has available and adapt ourselves accordingly. 89 * 90 * Of course, if the media description blocks in the EEPROM are bogus. 91 * what are the odds that the CWUC aren't bogus as well, right? Well, 92 * the CWUC value is more likely to be correct since wake on LAN mode 93 * won't work correctly without it, and wake on LAN is a big selling 94 * point these days. It's also harder to screw up a single byte than 95 * a whole media descriptor block. 96 * 97 * Note that not all tulip workalikes are handled in this driver: we only 98 * deal with those which are relatively well behaved. The Winbond is 99 * handled separately due to its different register offsets and the 100 * special handling needed for its various bugs. The PNIC is handled 101 * here, but I'm not thrilled about it. 102 * 103 * All of the workalike chips use some form of MII transceiver support 104 * with the exception of the Macronix chips, which also have a SYM port. 105 * The ASIX AX88140A is also documented to have a SYM port, but all 106 * the cards I've seen use an MII transceiver, probably because the 107 * AX88140A doesn't support internal NWAY. 108 */ 109 110 #include <sys/param.h> 111 #include <sys/systm.h> 112 #include <sys/sockio.h> 113 #include <sys/mbuf.h> 114 #include <sys/malloc.h> 115 #include <sys/kernel.h> 116 #include <sys/socket.h> 117 118 #include <net/if.h> 119 #include <net/if_arp.h> 120 #include <net/ethernet.h> 121 #include <net/if_dl.h> 122 #include <net/if_media.h> 123 124 #include <net/bpf.h> 125 126 #include <vm/vm.h> /* for vtophys */ 127 #include <vm/pmap.h> /* for vtophys */ 128 #include <machine/clock.h> /* for DELAY */ 129 #include <machine/bus_pio.h> 130 #include <machine/bus_memio.h> 131 #include <machine/bus.h> 132 #include <machine/resource.h> 133 #include <sys/bus.h> 134 #include <sys/rman.h> 135 136 #include <dev/mii/mii.h> 137 #include <dev/mii/miivar.h> 138 139 #include <pci/pcireg.h> 140 #include <pci/pcivar.h> 141 142 #define DC_USEIOSPACE 143 144 #include <pci/if_dcreg.h> 145 146 MODULE_DEPEND(dc, miibus, 1, 1, 1); 147 148 /* "controller miibus0" required. See GENERIC if you get errors here. */ 149 #include "miibus_if.h" 150 151 #ifndef lint 152 static const char rcsid[] = 153 "$FreeBSD$"; 154 #endif 155 156 /* 157 * Various supported device vendors/types and their names. 158 */ 159 static struct dc_type dc_devs[] = { 160 { DC_VENDORID_DEC, DC_DEVICEID_21143, 161 "Intel 21143 10/100BaseTX" }, 162 { DC_VENDORID_DAVICOM, DC_DEVICEID_DM9100, 163 "Davicom DM9100 10/100BaseTX" }, 164 { DC_VENDORID_DAVICOM, DC_DEVICEID_DM9102, 165 "Davicom DM9102 10/100BaseTX" }, 166 { DC_VENDORID_DAVICOM, DC_DEVICEID_DM9102, 167 "Davicom DM9102A 10/100BaseTX" }, 168 { DC_VENDORID_ADMTEK, DC_DEVICEID_AL981, 169 "ADMtek AL981 10/100BaseTX" }, 170 { DC_VENDORID_ADMTEK, DC_DEVICEID_AN985, 171 "ADMtek AN985 10/100BaseTX" }, 172 { DC_VENDORID_ASIX, DC_DEVICEID_AX88140A, 173 "ASIX AX88140A 10/100BaseTX" }, 174 { DC_VENDORID_ASIX, DC_DEVICEID_AX88140A, 175 "ASIX AX88141 10/100BaseTX" }, 176 { DC_VENDORID_MX, DC_DEVICEID_98713, 177 "Macronix 98713 10/100BaseTX" }, 178 { DC_VENDORID_MX, DC_DEVICEID_98713, 179 "Macronix 98713A 10/100BaseTX" }, 180 { DC_VENDORID_CP, DC_DEVICEID_98713_CP, 181 "Compex RL100-TX 10/100BaseTX" }, 182 { DC_VENDORID_CP, DC_DEVICEID_98713_CP, 183 "Compex RL100-TX 10/100BaseTX" }, 184 { DC_VENDORID_MX, DC_DEVICEID_987x5, 185 "Macronix 98715/98715A 10/100BaseTX" }, 186 { DC_VENDORID_MX, DC_DEVICEID_987x5, 187 "Macronix 98725 10/100BaseTX" }, 188 { DC_VENDORID_LO, DC_DEVICEID_82C115, 189 "LC82C115 PNIC II 10/100BaseTX" }, 190 { DC_VENDORID_LO, DC_DEVICEID_82C168, 191 "82c168 PNIC 10/100BaseTX" }, 192 { DC_VENDORID_LO, DC_DEVICEID_82C168, 193 "82c169 PNIC 10/100BaseTX" }, 194 { DC_VENDORID_ACCTON, DC_DEVICEID_EN1217, 195 "Accton EN1217 10/100BaseTX" }, 196 { 0, 0, NULL } 197 }; 198 199 static int dc_probe __P((device_t)); 200 static int dc_attach __P((device_t)); 201 static int dc_detach __P((device_t)); 202 static void dc_acpi __P((device_t)); 203 static struct dc_type *dc_devtype __P((device_t)); 204 static int dc_newbuf __P((struct dc_softc *, int, struct mbuf *)); 205 static int dc_encap __P((struct dc_softc *, struct mbuf *, 206 u_int32_t *)); 207 static int dc_coal __P((struct dc_softc *, struct mbuf **)); 208 static void dc_pnic_rx_bug_war __P((struct dc_softc *, int)); 209 static int dc_rx_resync __P((struct dc_softc *)); 210 static void dc_rxeof __P((struct dc_softc *)); 211 static void dc_txeof __P((struct dc_softc *)); 212 static void dc_tick __P((void *)); 213 static void dc_intr __P((void *)); 214 static void dc_start __P((struct ifnet *)); 215 static int dc_ioctl __P((struct ifnet *, u_long, caddr_t)); 216 static void dc_init __P((void *)); 217 static void dc_stop __P((struct dc_softc *)); 218 static void dc_watchdog __P((struct ifnet *)); 219 static void dc_shutdown __P((device_t)); 220 static int dc_ifmedia_upd __P((struct ifnet *)); 221 static void dc_ifmedia_sts __P((struct ifnet *, struct ifmediareq *)); 222 223 static void dc_delay __P((struct dc_softc *)); 224 static void dc_eeprom_idle __P((struct dc_softc *)); 225 static void dc_eeprom_putbyte __P((struct dc_softc *, int)); 226 static void dc_eeprom_getword __P((struct dc_softc *, int, u_int16_t *)); 227 static void dc_eeprom_getword_pnic 228 __P((struct dc_softc *, int, u_int16_t *)); 229 static void dc_read_eeprom __P((struct dc_softc *, caddr_t, int, 230 int, int)); 231 232 static void dc_mii_writebit __P((struct dc_softc *, int)); 233 static int dc_mii_readbit __P((struct dc_softc *)); 234 static void dc_mii_sync __P((struct dc_softc *)); 235 static void dc_mii_send __P((struct dc_softc *, u_int32_t, int)); 236 static int dc_mii_readreg __P((struct dc_softc *, struct dc_mii_frame *)); 237 static int dc_mii_writereg __P((struct dc_softc *, struct dc_mii_frame *)); 238 static int dc_miibus_readreg __P((device_t, int, int)); 239 static int dc_miibus_writereg __P((device_t, int, int, int)); 240 static void dc_miibus_statchg __P((device_t)); 241 static void dc_miibus_mediainit __P((device_t)); 242 243 static void dc_setcfg __P((struct dc_softc *, int)); 244 static u_int32_t dc_crc_le __P((struct dc_softc *, caddr_t)); 245 static u_int32_t dc_crc_be __P((caddr_t)); 246 static void dc_setfilt_21143 __P((struct dc_softc *)); 247 static void dc_setfilt_asix __P((struct dc_softc *)); 248 static void dc_setfilt_admtek __P((struct dc_softc *)); 249 250 static void dc_setfilt __P((struct dc_softc *)); 251 252 static void dc_reset __P((struct dc_softc *)); 253 static int dc_list_rx_init __P((struct dc_softc *)); 254 static int dc_list_tx_init __P((struct dc_softc *)); 255 256 #ifdef DC_USEIOSPACE 257 #define DC_RES SYS_RES_IOPORT 258 #define DC_RID DC_PCI_CFBIO 259 #else 260 #define DC_RES SYS_RES_MEMORY 261 #define DC_RID DC_PCI_CFBMA 262 #endif 263 264 static device_method_t dc_methods[] = { 265 /* Device interface */ 266 DEVMETHOD(device_probe, dc_probe), 267 DEVMETHOD(device_attach, dc_attach), 268 DEVMETHOD(device_detach, dc_detach), 269 DEVMETHOD(device_shutdown, dc_shutdown), 270 271 /* bus interface */ 272 DEVMETHOD(bus_print_child, bus_generic_print_child), 273 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 274 275 /* MII interface */ 276 DEVMETHOD(miibus_readreg, dc_miibus_readreg), 277 DEVMETHOD(miibus_writereg, dc_miibus_writereg), 278 DEVMETHOD(miibus_statchg, dc_miibus_statchg), 279 DEVMETHOD(miibus_mediainit, dc_miibus_mediainit), 280 281 { 0, 0 } 282 }; 283 284 static driver_t dc_driver = { 285 "dc", 286 dc_methods, 287 sizeof(struct dc_softc) 288 }; 289 290 static devclass_t dc_devclass; 291 292 DRIVER_MODULE(if_dc, pci, dc_driver, dc_devclass, 0, 0); 293 DRIVER_MODULE(miibus, dc, miibus_driver, miibus_devclass, 0, 0); 294 295 #define DC_SETBIT(sc, reg, x) \ 296 CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) | (x)) 297 298 #define DC_CLRBIT(sc, reg, x) \ 299 CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) & ~(x)) 300 301 #define SIO_SET(x) DC_SETBIT(sc, DC_SIO, (x)) 302 #define SIO_CLR(x) DC_CLRBIT(sc, DC_SIO, (x)) 303 304 static void dc_delay(sc) 305 struct dc_softc *sc; 306 { 307 int idx; 308 309 for (idx = (300 / 33) + 1; idx > 0; idx--) 310 CSR_READ_4(sc, DC_BUSCTL); 311 } 312 313 static void dc_eeprom_idle(sc) 314 struct dc_softc *sc; 315 { 316 register int i; 317 318 CSR_WRITE_4(sc, DC_SIO, DC_SIO_EESEL); 319 dc_delay(sc); 320 DC_SETBIT(sc, DC_SIO, DC_SIO_ROMCTL_READ); 321 dc_delay(sc); 322 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); 323 dc_delay(sc); 324 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CS); 325 dc_delay(sc); 326 327 for (i = 0; i < 25; i++) { 328 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); 329 dc_delay(sc); 330 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CLK); 331 dc_delay(sc); 332 } 333 334 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); 335 dc_delay(sc); 336 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CS); 337 dc_delay(sc); 338 CSR_WRITE_4(sc, DC_SIO, 0x00000000); 339 340 return; 341 } 342 343 /* 344 * Send a read command and address to the EEPROM, check for ACK. 345 */ 346 static void dc_eeprom_putbyte(sc, addr) 347 struct dc_softc *sc; 348 int addr; 349 { 350 register int d, i; 351 352 /* 353 * The AN985 has a 93C66 EEPROM on it instead of 354 * a 93C46. It uses a different bit sequence for 355 * specifying the "read" opcode. 356 */ 357 if (DC_IS_CENTAUR(sc)) 358 d = addr | (DC_EECMD_READ << 2); 359 else 360 d = addr | DC_EECMD_READ; 361 362 /* 363 * Feed in each bit and strobe the clock. 364 */ 365 for (i = 0x400; i; i >>= 1) { 366 if (d & i) { 367 SIO_SET(DC_SIO_EE_DATAIN); 368 } else { 369 SIO_CLR(DC_SIO_EE_DATAIN); 370 } 371 dc_delay(sc); 372 SIO_SET(DC_SIO_EE_CLK); 373 dc_delay(sc); 374 SIO_CLR(DC_SIO_EE_CLK); 375 dc_delay(sc); 376 } 377 378 return; 379 } 380 381 /* 382 * Read a word of data stored in the EEPROM at address 'addr.' 383 * The PNIC 82c168/82c169 has its own non-standard way to read 384 * the EEPROM. 385 */ 386 static void dc_eeprom_getword_pnic(sc, addr, dest) 387 struct dc_softc *sc; 388 int addr; 389 u_int16_t *dest; 390 { 391 register int i; 392 u_int32_t r; 393 394 CSR_WRITE_4(sc, DC_PN_SIOCTL, DC_PN_EEOPCODE_READ|addr); 395 396 for (i = 0; i < DC_TIMEOUT; i++) { 397 DELAY(1); 398 r = CSR_READ_4(sc, DC_SIO); 399 if (!(r & DC_PN_SIOCTL_BUSY)) { 400 *dest = (u_int16_t)(r & 0xFFFF); 401 return; 402 } 403 } 404 405 return; 406 } 407 408 /* 409 * Read a word of data stored in the EEPROM at address 'addr.' 410 */ 411 static void dc_eeprom_getword(sc, addr, dest) 412 struct dc_softc *sc; 413 int addr; 414 u_int16_t *dest; 415 { 416 register int i; 417 u_int16_t word = 0; 418 419 /* Force EEPROM to idle state. */ 420 dc_eeprom_idle(sc); 421 422 /* Enter EEPROM access mode. */ 423 CSR_WRITE_4(sc, DC_SIO, DC_SIO_EESEL); 424 dc_delay(sc); 425 DC_SETBIT(sc, DC_SIO, DC_SIO_ROMCTL_READ); 426 dc_delay(sc); 427 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); 428 dc_delay(sc); 429 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CS); 430 dc_delay(sc); 431 432 /* 433 * Send address of word we want to read. 434 */ 435 dc_eeprom_putbyte(sc, addr); 436 437 /* 438 * Start reading bits from EEPROM. 439 */ 440 for (i = 0x8000; i; i >>= 1) { 441 SIO_SET(DC_SIO_EE_CLK); 442 dc_delay(sc); 443 if (CSR_READ_4(sc, DC_SIO) & DC_SIO_EE_DATAOUT) 444 word |= i; 445 dc_delay(sc); 446 SIO_CLR(DC_SIO_EE_CLK); 447 dc_delay(sc); 448 } 449 450 /* Turn off EEPROM access mode. */ 451 dc_eeprom_idle(sc); 452 453 *dest = word; 454 455 return; 456 } 457 458 /* 459 * Read a sequence of words from the EEPROM. 460 */ 461 static void dc_read_eeprom(sc, dest, off, cnt, swap) 462 struct dc_softc *sc; 463 caddr_t dest; 464 int off; 465 int cnt; 466 int swap; 467 { 468 int i; 469 u_int16_t word = 0, *ptr; 470 471 for (i = 0; i < cnt; i++) { 472 if (DC_IS_PNIC(sc)) 473 dc_eeprom_getword_pnic(sc, off + i, &word); 474 else 475 dc_eeprom_getword(sc, off + i, &word); 476 ptr = (u_int16_t *)(dest + (i * 2)); 477 if (swap) 478 *ptr = ntohs(word); 479 else 480 *ptr = word; 481 } 482 483 return; 484 } 485 486 /* 487 * The following two routines are taken from the Macronix 98713 488 * Application Notes pp.19-21. 489 */ 490 /* 491 * Write a bit to the MII bus. 492 */ 493 static void dc_mii_writebit(sc, bit) 494 struct dc_softc *sc; 495 int bit; 496 { 497 if (bit) 498 CSR_WRITE_4(sc, DC_SIO, 499 DC_SIO_ROMCTL_WRITE|DC_SIO_MII_DATAOUT); 500 else 501 CSR_WRITE_4(sc, DC_SIO, DC_SIO_ROMCTL_WRITE); 502 503 DC_SETBIT(sc, DC_SIO, DC_SIO_MII_CLK); 504 DC_CLRBIT(sc, DC_SIO, DC_SIO_MII_CLK); 505 506 return; 507 } 508 509 /* 510 * Read a bit from the MII bus. 511 */ 512 static int dc_mii_readbit(sc) 513 struct dc_softc *sc; 514 { 515 CSR_WRITE_4(sc, DC_SIO, DC_SIO_ROMCTL_READ|DC_SIO_MII_DIR); 516 CSR_READ_4(sc, DC_SIO); 517 DC_SETBIT(sc, DC_SIO, DC_SIO_MII_CLK); 518 DC_CLRBIT(sc, DC_SIO, DC_SIO_MII_CLK); 519 if (CSR_READ_4(sc, DC_SIO) & DC_SIO_MII_DATAIN) 520 return(1); 521 522 return(0); 523 } 524 525 /* 526 * Sync the PHYs by setting data bit and strobing the clock 32 times. 527 */ 528 static void dc_mii_sync(sc) 529 struct dc_softc *sc; 530 { 531 register int i; 532 533 CSR_WRITE_4(sc, DC_SIO, DC_SIO_ROMCTL_WRITE); 534 535 for (i = 0; i < 32; i++) 536 dc_mii_writebit(sc, 1); 537 538 return; 539 } 540 541 /* 542 * Clock a series of bits through the MII. 543 */ 544 static void dc_mii_send(sc, bits, cnt) 545 struct dc_softc *sc; 546 u_int32_t bits; 547 int cnt; 548 { 549 int i; 550 551 for (i = (0x1 << (cnt - 1)); i; i >>= 1) 552 dc_mii_writebit(sc, bits & i); 553 } 554 555 /* 556 * Read an PHY register through the MII. 557 */ 558 static int dc_mii_readreg(sc, frame) 559 struct dc_softc *sc; 560 struct dc_mii_frame *frame; 561 562 { 563 int i, ack, s; 564 565 s = splimp(); 566 567 /* 568 * Set up frame for RX. 569 */ 570 frame->mii_stdelim = DC_MII_STARTDELIM; 571 frame->mii_opcode = DC_MII_READOP; 572 frame->mii_turnaround = 0; 573 frame->mii_data = 0; 574 575 /* 576 * Sync the PHYs. 577 */ 578 dc_mii_sync(sc); 579 580 /* 581 * Send command/address info. 582 */ 583 dc_mii_send(sc, frame->mii_stdelim, 2); 584 dc_mii_send(sc, frame->mii_opcode, 2); 585 dc_mii_send(sc, frame->mii_phyaddr, 5); 586 dc_mii_send(sc, frame->mii_regaddr, 5); 587 588 #ifdef notdef 589 /* Idle bit */ 590 dc_mii_writebit(sc, 1); 591 dc_mii_writebit(sc, 0); 592 #endif 593 594 /* Check for ack */ 595 ack = dc_mii_readbit(sc); 596 597 /* 598 * Now try reading data bits. If the ack failed, we still 599 * need to clock through 16 cycles to keep the PHY(s) in sync. 600 */ 601 if (ack) { 602 for(i = 0; i < 16; i++) { 603 dc_mii_readbit(sc); 604 } 605 goto fail; 606 } 607 608 for (i = 0x8000; i; i >>= 1) { 609 if (!ack) { 610 if (dc_mii_readbit(sc)) 611 frame->mii_data |= i; 612 } 613 } 614 615 fail: 616 617 dc_mii_writebit(sc, 0); 618 dc_mii_writebit(sc, 0); 619 620 splx(s); 621 622 if (ack) 623 return(1); 624 return(0); 625 } 626 627 /* 628 * Write to a PHY register through the MII. 629 */ 630 static int dc_mii_writereg(sc, frame) 631 struct dc_softc *sc; 632 struct dc_mii_frame *frame; 633 634 { 635 int s; 636 637 s = splimp(); 638 /* 639 * Set up frame for TX. 640 */ 641 642 frame->mii_stdelim = DC_MII_STARTDELIM; 643 frame->mii_opcode = DC_MII_WRITEOP; 644 frame->mii_turnaround = DC_MII_TURNAROUND; 645 646 /* 647 * Sync the PHYs. 648 */ 649 dc_mii_sync(sc); 650 651 dc_mii_send(sc, frame->mii_stdelim, 2); 652 dc_mii_send(sc, frame->mii_opcode, 2); 653 dc_mii_send(sc, frame->mii_phyaddr, 5); 654 dc_mii_send(sc, frame->mii_regaddr, 5); 655 dc_mii_send(sc, frame->mii_turnaround, 2); 656 dc_mii_send(sc, frame->mii_data, 16); 657 658 /* Idle bit. */ 659 dc_mii_writebit(sc, 0); 660 dc_mii_writebit(sc, 0); 661 662 splx(s); 663 664 return(0); 665 } 666 667 static int dc_miibus_readreg(dev, phy, reg) 668 device_t dev; 669 int phy, reg; 670 { 671 struct dc_mii_frame frame; 672 struct dc_softc *sc; 673 int i, rval, phy_reg; 674 675 sc = device_get_softc(dev); 676 bzero((char *)&frame, sizeof(frame)); 677 678 /* 679 * Note: both the AL981 and AN985 have internal PHYs, 680 * however the AL981 provides direct access to the PHY 681 * registers while the AN985 uses a serial MII interface. 682 * The AN985's MII interface is also buggy in that you 683 * can read from any MII address (0 to 31), but only address 1 684 * behaves normally. To deal with both cases, we pretend 685 * that the PHY is at MII address 1. 686 */ 687 if (DC_IS_ADMTEK(sc) && phy != DC_ADMTEK_PHYADDR) 688 return(0); 689 690 if (sc->dc_pmode == DC_PMODE_SYM) { 691 if (phy == (MII_NPHY - 1)) { 692 switch(reg) { 693 case MII_BMSR: 694 /* 695 * Fake something to make the probe 696 * code think there's a PHY here. 697 */ 698 return(BMSR_MEDIAMASK); 699 break; 700 case MII_PHYIDR1: 701 if (DC_IS_PNIC(sc)) 702 return(DC_VENDORID_LO); 703 return(DC_VENDORID_DEC); 704 break; 705 case MII_PHYIDR2: 706 if (DC_IS_PNIC(sc)) 707 return(DC_DEVICEID_82C168); 708 return(DC_DEVICEID_21143); 709 break; 710 default: 711 return(0); 712 break; 713 } 714 } else 715 return(0); 716 } 717 718 if (DC_IS_PNIC(sc)) { 719 CSR_WRITE_4(sc, DC_PN_MII, DC_PN_MIIOPCODE_READ | 720 (phy << 23) | (reg << 18)); 721 for (i = 0; i < DC_TIMEOUT; i++) { 722 DELAY(1); 723 rval = CSR_READ_4(sc, DC_PN_MII); 724 if (!(rval & DC_PN_MII_BUSY)) { 725 rval &= 0xFFFF; 726 return(rval == 0xFFFF ? 0 : rval); 727 } 728 } 729 return(0); 730 } 731 732 if (DC_IS_COMET(sc)) { 733 switch(reg) { 734 case MII_BMCR: 735 phy_reg = DC_AL_BMCR; 736 break; 737 case MII_BMSR: 738 phy_reg = DC_AL_BMSR; 739 break; 740 case MII_PHYIDR1: 741 phy_reg = DC_AL_VENID; 742 break; 743 case MII_PHYIDR2: 744 phy_reg = DC_AL_DEVID; 745 break; 746 case MII_ANAR: 747 phy_reg = DC_AL_ANAR; 748 break; 749 case MII_ANLPAR: 750 phy_reg = DC_AL_LPAR; 751 break; 752 case MII_ANER: 753 phy_reg = DC_AL_ANER; 754 break; 755 default: 756 printf("dc%d: phy_read: bad phy register %x\n", 757 sc->dc_unit, reg); 758 return(0); 759 break; 760 } 761 762 rval = CSR_READ_4(sc, phy_reg) & 0x0000FFFF; 763 764 if (rval == 0xFFFF) 765 return(0); 766 return(rval); 767 } 768 769 frame.mii_phyaddr = phy; 770 frame.mii_regaddr = reg; 771 phy_reg = CSR_READ_4(sc, DC_NETCFG); 772 CSR_WRITE_4(sc, DC_NETCFG, phy_reg & ~DC_NETCFG_PORTSEL); 773 dc_mii_readreg(sc, &frame); 774 CSR_WRITE_4(sc, DC_NETCFG, phy_reg); 775 776 return(frame.mii_data); 777 } 778 779 static int dc_miibus_writereg(dev, phy, reg, data) 780 device_t dev; 781 int phy, reg, data; 782 { 783 struct dc_softc *sc; 784 struct dc_mii_frame frame; 785 int i, phy_reg; 786 787 sc = device_get_softc(dev); 788 bzero((char *)&frame, sizeof(frame)); 789 790 if (DC_IS_ADMTEK(sc) && phy != DC_ADMTEK_PHYADDR) 791 return(0); 792 793 if (DC_IS_PNIC(sc)) { 794 CSR_WRITE_4(sc, DC_PN_MII, DC_PN_MIIOPCODE_WRITE | 795 (phy << 23) | (reg << 10) | data); 796 for (i = 0; i < DC_TIMEOUT; i++) { 797 if (!(CSR_READ_4(sc, DC_PN_MII) & DC_PN_MII_BUSY)) 798 break; 799 } 800 return(0); 801 } 802 803 if (DC_IS_COMET(sc)) { 804 switch(reg) { 805 case MII_BMCR: 806 phy_reg = DC_AL_BMCR; 807 break; 808 case MII_BMSR: 809 phy_reg = DC_AL_BMSR; 810 break; 811 case MII_PHYIDR1: 812 phy_reg = DC_AL_VENID; 813 break; 814 case MII_PHYIDR2: 815 phy_reg = DC_AL_DEVID; 816 break; 817 case MII_ANAR: 818 phy_reg = DC_AL_ANAR; 819 break; 820 case MII_ANLPAR: 821 phy_reg = DC_AL_LPAR; 822 break; 823 case MII_ANER: 824 phy_reg = DC_AL_ANER; 825 break; 826 default: 827 printf("dc%d: phy_write: bad phy register %x\n", 828 sc->dc_unit, reg); 829 return(0); 830 break; 831 } 832 833 CSR_WRITE_4(sc, phy_reg, data); 834 return(0); 835 } 836 837 frame.mii_phyaddr = phy; 838 frame.mii_regaddr = reg; 839 frame.mii_data = data; 840 841 phy_reg = CSR_READ_4(sc, DC_NETCFG); 842 CSR_WRITE_4(sc, DC_NETCFG, phy_reg & ~DC_NETCFG_PORTSEL); 843 dc_mii_writereg(sc, &frame); 844 CSR_WRITE_4(sc, DC_NETCFG, phy_reg); 845 846 return(0); 847 } 848 849 static void dc_miibus_statchg(dev) 850 device_t dev; 851 { 852 struct dc_softc *sc; 853 struct mii_data *mii; 854 struct ifmedia *ifm; 855 856 sc = device_get_softc(dev); 857 if (DC_IS_ADMTEK(sc)) 858 return; 859 mii = device_get_softc(sc->dc_miibus); 860 ifm = &mii->mii_media; 861 if (DC_IS_DAVICOM(sc) && 862 IFM_SUBTYPE(ifm->ifm_media) == IFM_homePNA) { 863 dc_setcfg(sc, ifm->ifm_media); 864 sc->dc_if_media = ifm->ifm_media; 865 } else { 866 dc_setcfg(sc, mii->mii_media_active); 867 sc->dc_if_media = mii->mii_media_active; 868 } 869 870 return; 871 } 872 873 /* 874 * Special support for DM9102A cards with HomePNA PHYs. Note: 875 * with the Davicom DM9102A/DM9801 eval board that I have, it seems 876 * to be impossible to talk to the management interface of the DM9801 877 * PHY (its MDIO pin is not connected to anything). Consequently, 878 * the driver has to just 'know' about the additional mode and deal 879 * with it itself. *sigh* 880 */ 881 static void dc_miibus_mediainit(dev) 882 device_t dev; 883 { 884 struct dc_softc *sc; 885 struct mii_data *mii; 886 struct ifmedia *ifm; 887 int rev; 888 889 rev = pci_read_config(dev, DC_PCI_CFRV, 4) & 0xFF; 890 891 sc = device_get_softc(dev); 892 mii = device_get_softc(sc->dc_miibus); 893 ifm = &mii->mii_media; 894 895 if (DC_IS_DAVICOM(sc) && rev >= DC_REVISION_DM9102A) 896 ifmedia_add(ifm, IFM_ETHER|IFM_homePNA, 0, NULL); 897 898 return; 899 } 900 901 #define DC_POLY 0xEDB88320 902 #define DC_BITS 9 903 #define DC_BITS_PNIC_II 7 904 905 static u_int32_t dc_crc_le(sc, addr) 906 struct dc_softc *sc; 907 caddr_t addr; 908 { 909 u_int32_t idx, bit, data, crc; 910 911 /* Compute CRC for the address value. */ 912 crc = 0xFFFFFFFF; /* initial value */ 913 914 for (idx = 0; idx < 6; idx++) { 915 for (data = *addr++, bit = 0; bit < 8; bit++, data >>= 1) 916 crc = (crc >> 1) ^ (((crc ^ data) & 1) ? DC_POLY : 0); 917 } 918 919 /* The hash table on the PNIC II is only 128 bits wide. */ 920 if (DC_IS_PNICII(sc)) 921 return (crc & ((1 << DC_BITS_PNIC_II) - 1)); 922 923 return (crc & ((1 << DC_BITS) - 1)); 924 } 925 926 /* 927 * Calculate CRC of a multicast group address, return the lower 6 bits. 928 */ 929 static u_int32_t dc_crc_be(addr) 930 caddr_t addr; 931 { 932 u_int32_t crc, carry; 933 int i, j; 934 u_int8_t c; 935 936 /* Compute CRC for the address value. */ 937 crc = 0xFFFFFFFF; /* initial value */ 938 939 for (i = 0; i < 6; i++) { 940 c = *(addr + i); 941 for (j = 0; j < 8; j++) { 942 carry = ((crc & 0x80000000) ? 1 : 0) ^ (c & 0x01); 943 crc <<= 1; 944 c >>= 1; 945 if (carry) 946 crc = (crc ^ 0x04c11db6) | carry; 947 } 948 } 949 950 /* return the filter bit position */ 951 return((crc >> 26) & 0x0000003F); 952 } 953 954 /* 955 * 21143-style RX filter setup routine. Filter programming is done by 956 * downloading a special setup frame into the TX engine. 21143, Macronix, 957 * PNIC, PNIC II and Davicom chips are programmed this way. 958 * 959 * We always program the chip using 'hash perfect' mode, i.e. one perfect 960 * address (our node address) and a 512-bit hash filter for multicast 961 * frames. We also sneak the broadcast address into the hash filter since 962 * we need that too. 963 */ 964 void dc_setfilt_21143(sc) 965 struct dc_softc *sc; 966 { 967 struct dc_desc *sframe; 968 u_int32_t h, *sp; 969 struct ifmultiaddr *ifma; 970 struct ifnet *ifp; 971 int i; 972 973 ifp = &sc->arpcom.ac_if; 974 975 i = sc->dc_cdata.dc_tx_prod; 976 DC_INC(sc->dc_cdata.dc_tx_prod, DC_TX_LIST_CNT); 977 sc->dc_cdata.dc_tx_cnt++; 978 sframe = &sc->dc_ldata->dc_tx_list[i]; 979 sp = (u_int32_t *)&sc->dc_cdata.dc_sbuf; 980 bzero((char *)sp, DC_SFRAME_LEN); 981 982 sframe->dc_data = vtophys(&sc->dc_cdata.dc_sbuf); 983 sframe->dc_ctl = DC_SFRAME_LEN | DC_TXCTL_SETUP | DC_TXCTL_TLINK | 984 DC_FILTER_HASHPERF | DC_TXCTL_FINT; 985 986 sc->dc_cdata.dc_tx_chain[i] = (struct mbuf *)&sc->dc_cdata.dc_sbuf; 987 988 /* If we want promiscuous mode, set the allframes bit. */ 989 if (ifp->if_flags & IFF_PROMISC) 990 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC); 991 else 992 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC); 993 994 if (ifp->if_flags & IFF_ALLMULTI) 995 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI); 996 else 997 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI); 998 999 for (ifma = ifp->if_multiaddrs.lh_first; ifma != NULL; 1000 ifma = ifma->ifma_link.le_next) { 1001 if (ifma->ifma_addr->sa_family != AF_LINK) 1002 continue; 1003 h = dc_crc_le(sc, 1004 LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 1005 sp[h >> 4] |= 1 << (h & 0xF); 1006 } 1007 1008 if (ifp->if_flags & IFF_BROADCAST) { 1009 h = dc_crc_le(sc, (caddr_t)ðerbroadcastaddr); 1010 sp[h >> 4] |= 1 << (h & 0xF); 1011 } 1012 1013 /* Set our MAC address */ 1014 sp[39] = ((u_int16_t *)sc->arpcom.ac_enaddr)[0]; 1015 sp[40] = ((u_int16_t *)sc->arpcom.ac_enaddr)[1]; 1016 sp[41] = ((u_int16_t *)sc->arpcom.ac_enaddr)[2]; 1017 1018 sframe->dc_status = DC_TXSTAT_OWN; 1019 CSR_WRITE_4(sc, DC_TXSTART, 0xFFFFFFFF); 1020 1021 /* 1022 * The PNIC takes an exceedingly long time to process its 1023 * setup frame; wait 10ms after posting the setup frame 1024 * before proceeding, just so it has time to swallow its 1025 * medicine. 1026 */ 1027 DELAY(10000); 1028 1029 ifp->if_timer = 5; 1030 1031 return; 1032 } 1033 1034 void dc_setfilt_admtek(sc) 1035 struct dc_softc *sc; 1036 { 1037 struct ifnet *ifp; 1038 int h = 0; 1039 u_int32_t hashes[2] = { 0, 0 }; 1040 struct ifmultiaddr *ifma; 1041 1042 ifp = &sc->arpcom.ac_if; 1043 1044 /* Init our MAC address */ 1045 CSR_WRITE_4(sc, DC_AL_PAR0, *(u_int32_t *)(&sc->arpcom.ac_enaddr[0])); 1046 CSR_WRITE_4(sc, DC_AL_PAR1, *(u_int32_t *)(&sc->arpcom.ac_enaddr[4])); 1047 1048 /* If we want promiscuous mode, set the allframes bit. */ 1049 if (ifp->if_flags & IFF_PROMISC) 1050 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC); 1051 else 1052 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC); 1053 1054 if (ifp->if_flags & IFF_ALLMULTI) 1055 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI); 1056 else 1057 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI); 1058 1059 /* first, zot all the existing hash bits */ 1060 CSR_WRITE_4(sc, DC_AL_MAR0, 0); 1061 CSR_WRITE_4(sc, DC_AL_MAR1, 0); 1062 1063 /* 1064 * If we're already in promisc or allmulti mode, we 1065 * don't have to bother programming the multicast filter. 1066 */ 1067 if (ifp->if_flags & (IFF_PROMISC|IFF_ALLMULTI)) 1068 return; 1069 1070 /* now program new ones */ 1071 for (ifma = ifp->if_multiaddrs.lh_first; ifma != NULL; 1072 ifma = ifma->ifma_link.le_next) { 1073 if (ifma->ifma_addr->sa_family != AF_LINK) 1074 continue; 1075 h = dc_crc_be(LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 1076 if (h < 32) 1077 hashes[0] |= (1 << h); 1078 else 1079 hashes[1] |= (1 << (h - 32)); 1080 } 1081 1082 CSR_WRITE_4(sc, DC_AL_MAR0, hashes[0]); 1083 CSR_WRITE_4(sc, DC_AL_MAR1, hashes[1]); 1084 1085 return; 1086 } 1087 1088 void dc_setfilt_asix(sc) 1089 struct dc_softc *sc; 1090 { 1091 struct ifnet *ifp; 1092 int h = 0; 1093 u_int32_t hashes[2] = { 0, 0 }; 1094 struct ifmultiaddr *ifma; 1095 1096 ifp = &sc->arpcom.ac_if; 1097 1098 /* Init our MAC address */ 1099 CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_PAR0); 1100 CSR_WRITE_4(sc, DC_AX_FILTDATA, 1101 *(u_int32_t *)(&sc->arpcom.ac_enaddr[0])); 1102 CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_PAR1); 1103 CSR_WRITE_4(sc, DC_AX_FILTDATA, 1104 *(u_int32_t *)(&sc->arpcom.ac_enaddr[4])); 1105 1106 /* If we want promiscuous mode, set the allframes bit. */ 1107 if (ifp->if_flags & IFF_PROMISC) 1108 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC); 1109 else 1110 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC); 1111 1112 if (ifp->if_flags & IFF_ALLMULTI) 1113 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI); 1114 else 1115 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI); 1116 1117 /* 1118 * The ASIX chip has a special bit to enable reception 1119 * of broadcast frames. 1120 */ 1121 if (ifp->if_flags & IFF_BROADCAST) 1122 DC_SETBIT(sc, DC_NETCFG, DC_AX_NETCFG_RX_BROAD); 1123 else 1124 DC_CLRBIT(sc, DC_NETCFG, DC_AX_NETCFG_RX_BROAD); 1125 1126 /* first, zot all the existing hash bits */ 1127 CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_MAR0); 1128 CSR_WRITE_4(sc, DC_AX_FILTDATA, 0); 1129 CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_MAR1); 1130 CSR_WRITE_4(sc, DC_AX_FILTDATA, 0); 1131 1132 /* 1133 * If we're already in promisc or allmulti mode, we 1134 * don't have to bother programming the multicast filter. 1135 */ 1136 if (ifp->if_flags & (IFF_PROMISC|IFF_ALLMULTI)) 1137 return; 1138 1139 /* now program new ones */ 1140 for (ifma = ifp->if_multiaddrs.lh_first; ifma != NULL; 1141 ifma = ifma->ifma_link.le_next) { 1142 if (ifma->ifma_addr->sa_family != AF_LINK) 1143 continue; 1144 h = dc_crc_be(LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 1145 if (h < 32) 1146 hashes[0] |= (1 << h); 1147 else 1148 hashes[1] |= (1 << (h - 32)); 1149 } 1150 1151 CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_MAR0); 1152 CSR_WRITE_4(sc, DC_AX_FILTDATA, hashes[0]); 1153 CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_MAR1); 1154 CSR_WRITE_4(sc, DC_AX_FILTDATA, hashes[1]); 1155 1156 return; 1157 } 1158 1159 static void dc_setfilt(sc) 1160 struct dc_softc *sc; 1161 { 1162 if (DC_IS_INTEL(sc) || DC_IS_MACRONIX(sc) || DC_IS_PNIC(sc) || 1163 DC_IS_PNICII(sc) || DC_IS_DAVICOM(sc)) 1164 dc_setfilt_21143(sc); 1165 1166 if (DC_IS_ASIX(sc)) 1167 dc_setfilt_asix(sc); 1168 1169 if (DC_IS_ADMTEK(sc)) 1170 dc_setfilt_admtek(sc); 1171 1172 return; 1173 } 1174 1175 /* 1176 * In order to fiddle with the 1177 * 'full-duplex' and '100Mbps' bits in the netconfig register, we 1178 * first have to put the transmit and/or receive logic in the idle state. 1179 */ 1180 static void dc_setcfg(sc, media) 1181 struct dc_softc *sc; 1182 int media; 1183 { 1184 int i, restart = 0; 1185 u_int32_t isr; 1186 1187 if (IFM_SUBTYPE(media) == IFM_NONE) 1188 return; 1189 1190 if (CSR_READ_4(sc, DC_NETCFG) & (DC_NETCFG_TX_ON|DC_NETCFG_RX_ON)) { 1191 restart = 1; 1192 DC_CLRBIT(sc, DC_NETCFG, (DC_NETCFG_TX_ON|DC_NETCFG_RX_ON)); 1193 1194 for (i = 0; i < DC_TIMEOUT; i++) { 1195 DELAY(10); 1196 isr = CSR_READ_4(sc, DC_ISR); 1197 if (isr & DC_ISR_TX_IDLE || 1198 (isr & DC_ISR_RX_STATE) == DC_RXSTATE_STOPPED) 1199 break; 1200 } 1201 1202 if (i == DC_TIMEOUT) 1203 printf("dc%d: failed to force tx and " 1204 "rx to idle state\n", sc->dc_unit); 1205 1206 } 1207 1208 if (IFM_SUBTYPE(media) == IFM_100_TX) { 1209 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_SPEEDSEL); 1210 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_HEARTBEAT); 1211 if (sc->dc_pmode == DC_PMODE_MII) { 1212 DC_SETBIT(sc, DC_WATCHDOG, DC_WDOG_JABBERDIS); 1213 DC_CLRBIT(sc, DC_NETCFG, (DC_NETCFG_PCS| 1214 DC_NETCFG_PORTSEL|DC_NETCFG_SCRAMBLER)); 1215 if (sc->dc_type == DC_TYPE_98713) 1216 DC_SETBIT(sc, DC_NETCFG, (DC_NETCFG_PCS| 1217 DC_NETCFG_SCRAMBLER)); 1218 if (!DC_IS_DAVICOM(sc)) 1219 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL); 1220 DC_CLRBIT(sc, DC_10BTCTRL, 0xFFFF); 1221 } else { 1222 if (DC_IS_PNIC(sc)) { 1223 DC_PN_GPIO_SETBIT(sc, DC_PN_GPIO_SPEEDSEL); 1224 DC_PN_GPIO_SETBIT(sc, DC_PN_GPIO_100TX_LOOP); 1225 DC_SETBIT(sc, DC_PN_NWAY, DC_PN_NWAY_SPEEDSEL); 1226 } 1227 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL); 1228 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PCS); 1229 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_SCRAMBLER); 1230 } 1231 } 1232 1233 if (IFM_SUBTYPE(media) == IFM_10_T) { 1234 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_SPEEDSEL); 1235 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_HEARTBEAT); 1236 if (sc->dc_pmode == DC_PMODE_MII) { 1237 DC_SETBIT(sc, DC_WATCHDOG, DC_WDOG_JABBERDIS); 1238 DC_CLRBIT(sc, DC_NETCFG, (DC_NETCFG_PCS| 1239 DC_NETCFG_PORTSEL|DC_NETCFG_SCRAMBLER)); 1240 if (sc->dc_type == DC_TYPE_98713) 1241 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PCS); 1242 if (!DC_IS_DAVICOM(sc)) 1243 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL); 1244 DC_CLRBIT(sc, DC_10BTCTRL, 0xFFFF); 1245 } else { 1246 if (DC_IS_PNIC(sc)) { 1247 DC_PN_GPIO_CLRBIT(sc, DC_PN_GPIO_SPEEDSEL); 1248 DC_PN_GPIO_SETBIT(sc, DC_PN_GPIO_100TX_LOOP); 1249 DC_CLRBIT(sc, DC_PN_NWAY, DC_PN_NWAY_SPEEDSEL); 1250 } 1251 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL); 1252 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_PCS); 1253 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_SCRAMBLER); 1254 } 1255 } 1256 1257 /* 1258 * If this is a Davicom DM9102A card with a DM9801 HomePNA 1259 * PHY and we want HomePNA mode, set the portsel bit to turn 1260 * on the external MII port. 1261 */ 1262 if (DC_IS_DAVICOM(sc)) { 1263 if (IFM_SUBTYPE(media) == IFM_homePNA) { 1264 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL); 1265 sc->dc_link = 1; 1266 } else { 1267 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL); 1268 } 1269 } 1270 1271 if ((media & IFM_GMASK) == IFM_FDX) { 1272 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_FULLDUPLEX); 1273 if (sc->dc_pmode == DC_PMODE_SYM && DC_IS_PNIC(sc)) 1274 DC_SETBIT(sc, DC_PN_NWAY, DC_PN_NWAY_DUPLEX); 1275 } else { 1276 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_FULLDUPLEX); 1277 if (sc->dc_pmode == DC_PMODE_SYM && DC_IS_PNIC(sc)) 1278 DC_CLRBIT(sc, DC_PN_NWAY, DC_PN_NWAY_DUPLEX); 1279 } 1280 1281 if (restart) 1282 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_TX_ON|DC_NETCFG_RX_ON); 1283 1284 return; 1285 } 1286 1287 static void dc_reset(sc) 1288 struct dc_softc *sc; 1289 { 1290 register int i; 1291 1292 DC_SETBIT(sc, DC_BUSCTL, DC_BUSCTL_RESET); 1293 1294 for (i = 0; i < DC_TIMEOUT; i++) { 1295 DELAY(10); 1296 if (!(CSR_READ_4(sc, DC_BUSCTL) & DC_BUSCTL_RESET)) 1297 break; 1298 } 1299 1300 if (DC_IS_ASIX(sc) || DC_IS_ADMTEK(sc)) { 1301 DELAY(10000); 1302 DC_CLRBIT(sc, DC_BUSCTL, DC_BUSCTL_RESET); 1303 i = 0; 1304 } 1305 1306 if (i == DC_TIMEOUT) 1307 printf("dc%d: reset never completed!\n", sc->dc_unit); 1308 1309 /* Wait a little while for the chip to get its brains in order. */ 1310 DELAY(1000); 1311 1312 CSR_WRITE_4(sc, DC_IMR, 0x00000000); 1313 CSR_WRITE_4(sc, DC_BUSCTL, 0x00000000); 1314 CSR_WRITE_4(sc, DC_NETCFG, 0x00000000); 1315 1316 /* 1317 * Bring the SIA out of reset. In some cases, it looks 1318 * like failing to unreset the SIA soon enough gets it 1319 * into a state where it will never come out of reset 1320 * until we reset the whole chip again. 1321 */ 1322 if (DC_IS_INTEL(sc)) 1323 DC_SETBIT(sc, DC_SIARESET, DC_SIA_RESET); 1324 1325 return; 1326 } 1327 1328 static struct dc_type *dc_devtype(dev) 1329 device_t dev; 1330 { 1331 struct dc_type *t; 1332 u_int32_t rev; 1333 1334 t = dc_devs; 1335 1336 while(t->dc_name != NULL) { 1337 if ((pci_get_vendor(dev) == t->dc_vid) && 1338 (pci_get_device(dev) == t->dc_did)) { 1339 /* Check the PCI revision */ 1340 rev = pci_read_config(dev, DC_PCI_CFRV, 4) & 0xFF; 1341 if (t->dc_did == DC_DEVICEID_98713 && 1342 rev >= DC_REVISION_98713A) 1343 t++; 1344 if (t->dc_did == DC_DEVICEID_98713_CP && 1345 rev >= DC_REVISION_98713A) 1346 t++; 1347 if (t->dc_did == DC_DEVICEID_987x5 && 1348 rev >= DC_REVISION_98725) 1349 t++; 1350 if (t->dc_did == DC_DEVICEID_AX88140A && 1351 rev >= DC_REVISION_88141) 1352 t++; 1353 if (t->dc_did == DC_DEVICEID_82C168 && 1354 rev >= DC_REVISION_82C169) 1355 t++; 1356 if (t->dc_did == DC_DEVICEID_DM9102 && 1357 rev >= DC_REVISION_DM9102A) 1358 t++; 1359 return(t); 1360 } 1361 t++; 1362 } 1363 1364 return(NULL); 1365 } 1366 1367 /* 1368 * Probe for a 21143 or clone chip. Check the PCI vendor and device 1369 * IDs against our list and return a device name if we find a match. 1370 * We do a little bit of extra work to identify the exact type of 1371 * chip. The MX98713 and MX98713A have the same PCI vendor/device ID, 1372 * but different revision IDs. The same is true for 98715/98715A 1373 * chips and the 98725, as well as the ASIX and ADMtek chips. In some 1374 * cases, the exact chip revision affects driver behavior. 1375 */ 1376 static int dc_probe(dev) 1377 device_t dev; 1378 { 1379 struct dc_type *t; 1380 1381 t = dc_devtype(dev); 1382 1383 if (t != NULL) { 1384 device_set_desc(dev, t->dc_name); 1385 return(0); 1386 } 1387 1388 return(ENXIO); 1389 } 1390 1391 static void dc_acpi(dev) 1392 device_t dev; 1393 { 1394 u_int32_t r, cptr; 1395 int unit; 1396 1397 unit = device_get_unit(dev); 1398 1399 /* Find the location of the capabilities block */ 1400 cptr = pci_read_config(dev, DC_PCI_CCAP, 4) & 0xFF; 1401 1402 r = pci_read_config(dev, cptr, 4) & 0xFF; 1403 if (r == 0x01) { 1404 1405 r = pci_read_config(dev, cptr + 4, 4); 1406 if (r & DC_PSTATE_D3) { 1407 u_int32_t iobase, membase, irq; 1408 1409 /* Save important PCI config data. */ 1410 iobase = pci_read_config(dev, DC_PCI_CFBIO, 4); 1411 membase = pci_read_config(dev, DC_PCI_CFBMA, 4); 1412 irq = pci_read_config(dev, DC_PCI_CFIT, 4); 1413 1414 /* Reset the power state. */ 1415 printf("dc%d: chip is in D%d power mode " 1416 "-- setting to D0\n", unit, r & DC_PSTATE_D3); 1417 r &= 0xFFFFFFFC; 1418 pci_write_config(dev, cptr + 4, r, 4); 1419 1420 /* Restore PCI config data. */ 1421 pci_write_config(dev, DC_PCI_CFBIO, iobase, 4); 1422 pci_write_config(dev, DC_PCI_CFBMA, membase, 4); 1423 pci_write_config(dev, DC_PCI_CFIT, irq, 4); 1424 } 1425 } 1426 return; 1427 } 1428 1429 /* 1430 * Attach the interface. Allocate softc structures, do ifmedia 1431 * setup and ethernet/BPF attach. 1432 */ 1433 static int dc_attach(dev) 1434 device_t dev; 1435 { 1436 int s; 1437 u_char eaddr[ETHER_ADDR_LEN]; 1438 u_int32_t command; 1439 struct dc_softc *sc; 1440 struct ifnet *ifp; 1441 u_int32_t revision; 1442 int unit, error = 0, rid, mac_offset; 1443 1444 s = splimp(); 1445 1446 sc = device_get_softc(dev); 1447 unit = device_get_unit(dev); 1448 bzero(sc, sizeof(struct dc_softc)); 1449 1450 /* 1451 * Handle power management nonsense. 1452 */ 1453 dc_acpi(dev); 1454 1455 /* 1456 * Map control/status registers. 1457 */ 1458 command = pci_read_config(dev, PCIR_COMMAND, 4); 1459 command |= (PCIM_CMD_PORTEN|PCIM_CMD_MEMEN|PCIM_CMD_BUSMASTEREN); 1460 pci_write_config(dev, PCIR_COMMAND, command, 4); 1461 command = pci_read_config(dev, PCIR_COMMAND, 4); 1462 1463 #ifdef DC_USEIOSPACE 1464 if (!(command & PCIM_CMD_PORTEN)) { 1465 printf("dc%d: failed to enable I/O ports!\n", unit); 1466 error = ENXIO; 1467 goto fail; 1468 } 1469 #else 1470 if (!(command & PCIM_CMD_MEMEN)) { 1471 printf("dc%d: failed to enable memory mapping!\n", unit); 1472 error = ENXIO; 1473 goto fail; 1474 } 1475 #endif 1476 1477 rid = DC_RID; 1478 sc->dc_res = bus_alloc_resource(dev, DC_RES, &rid, 1479 0, ~0, 1, RF_ACTIVE); 1480 1481 if (sc->dc_res == NULL) { 1482 printf("dc%d: couldn't map ports/memory\n", unit); 1483 error = ENXIO; 1484 goto fail; 1485 } 1486 1487 sc->dc_btag = rman_get_bustag(sc->dc_res); 1488 sc->dc_bhandle = rman_get_bushandle(sc->dc_res); 1489 1490 /* Allocate interrupt */ 1491 rid = 0; 1492 sc->dc_irq = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, 0, ~0, 1, 1493 RF_SHAREABLE | RF_ACTIVE); 1494 1495 if (sc->dc_irq == NULL) { 1496 printf("dc%d: couldn't map interrupt\n", unit); 1497 bus_release_resource(dev, DC_RES, DC_RID, sc->dc_res); 1498 error = ENXIO; 1499 goto fail; 1500 } 1501 1502 error = bus_setup_intr(dev, sc->dc_irq, INTR_TYPE_NET, 1503 dc_intr, sc, &sc->dc_intrhand); 1504 1505 if (error) { 1506 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->dc_irq); 1507 bus_release_resource(dev, DC_RES, DC_RID, sc->dc_res); 1508 printf("dc%d: couldn't set up irq\n", unit); 1509 goto fail; 1510 } 1511 1512 /* Need this info to decide on a chip type. */ 1513 sc->dc_info = dc_devtype(dev); 1514 revision = pci_read_config(dev, DC_PCI_CFRV, 4) & 0x000000FF; 1515 1516 switch(sc->dc_info->dc_did) { 1517 case DC_DEVICEID_21143: 1518 sc->dc_type = DC_TYPE_21143; 1519 sc->dc_flags |= DC_TX_POLL|DC_TX_USE_TX_INTR; 1520 sc->dc_flags |= DC_REDUCED_MII_POLL; 1521 break; 1522 case DC_DEVICEID_DM9100: 1523 case DC_DEVICEID_DM9102: 1524 sc->dc_type = DC_TYPE_DM9102; 1525 sc->dc_flags |= DC_TX_COALESCE|DC_TX_USE_TX_INTR; 1526 sc->dc_flags |= DC_REDUCED_MII_POLL; 1527 sc->dc_pmode = DC_PMODE_MII; 1528 break; 1529 case DC_DEVICEID_AL981: 1530 sc->dc_type = DC_TYPE_AL981; 1531 sc->dc_flags |= DC_TX_USE_TX_INTR; 1532 sc->dc_flags |= DC_TX_ADMTEK_WAR; 1533 sc->dc_pmode = DC_PMODE_MII; 1534 break; 1535 case DC_DEVICEID_AN985: 1536 sc->dc_type = DC_TYPE_AN985; 1537 sc->dc_flags |= DC_TX_USE_TX_INTR; 1538 sc->dc_flags |= DC_TX_ADMTEK_WAR; 1539 sc->dc_pmode = DC_PMODE_MII; 1540 break; 1541 case DC_DEVICEID_98713: 1542 case DC_DEVICEID_98713_CP: 1543 if (revision < DC_REVISION_98713A) { 1544 sc->dc_type = DC_TYPE_98713; 1545 } 1546 if (revision >= DC_REVISION_98713A) { 1547 sc->dc_type = DC_TYPE_98713A; 1548 sc->dc_flags |= DC_21143_NWAY; 1549 } 1550 sc->dc_flags |= DC_REDUCED_MII_POLL; 1551 sc->dc_flags |= DC_TX_POLL|DC_TX_USE_TX_INTR; 1552 break; 1553 case DC_DEVICEID_987x5: 1554 case DC_DEVICEID_EN1217: 1555 sc->dc_type = DC_TYPE_987x5; 1556 sc->dc_flags |= DC_TX_POLL|DC_TX_USE_TX_INTR; 1557 sc->dc_flags |= DC_REDUCED_MII_POLL|DC_21143_NWAY; 1558 break; 1559 case DC_DEVICEID_82C115: 1560 sc->dc_type = DC_TYPE_PNICII; 1561 sc->dc_flags |= DC_TX_POLL|DC_TX_USE_TX_INTR; 1562 sc->dc_flags |= DC_REDUCED_MII_POLL|DC_21143_NWAY; 1563 break; 1564 case DC_DEVICEID_82C168: 1565 sc->dc_type = DC_TYPE_PNIC; 1566 sc->dc_flags |= DC_TX_STORENFWD|DC_TX_INTR_ALWAYS; 1567 sc->dc_flags |= DC_PNIC_RX_BUG_WAR; 1568 sc->dc_pnic_rx_buf = malloc(DC_RXLEN * 5, M_DEVBUF, M_NOWAIT); 1569 if (revision < DC_REVISION_82C169) 1570 sc->dc_pmode = DC_PMODE_SYM; 1571 break; 1572 case DC_DEVICEID_AX88140A: 1573 sc->dc_type = DC_TYPE_ASIX; 1574 sc->dc_flags |= DC_TX_USE_TX_INTR|DC_TX_INTR_FIRSTFRAG; 1575 sc->dc_flags |= DC_REDUCED_MII_POLL; 1576 sc->dc_pmode = DC_PMODE_MII; 1577 break; 1578 default: 1579 printf("dc%d: unknown device: %x\n", sc->dc_unit, 1580 sc->dc_info->dc_did); 1581 break; 1582 } 1583 1584 /* Save the cache line size. */ 1585 if (DC_IS_DAVICOM(sc)) 1586 sc->dc_cachesize = 0; 1587 else 1588 sc->dc_cachesize = pci_read_config(dev, 1589 DC_PCI_CFLT, 4) & 0xFF; 1590 1591 /* Reset the adapter. */ 1592 dc_reset(sc); 1593 1594 /* Take 21143 out of snooze mode */ 1595 if (DC_IS_INTEL(sc)) { 1596 command = pci_read_config(dev, DC_PCI_CFDD, 4); 1597 command &= ~(DC_CFDD_SNOOZE_MODE|DC_CFDD_SLEEP_MODE); 1598 pci_write_config(dev, DC_PCI_CFDD, command, 4); 1599 } 1600 1601 /* 1602 * Try to learn something about the supported media. 1603 * We know that ASIX and ADMtek and Davicom devices 1604 * will *always* be using MII media, so that's a no-brainer. 1605 * The tricky ones are the Macronix/PNIC II and the 1606 * Intel 21143. 1607 */ 1608 if (DC_IS_INTEL(sc)) { 1609 u_int32_t media, cwuc; 1610 cwuc = pci_read_config(dev, DC_PCI_CWUC, 4); 1611 cwuc |= DC_CWUC_FORCE_WUL; 1612 pci_write_config(dev, DC_PCI_CWUC, cwuc, 4); 1613 DELAY(10000); 1614 media = pci_read_config(dev, DC_PCI_CWUC, 4); 1615 cwuc &= ~DC_CWUC_FORCE_WUL; 1616 pci_write_config(dev, DC_PCI_CWUC, cwuc, 4); 1617 DELAY(10000); 1618 if (media & DC_CWUC_MII_ABILITY) 1619 sc->dc_pmode = DC_PMODE_MII; 1620 if (media & DC_CWUC_SYM_ABILITY) { 1621 sc->dc_pmode = DC_PMODE_SYM; 1622 sc->dc_flags |= DC_21143_NWAY; 1623 } 1624 /* 1625 * If none of the bits are set, then this NIC 1626 * isn't meant to support 'wake up LAN' mode. 1627 * This is usually only the case on multiport 1628 * cards, and these cards almost always have 1629 * MII transceivers. 1630 */ 1631 if (media == 0) 1632 sc->dc_pmode = DC_PMODE_MII; 1633 } else if (DC_IS_MACRONIX(sc) || DC_IS_PNICII(sc)) { 1634 if (sc->dc_type == DC_TYPE_98713) 1635 sc->dc_pmode = DC_PMODE_MII; 1636 else 1637 sc->dc_pmode = DC_PMODE_SYM; 1638 } else if (!sc->dc_pmode) 1639 sc->dc_pmode = DC_PMODE_MII; 1640 1641 /* 1642 * Get station address from the EEPROM. 1643 */ 1644 switch(sc->dc_type) { 1645 case DC_TYPE_98713: 1646 case DC_TYPE_98713A: 1647 case DC_TYPE_987x5: 1648 case DC_TYPE_PNICII: 1649 dc_read_eeprom(sc, (caddr_t)&mac_offset, 1650 (DC_EE_NODEADDR_OFFSET / 2), 1, 0); 1651 dc_read_eeprom(sc, (caddr_t)&eaddr, (mac_offset / 2), 3, 0); 1652 break; 1653 case DC_TYPE_PNIC: 1654 dc_read_eeprom(sc, (caddr_t)&eaddr, 0, 3, 1); 1655 break; 1656 case DC_TYPE_DM9102: 1657 case DC_TYPE_21143: 1658 case DC_TYPE_ASIX: 1659 dc_read_eeprom(sc, (caddr_t)&eaddr, DC_EE_NODEADDR, 3, 0); 1660 break; 1661 case DC_TYPE_AL981: 1662 case DC_TYPE_AN985: 1663 dc_read_eeprom(sc, (caddr_t)&eaddr, DC_AL_EE_NODEADDR, 3, 0); 1664 break; 1665 default: 1666 dc_read_eeprom(sc, (caddr_t)&eaddr, DC_EE_NODEADDR, 3, 0); 1667 break; 1668 } 1669 1670 /* 1671 * A 21143 or clone chip was detected. Inform the world. 1672 */ 1673 printf("dc%d: Ethernet address: %6D\n", unit, eaddr, ":"); 1674 1675 sc->dc_unit = unit; 1676 bcopy(eaddr, (char *)&sc->arpcom.ac_enaddr, ETHER_ADDR_LEN); 1677 1678 sc->dc_ldata = contigmalloc(sizeof(struct dc_list_data), M_DEVBUF, 1679 M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0); 1680 1681 if (sc->dc_ldata == NULL) { 1682 printf("dc%d: no memory for list buffers!\n", unit); 1683 bus_teardown_intr(dev, sc->dc_irq, sc->dc_intrhand); 1684 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->dc_irq); 1685 bus_release_resource(dev, DC_RES, DC_RID, sc->dc_res); 1686 error = ENXIO; 1687 goto fail; 1688 } 1689 1690 bzero(sc->dc_ldata, sizeof(struct dc_list_data)); 1691 1692 ifp = &sc->arpcom.ac_if; 1693 ifp->if_softc = sc; 1694 ifp->if_unit = unit; 1695 ifp->if_name = "dc"; 1696 ifp->if_mtu = ETHERMTU; 1697 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 1698 ifp->if_ioctl = dc_ioctl; 1699 ifp->if_output = ether_output; 1700 ifp->if_start = dc_start; 1701 ifp->if_watchdog = dc_watchdog; 1702 ifp->if_init = dc_init; 1703 ifp->if_baudrate = 10000000; 1704 ifp->if_snd.ifq_maxlen = DC_TX_LIST_CNT - 1; 1705 1706 /* 1707 * Do MII setup. 1708 */ 1709 error = mii_phy_probe(dev, &sc->dc_miibus, 1710 dc_ifmedia_upd, dc_ifmedia_sts); 1711 1712 if (error && DC_IS_INTEL(sc)) { 1713 sc->dc_pmode = DC_PMODE_SYM; 1714 sc->dc_flags |= DC_21143_NWAY; 1715 mii_phy_probe(dev, &sc->dc_miibus, 1716 dc_ifmedia_upd, dc_ifmedia_sts); 1717 error = 0; 1718 } 1719 1720 if (error) { 1721 printf("dc%d: MII without any PHY!\n", sc->dc_unit); 1722 bus_teardown_intr(dev, sc->dc_irq, sc->dc_intrhand); 1723 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->dc_irq); 1724 bus_release_resource(dev, DC_RES, DC_RID, sc->dc_res); 1725 error = ENXIO; 1726 goto fail; 1727 } 1728 1729 /* 1730 * Call MI attach routines. 1731 */ 1732 if_attach(ifp); 1733 ether_ifattach(ifp); 1734 callout_handle_init(&sc->dc_stat_ch); 1735 1736 bpfattach(ifp, DLT_EN10MB, sizeof(struct ether_header)); 1737 1738 #ifdef __alpha__ 1739 sc->dc_srm_media = 0; 1740 1741 /* Remember the SRM console media setting */ 1742 if (DC_IS_INTEL(sc)) { 1743 command = pci_read_config(dev, DC_PCI_CFDD, 4); 1744 command &= ~(DC_CFDD_SNOOZE_MODE|DC_CFDD_SLEEP_MODE); 1745 switch ((command >> 8) & 0xff) { 1746 case 3: 1747 sc->dc_srm_media = IFM_10_T; 1748 break; 1749 case 4: 1750 sc->dc_srm_media = IFM_10_T | IFM_FDX; 1751 break; 1752 case 5: 1753 sc->dc_srm_media = IFM_100_TX; 1754 break; 1755 case 6: 1756 sc->dc_srm_media = IFM_100_TX | IFM_FDX; 1757 break; 1758 } 1759 if (sc->dc_srm_media) 1760 sc->dc_srm_media |= IFM_ACTIVE | IFM_ETHER; 1761 } 1762 #endif 1763 1764 1765 fail: 1766 splx(s); 1767 1768 return(error); 1769 } 1770 1771 static int dc_detach(dev) 1772 device_t dev; 1773 { 1774 struct dc_softc *sc; 1775 struct ifnet *ifp; 1776 int s; 1777 1778 s = splimp(); 1779 1780 sc = device_get_softc(dev); 1781 ifp = &sc->arpcom.ac_if; 1782 1783 dc_stop(sc); 1784 if_detach(ifp); 1785 1786 bus_generic_detach(dev); 1787 device_delete_child(dev, sc->dc_miibus); 1788 1789 bus_teardown_intr(dev, sc->dc_irq, sc->dc_intrhand); 1790 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->dc_irq); 1791 bus_release_resource(dev, DC_RES, DC_RID, sc->dc_res); 1792 1793 contigfree(sc->dc_ldata, sizeof(struct dc_list_data), M_DEVBUF); 1794 if (sc->dc_pnic_rx_buf != NULL) 1795 free(sc->dc_pnic_rx_buf, M_DEVBUF); 1796 1797 splx(s); 1798 1799 return(0); 1800 } 1801 1802 /* 1803 * Initialize the transmit descriptors. 1804 */ 1805 static int dc_list_tx_init(sc) 1806 struct dc_softc *sc; 1807 { 1808 struct dc_chain_data *cd; 1809 struct dc_list_data *ld; 1810 int i; 1811 1812 cd = &sc->dc_cdata; 1813 ld = sc->dc_ldata; 1814 for (i = 0; i < DC_TX_LIST_CNT; i++) { 1815 if (i == (DC_TX_LIST_CNT - 1)) { 1816 ld->dc_tx_list[i].dc_next = 1817 vtophys(&ld->dc_tx_list[0]); 1818 } else { 1819 ld->dc_tx_list[i].dc_next = 1820 vtophys(&ld->dc_tx_list[i + 1]); 1821 } 1822 cd->dc_tx_chain[i] = NULL; 1823 ld->dc_tx_list[i].dc_data = 0; 1824 ld->dc_tx_list[i].dc_ctl = 0; 1825 } 1826 1827 cd->dc_tx_prod = cd->dc_tx_cons = cd->dc_tx_cnt = 0; 1828 1829 return(0); 1830 } 1831 1832 1833 /* 1834 * Initialize the RX descriptors and allocate mbufs for them. Note that 1835 * we arrange the descriptors in a closed ring, so that the last descriptor 1836 * points back to the first. 1837 */ 1838 static int dc_list_rx_init(sc) 1839 struct dc_softc *sc; 1840 { 1841 struct dc_chain_data *cd; 1842 struct dc_list_data *ld; 1843 int i; 1844 1845 cd = &sc->dc_cdata; 1846 ld = sc->dc_ldata; 1847 1848 for (i = 0; i < DC_RX_LIST_CNT; i++) { 1849 if (dc_newbuf(sc, i, NULL) == ENOBUFS) 1850 return(ENOBUFS); 1851 if (i == (DC_RX_LIST_CNT - 1)) { 1852 ld->dc_rx_list[i].dc_next = 1853 vtophys(&ld->dc_rx_list[0]); 1854 } else { 1855 ld->dc_rx_list[i].dc_next = 1856 vtophys(&ld->dc_rx_list[i + 1]); 1857 } 1858 } 1859 1860 cd->dc_rx_prod = 0; 1861 1862 return(0); 1863 } 1864 1865 /* 1866 * Initialize an RX descriptor and attach an MBUF cluster. 1867 */ 1868 static int dc_newbuf(sc, i, m) 1869 struct dc_softc *sc; 1870 int i; 1871 struct mbuf *m; 1872 { 1873 struct mbuf *m_new = NULL; 1874 struct dc_desc *c; 1875 1876 c = &sc->dc_ldata->dc_rx_list[i]; 1877 1878 if (m == NULL) { 1879 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 1880 if (m_new == NULL) { 1881 printf("dc%d: no memory for rx list " 1882 "-- packet dropped!\n", sc->dc_unit); 1883 return(ENOBUFS); 1884 } 1885 1886 MCLGET(m_new, M_DONTWAIT); 1887 if (!(m_new->m_flags & M_EXT)) { 1888 printf("dc%d: no memory for rx list " 1889 "-- packet dropped!\n", sc->dc_unit); 1890 m_freem(m_new); 1891 return(ENOBUFS); 1892 } 1893 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 1894 } else { 1895 m_new = m; 1896 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 1897 m_new->m_data = m_new->m_ext.ext_buf; 1898 } 1899 1900 m_adj(m_new, sizeof(u_int64_t)); 1901 1902 /* 1903 * If this is a PNIC chip, zero the buffer. This is part 1904 * of the workaround for the receive bug in the 82c168 and 1905 * 82c169 chips. 1906 */ 1907 if (sc->dc_flags & DC_PNIC_RX_BUG_WAR) 1908 bzero((char *)mtod(m_new, char *), m_new->m_len); 1909 1910 sc->dc_cdata.dc_rx_chain[i] = m_new; 1911 c->dc_data = vtophys(mtod(m_new, caddr_t)); 1912 c->dc_ctl = DC_RXCTL_RLINK | DC_RXLEN; 1913 c->dc_status = DC_RXSTAT_OWN; 1914 1915 return(0); 1916 } 1917 1918 /* 1919 * Grrrrr. 1920 * The PNIC chip has a terrible bug in it that manifests itself during 1921 * periods of heavy activity. The exact mode of failure if difficult to 1922 * pinpoint: sometimes it only happens in promiscuous mode, sometimes it 1923 * will happen on slow machines. The bug is that sometimes instead of 1924 * uploading one complete frame during reception, it uploads what looks 1925 * like the entire contents of its FIFO memory. The frame we want is at 1926 * the end of the whole mess, but we never know exactly how much data has 1927 * been uploaded, so salvaging the frame is hard. 1928 * 1929 * There is only one way to do it reliably, and it's disgusting. 1930 * Here's what we know: 1931 * 1932 * - We know there will always be somewhere between one and three extra 1933 * descriptors uploaded. 1934 * 1935 * - We know the desired received frame will always be at the end of the 1936 * total data upload. 1937 * 1938 * - We know the size of the desired received frame because it will be 1939 * provided in the length field of the status word in the last descriptor. 1940 * 1941 * Here's what we do: 1942 * 1943 * - When we allocate buffers for the receive ring, we bzero() them. 1944 * This means that we know that the buffer contents should be all 1945 * zeros, except for data uploaded by the chip. 1946 * 1947 * - We also force the PNIC chip to upload frames that include the 1948 * ethernet CRC at the end. 1949 * 1950 * - We gather all of the bogus frame data into a single buffer. 1951 * 1952 * - We then position a pointer at the end of this buffer and scan 1953 * backwards until we encounter the first non-zero byte of data. 1954 * This is the end of the received frame. We know we will encounter 1955 * some data at the end of the frame because the CRC will always be 1956 * there, so even if the sender transmits a packet of all zeros, 1957 * we won't be fooled. 1958 * 1959 * - We know the size of the actual received frame, so we subtract 1960 * that value from the current pointer location. This brings us 1961 * to the start of the actual received packet. 1962 * 1963 * - We copy this into an mbuf and pass it on, along with the actual 1964 * frame length. 1965 * 1966 * The performance hit is tremendous, but it beats dropping frames all 1967 * the time. 1968 */ 1969 1970 #define DC_WHOLEFRAME (DC_RXSTAT_FIRSTFRAG|DC_RXSTAT_LASTFRAG) 1971 static void dc_pnic_rx_bug_war(sc, idx) 1972 struct dc_softc *sc; 1973 int idx; 1974 { 1975 struct dc_desc *cur_rx; 1976 struct dc_desc *c = NULL; 1977 struct mbuf *m = NULL; 1978 unsigned char *ptr; 1979 int i, total_len; 1980 u_int32_t rxstat = 0; 1981 1982 i = sc->dc_pnic_rx_bug_save; 1983 cur_rx = &sc->dc_ldata->dc_rx_list[idx]; 1984 ptr = sc->dc_pnic_rx_buf; 1985 bzero(ptr, sizeof(DC_RXLEN * 5)); 1986 1987 /* Copy all the bytes from the bogus buffers. */ 1988 while (1) { 1989 c = &sc->dc_ldata->dc_rx_list[i]; 1990 rxstat = c->dc_status; 1991 m = sc->dc_cdata.dc_rx_chain[i]; 1992 bcopy(mtod(m, char *), ptr, DC_RXLEN); 1993 ptr += DC_RXLEN; 1994 /* If this is the last buffer, break out. */ 1995 if (i == idx || rxstat & DC_RXSTAT_LASTFRAG) 1996 break; 1997 dc_newbuf(sc, i, m); 1998 DC_INC(i, DC_RX_LIST_CNT); 1999 } 2000 2001 /* Find the length of the actual receive frame. */ 2002 total_len = DC_RXBYTES(rxstat); 2003 2004 /* Scan backwards until we hit a non-zero byte. */ 2005 while(*ptr == 0x00) 2006 ptr--; 2007 2008 /* Round off. */ 2009 if ((uintptr_t)(ptr) & 0x3) 2010 ptr -= 1; 2011 2012 /* Now find the start of the frame. */ 2013 ptr -= total_len; 2014 if (ptr < sc->dc_pnic_rx_buf) 2015 ptr = sc->dc_pnic_rx_buf; 2016 2017 /* 2018 * Now copy the salvaged frame to the last mbuf and fake up 2019 * the status word to make it look like a successful 2020 * frame reception. 2021 */ 2022 dc_newbuf(sc, i, m); 2023 bcopy(ptr, mtod(m, char *), total_len); 2024 cur_rx->dc_status = rxstat | DC_RXSTAT_FIRSTFRAG; 2025 2026 return; 2027 } 2028 2029 /* 2030 * This routine searches the RX ring for dirty descriptors in the 2031 * event that the rxeof routine falls out of sync with the chip's 2032 * current descriptor pointer. This may happen sometimes as a result 2033 * of a "no RX buffer available" condition that happens when the chip 2034 * consumes all of the RX buffers before the driver has a chance to 2035 * process the RX ring. This routine may need to be called more than 2036 * once to bring the driver back in sync with the chip, however we 2037 * should still be getting RX DONE interrupts to drive the search 2038 * for new packets in the RX ring, so we should catch up eventually. 2039 */ 2040 static int dc_rx_resync(sc) 2041 struct dc_softc *sc; 2042 { 2043 int i, pos; 2044 struct dc_desc *cur_rx; 2045 2046 pos = sc->dc_cdata.dc_rx_prod; 2047 2048 for (i = 0; i < DC_RX_LIST_CNT; i++) { 2049 cur_rx = &sc->dc_ldata->dc_rx_list[pos]; 2050 if (!(cur_rx->dc_status & DC_RXSTAT_OWN)) 2051 break; 2052 DC_INC(pos, DC_RX_LIST_CNT); 2053 } 2054 2055 /* If the ring really is empty, then just return. */ 2056 if (i == DC_RX_LIST_CNT) 2057 return(0); 2058 2059 /* We've fallen behing the chip: catch it. */ 2060 sc->dc_cdata.dc_rx_prod = pos; 2061 2062 return(EAGAIN); 2063 } 2064 2065 /* 2066 * A frame has been uploaded: pass the resulting mbuf chain up to 2067 * the higher level protocols. 2068 */ 2069 static void dc_rxeof(sc) 2070 struct dc_softc *sc; 2071 { 2072 struct ether_header *eh; 2073 struct mbuf *m; 2074 struct ifnet *ifp; 2075 struct dc_desc *cur_rx; 2076 int i, total_len = 0; 2077 u_int32_t rxstat; 2078 2079 ifp = &sc->arpcom.ac_if; 2080 i = sc->dc_cdata.dc_rx_prod; 2081 2082 while(!(sc->dc_ldata->dc_rx_list[i].dc_status & DC_RXSTAT_OWN)) { 2083 struct mbuf *m0 = NULL; 2084 2085 cur_rx = &sc->dc_ldata->dc_rx_list[i]; 2086 rxstat = cur_rx->dc_status; 2087 m = sc->dc_cdata.dc_rx_chain[i]; 2088 total_len = DC_RXBYTES(rxstat); 2089 2090 if (sc->dc_flags & DC_PNIC_RX_BUG_WAR) { 2091 if ((rxstat & DC_WHOLEFRAME) != DC_WHOLEFRAME) { 2092 if (rxstat & DC_RXSTAT_FIRSTFRAG) 2093 sc->dc_pnic_rx_bug_save = i; 2094 if ((rxstat & DC_RXSTAT_LASTFRAG) == 0) { 2095 DC_INC(i, DC_RX_LIST_CNT); 2096 continue; 2097 } 2098 dc_pnic_rx_bug_war(sc, i); 2099 rxstat = cur_rx->dc_status; 2100 total_len = DC_RXBYTES(rxstat); 2101 } 2102 } 2103 2104 sc->dc_cdata.dc_rx_chain[i] = NULL; 2105 2106 /* 2107 * If an error occurs, update stats, clear the 2108 * status word and leave the mbuf cluster in place: 2109 * it should simply get re-used next time this descriptor 2110 * comes up in the ring. 2111 */ 2112 if (rxstat & DC_RXSTAT_RXERR) { 2113 ifp->if_ierrors++; 2114 if (rxstat & DC_RXSTAT_COLLSEEN) 2115 ifp->if_collisions++; 2116 dc_newbuf(sc, i, m); 2117 if (rxstat & DC_RXSTAT_CRCERR) { 2118 DC_INC(i, DC_RX_LIST_CNT); 2119 continue; 2120 } else { 2121 dc_init(sc); 2122 return; 2123 } 2124 } 2125 2126 /* No errors; receive the packet. */ 2127 total_len -= ETHER_CRC_LEN; 2128 2129 m0 = m_devget(mtod(m, char *) - ETHER_ALIGN, 2130 total_len + ETHER_ALIGN, 0, ifp, NULL); 2131 dc_newbuf(sc, i, m); 2132 DC_INC(i, DC_RX_LIST_CNT); 2133 if (m0 == NULL) { 2134 ifp->if_ierrors++; 2135 continue; 2136 } 2137 m_adj(m0, ETHER_ALIGN); 2138 m = m0; 2139 2140 ifp->if_ipackets++; 2141 eh = mtod(m, struct ether_header *); 2142 2143 /* Remove header from mbuf and pass it on. */ 2144 m_adj(m, sizeof(struct ether_header)); 2145 ether_input(ifp, eh, m); 2146 } 2147 2148 sc->dc_cdata.dc_rx_prod = i; 2149 } 2150 2151 /* 2152 * A frame was downloaded to the chip. It's safe for us to clean up 2153 * the list buffers. 2154 */ 2155 2156 static void dc_txeof(sc) 2157 struct dc_softc *sc; 2158 { 2159 struct dc_desc *cur_tx = NULL; 2160 struct ifnet *ifp; 2161 int idx; 2162 2163 ifp = &sc->arpcom.ac_if; 2164 2165 /* Clear the timeout timer. */ 2166 ifp->if_timer = 0; 2167 2168 /* 2169 * Go through our tx list and free mbufs for those 2170 * frames that have been transmitted. 2171 */ 2172 idx = sc->dc_cdata.dc_tx_cons; 2173 while(idx != sc->dc_cdata.dc_tx_prod) { 2174 u_int32_t txstat; 2175 2176 cur_tx = &sc->dc_ldata->dc_tx_list[idx]; 2177 txstat = cur_tx->dc_status; 2178 2179 if (txstat & DC_TXSTAT_OWN) 2180 break; 2181 2182 if (!(cur_tx->dc_ctl & DC_TXCTL_LASTFRAG) || 2183 cur_tx->dc_ctl & DC_TXCTL_SETUP) { 2184 sc->dc_cdata.dc_tx_cnt--; 2185 if (cur_tx->dc_ctl & DC_TXCTL_SETUP) { 2186 /* 2187 * Yes, the PNIC is so brain damaged 2188 * that it will sometimes generate a TX 2189 * underrun error while DMAing the RX 2190 * filter setup frame. If we detect this, 2191 * we have to send the setup frame again, 2192 * or else the filter won't be programmed 2193 * correctly. 2194 */ 2195 if (DC_IS_PNIC(sc)) { 2196 if (txstat & DC_TXSTAT_ERRSUM) 2197 dc_setfilt(sc); 2198 } 2199 sc->dc_cdata.dc_tx_chain[idx] = NULL; 2200 } 2201 DC_INC(idx, DC_TX_LIST_CNT); 2202 continue; 2203 } 2204 2205 if (/*sc->dc_type == DC_TYPE_21143 &&*/ 2206 sc->dc_pmode == DC_PMODE_MII && 2207 ((txstat & 0xFFFF) & ~(DC_TXSTAT_ERRSUM| 2208 DC_TXSTAT_NOCARRIER|DC_TXSTAT_CARRLOST))) 2209 txstat &= ~DC_TXSTAT_ERRSUM; 2210 2211 if (txstat & DC_TXSTAT_ERRSUM) { 2212 ifp->if_oerrors++; 2213 if (txstat & DC_TXSTAT_EXCESSCOLL) 2214 ifp->if_collisions++; 2215 if (txstat & DC_TXSTAT_LATECOLL) 2216 ifp->if_collisions++; 2217 if (!(txstat & DC_TXSTAT_UNDERRUN)) { 2218 dc_init(sc); 2219 return; 2220 } 2221 } 2222 2223 ifp->if_collisions += (txstat & DC_TXSTAT_COLLCNT) >> 3; 2224 2225 ifp->if_opackets++; 2226 if (sc->dc_cdata.dc_tx_chain[idx] != NULL) { 2227 m_freem(sc->dc_cdata.dc_tx_chain[idx]); 2228 sc->dc_cdata.dc_tx_chain[idx] = NULL; 2229 } 2230 2231 sc->dc_cdata.dc_tx_cnt--; 2232 DC_INC(idx, DC_TX_LIST_CNT); 2233 } 2234 2235 sc->dc_cdata.dc_tx_cons = idx; 2236 if (cur_tx != NULL) 2237 ifp->if_flags &= ~IFF_OACTIVE; 2238 2239 return; 2240 } 2241 2242 static void dc_tick(xsc) 2243 void *xsc; 2244 { 2245 struct dc_softc *sc; 2246 struct mii_data *mii; 2247 struct ifnet *ifp; 2248 int s; 2249 u_int32_t r; 2250 2251 s = splimp(); 2252 2253 sc = xsc; 2254 ifp = &sc->arpcom.ac_if; 2255 mii = device_get_softc(sc->dc_miibus); 2256 2257 if (sc->dc_flags & DC_REDUCED_MII_POLL) { 2258 if (sc->dc_flags & DC_21143_NWAY) { 2259 r = CSR_READ_4(sc, DC_10BTSTAT); 2260 if (IFM_SUBTYPE(mii->mii_media_active) == 2261 IFM_100_TX && (r & DC_TSTAT_LS100)) { 2262 sc->dc_link = 0; 2263 mii_mediachg(mii); 2264 } 2265 if (IFM_SUBTYPE(mii->mii_media_active) == 2266 IFM_10_T && (r & DC_TSTAT_LS10)) { 2267 sc->dc_link = 0; 2268 mii_mediachg(mii); 2269 } 2270 if (sc->dc_link == 0) 2271 mii_tick(mii); 2272 } else { 2273 r = CSR_READ_4(sc, DC_ISR); 2274 if ((r & DC_ISR_RX_STATE) == DC_RXSTATE_WAIT && 2275 sc->dc_cdata.dc_tx_cnt == 0) 2276 mii_tick(mii); 2277 if (!(mii->mii_media_status & IFM_ACTIVE)) 2278 sc->dc_link = 0; 2279 } 2280 } else 2281 mii_tick(mii); 2282 2283 /* 2284 * When the init routine completes, we expect to be able to send 2285 * packets right away, and in fact the network code will send a 2286 * gratuitous ARP the moment the init routine marks the interface 2287 * as running. However, even though the MAC may have been initialized, 2288 * there may be a delay of a few seconds before the PHY completes 2289 * autonegotiation and the link is brought up. Any transmissions 2290 * made during that delay will be lost. Dealing with this is tricky: 2291 * we can't just pause in the init routine while waiting for the 2292 * PHY to come ready since that would bring the whole system to 2293 * a screeching halt for several seconds. 2294 * 2295 * What we do here is prevent the TX start routine from sending 2296 * any packets until a link has been established. After the 2297 * interface has been initialized, the tick routine will poll 2298 * the state of the PHY until the IFM_ACTIVE flag is set. Until 2299 * that time, packets will stay in the send queue, and once the 2300 * link comes up, they will be flushed out to the wire. 2301 */ 2302 if (!sc->dc_link) { 2303 mii_pollstat(mii); 2304 if (mii->mii_media_status & IFM_ACTIVE && 2305 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) { 2306 sc->dc_link++; 2307 if (ifp->if_snd.ifq_head != NULL) 2308 dc_start(ifp); 2309 } 2310 } 2311 2312 if (sc->dc_flags & DC_21143_NWAY && !sc->dc_link) 2313 sc->dc_stat_ch = timeout(dc_tick, sc, hz/10); 2314 else 2315 sc->dc_stat_ch = timeout(dc_tick, sc, hz); 2316 2317 splx(s); 2318 2319 return; 2320 } 2321 2322 static void dc_intr(arg) 2323 void *arg; 2324 { 2325 struct dc_softc *sc; 2326 struct ifnet *ifp; 2327 u_int32_t status; 2328 2329 sc = arg; 2330 ifp = &sc->arpcom.ac_if; 2331 2332 /* Supress unwanted interrupts */ 2333 if (!(ifp->if_flags & IFF_UP)) { 2334 if (CSR_READ_4(sc, DC_ISR) & DC_INTRS) 2335 dc_stop(sc); 2336 return; 2337 } 2338 2339 /* Disable interrupts. */ 2340 CSR_WRITE_4(sc, DC_IMR, 0x00000000); 2341 2342 while((status = CSR_READ_4(sc, DC_ISR)) & DC_INTRS) { 2343 2344 CSR_WRITE_4(sc, DC_ISR, status); 2345 2346 if (status & DC_ISR_RX_OK) { 2347 int curpkts; 2348 curpkts = ifp->if_ipackets; 2349 dc_rxeof(sc); 2350 if (curpkts == ifp->if_ipackets) { 2351 while(dc_rx_resync(sc)) 2352 dc_rxeof(sc); 2353 } 2354 } 2355 2356 if (status & (DC_ISR_TX_OK|DC_ISR_TX_NOBUF)) 2357 dc_txeof(sc); 2358 2359 if (status & DC_ISR_TX_IDLE) { 2360 dc_txeof(sc); 2361 if (sc->dc_cdata.dc_tx_cnt) { 2362 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_TX_ON); 2363 CSR_WRITE_4(sc, DC_TXSTART, 0xFFFFFFFF); 2364 } 2365 } 2366 2367 if (status & DC_ISR_TX_UNDERRUN) { 2368 u_int32_t cfg; 2369 2370 printf("dc%d: TX underrun -- ", sc->dc_unit); 2371 if (DC_IS_DAVICOM(sc) || DC_IS_INTEL(sc)) 2372 dc_init(sc); 2373 cfg = CSR_READ_4(sc, DC_NETCFG); 2374 cfg &= ~DC_NETCFG_TX_THRESH; 2375 if (sc->dc_txthresh == DC_TXTHRESH_160BYTES) { 2376 printf("using store and forward mode\n"); 2377 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_STORENFWD); 2378 } else if (sc->dc_flags & DC_TX_STORENFWD) { 2379 printf("resetting\n"); 2380 } else { 2381 sc->dc_txthresh += 0x4000; 2382 printf("increasing TX threshold\n"); 2383 CSR_WRITE_4(sc, DC_NETCFG, cfg); 2384 DC_SETBIT(sc, DC_NETCFG, sc->dc_txthresh); 2385 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_STORENFWD); 2386 } 2387 } 2388 2389 if ((status & DC_ISR_RX_WATDOGTIMEO) 2390 || (status & DC_ISR_RX_NOBUF)) { 2391 int curpkts; 2392 curpkts = ifp->if_ipackets; 2393 dc_rxeof(sc); 2394 if (curpkts == ifp->if_ipackets) { 2395 while(dc_rx_resync(sc)) 2396 dc_rxeof(sc); 2397 } 2398 } 2399 2400 if (status & DC_ISR_BUS_ERR) { 2401 dc_reset(sc); 2402 dc_init(sc); 2403 } 2404 } 2405 2406 /* Re-enable interrupts. */ 2407 CSR_WRITE_4(sc, DC_IMR, DC_INTRS); 2408 2409 if (ifp->if_snd.ifq_head != NULL) 2410 dc_start(ifp); 2411 2412 return; 2413 } 2414 2415 /* 2416 * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data 2417 * pointers to the fragment pointers. 2418 */ 2419 static int dc_encap(sc, m_head, txidx) 2420 struct dc_softc *sc; 2421 struct mbuf *m_head; 2422 u_int32_t *txidx; 2423 { 2424 struct dc_desc *f = NULL; 2425 struct mbuf *m; 2426 int frag, cur, cnt = 0; 2427 2428 /* 2429 * Start packing the mbufs in this chain into 2430 * the fragment pointers. Stop when we run out 2431 * of fragments or hit the end of the mbuf chain. 2432 */ 2433 m = m_head; 2434 cur = frag = *txidx; 2435 2436 for (m = m_head; m != NULL; m = m->m_next) { 2437 if (m->m_len != 0) { 2438 if (sc->dc_flags & DC_TX_ADMTEK_WAR) { 2439 if (*txidx != sc->dc_cdata.dc_tx_prod && 2440 frag == (DC_TX_LIST_CNT - 1)) 2441 return(ENOBUFS); 2442 } 2443 if ((DC_TX_LIST_CNT - 2444 (sc->dc_cdata.dc_tx_cnt + cnt)) < 5) 2445 return(ENOBUFS); 2446 2447 f = &sc->dc_ldata->dc_tx_list[frag]; 2448 f->dc_ctl = DC_TXCTL_TLINK | m->m_len; 2449 if (cnt == 0) { 2450 f->dc_status = 0; 2451 f->dc_ctl |= DC_TXCTL_FIRSTFRAG; 2452 } else 2453 f->dc_status = DC_TXSTAT_OWN; 2454 f->dc_data = vtophys(mtod(m, vm_offset_t)); 2455 cur = frag; 2456 DC_INC(frag, DC_TX_LIST_CNT); 2457 cnt++; 2458 } 2459 } 2460 2461 if (m != NULL) 2462 return(ENOBUFS); 2463 2464 sc->dc_cdata.dc_tx_cnt += cnt; 2465 sc->dc_cdata.dc_tx_chain[cur] = m_head; 2466 sc->dc_ldata->dc_tx_list[cur].dc_ctl |= DC_TXCTL_LASTFRAG; 2467 if (sc->dc_flags & DC_TX_INTR_FIRSTFRAG) 2468 sc->dc_ldata->dc_tx_list[*txidx].dc_ctl |= DC_TXCTL_FINT; 2469 if (sc->dc_flags & DC_TX_INTR_ALWAYS) 2470 sc->dc_ldata->dc_tx_list[cur].dc_ctl |= DC_TXCTL_FINT; 2471 if (sc->dc_flags & DC_TX_USE_TX_INTR && sc->dc_cdata.dc_tx_cnt > 64) 2472 sc->dc_ldata->dc_tx_list[cur].dc_ctl |= DC_TXCTL_FINT; 2473 sc->dc_ldata->dc_tx_list[*txidx].dc_status = DC_TXSTAT_OWN; 2474 *txidx = frag; 2475 2476 return(0); 2477 } 2478 2479 /* 2480 * Coalesce an mbuf chain into a single mbuf cluster buffer. 2481 * Needed for some really badly behaved chips that just can't 2482 * do scatter/gather correctly. 2483 */ 2484 static int dc_coal(sc, m_head) 2485 struct dc_softc *sc; 2486 struct mbuf **m_head; 2487 { 2488 struct mbuf *m_new, *m; 2489 2490 m = *m_head; 2491 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 2492 if (m_new == NULL) { 2493 printf("dc%d: no memory for tx list", sc->dc_unit); 2494 return(ENOBUFS); 2495 } 2496 if (m->m_pkthdr.len > MHLEN) { 2497 MCLGET(m_new, M_DONTWAIT); 2498 if (!(m_new->m_flags & M_EXT)) { 2499 m_freem(m_new); 2500 printf("dc%d: no memory for tx list", sc->dc_unit); 2501 return(ENOBUFS); 2502 } 2503 } 2504 m_copydata(m, 0, m->m_pkthdr.len, mtod(m_new, caddr_t)); 2505 m_new->m_pkthdr.len = m_new->m_len = m->m_pkthdr.len; 2506 m_freem(m); 2507 *m_head = m_new; 2508 2509 return(0); 2510 } 2511 2512 /* 2513 * Main transmit routine. To avoid having to do mbuf copies, we put pointers 2514 * to the mbuf data regions directly in the transmit lists. We also save a 2515 * copy of the pointers since the transmit list fragment pointers are 2516 * physical addresses. 2517 */ 2518 2519 static void dc_start(ifp) 2520 struct ifnet *ifp; 2521 { 2522 struct dc_softc *sc; 2523 struct mbuf *m_head = NULL; 2524 int idx; 2525 2526 sc = ifp->if_softc; 2527 2528 if (!sc->dc_link) 2529 return; 2530 2531 if (ifp->if_flags & IFF_OACTIVE) 2532 return; 2533 2534 idx = sc->dc_cdata.dc_tx_prod; 2535 2536 while(sc->dc_cdata.dc_tx_chain[idx] == NULL) { 2537 IF_DEQUEUE(&ifp->if_snd, m_head); 2538 if (m_head == NULL) 2539 break; 2540 2541 if (sc->dc_flags & DC_TX_COALESCE) { 2542 if (dc_coal(sc, &m_head)) { 2543 IF_PREPEND(&ifp->if_snd, m_head); 2544 ifp->if_flags |= IFF_OACTIVE; 2545 break; 2546 } 2547 } 2548 2549 if (dc_encap(sc, m_head, &idx)) { 2550 IF_PREPEND(&ifp->if_snd, m_head); 2551 ifp->if_flags |= IFF_OACTIVE; 2552 break; 2553 } 2554 2555 /* 2556 * If there's a BPF listener, bounce a copy of this frame 2557 * to him. 2558 */ 2559 if (ifp->if_bpf) 2560 bpf_mtap(ifp, m_head); 2561 } 2562 2563 /* Transmit */ 2564 sc->dc_cdata.dc_tx_prod = idx; 2565 if (!(sc->dc_flags & DC_TX_POLL)) 2566 CSR_WRITE_4(sc, DC_TXSTART, 0xFFFFFFFF); 2567 2568 /* 2569 * Set a timeout in case the chip goes out to lunch. 2570 */ 2571 ifp->if_timer = 5; 2572 2573 return; 2574 } 2575 2576 static void dc_init(xsc) 2577 void *xsc; 2578 { 2579 struct dc_softc *sc = xsc; 2580 struct ifnet *ifp = &sc->arpcom.ac_if; 2581 struct mii_data *mii; 2582 int s; 2583 2584 s = splimp(); 2585 2586 mii = device_get_softc(sc->dc_miibus); 2587 2588 /* 2589 * Cancel pending I/O and free all RX/TX buffers. 2590 */ 2591 dc_stop(sc); 2592 dc_reset(sc); 2593 2594 /* 2595 * Set cache alignment and burst length. 2596 */ 2597 if (DC_IS_ASIX(sc) || DC_IS_DAVICOM(sc)) 2598 CSR_WRITE_4(sc, DC_BUSCTL, 0); 2599 else 2600 CSR_WRITE_4(sc, DC_BUSCTL, DC_BUSCTL_MRME|DC_BUSCTL_MRLE); 2601 if (DC_IS_DAVICOM(sc) || DC_IS_INTEL(sc)) { 2602 DC_SETBIT(sc, DC_BUSCTL, DC_BURSTLEN_USECA); 2603 } else { 2604 DC_SETBIT(sc, DC_BUSCTL, DC_BURSTLEN_16LONG); 2605 } 2606 if (sc->dc_flags & DC_TX_POLL) 2607 DC_SETBIT(sc, DC_BUSCTL, DC_TXPOLL_1); 2608 switch(sc->dc_cachesize) { 2609 case 32: 2610 DC_SETBIT(sc, DC_BUSCTL, DC_CACHEALIGN_32LONG); 2611 break; 2612 case 16: 2613 DC_SETBIT(sc, DC_BUSCTL, DC_CACHEALIGN_16LONG); 2614 break; 2615 case 8: 2616 DC_SETBIT(sc, DC_BUSCTL, DC_CACHEALIGN_8LONG); 2617 break; 2618 case 0: 2619 default: 2620 DC_SETBIT(sc, DC_BUSCTL, DC_CACHEALIGN_NONE); 2621 break; 2622 } 2623 2624 if (sc->dc_flags & DC_TX_STORENFWD) 2625 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_STORENFWD); 2626 else { 2627 if (sc->dc_txthresh == DC_TXTHRESH_160BYTES) { 2628 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_STORENFWD); 2629 } else { 2630 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_STORENFWD); 2631 DC_SETBIT(sc, DC_NETCFG, sc->dc_txthresh); 2632 } 2633 } 2634 2635 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_NO_RXCRC); 2636 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_TX_BACKOFF); 2637 2638 if (DC_IS_MACRONIX(sc) || DC_IS_PNICII(sc)) { 2639 /* 2640 * The app notes for the 98713 and 98715A say that 2641 * in order to have the chips operate properly, a magic 2642 * number must be written to CSR16. Macronix does not 2643 * document the meaning of these bits so there's no way 2644 * to know exactly what they do. The 98713 has a magic 2645 * number all its own; the rest all use a different one. 2646 */ 2647 DC_CLRBIT(sc, DC_MX_MAGICPACKET, 0xFFFF0000); 2648 if (sc->dc_type == DC_TYPE_98713) 2649 DC_SETBIT(sc, DC_MX_MAGICPACKET, DC_MX_MAGIC_98713); 2650 else 2651 DC_SETBIT(sc, DC_MX_MAGICPACKET, DC_MX_MAGIC_98715); 2652 } 2653 2654 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_TX_THRESH); 2655 DC_SETBIT(sc, DC_NETCFG, DC_TXTHRESH_72BYTES); 2656 2657 /* Init circular RX list. */ 2658 if (dc_list_rx_init(sc) == ENOBUFS) { 2659 printf("dc%d: initialization failed: no " 2660 "memory for rx buffers\n", sc->dc_unit); 2661 dc_stop(sc); 2662 (void)splx(s); 2663 return; 2664 } 2665 2666 /* 2667 * Init tx descriptors. 2668 */ 2669 dc_list_tx_init(sc); 2670 2671 /* 2672 * Load the address of the RX list. 2673 */ 2674 CSR_WRITE_4(sc, DC_RXADDR, vtophys(&sc->dc_ldata->dc_rx_list[0])); 2675 CSR_WRITE_4(sc, DC_TXADDR, vtophys(&sc->dc_ldata->dc_tx_list[0])); 2676 2677 /* 2678 * Enable interrupts. 2679 */ 2680 CSR_WRITE_4(sc, DC_IMR, DC_INTRS); 2681 CSR_WRITE_4(sc, DC_ISR, 0xFFFFFFFF); 2682 2683 /* Enable transmitter. */ 2684 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_TX_ON); 2685 2686 /* 2687 * Load the RX/multicast filter. We do this sort of late 2688 * because the filter programming scheme on the 21143 and 2689 * some clones requires DMAing a setup frame via the TX 2690 * engine, and we need the transmitter enabled for that. 2691 */ 2692 dc_setfilt(sc); 2693 2694 /* Enable receiver. */ 2695 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_ON); 2696 CSR_WRITE_4(sc, DC_RXSTART, 0xFFFFFFFF); 2697 2698 mii_mediachg(mii); 2699 dc_setcfg(sc, sc->dc_if_media); 2700 2701 ifp->if_flags |= IFF_RUNNING; 2702 ifp->if_flags &= ~IFF_OACTIVE; 2703 2704 (void)splx(s); 2705 2706 if (sc->dc_flags & DC_21143_NWAY) 2707 sc->dc_stat_ch = timeout(dc_tick, sc, hz/10); 2708 else 2709 sc->dc_stat_ch = timeout(dc_tick, sc, hz); 2710 2711 #ifdef __alpha__ 2712 if(sc->dc_srm_media) { 2713 struct ifreq ifr; 2714 2715 ifr.ifr_media = sc->dc_srm_media; 2716 ifmedia_ioctl(ifp, &ifr, &mii->mii_media, SIOCSIFMEDIA); 2717 sc->dc_srm_media = 0; 2718 } 2719 #endif 2720 return; 2721 } 2722 2723 /* 2724 * Set media options. 2725 */ 2726 static int dc_ifmedia_upd(ifp) 2727 struct ifnet *ifp; 2728 { 2729 struct dc_softc *sc; 2730 struct mii_data *mii; 2731 struct ifmedia *ifm; 2732 2733 sc = ifp->if_softc; 2734 mii = device_get_softc(sc->dc_miibus); 2735 mii_mediachg(mii); 2736 ifm = &mii->mii_media; 2737 2738 if (DC_IS_DAVICOM(sc) && 2739 IFM_SUBTYPE(ifm->ifm_media) == IFM_homePNA) 2740 dc_setcfg(sc, ifm->ifm_media); 2741 else 2742 sc->dc_link = 0; 2743 2744 return(0); 2745 } 2746 2747 /* 2748 * Report current media status. 2749 */ 2750 static void dc_ifmedia_sts(ifp, ifmr) 2751 struct ifnet *ifp; 2752 struct ifmediareq *ifmr; 2753 { 2754 struct dc_softc *sc; 2755 struct mii_data *mii; 2756 struct ifmedia *ifm; 2757 2758 sc = ifp->if_softc; 2759 mii = device_get_softc(sc->dc_miibus); 2760 mii_pollstat(mii); 2761 ifm = &mii->mii_media; 2762 if (DC_IS_DAVICOM(sc)) { 2763 if (IFM_SUBTYPE(ifm->ifm_media) == IFM_homePNA) { 2764 ifmr->ifm_active = ifm->ifm_media; 2765 ifmr->ifm_status = 0; 2766 return; 2767 } 2768 } 2769 ifmr->ifm_active = mii->mii_media_active; 2770 ifmr->ifm_status = mii->mii_media_status; 2771 2772 return; 2773 } 2774 2775 static int dc_ioctl(ifp, command, data) 2776 struct ifnet *ifp; 2777 u_long command; 2778 caddr_t data; 2779 { 2780 struct dc_softc *sc = ifp->if_softc; 2781 struct ifreq *ifr = (struct ifreq *) data; 2782 struct mii_data *mii; 2783 int s, error = 0; 2784 2785 s = splimp(); 2786 2787 switch(command) { 2788 case SIOCSIFADDR: 2789 case SIOCGIFADDR: 2790 case SIOCSIFMTU: 2791 error = ether_ioctl(ifp, command, data); 2792 break; 2793 case SIOCSIFFLAGS: 2794 if (ifp->if_flags & IFF_UP) { 2795 if (ifp->if_flags & IFF_RUNNING && 2796 ifp->if_flags & IFF_PROMISC && 2797 !(sc->dc_if_flags & IFF_PROMISC)) { 2798 dc_setfilt(sc); 2799 } else if (ifp->if_flags & IFF_RUNNING && 2800 !(ifp->if_flags & IFF_PROMISC) && 2801 sc->dc_if_flags & IFF_PROMISC) { 2802 dc_setfilt(sc); 2803 } else if (!(ifp->if_flags & IFF_RUNNING)) { 2804 sc->dc_txthresh = 0; 2805 dc_init(sc); 2806 } 2807 } else { 2808 if (ifp->if_flags & IFF_RUNNING) 2809 dc_stop(sc); 2810 } 2811 sc->dc_if_flags = ifp->if_flags; 2812 error = 0; 2813 break; 2814 case SIOCADDMULTI: 2815 case SIOCDELMULTI: 2816 dc_setfilt(sc); 2817 error = 0; 2818 break; 2819 case SIOCGIFMEDIA: 2820 case SIOCSIFMEDIA: 2821 mii = device_get_softc(sc->dc_miibus); 2822 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 2823 #ifdef __alpha__ 2824 if (sc->dc_srm_media) 2825 sc->dc_srm_media = 0; 2826 #endif 2827 break; 2828 default: 2829 error = EINVAL; 2830 break; 2831 } 2832 2833 (void)splx(s); 2834 2835 return(error); 2836 } 2837 2838 static void dc_watchdog(ifp) 2839 struct ifnet *ifp; 2840 { 2841 struct dc_softc *sc; 2842 2843 sc = ifp->if_softc; 2844 2845 ifp->if_oerrors++; 2846 printf("dc%d: watchdog timeout\n", sc->dc_unit); 2847 2848 dc_stop(sc); 2849 dc_reset(sc); 2850 dc_init(sc); 2851 2852 if (ifp->if_snd.ifq_head != NULL) 2853 dc_start(ifp); 2854 2855 return; 2856 } 2857 2858 /* 2859 * Stop the adapter and free any mbufs allocated to the 2860 * RX and TX lists. 2861 */ 2862 static void dc_stop(sc) 2863 struct dc_softc *sc; 2864 { 2865 register int i; 2866 struct ifnet *ifp; 2867 2868 ifp = &sc->arpcom.ac_if; 2869 ifp->if_timer = 0; 2870 2871 untimeout(dc_tick, sc, sc->dc_stat_ch); 2872 2873 DC_CLRBIT(sc, DC_NETCFG, (DC_NETCFG_RX_ON|DC_NETCFG_TX_ON)); 2874 CSR_WRITE_4(sc, DC_IMR, 0x00000000); 2875 CSR_WRITE_4(sc, DC_TXADDR, 0x00000000); 2876 CSR_WRITE_4(sc, DC_RXADDR, 0x00000000); 2877 sc->dc_link = 0; 2878 2879 /* 2880 * Free data in the RX lists. 2881 */ 2882 for (i = 0; i < DC_RX_LIST_CNT; i++) { 2883 if (sc->dc_cdata.dc_rx_chain[i] != NULL) { 2884 m_freem(sc->dc_cdata.dc_rx_chain[i]); 2885 sc->dc_cdata.dc_rx_chain[i] = NULL; 2886 } 2887 } 2888 bzero((char *)&sc->dc_ldata->dc_rx_list, 2889 sizeof(sc->dc_ldata->dc_rx_list)); 2890 2891 /* 2892 * Free the TX list buffers. 2893 */ 2894 for (i = 0; i < DC_TX_LIST_CNT; i++) { 2895 if (sc->dc_cdata.dc_tx_chain[i] != NULL) { 2896 if (sc->dc_ldata->dc_tx_list[i].dc_ctl & 2897 DC_TXCTL_SETUP) { 2898 sc->dc_cdata.dc_tx_chain[i] = NULL; 2899 continue; 2900 } 2901 m_freem(sc->dc_cdata.dc_tx_chain[i]); 2902 sc->dc_cdata.dc_tx_chain[i] = NULL; 2903 } 2904 } 2905 2906 bzero((char *)&sc->dc_ldata->dc_tx_list, 2907 sizeof(sc->dc_ldata->dc_tx_list)); 2908 2909 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 2910 2911 return; 2912 } 2913 2914 /* 2915 * Stop all chip I/O so that the kernel's probe routines don't 2916 * get confused by errant DMAs when rebooting. 2917 */ 2918 static void dc_shutdown(dev) 2919 device_t dev; 2920 { 2921 struct dc_softc *sc; 2922 2923 sc = device_get_softc(dev); 2924 2925 dc_stop(sc); 2926 2927 return; 2928 } 2929