1 /*- 2 * Copyright (c) 1997, 1998, 1999 3 * Bill Paul <wpaul@ee.columbia.edu>. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 3. All advertising materials mentioning features or use of this software 14 * must display the following acknowledgement: 15 * This product includes software developed by Bill Paul. 16 * 4. Neither the name of the author nor the names of any co-contributors 17 * may be used to endorse or promote products derived from this software 18 * without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30 * THE POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33 #include <sys/cdefs.h> 34 __FBSDID("$FreeBSD$"); 35 36 /* 37 * DEC "tulip" clone ethernet driver. Supports the DEC/Intel 21143 38 * series chips and several workalikes including the following: 39 * 40 * Macronix 98713/98715/98725/98727/98732 PMAC (www.macronix.com) 41 * Macronix/Lite-On 82c115 PNIC II (www.macronix.com) 42 * Lite-On 82c168/82c169 PNIC (www.litecom.com) 43 * ASIX Electronics AX88140A (www.asix.com.tw) 44 * ASIX Electronics AX88141 (www.asix.com.tw) 45 * ADMtek AL981 (www.admtek.com.tw) 46 * ADMtek AN985 (www.admtek.com.tw) 47 * Netgear FA511 (www.netgear.com) Appears to be rebadged ADMTek AN985 48 * Davicom DM9100, DM9102, DM9102A (www.davicom8.com) 49 * Accton EN1217 (www.accton.com) 50 * Xircom X3201 (www.xircom.com) 51 * Abocom FE2500 52 * Conexant LANfinity (www.conexant.com) 53 * 3Com OfficeConnect 10/100B 3CSOHO100B (www.3com.com) 54 * 55 * Datasheets for the 21143 are available at developer.intel.com. 56 * Datasheets for the clone parts can be found at their respective sites. 57 * (Except for the PNIC; see www.freebsd.org/~wpaul/PNIC/pnic.ps.gz.) 58 * The PNIC II is essentially a Macronix 98715A chip; the only difference 59 * worth noting is that its multicast hash table is only 128 bits wide 60 * instead of 512. 61 * 62 * Written by Bill Paul <wpaul@ee.columbia.edu> 63 * Electrical Engineering Department 64 * Columbia University, New York City 65 */ 66 /* 67 * The Intel 21143 is the successor to the DEC 21140. It is basically 68 * the same as the 21140 but with a few new features. The 21143 supports 69 * three kinds of media attachments: 70 * 71 * o MII port, for 10Mbps and 100Mbps support and NWAY 72 * autonegotiation provided by an external PHY. 73 * o SYM port, for symbol mode 100Mbps support. 74 * o 10baseT port. 75 * o AUI/BNC port. 76 * 77 * The 100Mbps SYM port and 10baseT port can be used together in 78 * combination with the internal NWAY support to create a 10/100 79 * autosensing configuration. 80 * 81 * Note that not all tulip workalikes are handled in this driver: we only 82 * deal with those which are relatively well behaved. The Winbond is 83 * handled separately due to its different register offsets and the 84 * special handling needed for its various bugs. The PNIC is handled 85 * here, but I'm not thrilled about it. 86 * 87 * All of the workalike chips use some form of MII transceiver support 88 * with the exception of the Macronix chips, which also have a SYM port. 89 * The ASIX AX88140A is also documented to have a SYM port, but all 90 * the cards I've seen use an MII transceiver, probably because the 91 * AX88140A doesn't support internal NWAY. 92 */ 93 94 #ifdef HAVE_KERNEL_OPTION_HEADERS 95 #include "opt_device_polling.h" 96 #endif 97 98 #include <sys/param.h> 99 #include <sys/endian.h> 100 #include <sys/systm.h> 101 #include <sys/sockio.h> 102 #include <sys/mbuf.h> 103 #include <sys/malloc.h> 104 #include <sys/kernel.h> 105 #include <sys/module.h> 106 #include <sys/socket.h> 107 #include <sys/sysctl.h> 108 109 #include <net/if.h> 110 #include <net/if_arp.h> 111 #include <net/ethernet.h> 112 #include <net/if_dl.h> 113 #include <net/if_media.h> 114 #include <net/if_types.h> 115 #include <net/if_vlan_var.h> 116 117 #include <net/bpf.h> 118 119 #include <machine/bus.h> 120 #include <machine/resource.h> 121 #include <sys/bus.h> 122 #include <sys/rman.h> 123 124 #include <dev/mii/mii.h> 125 #include <dev/mii/miivar.h> 126 127 #include <dev/pci/pcireg.h> 128 #include <dev/pci/pcivar.h> 129 130 #define DC_USEIOSPACE 131 132 #include <dev/dc/if_dcreg.h> 133 134 #ifdef __sparc64__ 135 #include <dev/ofw/openfirm.h> 136 #include <machine/ofw_machdep.h> 137 #endif 138 139 MODULE_DEPEND(dc, pci, 1, 1, 1); 140 MODULE_DEPEND(dc, ether, 1, 1, 1); 141 MODULE_DEPEND(dc, miibus, 1, 1, 1); 142 143 /* 144 * "device miibus" is required in kernel config. See GENERIC if you get 145 * errors here. 146 */ 147 #include "miibus_if.h" 148 149 /* 150 * Various supported device vendors/types and their names. 151 */ 152 static struct dc_type dc_devs[] = { 153 { DC_DEVID(DC_VENDORID_DEC, DC_DEVICEID_21143), 0, 154 "Intel 21143 10/100BaseTX" }, 155 { DC_DEVID(DC_VENDORID_DAVICOM, DC_DEVICEID_DM9009), 0, 156 "Davicom DM9009 10/100BaseTX" }, 157 { DC_DEVID(DC_VENDORID_DAVICOM, DC_DEVICEID_DM9100), 0, 158 "Davicom DM9100 10/100BaseTX" }, 159 { DC_DEVID(DC_VENDORID_DAVICOM, DC_DEVICEID_DM9102), DC_REVISION_DM9102A, 160 "Davicom DM9102A 10/100BaseTX" }, 161 { DC_DEVID(DC_VENDORID_DAVICOM, DC_DEVICEID_DM9102), 0, 162 "Davicom DM9102 10/100BaseTX" }, 163 { DC_DEVID(DC_VENDORID_ADMTEK, DC_DEVICEID_AL981), 0, 164 "ADMtek AL981 10/100BaseTX" }, 165 { DC_DEVID(DC_VENDORID_ADMTEK, DC_DEVICEID_AN985), 0, 166 "ADMtek AN985 10/100BaseTX" }, 167 { DC_DEVID(DC_VENDORID_ADMTEK, DC_DEVICEID_ADM9511), 0, 168 "ADMtek ADM9511 10/100BaseTX" }, 169 { DC_DEVID(DC_VENDORID_ADMTEK, DC_DEVICEID_ADM9513), 0, 170 "ADMtek ADM9513 10/100BaseTX" }, 171 { DC_DEVID(DC_VENDORID_ADMTEK, DC_DEVICEID_FA511), 0, 172 "Netgear FA511 10/100BaseTX" }, 173 { DC_DEVID(DC_VENDORID_ASIX, DC_DEVICEID_AX88140A), DC_REVISION_88141, 174 "ASIX AX88141 10/100BaseTX" }, 175 { DC_DEVID(DC_VENDORID_ASIX, DC_DEVICEID_AX88140A), 0, 176 "ASIX AX88140A 10/100BaseTX" }, 177 { DC_DEVID(DC_VENDORID_MX, DC_DEVICEID_98713), DC_REVISION_98713A, 178 "Macronix 98713A 10/100BaseTX" }, 179 { DC_DEVID(DC_VENDORID_MX, DC_DEVICEID_98713), 0, 180 "Macronix 98713 10/100BaseTX" }, 181 { DC_DEVID(DC_VENDORID_CP, DC_DEVICEID_98713_CP), DC_REVISION_98713A, 182 "Compex RL100-TX 10/100BaseTX" }, 183 { DC_DEVID(DC_VENDORID_CP, DC_DEVICEID_98713_CP), 0, 184 "Compex RL100-TX 10/100BaseTX" }, 185 { DC_DEVID(DC_VENDORID_MX, DC_DEVICEID_987x5), DC_REVISION_98725, 186 "Macronix 98725 10/100BaseTX" }, 187 { DC_DEVID(DC_VENDORID_MX, DC_DEVICEID_987x5), DC_REVISION_98715AEC_C, 188 "Macronix 98715AEC-C 10/100BaseTX" }, 189 { DC_DEVID(DC_VENDORID_MX, DC_DEVICEID_987x5), 0, 190 "Macronix 98715/98715A 10/100BaseTX" }, 191 { DC_DEVID(DC_VENDORID_MX, DC_DEVICEID_98727), 0, 192 "Macronix 98727/98732 10/100BaseTX" }, 193 { DC_DEVID(DC_VENDORID_LO, DC_DEVICEID_82C115), 0, 194 "LC82C115 PNIC II 10/100BaseTX" }, 195 { DC_DEVID(DC_VENDORID_LO, DC_DEVICEID_82C168), DC_REVISION_82C169, 196 "82c169 PNIC 10/100BaseTX" }, 197 { DC_DEVID(DC_VENDORID_LO, DC_DEVICEID_82C168), 0, 198 "82c168 PNIC 10/100BaseTX" }, 199 { DC_DEVID(DC_VENDORID_ACCTON, DC_DEVICEID_EN1217), 0, 200 "Accton EN1217 10/100BaseTX" }, 201 { DC_DEVID(DC_VENDORID_ACCTON, DC_DEVICEID_EN2242), 0, 202 "Accton EN2242 MiniPCI 10/100BaseTX" }, 203 { DC_DEVID(DC_VENDORID_XIRCOM, DC_DEVICEID_X3201), 0, 204 "Xircom X3201 10/100BaseTX" }, 205 { DC_DEVID(DC_VENDORID_DLINK, DC_DEVICEID_DRP32TXD), 0, 206 "Neteasy DRP-32TXD Cardbus 10/100" }, 207 { DC_DEVID(DC_VENDORID_ABOCOM, DC_DEVICEID_FE2500), 0, 208 "Abocom FE2500 10/100BaseTX" }, 209 { DC_DEVID(DC_VENDORID_ABOCOM, DC_DEVICEID_FE2500MX), 0, 210 "Abocom FE2500MX 10/100BaseTX" }, 211 { DC_DEVID(DC_VENDORID_CONEXANT, DC_DEVICEID_RS7112), 0, 212 "Conexant LANfinity MiniPCI 10/100BaseTX" }, 213 { DC_DEVID(DC_VENDORID_HAWKING, DC_DEVICEID_HAWKING_PN672TX), 0, 214 "Hawking CB102 CardBus 10/100" }, 215 { DC_DEVID(DC_VENDORID_PLANEX, DC_DEVICEID_FNW3602T), 0, 216 "PlaneX FNW-3602-T CardBus 10/100" }, 217 { DC_DEVID(DC_VENDORID_3COM, DC_DEVICEID_3CSOHOB), 0, 218 "3Com OfficeConnect 10/100B" }, 219 { DC_DEVID(DC_VENDORID_MICROSOFT, DC_DEVICEID_MSMN120), 0, 220 "Microsoft MN-120 CardBus 10/100" }, 221 { DC_DEVID(DC_VENDORID_MICROSOFT, DC_DEVICEID_MSMN130), 0, 222 "Microsoft MN-130 10/100" }, 223 { DC_DEVID(DC_VENDORID_LINKSYS, DC_DEVICEID_PCMPC200_AB08), 0, 224 "Linksys PCMPC200 CardBus 10/100" }, 225 { DC_DEVID(DC_VENDORID_LINKSYS, DC_DEVICEID_PCMPC200_AB09), 0, 226 "Linksys PCMPC200 CardBus 10/100" }, 227 { 0, 0, NULL } 228 }; 229 230 static int dc_probe(device_t); 231 static int dc_attach(device_t); 232 static int dc_detach(device_t); 233 static int dc_suspend(device_t); 234 static int dc_resume(device_t); 235 static struct dc_type *dc_devtype(device_t); 236 static int dc_newbuf(struct dc_softc *, int, int); 237 static int dc_encap(struct dc_softc *, struct mbuf **); 238 static void dc_pnic_rx_bug_war(struct dc_softc *, int); 239 static int dc_rx_resync(struct dc_softc *); 240 static void dc_rxeof(struct dc_softc *); 241 static void dc_txeof(struct dc_softc *); 242 static void dc_tick(void *); 243 static void dc_tx_underrun(struct dc_softc *); 244 static void dc_intr(void *); 245 static void dc_start(struct ifnet *); 246 static void dc_start_locked(struct ifnet *); 247 static int dc_ioctl(struct ifnet *, u_long, caddr_t); 248 static void dc_init(void *); 249 static void dc_init_locked(struct dc_softc *); 250 static void dc_stop(struct dc_softc *); 251 static void dc_watchdog(struct ifnet *); 252 static void dc_shutdown(device_t); 253 static int dc_ifmedia_upd(struct ifnet *); 254 static void dc_ifmedia_sts(struct ifnet *, struct ifmediareq *); 255 256 static void dc_delay(struct dc_softc *); 257 static void dc_eeprom_idle(struct dc_softc *); 258 static void dc_eeprom_putbyte(struct dc_softc *, int); 259 static void dc_eeprom_getword(struct dc_softc *, int, u_int16_t *); 260 static void dc_eeprom_getword_pnic(struct dc_softc *, int, u_int16_t *); 261 static void dc_eeprom_getword_xircom(struct dc_softc *, int, u_int16_t *); 262 static void dc_eeprom_width(struct dc_softc *); 263 static void dc_read_eeprom(struct dc_softc *, caddr_t, int, int, int); 264 265 static void dc_mii_writebit(struct dc_softc *, int); 266 static int dc_mii_readbit(struct dc_softc *); 267 static void dc_mii_sync(struct dc_softc *); 268 static void dc_mii_send(struct dc_softc *, u_int32_t, int); 269 static int dc_mii_readreg(struct dc_softc *, struct dc_mii_frame *); 270 static int dc_mii_writereg(struct dc_softc *, struct dc_mii_frame *); 271 static int dc_miibus_readreg(device_t, int, int); 272 static int dc_miibus_writereg(device_t, int, int, int); 273 static void dc_miibus_statchg(device_t); 274 static void dc_miibus_mediainit(device_t); 275 276 static void dc_setcfg(struct dc_softc *, int); 277 static uint32_t dc_mchash_le(struct dc_softc *, const uint8_t *); 278 static uint32_t dc_mchash_be(const uint8_t *); 279 static void dc_setfilt_21143(struct dc_softc *); 280 static void dc_setfilt_asix(struct dc_softc *); 281 static void dc_setfilt_admtek(struct dc_softc *); 282 static void dc_setfilt_xircom(struct dc_softc *); 283 284 static void dc_setfilt(struct dc_softc *); 285 286 static void dc_reset(struct dc_softc *); 287 static int dc_list_rx_init(struct dc_softc *); 288 static int dc_list_tx_init(struct dc_softc *); 289 290 static void dc_read_srom(struct dc_softc *, int); 291 static void dc_parse_21143_srom(struct dc_softc *); 292 static void dc_decode_leaf_sia(struct dc_softc *, struct dc_eblock_sia *); 293 static void dc_decode_leaf_mii(struct dc_softc *, struct dc_eblock_mii *); 294 static void dc_decode_leaf_sym(struct dc_softc *, struct dc_eblock_sym *); 295 static void dc_apply_fixup(struct dc_softc *, int); 296 297 static void dc_dma_map_txbuf(void *, bus_dma_segment_t *, int, bus_size_t, int); 298 static void dc_dma_map_rxbuf(void *, bus_dma_segment_t *, int, bus_size_t, int); 299 300 #ifdef DC_USEIOSPACE 301 #define DC_RES SYS_RES_IOPORT 302 #define DC_RID DC_PCI_CFBIO 303 #else 304 #define DC_RES SYS_RES_MEMORY 305 #define DC_RID DC_PCI_CFBMA 306 #endif 307 308 static device_method_t dc_methods[] = { 309 /* Device interface */ 310 DEVMETHOD(device_probe, dc_probe), 311 DEVMETHOD(device_attach, dc_attach), 312 DEVMETHOD(device_detach, dc_detach), 313 DEVMETHOD(device_suspend, dc_suspend), 314 DEVMETHOD(device_resume, dc_resume), 315 DEVMETHOD(device_shutdown, dc_shutdown), 316 317 /* bus interface */ 318 DEVMETHOD(bus_print_child, bus_generic_print_child), 319 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 320 321 /* MII interface */ 322 DEVMETHOD(miibus_readreg, dc_miibus_readreg), 323 DEVMETHOD(miibus_writereg, dc_miibus_writereg), 324 DEVMETHOD(miibus_statchg, dc_miibus_statchg), 325 DEVMETHOD(miibus_mediainit, dc_miibus_mediainit), 326 327 { 0, 0 } 328 }; 329 330 static driver_t dc_driver = { 331 "dc", 332 dc_methods, 333 sizeof(struct dc_softc) 334 }; 335 336 static devclass_t dc_devclass; 337 #ifdef __i386__ 338 static int dc_quick = 1; 339 SYSCTL_INT(_hw, OID_AUTO, dc_quick, CTLFLAG_RW, &dc_quick, 0, 340 "do not m_devget() in dc driver"); 341 #endif 342 343 DRIVER_MODULE(dc, cardbus, dc_driver, dc_devclass, 0, 0); 344 DRIVER_MODULE(dc, pci, dc_driver, dc_devclass, 0, 0); 345 DRIVER_MODULE(miibus, dc, miibus_driver, miibus_devclass, 0, 0); 346 347 #define DC_SETBIT(sc, reg, x) \ 348 CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) | (x)) 349 350 #define DC_CLRBIT(sc, reg, x) \ 351 CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) & ~(x)) 352 353 #define SIO_SET(x) DC_SETBIT(sc, DC_SIO, (x)) 354 #define SIO_CLR(x) DC_CLRBIT(sc, DC_SIO, (x)) 355 356 static void 357 dc_delay(struct dc_softc *sc) 358 { 359 int idx; 360 361 for (idx = (300 / 33) + 1; idx > 0; idx--) 362 CSR_READ_4(sc, DC_BUSCTL); 363 } 364 365 static void 366 dc_eeprom_width(struct dc_softc *sc) 367 { 368 int i; 369 370 /* Force EEPROM to idle state. */ 371 dc_eeprom_idle(sc); 372 373 /* Enter EEPROM access mode. */ 374 CSR_WRITE_4(sc, DC_SIO, DC_SIO_EESEL); 375 dc_delay(sc); 376 DC_SETBIT(sc, DC_SIO, DC_SIO_ROMCTL_READ); 377 dc_delay(sc); 378 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); 379 dc_delay(sc); 380 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CS); 381 dc_delay(sc); 382 383 for (i = 3; i--;) { 384 if (6 & (1 << i)) 385 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_DATAIN); 386 else 387 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_DATAIN); 388 dc_delay(sc); 389 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CLK); 390 dc_delay(sc); 391 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); 392 dc_delay(sc); 393 } 394 395 for (i = 1; i <= 12; i++) { 396 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CLK); 397 dc_delay(sc); 398 if (!(CSR_READ_4(sc, DC_SIO) & DC_SIO_EE_DATAOUT)) { 399 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); 400 dc_delay(sc); 401 break; 402 } 403 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); 404 dc_delay(sc); 405 } 406 407 /* Turn off EEPROM access mode. */ 408 dc_eeprom_idle(sc); 409 410 if (i < 4 || i > 12) 411 sc->dc_romwidth = 6; 412 else 413 sc->dc_romwidth = i; 414 415 /* Enter EEPROM access mode. */ 416 CSR_WRITE_4(sc, DC_SIO, DC_SIO_EESEL); 417 dc_delay(sc); 418 DC_SETBIT(sc, DC_SIO, DC_SIO_ROMCTL_READ); 419 dc_delay(sc); 420 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); 421 dc_delay(sc); 422 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CS); 423 dc_delay(sc); 424 425 /* Turn off EEPROM access mode. */ 426 dc_eeprom_idle(sc); 427 } 428 429 static void 430 dc_eeprom_idle(struct dc_softc *sc) 431 { 432 int i; 433 434 CSR_WRITE_4(sc, DC_SIO, DC_SIO_EESEL); 435 dc_delay(sc); 436 DC_SETBIT(sc, DC_SIO, DC_SIO_ROMCTL_READ); 437 dc_delay(sc); 438 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); 439 dc_delay(sc); 440 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CS); 441 dc_delay(sc); 442 443 for (i = 0; i < 25; i++) { 444 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); 445 dc_delay(sc); 446 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CLK); 447 dc_delay(sc); 448 } 449 450 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); 451 dc_delay(sc); 452 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CS); 453 dc_delay(sc); 454 CSR_WRITE_4(sc, DC_SIO, 0x00000000); 455 } 456 457 /* 458 * Send a read command and address to the EEPROM, check for ACK. 459 */ 460 static void 461 dc_eeprom_putbyte(struct dc_softc *sc, int addr) 462 { 463 int d, i; 464 465 d = DC_EECMD_READ >> 6; 466 for (i = 3; i--; ) { 467 if (d & (1 << i)) 468 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_DATAIN); 469 else 470 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_DATAIN); 471 dc_delay(sc); 472 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CLK); 473 dc_delay(sc); 474 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); 475 dc_delay(sc); 476 } 477 478 /* 479 * Feed in each bit and strobe the clock. 480 */ 481 for (i = sc->dc_romwidth; i--;) { 482 if (addr & (1 << i)) { 483 SIO_SET(DC_SIO_EE_DATAIN); 484 } else { 485 SIO_CLR(DC_SIO_EE_DATAIN); 486 } 487 dc_delay(sc); 488 SIO_SET(DC_SIO_EE_CLK); 489 dc_delay(sc); 490 SIO_CLR(DC_SIO_EE_CLK); 491 dc_delay(sc); 492 } 493 } 494 495 /* 496 * Read a word of data stored in the EEPROM at address 'addr.' 497 * The PNIC 82c168/82c169 has its own non-standard way to read 498 * the EEPROM. 499 */ 500 static void 501 dc_eeprom_getword_pnic(struct dc_softc *sc, int addr, u_int16_t *dest) 502 { 503 int i; 504 u_int32_t r; 505 506 CSR_WRITE_4(sc, DC_PN_SIOCTL, DC_PN_EEOPCODE_READ | addr); 507 508 for (i = 0; i < DC_TIMEOUT; i++) { 509 DELAY(1); 510 r = CSR_READ_4(sc, DC_SIO); 511 if (!(r & DC_PN_SIOCTL_BUSY)) { 512 *dest = (u_int16_t)(r & 0xFFFF); 513 return; 514 } 515 } 516 } 517 518 /* 519 * Read a word of data stored in the EEPROM at address 'addr.' 520 * The Xircom X3201 has its own non-standard way to read 521 * the EEPROM, too. 522 */ 523 static void 524 dc_eeprom_getword_xircom(struct dc_softc *sc, int addr, u_int16_t *dest) 525 { 526 527 SIO_SET(DC_SIO_ROMSEL | DC_SIO_ROMCTL_READ); 528 529 addr *= 2; 530 CSR_WRITE_4(sc, DC_ROM, addr | 0x160); 531 *dest = (u_int16_t)CSR_READ_4(sc, DC_SIO) & 0xff; 532 addr += 1; 533 CSR_WRITE_4(sc, DC_ROM, addr | 0x160); 534 *dest |= ((u_int16_t)CSR_READ_4(sc, DC_SIO) & 0xff) << 8; 535 536 SIO_CLR(DC_SIO_ROMSEL | DC_SIO_ROMCTL_READ); 537 } 538 539 /* 540 * Read a word of data stored in the EEPROM at address 'addr.' 541 */ 542 static void 543 dc_eeprom_getword(struct dc_softc *sc, int addr, u_int16_t *dest) 544 { 545 int i; 546 u_int16_t word = 0; 547 548 /* Force EEPROM to idle state. */ 549 dc_eeprom_idle(sc); 550 551 /* Enter EEPROM access mode. */ 552 CSR_WRITE_4(sc, DC_SIO, DC_SIO_EESEL); 553 dc_delay(sc); 554 DC_SETBIT(sc, DC_SIO, DC_SIO_ROMCTL_READ); 555 dc_delay(sc); 556 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); 557 dc_delay(sc); 558 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CS); 559 dc_delay(sc); 560 561 /* 562 * Send address of word we want to read. 563 */ 564 dc_eeprom_putbyte(sc, addr); 565 566 /* 567 * Start reading bits from EEPROM. 568 */ 569 for (i = 0x8000; i; i >>= 1) { 570 SIO_SET(DC_SIO_EE_CLK); 571 dc_delay(sc); 572 if (CSR_READ_4(sc, DC_SIO) & DC_SIO_EE_DATAOUT) 573 word |= i; 574 dc_delay(sc); 575 SIO_CLR(DC_SIO_EE_CLK); 576 dc_delay(sc); 577 } 578 579 /* Turn off EEPROM access mode. */ 580 dc_eeprom_idle(sc); 581 582 *dest = word; 583 } 584 585 /* 586 * Read a sequence of words from the EEPROM. 587 */ 588 static void 589 dc_read_eeprom(struct dc_softc *sc, caddr_t dest, int off, int cnt, int be) 590 { 591 int i; 592 u_int16_t word = 0, *ptr; 593 594 for (i = 0; i < cnt; i++) { 595 if (DC_IS_PNIC(sc)) 596 dc_eeprom_getword_pnic(sc, off + i, &word); 597 else if (DC_IS_XIRCOM(sc)) 598 dc_eeprom_getword_xircom(sc, off + i, &word); 599 else 600 dc_eeprom_getword(sc, off + i, &word); 601 ptr = (u_int16_t *)(dest + (i * 2)); 602 if (be) 603 *ptr = be16toh(word); 604 else 605 *ptr = le16toh(word); 606 } 607 } 608 609 /* 610 * The following two routines are taken from the Macronix 98713 611 * Application Notes pp.19-21. 612 */ 613 /* 614 * Write a bit to the MII bus. 615 */ 616 static void 617 dc_mii_writebit(struct dc_softc *sc, int bit) 618 { 619 620 if (bit) 621 CSR_WRITE_4(sc, DC_SIO, 622 DC_SIO_ROMCTL_WRITE | DC_SIO_MII_DATAOUT); 623 else 624 CSR_WRITE_4(sc, DC_SIO, DC_SIO_ROMCTL_WRITE); 625 626 DC_SETBIT(sc, DC_SIO, DC_SIO_MII_CLK); 627 DC_CLRBIT(sc, DC_SIO, DC_SIO_MII_CLK); 628 } 629 630 /* 631 * Read a bit from the MII bus. 632 */ 633 static int 634 dc_mii_readbit(struct dc_softc *sc) 635 { 636 637 CSR_WRITE_4(sc, DC_SIO, DC_SIO_ROMCTL_READ | DC_SIO_MII_DIR); 638 CSR_READ_4(sc, DC_SIO); 639 DC_SETBIT(sc, DC_SIO, DC_SIO_MII_CLK); 640 DC_CLRBIT(sc, DC_SIO, DC_SIO_MII_CLK); 641 if (CSR_READ_4(sc, DC_SIO) & DC_SIO_MII_DATAIN) 642 return (1); 643 644 return (0); 645 } 646 647 /* 648 * Sync the PHYs by setting data bit and strobing the clock 32 times. 649 */ 650 static void 651 dc_mii_sync(struct dc_softc *sc) 652 { 653 int i; 654 655 CSR_WRITE_4(sc, DC_SIO, DC_SIO_ROMCTL_WRITE); 656 657 for (i = 0; i < 32; i++) 658 dc_mii_writebit(sc, 1); 659 } 660 661 /* 662 * Clock a series of bits through the MII. 663 */ 664 static void 665 dc_mii_send(struct dc_softc *sc, u_int32_t bits, int cnt) 666 { 667 int i; 668 669 for (i = (0x1 << (cnt - 1)); i; i >>= 1) 670 dc_mii_writebit(sc, bits & i); 671 } 672 673 /* 674 * Read an PHY register through the MII. 675 */ 676 static int 677 dc_mii_readreg(struct dc_softc *sc, struct dc_mii_frame *frame) 678 { 679 int i, ack; 680 681 /* 682 * Set up frame for RX. 683 */ 684 frame->mii_stdelim = DC_MII_STARTDELIM; 685 frame->mii_opcode = DC_MII_READOP; 686 frame->mii_turnaround = 0; 687 frame->mii_data = 0; 688 689 /* 690 * Sync the PHYs. 691 */ 692 dc_mii_sync(sc); 693 694 /* 695 * Send command/address info. 696 */ 697 dc_mii_send(sc, frame->mii_stdelim, 2); 698 dc_mii_send(sc, frame->mii_opcode, 2); 699 dc_mii_send(sc, frame->mii_phyaddr, 5); 700 dc_mii_send(sc, frame->mii_regaddr, 5); 701 702 #ifdef notdef 703 /* Idle bit */ 704 dc_mii_writebit(sc, 1); 705 dc_mii_writebit(sc, 0); 706 #endif 707 708 /* Check for ack. */ 709 ack = dc_mii_readbit(sc); 710 711 /* 712 * Now try reading data bits. If the ack failed, we still 713 * need to clock through 16 cycles to keep the PHY(s) in sync. 714 */ 715 if (ack) { 716 for (i = 0; i < 16; i++) 717 dc_mii_readbit(sc); 718 goto fail; 719 } 720 721 for (i = 0x8000; i; i >>= 1) { 722 if (!ack) { 723 if (dc_mii_readbit(sc)) 724 frame->mii_data |= i; 725 } 726 } 727 728 fail: 729 730 dc_mii_writebit(sc, 0); 731 dc_mii_writebit(sc, 0); 732 733 if (ack) 734 return (1); 735 return (0); 736 } 737 738 /* 739 * Write to a PHY register through the MII. 740 */ 741 static int 742 dc_mii_writereg(struct dc_softc *sc, struct dc_mii_frame *frame) 743 { 744 745 /* 746 * Set up frame for TX. 747 */ 748 749 frame->mii_stdelim = DC_MII_STARTDELIM; 750 frame->mii_opcode = DC_MII_WRITEOP; 751 frame->mii_turnaround = DC_MII_TURNAROUND; 752 753 /* 754 * Sync the PHYs. 755 */ 756 dc_mii_sync(sc); 757 758 dc_mii_send(sc, frame->mii_stdelim, 2); 759 dc_mii_send(sc, frame->mii_opcode, 2); 760 dc_mii_send(sc, frame->mii_phyaddr, 5); 761 dc_mii_send(sc, frame->mii_regaddr, 5); 762 dc_mii_send(sc, frame->mii_turnaround, 2); 763 dc_mii_send(sc, frame->mii_data, 16); 764 765 /* Idle bit. */ 766 dc_mii_writebit(sc, 0); 767 dc_mii_writebit(sc, 0); 768 769 return (0); 770 } 771 772 static int 773 dc_miibus_readreg(device_t dev, int phy, int reg) 774 { 775 struct dc_mii_frame frame; 776 struct dc_softc *sc; 777 int i, rval, phy_reg = 0; 778 779 sc = device_get_softc(dev); 780 bzero(&frame, sizeof(frame)); 781 782 /* 783 * Note: both the AL981 and AN985 have internal PHYs, 784 * however the AL981 provides direct access to the PHY 785 * registers while the AN985 uses a serial MII interface. 786 * The AN985's MII interface is also buggy in that you 787 * can read from any MII address (0 to 31), but only address 1 788 * behaves normally. To deal with both cases, we pretend 789 * that the PHY is at MII address 1. 790 */ 791 if (DC_IS_ADMTEK(sc) && phy != DC_ADMTEK_PHYADDR) 792 return (0); 793 794 /* 795 * Note: the ukphy probes of the RS7112 report a PHY at 796 * MII address 0 (possibly HomePNA?) and 1 (ethernet) 797 * so we only respond to correct one. 798 */ 799 if (DC_IS_CONEXANT(sc) && phy != DC_CONEXANT_PHYADDR) 800 return (0); 801 802 if (sc->dc_pmode != DC_PMODE_MII) { 803 if (phy == (MII_NPHY - 1)) { 804 switch (reg) { 805 case MII_BMSR: 806 /* 807 * Fake something to make the probe 808 * code think there's a PHY here. 809 */ 810 return (BMSR_MEDIAMASK); 811 break; 812 case MII_PHYIDR1: 813 if (DC_IS_PNIC(sc)) 814 return (DC_VENDORID_LO); 815 return (DC_VENDORID_DEC); 816 break; 817 case MII_PHYIDR2: 818 if (DC_IS_PNIC(sc)) 819 return (DC_DEVICEID_82C168); 820 return (DC_DEVICEID_21143); 821 break; 822 default: 823 return (0); 824 break; 825 } 826 } else 827 return (0); 828 } 829 830 if (DC_IS_PNIC(sc)) { 831 CSR_WRITE_4(sc, DC_PN_MII, DC_PN_MIIOPCODE_READ | 832 (phy << 23) | (reg << 18)); 833 for (i = 0; i < DC_TIMEOUT; i++) { 834 DELAY(1); 835 rval = CSR_READ_4(sc, DC_PN_MII); 836 if (!(rval & DC_PN_MII_BUSY)) { 837 rval &= 0xFFFF; 838 return (rval == 0xFFFF ? 0 : rval); 839 } 840 } 841 return (0); 842 } 843 844 if (DC_IS_COMET(sc)) { 845 switch (reg) { 846 case MII_BMCR: 847 phy_reg = DC_AL_BMCR; 848 break; 849 case MII_BMSR: 850 phy_reg = DC_AL_BMSR; 851 break; 852 case MII_PHYIDR1: 853 phy_reg = DC_AL_VENID; 854 break; 855 case MII_PHYIDR2: 856 phy_reg = DC_AL_DEVID; 857 break; 858 case MII_ANAR: 859 phy_reg = DC_AL_ANAR; 860 break; 861 case MII_ANLPAR: 862 phy_reg = DC_AL_LPAR; 863 break; 864 case MII_ANER: 865 phy_reg = DC_AL_ANER; 866 break; 867 default: 868 device_printf(dev, "phy_read: bad phy register %x\n", 869 reg); 870 return (0); 871 break; 872 } 873 874 rval = CSR_READ_4(sc, phy_reg) & 0x0000FFFF; 875 876 if (rval == 0xFFFF) 877 return (0); 878 return (rval); 879 } 880 881 frame.mii_phyaddr = phy; 882 frame.mii_regaddr = reg; 883 if (sc->dc_type == DC_TYPE_98713) { 884 phy_reg = CSR_READ_4(sc, DC_NETCFG); 885 CSR_WRITE_4(sc, DC_NETCFG, phy_reg & ~DC_NETCFG_PORTSEL); 886 } 887 dc_mii_readreg(sc, &frame); 888 if (sc->dc_type == DC_TYPE_98713) 889 CSR_WRITE_4(sc, DC_NETCFG, phy_reg); 890 891 return (frame.mii_data); 892 } 893 894 static int 895 dc_miibus_writereg(device_t dev, int phy, int reg, int data) 896 { 897 struct dc_softc *sc; 898 struct dc_mii_frame frame; 899 int i, phy_reg = 0; 900 901 sc = device_get_softc(dev); 902 bzero(&frame, sizeof(frame)); 903 904 if (DC_IS_ADMTEK(sc) && phy != DC_ADMTEK_PHYADDR) 905 return (0); 906 907 if (DC_IS_CONEXANT(sc) && phy != DC_CONEXANT_PHYADDR) 908 return (0); 909 910 if (DC_IS_PNIC(sc)) { 911 CSR_WRITE_4(sc, DC_PN_MII, DC_PN_MIIOPCODE_WRITE | 912 (phy << 23) | (reg << 10) | data); 913 for (i = 0; i < DC_TIMEOUT; i++) { 914 if (!(CSR_READ_4(sc, DC_PN_MII) & DC_PN_MII_BUSY)) 915 break; 916 } 917 return (0); 918 } 919 920 if (DC_IS_COMET(sc)) { 921 switch (reg) { 922 case MII_BMCR: 923 phy_reg = DC_AL_BMCR; 924 break; 925 case MII_BMSR: 926 phy_reg = DC_AL_BMSR; 927 break; 928 case MII_PHYIDR1: 929 phy_reg = DC_AL_VENID; 930 break; 931 case MII_PHYIDR2: 932 phy_reg = DC_AL_DEVID; 933 break; 934 case MII_ANAR: 935 phy_reg = DC_AL_ANAR; 936 break; 937 case MII_ANLPAR: 938 phy_reg = DC_AL_LPAR; 939 break; 940 case MII_ANER: 941 phy_reg = DC_AL_ANER; 942 break; 943 default: 944 device_printf(dev, "phy_write: bad phy register %x\n", 945 reg); 946 return (0); 947 break; 948 } 949 950 CSR_WRITE_4(sc, phy_reg, data); 951 return (0); 952 } 953 954 frame.mii_phyaddr = phy; 955 frame.mii_regaddr = reg; 956 frame.mii_data = data; 957 958 if (sc->dc_type == DC_TYPE_98713) { 959 phy_reg = CSR_READ_4(sc, DC_NETCFG); 960 CSR_WRITE_4(sc, DC_NETCFG, phy_reg & ~DC_NETCFG_PORTSEL); 961 } 962 dc_mii_writereg(sc, &frame); 963 if (sc->dc_type == DC_TYPE_98713) 964 CSR_WRITE_4(sc, DC_NETCFG, phy_reg); 965 966 return (0); 967 } 968 969 static void 970 dc_miibus_statchg(device_t dev) 971 { 972 struct dc_softc *sc; 973 struct mii_data *mii; 974 struct ifmedia *ifm; 975 976 sc = device_get_softc(dev); 977 if (DC_IS_ADMTEK(sc)) 978 return; 979 980 mii = device_get_softc(sc->dc_miibus); 981 ifm = &mii->mii_media; 982 if (DC_IS_DAVICOM(sc) && 983 IFM_SUBTYPE(ifm->ifm_media) == IFM_HPNA_1) { 984 dc_setcfg(sc, ifm->ifm_media); 985 sc->dc_if_media = ifm->ifm_media; 986 } else { 987 dc_setcfg(sc, mii->mii_media_active); 988 sc->dc_if_media = mii->mii_media_active; 989 } 990 } 991 992 /* 993 * Special support for DM9102A cards with HomePNA PHYs. Note: 994 * with the Davicom DM9102A/DM9801 eval board that I have, it seems 995 * to be impossible to talk to the management interface of the DM9801 996 * PHY (its MDIO pin is not connected to anything). Consequently, 997 * the driver has to just 'know' about the additional mode and deal 998 * with it itself. *sigh* 999 */ 1000 static void 1001 dc_miibus_mediainit(device_t dev) 1002 { 1003 struct dc_softc *sc; 1004 struct mii_data *mii; 1005 struct ifmedia *ifm; 1006 int rev; 1007 1008 rev = pci_get_revid(dev); 1009 1010 sc = device_get_softc(dev); 1011 mii = device_get_softc(sc->dc_miibus); 1012 ifm = &mii->mii_media; 1013 1014 if (DC_IS_DAVICOM(sc) && rev >= DC_REVISION_DM9102A) 1015 ifmedia_add(ifm, IFM_ETHER | IFM_HPNA_1, 0, NULL); 1016 } 1017 1018 #define DC_BITS_512 9 1019 #define DC_BITS_128 7 1020 #define DC_BITS_64 6 1021 1022 static uint32_t 1023 dc_mchash_le(struct dc_softc *sc, const uint8_t *addr) 1024 { 1025 uint32_t crc; 1026 1027 /* Compute CRC for the address value. */ 1028 crc = ether_crc32_le(addr, ETHER_ADDR_LEN); 1029 1030 /* 1031 * The hash table on the PNIC II and the MX98715AEC-C/D/E 1032 * chips is only 128 bits wide. 1033 */ 1034 if (sc->dc_flags & DC_128BIT_HASH) 1035 return (crc & ((1 << DC_BITS_128) - 1)); 1036 1037 /* The hash table on the MX98715BEC is only 64 bits wide. */ 1038 if (sc->dc_flags & DC_64BIT_HASH) 1039 return (crc & ((1 << DC_BITS_64) - 1)); 1040 1041 /* Xircom's hash filtering table is different (read: weird) */ 1042 /* Xircom uses the LEAST significant bits */ 1043 if (DC_IS_XIRCOM(sc)) { 1044 if ((crc & 0x180) == 0x180) 1045 return ((crc & 0x0F) + (crc & 0x70) * 3 + (14 << 4)); 1046 else 1047 return ((crc & 0x1F) + ((crc >> 1) & 0xF0) * 3 + 1048 (12 << 4)); 1049 } 1050 1051 return (crc & ((1 << DC_BITS_512) - 1)); 1052 } 1053 1054 /* 1055 * Calculate CRC of a multicast group address, return the lower 6 bits. 1056 */ 1057 static uint32_t 1058 dc_mchash_be(const uint8_t *addr) 1059 { 1060 uint32_t crc; 1061 1062 /* Compute CRC for the address value. */ 1063 crc = ether_crc32_be(addr, ETHER_ADDR_LEN); 1064 1065 /* Return the filter bit position. */ 1066 return ((crc >> 26) & 0x0000003F); 1067 } 1068 1069 /* 1070 * 21143-style RX filter setup routine. Filter programming is done by 1071 * downloading a special setup frame into the TX engine. 21143, Macronix, 1072 * PNIC, PNIC II and Davicom chips are programmed this way. 1073 * 1074 * We always program the chip using 'hash perfect' mode, i.e. one perfect 1075 * address (our node address) and a 512-bit hash filter for multicast 1076 * frames. We also sneak the broadcast address into the hash filter since 1077 * we need that too. 1078 */ 1079 static void 1080 dc_setfilt_21143(struct dc_softc *sc) 1081 { 1082 uint16_t eaddr[(ETHER_ADDR_LEN+1)/2]; 1083 struct dc_desc *sframe; 1084 u_int32_t h, *sp; 1085 struct ifmultiaddr *ifma; 1086 struct ifnet *ifp; 1087 int i; 1088 1089 ifp = sc->dc_ifp; 1090 1091 i = sc->dc_cdata.dc_tx_prod; 1092 DC_INC(sc->dc_cdata.dc_tx_prod, DC_TX_LIST_CNT); 1093 sc->dc_cdata.dc_tx_cnt++; 1094 sframe = &sc->dc_ldata->dc_tx_list[i]; 1095 sp = sc->dc_cdata.dc_sbuf; 1096 bzero(sp, DC_SFRAME_LEN); 1097 1098 sframe->dc_data = htole32(sc->dc_saddr); 1099 sframe->dc_ctl = htole32(DC_SFRAME_LEN | DC_TXCTL_SETUP | 1100 DC_TXCTL_TLINK | DC_FILTER_HASHPERF | DC_TXCTL_FINT); 1101 1102 sc->dc_cdata.dc_tx_chain[i] = (struct mbuf *)sc->dc_cdata.dc_sbuf; 1103 1104 /* If we want promiscuous mode, set the allframes bit. */ 1105 if (ifp->if_flags & IFF_PROMISC) 1106 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC); 1107 else 1108 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC); 1109 1110 if (ifp->if_flags & IFF_ALLMULTI) 1111 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI); 1112 else 1113 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI); 1114 1115 IF_ADDR_LOCK(ifp); 1116 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 1117 if (ifma->ifma_addr->sa_family != AF_LINK) 1118 continue; 1119 h = dc_mchash_le(sc, 1120 LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 1121 sp[h >> 4] |= htole32(1 << (h & 0xF)); 1122 } 1123 IF_ADDR_UNLOCK(ifp); 1124 1125 if (ifp->if_flags & IFF_BROADCAST) { 1126 h = dc_mchash_le(sc, ifp->if_broadcastaddr); 1127 sp[h >> 4] |= htole32(1 << (h & 0xF)); 1128 } 1129 1130 /* Set our MAC address. */ 1131 bcopy(IF_LLADDR(sc->dc_ifp), eaddr, ETHER_ADDR_LEN); 1132 sp[39] = DC_SP_MAC(eaddr[0]); 1133 sp[40] = DC_SP_MAC(eaddr[1]); 1134 sp[41] = DC_SP_MAC(eaddr[2]); 1135 1136 sframe->dc_status = htole32(DC_TXSTAT_OWN); 1137 CSR_WRITE_4(sc, DC_TXSTART, 0xFFFFFFFF); 1138 1139 /* 1140 * The PNIC takes an exceedingly long time to process its 1141 * setup frame; wait 10ms after posting the setup frame 1142 * before proceeding, just so it has time to swallow its 1143 * medicine. 1144 */ 1145 DELAY(10000); 1146 1147 ifp->if_timer = 5; 1148 } 1149 1150 static void 1151 dc_setfilt_admtek(struct dc_softc *sc) 1152 { 1153 uint32_t eaddr[(ETHER_ADDR_LEN+3)/4]; 1154 struct ifnet *ifp; 1155 struct ifmultiaddr *ifma; 1156 int h = 0; 1157 u_int32_t hashes[2] = { 0, 0 }; 1158 1159 ifp = sc->dc_ifp; 1160 1161 /* Init our MAC address. */ 1162 bcopy(IF_LLADDR(sc->dc_ifp), eaddr, ETHER_ADDR_LEN); 1163 CSR_WRITE_4(sc, DC_AL_PAR0, eaddr[0]); 1164 CSR_WRITE_4(sc, DC_AL_PAR1, eaddr[1]); 1165 1166 /* If we want promiscuous mode, set the allframes bit. */ 1167 if (ifp->if_flags & IFF_PROMISC) 1168 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC); 1169 else 1170 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC); 1171 1172 if (ifp->if_flags & IFF_ALLMULTI) 1173 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI); 1174 else 1175 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI); 1176 1177 /* First, zot all the existing hash bits. */ 1178 CSR_WRITE_4(sc, DC_AL_MAR0, 0); 1179 CSR_WRITE_4(sc, DC_AL_MAR1, 0); 1180 1181 /* 1182 * If we're already in promisc or allmulti mode, we 1183 * don't have to bother programming the multicast filter. 1184 */ 1185 if (ifp->if_flags & (IFF_PROMISC | IFF_ALLMULTI)) 1186 return; 1187 1188 /* Now program new ones. */ 1189 IF_ADDR_LOCK(ifp); 1190 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 1191 if (ifma->ifma_addr->sa_family != AF_LINK) 1192 continue; 1193 if (DC_IS_CENTAUR(sc)) 1194 h = dc_mchash_le(sc, 1195 LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 1196 else 1197 h = dc_mchash_be( 1198 LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 1199 if (h < 32) 1200 hashes[0] |= (1 << h); 1201 else 1202 hashes[1] |= (1 << (h - 32)); 1203 } 1204 IF_ADDR_UNLOCK(ifp); 1205 1206 CSR_WRITE_4(sc, DC_AL_MAR0, hashes[0]); 1207 CSR_WRITE_4(sc, DC_AL_MAR1, hashes[1]); 1208 } 1209 1210 static void 1211 dc_setfilt_asix(struct dc_softc *sc) 1212 { 1213 uint32_t eaddr[(ETHER_ADDR_LEN+3)/4]; 1214 struct ifnet *ifp; 1215 struct ifmultiaddr *ifma; 1216 int h = 0; 1217 u_int32_t hashes[2] = { 0, 0 }; 1218 1219 ifp = sc->dc_ifp; 1220 1221 /* Init our MAC address. */ 1222 bcopy(IF_LLADDR(sc->dc_ifp), eaddr, ETHER_ADDR_LEN); 1223 CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_PAR0); 1224 CSR_WRITE_4(sc, DC_AX_FILTDATA, eaddr[0]); 1225 CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_PAR1); 1226 CSR_WRITE_4(sc, DC_AX_FILTDATA, eaddr[1]); 1227 1228 /* If we want promiscuous mode, set the allframes bit. */ 1229 if (ifp->if_flags & IFF_PROMISC) 1230 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC); 1231 else 1232 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC); 1233 1234 if (ifp->if_flags & IFF_ALLMULTI) 1235 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI); 1236 else 1237 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI); 1238 1239 /* 1240 * The ASIX chip has a special bit to enable reception 1241 * of broadcast frames. 1242 */ 1243 if (ifp->if_flags & IFF_BROADCAST) 1244 DC_SETBIT(sc, DC_NETCFG, DC_AX_NETCFG_RX_BROAD); 1245 else 1246 DC_CLRBIT(sc, DC_NETCFG, DC_AX_NETCFG_RX_BROAD); 1247 1248 /* first, zot all the existing hash bits */ 1249 CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_MAR0); 1250 CSR_WRITE_4(sc, DC_AX_FILTDATA, 0); 1251 CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_MAR1); 1252 CSR_WRITE_4(sc, DC_AX_FILTDATA, 0); 1253 1254 /* 1255 * If we're already in promisc or allmulti mode, we 1256 * don't have to bother programming the multicast filter. 1257 */ 1258 if (ifp->if_flags & (IFF_PROMISC | IFF_ALLMULTI)) 1259 return; 1260 1261 /* now program new ones */ 1262 IF_ADDR_LOCK(ifp); 1263 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 1264 if (ifma->ifma_addr->sa_family != AF_LINK) 1265 continue; 1266 h = dc_mchash_be(LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 1267 if (h < 32) 1268 hashes[0] |= (1 << h); 1269 else 1270 hashes[1] |= (1 << (h - 32)); 1271 } 1272 IF_ADDR_UNLOCK(ifp); 1273 1274 CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_MAR0); 1275 CSR_WRITE_4(sc, DC_AX_FILTDATA, hashes[0]); 1276 CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_MAR1); 1277 CSR_WRITE_4(sc, DC_AX_FILTDATA, hashes[1]); 1278 } 1279 1280 static void 1281 dc_setfilt_xircom(struct dc_softc *sc) 1282 { 1283 uint16_t eaddr[(ETHER_ADDR_LEN+1)/2]; 1284 struct ifnet *ifp; 1285 struct ifmultiaddr *ifma; 1286 struct dc_desc *sframe; 1287 u_int32_t h, *sp; 1288 int i; 1289 1290 ifp = sc->dc_ifp; 1291 DC_CLRBIT(sc, DC_NETCFG, (DC_NETCFG_TX_ON | DC_NETCFG_RX_ON)); 1292 1293 i = sc->dc_cdata.dc_tx_prod; 1294 DC_INC(sc->dc_cdata.dc_tx_prod, DC_TX_LIST_CNT); 1295 sc->dc_cdata.dc_tx_cnt++; 1296 sframe = &sc->dc_ldata->dc_tx_list[i]; 1297 sp = sc->dc_cdata.dc_sbuf; 1298 bzero(sp, DC_SFRAME_LEN); 1299 1300 sframe->dc_data = htole32(sc->dc_saddr); 1301 sframe->dc_ctl = htole32(DC_SFRAME_LEN | DC_TXCTL_SETUP | 1302 DC_TXCTL_TLINK | DC_FILTER_HASHPERF | DC_TXCTL_FINT); 1303 1304 sc->dc_cdata.dc_tx_chain[i] = (struct mbuf *)sc->dc_cdata.dc_sbuf; 1305 1306 /* If we want promiscuous mode, set the allframes bit. */ 1307 if (ifp->if_flags & IFF_PROMISC) 1308 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC); 1309 else 1310 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC); 1311 1312 if (ifp->if_flags & IFF_ALLMULTI) 1313 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI); 1314 else 1315 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI); 1316 1317 IF_ADDR_LOCK(ifp); 1318 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 1319 if (ifma->ifma_addr->sa_family != AF_LINK) 1320 continue; 1321 h = dc_mchash_le(sc, 1322 LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 1323 sp[h >> 4] |= htole32(1 << (h & 0xF)); 1324 } 1325 IF_ADDR_UNLOCK(ifp); 1326 1327 if (ifp->if_flags & IFF_BROADCAST) { 1328 h = dc_mchash_le(sc, ifp->if_broadcastaddr); 1329 sp[h >> 4] |= htole32(1 << (h & 0xF)); 1330 } 1331 1332 /* Set our MAC address. */ 1333 bcopy(IF_LLADDR(sc->dc_ifp), eaddr, ETHER_ADDR_LEN); 1334 sp[0] = DC_SP_MAC(eaddr[0]); 1335 sp[1] = DC_SP_MAC(eaddr[1]); 1336 sp[2] = DC_SP_MAC(eaddr[2]); 1337 1338 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_TX_ON); 1339 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_ON); 1340 ifp->if_drv_flags |= IFF_DRV_RUNNING; 1341 sframe->dc_status = htole32(DC_TXSTAT_OWN); 1342 CSR_WRITE_4(sc, DC_TXSTART, 0xFFFFFFFF); 1343 1344 /* 1345 * Wait some time... 1346 */ 1347 DELAY(1000); 1348 1349 ifp->if_timer = 5; 1350 } 1351 1352 static void 1353 dc_setfilt(struct dc_softc *sc) 1354 { 1355 1356 if (DC_IS_INTEL(sc) || DC_IS_MACRONIX(sc) || DC_IS_PNIC(sc) || 1357 DC_IS_PNICII(sc) || DC_IS_DAVICOM(sc) || DC_IS_CONEXANT(sc)) 1358 dc_setfilt_21143(sc); 1359 1360 if (DC_IS_ASIX(sc)) 1361 dc_setfilt_asix(sc); 1362 1363 if (DC_IS_ADMTEK(sc)) 1364 dc_setfilt_admtek(sc); 1365 1366 if (DC_IS_XIRCOM(sc)) 1367 dc_setfilt_xircom(sc); 1368 } 1369 1370 /* 1371 * In order to fiddle with the 'full-duplex' and '100Mbps' bits in 1372 * the netconfig register, we first have to put the transmit and/or 1373 * receive logic in the idle state. 1374 */ 1375 static void 1376 dc_setcfg(struct dc_softc *sc, int media) 1377 { 1378 int i, restart = 0, watchdogreg; 1379 u_int32_t isr; 1380 1381 if (IFM_SUBTYPE(media) == IFM_NONE) 1382 return; 1383 1384 if (CSR_READ_4(sc, DC_NETCFG) & (DC_NETCFG_TX_ON | DC_NETCFG_RX_ON)) { 1385 restart = 1; 1386 DC_CLRBIT(sc, DC_NETCFG, (DC_NETCFG_TX_ON | DC_NETCFG_RX_ON)); 1387 1388 for (i = 0; i < DC_TIMEOUT; i++) { 1389 isr = CSR_READ_4(sc, DC_ISR); 1390 if (isr & DC_ISR_TX_IDLE && 1391 ((isr & DC_ISR_RX_STATE) == DC_RXSTATE_STOPPED || 1392 (isr & DC_ISR_RX_STATE) == DC_RXSTATE_WAIT)) 1393 break; 1394 DELAY(10); 1395 } 1396 1397 if (i == DC_TIMEOUT) 1398 device_printf(sc->dc_dev, 1399 "failed to force tx and rx to idle state\n"); 1400 } 1401 1402 if (IFM_SUBTYPE(media) == IFM_100_TX) { 1403 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_SPEEDSEL); 1404 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_HEARTBEAT); 1405 if (sc->dc_pmode == DC_PMODE_MII) { 1406 if (DC_IS_INTEL(sc)) { 1407 /* There's a write enable bit here that reads as 1. */ 1408 watchdogreg = CSR_READ_4(sc, DC_WATCHDOG); 1409 watchdogreg &= ~DC_WDOG_CTLWREN; 1410 watchdogreg |= DC_WDOG_JABBERDIS; 1411 CSR_WRITE_4(sc, DC_WATCHDOG, watchdogreg); 1412 } else { 1413 DC_SETBIT(sc, DC_WATCHDOG, DC_WDOG_JABBERDIS); 1414 } 1415 DC_CLRBIT(sc, DC_NETCFG, (DC_NETCFG_PCS | 1416 DC_NETCFG_PORTSEL | DC_NETCFG_SCRAMBLER)); 1417 if (sc->dc_type == DC_TYPE_98713) 1418 DC_SETBIT(sc, DC_NETCFG, (DC_NETCFG_PCS | 1419 DC_NETCFG_SCRAMBLER)); 1420 if (!DC_IS_DAVICOM(sc)) 1421 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL); 1422 DC_CLRBIT(sc, DC_10BTCTRL, 0xFFFF); 1423 if (DC_IS_INTEL(sc)) 1424 dc_apply_fixup(sc, IFM_AUTO); 1425 } else { 1426 if (DC_IS_PNIC(sc)) { 1427 DC_PN_GPIO_SETBIT(sc, DC_PN_GPIO_SPEEDSEL); 1428 DC_PN_GPIO_SETBIT(sc, DC_PN_GPIO_100TX_LOOP); 1429 DC_SETBIT(sc, DC_PN_NWAY, DC_PN_NWAY_SPEEDSEL); 1430 } 1431 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL); 1432 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PCS); 1433 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_SCRAMBLER); 1434 if (DC_IS_INTEL(sc)) 1435 dc_apply_fixup(sc, 1436 (media & IFM_GMASK) == IFM_FDX ? 1437 IFM_100_TX | IFM_FDX : IFM_100_TX); 1438 } 1439 } 1440 1441 if (IFM_SUBTYPE(media) == IFM_10_T) { 1442 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_SPEEDSEL); 1443 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_HEARTBEAT); 1444 if (sc->dc_pmode == DC_PMODE_MII) { 1445 /* There's a write enable bit here that reads as 1. */ 1446 if (DC_IS_INTEL(sc)) { 1447 watchdogreg = CSR_READ_4(sc, DC_WATCHDOG); 1448 watchdogreg &= ~DC_WDOG_CTLWREN; 1449 watchdogreg |= DC_WDOG_JABBERDIS; 1450 CSR_WRITE_4(sc, DC_WATCHDOG, watchdogreg); 1451 } else { 1452 DC_SETBIT(sc, DC_WATCHDOG, DC_WDOG_JABBERDIS); 1453 } 1454 DC_CLRBIT(sc, DC_NETCFG, (DC_NETCFG_PCS | 1455 DC_NETCFG_PORTSEL | DC_NETCFG_SCRAMBLER)); 1456 if (sc->dc_type == DC_TYPE_98713) 1457 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PCS); 1458 if (!DC_IS_DAVICOM(sc)) 1459 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL); 1460 DC_CLRBIT(sc, DC_10BTCTRL, 0xFFFF); 1461 if (DC_IS_INTEL(sc)) 1462 dc_apply_fixup(sc, IFM_AUTO); 1463 } else { 1464 if (DC_IS_PNIC(sc)) { 1465 DC_PN_GPIO_CLRBIT(sc, DC_PN_GPIO_SPEEDSEL); 1466 DC_PN_GPIO_SETBIT(sc, DC_PN_GPIO_100TX_LOOP); 1467 DC_CLRBIT(sc, DC_PN_NWAY, DC_PN_NWAY_SPEEDSEL); 1468 } 1469 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL); 1470 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_PCS); 1471 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_SCRAMBLER); 1472 if (DC_IS_INTEL(sc)) { 1473 DC_CLRBIT(sc, DC_SIARESET, DC_SIA_RESET); 1474 DC_CLRBIT(sc, DC_10BTCTRL, 0xFFFF); 1475 if ((media & IFM_GMASK) == IFM_FDX) 1476 DC_SETBIT(sc, DC_10BTCTRL, 0x7F3D); 1477 else 1478 DC_SETBIT(sc, DC_10BTCTRL, 0x7F3F); 1479 DC_SETBIT(sc, DC_SIARESET, DC_SIA_RESET); 1480 DC_CLRBIT(sc, DC_10BTCTRL, 1481 DC_TCTL_AUTONEGENBL); 1482 dc_apply_fixup(sc, 1483 (media & IFM_GMASK) == IFM_FDX ? 1484 IFM_10_T | IFM_FDX : IFM_10_T); 1485 DELAY(20000); 1486 } 1487 } 1488 } 1489 1490 /* 1491 * If this is a Davicom DM9102A card with a DM9801 HomePNA 1492 * PHY and we want HomePNA mode, set the portsel bit to turn 1493 * on the external MII port. 1494 */ 1495 if (DC_IS_DAVICOM(sc)) { 1496 if (IFM_SUBTYPE(media) == IFM_HPNA_1) { 1497 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL); 1498 sc->dc_link = 1; 1499 } else { 1500 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL); 1501 } 1502 } 1503 1504 if ((media & IFM_GMASK) == IFM_FDX) { 1505 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_FULLDUPLEX); 1506 if (sc->dc_pmode == DC_PMODE_SYM && DC_IS_PNIC(sc)) 1507 DC_SETBIT(sc, DC_PN_NWAY, DC_PN_NWAY_DUPLEX); 1508 } else { 1509 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_FULLDUPLEX); 1510 if (sc->dc_pmode == DC_PMODE_SYM && DC_IS_PNIC(sc)) 1511 DC_CLRBIT(sc, DC_PN_NWAY, DC_PN_NWAY_DUPLEX); 1512 } 1513 1514 if (restart) 1515 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_TX_ON | DC_NETCFG_RX_ON); 1516 } 1517 1518 static void 1519 dc_reset(struct dc_softc *sc) 1520 { 1521 int i; 1522 1523 DC_SETBIT(sc, DC_BUSCTL, DC_BUSCTL_RESET); 1524 1525 for (i = 0; i < DC_TIMEOUT; i++) { 1526 DELAY(10); 1527 if (!(CSR_READ_4(sc, DC_BUSCTL) & DC_BUSCTL_RESET)) 1528 break; 1529 } 1530 1531 if (DC_IS_ASIX(sc) || DC_IS_ADMTEK(sc) || DC_IS_CONEXANT(sc) || 1532 DC_IS_XIRCOM(sc) || DC_IS_INTEL(sc)) { 1533 DELAY(10000); 1534 DC_CLRBIT(sc, DC_BUSCTL, DC_BUSCTL_RESET); 1535 i = 0; 1536 } 1537 1538 if (i == DC_TIMEOUT) 1539 device_printf(sc->dc_dev, "reset never completed!\n"); 1540 1541 /* Wait a little while for the chip to get its brains in order. */ 1542 DELAY(1000); 1543 1544 CSR_WRITE_4(sc, DC_IMR, 0x00000000); 1545 CSR_WRITE_4(sc, DC_BUSCTL, 0x00000000); 1546 CSR_WRITE_4(sc, DC_NETCFG, 0x00000000); 1547 1548 /* 1549 * Bring the SIA out of reset. In some cases, it looks 1550 * like failing to unreset the SIA soon enough gets it 1551 * into a state where it will never come out of reset 1552 * until we reset the whole chip again. 1553 */ 1554 if (DC_IS_INTEL(sc)) { 1555 DC_SETBIT(sc, DC_SIARESET, DC_SIA_RESET); 1556 CSR_WRITE_4(sc, DC_10BTCTRL, 0); 1557 CSR_WRITE_4(sc, DC_WATCHDOG, 0); 1558 } 1559 } 1560 1561 static struct dc_type * 1562 dc_devtype(device_t dev) 1563 { 1564 struct dc_type *t; 1565 u_int32_t devid; 1566 u_int8_t rev; 1567 1568 t = dc_devs; 1569 devid = pci_get_devid(dev); 1570 rev = pci_get_revid(dev); 1571 1572 while (t->dc_name != NULL) { 1573 if (devid == t->dc_devid && rev >= t->dc_minrev) 1574 return (t); 1575 t++; 1576 } 1577 1578 return (NULL); 1579 } 1580 1581 /* 1582 * Probe for a 21143 or clone chip. Check the PCI vendor and device 1583 * IDs against our list and return a device name if we find a match. 1584 * We do a little bit of extra work to identify the exact type of 1585 * chip. The MX98713 and MX98713A have the same PCI vendor/device ID, 1586 * but different revision IDs. The same is true for 98715/98715A 1587 * chips and the 98725, as well as the ASIX and ADMtek chips. In some 1588 * cases, the exact chip revision affects driver behavior. 1589 */ 1590 static int 1591 dc_probe(device_t dev) 1592 { 1593 struct dc_type *t; 1594 1595 t = dc_devtype(dev); 1596 1597 if (t != NULL) { 1598 device_set_desc(dev, t->dc_name); 1599 return (BUS_PROBE_DEFAULT); 1600 } 1601 1602 return (ENXIO); 1603 } 1604 1605 static void 1606 dc_apply_fixup(struct dc_softc *sc, int media) 1607 { 1608 struct dc_mediainfo *m; 1609 u_int8_t *p; 1610 int i; 1611 u_int32_t reg; 1612 1613 m = sc->dc_mi; 1614 1615 while (m != NULL) { 1616 if (m->dc_media == media) 1617 break; 1618 m = m->dc_next; 1619 } 1620 1621 if (m == NULL) 1622 return; 1623 1624 for (i = 0, p = m->dc_reset_ptr; i < m->dc_reset_len; i++, p += 2) { 1625 reg = (p[0] | (p[1] << 8)) << 16; 1626 CSR_WRITE_4(sc, DC_WATCHDOG, reg); 1627 } 1628 1629 for (i = 0, p = m->dc_gp_ptr; i < m->dc_gp_len; i++, p += 2) { 1630 reg = (p[0] | (p[1] << 8)) << 16; 1631 CSR_WRITE_4(sc, DC_WATCHDOG, reg); 1632 } 1633 } 1634 1635 static void 1636 dc_decode_leaf_sia(struct dc_softc *sc, struct dc_eblock_sia *l) 1637 { 1638 struct dc_mediainfo *m; 1639 1640 m = malloc(sizeof(struct dc_mediainfo), M_DEVBUF, M_NOWAIT | M_ZERO); 1641 switch (l->dc_sia_code & ~DC_SIA_CODE_EXT) { 1642 case DC_SIA_CODE_10BT: 1643 m->dc_media = IFM_10_T; 1644 break; 1645 case DC_SIA_CODE_10BT_FDX: 1646 m->dc_media = IFM_10_T | IFM_FDX; 1647 break; 1648 case DC_SIA_CODE_10B2: 1649 m->dc_media = IFM_10_2; 1650 break; 1651 case DC_SIA_CODE_10B5: 1652 m->dc_media = IFM_10_5; 1653 break; 1654 default: 1655 break; 1656 } 1657 1658 /* 1659 * We need to ignore CSR13, CSR14, CSR15 for SIA mode. 1660 * Things apparently already work for cards that do 1661 * supply Media Specific Data. 1662 */ 1663 if (l->dc_sia_code & DC_SIA_CODE_EXT) { 1664 m->dc_gp_len = 2; 1665 m->dc_gp_ptr = 1666 (u_int8_t *)&l->dc_un.dc_sia_ext.dc_sia_gpio_ctl; 1667 } else { 1668 m->dc_gp_len = 2; 1669 m->dc_gp_ptr = 1670 (u_int8_t *)&l->dc_un.dc_sia_noext.dc_sia_gpio_ctl; 1671 } 1672 1673 m->dc_next = sc->dc_mi; 1674 sc->dc_mi = m; 1675 1676 sc->dc_pmode = DC_PMODE_SIA; 1677 } 1678 1679 static void 1680 dc_decode_leaf_sym(struct dc_softc *sc, struct dc_eblock_sym *l) 1681 { 1682 struct dc_mediainfo *m; 1683 1684 m = malloc(sizeof(struct dc_mediainfo), M_DEVBUF, M_NOWAIT | M_ZERO); 1685 if (l->dc_sym_code == DC_SYM_CODE_100BT) 1686 m->dc_media = IFM_100_TX; 1687 1688 if (l->dc_sym_code == DC_SYM_CODE_100BT_FDX) 1689 m->dc_media = IFM_100_TX | IFM_FDX; 1690 1691 m->dc_gp_len = 2; 1692 m->dc_gp_ptr = (u_int8_t *)&l->dc_sym_gpio_ctl; 1693 1694 m->dc_next = sc->dc_mi; 1695 sc->dc_mi = m; 1696 1697 sc->dc_pmode = DC_PMODE_SYM; 1698 } 1699 1700 static void 1701 dc_decode_leaf_mii(struct dc_softc *sc, struct dc_eblock_mii *l) 1702 { 1703 struct dc_mediainfo *m; 1704 u_int8_t *p; 1705 1706 m = malloc(sizeof(struct dc_mediainfo), M_DEVBUF, M_NOWAIT | M_ZERO); 1707 /* We abuse IFM_AUTO to represent MII. */ 1708 m->dc_media = IFM_AUTO; 1709 m->dc_gp_len = l->dc_gpr_len; 1710 1711 p = (u_int8_t *)l; 1712 p += sizeof(struct dc_eblock_mii); 1713 m->dc_gp_ptr = p; 1714 p += 2 * l->dc_gpr_len; 1715 m->dc_reset_len = *p; 1716 p++; 1717 m->dc_reset_ptr = p; 1718 1719 m->dc_next = sc->dc_mi; 1720 sc->dc_mi = m; 1721 } 1722 1723 static void 1724 dc_read_srom(struct dc_softc *sc, int bits) 1725 { 1726 int size; 1727 1728 size = 2 << bits; 1729 sc->dc_srom = malloc(size, M_DEVBUF, M_NOWAIT); 1730 dc_read_eeprom(sc, (caddr_t)sc->dc_srom, 0, (size / 2), 0); 1731 } 1732 1733 static void 1734 dc_parse_21143_srom(struct dc_softc *sc) 1735 { 1736 struct dc_leaf_hdr *lhdr; 1737 struct dc_eblock_hdr *hdr; 1738 int have_mii, i, loff; 1739 char *ptr; 1740 1741 have_mii = 0; 1742 loff = sc->dc_srom[27]; 1743 lhdr = (struct dc_leaf_hdr *)&(sc->dc_srom[loff]); 1744 1745 ptr = (char *)lhdr; 1746 ptr += sizeof(struct dc_leaf_hdr) - 1; 1747 /* 1748 * Look if we got a MII media block. 1749 */ 1750 for (i = 0; i < lhdr->dc_mcnt; i++) { 1751 hdr = (struct dc_eblock_hdr *)ptr; 1752 if (hdr->dc_type == DC_EBLOCK_MII) 1753 have_mii++; 1754 1755 ptr += (hdr->dc_len & 0x7F); 1756 ptr++; 1757 } 1758 1759 /* 1760 * Do the same thing again. Only use SIA and SYM media 1761 * blocks if no MII media block is available. 1762 */ 1763 ptr = (char *)lhdr; 1764 ptr += sizeof(struct dc_leaf_hdr) - 1; 1765 for (i = 0; i < lhdr->dc_mcnt; i++) { 1766 hdr = (struct dc_eblock_hdr *)ptr; 1767 switch (hdr->dc_type) { 1768 case DC_EBLOCK_MII: 1769 dc_decode_leaf_mii(sc, (struct dc_eblock_mii *)hdr); 1770 break; 1771 case DC_EBLOCK_SIA: 1772 if (! have_mii) 1773 dc_decode_leaf_sia(sc, 1774 (struct dc_eblock_sia *)hdr); 1775 break; 1776 case DC_EBLOCK_SYM: 1777 if (! have_mii) 1778 dc_decode_leaf_sym(sc, 1779 (struct dc_eblock_sym *)hdr); 1780 break; 1781 default: 1782 /* Don't care. Yet. */ 1783 break; 1784 } 1785 ptr += (hdr->dc_len & 0x7F); 1786 ptr++; 1787 } 1788 } 1789 1790 static void 1791 dc_dma_map_addr(void *arg, bus_dma_segment_t *segs, int nseg, int error) 1792 { 1793 u_int32_t *paddr; 1794 1795 KASSERT(nseg == 1, ("wrong number of segments, should be 1")); 1796 paddr = arg; 1797 *paddr = segs->ds_addr; 1798 } 1799 1800 /* 1801 * Attach the interface. Allocate softc structures, do ifmedia 1802 * setup and ethernet/BPF attach. 1803 */ 1804 static int 1805 dc_attach(device_t dev) 1806 { 1807 int tmp = 0; 1808 uint32_t eaddr[(ETHER_ADDR_LEN+3)/4]; 1809 u_int32_t command; 1810 struct dc_softc *sc; 1811 struct ifnet *ifp; 1812 u_int32_t revision; 1813 int error = 0, rid, mac_offset; 1814 int i; 1815 u_int8_t *mac; 1816 1817 sc = device_get_softc(dev); 1818 sc->dc_dev = dev; 1819 1820 mtx_init(&sc->dc_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 1821 MTX_DEF); 1822 1823 /* 1824 * Map control/status registers. 1825 */ 1826 pci_enable_busmaster(dev); 1827 1828 rid = DC_RID; 1829 sc->dc_res = bus_alloc_resource_any(dev, DC_RES, &rid, RF_ACTIVE); 1830 1831 if (sc->dc_res == NULL) { 1832 device_printf(dev, "couldn't map ports/memory\n"); 1833 error = ENXIO; 1834 goto fail; 1835 } 1836 1837 sc->dc_btag = rman_get_bustag(sc->dc_res); 1838 sc->dc_bhandle = rman_get_bushandle(sc->dc_res); 1839 1840 /* Allocate interrupt. */ 1841 rid = 0; 1842 sc->dc_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 1843 RF_SHAREABLE | RF_ACTIVE); 1844 1845 if (sc->dc_irq == NULL) { 1846 device_printf(dev, "couldn't map interrupt\n"); 1847 error = ENXIO; 1848 goto fail; 1849 } 1850 1851 /* Need this info to decide on a chip type. */ 1852 sc->dc_info = dc_devtype(dev); 1853 revision = pci_get_revid(dev); 1854 1855 /* Get the eeprom width, but PNIC and XIRCOM have diff eeprom */ 1856 if (sc->dc_info->dc_devid != 1857 DC_DEVID(DC_VENDORID_LO, DC_DEVICEID_82C168) && 1858 sc->dc_info->dc_devid != 1859 DC_DEVID(DC_VENDORID_XIRCOM, DC_DEVICEID_X3201)) 1860 dc_eeprom_width(sc); 1861 1862 switch (sc->dc_info->dc_devid) { 1863 case DC_DEVID(DC_VENDORID_DEC, DC_DEVICEID_21143): 1864 sc->dc_type = DC_TYPE_21143; 1865 sc->dc_flags |= DC_TX_POLL | DC_TX_USE_TX_INTR; 1866 sc->dc_flags |= DC_REDUCED_MII_POLL; 1867 /* Save EEPROM contents so we can parse them later. */ 1868 dc_read_srom(sc, sc->dc_romwidth); 1869 break; 1870 case DC_DEVID(DC_VENDORID_DAVICOM, DC_DEVICEID_DM9009): 1871 case DC_DEVID(DC_VENDORID_DAVICOM, DC_DEVICEID_DM9100): 1872 case DC_DEVID(DC_VENDORID_DAVICOM, DC_DEVICEID_DM9102): 1873 sc->dc_type = DC_TYPE_DM9102; 1874 sc->dc_flags |= DC_TX_COALESCE | DC_TX_INTR_ALWAYS; 1875 sc->dc_flags |= DC_REDUCED_MII_POLL | DC_TX_STORENFWD; 1876 sc->dc_flags |= DC_TX_ALIGN; 1877 sc->dc_pmode = DC_PMODE_MII; 1878 1879 /* Increase the latency timer value. */ 1880 pci_write_config(dev, PCIR_LATTIMER, 0x80, 1); 1881 break; 1882 case DC_DEVID(DC_VENDORID_ADMTEK, DC_DEVICEID_AL981): 1883 sc->dc_type = DC_TYPE_AL981; 1884 sc->dc_flags |= DC_TX_USE_TX_INTR; 1885 sc->dc_flags |= DC_TX_ADMTEK_WAR; 1886 sc->dc_pmode = DC_PMODE_MII; 1887 dc_read_srom(sc, sc->dc_romwidth); 1888 break; 1889 case DC_DEVID(DC_VENDORID_ADMTEK, DC_DEVICEID_AN985): 1890 case DC_DEVID(DC_VENDORID_ADMTEK, DC_DEVICEID_ADM9511): 1891 case DC_DEVID(DC_VENDORID_ADMTEK, DC_DEVICEID_ADM9513): 1892 case DC_DEVID(DC_VENDORID_DLINK, DC_DEVICEID_DRP32TXD): 1893 case DC_DEVID(DC_VENDORID_ADMTEK, DC_DEVICEID_FA511): 1894 case DC_DEVID(DC_VENDORID_ABOCOM, DC_DEVICEID_FE2500): 1895 case DC_DEVID(DC_VENDORID_ABOCOM, DC_DEVICEID_FE2500MX): 1896 case DC_DEVID(DC_VENDORID_ACCTON, DC_DEVICEID_EN2242): 1897 case DC_DEVID(DC_VENDORID_HAWKING, DC_DEVICEID_HAWKING_PN672TX): 1898 case DC_DEVID(DC_VENDORID_PLANEX, DC_DEVICEID_FNW3602T): 1899 case DC_DEVID(DC_VENDORID_3COM, DC_DEVICEID_3CSOHOB): 1900 case DC_DEVID(DC_VENDORID_MICROSOFT, DC_DEVICEID_MSMN120): 1901 case DC_DEVID(DC_VENDORID_MICROSOFT, DC_DEVICEID_MSMN130): 1902 case DC_DEVID(DC_VENDORID_LINKSYS, DC_DEVICEID_PCMPC200_AB08): 1903 case DC_DEVID(DC_VENDORID_LINKSYS, DC_DEVICEID_PCMPC200_AB09): 1904 sc->dc_type = DC_TYPE_AN985; 1905 sc->dc_flags |= DC_64BIT_HASH; 1906 sc->dc_flags |= DC_TX_USE_TX_INTR; 1907 sc->dc_flags |= DC_TX_ADMTEK_WAR; 1908 sc->dc_pmode = DC_PMODE_MII; 1909 /* Don't read SROM for - auto-loaded on reset */ 1910 break; 1911 case DC_DEVID(DC_VENDORID_MX, DC_DEVICEID_98713): 1912 case DC_DEVID(DC_VENDORID_CP, DC_DEVICEID_98713_CP): 1913 if (revision < DC_REVISION_98713A) { 1914 sc->dc_type = DC_TYPE_98713; 1915 } 1916 if (revision >= DC_REVISION_98713A) { 1917 sc->dc_type = DC_TYPE_98713A; 1918 sc->dc_flags |= DC_21143_NWAY; 1919 } 1920 sc->dc_flags |= DC_REDUCED_MII_POLL; 1921 sc->dc_flags |= DC_TX_POLL | DC_TX_USE_TX_INTR; 1922 break; 1923 case DC_DEVID(DC_VENDORID_MX, DC_DEVICEID_987x5): 1924 case DC_DEVID(DC_VENDORID_ACCTON, DC_DEVICEID_EN1217): 1925 /* 1926 * Macronix MX98715AEC-C/D/E parts have only a 1927 * 128-bit hash table. We need to deal with these 1928 * in the same manner as the PNIC II so that we 1929 * get the right number of bits out of the 1930 * CRC routine. 1931 */ 1932 if (revision >= DC_REVISION_98715AEC_C && 1933 revision < DC_REVISION_98725) 1934 sc->dc_flags |= DC_128BIT_HASH; 1935 sc->dc_type = DC_TYPE_987x5; 1936 sc->dc_flags |= DC_TX_POLL | DC_TX_USE_TX_INTR; 1937 sc->dc_flags |= DC_REDUCED_MII_POLL | DC_21143_NWAY; 1938 break; 1939 case DC_DEVID(DC_VENDORID_MX, DC_DEVICEID_98727): 1940 sc->dc_type = DC_TYPE_987x5; 1941 sc->dc_flags |= DC_TX_POLL | DC_TX_USE_TX_INTR; 1942 sc->dc_flags |= DC_REDUCED_MII_POLL | DC_21143_NWAY; 1943 break; 1944 case DC_DEVID(DC_VENDORID_LO, DC_DEVICEID_82C115): 1945 sc->dc_type = DC_TYPE_PNICII; 1946 sc->dc_flags |= DC_TX_POLL | DC_TX_USE_TX_INTR | DC_128BIT_HASH; 1947 sc->dc_flags |= DC_REDUCED_MII_POLL | DC_21143_NWAY; 1948 break; 1949 case DC_DEVID(DC_VENDORID_LO, DC_DEVICEID_82C168): 1950 sc->dc_type = DC_TYPE_PNIC; 1951 sc->dc_flags |= DC_TX_STORENFWD | DC_TX_INTR_ALWAYS; 1952 sc->dc_flags |= DC_PNIC_RX_BUG_WAR; 1953 sc->dc_pnic_rx_buf = malloc(DC_RXLEN * 5, M_DEVBUF, M_NOWAIT); 1954 if (revision < DC_REVISION_82C169) 1955 sc->dc_pmode = DC_PMODE_SYM; 1956 break; 1957 case DC_DEVID(DC_VENDORID_ASIX, DC_DEVICEID_AX88140A): 1958 sc->dc_type = DC_TYPE_ASIX; 1959 sc->dc_flags |= DC_TX_USE_TX_INTR | DC_TX_INTR_FIRSTFRAG; 1960 sc->dc_flags |= DC_REDUCED_MII_POLL; 1961 sc->dc_pmode = DC_PMODE_MII; 1962 break; 1963 case DC_DEVID(DC_VENDORID_XIRCOM, DC_DEVICEID_X3201): 1964 sc->dc_type = DC_TYPE_XIRCOM; 1965 sc->dc_flags |= DC_TX_INTR_ALWAYS | DC_TX_COALESCE | 1966 DC_TX_ALIGN; 1967 /* 1968 * We don't actually need to coalesce, but we're doing 1969 * it to obtain a double word aligned buffer. 1970 * The DC_TX_COALESCE flag is required. 1971 */ 1972 sc->dc_pmode = DC_PMODE_MII; 1973 break; 1974 case DC_DEVID(DC_VENDORID_CONEXANT, DC_DEVICEID_RS7112): 1975 sc->dc_type = DC_TYPE_CONEXANT; 1976 sc->dc_flags |= DC_TX_INTR_ALWAYS; 1977 sc->dc_flags |= DC_REDUCED_MII_POLL; 1978 sc->dc_pmode = DC_PMODE_MII; 1979 dc_read_srom(sc, sc->dc_romwidth); 1980 break; 1981 default: 1982 device_printf(dev, "unknown device: %x\n", 1983 sc->dc_info->dc_devid); 1984 break; 1985 } 1986 1987 /* Save the cache line size. */ 1988 if (DC_IS_DAVICOM(sc)) 1989 sc->dc_cachesize = 0; 1990 else 1991 sc->dc_cachesize = pci_get_cachelnsz(dev); 1992 1993 /* Reset the adapter. */ 1994 dc_reset(sc); 1995 1996 /* Take 21143 out of snooze mode */ 1997 if (DC_IS_INTEL(sc) || DC_IS_XIRCOM(sc)) { 1998 command = pci_read_config(dev, DC_PCI_CFDD, 4); 1999 command &= ~(DC_CFDD_SNOOZE_MODE | DC_CFDD_SLEEP_MODE); 2000 pci_write_config(dev, DC_PCI_CFDD, command, 4); 2001 } 2002 2003 /* 2004 * Try to learn something about the supported media. 2005 * We know that ASIX and ADMtek and Davicom devices 2006 * will *always* be using MII media, so that's a no-brainer. 2007 * The tricky ones are the Macronix/PNIC II and the 2008 * Intel 21143. 2009 */ 2010 if (DC_IS_INTEL(sc)) 2011 dc_parse_21143_srom(sc); 2012 else if (DC_IS_MACRONIX(sc) || DC_IS_PNICII(sc)) { 2013 if (sc->dc_type == DC_TYPE_98713) 2014 sc->dc_pmode = DC_PMODE_MII; 2015 else 2016 sc->dc_pmode = DC_PMODE_SYM; 2017 } else if (!sc->dc_pmode) 2018 sc->dc_pmode = DC_PMODE_MII; 2019 2020 /* 2021 * Get station address from the EEPROM. 2022 */ 2023 switch(sc->dc_type) { 2024 case DC_TYPE_98713: 2025 case DC_TYPE_98713A: 2026 case DC_TYPE_987x5: 2027 case DC_TYPE_PNICII: 2028 dc_read_eeprom(sc, (caddr_t)&mac_offset, 2029 (DC_EE_NODEADDR_OFFSET / 2), 1, 0); 2030 dc_read_eeprom(sc, (caddr_t)&eaddr, (mac_offset / 2), 3, 0); 2031 break; 2032 case DC_TYPE_PNIC: 2033 dc_read_eeprom(sc, (caddr_t)&eaddr, 0, 3, 1); 2034 break; 2035 case DC_TYPE_DM9102: 2036 dc_read_eeprom(sc, (caddr_t)&eaddr, DC_EE_NODEADDR, 3, 0); 2037 #ifdef __sparc64__ 2038 /* 2039 * If this is an onboard dc(4) the station address read from 2040 * the EEPROM is all zero and we have to get it from the FCode. 2041 */ 2042 if (eaddr[0] == 0 && (eaddr[1] & ~0xffff) == 0) 2043 OF_getetheraddr(dev, (caddr_t)&eaddr); 2044 #endif 2045 break; 2046 case DC_TYPE_21143: 2047 case DC_TYPE_ASIX: 2048 dc_read_eeprom(sc, (caddr_t)&eaddr, DC_EE_NODEADDR, 3, 0); 2049 break; 2050 case DC_TYPE_AL981: 2051 case DC_TYPE_AN985: 2052 eaddr[0] = CSR_READ_4(sc, DC_AL_PAR0); 2053 eaddr[1] = CSR_READ_4(sc, DC_AL_PAR1); 2054 break; 2055 case DC_TYPE_CONEXANT: 2056 bcopy(sc->dc_srom + DC_CONEXANT_EE_NODEADDR, &eaddr, 2057 ETHER_ADDR_LEN); 2058 break; 2059 case DC_TYPE_XIRCOM: 2060 /* The MAC comes from the CIS. */ 2061 mac = pci_get_ether(dev); 2062 if (!mac) { 2063 device_printf(dev, "No station address in CIS!\n"); 2064 error = ENXIO; 2065 goto fail; 2066 } 2067 bcopy(mac, eaddr, ETHER_ADDR_LEN); 2068 break; 2069 default: 2070 dc_read_eeprom(sc, (caddr_t)&eaddr, DC_EE_NODEADDR, 3, 0); 2071 break; 2072 } 2073 2074 /* Allocate a busdma tag and DMA safe memory for TX/RX descriptors. */ 2075 error = bus_dma_tag_create(NULL, PAGE_SIZE, 0, BUS_SPACE_MAXADDR_32BIT, 2076 BUS_SPACE_MAXADDR, NULL, NULL, sizeof(struct dc_list_data), 1, 2077 sizeof(struct dc_list_data), 0, NULL, NULL, &sc->dc_ltag); 2078 if (error) { 2079 device_printf(dev, "failed to allocate busdma tag\n"); 2080 error = ENXIO; 2081 goto fail; 2082 } 2083 error = bus_dmamem_alloc(sc->dc_ltag, (void **)&sc->dc_ldata, 2084 BUS_DMA_NOWAIT | BUS_DMA_ZERO, &sc->dc_lmap); 2085 if (error) { 2086 device_printf(dev, "failed to allocate DMA safe memory\n"); 2087 error = ENXIO; 2088 goto fail; 2089 } 2090 error = bus_dmamap_load(sc->dc_ltag, sc->dc_lmap, sc->dc_ldata, 2091 sizeof(struct dc_list_data), dc_dma_map_addr, &sc->dc_laddr, 2092 BUS_DMA_NOWAIT); 2093 if (error) { 2094 device_printf(dev, "cannot get address of the descriptors\n"); 2095 error = ENXIO; 2096 goto fail; 2097 } 2098 2099 /* 2100 * Allocate a busdma tag and DMA safe memory for the multicast 2101 * setup frame. 2102 */ 2103 error = bus_dma_tag_create(NULL, PAGE_SIZE, 0, BUS_SPACE_MAXADDR_32BIT, 2104 BUS_SPACE_MAXADDR, NULL, NULL, DC_SFRAME_LEN + DC_MIN_FRAMELEN, 1, 2105 DC_SFRAME_LEN + DC_MIN_FRAMELEN, 0, NULL, NULL, &sc->dc_stag); 2106 if (error) { 2107 device_printf(dev, "failed to allocate busdma tag\n"); 2108 error = ENXIO; 2109 goto fail; 2110 } 2111 error = bus_dmamem_alloc(sc->dc_stag, (void **)&sc->dc_cdata.dc_sbuf, 2112 BUS_DMA_NOWAIT, &sc->dc_smap); 2113 if (error) { 2114 device_printf(dev, "failed to allocate DMA safe memory\n"); 2115 error = ENXIO; 2116 goto fail; 2117 } 2118 error = bus_dmamap_load(sc->dc_stag, sc->dc_smap, sc->dc_cdata.dc_sbuf, 2119 DC_SFRAME_LEN, dc_dma_map_addr, &sc->dc_saddr, BUS_DMA_NOWAIT); 2120 if (error) { 2121 device_printf(dev, "cannot get address of the descriptors\n"); 2122 error = ENXIO; 2123 goto fail; 2124 } 2125 2126 /* Allocate a busdma tag for mbufs. */ 2127 error = bus_dma_tag_create(NULL, 1, 0, BUS_SPACE_MAXADDR_32BIT, 2128 BUS_SPACE_MAXADDR, NULL, NULL, MCLBYTES, DC_TX_LIST_CNT, MCLBYTES, 2129 0, NULL, NULL, &sc->dc_mtag); 2130 if (error) { 2131 device_printf(dev, "failed to allocate busdma tag\n"); 2132 error = ENXIO; 2133 goto fail; 2134 } 2135 2136 /* Create the TX/RX busdma maps. */ 2137 for (i = 0; i < DC_TX_LIST_CNT; i++) { 2138 error = bus_dmamap_create(sc->dc_mtag, 0, 2139 &sc->dc_cdata.dc_tx_map[i]); 2140 if (error) { 2141 device_printf(dev, "failed to init TX ring\n"); 2142 error = ENXIO; 2143 goto fail; 2144 } 2145 } 2146 for (i = 0; i < DC_RX_LIST_CNT; i++) { 2147 error = bus_dmamap_create(sc->dc_mtag, 0, 2148 &sc->dc_cdata.dc_rx_map[i]); 2149 if (error) { 2150 device_printf(dev, "failed to init RX ring\n"); 2151 error = ENXIO; 2152 goto fail; 2153 } 2154 } 2155 error = bus_dmamap_create(sc->dc_mtag, 0, &sc->dc_sparemap); 2156 if (error) { 2157 device_printf(dev, "failed to init RX ring\n"); 2158 error = ENXIO; 2159 goto fail; 2160 } 2161 2162 ifp = sc->dc_ifp = if_alloc(IFT_ETHER); 2163 if (ifp == NULL) { 2164 device_printf(dev, "can not if_alloc()\n"); 2165 error = ENOSPC; 2166 goto fail; 2167 } 2168 ifp->if_softc = sc; 2169 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 2170 /* XXX: bleah, MTU gets overwritten in ether_ifattach() */ 2171 ifp->if_mtu = ETHERMTU; 2172 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 2173 ifp->if_ioctl = dc_ioctl; 2174 ifp->if_start = dc_start; 2175 ifp->if_watchdog = dc_watchdog; 2176 ifp->if_init = dc_init; 2177 IFQ_SET_MAXLEN(&ifp->if_snd, DC_TX_LIST_CNT - 1); 2178 ifp->if_snd.ifq_drv_maxlen = DC_TX_LIST_CNT - 1; 2179 IFQ_SET_READY(&ifp->if_snd); 2180 2181 /* 2182 * Do MII setup. If this is a 21143, check for a PHY on the 2183 * MII bus after applying any necessary fixups to twiddle the 2184 * GPIO bits. If we don't end up finding a PHY, restore the 2185 * old selection (SIA only or SIA/SYM) and attach the dcphy 2186 * driver instead. 2187 */ 2188 if (DC_IS_INTEL(sc)) { 2189 dc_apply_fixup(sc, IFM_AUTO); 2190 tmp = sc->dc_pmode; 2191 sc->dc_pmode = DC_PMODE_MII; 2192 } 2193 2194 /* 2195 * Setup General Purpose port mode and data so the tulip can talk 2196 * to the MII. This needs to be done before mii_phy_probe so that 2197 * we can actually see them. 2198 */ 2199 if (DC_IS_XIRCOM(sc)) { 2200 CSR_WRITE_4(sc, DC_SIAGP, DC_SIAGP_WRITE_EN | DC_SIAGP_INT1_EN | 2201 DC_SIAGP_MD_GP2_OUTPUT | DC_SIAGP_MD_GP0_OUTPUT); 2202 DELAY(10); 2203 CSR_WRITE_4(sc, DC_SIAGP, DC_SIAGP_INT1_EN | 2204 DC_SIAGP_MD_GP2_OUTPUT | DC_SIAGP_MD_GP0_OUTPUT); 2205 DELAY(10); 2206 } 2207 2208 error = mii_phy_probe(dev, &sc->dc_miibus, 2209 dc_ifmedia_upd, dc_ifmedia_sts); 2210 2211 if (error && DC_IS_INTEL(sc)) { 2212 sc->dc_pmode = tmp; 2213 if (sc->dc_pmode != DC_PMODE_SIA) 2214 sc->dc_pmode = DC_PMODE_SYM; 2215 sc->dc_flags |= DC_21143_NWAY; 2216 mii_phy_probe(dev, &sc->dc_miibus, 2217 dc_ifmedia_upd, dc_ifmedia_sts); 2218 /* 2219 * For non-MII cards, we need to have the 21143 2220 * drive the LEDs. Except there are some systems 2221 * like the NEC VersaPro NoteBook PC which have no 2222 * LEDs, and twiddling these bits has adverse effects 2223 * on them. (I.e. you suddenly can't get a link.) 2224 */ 2225 if (!(pci_get_subvendor(dev) == 0x1033 && 2226 pci_get_subdevice(dev) == 0x8028)) 2227 sc->dc_flags |= DC_TULIP_LEDS; 2228 error = 0; 2229 } 2230 2231 if (error) { 2232 device_printf(dev, "MII without any PHY!\n"); 2233 goto fail; 2234 } 2235 2236 if (DC_IS_ADMTEK(sc)) { 2237 /* 2238 * Set automatic TX underrun recovery for the ADMtek chips 2239 */ 2240 DC_SETBIT(sc, DC_AL_CR, DC_AL_CR_ATUR); 2241 } 2242 2243 /* 2244 * Tell the upper layer(s) we support long frames. 2245 */ 2246 ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header); 2247 ifp->if_capabilities |= IFCAP_VLAN_MTU; 2248 ifp->if_capenable = ifp->if_capabilities; 2249 #ifdef DEVICE_POLLING 2250 ifp->if_capabilities |= IFCAP_POLLING; 2251 #endif 2252 2253 callout_init_mtx(&sc->dc_stat_ch, &sc->dc_mtx, 0); 2254 2255 /* 2256 * Call MI attach routine. 2257 */ 2258 ether_ifattach(ifp, (caddr_t)eaddr); 2259 2260 /* Hook interrupt last to avoid having to lock softc */ 2261 error = bus_setup_intr(dev, sc->dc_irq, INTR_TYPE_NET | INTR_MPSAFE, 2262 dc_intr, sc, &sc->dc_intrhand); 2263 2264 if (error) { 2265 device_printf(dev, "couldn't set up irq\n"); 2266 ether_ifdetach(ifp); 2267 goto fail; 2268 } 2269 2270 fail: 2271 if (error) 2272 dc_detach(dev); 2273 return (error); 2274 } 2275 2276 /* 2277 * Shutdown hardware and free up resources. This can be called any 2278 * time after the mutex has been initialized. It is called in both 2279 * the error case in attach and the normal detach case so it needs 2280 * to be careful about only freeing resources that have actually been 2281 * allocated. 2282 */ 2283 static int 2284 dc_detach(device_t dev) 2285 { 2286 struct dc_softc *sc; 2287 struct ifnet *ifp; 2288 struct dc_mediainfo *m; 2289 int i; 2290 2291 sc = device_get_softc(dev); 2292 KASSERT(mtx_initialized(&sc->dc_mtx), ("dc mutex not initialized")); 2293 2294 ifp = sc->dc_ifp; 2295 2296 #ifdef DEVICE_POLLING 2297 if (ifp->if_capenable & IFCAP_POLLING) 2298 ether_poll_deregister(ifp); 2299 #endif 2300 2301 /* These should only be active if attach succeeded */ 2302 if (device_is_attached(dev)) { 2303 DC_LOCK(sc); 2304 dc_stop(sc); 2305 DC_UNLOCK(sc); 2306 callout_drain(&sc->dc_stat_ch); 2307 ether_ifdetach(ifp); 2308 } 2309 if (sc->dc_miibus) 2310 device_delete_child(dev, sc->dc_miibus); 2311 bus_generic_detach(dev); 2312 2313 if (sc->dc_intrhand) 2314 bus_teardown_intr(dev, sc->dc_irq, sc->dc_intrhand); 2315 if (sc->dc_irq) 2316 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->dc_irq); 2317 if (sc->dc_res) 2318 bus_release_resource(dev, DC_RES, DC_RID, sc->dc_res); 2319 2320 if (ifp) 2321 if_free(ifp); 2322 2323 if (sc->dc_cdata.dc_sbuf != NULL) 2324 bus_dmamem_free(sc->dc_stag, sc->dc_cdata.dc_sbuf, sc->dc_smap); 2325 if (sc->dc_ldata != NULL) 2326 bus_dmamem_free(sc->dc_ltag, sc->dc_ldata, sc->dc_lmap); 2327 if (sc->dc_mtag) { 2328 for (i = 0; i < DC_TX_LIST_CNT; i++) 2329 if (sc->dc_cdata.dc_tx_map[i] != NULL) 2330 bus_dmamap_destroy(sc->dc_mtag, 2331 sc->dc_cdata.dc_tx_map[i]); 2332 for (i = 0; i < DC_RX_LIST_CNT; i++) 2333 if (sc->dc_cdata.dc_rx_map[i] != NULL) 2334 bus_dmamap_destroy(sc->dc_mtag, 2335 sc->dc_cdata.dc_rx_map[i]); 2336 bus_dmamap_destroy(sc->dc_mtag, sc->dc_sparemap); 2337 } 2338 if (sc->dc_stag) 2339 bus_dma_tag_destroy(sc->dc_stag); 2340 if (sc->dc_mtag) 2341 bus_dma_tag_destroy(sc->dc_mtag); 2342 if (sc->dc_ltag) 2343 bus_dma_tag_destroy(sc->dc_ltag); 2344 2345 free(sc->dc_pnic_rx_buf, M_DEVBUF); 2346 2347 while (sc->dc_mi != NULL) { 2348 m = sc->dc_mi->dc_next; 2349 free(sc->dc_mi, M_DEVBUF); 2350 sc->dc_mi = m; 2351 } 2352 free(sc->dc_srom, M_DEVBUF); 2353 2354 mtx_destroy(&sc->dc_mtx); 2355 2356 return (0); 2357 } 2358 2359 /* 2360 * Initialize the transmit descriptors. 2361 */ 2362 static int 2363 dc_list_tx_init(struct dc_softc *sc) 2364 { 2365 struct dc_chain_data *cd; 2366 struct dc_list_data *ld; 2367 int i, nexti; 2368 2369 cd = &sc->dc_cdata; 2370 ld = sc->dc_ldata; 2371 for (i = 0; i < DC_TX_LIST_CNT; i++) { 2372 if (i == DC_TX_LIST_CNT - 1) 2373 nexti = 0; 2374 else 2375 nexti = i + 1; 2376 ld->dc_tx_list[i].dc_next = htole32(DC_TXDESC(sc, nexti)); 2377 cd->dc_tx_chain[i] = NULL; 2378 ld->dc_tx_list[i].dc_data = 0; 2379 ld->dc_tx_list[i].dc_ctl = 0; 2380 } 2381 2382 cd->dc_tx_prod = cd->dc_tx_cons = cd->dc_tx_cnt = 0; 2383 bus_dmamap_sync(sc->dc_ltag, sc->dc_lmap, 2384 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2385 return (0); 2386 } 2387 2388 2389 /* 2390 * Initialize the RX descriptors and allocate mbufs for them. Note that 2391 * we arrange the descriptors in a closed ring, so that the last descriptor 2392 * points back to the first. 2393 */ 2394 static int 2395 dc_list_rx_init(struct dc_softc *sc) 2396 { 2397 struct dc_chain_data *cd; 2398 struct dc_list_data *ld; 2399 int i, nexti; 2400 2401 cd = &sc->dc_cdata; 2402 ld = sc->dc_ldata; 2403 2404 for (i = 0; i < DC_RX_LIST_CNT; i++) { 2405 if (dc_newbuf(sc, i, 1) != 0) 2406 return (ENOBUFS); 2407 if (i == DC_RX_LIST_CNT - 1) 2408 nexti = 0; 2409 else 2410 nexti = i + 1; 2411 ld->dc_rx_list[i].dc_next = htole32(DC_RXDESC(sc, nexti)); 2412 } 2413 2414 cd->dc_rx_prod = 0; 2415 bus_dmamap_sync(sc->dc_ltag, sc->dc_lmap, 2416 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2417 return (0); 2418 } 2419 2420 static void 2421 dc_dma_map_rxbuf(arg, segs, nseg, mapsize, error) 2422 void *arg; 2423 bus_dma_segment_t *segs; 2424 int nseg; 2425 bus_size_t mapsize; 2426 int error; 2427 { 2428 struct dc_softc *sc; 2429 struct dc_desc *c; 2430 2431 sc = arg; 2432 c = &sc->dc_ldata->dc_rx_list[sc->dc_cdata.dc_rx_cur]; 2433 if (error) { 2434 sc->dc_cdata.dc_rx_err = error; 2435 return; 2436 } 2437 2438 KASSERT(nseg == 1, ("wrong number of segments, should be 1")); 2439 sc->dc_cdata.dc_rx_err = 0; 2440 c->dc_data = htole32(segs->ds_addr); 2441 } 2442 2443 /* 2444 * Initialize an RX descriptor and attach an MBUF cluster. 2445 */ 2446 static int 2447 dc_newbuf(struct dc_softc *sc, int i, int alloc) 2448 { 2449 struct mbuf *m_new; 2450 bus_dmamap_t tmp; 2451 int error; 2452 2453 if (alloc) { 2454 m_new = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR); 2455 if (m_new == NULL) 2456 return (ENOBUFS); 2457 } else { 2458 m_new = sc->dc_cdata.dc_rx_chain[i]; 2459 m_new->m_data = m_new->m_ext.ext_buf; 2460 } 2461 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 2462 m_adj(m_new, sizeof(u_int64_t)); 2463 2464 /* 2465 * If this is a PNIC chip, zero the buffer. This is part 2466 * of the workaround for the receive bug in the 82c168 and 2467 * 82c169 chips. 2468 */ 2469 if (sc->dc_flags & DC_PNIC_RX_BUG_WAR) 2470 bzero(mtod(m_new, char *), m_new->m_len); 2471 2472 /* No need to remap the mbuf if we're reusing it. */ 2473 if (alloc) { 2474 sc->dc_cdata.dc_rx_cur = i; 2475 error = bus_dmamap_load_mbuf(sc->dc_mtag, sc->dc_sparemap, 2476 m_new, dc_dma_map_rxbuf, sc, 0); 2477 if (error) { 2478 m_freem(m_new); 2479 return (error); 2480 } 2481 if (sc->dc_cdata.dc_rx_err != 0) { 2482 m_freem(m_new); 2483 return (sc->dc_cdata.dc_rx_err); 2484 } 2485 bus_dmamap_unload(sc->dc_mtag, sc->dc_cdata.dc_rx_map[i]); 2486 tmp = sc->dc_cdata.dc_rx_map[i]; 2487 sc->dc_cdata.dc_rx_map[i] = sc->dc_sparemap; 2488 sc->dc_sparemap = tmp; 2489 sc->dc_cdata.dc_rx_chain[i] = m_new; 2490 } 2491 2492 sc->dc_ldata->dc_rx_list[i].dc_ctl = htole32(DC_RXCTL_RLINK | DC_RXLEN); 2493 sc->dc_ldata->dc_rx_list[i].dc_status = htole32(DC_RXSTAT_OWN); 2494 bus_dmamap_sync(sc->dc_mtag, sc->dc_cdata.dc_rx_map[i], 2495 BUS_DMASYNC_PREREAD); 2496 bus_dmamap_sync(sc->dc_ltag, sc->dc_lmap, 2497 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2498 return (0); 2499 } 2500 2501 /* 2502 * Grrrrr. 2503 * The PNIC chip has a terrible bug in it that manifests itself during 2504 * periods of heavy activity. The exact mode of failure if difficult to 2505 * pinpoint: sometimes it only happens in promiscuous mode, sometimes it 2506 * will happen on slow machines. The bug is that sometimes instead of 2507 * uploading one complete frame during reception, it uploads what looks 2508 * like the entire contents of its FIFO memory. The frame we want is at 2509 * the end of the whole mess, but we never know exactly how much data has 2510 * been uploaded, so salvaging the frame is hard. 2511 * 2512 * There is only one way to do it reliably, and it's disgusting. 2513 * Here's what we know: 2514 * 2515 * - We know there will always be somewhere between one and three extra 2516 * descriptors uploaded. 2517 * 2518 * - We know the desired received frame will always be at the end of the 2519 * total data upload. 2520 * 2521 * - We know the size of the desired received frame because it will be 2522 * provided in the length field of the status word in the last descriptor. 2523 * 2524 * Here's what we do: 2525 * 2526 * - When we allocate buffers for the receive ring, we bzero() them. 2527 * This means that we know that the buffer contents should be all 2528 * zeros, except for data uploaded by the chip. 2529 * 2530 * - We also force the PNIC chip to upload frames that include the 2531 * ethernet CRC at the end. 2532 * 2533 * - We gather all of the bogus frame data into a single buffer. 2534 * 2535 * - We then position a pointer at the end of this buffer and scan 2536 * backwards until we encounter the first non-zero byte of data. 2537 * This is the end of the received frame. We know we will encounter 2538 * some data at the end of the frame because the CRC will always be 2539 * there, so even if the sender transmits a packet of all zeros, 2540 * we won't be fooled. 2541 * 2542 * - We know the size of the actual received frame, so we subtract 2543 * that value from the current pointer location. This brings us 2544 * to the start of the actual received packet. 2545 * 2546 * - We copy this into an mbuf and pass it on, along with the actual 2547 * frame length. 2548 * 2549 * The performance hit is tremendous, but it beats dropping frames all 2550 * the time. 2551 */ 2552 2553 #define DC_WHOLEFRAME (DC_RXSTAT_FIRSTFRAG | DC_RXSTAT_LASTFRAG) 2554 static void 2555 dc_pnic_rx_bug_war(struct dc_softc *sc, int idx) 2556 { 2557 struct dc_desc *cur_rx; 2558 struct dc_desc *c = NULL; 2559 struct mbuf *m = NULL; 2560 unsigned char *ptr; 2561 int i, total_len; 2562 u_int32_t rxstat = 0; 2563 2564 i = sc->dc_pnic_rx_bug_save; 2565 cur_rx = &sc->dc_ldata->dc_rx_list[idx]; 2566 ptr = sc->dc_pnic_rx_buf; 2567 bzero(ptr, DC_RXLEN * 5); 2568 2569 /* Copy all the bytes from the bogus buffers. */ 2570 while (1) { 2571 c = &sc->dc_ldata->dc_rx_list[i]; 2572 rxstat = le32toh(c->dc_status); 2573 m = sc->dc_cdata.dc_rx_chain[i]; 2574 bcopy(mtod(m, char *), ptr, DC_RXLEN); 2575 ptr += DC_RXLEN; 2576 /* If this is the last buffer, break out. */ 2577 if (i == idx || rxstat & DC_RXSTAT_LASTFRAG) 2578 break; 2579 dc_newbuf(sc, i, 0); 2580 DC_INC(i, DC_RX_LIST_CNT); 2581 } 2582 2583 /* Find the length of the actual receive frame. */ 2584 total_len = DC_RXBYTES(rxstat); 2585 2586 /* Scan backwards until we hit a non-zero byte. */ 2587 while (*ptr == 0x00) 2588 ptr--; 2589 2590 /* Round off. */ 2591 if ((uintptr_t)(ptr) & 0x3) 2592 ptr -= 1; 2593 2594 /* Now find the start of the frame. */ 2595 ptr -= total_len; 2596 if (ptr < sc->dc_pnic_rx_buf) 2597 ptr = sc->dc_pnic_rx_buf; 2598 2599 /* 2600 * Now copy the salvaged frame to the last mbuf and fake up 2601 * the status word to make it look like a successful 2602 * frame reception. 2603 */ 2604 dc_newbuf(sc, i, 0); 2605 bcopy(ptr, mtod(m, char *), total_len); 2606 cur_rx->dc_status = htole32(rxstat | DC_RXSTAT_FIRSTFRAG); 2607 } 2608 2609 /* 2610 * This routine searches the RX ring for dirty descriptors in the 2611 * event that the rxeof routine falls out of sync with the chip's 2612 * current descriptor pointer. This may happen sometimes as a result 2613 * of a "no RX buffer available" condition that happens when the chip 2614 * consumes all of the RX buffers before the driver has a chance to 2615 * process the RX ring. This routine may need to be called more than 2616 * once to bring the driver back in sync with the chip, however we 2617 * should still be getting RX DONE interrupts to drive the search 2618 * for new packets in the RX ring, so we should catch up eventually. 2619 */ 2620 static int 2621 dc_rx_resync(struct dc_softc *sc) 2622 { 2623 struct dc_desc *cur_rx; 2624 int i, pos; 2625 2626 pos = sc->dc_cdata.dc_rx_prod; 2627 2628 for (i = 0; i < DC_RX_LIST_CNT; i++) { 2629 cur_rx = &sc->dc_ldata->dc_rx_list[pos]; 2630 if (!(le32toh(cur_rx->dc_status) & DC_RXSTAT_OWN)) 2631 break; 2632 DC_INC(pos, DC_RX_LIST_CNT); 2633 } 2634 2635 /* If the ring really is empty, then just return. */ 2636 if (i == DC_RX_LIST_CNT) 2637 return (0); 2638 2639 /* We've fallen behing the chip: catch it. */ 2640 sc->dc_cdata.dc_rx_prod = pos; 2641 2642 return (EAGAIN); 2643 } 2644 2645 /* 2646 * A frame has been uploaded: pass the resulting mbuf chain up to 2647 * the higher level protocols. 2648 */ 2649 static void 2650 dc_rxeof(struct dc_softc *sc) 2651 { 2652 struct mbuf *m; 2653 struct ifnet *ifp; 2654 struct dc_desc *cur_rx; 2655 int i, total_len = 0; 2656 u_int32_t rxstat; 2657 2658 DC_LOCK_ASSERT(sc); 2659 2660 ifp = sc->dc_ifp; 2661 i = sc->dc_cdata.dc_rx_prod; 2662 2663 bus_dmamap_sync(sc->dc_ltag, sc->dc_lmap, BUS_DMASYNC_POSTREAD); 2664 while (!(le32toh(sc->dc_ldata->dc_rx_list[i].dc_status) & 2665 DC_RXSTAT_OWN)) { 2666 #ifdef DEVICE_POLLING 2667 if (ifp->if_capenable & IFCAP_POLLING) { 2668 if (sc->rxcycles <= 0) 2669 break; 2670 sc->rxcycles--; 2671 } 2672 #endif 2673 cur_rx = &sc->dc_ldata->dc_rx_list[i]; 2674 rxstat = le32toh(cur_rx->dc_status); 2675 m = sc->dc_cdata.dc_rx_chain[i]; 2676 bus_dmamap_sync(sc->dc_mtag, sc->dc_cdata.dc_rx_map[i], 2677 BUS_DMASYNC_POSTREAD); 2678 total_len = DC_RXBYTES(rxstat); 2679 2680 if (sc->dc_flags & DC_PNIC_RX_BUG_WAR) { 2681 if ((rxstat & DC_WHOLEFRAME) != DC_WHOLEFRAME) { 2682 if (rxstat & DC_RXSTAT_FIRSTFRAG) 2683 sc->dc_pnic_rx_bug_save = i; 2684 if ((rxstat & DC_RXSTAT_LASTFRAG) == 0) { 2685 DC_INC(i, DC_RX_LIST_CNT); 2686 continue; 2687 } 2688 dc_pnic_rx_bug_war(sc, i); 2689 rxstat = le32toh(cur_rx->dc_status); 2690 total_len = DC_RXBYTES(rxstat); 2691 } 2692 } 2693 2694 /* 2695 * If an error occurs, update stats, clear the 2696 * status word and leave the mbuf cluster in place: 2697 * it should simply get re-used next time this descriptor 2698 * comes up in the ring. However, don't report long 2699 * frames as errors since they could be vlans. 2700 */ 2701 if ((rxstat & DC_RXSTAT_RXERR)) { 2702 if (!(rxstat & DC_RXSTAT_GIANT) || 2703 (rxstat & (DC_RXSTAT_CRCERR | DC_RXSTAT_DRIBBLE | 2704 DC_RXSTAT_MIIERE | DC_RXSTAT_COLLSEEN | 2705 DC_RXSTAT_RUNT | DC_RXSTAT_DE))) { 2706 ifp->if_ierrors++; 2707 if (rxstat & DC_RXSTAT_COLLSEEN) 2708 ifp->if_collisions++; 2709 dc_newbuf(sc, i, 0); 2710 if (rxstat & DC_RXSTAT_CRCERR) { 2711 DC_INC(i, DC_RX_LIST_CNT); 2712 continue; 2713 } else { 2714 dc_init_locked(sc); 2715 return; 2716 } 2717 } 2718 } 2719 2720 /* No errors; receive the packet. */ 2721 total_len -= ETHER_CRC_LEN; 2722 #ifdef __i386__ 2723 /* 2724 * On the x86 we do not have alignment problems, so try to 2725 * allocate a new buffer for the receive ring, and pass up 2726 * the one where the packet is already, saving the expensive 2727 * copy done in m_devget(). 2728 * If we are on an architecture with alignment problems, or 2729 * if the allocation fails, then use m_devget and leave the 2730 * existing buffer in the receive ring. 2731 */ 2732 if (dc_quick && dc_newbuf(sc, i, 1) == 0) { 2733 m->m_pkthdr.rcvif = ifp; 2734 m->m_pkthdr.len = m->m_len = total_len; 2735 DC_INC(i, DC_RX_LIST_CNT); 2736 } else 2737 #endif 2738 { 2739 struct mbuf *m0; 2740 2741 m0 = m_devget(mtod(m, char *), total_len, 2742 ETHER_ALIGN, ifp, NULL); 2743 dc_newbuf(sc, i, 0); 2744 DC_INC(i, DC_RX_LIST_CNT); 2745 if (m0 == NULL) { 2746 ifp->if_ierrors++; 2747 continue; 2748 } 2749 m = m0; 2750 } 2751 2752 ifp->if_ipackets++; 2753 DC_UNLOCK(sc); 2754 (*ifp->if_input)(ifp, m); 2755 DC_LOCK(sc); 2756 } 2757 2758 sc->dc_cdata.dc_rx_prod = i; 2759 } 2760 2761 /* 2762 * A frame was downloaded to the chip. It's safe for us to clean up 2763 * the list buffers. 2764 */ 2765 2766 static void 2767 dc_txeof(struct dc_softc *sc) 2768 { 2769 struct dc_desc *cur_tx = NULL; 2770 struct ifnet *ifp; 2771 int idx; 2772 u_int32_t ctl, txstat; 2773 2774 ifp = sc->dc_ifp; 2775 2776 /* 2777 * Go through our tx list and free mbufs for those 2778 * frames that have been transmitted. 2779 */ 2780 bus_dmamap_sync(sc->dc_ltag, sc->dc_lmap, BUS_DMASYNC_POSTREAD); 2781 idx = sc->dc_cdata.dc_tx_cons; 2782 while (idx != sc->dc_cdata.dc_tx_prod) { 2783 2784 cur_tx = &sc->dc_ldata->dc_tx_list[idx]; 2785 txstat = le32toh(cur_tx->dc_status); 2786 ctl = le32toh(cur_tx->dc_ctl); 2787 2788 if (txstat & DC_TXSTAT_OWN) 2789 break; 2790 2791 if (!(ctl & DC_TXCTL_LASTFRAG) || ctl & DC_TXCTL_SETUP) { 2792 if (ctl & DC_TXCTL_SETUP) { 2793 /* 2794 * Yes, the PNIC is so brain damaged 2795 * that it will sometimes generate a TX 2796 * underrun error while DMAing the RX 2797 * filter setup frame. If we detect this, 2798 * we have to send the setup frame again, 2799 * or else the filter won't be programmed 2800 * correctly. 2801 */ 2802 if (DC_IS_PNIC(sc)) { 2803 if (txstat & DC_TXSTAT_ERRSUM) 2804 dc_setfilt(sc); 2805 } 2806 sc->dc_cdata.dc_tx_chain[idx] = NULL; 2807 } 2808 sc->dc_cdata.dc_tx_cnt--; 2809 DC_INC(idx, DC_TX_LIST_CNT); 2810 continue; 2811 } 2812 2813 if (DC_IS_XIRCOM(sc) || DC_IS_CONEXANT(sc)) { 2814 /* 2815 * XXX: Why does my Xircom taunt me so? 2816 * For some reason it likes setting the CARRLOST flag 2817 * even when the carrier is there. wtf?!? 2818 * Who knows, but Conexant chips have the 2819 * same problem. Maybe they took lessons 2820 * from Xircom. 2821 */ 2822 if (/*sc->dc_type == DC_TYPE_21143 &&*/ 2823 sc->dc_pmode == DC_PMODE_MII && 2824 ((txstat & 0xFFFF) & ~(DC_TXSTAT_ERRSUM | 2825 DC_TXSTAT_NOCARRIER))) 2826 txstat &= ~DC_TXSTAT_ERRSUM; 2827 } else { 2828 if (/*sc->dc_type == DC_TYPE_21143 &&*/ 2829 sc->dc_pmode == DC_PMODE_MII && 2830 ((txstat & 0xFFFF) & ~(DC_TXSTAT_ERRSUM | 2831 DC_TXSTAT_NOCARRIER | DC_TXSTAT_CARRLOST))) 2832 txstat &= ~DC_TXSTAT_ERRSUM; 2833 } 2834 2835 if (txstat & DC_TXSTAT_ERRSUM) { 2836 ifp->if_oerrors++; 2837 if (txstat & DC_TXSTAT_EXCESSCOLL) 2838 ifp->if_collisions++; 2839 if (txstat & DC_TXSTAT_LATECOLL) 2840 ifp->if_collisions++; 2841 if (!(txstat & DC_TXSTAT_UNDERRUN)) { 2842 dc_init_locked(sc); 2843 return; 2844 } 2845 } 2846 2847 ifp->if_collisions += (txstat & DC_TXSTAT_COLLCNT) >> 3; 2848 2849 ifp->if_opackets++; 2850 if (sc->dc_cdata.dc_tx_chain[idx] != NULL) { 2851 bus_dmamap_sync(sc->dc_mtag, 2852 sc->dc_cdata.dc_tx_map[idx], 2853 BUS_DMASYNC_POSTWRITE); 2854 bus_dmamap_unload(sc->dc_mtag, 2855 sc->dc_cdata.dc_tx_map[idx]); 2856 m_freem(sc->dc_cdata.dc_tx_chain[idx]); 2857 sc->dc_cdata.dc_tx_chain[idx] = NULL; 2858 } 2859 2860 sc->dc_cdata.dc_tx_cnt--; 2861 DC_INC(idx, DC_TX_LIST_CNT); 2862 } 2863 2864 if (idx != sc->dc_cdata.dc_tx_cons) { 2865 /* Some buffers have been freed. */ 2866 sc->dc_cdata.dc_tx_cons = idx; 2867 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 2868 } 2869 ifp->if_timer = (sc->dc_cdata.dc_tx_cnt == 0) ? 0 : 5; 2870 } 2871 2872 static void 2873 dc_tick(void *xsc) 2874 { 2875 struct dc_softc *sc; 2876 struct mii_data *mii; 2877 struct ifnet *ifp; 2878 u_int32_t r; 2879 2880 sc = xsc; 2881 DC_LOCK_ASSERT(sc); 2882 ifp = sc->dc_ifp; 2883 mii = device_get_softc(sc->dc_miibus); 2884 2885 if (sc->dc_flags & DC_REDUCED_MII_POLL) { 2886 if (sc->dc_flags & DC_21143_NWAY) { 2887 r = CSR_READ_4(sc, DC_10BTSTAT); 2888 if (IFM_SUBTYPE(mii->mii_media_active) == 2889 IFM_100_TX && (r & DC_TSTAT_LS100)) { 2890 sc->dc_link = 0; 2891 mii_mediachg(mii); 2892 } 2893 if (IFM_SUBTYPE(mii->mii_media_active) == 2894 IFM_10_T && (r & DC_TSTAT_LS10)) { 2895 sc->dc_link = 0; 2896 mii_mediachg(mii); 2897 } 2898 if (sc->dc_link == 0) 2899 mii_tick(mii); 2900 } else { 2901 r = CSR_READ_4(sc, DC_ISR); 2902 if ((r & DC_ISR_RX_STATE) == DC_RXSTATE_WAIT && 2903 sc->dc_cdata.dc_tx_cnt == 0) { 2904 mii_tick(mii); 2905 if (!(mii->mii_media_status & IFM_ACTIVE)) 2906 sc->dc_link = 0; 2907 } 2908 } 2909 } else 2910 mii_tick(mii); 2911 2912 /* 2913 * When the init routine completes, we expect to be able to send 2914 * packets right away, and in fact the network code will send a 2915 * gratuitous ARP the moment the init routine marks the interface 2916 * as running. However, even though the MAC may have been initialized, 2917 * there may be a delay of a few seconds before the PHY completes 2918 * autonegotiation and the link is brought up. Any transmissions 2919 * made during that delay will be lost. Dealing with this is tricky: 2920 * we can't just pause in the init routine while waiting for the 2921 * PHY to come ready since that would bring the whole system to 2922 * a screeching halt for several seconds. 2923 * 2924 * What we do here is prevent the TX start routine from sending 2925 * any packets until a link has been established. After the 2926 * interface has been initialized, the tick routine will poll 2927 * the state of the PHY until the IFM_ACTIVE flag is set. Until 2928 * that time, packets will stay in the send queue, and once the 2929 * link comes up, they will be flushed out to the wire. 2930 */ 2931 if (!sc->dc_link && mii->mii_media_status & IFM_ACTIVE && 2932 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) { 2933 sc->dc_link++; 2934 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 2935 dc_start_locked(ifp); 2936 } 2937 2938 if (sc->dc_flags & DC_21143_NWAY && !sc->dc_link) 2939 callout_reset(&sc->dc_stat_ch, hz/10, dc_tick, sc); 2940 else 2941 callout_reset(&sc->dc_stat_ch, hz, dc_tick, sc); 2942 } 2943 2944 /* 2945 * A transmit underrun has occurred. Back off the transmit threshold, 2946 * or switch to store and forward mode if we have to. 2947 */ 2948 static void 2949 dc_tx_underrun(struct dc_softc *sc) 2950 { 2951 u_int32_t isr; 2952 int i; 2953 2954 if (DC_IS_DAVICOM(sc)) 2955 dc_init_locked(sc); 2956 2957 if (DC_IS_INTEL(sc)) { 2958 /* 2959 * The real 21143 requires that the transmitter be idle 2960 * in order to change the transmit threshold or store 2961 * and forward state. 2962 */ 2963 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_TX_ON); 2964 2965 for (i = 0; i < DC_TIMEOUT; i++) { 2966 isr = CSR_READ_4(sc, DC_ISR); 2967 if (isr & DC_ISR_TX_IDLE) 2968 break; 2969 DELAY(10); 2970 } 2971 if (i == DC_TIMEOUT) { 2972 device_printf(sc->dc_dev, 2973 "failed to force tx to idle state\n"); 2974 dc_init_locked(sc); 2975 } 2976 } 2977 2978 device_printf(sc->dc_dev, "TX underrun -- "); 2979 sc->dc_txthresh += DC_TXTHRESH_INC; 2980 if (sc->dc_txthresh > DC_TXTHRESH_MAX) { 2981 printf("using store and forward mode\n"); 2982 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_STORENFWD); 2983 } else { 2984 printf("increasing TX threshold\n"); 2985 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_TX_THRESH); 2986 DC_SETBIT(sc, DC_NETCFG, sc->dc_txthresh); 2987 } 2988 2989 if (DC_IS_INTEL(sc)) 2990 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_TX_ON); 2991 } 2992 2993 #ifdef DEVICE_POLLING 2994 static poll_handler_t dc_poll; 2995 2996 static void 2997 dc_poll(struct ifnet *ifp, enum poll_cmd cmd, int count) 2998 { 2999 struct dc_softc *sc = ifp->if_softc; 3000 3001 DC_LOCK(sc); 3002 3003 if (!(ifp->if_drv_flags & IFF_DRV_RUNNING)) { 3004 DC_UNLOCK(sc); 3005 return; 3006 } 3007 3008 sc->rxcycles = count; 3009 dc_rxeof(sc); 3010 dc_txeof(sc); 3011 if (!IFQ_IS_EMPTY(&ifp->if_snd) && 3012 !(ifp->if_drv_flags & IFF_DRV_OACTIVE)) 3013 dc_start_locked(ifp); 3014 3015 if (cmd == POLL_AND_CHECK_STATUS) { /* also check status register */ 3016 u_int32_t status; 3017 3018 status = CSR_READ_4(sc, DC_ISR); 3019 status &= (DC_ISR_RX_WATDOGTIMEO | DC_ISR_RX_NOBUF | 3020 DC_ISR_TX_NOBUF | DC_ISR_TX_IDLE | DC_ISR_TX_UNDERRUN | 3021 DC_ISR_BUS_ERR); 3022 if (!status) { 3023 DC_UNLOCK(sc); 3024 return; 3025 } 3026 /* ack what we have */ 3027 CSR_WRITE_4(sc, DC_ISR, status); 3028 3029 if (status & (DC_ISR_RX_WATDOGTIMEO | DC_ISR_RX_NOBUF)) { 3030 u_int32_t r = CSR_READ_4(sc, DC_FRAMESDISCARDED); 3031 ifp->if_ierrors += (r & 0xffff) + ((r >> 17) & 0x7ff); 3032 3033 if (dc_rx_resync(sc)) 3034 dc_rxeof(sc); 3035 } 3036 /* restart transmit unit if necessary */ 3037 if (status & DC_ISR_TX_IDLE && sc->dc_cdata.dc_tx_cnt) 3038 CSR_WRITE_4(sc, DC_TXSTART, 0xFFFFFFFF); 3039 3040 if (status & DC_ISR_TX_UNDERRUN) 3041 dc_tx_underrun(sc); 3042 3043 if (status & DC_ISR_BUS_ERR) { 3044 if_printf(ifp, "%s: bus error\n", __func__); 3045 dc_reset(sc); 3046 dc_init_locked(sc); 3047 } 3048 } 3049 DC_UNLOCK(sc); 3050 } 3051 #endif /* DEVICE_POLLING */ 3052 3053 static void 3054 dc_intr(void *arg) 3055 { 3056 struct dc_softc *sc; 3057 struct ifnet *ifp; 3058 u_int32_t status; 3059 3060 sc = arg; 3061 3062 if (sc->suspended) 3063 return; 3064 3065 if ((CSR_READ_4(sc, DC_ISR) & DC_INTRS) == 0) 3066 return; 3067 3068 DC_LOCK(sc); 3069 ifp = sc->dc_ifp; 3070 #ifdef DEVICE_POLLING 3071 if (ifp->if_capenable & IFCAP_POLLING) { 3072 DC_UNLOCK(sc); 3073 return; 3074 } 3075 #endif 3076 3077 /* Suppress unwanted interrupts */ 3078 if (!(ifp->if_flags & IFF_UP)) { 3079 if (CSR_READ_4(sc, DC_ISR) & DC_INTRS) 3080 dc_stop(sc); 3081 DC_UNLOCK(sc); 3082 return; 3083 } 3084 3085 /* Disable interrupts. */ 3086 CSR_WRITE_4(sc, DC_IMR, 0x00000000); 3087 3088 while (((status = CSR_READ_4(sc, DC_ISR)) & DC_INTRS) && 3089 status != 0xFFFFFFFF && 3090 (ifp->if_drv_flags & IFF_DRV_RUNNING)) { 3091 3092 CSR_WRITE_4(sc, DC_ISR, status); 3093 3094 if (status & DC_ISR_RX_OK) { 3095 int curpkts; 3096 curpkts = ifp->if_ipackets; 3097 dc_rxeof(sc); 3098 if (curpkts == ifp->if_ipackets) { 3099 while (dc_rx_resync(sc)) 3100 dc_rxeof(sc); 3101 } 3102 } 3103 3104 if (status & (DC_ISR_TX_OK | DC_ISR_TX_NOBUF)) 3105 dc_txeof(sc); 3106 3107 if (status & DC_ISR_TX_IDLE) { 3108 dc_txeof(sc); 3109 if (sc->dc_cdata.dc_tx_cnt) { 3110 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_TX_ON); 3111 CSR_WRITE_4(sc, DC_TXSTART, 0xFFFFFFFF); 3112 } 3113 } 3114 3115 if (status & DC_ISR_TX_UNDERRUN) 3116 dc_tx_underrun(sc); 3117 3118 if ((status & DC_ISR_RX_WATDOGTIMEO) 3119 || (status & DC_ISR_RX_NOBUF)) { 3120 int curpkts; 3121 curpkts = ifp->if_ipackets; 3122 dc_rxeof(sc); 3123 if (curpkts == ifp->if_ipackets) { 3124 while (dc_rx_resync(sc)) 3125 dc_rxeof(sc); 3126 } 3127 } 3128 3129 if (status & DC_ISR_BUS_ERR) { 3130 dc_reset(sc); 3131 dc_init_locked(sc); 3132 } 3133 } 3134 3135 /* Re-enable interrupts. */ 3136 CSR_WRITE_4(sc, DC_IMR, DC_INTRS); 3137 3138 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 3139 dc_start_locked(ifp); 3140 3141 DC_UNLOCK(sc); 3142 } 3143 3144 static void 3145 dc_dma_map_txbuf(arg, segs, nseg, mapsize, error) 3146 void *arg; 3147 bus_dma_segment_t *segs; 3148 int nseg; 3149 bus_size_t mapsize; 3150 int error; 3151 { 3152 struct dc_softc *sc; 3153 struct dc_desc *f; 3154 int cur, first, frag, i; 3155 3156 sc = arg; 3157 if (error) { 3158 sc->dc_cdata.dc_tx_err = error; 3159 return; 3160 } 3161 3162 first = cur = frag = sc->dc_cdata.dc_tx_prod; 3163 for (i = 0; i < nseg; i++) { 3164 if ((sc->dc_flags & DC_TX_ADMTEK_WAR) && 3165 (frag == (DC_TX_LIST_CNT - 1)) && 3166 (first != sc->dc_cdata.dc_tx_first)) { 3167 bus_dmamap_unload(sc->dc_mtag, 3168 sc->dc_cdata.dc_tx_map[first]); 3169 sc->dc_cdata.dc_tx_err = ENOBUFS; 3170 return; 3171 } 3172 3173 f = &sc->dc_ldata->dc_tx_list[frag]; 3174 f->dc_ctl = htole32(DC_TXCTL_TLINK | segs[i].ds_len); 3175 if (i == 0) { 3176 f->dc_status = 0; 3177 f->dc_ctl |= htole32(DC_TXCTL_FIRSTFRAG); 3178 } else 3179 f->dc_status = htole32(DC_TXSTAT_OWN); 3180 f->dc_data = htole32(segs[i].ds_addr); 3181 cur = frag; 3182 DC_INC(frag, DC_TX_LIST_CNT); 3183 } 3184 3185 sc->dc_cdata.dc_tx_err = 0; 3186 sc->dc_cdata.dc_tx_prod = frag; 3187 sc->dc_cdata.dc_tx_cnt += nseg; 3188 sc->dc_ldata->dc_tx_list[cur].dc_ctl |= htole32(DC_TXCTL_LASTFRAG); 3189 sc->dc_cdata.dc_tx_chain[cur] = sc->dc_cdata.dc_tx_mapping; 3190 if (sc->dc_flags & DC_TX_INTR_FIRSTFRAG) 3191 sc->dc_ldata->dc_tx_list[first].dc_ctl |= 3192 htole32(DC_TXCTL_FINT); 3193 if (sc->dc_flags & DC_TX_INTR_ALWAYS) 3194 sc->dc_ldata->dc_tx_list[cur].dc_ctl |= htole32(DC_TXCTL_FINT); 3195 if (sc->dc_flags & DC_TX_USE_TX_INTR && sc->dc_cdata.dc_tx_cnt > 64) 3196 sc->dc_ldata->dc_tx_list[cur].dc_ctl |= htole32(DC_TXCTL_FINT); 3197 sc->dc_ldata->dc_tx_list[first].dc_status = htole32(DC_TXSTAT_OWN); 3198 } 3199 3200 /* 3201 * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data 3202 * pointers to the fragment pointers. 3203 */ 3204 static int 3205 dc_encap(struct dc_softc *sc, struct mbuf **m_head) 3206 { 3207 struct mbuf *m; 3208 int error, idx, chainlen = 0; 3209 3210 /* 3211 * If there's no way we can send any packets, return now. 3212 */ 3213 if (DC_TX_LIST_CNT - sc->dc_cdata.dc_tx_cnt < 6) 3214 return (ENOBUFS); 3215 3216 /* 3217 * Count the number of frags in this chain to see if 3218 * we need to m_defrag. Since the descriptor list is shared 3219 * by all packets, we'll m_defrag long chains so that they 3220 * do not use up the entire list, even if they would fit. 3221 */ 3222 for (m = *m_head; m != NULL; m = m->m_next) 3223 chainlen++; 3224 3225 if ((chainlen > DC_TX_LIST_CNT / 4) || 3226 ((DC_TX_LIST_CNT - (chainlen + sc->dc_cdata.dc_tx_cnt)) < 6)) { 3227 m = m_defrag(*m_head, M_DONTWAIT); 3228 if (m == NULL) 3229 return (ENOBUFS); 3230 *m_head = m; 3231 } 3232 3233 /* 3234 * Start packing the mbufs in this chain into 3235 * the fragment pointers. Stop when we run out 3236 * of fragments or hit the end of the mbuf chain. 3237 */ 3238 idx = sc->dc_cdata.dc_tx_prod; 3239 sc->dc_cdata.dc_tx_mapping = *m_head; 3240 error = bus_dmamap_load_mbuf(sc->dc_mtag, sc->dc_cdata.dc_tx_map[idx], 3241 *m_head, dc_dma_map_txbuf, sc, 0); 3242 if (error) 3243 return (error); 3244 if (sc->dc_cdata.dc_tx_err != 0) 3245 return (sc->dc_cdata.dc_tx_err); 3246 bus_dmamap_sync(sc->dc_mtag, sc->dc_cdata.dc_tx_map[idx], 3247 BUS_DMASYNC_PREWRITE); 3248 bus_dmamap_sync(sc->dc_ltag, sc->dc_lmap, 3249 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3250 return (0); 3251 } 3252 3253 /* 3254 * Main transmit routine. To avoid having to do mbuf copies, we put pointers 3255 * to the mbuf data regions directly in the transmit lists. We also save a 3256 * copy of the pointers since the transmit list fragment pointers are 3257 * physical addresses. 3258 */ 3259 3260 static void 3261 dc_start(struct ifnet *ifp) 3262 { 3263 struct dc_softc *sc; 3264 3265 sc = ifp->if_softc; 3266 DC_LOCK(sc); 3267 dc_start_locked(ifp); 3268 DC_UNLOCK(sc); 3269 } 3270 3271 static void 3272 dc_start_locked(struct ifnet *ifp) 3273 { 3274 struct dc_softc *sc; 3275 struct mbuf *m_head = NULL, *m; 3276 unsigned int queued = 0; 3277 int idx; 3278 3279 sc = ifp->if_softc; 3280 3281 DC_LOCK_ASSERT(sc); 3282 3283 if (!sc->dc_link && ifp->if_snd.ifq_len < 10) 3284 return; 3285 3286 if (ifp->if_drv_flags & IFF_DRV_OACTIVE) 3287 return; 3288 3289 idx = sc->dc_cdata.dc_tx_first = sc->dc_cdata.dc_tx_prod; 3290 3291 while (sc->dc_cdata.dc_tx_chain[idx] == NULL) { 3292 IFQ_DRV_DEQUEUE(&ifp->if_snd, m_head); 3293 if (m_head == NULL) 3294 break; 3295 3296 if (sc->dc_flags & DC_TX_COALESCE && 3297 (m_head->m_next != NULL || 3298 sc->dc_flags & DC_TX_ALIGN)) { 3299 m = m_defrag(m_head, M_DONTWAIT); 3300 if (m == NULL) { 3301 IFQ_DRV_PREPEND(&ifp->if_snd, m_head); 3302 ifp->if_drv_flags |= IFF_DRV_OACTIVE; 3303 break; 3304 } else { 3305 m_head = m; 3306 } 3307 } 3308 3309 if (dc_encap(sc, &m_head)) { 3310 IFQ_DRV_PREPEND(&ifp->if_snd, m_head); 3311 ifp->if_drv_flags |= IFF_DRV_OACTIVE; 3312 break; 3313 } 3314 idx = sc->dc_cdata.dc_tx_prod; 3315 3316 queued++; 3317 /* 3318 * If there's a BPF listener, bounce a copy of this frame 3319 * to him. 3320 */ 3321 BPF_MTAP(ifp, m_head); 3322 3323 if (sc->dc_flags & DC_TX_ONE) { 3324 ifp->if_drv_flags |= IFF_DRV_OACTIVE; 3325 break; 3326 } 3327 } 3328 3329 if (queued > 0) { 3330 /* Transmit */ 3331 if (!(sc->dc_flags & DC_TX_POLL)) 3332 CSR_WRITE_4(sc, DC_TXSTART, 0xFFFFFFFF); 3333 3334 /* 3335 * Set a timeout in case the chip goes out to lunch. 3336 */ 3337 ifp->if_timer = 5; 3338 } 3339 } 3340 3341 static void 3342 dc_init(void *xsc) 3343 { 3344 struct dc_softc *sc = xsc; 3345 3346 DC_LOCK(sc); 3347 dc_init_locked(sc); 3348 DC_UNLOCK(sc); 3349 } 3350 3351 static void 3352 dc_init_locked(struct dc_softc *sc) 3353 { 3354 struct ifnet *ifp = sc->dc_ifp; 3355 struct mii_data *mii; 3356 3357 DC_LOCK_ASSERT(sc); 3358 3359 mii = device_get_softc(sc->dc_miibus); 3360 3361 /* 3362 * Cancel pending I/O and free all RX/TX buffers. 3363 */ 3364 dc_stop(sc); 3365 dc_reset(sc); 3366 3367 /* 3368 * Set cache alignment and burst length. 3369 */ 3370 if (DC_IS_ASIX(sc) || DC_IS_DAVICOM(sc)) 3371 CSR_WRITE_4(sc, DC_BUSCTL, 0); 3372 else 3373 CSR_WRITE_4(sc, DC_BUSCTL, DC_BUSCTL_MRME | DC_BUSCTL_MRLE); 3374 /* 3375 * Evenly share the bus between receive and transmit process. 3376 */ 3377 if (DC_IS_INTEL(sc)) 3378 DC_SETBIT(sc, DC_BUSCTL, DC_BUSCTL_ARBITRATION); 3379 if (DC_IS_DAVICOM(sc) || DC_IS_INTEL(sc)) { 3380 DC_SETBIT(sc, DC_BUSCTL, DC_BURSTLEN_USECA); 3381 } else { 3382 DC_SETBIT(sc, DC_BUSCTL, DC_BURSTLEN_16LONG); 3383 } 3384 if (sc->dc_flags & DC_TX_POLL) 3385 DC_SETBIT(sc, DC_BUSCTL, DC_TXPOLL_1); 3386 switch(sc->dc_cachesize) { 3387 case 32: 3388 DC_SETBIT(sc, DC_BUSCTL, DC_CACHEALIGN_32LONG); 3389 break; 3390 case 16: 3391 DC_SETBIT(sc, DC_BUSCTL, DC_CACHEALIGN_16LONG); 3392 break; 3393 case 8: 3394 DC_SETBIT(sc, DC_BUSCTL, DC_CACHEALIGN_8LONG); 3395 break; 3396 case 0: 3397 default: 3398 DC_SETBIT(sc, DC_BUSCTL, DC_CACHEALIGN_NONE); 3399 break; 3400 } 3401 3402 if (sc->dc_flags & DC_TX_STORENFWD) 3403 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_STORENFWD); 3404 else { 3405 if (sc->dc_txthresh > DC_TXTHRESH_MAX) { 3406 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_STORENFWD); 3407 } else { 3408 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_STORENFWD); 3409 DC_SETBIT(sc, DC_NETCFG, sc->dc_txthresh); 3410 } 3411 } 3412 3413 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_NO_RXCRC); 3414 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_TX_BACKOFF); 3415 3416 if (DC_IS_MACRONIX(sc) || DC_IS_PNICII(sc)) { 3417 /* 3418 * The app notes for the 98713 and 98715A say that 3419 * in order to have the chips operate properly, a magic 3420 * number must be written to CSR16. Macronix does not 3421 * document the meaning of these bits so there's no way 3422 * to know exactly what they do. The 98713 has a magic 3423 * number all its own; the rest all use a different one. 3424 */ 3425 DC_CLRBIT(sc, DC_MX_MAGICPACKET, 0xFFFF0000); 3426 if (sc->dc_type == DC_TYPE_98713) 3427 DC_SETBIT(sc, DC_MX_MAGICPACKET, DC_MX_MAGIC_98713); 3428 else 3429 DC_SETBIT(sc, DC_MX_MAGICPACKET, DC_MX_MAGIC_98715); 3430 } 3431 3432 if (DC_IS_XIRCOM(sc)) { 3433 /* 3434 * setup General Purpose Port mode and data so the tulip 3435 * can talk to the MII. 3436 */ 3437 CSR_WRITE_4(sc, DC_SIAGP, DC_SIAGP_WRITE_EN | DC_SIAGP_INT1_EN | 3438 DC_SIAGP_MD_GP2_OUTPUT | DC_SIAGP_MD_GP0_OUTPUT); 3439 DELAY(10); 3440 CSR_WRITE_4(sc, DC_SIAGP, DC_SIAGP_INT1_EN | 3441 DC_SIAGP_MD_GP2_OUTPUT | DC_SIAGP_MD_GP0_OUTPUT); 3442 DELAY(10); 3443 } 3444 3445 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_TX_THRESH); 3446 DC_SETBIT(sc, DC_NETCFG, DC_TXTHRESH_MIN); 3447 3448 /* Init circular RX list. */ 3449 if (dc_list_rx_init(sc) == ENOBUFS) { 3450 device_printf(sc->dc_dev, 3451 "initialization failed: no memory for rx buffers\n"); 3452 dc_stop(sc); 3453 return; 3454 } 3455 3456 /* 3457 * Init TX descriptors. 3458 */ 3459 dc_list_tx_init(sc); 3460 3461 /* 3462 * Load the address of the RX list. 3463 */ 3464 CSR_WRITE_4(sc, DC_RXADDR, DC_RXDESC(sc, 0)); 3465 CSR_WRITE_4(sc, DC_TXADDR, DC_TXDESC(sc, 0)); 3466 3467 /* 3468 * Enable interrupts. 3469 */ 3470 #ifdef DEVICE_POLLING 3471 /* 3472 * ... but only if we are not polling, and make sure they are off in 3473 * the case of polling. Some cards (e.g. fxp) turn interrupts on 3474 * after a reset. 3475 */ 3476 if (ifp->if_capenable & IFCAP_POLLING) 3477 CSR_WRITE_4(sc, DC_IMR, 0x00000000); 3478 else 3479 #endif 3480 CSR_WRITE_4(sc, DC_IMR, DC_INTRS); 3481 CSR_WRITE_4(sc, DC_ISR, 0xFFFFFFFF); 3482 3483 /* Enable transmitter. */ 3484 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_TX_ON); 3485 3486 /* 3487 * If this is an Intel 21143 and we're not using the 3488 * MII port, program the LED control pins so we get 3489 * link and activity indications. 3490 */ 3491 if (sc->dc_flags & DC_TULIP_LEDS) { 3492 CSR_WRITE_4(sc, DC_WATCHDOG, 3493 DC_WDOG_CTLWREN | DC_WDOG_LINK | DC_WDOG_ACTIVITY); 3494 CSR_WRITE_4(sc, DC_WATCHDOG, 0); 3495 } 3496 3497 /* 3498 * Load the RX/multicast filter. We do this sort of late 3499 * because the filter programming scheme on the 21143 and 3500 * some clones requires DMAing a setup frame via the TX 3501 * engine, and we need the transmitter enabled for that. 3502 */ 3503 dc_setfilt(sc); 3504 3505 /* Enable receiver. */ 3506 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_ON); 3507 CSR_WRITE_4(sc, DC_RXSTART, 0xFFFFFFFF); 3508 3509 mii_mediachg(mii); 3510 dc_setcfg(sc, sc->dc_if_media); 3511 3512 ifp->if_drv_flags |= IFF_DRV_RUNNING; 3513 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 3514 3515 /* Don't start the ticker if this is a homePNA link. */ 3516 if (IFM_SUBTYPE(mii->mii_media.ifm_media) == IFM_HPNA_1) 3517 sc->dc_link = 1; 3518 else { 3519 if (sc->dc_flags & DC_21143_NWAY) 3520 callout_reset(&sc->dc_stat_ch, hz/10, dc_tick, sc); 3521 else 3522 callout_reset(&sc->dc_stat_ch, hz, dc_tick, sc); 3523 } 3524 } 3525 3526 /* 3527 * Set media options. 3528 */ 3529 static int 3530 dc_ifmedia_upd(struct ifnet *ifp) 3531 { 3532 struct dc_softc *sc; 3533 struct mii_data *mii; 3534 struct ifmedia *ifm; 3535 3536 sc = ifp->if_softc; 3537 mii = device_get_softc(sc->dc_miibus); 3538 DC_LOCK(sc); 3539 mii_mediachg(mii); 3540 ifm = &mii->mii_media; 3541 3542 if (DC_IS_DAVICOM(sc) && 3543 IFM_SUBTYPE(ifm->ifm_media) == IFM_HPNA_1) 3544 dc_setcfg(sc, ifm->ifm_media); 3545 else 3546 sc->dc_link = 0; 3547 DC_UNLOCK(sc); 3548 3549 return (0); 3550 } 3551 3552 /* 3553 * Report current media status. 3554 */ 3555 static void 3556 dc_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 3557 { 3558 struct dc_softc *sc; 3559 struct mii_data *mii; 3560 struct ifmedia *ifm; 3561 3562 sc = ifp->if_softc; 3563 mii = device_get_softc(sc->dc_miibus); 3564 DC_LOCK(sc); 3565 mii_pollstat(mii); 3566 ifm = &mii->mii_media; 3567 if (DC_IS_DAVICOM(sc)) { 3568 if (IFM_SUBTYPE(ifm->ifm_media) == IFM_HPNA_1) { 3569 ifmr->ifm_active = ifm->ifm_media; 3570 ifmr->ifm_status = 0; 3571 return; 3572 } 3573 } 3574 ifmr->ifm_active = mii->mii_media_active; 3575 ifmr->ifm_status = mii->mii_media_status; 3576 DC_UNLOCK(sc); 3577 } 3578 3579 static int 3580 dc_ioctl(struct ifnet *ifp, u_long command, caddr_t data) 3581 { 3582 struct dc_softc *sc = ifp->if_softc; 3583 struct ifreq *ifr = (struct ifreq *)data; 3584 struct mii_data *mii; 3585 int error = 0; 3586 3587 switch (command) { 3588 case SIOCSIFFLAGS: 3589 DC_LOCK(sc); 3590 if (ifp->if_flags & IFF_UP) { 3591 int need_setfilt = (ifp->if_flags ^ sc->dc_if_flags) & 3592 (IFF_PROMISC | IFF_ALLMULTI); 3593 3594 if (ifp->if_drv_flags & IFF_DRV_RUNNING) { 3595 if (need_setfilt) 3596 dc_setfilt(sc); 3597 } else { 3598 sc->dc_txthresh = 0; 3599 dc_init_locked(sc); 3600 } 3601 } else { 3602 if (ifp->if_drv_flags & IFF_DRV_RUNNING) 3603 dc_stop(sc); 3604 } 3605 sc->dc_if_flags = ifp->if_flags; 3606 DC_UNLOCK(sc); 3607 error = 0; 3608 break; 3609 case SIOCADDMULTI: 3610 case SIOCDELMULTI: 3611 DC_LOCK(sc); 3612 dc_setfilt(sc); 3613 DC_UNLOCK(sc); 3614 error = 0; 3615 break; 3616 case SIOCGIFMEDIA: 3617 case SIOCSIFMEDIA: 3618 mii = device_get_softc(sc->dc_miibus); 3619 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 3620 break; 3621 case SIOCSIFCAP: 3622 #ifdef DEVICE_POLLING 3623 if (ifr->ifr_reqcap & IFCAP_POLLING && 3624 !(ifp->if_capenable & IFCAP_POLLING)) { 3625 error = ether_poll_register(dc_poll, ifp); 3626 if (error) 3627 return(error); 3628 DC_LOCK(sc); 3629 /* Disable interrupts */ 3630 CSR_WRITE_4(sc, DC_IMR, 0x00000000); 3631 ifp->if_capenable |= IFCAP_POLLING; 3632 DC_UNLOCK(sc); 3633 return (error); 3634 3635 } 3636 if (!(ifr->ifr_reqcap & IFCAP_POLLING) && 3637 ifp->if_capenable & IFCAP_POLLING) { 3638 error = ether_poll_deregister(ifp); 3639 /* Enable interrupts. */ 3640 DC_LOCK(sc); 3641 CSR_WRITE_4(sc, DC_IMR, DC_INTRS); 3642 ifp->if_capenable &= ~IFCAP_POLLING; 3643 DC_UNLOCK(sc); 3644 return (error); 3645 } 3646 #endif /* DEVICE_POLLING */ 3647 break; 3648 default: 3649 error = ether_ioctl(ifp, command, data); 3650 break; 3651 } 3652 3653 return (error); 3654 } 3655 3656 static void 3657 dc_watchdog(struct ifnet *ifp) 3658 { 3659 struct dc_softc *sc; 3660 3661 sc = ifp->if_softc; 3662 3663 DC_LOCK(sc); 3664 3665 ifp->if_oerrors++; 3666 if_printf(ifp, "watchdog timeout\n"); 3667 3668 dc_stop(sc); 3669 dc_reset(sc); 3670 dc_init_locked(sc); 3671 3672 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 3673 dc_start_locked(ifp); 3674 3675 DC_UNLOCK(sc); 3676 } 3677 3678 /* 3679 * Stop the adapter and free any mbufs allocated to the 3680 * RX and TX lists. 3681 */ 3682 static void 3683 dc_stop(struct dc_softc *sc) 3684 { 3685 struct ifnet *ifp; 3686 struct dc_list_data *ld; 3687 struct dc_chain_data *cd; 3688 int i; 3689 u_int32_t ctl; 3690 3691 DC_LOCK_ASSERT(sc); 3692 3693 ifp = sc->dc_ifp; 3694 ifp->if_timer = 0; 3695 ld = sc->dc_ldata; 3696 cd = &sc->dc_cdata; 3697 3698 callout_stop(&sc->dc_stat_ch); 3699 3700 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE); 3701 3702 DC_CLRBIT(sc, DC_NETCFG, (DC_NETCFG_RX_ON | DC_NETCFG_TX_ON)); 3703 CSR_WRITE_4(sc, DC_IMR, 0x00000000); 3704 CSR_WRITE_4(sc, DC_TXADDR, 0x00000000); 3705 CSR_WRITE_4(sc, DC_RXADDR, 0x00000000); 3706 sc->dc_link = 0; 3707 3708 /* 3709 * Free data in the RX lists. 3710 */ 3711 for (i = 0; i < DC_RX_LIST_CNT; i++) { 3712 if (cd->dc_rx_chain[i] != NULL) { 3713 m_freem(cd->dc_rx_chain[i]); 3714 cd->dc_rx_chain[i] = NULL; 3715 } 3716 } 3717 bzero(&ld->dc_rx_list, sizeof(ld->dc_rx_list)); 3718 3719 /* 3720 * Free the TX list buffers. 3721 */ 3722 for (i = 0; i < DC_TX_LIST_CNT; i++) { 3723 if (cd->dc_tx_chain[i] != NULL) { 3724 ctl = le32toh(ld->dc_tx_list[i].dc_ctl); 3725 if ((ctl & DC_TXCTL_SETUP) || 3726 !(ctl & DC_TXCTL_LASTFRAG)) { 3727 cd->dc_tx_chain[i] = NULL; 3728 continue; 3729 } 3730 bus_dmamap_unload(sc->dc_mtag, cd->dc_tx_map[i]); 3731 m_freem(cd->dc_tx_chain[i]); 3732 cd->dc_tx_chain[i] = NULL; 3733 } 3734 } 3735 bzero(&ld->dc_tx_list, sizeof(ld->dc_tx_list)); 3736 } 3737 3738 /* 3739 * Device suspend routine. Stop the interface and save some PCI 3740 * settings in case the BIOS doesn't restore them properly on 3741 * resume. 3742 */ 3743 static int 3744 dc_suspend(device_t dev) 3745 { 3746 struct dc_softc *sc; 3747 3748 sc = device_get_softc(dev); 3749 DC_LOCK(sc); 3750 dc_stop(sc); 3751 sc->suspended = 1; 3752 DC_UNLOCK(sc); 3753 3754 return (0); 3755 } 3756 3757 /* 3758 * Device resume routine. Restore some PCI settings in case the BIOS 3759 * doesn't, re-enable busmastering, and restart the interface if 3760 * appropriate. 3761 */ 3762 static int 3763 dc_resume(device_t dev) 3764 { 3765 struct dc_softc *sc; 3766 struct ifnet *ifp; 3767 3768 sc = device_get_softc(dev); 3769 ifp = sc->dc_ifp; 3770 3771 /* reinitialize interface if necessary */ 3772 DC_LOCK(sc); 3773 if (ifp->if_flags & IFF_UP) 3774 dc_init_locked(sc); 3775 3776 sc->suspended = 0; 3777 DC_UNLOCK(sc); 3778 3779 return (0); 3780 } 3781 3782 /* 3783 * Stop all chip I/O so that the kernel's probe routines don't 3784 * get confused by errant DMAs when rebooting. 3785 */ 3786 static void 3787 dc_shutdown(device_t dev) 3788 { 3789 struct dc_softc *sc; 3790 3791 sc = device_get_softc(dev); 3792 3793 DC_LOCK(sc); 3794 dc_stop(sc); 3795 DC_UNLOCK(sc); 3796 } 3797