1 /* 2 * Copyright (c) 1997, 1998, 1999 3 * Bill Paul <wpaul@ee.columbia.edu>. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 3. All advertising materials mentioning features or use of this software 14 * must display the following acknowledgement: 15 * This product includes software developed by Bill Paul. 16 * 4. Neither the name of the author nor the names of any co-contributors 17 * may be used to endorse or promote products derived from this software 18 * without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30 * THE POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33 #include <sys/cdefs.h> 34 __FBSDID("$FreeBSD$"); 35 36 /* 37 * DEC "tulip" clone ethernet driver. Supports the DEC/Intel 21143 38 * series chips and several workalikes including the following: 39 * 40 * Macronix 98713/98715/98725/98727/98732 PMAC (www.macronix.com) 41 * Macronix/Lite-On 82c115 PNIC II (www.macronix.com) 42 * Lite-On 82c168/82c169 PNIC (www.litecom.com) 43 * ASIX Electronics AX88140A (www.asix.com.tw) 44 * ASIX Electronics AX88141 (www.asix.com.tw) 45 * ADMtek AL981 (www.admtek.com.tw) 46 * ADMtek AN985 (www.admtek.com.tw) 47 * Netgear FA511 (www.netgear.com) Appears to be rebadged ADMTek AN985 48 * Davicom DM9100, DM9102, DM9102A (www.davicom8.com) 49 * Accton EN1217 (www.accton.com) 50 * Xircom X3201 (www.xircom.com) 51 * Abocom FE2500 52 * Conexant LANfinity (www.conexant.com) 53 * 3Com OfficeConnect 10/100B 3CSOHO100B (www.3com.com) 54 * 55 * Datasheets for the 21143 are available at developer.intel.com. 56 * Datasheets for the clone parts can be found at their respective sites. 57 * (Except for the PNIC; see www.freebsd.org/~wpaul/PNIC/pnic.ps.gz.) 58 * The PNIC II is essentially a Macronix 98715A chip; the only difference 59 * worth noting is that its multicast hash table is only 128 bits wide 60 * instead of 512. 61 * 62 * Written by Bill Paul <wpaul@ee.columbia.edu> 63 * Electrical Engineering Department 64 * Columbia University, New York City 65 */ 66 /* 67 * The Intel 21143 is the successor to the DEC 21140. It is basically 68 * the same as the 21140 but with a few new features. The 21143 supports 69 * three kinds of media attachments: 70 * 71 * o MII port, for 10Mbps and 100Mbps support and NWAY 72 * autonegotiation provided by an external PHY. 73 * o SYM port, for symbol mode 100Mbps support. 74 * o 10baseT port. 75 * o AUI/BNC port. 76 * 77 * The 100Mbps SYM port and 10baseT port can be used together in 78 * combination with the internal NWAY support to create a 10/100 79 * autosensing configuration. 80 * 81 * Note that not all tulip workalikes are handled in this driver: we only 82 * deal with those which are relatively well behaved. The Winbond is 83 * handled separately due to its different register offsets and the 84 * special handling needed for its various bugs. The PNIC is handled 85 * here, but I'm not thrilled about it. 86 * 87 * All of the workalike chips use some form of MII transceiver support 88 * with the exception of the Macronix chips, which also have a SYM port. 89 * The ASIX AX88140A is also documented to have a SYM port, but all 90 * the cards I've seen use an MII transceiver, probably because the 91 * AX88140A doesn't support internal NWAY. 92 */ 93 94 #include <sys/param.h> 95 #include <sys/endian.h> 96 #include <sys/systm.h> 97 #include <sys/sockio.h> 98 #include <sys/mbuf.h> 99 #include <sys/malloc.h> 100 #include <sys/kernel.h> 101 #include <sys/socket.h> 102 #include <sys/sysctl.h> 103 104 #include <net/if.h> 105 #include <net/if_arp.h> 106 #include <net/ethernet.h> 107 #include <net/if_dl.h> 108 #include <net/if_media.h> 109 #include <net/if_types.h> 110 #include <net/if_vlan_var.h> 111 112 #include <net/bpf.h> 113 114 #include <machine/bus_pio.h> 115 #include <machine/bus_memio.h> 116 #include <machine/bus.h> 117 #include <machine/resource.h> 118 #include <sys/bus.h> 119 #include <sys/rman.h> 120 121 #include <dev/mii/mii.h> 122 #include <dev/mii/miivar.h> 123 124 #include <dev/pci/pcireg.h> 125 #include <dev/pci/pcivar.h> 126 127 #define DC_USEIOSPACE 128 #ifdef __alpha__ 129 #define SRM_MEDIA 130 #endif 131 132 #include <pci/if_dcreg.h> 133 134 #ifdef __sparc64__ 135 #include <dev/ofw/openfirm.h> 136 #include <machine/ofw_machdep.h> 137 #endif 138 139 MODULE_DEPEND(dc, pci, 1, 1, 1); 140 MODULE_DEPEND(dc, ether, 1, 1, 1); 141 MODULE_DEPEND(dc, miibus, 1, 1, 1); 142 143 /* "controller miibus0" required. See GENERIC if you get errors here. */ 144 #include "miibus_if.h" 145 146 /* 147 * Various supported device vendors/types and their names. 148 */ 149 static struct dc_type dc_devs[] = { 150 { DC_VENDORID_DEC, DC_DEVICEID_21143, 151 "Intel 21143 10/100BaseTX" }, 152 { DC_VENDORID_DAVICOM, DC_DEVICEID_DM9009, 153 "Davicom DM9009 10/100BaseTX" }, 154 { DC_VENDORID_DAVICOM, DC_DEVICEID_DM9100, 155 "Davicom DM9100 10/100BaseTX" }, 156 { DC_VENDORID_DAVICOM, DC_DEVICEID_DM9102, 157 "Davicom DM9102 10/100BaseTX" }, 158 { DC_VENDORID_DAVICOM, DC_DEVICEID_DM9102, 159 "Davicom DM9102A 10/100BaseTX" }, 160 { DC_VENDORID_ADMTEK, DC_DEVICEID_AL981, 161 "ADMtek AL981 10/100BaseTX" }, 162 { DC_VENDORID_ADMTEK, DC_DEVICEID_AN985, 163 "ADMtek AN985 10/100BaseTX" }, 164 { DC_VENDORID_ADMTEK, DC_DEVICEID_ADM9511, 165 "ADMtek ADM9511 10/100BaseTX" }, 166 { DC_VENDORID_ADMTEK, DC_DEVICEID_ADM9513, 167 "ADMtek ADM9513 10/100BaseTX" }, 168 { DC_VENDORID_ADMTEK, DC_DEVICEID_FA511, 169 "Netgear FA511 10/100BaseTX" }, 170 { DC_VENDORID_ASIX, DC_DEVICEID_AX88140A, 171 "ASIX AX88140A 10/100BaseTX" }, 172 { DC_VENDORID_ASIX, DC_DEVICEID_AX88140A, 173 "ASIX AX88141 10/100BaseTX" }, 174 { DC_VENDORID_MX, DC_DEVICEID_98713, 175 "Macronix 98713 10/100BaseTX" }, 176 { DC_VENDORID_MX, DC_DEVICEID_98713, 177 "Macronix 98713A 10/100BaseTX" }, 178 { DC_VENDORID_CP, DC_DEVICEID_98713_CP, 179 "Compex RL100-TX 10/100BaseTX" }, 180 { DC_VENDORID_CP, DC_DEVICEID_98713_CP, 181 "Compex RL100-TX 10/100BaseTX" }, 182 { DC_VENDORID_MX, DC_DEVICEID_987x5, 183 "Macronix 98715/98715A 10/100BaseTX" }, 184 { DC_VENDORID_MX, DC_DEVICEID_987x5, 185 "Macronix 98715AEC-C 10/100BaseTX" }, 186 { DC_VENDORID_MX, DC_DEVICEID_987x5, 187 "Macronix 98725 10/100BaseTX" }, 188 { DC_VENDORID_MX, DC_DEVICEID_98727, 189 "Macronix 98727/98732 10/100BaseTX" }, 190 { DC_VENDORID_LO, DC_DEVICEID_82C115, 191 "LC82C115 PNIC II 10/100BaseTX" }, 192 { DC_VENDORID_LO, DC_DEVICEID_82C168, 193 "82c168 PNIC 10/100BaseTX" }, 194 { DC_VENDORID_LO, DC_DEVICEID_82C168, 195 "82c169 PNIC 10/100BaseTX" }, 196 { DC_VENDORID_ACCTON, DC_DEVICEID_EN1217, 197 "Accton EN1217 10/100BaseTX" }, 198 { DC_VENDORID_ACCTON, DC_DEVICEID_EN2242, 199 "Accton EN2242 MiniPCI 10/100BaseTX" }, 200 { DC_VENDORID_XIRCOM, DC_DEVICEID_X3201, 201 "Xircom X3201 10/100BaseTX" }, 202 { DC_VENDORID_ABOCOM, DC_DEVICEID_FE2500, 203 "Abocom FE2500 10/100BaseTX" }, 204 { DC_VENDORID_ABOCOM, DC_DEVICEID_FE2500MX, 205 "Abocom FE2500MX 10/100BaseTX" }, 206 { DC_VENDORID_CONEXANT, DC_DEVICEID_RS7112, 207 "Conexant LANfinity MiniPCI 10/100BaseTX" }, 208 { DC_VENDORID_HAWKING, DC_DEVICEID_HAWKING_PN672TX, 209 "Hawking CB102 CardBus 10/100" }, 210 { DC_VENDORID_PLANEX, DC_DEVICEID_FNW3602T, 211 "PlaneX FNW-3602-T CardBus 10/100" }, 212 { DC_VENDORID_3COM, DC_DEVICEID_3CSOHOB, 213 "3Com OfficeConnect 10/100B" }, 214 { DC_VENDORID_MICROSOFT, DC_DEVICEID_MSMN120, 215 "Microsoft MN-120 CardBus 10/100" }, 216 { DC_VENDORID_MICROSOFT, DC_DEVICEID_MSMN130, 217 "Microsoft MN-130 10/100" }, 218 { DC_VENDORID_MICROSOFT, DC_DEVICEID_MSMN130_FAKE, 219 "Microsoft MN-130 10/100" }, 220 { 0, 0, NULL } 221 }; 222 223 static int dc_probe (device_t); 224 static int dc_attach (device_t); 225 static int dc_detach (device_t); 226 static int dc_suspend (device_t); 227 static int dc_resume (device_t); 228 #ifndef BURN_BRIDGES 229 static void dc_acpi (device_t); 230 #endif 231 static struct dc_type *dc_devtype (device_t); 232 static int dc_newbuf (struct dc_softc *, int, int); 233 static int dc_encap (struct dc_softc *, struct mbuf **); 234 static void dc_pnic_rx_bug_war (struct dc_softc *, int); 235 static int dc_rx_resync (struct dc_softc *); 236 static void dc_rxeof (struct dc_softc *); 237 static void dc_txeof (struct dc_softc *); 238 static void dc_tick (void *); 239 static void dc_tx_underrun (struct dc_softc *); 240 static void dc_intr (void *); 241 static void dc_start (struct ifnet *); 242 static int dc_ioctl (struct ifnet *, u_long, caddr_t); 243 static void dc_init (void *); 244 static void dc_stop (struct dc_softc *); 245 static void dc_watchdog (struct ifnet *); 246 static void dc_shutdown (device_t); 247 static int dc_ifmedia_upd (struct ifnet *); 248 static void dc_ifmedia_sts (struct ifnet *, struct ifmediareq *); 249 250 static void dc_delay (struct dc_softc *); 251 static void dc_eeprom_idle (struct dc_softc *); 252 static void dc_eeprom_putbyte (struct dc_softc *, int); 253 static void dc_eeprom_getword (struct dc_softc *, int, u_int16_t *); 254 static void dc_eeprom_getword_pnic 255 (struct dc_softc *, int, u_int16_t *); 256 static void dc_eeprom_getword_xircom 257 (struct dc_softc *, int, u_int16_t *); 258 static void dc_eeprom_width (struct dc_softc *); 259 static void dc_read_eeprom (struct dc_softc *, caddr_t, int, int, int); 260 261 static void dc_mii_writebit (struct dc_softc *, int); 262 static int dc_mii_readbit (struct dc_softc *); 263 static void dc_mii_sync (struct dc_softc *); 264 static void dc_mii_send (struct dc_softc *, u_int32_t, int); 265 static int dc_mii_readreg (struct dc_softc *, struct dc_mii_frame *); 266 static int dc_mii_writereg (struct dc_softc *, struct dc_mii_frame *); 267 static int dc_miibus_readreg (device_t, int, int); 268 static int dc_miibus_writereg (device_t, int, int, int); 269 static void dc_miibus_statchg (device_t); 270 static void dc_miibus_mediainit (device_t); 271 272 static void dc_setcfg (struct dc_softc *, int); 273 static uint32_t dc_mchash_le (struct dc_softc *, const uint8_t *); 274 static uint32_t dc_mchash_be (const uint8_t *); 275 static void dc_setfilt_21143 (struct dc_softc *); 276 static void dc_setfilt_asix (struct dc_softc *); 277 static void dc_setfilt_admtek (struct dc_softc *); 278 static void dc_setfilt_xircom (struct dc_softc *); 279 280 static void dc_setfilt (struct dc_softc *); 281 282 static void dc_reset (struct dc_softc *); 283 static int dc_list_rx_init (struct dc_softc *); 284 static int dc_list_tx_init (struct dc_softc *); 285 286 static void dc_read_srom (struct dc_softc *, int); 287 static void dc_parse_21143_srom (struct dc_softc *); 288 static void dc_decode_leaf_sia (struct dc_softc *, struct dc_eblock_sia *); 289 static void dc_decode_leaf_mii (struct dc_softc *, struct dc_eblock_mii *); 290 static void dc_decode_leaf_sym (struct dc_softc *, struct dc_eblock_sym *); 291 static void dc_apply_fixup (struct dc_softc *, int); 292 293 static void dc_dma_map_txbuf (void *, bus_dma_segment_t *, int, bus_size_t, 294 int); 295 static void dc_dma_map_rxbuf (void *, bus_dma_segment_t *, int, bus_size_t, 296 int); 297 298 #ifdef DC_USEIOSPACE 299 #define DC_RES SYS_RES_IOPORT 300 #define DC_RID DC_PCI_CFBIO 301 #else 302 #define DC_RES SYS_RES_MEMORY 303 #define DC_RID DC_PCI_CFBMA 304 #endif 305 306 static device_method_t dc_methods[] = { 307 /* Device interface */ 308 DEVMETHOD(device_probe, dc_probe), 309 DEVMETHOD(device_attach, dc_attach), 310 DEVMETHOD(device_detach, dc_detach), 311 DEVMETHOD(device_suspend, dc_suspend), 312 DEVMETHOD(device_resume, dc_resume), 313 DEVMETHOD(device_shutdown, dc_shutdown), 314 315 /* bus interface */ 316 DEVMETHOD(bus_print_child, bus_generic_print_child), 317 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 318 319 /* MII interface */ 320 DEVMETHOD(miibus_readreg, dc_miibus_readreg), 321 DEVMETHOD(miibus_writereg, dc_miibus_writereg), 322 DEVMETHOD(miibus_statchg, dc_miibus_statchg), 323 DEVMETHOD(miibus_mediainit, dc_miibus_mediainit), 324 325 { 0, 0 } 326 }; 327 328 static driver_t dc_driver = { 329 "dc", 330 dc_methods, 331 sizeof(struct dc_softc) 332 }; 333 334 static devclass_t dc_devclass; 335 #ifdef __i386__ 336 static int dc_quick = 1; 337 SYSCTL_INT(_hw, OID_AUTO, dc_quick, CTLFLAG_RW, &dc_quick, 0, 338 "do not m_devget() in dc driver"); 339 #endif 340 341 DRIVER_MODULE(dc, cardbus, dc_driver, dc_devclass, 0, 0); 342 DRIVER_MODULE(dc, pci, dc_driver, dc_devclass, 0, 0); 343 DRIVER_MODULE(miibus, dc, miibus_driver, miibus_devclass, 0, 0); 344 345 #define DC_SETBIT(sc, reg, x) \ 346 CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) | (x)) 347 348 #define DC_CLRBIT(sc, reg, x) \ 349 CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) & ~(x)) 350 351 #define SIO_SET(x) DC_SETBIT(sc, DC_SIO, (x)) 352 #define SIO_CLR(x) DC_CLRBIT(sc, DC_SIO, (x)) 353 354 #define IS_MPSAFE 0 355 356 static void 357 dc_delay(struct dc_softc *sc) 358 { 359 int idx; 360 361 for (idx = (300 / 33) + 1; idx > 0; idx--) 362 CSR_READ_4(sc, DC_BUSCTL); 363 } 364 365 static void 366 dc_eeprom_width(struct dc_softc *sc) 367 { 368 int i; 369 370 /* Force EEPROM to idle state. */ 371 dc_eeprom_idle(sc); 372 373 /* Enter EEPROM access mode. */ 374 CSR_WRITE_4(sc, DC_SIO, DC_SIO_EESEL); 375 dc_delay(sc); 376 DC_SETBIT(sc, DC_SIO, DC_SIO_ROMCTL_READ); 377 dc_delay(sc); 378 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); 379 dc_delay(sc); 380 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CS); 381 dc_delay(sc); 382 383 for (i = 3; i--;) { 384 if (6 & (1 << i)) 385 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_DATAIN); 386 else 387 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_DATAIN); 388 dc_delay(sc); 389 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CLK); 390 dc_delay(sc); 391 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); 392 dc_delay(sc); 393 } 394 395 for (i = 1; i <= 12; i++) { 396 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CLK); 397 dc_delay(sc); 398 if (!(CSR_READ_4(sc, DC_SIO) & DC_SIO_EE_DATAOUT)) { 399 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); 400 dc_delay(sc); 401 break; 402 } 403 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); 404 dc_delay(sc); 405 } 406 407 /* Turn off EEPROM access mode. */ 408 dc_eeprom_idle(sc); 409 410 if (i < 4 || i > 12) 411 sc->dc_romwidth = 6; 412 else 413 sc->dc_romwidth = i; 414 415 /* Enter EEPROM access mode. */ 416 CSR_WRITE_4(sc, DC_SIO, DC_SIO_EESEL); 417 dc_delay(sc); 418 DC_SETBIT(sc, DC_SIO, DC_SIO_ROMCTL_READ); 419 dc_delay(sc); 420 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); 421 dc_delay(sc); 422 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CS); 423 dc_delay(sc); 424 425 /* Turn off EEPROM access mode. */ 426 dc_eeprom_idle(sc); 427 } 428 429 static void 430 dc_eeprom_idle(struct dc_softc *sc) 431 { 432 int i; 433 434 CSR_WRITE_4(sc, DC_SIO, DC_SIO_EESEL); 435 dc_delay(sc); 436 DC_SETBIT(sc, DC_SIO, DC_SIO_ROMCTL_READ); 437 dc_delay(sc); 438 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); 439 dc_delay(sc); 440 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CS); 441 dc_delay(sc); 442 443 for (i = 0; i < 25; i++) { 444 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); 445 dc_delay(sc); 446 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CLK); 447 dc_delay(sc); 448 } 449 450 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); 451 dc_delay(sc); 452 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CS); 453 dc_delay(sc); 454 CSR_WRITE_4(sc, DC_SIO, 0x00000000); 455 } 456 457 /* 458 * Send a read command and address to the EEPROM, check for ACK. 459 */ 460 static void 461 dc_eeprom_putbyte(struct dc_softc *sc, int addr) 462 { 463 int d, i; 464 465 d = DC_EECMD_READ >> 6; 466 for (i = 3; i--; ) { 467 if (d & (1 << i)) 468 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_DATAIN); 469 else 470 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_DATAIN); 471 dc_delay(sc); 472 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CLK); 473 dc_delay(sc); 474 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); 475 dc_delay(sc); 476 } 477 478 /* 479 * Feed in each bit and strobe the clock. 480 */ 481 for (i = sc->dc_romwidth; i--;) { 482 if (addr & (1 << i)) { 483 SIO_SET(DC_SIO_EE_DATAIN); 484 } else { 485 SIO_CLR(DC_SIO_EE_DATAIN); 486 } 487 dc_delay(sc); 488 SIO_SET(DC_SIO_EE_CLK); 489 dc_delay(sc); 490 SIO_CLR(DC_SIO_EE_CLK); 491 dc_delay(sc); 492 } 493 } 494 495 /* 496 * Read a word of data stored in the EEPROM at address 'addr.' 497 * The PNIC 82c168/82c169 has its own non-standard way to read 498 * the EEPROM. 499 */ 500 static void 501 dc_eeprom_getword_pnic(struct dc_softc *sc, int addr, u_int16_t *dest) 502 { 503 int i; 504 u_int32_t r; 505 506 CSR_WRITE_4(sc, DC_PN_SIOCTL, DC_PN_EEOPCODE_READ | addr); 507 508 for (i = 0; i < DC_TIMEOUT; i++) { 509 DELAY(1); 510 r = CSR_READ_4(sc, DC_SIO); 511 if (!(r & DC_PN_SIOCTL_BUSY)) { 512 *dest = (u_int16_t)(r & 0xFFFF); 513 return; 514 } 515 } 516 } 517 518 /* 519 * Read a word of data stored in the EEPROM at address 'addr.' 520 * The Xircom X3201 has its own non-standard way to read 521 * the EEPROM, too. 522 */ 523 static void 524 dc_eeprom_getword_xircom(struct dc_softc *sc, int addr, u_int16_t *dest) 525 { 526 527 SIO_SET(DC_SIO_ROMSEL | DC_SIO_ROMCTL_READ); 528 529 addr *= 2; 530 CSR_WRITE_4(sc, DC_ROM, addr | 0x160); 531 *dest = (u_int16_t)CSR_READ_4(sc, DC_SIO) & 0xff; 532 addr += 1; 533 CSR_WRITE_4(sc, DC_ROM, addr | 0x160); 534 *dest |= ((u_int16_t)CSR_READ_4(sc, DC_SIO) & 0xff) << 8; 535 536 SIO_CLR(DC_SIO_ROMSEL | DC_SIO_ROMCTL_READ); 537 } 538 539 /* 540 * Read a word of data stored in the EEPROM at address 'addr.' 541 */ 542 static void 543 dc_eeprom_getword(struct dc_softc *sc, int addr, u_int16_t *dest) 544 { 545 int i; 546 u_int16_t word = 0; 547 548 /* Force EEPROM to idle state. */ 549 dc_eeprom_idle(sc); 550 551 /* Enter EEPROM access mode. */ 552 CSR_WRITE_4(sc, DC_SIO, DC_SIO_EESEL); 553 dc_delay(sc); 554 DC_SETBIT(sc, DC_SIO, DC_SIO_ROMCTL_READ); 555 dc_delay(sc); 556 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); 557 dc_delay(sc); 558 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CS); 559 dc_delay(sc); 560 561 /* 562 * Send address of word we want to read. 563 */ 564 dc_eeprom_putbyte(sc, addr); 565 566 /* 567 * Start reading bits from EEPROM. 568 */ 569 for (i = 0x8000; i; i >>= 1) { 570 SIO_SET(DC_SIO_EE_CLK); 571 dc_delay(sc); 572 if (CSR_READ_4(sc, DC_SIO) & DC_SIO_EE_DATAOUT) 573 word |= i; 574 dc_delay(sc); 575 SIO_CLR(DC_SIO_EE_CLK); 576 dc_delay(sc); 577 } 578 579 /* Turn off EEPROM access mode. */ 580 dc_eeprom_idle(sc); 581 582 *dest = word; 583 } 584 585 /* 586 * Read a sequence of words from the EEPROM. 587 */ 588 static void 589 dc_read_eeprom(struct dc_softc *sc, caddr_t dest, int off, int cnt, int swap) 590 { 591 int i; 592 u_int16_t word = 0, *ptr; 593 594 for (i = 0; i < cnt; i++) { 595 if (DC_IS_PNIC(sc)) 596 dc_eeprom_getword_pnic(sc, off + i, &word); 597 else if (DC_IS_XIRCOM(sc)) 598 dc_eeprom_getword_xircom(sc, off + i, &word); 599 else 600 dc_eeprom_getword(sc, off + i, &word); 601 ptr = (u_int16_t *)(dest + (i * 2)); 602 if (swap) 603 *ptr = ntohs(word); 604 else 605 *ptr = word; 606 } 607 } 608 609 /* 610 * The following two routines are taken from the Macronix 98713 611 * Application Notes pp.19-21. 612 */ 613 /* 614 * Write a bit to the MII bus. 615 */ 616 static void 617 dc_mii_writebit(struct dc_softc *sc, int bit) 618 { 619 620 if (bit) 621 CSR_WRITE_4(sc, DC_SIO, 622 DC_SIO_ROMCTL_WRITE | DC_SIO_MII_DATAOUT); 623 else 624 CSR_WRITE_4(sc, DC_SIO, DC_SIO_ROMCTL_WRITE); 625 626 DC_SETBIT(sc, DC_SIO, DC_SIO_MII_CLK); 627 DC_CLRBIT(sc, DC_SIO, DC_SIO_MII_CLK); 628 } 629 630 /* 631 * Read a bit from the MII bus. 632 */ 633 static int 634 dc_mii_readbit(struct dc_softc *sc) 635 { 636 637 CSR_WRITE_4(sc, DC_SIO, DC_SIO_ROMCTL_READ | DC_SIO_MII_DIR); 638 CSR_READ_4(sc, DC_SIO); 639 DC_SETBIT(sc, DC_SIO, DC_SIO_MII_CLK); 640 DC_CLRBIT(sc, DC_SIO, DC_SIO_MII_CLK); 641 if (CSR_READ_4(sc, DC_SIO) & DC_SIO_MII_DATAIN) 642 return (1); 643 644 return (0); 645 } 646 647 /* 648 * Sync the PHYs by setting data bit and strobing the clock 32 times. 649 */ 650 static void 651 dc_mii_sync(struct dc_softc *sc) 652 { 653 int i; 654 655 CSR_WRITE_4(sc, DC_SIO, DC_SIO_ROMCTL_WRITE); 656 657 for (i = 0; i < 32; i++) 658 dc_mii_writebit(sc, 1); 659 } 660 661 /* 662 * Clock a series of bits through the MII. 663 */ 664 static void 665 dc_mii_send(struct dc_softc *sc, u_int32_t bits, int cnt) 666 { 667 int i; 668 669 for (i = (0x1 << (cnt - 1)); i; i >>= 1) 670 dc_mii_writebit(sc, bits & i); 671 } 672 673 /* 674 * Read an PHY register through the MII. 675 */ 676 static int 677 dc_mii_readreg(struct dc_softc *sc, struct dc_mii_frame *frame) 678 { 679 int i, ack; 680 681 DC_LOCK(sc); 682 683 /* 684 * Set up frame for RX. 685 */ 686 frame->mii_stdelim = DC_MII_STARTDELIM; 687 frame->mii_opcode = DC_MII_READOP; 688 frame->mii_turnaround = 0; 689 frame->mii_data = 0; 690 691 /* 692 * Sync the PHYs. 693 */ 694 dc_mii_sync(sc); 695 696 /* 697 * Send command/address info. 698 */ 699 dc_mii_send(sc, frame->mii_stdelim, 2); 700 dc_mii_send(sc, frame->mii_opcode, 2); 701 dc_mii_send(sc, frame->mii_phyaddr, 5); 702 dc_mii_send(sc, frame->mii_regaddr, 5); 703 704 #ifdef notdef 705 /* Idle bit */ 706 dc_mii_writebit(sc, 1); 707 dc_mii_writebit(sc, 0); 708 #endif 709 710 /* Check for ack. */ 711 ack = dc_mii_readbit(sc); 712 713 /* 714 * Now try reading data bits. If the ack failed, we still 715 * need to clock through 16 cycles to keep the PHY(s) in sync. 716 */ 717 if (ack) { 718 for (i = 0; i < 16; i++) 719 dc_mii_readbit(sc); 720 goto fail; 721 } 722 723 for (i = 0x8000; i; i >>= 1) { 724 if (!ack) { 725 if (dc_mii_readbit(sc)) 726 frame->mii_data |= i; 727 } 728 } 729 730 fail: 731 732 dc_mii_writebit(sc, 0); 733 dc_mii_writebit(sc, 0); 734 735 DC_UNLOCK(sc); 736 737 if (ack) 738 return (1); 739 return (0); 740 } 741 742 /* 743 * Write to a PHY register through the MII. 744 */ 745 static int 746 dc_mii_writereg(struct dc_softc *sc, struct dc_mii_frame *frame) 747 { 748 749 DC_LOCK(sc); 750 /* 751 * Set up frame for TX. 752 */ 753 754 frame->mii_stdelim = DC_MII_STARTDELIM; 755 frame->mii_opcode = DC_MII_WRITEOP; 756 frame->mii_turnaround = DC_MII_TURNAROUND; 757 758 /* 759 * Sync the PHYs. 760 */ 761 dc_mii_sync(sc); 762 763 dc_mii_send(sc, frame->mii_stdelim, 2); 764 dc_mii_send(sc, frame->mii_opcode, 2); 765 dc_mii_send(sc, frame->mii_phyaddr, 5); 766 dc_mii_send(sc, frame->mii_regaddr, 5); 767 dc_mii_send(sc, frame->mii_turnaround, 2); 768 dc_mii_send(sc, frame->mii_data, 16); 769 770 /* Idle bit. */ 771 dc_mii_writebit(sc, 0); 772 dc_mii_writebit(sc, 0); 773 774 DC_UNLOCK(sc); 775 776 return (0); 777 } 778 779 static int 780 dc_miibus_readreg(device_t dev, int phy, int reg) 781 { 782 struct dc_mii_frame frame; 783 struct dc_softc *sc; 784 int i, rval, phy_reg = 0; 785 786 sc = device_get_softc(dev); 787 bzero(&frame, sizeof(frame)); 788 789 /* 790 * Note: both the AL981 and AN985 have internal PHYs, 791 * however the AL981 provides direct access to the PHY 792 * registers while the AN985 uses a serial MII interface. 793 * The AN985's MII interface is also buggy in that you 794 * can read from any MII address (0 to 31), but only address 1 795 * behaves normally. To deal with both cases, we pretend 796 * that the PHY is at MII address 1. 797 */ 798 if (DC_IS_ADMTEK(sc) && phy != DC_ADMTEK_PHYADDR) 799 return (0); 800 801 /* 802 * Note: the ukphy probes of the RS7112 report a PHY at 803 * MII address 0 (possibly HomePNA?) and 1 (ethernet) 804 * so we only respond to correct one. 805 */ 806 if (DC_IS_CONEXANT(sc) && phy != DC_CONEXANT_PHYADDR) 807 return (0); 808 809 if (sc->dc_pmode != DC_PMODE_MII) { 810 if (phy == (MII_NPHY - 1)) { 811 switch (reg) { 812 case MII_BMSR: 813 /* 814 * Fake something to make the probe 815 * code think there's a PHY here. 816 */ 817 return (BMSR_MEDIAMASK); 818 break; 819 case MII_PHYIDR1: 820 if (DC_IS_PNIC(sc)) 821 return (DC_VENDORID_LO); 822 return (DC_VENDORID_DEC); 823 break; 824 case MII_PHYIDR2: 825 if (DC_IS_PNIC(sc)) 826 return (DC_DEVICEID_82C168); 827 return (DC_DEVICEID_21143); 828 break; 829 default: 830 return (0); 831 break; 832 } 833 } else 834 return (0); 835 } 836 837 if (DC_IS_PNIC(sc)) { 838 CSR_WRITE_4(sc, DC_PN_MII, DC_PN_MIIOPCODE_READ | 839 (phy << 23) | (reg << 18)); 840 for (i = 0; i < DC_TIMEOUT; i++) { 841 DELAY(1); 842 rval = CSR_READ_4(sc, DC_PN_MII); 843 if (!(rval & DC_PN_MII_BUSY)) { 844 rval &= 0xFFFF; 845 return (rval == 0xFFFF ? 0 : rval); 846 } 847 } 848 return (0); 849 } 850 851 if (DC_IS_COMET(sc)) { 852 switch (reg) { 853 case MII_BMCR: 854 phy_reg = DC_AL_BMCR; 855 break; 856 case MII_BMSR: 857 phy_reg = DC_AL_BMSR; 858 break; 859 case MII_PHYIDR1: 860 phy_reg = DC_AL_VENID; 861 break; 862 case MII_PHYIDR2: 863 phy_reg = DC_AL_DEVID; 864 break; 865 case MII_ANAR: 866 phy_reg = DC_AL_ANAR; 867 break; 868 case MII_ANLPAR: 869 phy_reg = DC_AL_LPAR; 870 break; 871 case MII_ANER: 872 phy_reg = DC_AL_ANER; 873 break; 874 default: 875 printf("dc%d: phy_read: bad phy register %x\n", 876 sc->dc_unit, reg); 877 return (0); 878 break; 879 } 880 881 rval = CSR_READ_4(sc, phy_reg) & 0x0000FFFF; 882 883 if (rval == 0xFFFF) 884 return (0); 885 return (rval); 886 } 887 888 frame.mii_phyaddr = phy; 889 frame.mii_regaddr = reg; 890 if (sc->dc_type == DC_TYPE_98713) { 891 phy_reg = CSR_READ_4(sc, DC_NETCFG); 892 CSR_WRITE_4(sc, DC_NETCFG, phy_reg & ~DC_NETCFG_PORTSEL); 893 } 894 dc_mii_readreg(sc, &frame); 895 if (sc->dc_type == DC_TYPE_98713) 896 CSR_WRITE_4(sc, DC_NETCFG, phy_reg); 897 898 return (frame.mii_data); 899 } 900 901 static int 902 dc_miibus_writereg(device_t dev, int phy, int reg, int data) 903 { 904 struct dc_softc *sc; 905 struct dc_mii_frame frame; 906 int i, phy_reg = 0; 907 908 sc = device_get_softc(dev); 909 bzero(&frame, sizeof(frame)); 910 911 if (DC_IS_ADMTEK(sc) && phy != DC_ADMTEK_PHYADDR) 912 return (0); 913 914 if (DC_IS_CONEXANT(sc) && phy != DC_CONEXANT_PHYADDR) 915 return (0); 916 917 if (DC_IS_PNIC(sc)) { 918 CSR_WRITE_4(sc, DC_PN_MII, DC_PN_MIIOPCODE_WRITE | 919 (phy << 23) | (reg << 10) | data); 920 for (i = 0; i < DC_TIMEOUT; i++) { 921 if (!(CSR_READ_4(sc, DC_PN_MII) & DC_PN_MII_BUSY)) 922 break; 923 } 924 return (0); 925 } 926 927 if (DC_IS_COMET(sc)) { 928 switch (reg) { 929 case MII_BMCR: 930 phy_reg = DC_AL_BMCR; 931 break; 932 case MII_BMSR: 933 phy_reg = DC_AL_BMSR; 934 break; 935 case MII_PHYIDR1: 936 phy_reg = DC_AL_VENID; 937 break; 938 case MII_PHYIDR2: 939 phy_reg = DC_AL_DEVID; 940 break; 941 case MII_ANAR: 942 phy_reg = DC_AL_ANAR; 943 break; 944 case MII_ANLPAR: 945 phy_reg = DC_AL_LPAR; 946 break; 947 case MII_ANER: 948 phy_reg = DC_AL_ANER; 949 break; 950 default: 951 printf("dc%d: phy_write: bad phy register %x\n", 952 sc->dc_unit, reg); 953 return (0); 954 break; 955 } 956 957 CSR_WRITE_4(sc, phy_reg, data); 958 return (0); 959 } 960 961 frame.mii_phyaddr = phy; 962 frame.mii_regaddr = reg; 963 frame.mii_data = data; 964 965 if (sc->dc_type == DC_TYPE_98713) { 966 phy_reg = CSR_READ_4(sc, DC_NETCFG); 967 CSR_WRITE_4(sc, DC_NETCFG, phy_reg & ~DC_NETCFG_PORTSEL); 968 } 969 dc_mii_writereg(sc, &frame); 970 if (sc->dc_type == DC_TYPE_98713) 971 CSR_WRITE_4(sc, DC_NETCFG, phy_reg); 972 973 return (0); 974 } 975 976 static void 977 dc_miibus_statchg(device_t dev) 978 { 979 struct dc_softc *sc; 980 struct mii_data *mii; 981 struct ifmedia *ifm; 982 983 sc = device_get_softc(dev); 984 if (DC_IS_ADMTEK(sc)) 985 return; 986 987 mii = device_get_softc(sc->dc_miibus); 988 ifm = &mii->mii_media; 989 if (DC_IS_DAVICOM(sc) && 990 IFM_SUBTYPE(ifm->ifm_media) == IFM_HPNA_1) { 991 dc_setcfg(sc, ifm->ifm_media); 992 sc->dc_if_media = ifm->ifm_media; 993 } else { 994 dc_setcfg(sc, mii->mii_media_active); 995 sc->dc_if_media = mii->mii_media_active; 996 } 997 } 998 999 /* 1000 * Special support for DM9102A cards with HomePNA PHYs. Note: 1001 * with the Davicom DM9102A/DM9801 eval board that I have, it seems 1002 * to be impossible to talk to the management interface of the DM9801 1003 * PHY (its MDIO pin is not connected to anything). Consequently, 1004 * the driver has to just 'know' about the additional mode and deal 1005 * with it itself. *sigh* 1006 */ 1007 static void 1008 dc_miibus_mediainit(device_t dev) 1009 { 1010 struct dc_softc *sc; 1011 struct mii_data *mii; 1012 struct ifmedia *ifm; 1013 int rev; 1014 1015 rev = pci_read_config(dev, DC_PCI_CFRV, 4) & 0xFF; 1016 1017 sc = device_get_softc(dev); 1018 mii = device_get_softc(sc->dc_miibus); 1019 ifm = &mii->mii_media; 1020 1021 if (DC_IS_DAVICOM(sc) && rev >= DC_REVISION_DM9102A) 1022 ifmedia_add(ifm, IFM_ETHER | IFM_HPNA_1, 0, NULL); 1023 } 1024 1025 #define DC_POLY 0xEDB88320 1026 #define DC_BITS_512 9 1027 #define DC_BITS_128 7 1028 #define DC_BITS_64 6 1029 1030 static uint32_t 1031 dc_mchash_le(struct dc_softc *sc, const uint8_t *addr) 1032 { 1033 uint32_t crc; 1034 int idx, bit; 1035 uint8_t data; 1036 1037 /* Compute CRC for the address value. */ 1038 crc = 0xFFFFFFFF; /* initial value */ 1039 1040 for (idx = 0; idx < 6; idx++) { 1041 for (data = *addr++, bit = 0; bit < 8; bit++, data >>= 1) 1042 crc = (crc >> 1) ^ (((crc ^ data) & 1) ? DC_POLY : 0); 1043 } 1044 1045 /* 1046 * The hash table on the PNIC II and the MX98715AEC-C/D/E 1047 * chips is only 128 bits wide. 1048 */ 1049 if (sc->dc_flags & DC_128BIT_HASH) 1050 return (crc & ((1 << DC_BITS_128) - 1)); 1051 1052 /* The hash table on the MX98715BEC is only 64 bits wide. */ 1053 if (sc->dc_flags & DC_64BIT_HASH) 1054 return (crc & ((1 << DC_BITS_64) - 1)); 1055 1056 /* Xircom's hash filtering table is different (read: weird) */ 1057 /* Xircom uses the LEAST significant bits */ 1058 if (DC_IS_XIRCOM(sc)) { 1059 if ((crc & 0x180) == 0x180) 1060 return ((crc & 0x0F) + (crc & 0x70) * 3 + (14 << 4)); 1061 else 1062 return ((crc & 0x1F) + ((crc >> 1) & 0xF0) * 3 + 1063 (12 << 4)); 1064 } 1065 1066 return (crc & ((1 << DC_BITS_512) - 1)); 1067 } 1068 1069 /* 1070 * Calculate CRC of a multicast group address, return the lower 6 bits. 1071 */ 1072 static uint32_t 1073 dc_mchash_be(const uint8_t *addr) 1074 { 1075 uint32_t crc, carry; 1076 int idx, bit; 1077 uint8_t data; 1078 1079 /* Compute CRC for the address value. */ 1080 crc = 0xFFFFFFFF; /* initial value */ 1081 1082 for (idx = 0; idx < 6; idx++) { 1083 for (data = *addr++, bit = 0; bit < 8; bit++, data >>= 1) { 1084 carry = ((crc & 0x80000000) ? 1 : 0) ^ (data & 0x01); 1085 data >>= 1; 1086 crc <<= 1; 1087 if (carry) 1088 crc = (crc ^ 0x04c11db6) | carry; 1089 } 1090 } 1091 1092 /* Return the filter bit position. */ 1093 return ((crc >> 26) & 0x0000003F); 1094 } 1095 1096 /* 1097 * 21143-style RX filter setup routine. Filter programming is done by 1098 * downloading a special setup frame into the TX engine. 21143, Macronix, 1099 * PNIC, PNIC II and Davicom chips are programmed this way. 1100 * 1101 * We always program the chip using 'hash perfect' mode, i.e. one perfect 1102 * address (our node address) and a 512-bit hash filter for multicast 1103 * frames. We also sneak the broadcast address into the hash filter since 1104 * we need that too. 1105 */ 1106 static void 1107 dc_setfilt_21143(struct dc_softc *sc) 1108 { 1109 struct dc_desc *sframe; 1110 u_int32_t h, *sp; 1111 struct ifmultiaddr *ifma; 1112 struct ifnet *ifp; 1113 int i; 1114 1115 ifp = &sc->arpcom.ac_if; 1116 1117 i = sc->dc_cdata.dc_tx_prod; 1118 DC_INC(sc->dc_cdata.dc_tx_prod, DC_TX_LIST_CNT); 1119 sc->dc_cdata.dc_tx_cnt++; 1120 sframe = &sc->dc_ldata->dc_tx_list[i]; 1121 sp = sc->dc_cdata.dc_sbuf; 1122 bzero(sp, DC_SFRAME_LEN); 1123 1124 sframe->dc_data = htole32(sc->dc_saddr); 1125 sframe->dc_ctl = htole32(DC_SFRAME_LEN | DC_TXCTL_SETUP | 1126 DC_TXCTL_TLINK | DC_FILTER_HASHPERF | DC_TXCTL_FINT); 1127 1128 sc->dc_cdata.dc_tx_chain[i] = (struct mbuf *)sc->dc_cdata.dc_sbuf; 1129 1130 /* If we want promiscuous mode, set the allframes bit. */ 1131 if (ifp->if_flags & IFF_PROMISC) 1132 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC); 1133 else 1134 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC); 1135 1136 if (ifp->if_flags & IFF_ALLMULTI) 1137 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI); 1138 else 1139 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI); 1140 1141 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 1142 if (ifma->ifma_addr->sa_family != AF_LINK) 1143 continue; 1144 h = dc_mchash_le(sc, 1145 LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 1146 sp[h >> 4] |= htole32(1 << (h & 0xF)); 1147 } 1148 1149 if (ifp->if_flags & IFF_BROADCAST) { 1150 h = dc_mchash_le(sc, ifp->if_broadcastaddr); 1151 sp[h >> 4] |= htole32(1 << (h & 0xF)); 1152 } 1153 1154 /* Set our MAC address */ 1155 sp[39] = DC_SP_MAC(((u_int16_t *)sc->arpcom.ac_enaddr)[0]); 1156 sp[40] = DC_SP_MAC(((u_int16_t *)sc->arpcom.ac_enaddr)[1]); 1157 sp[41] = DC_SP_MAC(((u_int16_t *)sc->arpcom.ac_enaddr)[2]); 1158 1159 sframe->dc_status = htole32(DC_TXSTAT_OWN); 1160 CSR_WRITE_4(sc, DC_TXSTART, 0xFFFFFFFF); 1161 1162 /* 1163 * The PNIC takes an exceedingly long time to process its 1164 * setup frame; wait 10ms after posting the setup frame 1165 * before proceeding, just so it has time to swallow its 1166 * medicine. 1167 */ 1168 DELAY(10000); 1169 1170 ifp->if_timer = 5; 1171 } 1172 1173 static void 1174 dc_setfilt_admtek(struct dc_softc *sc) 1175 { 1176 struct ifnet *ifp; 1177 struct ifmultiaddr *ifma; 1178 int h = 0; 1179 u_int32_t hashes[2] = { 0, 0 }; 1180 1181 ifp = &sc->arpcom.ac_if; 1182 1183 /* Init our MAC address. */ 1184 CSR_WRITE_4(sc, DC_AL_PAR0, *(u_int32_t *)(&sc->arpcom.ac_enaddr[0])); 1185 CSR_WRITE_4(sc, DC_AL_PAR1, *(u_int32_t *)(&sc->arpcom.ac_enaddr[4])); 1186 1187 /* If we want promiscuous mode, set the allframes bit. */ 1188 if (ifp->if_flags & IFF_PROMISC) 1189 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC); 1190 else 1191 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC); 1192 1193 if (ifp->if_flags & IFF_ALLMULTI) 1194 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI); 1195 else 1196 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI); 1197 1198 /* First, zot all the existing hash bits. */ 1199 CSR_WRITE_4(sc, DC_AL_MAR0, 0); 1200 CSR_WRITE_4(sc, DC_AL_MAR1, 0); 1201 1202 /* 1203 * If we're already in promisc or allmulti mode, we 1204 * don't have to bother programming the multicast filter. 1205 */ 1206 if (ifp->if_flags & (IFF_PROMISC | IFF_ALLMULTI)) 1207 return; 1208 1209 /* Now program new ones. */ 1210 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 1211 if (ifma->ifma_addr->sa_family != AF_LINK) 1212 continue; 1213 if (DC_IS_CENTAUR(sc)) 1214 h = dc_mchash_le(sc, 1215 LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 1216 else 1217 h = dc_mchash_be( 1218 LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 1219 if (h < 32) 1220 hashes[0] |= (1 << h); 1221 else 1222 hashes[1] |= (1 << (h - 32)); 1223 } 1224 1225 CSR_WRITE_4(sc, DC_AL_MAR0, hashes[0]); 1226 CSR_WRITE_4(sc, DC_AL_MAR1, hashes[1]); 1227 } 1228 1229 static void 1230 dc_setfilt_asix(struct dc_softc *sc) 1231 { 1232 struct ifnet *ifp; 1233 struct ifmultiaddr *ifma; 1234 int h = 0; 1235 u_int32_t hashes[2] = { 0, 0 }; 1236 1237 ifp = &sc->arpcom.ac_if; 1238 1239 /* Init our MAC address */ 1240 CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_PAR0); 1241 CSR_WRITE_4(sc, DC_AX_FILTDATA, 1242 *(u_int32_t *)(&sc->arpcom.ac_enaddr[0])); 1243 CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_PAR1); 1244 CSR_WRITE_4(sc, DC_AX_FILTDATA, 1245 *(u_int32_t *)(&sc->arpcom.ac_enaddr[4])); 1246 1247 /* If we want promiscuous mode, set the allframes bit. */ 1248 if (ifp->if_flags & IFF_PROMISC) 1249 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC); 1250 else 1251 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC); 1252 1253 if (ifp->if_flags & IFF_ALLMULTI) 1254 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI); 1255 else 1256 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI); 1257 1258 /* 1259 * The ASIX chip has a special bit to enable reception 1260 * of broadcast frames. 1261 */ 1262 if (ifp->if_flags & IFF_BROADCAST) 1263 DC_SETBIT(sc, DC_NETCFG, DC_AX_NETCFG_RX_BROAD); 1264 else 1265 DC_CLRBIT(sc, DC_NETCFG, DC_AX_NETCFG_RX_BROAD); 1266 1267 /* first, zot all the existing hash bits */ 1268 CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_MAR0); 1269 CSR_WRITE_4(sc, DC_AX_FILTDATA, 0); 1270 CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_MAR1); 1271 CSR_WRITE_4(sc, DC_AX_FILTDATA, 0); 1272 1273 /* 1274 * If we're already in promisc or allmulti mode, we 1275 * don't have to bother programming the multicast filter. 1276 */ 1277 if (ifp->if_flags & (IFF_PROMISC | IFF_ALLMULTI)) 1278 return; 1279 1280 /* now program new ones */ 1281 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 1282 if (ifma->ifma_addr->sa_family != AF_LINK) 1283 continue; 1284 h = dc_mchash_be(LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 1285 if (h < 32) 1286 hashes[0] |= (1 << h); 1287 else 1288 hashes[1] |= (1 << (h - 32)); 1289 } 1290 1291 CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_MAR0); 1292 CSR_WRITE_4(sc, DC_AX_FILTDATA, hashes[0]); 1293 CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_MAR1); 1294 CSR_WRITE_4(sc, DC_AX_FILTDATA, hashes[1]); 1295 } 1296 1297 static void 1298 dc_setfilt_xircom(struct dc_softc *sc) 1299 { 1300 struct ifnet *ifp; 1301 struct ifmultiaddr *ifma; 1302 struct dc_desc *sframe; 1303 u_int32_t h, *sp; 1304 int i; 1305 1306 ifp = &sc->arpcom.ac_if; 1307 DC_CLRBIT(sc, DC_NETCFG, (DC_NETCFG_TX_ON | DC_NETCFG_RX_ON)); 1308 1309 i = sc->dc_cdata.dc_tx_prod; 1310 DC_INC(sc->dc_cdata.dc_tx_prod, DC_TX_LIST_CNT); 1311 sc->dc_cdata.dc_tx_cnt++; 1312 sframe = &sc->dc_ldata->dc_tx_list[i]; 1313 sp = sc->dc_cdata.dc_sbuf; 1314 bzero(sp, DC_SFRAME_LEN); 1315 1316 sframe->dc_data = htole32(sc->dc_saddr); 1317 sframe->dc_ctl = htole32(DC_SFRAME_LEN | DC_TXCTL_SETUP | 1318 DC_TXCTL_TLINK | DC_FILTER_HASHPERF | DC_TXCTL_FINT); 1319 1320 sc->dc_cdata.dc_tx_chain[i] = (struct mbuf *)sc->dc_cdata.dc_sbuf; 1321 1322 /* If we want promiscuous mode, set the allframes bit. */ 1323 if (ifp->if_flags & IFF_PROMISC) 1324 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC); 1325 else 1326 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC); 1327 1328 if (ifp->if_flags & IFF_ALLMULTI) 1329 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI); 1330 else 1331 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI); 1332 1333 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 1334 if (ifma->ifma_addr->sa_family != AF_LINK) 1335 continue; 1336 h = dc_mchash_le(sc, 1337 LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 1338 sp[h >> 4] |= htole32(1 << (h & 0xF)); 1339 } 1340 1341 if (ifp->if_flags & IFF_BROADCAST) { 1342 h = dc_mchash_le(sc, ifp->if_broadcastaddr); 1343 sp[h >> 4] |= htole32(1 << (h & 0xF)); 1344 } 1345 1346 /* Set our MAC address */ 1347 sp[0] = DC_SP_MAC(((u_int16_t *)sc->arpcom.ac_enaddr)[0]); 1348 sp[1] = DC_SP_MAC(((u_int16_t *)sc->arpcom.ac_enaddr)[1]); 1349 sp[2] = DC_SP_MAC(((u_int16_t *)sc->arpcom.ac_enaddr)[2]); 1350 1351 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_TX_ON); 1352 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_ON); 1353 ifp->if_flags |= IFF_RUNNING; 1354 sframe->dc_status = htole32(DC_TXSTAT_OWN); 1355 CSR_WRITE_4(sc, DC_TXSTART, 0xFFFFFFFF); 1356 1357 /* 1358 * Wait some time... 1359 */ 1360 DELAY(1000); 1361 1362 ifp->if_timer = 5; 1363 } 1364 1365 static void 1366 dc_setfilt(struct dc_softc *sc) 1367 { 1368 1369 if (DC_IS_INTEL(sc) || DC_IS_MACRONIX(sc) || DC_IS_PNIC(sc) || 1370 DC_IS_PNICII(sc) || DC_IS_DAVICOM(sc) || DC_IS_CONEXANT(sc)) 1371 dc_setfilt_21143(sc); 1372 1373 if (DC_IS_ASIX(sc)) 1374 dc_setfilt_asix(sc); 1375 1376 if (DC_IS_ADMTEK(sc)) 1377 dc_setfilt_admtek(sc); 1378 1379 if (DC_IS_XIRCOM(sc)) 1380 dc_setfilt_xircom(sc); 1381 } 1382 1383 /* 1384 * In order to fiddle with the 'full-duplex' and '100Mbps' bits in 1385 * the netconfig register, we first have to put the transmit and/or 1386 * receive logic in the idle state. 1387 */ 1388 static void 1389 dc_setcfg(struct dc_softc *sc, int media) 1390 { 1391 int i, restart = 0, watchdogreg; 1392 u_int32_t isr; 1393 1394 if (IFM_SUBTYPE(media) == IFM_NONE) 1395 return; 1396 1397 if (CSR_READ_4(sc, DC_NETCFG) & (DC_NETCFG_TX_ON | DC_NETCFG_RX_ON)) { 1398 restart = 1; 1399 DC_CLRBIT(sc, DC_NETCFG, (DC_NETCFG_TX_ON | DC_NETCFG_RX_ON)); 1400 1401 for (i = 0; i < DC_TIMEOUT; i++) { 1402 isr = CSR_READ_4(sc, DC_ISR); 1403 if (isr & DC_ISR_TX_IDLE && 1404 ((isr & DC_ISR_RX_STATE) == DC_RXSTATE_STOPPED || 1405 (isr & DC_ISR_RX_STATE) == DC_RXSTATE_WAIT)) 1406 break; 1407 DELAY(10); 1408 } 1409 1410 if (i == DC_TIMEOUT) 1411 printf("dc%d: failed to force tx and " 1412 "rx to idle state\n", sc->dc_unit); 1413 } 1414 1415 if (IFM_SUBTYPE(media) == IFM_100_TX) { 1416 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_SPEEDSEL); 1417 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_HEARTBEAT); 1418 if (sc->dc_pmode == DC_PMODE_MII) { 1419 if (DC_IS_INTEL(sc)) { 1420 /* There's a write enable bit here that reads as 1. */ 1421 watchdogreg = CSR_READ_4(sc, DC_WATCHDOG); 1422 watchdogreg &= ~DC_WDOG_CTLWREN; 1423 watchdogreg |= DC_WDOG_JABBERDIS; 1424 CSR_WRITE_4(sc, DC_WATCHDOG, watchdogreg); 1425 } else { 1426 DC_SETBIT(sc, DC_WATCHDOG, DC_WDOG_JABBERDIS); 1427 } 1428 DC_CLRBIT(sc, DC_NETCFG, (DC_NETCFG_PCS | 1429 DC_NETCFG_PORTSEL | DC_NETCFG_SCRAMBLER)); 1430 if (sc->dc_type == DC_TYPE_98713) 1431 DC_SETBIT(sc, DC_NETCFG, (DC_NETCFG_PCS | 1432 DC_NETCFG_SCRAMBLER)); 1433 if (!DC_IS_DAVICOM(sc)) 1434 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL); 1435 DC_CLRBIT(sc, DC_10BTCTRL, 0xFFFF); 1436 if (DC_IS_INTEL(sc)) 1437 dc_apply_fixup(sc, IFM_AUTO); 1438 } else { 1439 if (DC_IS_PNIC(sc)) { 1440 DC_PN_GPIO_SETBIT(sc, DC_PN_GPIO_SPEEDSEL); 1441 DC_PN_GPIO_SETBIT(sc, DC_PN_GPIO_100TX_LOOP); 1442 DC_SETBIT(sc, DC_PN_NWAY, DC_PN_NWAY_SPEEDSEL); 1443 } 1444 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL); 1445 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PCS); 1446 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_SCRAMBLER); 1447 if (DC_IS_INTEL(sc)) 1448 dc_apply_fixup(sc, 1449 (media & IFM_GMASK) == IFM_FDX ? 1450 IFM_100_TX | IFM_FDX : IFM_100_TX); 1451 } 1452 } 1453 1454 if (IFM_SUBTYPE(media) == IFM_10_T) { 1455 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_SPEEDSEL); 1456 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_HEARTBEAT); 1457 if (sc->dc_pmode == DC_PMODE_MII) { 1458 /* There's a write enable bit here that reads as 1. */ 1459 if (DC_IS_INTEL(sc)) { 1460 watchdogreg = CSR_READ_4(sc, DC_WATCHDOG); 1461 watchdogreg &= ~DC_WDOG_CTLWREN; 1462 watchdogreg |= DC_WDOG_JABBERDIS; 1463 CSR_WRITE_4(sc, DC_WATCHDOG, watchdogreg); 1464 } else { 1465 DC_SETBIT(sc, DC_WATCHDOG, DC_WDOG_JABBERDIS); 1466 } 1467 DC_CLRBIT(sc, DC_NETCFG, (DC_NETCFG_PCS | 1468 DC_NETCFG_PORTSEL | DC_NETCFG_SCRAMBLER)); 1469 if (sc->dc_type == DC_TYPE_98713) 1470 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PCS); 1471 if (!DC_IS_DAVICOM(sc)) 1472 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL); 1473 DC_CLRBIT(sc, DC_10BTCTRL, 0xFFFF); 1474 if (DC_IS_INTEL(sc)) 1475 dc_apply_fixup(sc, IFM_AUTO); 1476 } else { 1477 if (DC_IS_PNIC(sc)) { 1478 DC_PN_GPIO_CLRBIT(sc, DC_PN_GPIO_SPEEDSEL); 1479 DC_PN_GPIO_SETBIT(sc, DC_PN_GPIO_100TX_LOOP); 1480 DC_CLRBIT(sc, DC_PN_NWAY, DC_PN_NWAY_SPEEDSEL); 1481 } 1482 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL); 1483 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_PCS); 1484 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_SCRAMBLER); 1485 if (DC_IS_INTEL(sc)) { 1486 DC_CLRBIT(sc, DC_SIARESET, DC_SIA_RESET); 1487 DC_CLRBIT(sc, DC_10BTCTRL, 0xFFFF); 1488 if ((media & IFM_GMASK) == IFM_FDX) 1489 DC_SETBIT(sc, DC_10BTCTRL, 0x7F3D); 1490 else 1491 DC_SETBIT(sc, DC_10BTCTRL, 0x7F3F); 1492 DC_SETBIT(sc, DC_SIARESET, DC_SIA_RESET); 1493 DC_CLRBIT(sc, DC_10BTCTRL, 1494 DC_TCTL_AUTONEGENBL); 1495 dc_apply_fixup(sc, 1496 (media & IFM_GMASK) == IFM_FDX ? 1497 IFM_10_T | IFM_FDX : IFM_10_T); 1498 DELAY(20000); 1499 } 1500 } 1501 } 1502 1503 /* 1504 * If this is a Davicom DM9102A card with a DM9801 HomePNA 1505 * PHY and we want HomePNA mode, set the portsel bit to turn 1506 * on the external MII port. 1507 */ 1508 if (DC_IS_DAVICOM(sc)) { 1509 if (IFM_SUBTYPE(media) == IFM_HPNA_1) { 1510 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL); 1511 sc->dc_link = 1; 1512 } else { 1513 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL); 1514 } 1515 } 1516 1517 if ((media & IFM_GMASK) == IFM_FDX) { 1518 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_FULLDUPLEX); 1519 if (sc->dc_pmode == DC_PMODE_SYM && DC_IS_PNIC(sc)) 1520 DC_SETBIT(sc, DC_PN_NWAY, DC_PN_NWAY_DUPLEX); 1521 } else { 1522 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_FULLDUPLEX); 1523 if (sc->dc_pmode == DC_PMODE_SYM && DC_IS_PNIC(sc)) 1524 DC_CLRBIT(sc, DC_PN_NWAY, DC_PN_NWAY_DUPLEX); 1525 } 1526 1527 if (restart) 1528 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_TX_ON | DC_NETCFG_RX_ON); 1529 } 1530 1531 static void 1532 dc_reset(struct dc_softc *sc) 1533 { 1534 int i; 1535 1536 DC_SETBIT(sc, DC_BUSCTL, DC_BUSCTL_RESET); 1537 1538 for (i = 0; i < DC_TIMEOUT; i++) { 1539 DELAY(10); 1540 if (!(CSR_READ_4(sc, DC_BUSCTL) & DC_BUSCTL_RESET)) 1541 break; 1542 } 1543 1544 if (DC_IS_ASIX(sc) || DC_IS_ADMTEK(sc) || DC_IS_CONEXANT(sc) || 1545 DC_IS_XIRCOM(sc) || DC_IS_INTEL(sc)) { 1546 DELAY(10000); 1547 DC_CLRBIT(sc, DC_BUSCTL, DC_BUSCTL_RESET); 1548 i = 0; 1549 } 1550 1551 if (i == DC_TIMEOUT) 1552 printf("dc%d: reset never completed!\n", sc->dc_unit); 1553 1554 /* Wait a little while for the chip to get its brains in order. */ 1555 DELAY(1000); 1556 1557 CSR_WRITE_4(sc, DC_IMR, 0x00000000); 1558 CSR_WRITE_4(sc, DC_BUSCTL, 0x00000000); 1559 CSR_WRITE_4(sc, DC_NETCFG, 0x00000000); 1560 1561 /* 1562 * Bring the SIA out of reset. In some cases, it looks 1563 * like failing to unreset the SIA soon enough gets it 1564 * into a state where it will never come out of reset 1565 * until we reset the whole chip again. 1566 */ 1567 if (DC_IS_INTEL(sc)) { 1568 DC_SETBIT(sc, DC_SIARESET, DC_SIA_RESET); 1569 CSR_WRITE_4(sc, DC_10BTCTRL, 0); 1570 CSR_WRITE_4(sc, DC_WATCHDOG, 0); 1571 } 1572 } 1573 1574 static struct dc_type * 1575 dc_devtype(device_t dev) 1576 { 1577 struct dc_type *t; 1578 u_int32_t rev; 1579 1580 t = dc_devs; 1581 1582 while (t->dc_name != NULL) { 1583 if ((pci_get_vendor(dev) == t->dc_vid) && 1584 (pci_get_device(dev) == t->dc_did)) { 1585 /* Check the PCI revision */ 1586 rev = pci_read_config(dev, DC_PCI_CFRV, 4) & 0xFF; 1587 if (t->dc_did == DC_DEVICEID_98713 && 1588 rev >= DC_REVISION_98713A) 1589 t++; 1590 if (t->dc_did == DC_DEVICEID_98713_CP && 1591 rev >= DC_REVISION_98713A) 1592 t++; 1593 if (t->dc_did == DC_DEVICEID_987x5 && 1594 rev >= DC_REVISION_98715AEC_C) 1595 t++; 1596 if (t->dc_did == DC_DEVICEID_987x5 && 1597 rev >= DC_REVISION_98725) 1598 t++; 1599 if (t->dc_did == DC_DEVICEID_AX88140A && 1600 rev >= DC_REVISION_88141) 1601 t++; 1602 if (t->dc_did == DC_DEVICEID_82C168 && 1603 rev >= DC_REVISION_82C169) 1604 t++; 1605 if (t->dc_did == DC_DEVICEID_DM9102 && 1606 rev >= DC_REVISION_DM9102A) 1607 t++; 1608 /* 1609 * The Microsoft MN-130 has a device ID of 0x0002, 1610 * which happens to be the same as the PNIC 82c168. 1611 * To keep dc_attach() from getting confused, we 1612 * pretend its ID is something different. 1613 * XXX: ideally, dc_attach() should be checking 1614 * vendorid+deviceid together to avoid such 1615 * collisions. 1616 */ 1617 if (t->dc_vid == DC_VENDORID_MICROSOFT && 1618 t->dc_did == DC_DEVICEID_MSMN130) 1619 t++; 1620 return (t); 1621 } 1622 t++; 1623 } 1624 1625 return (NULL); 1626 } 1627 1628 /* 1629 * Probe for a 21143 or clone chip. Check the PCI vendor and device 1630 * IDs against our list and return a device name if we find a match. 1631 * We do a little bit of extra work to identify the exact type of 1632 * chip. The MX98713 and MX98713A have the same PCI vendor/device ID, 1633 * but different revision IDs. The same is true for 98715/98715A 1634 * chips and the 98725, as well as the ASIX and ADMtek chips. In some 1635 * cases, the exact chip revision affects driver behavior. 1636 */ 1637 static int 1638 dc_probe(device_t dev) 1639 { 1640 struct dc_type *t; 1641 1642 t = dc_devtype(dev); 1643 1644 if (t != NULL) { 1645 device_set_desc(dev, t->dc_name); 1646 return (0); 1647 } 1648 1649 return (ENXIO); 1650 } 1651 1652 #ifndef BURN_BRIDGES 1653 static void 1654 dc_acpi(device_t dev) 1655 { 1656 int unit; 1657 u_int32_t iobase, membase, irq; 1658 1659 unit = device_get_unit(dev); 1660 1661 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) { 1662 /* Save important PCI config data. */ 1663 iobase = pci_read_config(dev, DC_PCI_CFBIO, 4); 1664 membase = pci_read_config(dev, DC_PCI_CFBMA, 4); 1665 irq = pci_read_config(dev, DC_PCI_CFIT, 4); 1666 1667 /* Reset the power state. */ 1668 printf("dc%d: chip is in D%d power mode " 1669 "-- setting to D0\n", unit, 1670 pci_get_powerstate(dev)); 1671 pci_set_powerstate(dev, PCI_POWERSTATE_D0); 1672 1673 /* Restore PCI config data. */ 1674 pci_write_config(dev, DC_PCI_CFBIO, iobase, 4); 1675 pci_write_config(dev, DC_PCI_CFBMA, membase, 4); 1676 pci_write_config(dev, DC_PCI_CFIT, irq, 4); 1677 } 1678 } 1679 #endif 1680 1681 static void 1682 dc_apply_fixup(struct dc_softc *sc, int media) 1683 { 1684 struct dc_mediainfo *m; 1685 u_int8_t *p; 1686 int i; 1687 u_int32_t reg; 1688 1689 m = sc->dc_mi; 1690 1691 while (m != NULL) { 1692 if (m->dc_media == media) 1693 break; 1694 m = m->dc_next; 1695 } 1696 1697 if (m == NULL) 1698 return; 1699 1700 for (i = 0, p = m->dc_reset_ptr; i < m->dc_reset_len; i++, p += 2) { 1701 reg = (p[0] | (p[1] << 8)) << 16; 1702 CSR_WRITE_4(sc, DC_WATCHDOG, reg); 1703 } 1704 1705 for (i = 0, p = m->dc_gp_ptr; i < m->dc_gp_len; i++, p += 2) { 1706 reg = (p[0] | (p[1] << 8)) << 16; 1707 CSR_WRITE_4(sc, DC_WATCHDOG, reg); 1708 } 1709 } 1710 1711 static void 1712 dc_decode_leaf_sia(struct dc_softc *sc, struct dc_eblock_sia *l) 1713 { 1714 struct dc_mediainfo *m; 1715 1716 m = malloc(sizeof(struct dc_mediainfo), M_DEVBUF, M_NOWAIT | M_ZERO); 1717 switch (l->dc_sia_code & ~DC_SIA_CODE_EXT) { 1718 case DC_SIA_CODE_10BT: 1719 m->dc_media = IFM_10_T; 1720 break; 1721 case DC_SIA_CODE_10BT_FDX: 1722 m->dc_media = IFM_10_T | IFM_FDX; 1723 break; 1724 case DC_SIA_CODE_10B2: 1725 m->dc_media = IFM_10_2; 1726 break; 1727 case DC_SIA_CODE_10B5: 1728 m->dc_media = IFM_10_5; 1729 break; 1730 default: 1731 break; 1732 } 1733 1734 /* 1735 * We need to ignore CSR13, CSR14, CSR15 for SIA mode. 1736 * Things apparently already work for cards that do 1737 * supply Media Specific Data. 1738 */ 1739 if (l->dc_sia_code & DC_SIA_CODE_EXT) { 1740 m->dc_gp_len = 2; 1741 m->dc_gp_ptr = 1742 (u_int8_t *)&l->dc_un.dc_sia_ext.dc_sia_gpio_ctl; 1743 } else { 1744 m->dc_gp_len = 2; 1745 m->dc_gp_ptr = 1746 (u_int8_t *)&l->dc_un.dc_sia_noext.dc_sia_gpio_ctl; 1747 } 1748 1749 m->dc_next = sc->dc_mi; 1750 sc->dc_mi = m; 1751 1752 sc->dc_pmode = DC_PMODE_SIA; 1753 } 1754 1755 static void 1756 dc_decode_leaf_sym(struct dc_softc *sc, struct dc_eblock_sym *l) 1757 { 1758 struct dc_mediainfo *m; 1759 1760 m = malloc(sizeof(struct dc_mediainfo), M_DEVBUF, M_NOWAIT | M_ZERO); 1761 if (l->dc_sym_code == DC_SYM_CODE_100BT) 1762 m->dc_media = IFM_100_TX; 1763 1764 if (l->dc_sym_code == DC_SYM_CODE_100BT_FDX) 1765 m->dc_media = IFM_100_TX | IFM_FDX; 1766 1767 m->dc_gp_len = 2; 1768 m->dc_gp_ptr = (u_int8_t *)&l->dc_sym_gpio_ctl; 1769 1770 m->dc_next = sc->dc_mi; 1771 sc->dc_mi = m; 1772 1773 sc->dc_pmode = DC_PMODE_SYM; 1774 } 1775 1776 static void 1777 dc_decode_leaf_mii(struct dc_softc *sc, struct dc_eblock_mii *l) 1778 { 1779 struct dc_mediainfo *m; 1780 u_int8_t *p; 1781 1782 m = malloc(sizeof(struct dc_mediainfo), M_DEVBUF, M_NOWAIT | M_ZERO); 1783 /* We abuse IFM_AUTO to represent MII. */ 1784 m->dc_media = IFM_AUTO; 1785 m->dc_gp_len = l->dc_gpr_len; 1786 1787 p = (u_int8_t *)l; 1788 p += sizeof(struct dc_eblock_mii); 1789 m->dc_gp_ptr = p; 1790 p += 2 * l->dc_gpr_len; 1791 m->dc_reset_len = *p; 1792 p++; 1793 m->dc_reset_ptr = p; 1794 1795 m->dc_next = sc->dc_mi; 1796 sc->dc_mi = m; 1797 } 1798 1799 static void 1800 dc_read_srom(struct dc_softc *sc, int bits) 1801 { 1802 int size; 1803 1804 size = 2 << bits; 1805 sc->dc_srom = malloc(size, M_DEVBUF, M_NOWAIT); 1806 dc_read_eeprom(sc, (caddr_t)sc->dc_srom, 0, (size / 2), 0); 1807 } 1808 1809 static void 1810 dc_parse_21143_srom(struct dc_softc *sc) 1811 { 1812 struct dc_leaf_hdr *lhdr; 1813 struct dc_eblock_hdr *hdr; 1814 int have_mii, i, loff; 1815 char *ptr; 1816 1817 have_mii = 0; 1818 loff = sc->dc_srom[27]; 1819 lhdr = (struct dc_leaf_hdr *)&(sc->dc_srom[loff]); 1820 1821 ptr = (char *)lhdr; 1822 ptr += sizeof(struct dc_leaf_hdr) - 1; 1823 /* 1824 * Look if we got a MII media block. 1825 */ 1826 for (i = 0; i < lhdr->dc_mcnt; i++) { 1827 hdr = (struct dc_eblock_hdr *)ptr; 1828 if (hdr->dc_type == DC_EBLOCK_MII) 1829 have_mii++; 1830 1831 ptr += (hdr->dc_len & 0x7F); 1832 ptr++; 1833 } 1834 1835 /* 1836 * Do the same thing again. Only use SIA and SYM media 1837 * blocks if no MII media block is available. 1838 */ 1839 ptr = (char *)lhdr; 1840 ptr += sizeof(struct dc_leaf_hdr) - 1; 1841 for (i = 0; i < lhdr->dc_mcnt; i++) { 1842 hdr = (struct dc_eblock_hdr *)ptr; 1843 switch (hdr->dc_type) { 1844 case DC_EBLOCK_MII: 1845 dc_decode_leaf_mii(sc, (struct dc_eblock_mii *)hdr); 1846 break; 1847 case DC_EBLOCK_SIA: 1848 if (! have_mii) 1849 dc_decode_leaf_sia(sc, 1850 (struct dc_eblock_sia *)hdr); 1851 break; 1852 case DC_EBLOCK_SYM: 1853 if (! have_mii) 1854 dc_decode_leaf_sym(sc, 1855 (struct dc_eblock_sym *)hdr); 1856 break; 1857 default: 1858 /* Don't care. Yet. */ 1859 break; 1860 } 1861 ptr += (hdr->dc_len & 0x7F); 1862 ptr++; 1863 } 1864 } 1865 1866 static void 1867 dc_dma_map_addr(void *arg, bus_dma_segment_t *segs, int nseg, int error) 1868 { 1869 u_int32_t *paddr; 1870 1871 KASSERT(nseg == 1, ("wrong number of segments, should be 1")); 1872 paddr = arg; 1873 *paddr = segs->ds_addr; 1874 } 1875 1876 /* 1877 * Attach the interface. Allocate softc structures, do ifmedia 1878 * setup and ethernet/BPF attach. 1879 */ 1880 static int 1881 dc_attach(device_t dev) 1882 { 1883 int tmp = 0; 1884 u_char eaddr[ETHER_ADDR_LEN]; 1885 u_int32_t command; 1886 struct dc_softc *sc; 1887 struct ifnet *ifp; 1888 u_int32_t revision; 1889 int unit, error = 0, rid, mac_offset; 1890 int i; 1891 u_int8_t *mac; 1892 1893 sc = device_get_softc(dev); 1894 unit = device_get_unit(dev); 1895 1896 mtx_init(&sc->dc_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 1897 MTX_DEF | MTX_RECURSE); 1898 #ifndef BURN_BRIDGES 1899 /* 1900 * Handle power management nonsense. 1901 */ 1902 dc_acpi(dev); 1903 #endif 1904 /* 1905 * Map control/status registers. 1906 */ 1907 pci_enable_busmaster(dev); 1908 1909 rid = DC_RID; 1910 sc->dc_res = bus_alloc_resource(dev, DC_RES, &rid, 1911 0, ~0, 1, RF_ACTIVE); 1912 1913 if (sc->dc_res == NULL) { 1914 printf("dc%d: couldn't map ports/memory\n", unit); 1915 error = ENXIO; 1916 goto fail; 1917 } 1918 1919 sc->dc_btag = rman_get_bustag(sc->dc_res); 1920 sc->dc_bhandle = rman_get_bushandle(sc->dc_res); 1921 1922 /* Allocate interrupt. */ 1923 rid = 0; 1924 sc->dc_irq = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, 0, ~0, 1, 1925 RF_SHAREABLE | RF_ACTIVE); 1926 1927 if (sc->dc_irq == NULL) { 1928 printf("dc%d: couldn't map interrupt\n", unit); 1929 error = ENXIO; 1930 goto fail; 1931 } 1932 1933 /* Need this info to decide on a chip type. */ 1934 sc->dc_info = dc_devtype(dev); 1935 revision = pci_read_config(dev, DC_PCI_CFRV, 4) & 0x000000FF; 1936 1937 /* Get the eeprom width, but PNIC and XIRCOM have diff eeprom */ 1938 if (sc->dc_info->dc_did != DC_DEVICEID_82C168 && 1939 sc->dc_info->dc_did != DC_DEVICEID_X3201) 1940 dc_eeprom_width(sc); 1941 1942 switch (sc->dc_info->dc_did) { 1943 case DC_DEVICEID_21143: 1944 sc->dc_type = DC_TYPE_21143; 1945 sc->dc_flags |= DC_TX_POLL | DC_TX_USE_TX_INTR; 1946 sc->dc_flags |= DC_REDUCED_MII_POLL; 1947 /* Save EEPROM contents so we can parse them later. */ 1948 dc_read_srom(sc, sc->dc_romwidth); 1949 break; 1950 case DC_DEVICEID_DM9009: 1951 case DC_DEVICEID_DM9100: 1952 case DC_DEVICEID_DM9102: 1953 sc->dc_type = DC_TYPE_DM9102; 1954 sc->dc_flags |= DC_TX_COALESCE | DC_TX_INTR_ALWAYS; 1955 sc->dc_flags |= DC_REDUCED_MII_POLL | DC_TX_STORENFWD; 1956 sc->dc_flags |= DC_TX_ALIGN; 1957 sc->dc_pmode = DC_PMODE_MII; 1958 /* Increase the latency timer value. */ 1959 command = pci_read_config(dev, DC_PCI_CFLT, 4); 1960 command &= 0xFFFF00FF; 1961 command |= 0x00008000; 1962 pci_write_config(dev, DC_PCI_CFLT, command, 4); 1963 break; 1964 case DC_DEVICEID_AL981: 1965 sc->dc_type = DC_TYPE_AL981; 1966 sc->dc_flags |= DC_TX_USE_TX_INTR; 1967 sc->dc_flags |= DC_TX_ADMTEK_WAR; 1968 sc->dc_pmode = DC_PMODE_MII; 1969 dc_read_srom(sc, sc->dc_romwidth); 1970 break; 1971 case DC_DEVICEID_AN985: 1972 case DC_DEVICEID_ADM9511: 1973 case DC_DEVICEID_ADM9513: 1974 case DC_DEVICEID_FA511: 1975 case DC_DEVICEID_FE2500: 1976 case DC_DEVICEID_EN2242: 1977 case DC_DEVICEID_HAWKING_PN672TX: 1978 case DC_DEVICEID_3CSOHOB: 1979 case DC_DEVICEID_MSMN120: 1980 case DC_DEVICEID_MSMN130_FAKE: /* XXX avoid collision with PNIC*/ 1981 sc->dc_type = DC_TYPE_AN985; 1982 sc->dc_flags |= DC_64BIT_HASH; 1983 sc->dc_flags |= DC_TX_USE_TX_INTR; 1984 sc->dc_flags |= DC_TX_ADMTEK_WAR; 1985 sc->dc_pmode = DC_PMODE_MII; 1986 /* Don't read SROM for - auto-loaded on reset */ 1987 break; 1988 case DC_DEVICEID_98713: 1989 case DC_DEVICEID_98713_CP: 1990 if (revision < DC_REVISION_98713A) { 1991 sc->dc_type = DC_TYPE_98713; 1992 } 1993 if (revision >= DC_REVISION_98713A) { 1994 sc->dc_type = DC_TYPE_98713A; 1995 sc->dc_flags |= DC_21143_NWAY; 1996 } 1997 sc->dc_flags |= DC_REDUCED_MII_POLL; 1998 sc->dc_flags |= DC_TX_POLL | DC_TX_USE_TX_INTR; 1999 break; 2000 case DC_DEVICEID_987x5: 2001 case DC_DEVICEID_EN1217: 2002 /* 2003 * Macronix MX98715AEC-C/D/E parts have only a 2004 * 128-bit hash table. We need to deal with these 2005 * in the same manner as the PNIC II so that we 2006 * get the right number of bits out of the 2007 * CRC routine. 2008 */ 2009 if (revision >= DC_REVISION_98715AEC_C && 2010 revision < DC_REVISION_98725) 2011 sc->dc_flags |= DC_128BIT_HASH; 2012 sc->dc_type = DC_TYPE_987x5; 2013 sc->dc_flags |= DC_TX_POLL | DC_TX_USE_TX_INTR; 2014 sc->dc_flags |= DC_REDUCED_MII_POLL | DC_21143_NWAY; 2015 break; 2016 case DC_DEVICEID_98727: 2017 sc->dc_type = DC_TYPE_987x5; 2018 sc->dc_flags |= DC_TX_POLL | DC_TX_USE_TX_INTR; 2019 sc->dc_flags |= DC_REDUCED_MII_POLL | DC_21143_NWAY; 2020 break; 2021 case DC_DEVICEID_82C115: 2022 sc->dc_type = DC_TYPE_PNICII; 2023 sc->dc_flags |= DC_TX_POLL | DC_TX_USE_TX_INTR | DC_128BIT_HASH; 2024 sc->dc_flags |= DC_REDUCED_MII_POLL | DC_21143_NWAY; 2025 break; 2026 case DC_DEVICEID_82C168: 2027 sc->dc_type = DC_TYPE_PNIC; 2028 sc->dc_flags |= DC_TX_STORENFWD | DC_TX_INTR_ALWAYS; 2029 sc->dc_flags |= DC_PNIC_RX_BUG_WAR; 2030 sc->dc_pnic_rx_buf = malloc(DC_RXLEN * 5, M_DEVBUF, M_NOWAIT); 2031 if (revision < DC_REVISION_82C169) 2032 sc->dc_pmode = DC_PMODE_SYM; 2033 break; 2034 case DC_DEVICEID_AX88140A: 2035 sc->dc_type = DC_TYPE_ASIX; 2036 sc->dc_flags |= DC_TX_USE_TX_INTR | DC_TX_INTR_FIRSTFRAG; 2037 sc->dc_flags |= DC_REDUCED_MII_POLL; 2038 sc->dc_pmode = DC_PMODE_MII; 2039 break; 2040 case DC_DEVICEID_X3201: 2041 sc->dc_type = DC_TYPE_XIRCOM; 2042 sc->dc_flags |= DC_TX_INTR_ALWAYS | DC_TX_COALESCE | 2043 DC_TX_ALIGN; 2044 /* 2045 * We don't actually need to coalesce, but we're doing 2046 * it to obtain a double word aligned buffer. 2047 * The DC_TX_COALESCE flag is required. 2048 */ 2049 sc->dc_pmode = DC_PMODE_MII; 2050 break; 2051 case DC_DEVICEID_RS7112: 2052 sc->dc_type = DC_TYPE_CONEXANT; 2053 sc->dc_flags |= DC_TX_INTR_ALWAYS; 2054 sc->dc_flags |= DC_REDUCED_MII_POLL; 2055 sc->dc_pmode = DC_PMODE_MII; 2056 dc_read_srom(sc, sc->dc_romwidth); 2057 break; 2058 default: 2059 printf("dc%d: unknown device: %x\n", sc->dc_unit, 2060 sc->dc_info->dc_did); 2061 break; 2062 } 2063 2064 /* Save the cache line size. */ 2065 if (DC_IS_DAVICOM(sc)) 2066 sc->dc_cachesize = 0; 2067 else 2068 sc->dc_cachesize = pci_read_config(dev, 2069 DC_PCI_CFLT, 4) & 0xFF; 2070 2071 /* Reset the adapter. */ 2072 dc_reset(sc); 2073 2074 /* Take 21143 out of snooze mode */ 2075 if (DC_IS_INTEL(sc) || DC_IS_XIRCOM(sc)) { 2076 command = pci_read_config(dev, DC_PCI_CFDD, 4); 2077 command &= ~(DC_CFDD_SNOOZE_MODE | DC_CFDD_SLEEP_MODE); 2078 pci_write_config(dev, DC_PCI_CFDD, command, 4); 2079 } 2080 2081 /* 2082 * Try to learn something about the supported media. 2083 * We know that ASIX and ADMtek and Davicom devices 2084 * will *always* be using MII media, so that's a no-brainer. 2085 * The tricky ones are the Macronix/PNIC II and the 2086 * Intel 21143. 2087 */ 2088 if (DC_IS_INTEL(sc)) 2089 dc_parse_21143_srom(sc); 2090 else if (DC_IS_MACRONIX(sc) || DC_IS_PNICII(sc)) { 2091 if (sc->dc_type == DC_TYPE_98713) 2092 sc->dc_pmode = DC_PMODE_MII; 2093 else 2094 sc->dc_pmode = DC_PMODE_SYM; 2095 } else if (!sc->dc_pmode) 2096 sc->dc_pmode = DC_PMODE_MII; 2097 2098 /* 2099 * Get station address from the EEPROM. 2100 */ 2101 switch(sc->dc_type) { 2102 case DC_TYPE_98713: 2103 case DC_TYPE_98713A: 2104 case DC_TYPE_987x5: 2105 case DC_TYPE_PNICII: 2106 dc_read_eeprom(sc, (caddr_t)&mac_offset, 2107 (DC_EE_NODEADDR_OFFSET / 2), 1, 0); 2108 dc_read_eeprom(sc, (caddr_t)&eaddr, (mac_offset / 2), 3, 0); 2109 break; 2110 case DC_TYPE_PNIC: 2111 dc_read_eeprom(sc, (caddr_t)&eaddr, 0, 3, 1); 2112 break; 2113 case DC_TYPE_DM9102: 2114 dc_read_eeprom(sc, (caddr_t)&eaddr, DC_EE_NODEADDR, 3, 0); 2115 #ifdef __sparc64__ 2116 /* 2117 * If this is an onboard dc(4) the station address read from 2118 * the EEPROM is all zero and we have to get it from the fcode. 2119 */ 2120 for (i = 0; i < ETHER_ADDR_LEN; i++) 2121 if (eaddr[i] != 0x00) 2122 break; 2123 if (i >= ETHER_ADDR_LEN && OF_getetheraddr2(dev, eaddr) == -1) 2124 OF_getetheraddr(dev, eaddr); 2125 #endif 2126 break; 2127 case DC_TYPE_21143: 2128 case DC_TYPE_ASIX: 2129 dc_read_eeprom(sc, (caddr_t)&eaddr, DC_EE_NODEADDR, 3, 0); 2130 break; 2131 case DC_TYPE_AL981: 2132 case DC_TYPE_AN985: 2133 *(u_int32_t *)(&eaddr[0]) = CSR_READ_4(sc, DC_AL_PAR0); 2134 *(u_int16_t *)(&eaddr[4]) = CSR_READ_4(sc, DC_AL_PAR1); 2135 break; 2136 case DC_TYPE_CONEXANT: 2137 bcopy(sc->dc_srom + DC_CONEXANT_EE_NODEADDR, &eaddr, 2138 ETHER_ADDR_LEN); 2139 break; 2140 case DC_TYPE_XIRCOM: 2141 /* The MAC comes from the CIS. */ 2142 mac = pci_get_ether(dev); 2143 if (!mac) { 2144 device_printf(dev, "No station address in CIS!\n"); 2145 error = ENXIO; 2146 goto fail; 2147 } 2148 bcopy(mac, eaddr, ETHER_ADDR_LEN); 2149 break; 2150 default: 2151 dc_read_eeprom(sc, (caddr_t)&eaddr, DC_EE_NODEADDR, 3, 0); 2152 break; 2153 } 2154 2155 /* 2156 * A 21143 or clone chip was detected. Inform the world. 2157 */ 2158 printf("dc%d: Ethernet address: %6D\n", unit, eaddr, ":"); 2159 2160 sc->dc_unit = unit; 2161 bcopy(eaddr, &sc->arpcom.ac_enaddr, ETHER_ADDR_LEN); 2162 2163 /* Allocate a busdma tag and DMA safe memory for TX/RX descriptors. */ 2164 error = bus_dma_tag_create(NULL, PAGE_SIZE, 0, BUS_SPACE_MAXADDR_32BIT, 2165 BUS_SPACE_MAXADDR, NULL, NULL, sizeof(struct dc_list_data), 1, 2166 sizeof(struct dc_list_data), 0, NULL, NULL, &sc->dc_ltag); 2167 if (error) { 2168 printf("dc%d: failed to allocate busdma tag\n", unit); 2169 error = ENXIO; 2170 goto fail; 2171 } 2172 error = bus_dmamem_alloc(sc->dc_ltag, (void **)&sc->dc_ldata, 2173 BUS_DMA_NOWAIT | BUS_DMA_ZERO, &sc->dc_lmap); 2174 if (error) { 2175 printf("dc%d: failed to allocate DMA safe memory\n", unit); 2176 error = ENXIO; 2177 goto fail; 2178 } 2179 error = bus_dmamap_load(sc->dc_ltag, sc->dc_lmap, sc->dc_ldata, 2180 sizeof(struct dc_list_data), dc_dma_map_addr, &sc->dc_laddr, 2181 BUS_DMA_NOWAIT); 2182 if (error) { 2183 printf("dc%d: cannot get address of the descriptors\n", unit); 2184 error = ENXIO; 2185 goto fail; 2186 } 2187 2188 /* 2189 * Allocate a busdma tag and DMA safe memory for the multicast 2190 * setup frame. 2191 */ 2192 error = bus_dma_tag_create(NULL, PAGE_SIZE, 0, BUS_SPACE_MAXADDR_32BIT, 2193 BUS_SPACE_MAXADDR, NULL, NULL, DC_SFRAME_LEN + DC_MIN_FRAMELEN, 1, 2194 DC_SFRAME_LEN + DC_MIN_FRAMELEN, 0, NULL, NULL, &sc->dc_stag); 2195 if (error) { 2196 printf("dc%d: failed to allocate busdma tag\n", unit); 2197 error = ENXIO; 2198 goto fail; 2199 } 2200 error = bus_dmamem_alloc(sc->dc_stag, (void **)&sc->dc_cdata.dc_sbuf, 2201 BUS_DMA_NOWAIT, &sc->dc_smap); 2202 if (error) { 2203 printf("dc%d: failed to allocate DMA safe memory\n", unit); 2204 error = ENXIO; 2205 goto fail; 2206 } 2207 error = bus_dmamap_load(sc->dc_stag, sc->dc_smap, sc->dc_cdata.dc_sbuf, 2208 DC_SFRAME_LEN, dc_dma_map_addr, &sc->dc_saddr, BUS_DMA_NOWAIT); 2209 if (error) { 2210 printf("dc%d: cannot get address of the descriptors\n", unit); 2211 error = ENXIO; 2212 goto fail; 2213 } 2214 2215 /* Allocate a busdma tag for mbufs. */ 2216 error = bus_dma_tag_create(NULL, PAGE_SIZE, 0, BUS_SPACE_MAXADDR_32BIT, 2217 BUS_SPACE_MAXADDR, NULL, NULL, MCLBYTES * DC_TX_LIST_CNT, 2218 DC_TX_LIST_CNT, MCLBYTES, 0, NULL, NULL, &sc->dc_mtag); 2219 if (error) { 2220 printf("dc%d: failed to allocate busdma tag\n", unit); 2221 error = ENXIO; 2222 goto fail; 2223 } 2224 2225 /* Create the TX/RX busdma maps. */ 2226 for (i = 0; i < DC_TX_LIST_CNT; i++) { 2227 error = bus_dmamap_create(sc->dc_mtag, 0, 2228 &sc->dc_cdata.dc_tx_map[i]); 2229 if (error) { 2230 printf("dc%d: failed to init TX ring\n", unit); 2231 error = ENXIO; 2232 goto fail; 2233 } 2234 } 2235 for (i = 0; i < DC_RX_LIST_CNT; i++) { 2236 error = bus_dmamap_create(sc->dc_mtag, 0, 2237 &sc->dc_cdata.dc_rx_map[i]); 2238 if (error) { 2239 printf("dc%d: failed to init RX ring\n", unit); 2240 error = ENXIO; 2241 goto fail; 2242 } 2243 } 2244 error = bus_dmamap_create(sc->dc_mtag, 0, &sc->dc_sparemap); 2245 if (error) { 2246 printf("dc%d: failed to init RX ring\n", unit); 2247 error = ENXIO; 2248 goto fail; 2249 } 2250 2251 ifp = &sc->arpcom.ac_if; 2252 ifp->if_softc = sc; 2253 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 2254 /* XXX: bleah, MTU gets overwritten in ether_ifattach() */ 2255 ifp->if_mtu = ETHERMTU; 2256 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 2257 ifp->if_ioctl = dc_ioctl; 2258 ifp->if_start = dc_start; 2259 ifp->if_watchdog = dc_watchdog; 2260 ifp->if_init = dc_init; 2261 ifp->if_baudrate = 10000000; 2262 ifp->if_snd.ifq_maxlen = DC_TX_LIST_CNT - 1; 2263 2264 /* 2265 * Do MII setup. If this is a 21143, check for a PHY on the 2266 * MII bus after applying any necessary fixups to twiddle the 2267 * GPIO bits. If we don't end up finding a PHY, restore the 2268 * old selection (SIA only or SIA/SYM) and attach the dcphy 2269 * driver instead. 2270 */ 2271 if (DC_IS_INTEL(sc)) { 2272 dc_apply_fixup(sc, IFM_AUTO); 2273 tmp = sc->dc_pmode; 2274 sc->dc_pmode = DC_PMODE_MII; 2275 } 2276 2277 error = mii_phy_probe(dev, &sc->dc_miibus, 2278 dc_ifmedia_upd, dc_ifmedia_sts); 2279 2280 if (error && DC_IS_INTEL(sc)) { 2281 sc->dc_pmode = tmp; 2282 if (sc->dc_pmode != DC_PMODE_SIA) 2283 sc->dc_pmode = DC_PMODE_SYM; 2284 sc->dc_flags |= DC_21143_NWAY; 2285 mii_phy_probe(dev, &sc->dc_miibus, 2286 dc_ifmedia_upd, dc_ifmedia_sts); 2287 /* 2288 * For non-MII cards, we need to have the 21143 2289 * drive the LEDs. Except there are some systems 2290 * like the NEC VersaPro NoteBook PC which have no 2291 * LEDs, and twiddling these bits has adverse effects 2292 * on them. (I.e. you suddenly can't get a link.) 2293 */ 2294 if (pci_read_config(dev, DC_PCI_CSID, 4) != 0x80281033) 2295 sc->dc_flags |= DC_TULIP_LEDS; 2296 error = 0; 2297 } 2298 2299 if (error) { 2300 printf("dc%d: MII without any PHY!\n", sc->dc_unit); 2301 goto fail; 2302 } 2303 2304 if (DC_IS_XIRCOM(sc)) { 2305 /* 2306 * setup General Purpose Port mode and data so the tulip 2307 * can talk to the MII. 2308 */ 2309 CSR_WRITE_4(sc, DC_SIAGP, DC_SIAGP_WRITE_EN | DC_SIAGP_INT1_EN | 2310 DC_SIAGP_MD_GP2_OUTPUT | DC_SIAGP_MD_GP0_OUTPUT); 2311 DELAY(10); 2312 CSR_WRITE_4(sc, DC_SIAGP, DC_SIAGP_INT1_EN | 2313 DC_SIAGP_MD_GP2_OUTPUT | DC_SIAGP_MD_GP0_OUTPUT); 2314 DELAY(10); 2315 } 2316 2317 if (DC_IS_ADMTEK(sc)) { 2318 /* 2319 * Set automatic TX underrun recovery for the ADMtek chips 2320 */ 2321 DC_SETBIT(sc, DC_AL_CR, DC_AL_CR_ATUR); 2322 } 2323 2324 /* 2325 * Tell the upper layer(s) we support long frames. 2326 */ 2327 ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header); 2328 ifp->if_capabilities |= IFCAP_VLAN_MTU; 2329 2330 callout_init(&sc->dc_stat_ch, IS_MPSAFE ? CALLOUT_MPSAFE : 0); 2331 2332 #ifdef SRM_MEDIA 2333 sc->dc_srm_media = 0; 2334 2335 /* Remember the SRM console media setting */ 2336 if (DC_IS_INTEL(sc)) { 2337 command = pci_read_config(dev, DC_PCI_CFDD, 4); 2338 command &= ~(DC_CFDD_SNOOZE_MODE | DC_CFDD_SLEEP_MODE); 2339 switch ((command >> 8) & 0xff) { 2340 case 3: 2341 sc->dc_srm_media = IFM_10_T; 2342 break; 2343 case 4: 2344 sc->dc_srm_media = IFM_10_T | IFM_FDX; 2345 break; 2346 case 5: 2347 sc->dc_srm_media = IFM_100_TX; 2348 break; 2349 case 6: 2350 sc->dc_srm_media = IFM_100_TX | IFM_FDX; 2351 break; 2352 } 2353 if (sc->dc_srm_media) 2354 sc->dc_srm_media |= IFM_ACTIVE | IFM_ETHER; 2355 } 2356 #endif 2357 2358 /* 2359 * Call MI attach routine. 2360 */ 2361 ether_ifattach(ifp, eaddr); 2362 2363 /* Hook interrupt last to avoid having to lock softc */ 2364 error = bus_setup_intr(dev, sc->dc_irq, INTR_TYPE_NET | 2365 (IS_MPSAFE ? INTR_MPSAFE : 0), 2366 dc_intr, sc, &sc->dc_intrhand); 2367 2368 if (error) { 2369 printf("dc%d: couldn't set up irq\n", unit); 2370 ether_ifdetach(ifp); 2371 goto fail; 2372 } 2373 2374 fail: 2375 if (error) 2376 dc_detach(dev); 2377 return (error); 2378 } 2379 2380 /* 2381 * Shutdown hardware and free up resources. This can be called any 2382 * time after the mutex has been initialized. It is called in both 2383 * the error case in attach and the normal detach case so it needs 2384 * to be careful about only freeing resources that have actually been 2385 * allocated. 2386 */ 2387 static int 2388 dc_detach(device_t dev) 2389 { 2390 struct dc_softc *sc; 2391 struct ifnet *ifp; 2392 struct dc_mediainfo *m; 2393 int i; 2394 2395 sc = device_get_softc(dev); 2396 KASSERT(mtx_initialized(&sc->dc_mtx), ("dc mutex not initialized")); 2397 DC_LOCK(sc); 2398 2399 ifp = &sc->arpcom.ac_if; 2400 2401 /* These should only be active if attach succeeded */ 2402 if (device_is_attached(dev)) { 2403 dc_stop(sc); 2404 ether_ifdetach(ifp); 2405 } 2406 if (sc->dc_miibus) 2407 device_delete_child(dev, sc->dc_miibus); 2408 bus_generic_detach(dev); 2409 2410 if (sc->dc_intrhand) 2411 bus_teardown_intr(dev, sc->dc_irq, sc->dc_intrhand); 2412 if (sc->dc_irq) 2413 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->dc_irq); 2414 if (sc->dc_res) 2415 bus_release_resource(dev, DC_RES, DC_RID, sc->dc_res); 2416 2417 if (sc->dc_cdata.dc_sbuf != NULL) 2418 bus_dmamem_free(sc->dc_stag, sc->dc_cdata.dc_sbuf, sc->dc_smap); 2419 if (sc->dc_ldata != NULL) 2420 bus_dmamem_free(sc->dc_ltag, sc->dc_ldata, sc->dc_lmap); 2421 for (i = 0; i < DC_TX_LIST_CNT; i++) 2422 bus_dmamap_destroy(sc->dc_mtag, sc->dc_cdata.dc_tx_map[i]); 2423 for (i = 0; i < DC_RX_LIST_CNT; i++) 2424 bus_dmamap_destroy(sc->dc_mtag, sc->dc_cdata.dc_rx_map[i]); 2425 bus_dmamap_destroy(sc->dc_mtag, sc->dc_sparemap); 2426 if (sc->dc_stag) 2427 bus_dma_tag_destroy(sc->dc_stag); 2428 if (sc->dc_mtag) 2429 bus_dma_tag_destroy(sc->dc_mtag); 2430 if (sc->dc_ltag) 2431 bus_dma_tag_destroy(sc->dc_ltag); 2432 2433 free(sc->dc_pnic_rx_buf, M_DEVBUF); 2434 2435 while (sc->dc_mi != NULL) { 2436 m = sc->dc_mi->dc_next; 2437 free(sc->dc_mi, M_DEVBUF); 2438 sc->dc_mi = m; 2439 } 2440 free(sc->dc_srom, M_DEVBUF); 2441 2442 DC_UNLOCK(sc); 2443 mtx_destroy(&sc->dc_mtx); 2444 2445 return (0); 2446 } 2447 2448 /* 2449 * Initialize the transmit descriptors. 2450 */ 2451 static int 2452 dc_list_tx_init(struct dc_softc *sc) 2453 { 2454 struct dc_chain_data *cd; 2455 struct dc_list_data *ld; 2456 int i, nexti; 2457 2458 cd = &sc->dc_cdata; 2459 ld = sc->dc_ldata; 2460 for (i = 0; i < DC_TX_LIST_CNT; i++) { 2461 if (i == DC_TX_LIST_CNT - 1) 2462 nexti = 0; 2463 else 2464 nexti = i + 1; 2465 ld->dc_tx_list[i].dc_next = htole32(DC_TXDESC(sc, nexti)); 2466 cd->dc_tx_chain[i] = NULL; 2467 ld->dc_tx_list[i].dc_data = 0; 2468 ld->dc_tx_list[i].dc_ctl = 0; 2469 } 2470 2471 cd->dc_tx_prod = cd->dc_tx_cons = cd->dc_tx_cnt = 0; 2472 bus_dmamap_sync(sc->dc_ltag, sc->dc_lmap, 2473 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2474 return (0); 2475 } 2476 2477 2478 /* 2479 * Initialize the RX descriptors and allocate mbufs for them. Note that 2480 * we arrange the descriptors in a closed ring, so that the last descriptor 2481 * points back to the first. 2482 */ 2483 static int 2484 dc_list_rx_init(struct dc_softc *sc) 2485 { 2486 struct dc_chain_data *cd; 2487 struct dc_list_data *ld; 2488 int i, nexti; 2489 2490 cd = &sc->dc_cdata; 2491 ld = sc->dc_ldata; 2492 2493 for (i = 0; i < DC_RX_LIST_CNT; i++) { 2494 if (dc_newbuf(sc, i, 1) != 0) 2495 return (ENOBUFS); 2496 if (i == DC_RX_LIST_CNT - 1) 2497 nexti = 0; 2498 else 2499 nexti = i + 1; 2500 ld->dc_rx_list[i].dc_next = htole32(DC_RXDESC(sc, nexti)); 2501 } 2502 2503 cd->dc_rx_prod = 0; 2504 bus_dmamap_sync(sc->dc_ltag, sc->dc_lmap, 2505 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2506 return (0); 2507 } 2508 2509 static void 2510 dc_dma_map_rxbuf(arg, segs, nseg, mapsize, error) 2511 void *arg; 2512 bus_dma_segment_t *segs; 2513 int nseg; 2514 bus_size_t mapsize; 2515 int error; 2516 { 2517 struct dc_softc *sc; 2518 struct dc_desc *c; 2519 2520 sc = arg; 2521 c = &sc->dc_ldata->dc_rx_list[sc->dc_cdata.dc_rx_cur]; 2522 if (error) { 2523 sc->dc_cdata.dc_rx_err = error; 2524 return; 2525 } 2526 2527 KASSERT(nseg == 1, ("wrong number of segments, should be 1")); 2528 sc->dc_cdata.dc_rx_err = 0; 2529 c->dc_data = htole32(segs->ds_addr); 2530 } 2531 2532 /* 2533 * Initialize an RX descriptor and attach an MBUF cluster. 2534 */ 2535 static int 2536 dc_newbuf(struct dc_softc *sc, int i, int alloc) 2537 { 2538 struct mbuf *m_new; 2539 bus_dmamap_t tmp; 2540 int error; 2541 2542 if (alloc) { 2543 m_new = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR); 2544 if (m_new == NULL) 2545 return (ENOBUFS); 2546 } else { 2547 m_new = sc->dc_cdata.dc_rx_chain[i]; 2548 m_new->m_data = m_new->m_ext.ext_buf; 2549 } 2550 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 2551 m_adj(m_new, sizeof(u_int64_t)); 2552 2553 /* 2554 * If this is a PNIC chip, zero the buffer. This is part 2555 * of the workaround for the receive bug in the 82c168 and 2556 * 82c169 chips. 2557 */ 2558 if (sc->dc_flags & DC_PNIC_RX_BUG_WAR) 2559 bzero(mtod(m_new, char *), m_new->m_len); 2560 2561 /* No need to remap the mbuf if we're reusing it. */ 2562 if (alloc) { 2563 sc->dc_cdata.dc_rx_cur = i; 2564 error = bus_dmamap_load_mbuf(sc->dc_mtag, sc->dc_sparemap, 2565 m_new, dc_dma_map_rxbuf, sc, 0); 2566 if (error) { 2567 m_freem(m_new); 2568 return (error); 2569 } 2570 if (sc->dc_cdata.dc_rx_err != 0) { 2571 m_freem(m_new); 2572 return (sc->dc_cdata.dc_rx_err); 2573 } 2574 bus_dmamap_unload(sc->dc_mtag, sc->dc_cdata.dc_rx_map[i]); 2575 tmp = sc->dc_cdata.dc_rx_map[i]; 2576 sc->dc_cdata.dc_rx_map[i] = sc->dc_sparemap; 2577 sc->dc_sparemap = tmp; 2578 sc->dc_cdata.dc_rx_chain[i] = m_new; 2579 } 2580 2581 sc->dc_ldata->dc_rx_list[i].dc_ctl = htole32(DC_RXCTL_RLINK | DC_RXLEN); 2582 sc->dc_ldata->dc_rx_list[i].dc_status = htole32(DC_RXSTAT_OWN); 2583 bus_dmamap_sync(sc->dc_mtag, sc->dc_cdata.dc_rx_map[i], 2584 BUS_DMASYNC_PREREAD); 2585 bus_dmamap_sync(sc->dc_ltag, sc->dc_lmap, 2586 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2587 return (0); 2588 } 2589 2590 /* 2591 * Grrrrr. 2592 * The PNIC chip has a terrible bug in it that manifests itself during 2593 * periods of heavy activity. The exact mode of failure if difficult to 2594 * pinpoint: sometimes it only happens in promiscuous mode, sometimes it 2595 * will happen on slow machines. The bug is that sometimes instead of 2596 * uploading one complete frame during reception, it uploads what looks 2597 * like the entire contents of its FIFO memory. The frame we want is at 2598 * the end of the whole mess, but we never know exactly how much data has 2599 * been uploaded, so salvaging the frame is hard. 2600 * 2601 * There is only one way to do it reliably, and it's disgusting. 2602 * Here's what we know: 2603 * 2604 * - We know there will always be somewhere between one and three extra 2605 * descriptors uploaded. 2606 * 2607 * - We know the desired received frame will always be at the end of the 2608 * total data upload. 2609 * 2610 * - We know the size of the desired received frame because it will be 2611 * provided in the length field of the status word in the last descriptor. 2612 * 2613 * Here's what we do: 2614 * 2615 * - When we allocate buffers for the receive ring, we bzero() them. 2616 * This means that we know that the buffer contents should be all 2617 * zeros, except for data uploaded by the chip. 2618 * 2619 * - We also force the PNIC chip to upload frames that include the 2620 * ethernet CRC at the end. 2621 * 2622 * - We gather all of the bogus frame data into a single buffer. 2623 * 2624 * - We then position a pointer at the end of this buffer and scan 2625 * backwards until we encounter the first non-zero byte of data. 2626 * This is the end of the received frame. We know we will encounter 2627 * some data at the end of the frame because the CRC will always be 2628 * there, so even if the sender transmits a packet of all zeros, 2629 * we won't be fooled. 2630 * 2631 * - We know the size of the actual received frame, so we subtract 2632 * that value from the current pointer location. This brings us 2633 * to the start of the actual received packet. 2634 * 2635 * - We copy this into an mbuf and pass it on, along with the actual 2636 * frame length. 2637 * 2638 * The performance hit is tremendous, but it beats dropping frames all 2639 * the time. 2640 */ 2641 2642 #define DC_WHOLEFRAME (DC_RXSTAT_FIRSTFRAG | DC_RXSTAT_LASTFRAG) 2643 static void 2644 dc_pnic_rx_bug_war(struct dc_softc *sc, int idx) 2645 { 2646 struct dc_desc *cur_rx; 2647 struct dc_desc *c = NULL; 2648 struct mbuf *m = NULL; 2649 unsigned char *ptr; 2650 int i, total_len; 2651 u_int32_t rxstat = 0; 2652 2653 i = sc->dc_pnic_rx_bug_save; 2654 cur_rx = &sc->dc_ldata->dc_rx_list[idx]; 2655 ptr = sc->dc_pnic_rx_buf; 2656 bzero(ptr, DC_RXLEN * 5); 2657 2658 /* Copy all the bytes from the bogus buffers. */ 2659 while (1) { 2660 c = &sc->dc_ldata->dc_rx_list[i]; 2661 rxstat = le32toh(c->dc_status); 2662 m = sc->dc_cdata.dc_rx_chain[i]; 2663 bcopy(mtod(m, char *), ptr, DC_RXLEN); 2664 ptr += DC_RXLEN; 2665 /* If this is the last buffer, break out. */ 2666 if (i == idx || rxstat & DC_RXSTAT_LASTFRAG) 2667 break; 2668 dc_newbuf(sc, i, 0); 2669 DC_INC(i, DC_RX_LIST_CNT); 2670 } 2671 2672 /* Find the length of the actual receive frame. */ 2673 total_len = DC_RXBYTES(rxstat); 2674 2675 /* Scan backwards until we hit a non-zero byte. */ 2676 while (*ptr == 0x00) 2677 ptr--; 2678 2679 /* Round off. */ 2680 if ((uintptr_t)(ptr) & 0x3) 2681 ptr -= 1; 2682 2683 /* Now find the start of the frame. */ 2684 ptr -= total_len; 2685 if (ptr < sc->dc_pnic_rx_buf) 2686 ptr = sc->dc_pnic_rx_buf; 2687 2688 /* 2689 * Now copy the salvaged frame to the last mbuf and fake up 2690 * the status word to make it look like a successful 2691 * frame reception. 2692 */ 2693 dc_newbuf(sc, i, 0); 2694 bcopy(ptr, mtod(m, char *), total_len); 2695 cur_rx->dc_status = htole32(rxstat | DC_RXSTAT_FIRSTFRAG); 2696 } 2697 2698 /* 2699 * This routine searches the RX ring for dirty descriptors in the 2700 * event that the rxeof routine falls out of sync with the chip's 2701 * current descriptor pointer. This may happen sometimes as a result 2702 * of a "no RX buffer available" condition that happens when the chip 2703 * consumes all of the RX buffers before the driver has a chance to 2704 * process the RX ring. This routine may need to be called more than 2705 * once to bring the driver back in sync with the chip, however we 2706 * should still be getting RX DONE interrupts to drive the search 2707 * for new packets in the RX ring, so we should catch up eventually. 2708 */ 2709 static int 2710 dc_rx_resync(struct dc_softc *sc) 2711 { 2712 struct dc_desc *cur_rx; 2713 int i, pos; 2714 2715 pos = sc->dc_cdata.dc_rx_prod; 2716 2717 for (i = 0; i < DC_RX_LIST_CNT; i++) { 2718 cur_rx = &sc->dc_ldata->dc_rx_list[pos]; 2719 if (!(le32toh(cur_rx->dc_status) & DC_RXSTAT_OWN)) 2720 break; 2721 DC_INC(pos, DC_RX_LIST_CNT); 2722 } 2723 2724 /* If the ring really is empty, then just return. */ 2725 if (i == DC_RX_LIST_CNT) 2726 return (0); 2727 2728 /* We've fallen behing the chip: catch it. */ 2729 sc->dc_cdata.dc_rx_prod = pos; 2730 2731 return (EAGAIN); 2732 } 2733 2734 /* 2735 * A frame has been uploaded: pass the resulting mbuf chain up to 2736 * the higher level protocols. 2737 */ 2738 static void 2739 dc_rxeof(struct dc_softc *sc) 2740 { 2741 struct mbuf *m; 2742 struct ifnet *ifp; 2743 struct dc_desc *cur_rx; 2744 int i, total_len = 0; 2745 u_int32_t rxstat; 2746 2747 DC_LOCK_ASSERT(sc); 2748 2749 ifp = &sc->arpcom.ac_if; 2750 i = sc->dc_cdata.dc_rx_prod; 2751 2752 bus_dmamap_sync(sc->dc_ltag, sc->dc_lmap, BUS_DMASYNC_POSTREAD); 2753 while (!(le32toh(sc->dc_ldata->dc_rx_list[i].dc_status) & 2754 DC_RXSTAT_OWN)) { 2755 #ifdef DEVICE_POLLING 2756 if (ifp->if_flags & IFF_POLLING) { 2757 if (sc->rxcycles <= 0) 2758 break; 2759 sc->rxcycles--; 2760 } 2761 #endif 2762 cur_rx = &sc->dc_ldata->dc_rx_list[i]; 2763 rxstat = le32toh(cur_rx->dc_status); 2764 m = sc->dc_cdata.dc_rx_chain[i]; 2765 bus_dmamap_sync(sc->dc_mtag, sc->dc_cdata.dc_rx_map[i], 2766 BUS_DMASYNC_POSTREAD); 2767 total_len = DC_RXBYTES(rxstat); 2768 2769 if (sc->dc_flags & DC_PNIC_RX_BUG_WAR) { 2770 if ((rxstat & DC_WHOLEFRAME) != DC_WHOLEFRAME) { 2771 if (rxstat & DC_RXSTAT_FIRSTFRAG) 2772 sc->dc_pnic_rx_bug_save = i; 2773 if ((rxstat & DC_RXSTAT_LASTFRAG) == 0) { 2774 DC_INC(i, DC_RX_LIST_CNT); 2775 continue; 2776 } 2777 dc_pnic_rx_bug_war(sc, i); 2778 rxstat = le32toh(cur_rx->dc_status); 2779 total_len = DC_RXBYTES(rxstat); 2780 } 2781 } 2782 2783 /* 2784 * If an error occurs, update stats, clear the 2785 * status word and leave the mbuf cluster in place: 2786 * it should simply get re-used next time this descriptor 2787 * comes up in the ring. However, don't report long 2788 * frames as errors since they could be vlans. 2789 */ 2790 if ((rxstat & DC_RXSTAT_RXERR)) { 2791 if (!(rxstat & DC_RXSTAT_GIANT) || 2792 (rxstat & (DC_RXSTAT_CRCERR | DC_RXSTAT_DRIBBLE | 2793 DC_RXSTAT_MIIERE | DC_RXSTAT_COLLSEEN | 2794 DC_RXSTAT_RUNT | DC_RXSTAT_DE))) { 2795 ifp->if_ierrors++; 2796 if (rxstat & DC_RXSTAT_COLLSEEN) 2797 ifp->if_collisions++; 2798 dc_newbuf(sc, i, 0); 2799 if (rxstat & DC_RXSTAT_CRCERR) { 2800 DC_INC(i, DC_RX_LIST_CNT); 2801 continue; 2802 } else { 2803 dc_init(sc); 2804 return; 2805 } 2806 } 2807 } 2808 2809 /* No errors; receive the packet. */ 2810 total_len -= ETHER_CRC_LEN; 2811 #ifdef __i386__ 2812 /* 2813 * On the x86 we do not have alignment problems, so try to 2814 * allocate a new buffer for the receive ring, and pass up 2815 * the one where the packet is already, saving the expensive 2816 * copy done in m_devget(). 2817 * If we are on an architecture with alignment problems, or 2818 * if the allocation fails, then use m_devget and leave the 2819 * existing buffer in the receive ring. 2820 */ 2821 if (dc_quick && dc_newbuf(sc, i, 1) == 0) { 2822 m->m_pkthdr.rcvif = ifp; 2823 m->m_pkthdr.len = m->m_len = total_len; 2824 DC_INC(i, DC_RX_LIST_CNT); 2825 } else 2826 #endif 2827 { 2828 struct mbuf *m0; 2829 2830 m0 = m_devget(mtod(m, char *), total_len, 2831 ETHER_ALIGN, ifp, NULL); 2832 dc_newbuf(sc, i, 0); 2833 DC_INC(i, DC_RX_LIST_CNT); 2834 if (m0 == NULL) { 2835 ifp->if_ierrors++; 2836 continue; 2837 } 2838 m = m0; 2839 } 2840 2841 ifp->if_ipackets++; 2842 DC_UNLOCK(sc); 2843 (*ifp->if_input)(ifp, m); 2844 DC_LOCK(sc); 2845 } 2846 2847 sc->dc_cdata.dc_rx_prod = i; 2848 } 2849 2850 /* 2851 * A frame was downloaded to the chip. It's safe for us to clean up 2852 * the list buffers. 2853 */ 2854 2855 static void 2856 dc_txeof(struct dc_softc *sc) 2857 { 2858 struct dc_desc *cur_tx = NULL; 2859 struct ifnet *ifp; 2860 int idx; 2861 u_int32_t ctl, txstat; 2862 2863 ifp = &sc->arpcom.ac_if; 2864 2865 /* 2866 * Go through our tx list and free mbufs for those 2867 * frames that have been transmitted. 2868 */ 2869 bus_dmamap_sync(sc->dc_ltag, sc->dc_lmap, BUS_DMASYNC_POSTREAD); 2870 idx = sc->dc_cdata.dc_tx_cons; 2871 while (idx != sc->dc_cdata.dc_tx_prod) { 2872 2873 cur_tx = &sc->dc_ldata->dc_tx_list[idx]; 2874 txstat = le32toh(cur_tx->dc_status); 2875 ctl = le32toh(cur_tx->dc_ctl); 2876 2877 if (txstat & DC_TXSTAT_OWN) 2878 break; 2879 2880 if (!(ctl & DC_TXCTL_LASTFRAG) || ctl & DC_TXCTL_SETUP) { 2881 if (ctl & DC_TXCTL_SETUP) { 2882 /* 2883 * Yes, the PNIC is so brain damaged 2884 * that it will sometimes generate a TX 2885 * underrun error while DMAing the RX 2886 * filter setup frame. If we detect this, 2887 * we have to send the setup frame again, 2888 * or else the filter won't be programmed 2889 * correctly. 2890 */ 2891 if (DC_IS_PNIC(sc)) { 2892 if (txstat & DC_TXSTAT_ERRSUM) 2893 dc_setfilt(sc); 2894 } 2895 sc->dc_cdata.dc_tx_chain[idx] = NULL; 2896 } 2897 sc->dc_cdata.dc_tx_cnt--; 2898 DC_INC(idx, DC_TX_LIST_CNT); 2899 continue; 2900 } 2901 2902 if (DC_IS_XIRCOM(sc) || DC_IS_CONEXANT(sc)) { 2903 /* 2904 * XXX: Why does my Xircom taunt me so? 2905 * For some reason it likes setting the CARRLOST flag 2906 * even when the carrier is there. wtf?!? 2907 * Who knows, but Conexant chips have the 2908 * same problem. Maybe they took lessons 2909 * from Xircom. 2910 */ 2911 if (/*sc->dc_type == DC_TYPE_21143 &&*/ 2912 sc->dc_pmode == DC_PMODE_MII && 2913 ((txstat & 0xFFFF) & ~(DC_TXSTAT_ERRSUM | 2914 DC_TXSTAT_NOCARRIER))) 2915 txstat &= ~DC_TXSTAT_ERRSUM; 2916 } else { 2917 if (/*sc->dc_type == DC_TYPE_21143 &&*/ 2918 sc->dc_pmode == DC_PMODE_MII && 2919 ((txstat & 0xFFFF) & ~(DC_TXSTAT_ERRSUM | 2920 DC_TXSTAT_NOCARRIER | DC_TXSTAT_CARRLOST))) 2921 txstat &= ~DC_TXSTAT_ERRSUM; 2922 } 2923 2924 if (txstat & DC_TXSTAT_ERRSUM) { 2925 ifp->if_oerrors++; 2926 if (txstat & DC_TXSTAT_EXCESSCOLL) 2927 ifp->if_collisions++; 2928 if (txstat & DC_TXSTAT_LATECOLL) 2929 ifp->if_collisions++; 2930 if (!(txstat & DC_TXSTAT_UNDERRUN)) { 2931 dc_init(sc); 2932 return; 2933 } 2934 } 2935 2936 ifp->if_collisions += (txstat & DC_TXSTAT_COLLCNT) >> 3; 2937 2938 ifp->if_opackets++; 2939 if (sc->dc_cdata.dc_tx_chain[idx] != NULL) { 2940 bus_dmamap_sync(sc->dc_mtag, 2941 sc->dc_cdata.dc_tx_map[idx], 2942 BUS_DMASYNC_POSTWRITE); 2943 bus_dmamap_unload(sc->dc_mtag, 2944 sc->dc_cdata.dc_tx_map[idx]); 2945 m_freem(sc->dc_cdata.dc_tx_chain[idx]); 2946 sc->dc_cdata.dc_tx_chain[idx] = NULL; 2947 } 2948 2949 sc->dc_cdata.dc_tx_cnt--; 2950 DC_INC(idx, DC_TX_LIST_CNT); 2951 } 2952 2953 if (idx != sc->dc_cdata.dc_tx_cons) { 2954 /* Some buffers have been freed. */ 2955 sc->dc_cdata.dc_tx_cons = idx; 2956 ifp->if_flags &= ~IFF_OACTIVE; 2957 } 2958 ifp->if_timer = (sc->dc_cdata.dc_tx_cnt == 0) ? 0 : 5; 2959 } 2960 2961 static void 2962 dc_tick(void *xsc) 2963 { 2964 struct dc_softc *sc; 2965 struct mii_data *mii; 2966 struct ifnet *ifp; 2967 u_int32_t r; 2968 2969 sc = xsc; 2970 DC_LOCK(sc); 2971 ifp = &sc->arpcom.ac_if; 2972 mii = device_get_softc(sc->dc_miibus); 2973 2974 if (sc->dc_flags & DC_REDUCED_MII_POLL) { 2975 if (sc->dc_flags & DC_21143_NWAY) { 2976 r = CSR_READ_4(sc, DC_10BTSTAT); 2977 if (IFM_SUBTYPE(mii->mii_media_active) == 2978 IFM_100_TX && (r & DC_TSTAT_LS100)) { 2979 sc->dc_link = 0; 2980 mii_mediachg(mii); 2981 } 2982 if (IFM_SUBTYPE(mii->mii_media_active) == 2983 IFM_10_T && (r & DC_TSTAT_LS10)) { 2984 sc->dc_link = 0; 2985 mii_mediachg(mii); 2986 } 2987 if (sc->dc_link == 0) 2988 mii_tick(mii); 2989 } else { 2990 r = CSR_READ_4(sc, DC_ISR); 2991 if ((r & DC_ISR_RX_STATE) == DC_RXSTATE_WAIT && 2992 sc->dc_cdata.dc_tx_cnt == 0) { 2993 mii_tick(mii); 2994 if (!(mii->mii_media_status & IFM_ACTIVE)) 2995 sc->dc_link = 0; 2996 } 2997 } 2998 } else 2999 mii_tick(mii); 3000 3001 /* 3002 * When the init routine completes, we expect to be able to send 3003 * packets right away, and in fact the network code will send a 3004 * gratuitous ARP the moment the init routine marks the interface 3005 * as running. However, even though the MAC may have been initialized, 3006 * there may be a delay of a few seconds before the PHY completes 3007 * autonegotiation and the link is brought up. Any transmissions 3008 * made during that delay will be lost. Dealing with this is tricky: 3009 * we can't just pause in the init routine while waiting for the 3010 * PHY to come ready since that would bring the whole system to 3011 * a screeching halt for several seconds. 3012 * 3013 * What we do here is prevent the TX start routine from sending 3014 * any packets until a link has been established. After the 3015 * interface has been initialized, the tick routine will poll 3016 * the state of the PHY until the IFM_ACTIVE flag is set. Until 3017 * that time, packets will stay in the send queue, and once the 3018 * link comes up, they will be flushed out to the wire. 3019 */ 3020 if (!sc->dc_link && mii->mii_media_status & IFM_ACTIVE && 3021 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) { 3022 sc->dc_link++; 3023 if (ifp->if_snd.ifq_head != NULL) 3024 dc_start(ifp); 3025 } 3026 3027 if (sc->dc_flags & DC_21143_NWAY && !sc->dc_link) 3028 callout_reset(&sc->dc_stat_ch, hz/10, dc_tick, sc); 3029 else 3030 callout_reset(&sc->dc_stat_ch, hz, dc_tick, sc); 3031 3032 DC_UNLOCK(sc); 3033 } 3034 3035 /* 3036 * A transmit underrun has occurred. Back off the transmit threshold, 3037 * or switch to store and forward mode if we have to. 3038 */ 3039 static void 3040 dc_tx_underrun(struct dc_softc *sc) 3041 { 3042 u_int32_t isr; 3043 int i; 3044 3045 if (DC_IS_DAVICOM(sc)) 3046 dc_init(sc); 3047 3048 if (DC_IS_INTEL(sc)) { 3049 /* 3050 * The real 21143 requires that the transmitter be idle 3051 * in order to change the transmit threshold or store 3052 * and forward state. 3053 */ 3054 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_TX_ON); 3055 3056 for (i = 0; i < DC_TIMEOUT; i++) { 3057 isr = CSR_READ_4(sc, DC_ISR); 3058 if (isr & DC_ISR_TX_IDLE) 3059 break; 3060 DELAY(10); 3061 } 3062 if (i == DC_TIMEOUT) { 3063 printf("dc%d: failed to force tx to idle state\n", 3064 sc->dc_unit); 3065 dc_init(sc); 3066 } 3067 } 3068 3069 printf("dc%d: TX underrun -- ", sc->dc_unit); 3070 sc->dc_txthresh += DC_TXTHRESH_INC; 3071 if (sc->dc_txthresh > DC_TXTHRESH_MAX) { 3072 printf("using store and forward mode\n"); 3073 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_STORENFWD); 3074 } else { 3075 printf("increasing TX threshold\n"); 3076 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_TX_THRESH); 3077 DC_SETBIT(sc, DC_NETCFG, sc->dc_txthresh); 3078 } 3079 3080 if (DC_IS_INTEL(sc)) 3081 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_TX_ON); 3082 } 3083 3084 #ifdef DEVICE_POLLING 3085 static poll_handler_t dc_poll; 3086 3087 static void 3088 dc_poll(struct ifnet *ifp, enum poll_cmd cmd, int count) 3089 { 3090 struct dc_softc *sc = ifp->if_softc; 3091 3092 if (cmd == POLL_DEREGISTER) { /* final call, enable interrupts */ 3093 /* Re-enable interrupts. */ 3094 CSR_WRITE_4(sc, DC_IMR, DC_INTRS); 3095 return; 3096 } 3097 DC_LOCK(sc); 3098 sc->rxcycles = count; 3099 dc_rxeof(sc); 3100 dc_txeof(sc); 3101 if (ifp->if_snd.ifq_head != NULL && !(ifp->if_flags & IFF_OACTIVE)) 3102 dc_start(ifp); 3103 3104 if (cmd == POLL_AND_CHECK_STATUS) { /* also check status register */ 3105 u_int32_t status; 3106 3107 status = CSR_READ_4(sc, DC_ISR); 3108 status &= (DC_ISR_RX_WATDOGTIMEO | DC_ISR_RX_NOBUF | 3109 DC_ISR_TX_NOBUF | DC_ISR_TX_IDLE | DC_ISR_TX_UNDERRUN | 3110 DC_ISR_BUS_ERR); 3111 if (!status) { 3112 DC_UNLOCK(sc); 3113 return; 3114 } 3115 /* ack what we have */ 3116 CSR_WRITE_4(sc, DC_ISR, status); 3117 3118 if (status & (DC_ISR_RX_WATDOGTIMEO | DC_ISR_RX_NOBUF)) { 3119 u_int32_t r = CSR_READ_4(sc, DC_FRAMESDISCARDED); 3120 ifp->if_ierrors += (r & 0xffff) + ((r >> 17) & 0x7ff); 3121 3122 if (dc_rx_resync(sc)) 3123 dc_rxeof(sc); 3124 } 3125 /* restart transmit unit if necessary */ 3126 if (status & DC_ISR_TX_IDLE && sc->dc_cdata.dc_tx_cnt) 3127 CSR_WRITE_4(sc, DC_TXSTART, 0xFFFFFFFF); 3128 3129 if (status & DC_ISR_TX_UNDERRUN) 3130 dc_tx_underrun(sc); 3131 3132 if (status & DC_ISR_BUS_ERR) { 3133 printf("dc_poll: dc%d bus error\n", sc->dc_unit); 3134 dc_reset(sc); 3135 dc_init(sc); 3136 } 3137 } 3138 DC_UNLOCK(sc); 3139 } 3140 #endif /* DEVICE_POLLING */ 3141 3142 static void 3143 dc_intr(void *arg) 3144 { 3145 struct dc_softc *sc; 3146 struct ifnet *ifp; 3147 u_int32_t status; 3148 3149 sc = arg; 3150 3151 if (sc->suspended) 3152 return; 3153 3154 if ((CSR_READ_4(sc, DC_ISR) & DC_INTRS) == 0) 3155 return; 3156 3157 DC_LOCK(sc); 3158 ifp = &sc->arpcom.ac_if; 3159 #ifdef DEVICE_POLLING 3160 if (ifp->if_flags & IFF_POLLING) 3161 goto done; 3162 if (ether_poll_register(dc_poll, ifp)) { /* ok, disable interrupts */ 3163 CSR_WRITE_4(sc, DC_IMR, 0x00000000); 3164 goto done; 3165 } 3166 #endif 3167 3168 /* Suppress unwanted interrupts */ 3169 if (!(ifp->if_flags & IFF_UP)) { 3170 if (CSR_READ_4(sc, DC_ISR) & DC_INTRS) 3171 dc_stop(sc); 3172 DC_UNLOCK(sc); 3173 return; 3174 } 3175 3176 /* Disable interrupts. */ 3177 CSR_WRITE_4(sc, DC_IMR, 0x00000000); 3178 3179 while (((status = CSR_READ_4(sc, DC_ISR)) & DC_INTRS) 3180 && status != 0xFFFFFFFF) { 3181 3182 CSR_WRITE_4(sc, DC_ISR, status); 3183 3184 if (status & DC_ISR_RX_OK) { 3185 int curpkts; 3186 curpkts = ifp->if_ipackets; 3187 dc_rxeof(sc); 3188 if (curpkts == ifp->if_ipackets) { 3189 while (dc_rx_resync(sc)) 3190 dc_rxeof(sc); 3191 } 3192 } 3193 3194 if (status & (DC_ISR_TX_OK | DC_ISR_TX_NOBUF)) 3195 dc_txeof(sc); 3196 3197 if (status & DC_ISR_TX_IDLE) { 3198 dc_txeof(sc); 3199 if (sc->dc_cdata.dc_tx_cnt) { 3200 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_TX_ON); 3201 CSR_WRITE_4(sc, DC_TXSTART, 0xFFFFFFFF); 3202 } 3203 } 3204 3205 if (status & DC_ISR_TX_UNDERRUN) 3206 dc_tx_underrun(sc); 3207 3208 if ((status & DC_ISR_RX_WATDOGTIMEO) 3209 || (status & DC_ISR_RX_NOBUF)) { 3210 int curpkts; 3211 curpkts = ifp->if_ipackets; 3212 dc_rxeof(sc); 3213 if (curpkts == ifp->if_ipackets) { 3214 while (dc_rx_resync(sc)) 3215 dc_rxeof(sc); 3216 } 3217 } 3218 3219 if (status & DC_ISR_BUS_ERR) { 3220 dc_reset(sc); 3221 dc_init(sc); 3222 } 3223 } 3224 3225 /* Re-enable interrupts. */ 3226 CSR_WRITE_4(sc, DC_IMR, DC_INTRS); 3227 3228 if (ifp->if_snd.ifq_head != NULL) 3229 dc_start(ifp); 3230 3231 #ifdef DEVICE_POLLING 3232 done: 3233 #endif 3234 3235 DC_UNLOCK(sc); 3236 } 3237 3238 static void 3239 dc_dma_map_txbuf(arg, segs, nseg, mapsize, error) 3240 void *arg; 3241 bus_dma_segment_t *segs; 3242 int nseg; 3243 bus_size_t mapsize; 3244 int error; 3245 { 3246 struct dc_softc *sc; 3247 struct dc_desc *f; 3248 int cur, first, frag, i; 3249 3250 sc = arg; 3251 if (error) { 3252 sc->dc_cdata.dc_tx_err = error; 3253 return; 3254 } 3255 3256 first = cur = frag = sc->dc_cdata.dc_tx_prod; 3257 for (i = 0; i < nseg; i++) { 3258 if ((sc->dc_flags & DC_TX_ADMTEK_WAR) && 3259 (frag == (DC_TX_LIST_CNT - 1)) && 3260 (first != sc->dc_cdata.dc_tx_first)) { 3261 bus_dmamap_unload(sc->dc_mtag, 3262 sc->dc_cdata.dc_tx_map[first]); 3263 sc->dc_cdata.dc_tx_err = ENOBUFS; 3264 return; 3265 } 3266 3267 f = &sc->dc_ldata->dc_tx_list[frag]; 3268 f->dc_ctl = htole32(DC_TXCTL_TLINK | segs[i].ds_len); 3269 if (i == 0) { 3270 f->dc_status = 0; 3271 f->dc_ctl |= htole32(DC_TXCTL_FIRSTFRAG); 3272 } else 3273 f->dc_status = htole32(DC_TXSTAT_OWN); 3274 f->dc_data = htole32(segs[i].ds_addr); 3275 cur = frag; 3276 DC_INC(frag, DC_TX_LIST_CNT); 3277 } 3278 3279 sc->dc_cdata.dc_tx_err = 0; 3280 sc->dc_cdata.dc_tx_prod = frag; 3281 sc->dc_cdata.dc_tx_cnt += nseg; 3282 sc->dc_ldata->dc_tx_list[cur].dc_ctl |= htole32(DC_TXCTL_LASTFRAG); 3283 sc->dc_cdata.dc_tx_chain[cur] = sc->dc_cdata.dc_tx_mapping; 3284 if (sc->dc_flags & DC_TX_INTR_FIRSTFRAG) 3285 sc->dc_ldata->dc_tx_list[first].dc_ctl |= 3286 htole32(DC_TXCTL_FINT); 3287 if (sc->dc_flags & DC_TX_INTR_ALWAYS) 3288 sc->dc_ldata->dc_tx_list[cur].dc_ctl |= htole32(DC_TXCTL_FINT); 3289 if (sc->dc_flags & DC_TX_USE_TX_INTR && sc->dc_cdata.dc_tx_cnt > 64) 3290 sc->dc_ldata->dc_tx_list[cur].dc_ctl |= htole32(DC_TXCTL_FINT); 3291 sc->dc_ldata->dc_tx_list[first].dc_status = htole32(DC_TXSTAT_OWN); 3292 } 3293 3294 /* 3295 * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data 3296 * pointers to the fragment pointers. 3297 */ 3298 static int 3299 dc_encap(struct dc_softc *sc, struct mbuf **m_head) 3300 { 3301 struct mbuf *m; 3302 int error, idx, chainlen = 0; 3303 3304 /* 3305 * If there's no way we can send any packets, return now. 3306 */ 3307 if (DC_TX_LIST_CNT - sc->dc_cdata.dc_tx_cnt < 6) 3308 return (ENOBUFS); 3309 3310 /* 3311 * Count the number of frags in this chain to see if 3312 * we need to m_defrag. Since the descriptor list is shared 3313 * by all packets, we'll m_defrag long chains so that they 3314 * do not use up the entire list, even if they would fit. 3315 */ 3316 for (m = *m_head; m != NULL; m = m->m_next) 3317 chainlen++; 3318 3319 if ((chainlen > DC_TX_LIST_CNT / 4) || 3320 ((DC_TX_LIST_CNT - (chainlen + sc->dc_cdata.dc_tx_cnt)) < 6)) { 3321 m = m_defrag(*m_head, M_DONTWAIT); 3322 if (m == NULL) 3323 return (ENOBUFS); 3324 *m_head = m; 3325 } 3326 3327 /* 3328 * Start packing the mbufs in this chain into 3329 * the fragment pointers. Stop when we run out 3330 * of fragments or hit the end of the mbuf chain. 3331 */ 3332 idx = sc->dc_cdata.dc_tx_prod; 3333 sc->dc_cdata.dc_tx_mapping = *m_head; 3334 error = bus_dmamap_load_mbuf(sc->dc_mtag, sc->dc_cdata.dc_tx_map[idx], 3335 *m_head, dc_dma_map_txbuf, sc, 0); 3336 if (error) 3337 return (error); 3338 if (sc->dc_cdata.dc_tx_err != 0) 3339 return (sc->dc_cdata.dc_tx_err); 3340 bus_dmamap_sync(sc->dc_mtag, sc->dc_cdata.dc_tx_map[idx], 3341 BUS_DMASYNC_PREWRITE); 3342 bus_dmamap_sync(sc->dc_ltag, sc->dc_lmap, 3343 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3344 return (0); 3345 } 3346 3347 /* 3348 * Main transmit routine. To avoid having to do mbuf copies, we put pointers 3349 * to the mbuf data regions directly in the transmit lists. We also save a 3350 * copy of the pointers since the transmit list fragment pointers are 3351 * physical addresses. 3352 */ 3353 3354 static void 3355 dc_start(struct ifnet *ifp) 3356 { 3357 struct dc_softc *sc; 3358 struct mbuf *m_head = NULL, *m; 3359 int idx; 3360 3361 sc = ifp->if_softc; 3362 3363 DC_LOCK(sc); 3364 3365 if (!sc->dc_link && ifp->if_snd.ifq_len < 10) { 3366 DC_UNLOCK(sc); 3367 return; 3368 } 3369 3370 if (ifp->if_flags & IFF_OACTIVE) { 3371 DC_UNLOCK(sc); 3372 return; 3373 } 3374 3375 idx = sc->dc_cdata.dc_tx_first = sc->dc_cdata.dc_tx_prod; 3376 3377 while (sc->dc_cdata.dc_tx_chain[idx] == NULL) { 3378 IF_DEQUEUE(&ifp->if_snd, m_head); 3379 if (m_head == NULL) 3380 break; 3381 3382 if (sc->dc_flags & DC_TX_COALESCE && 3383 (m_head->m_next != NULL || 3384 sc->dc_flags & DC_TX_ALIGN)) { 3385 m = m_defrag(m_head, M_DONTWAIT); 3386 if (m == NULL) { 3387 IF_PREPEND(&ifp->if_snd, m_head); 3388 ifp->if_flags |= IFF_OACTIVE; 3389 break; 3390 } else { 3391 m_head = m; 3392 } 3393 } 3394 3395 if (dc_encap(sc, &m_head)) { 3396 IF_PREPEND(&ifp->if_snd, m_head); 3397 ifp->if_flags |= IFF_OACTIVE; 3398 break; 3399 } 3400 idx = sc->dc_cdata.dc_tx_prod; 3401 3402 /* 3403 * If there's a BPF listener, bounce a copy of this frame 3404 * to him. 3405 */ 3406 BPF_MTAP(ifp, m_head); 3407 3408 if (sc->dc_flags & DC_TX_ONE) { 3409 ifp->if_flags |= IFF_OACTIVE; 3410 break; 3411 } 3412 } 3413 3414 /* Transmit */ 3415 if (!(sc->dc_flags & DC_TX_POLL)) 3416 CSR_WRITE_4(sc, DC_TXSTART, 0xFFFFFFFF); 3417 3418 /* 3419 * Set a timeout in case the chip goes out to lunch. 3420 */ 3421 ifp->if_timer = 5; 3422 3423 DC_UNLOCK(sc); 3424 } 3425 3426 static void 3427 dc_init(void *xsc) 3428 { 3429 struct dc_softc *sc = xsc; 3430 struct ifnet *ifp = &sc->arpcom.ac_if; 3431 struct mii_data *mii; 3432 3433 DC_LOCK(sc); 3434 3435 mii = device_get_softc(sc->dc_miibus); 3436 3437 /* 3438 * Cancel pending I/O and free all RX/TX buffers. 3439 */ 3440 dc_stop(sc); 3441 dc_reset(sc); 3442 3443 /* 3444 * Set cache alignment and burst length. 3445 */ 3446 if (DC_IS_ASIX(sc) || DC_IS_DAVICOM(sc)) 3447 CSR_WRITE_4(sc, DC_BUSCTL, 0); 3448 else 3449 CSR_WRITE_4(sc, DC_BUSCTL, DC_BUSCTL_MRME | DC_BUSCTL_MRLE); 3450 /* 3451 * Evenly share the bus between receive and transmit process. 3452 */ 3453 if (DC_IS_INTEL(sc)) 3454 DC_SETBIT(sc, DC_BUSCTL, DC_BUSCTL_ARBITRATION); 3455 if (DC_IS_DAVICOM(sc) || DC_IS_INTEL(sc)) { 3456 DC_SETBIT(sc, DC_BUSCTL, DC_BURSTLEN_USECA); 3457 } else { 3458 DC_SETBIT(sc, DC_BUSCTL, DC_BURSTLEN_16LONG); 3459 } 3460 if (sc->dc_flags & DC_TX_POLL) 3461 DC_SETBIT(sc, DC_BUSCTL, DC_TXPOLL_1); 3462 switch(sc->dc_cachesize) { 3463 case 32: 3464 DC_SETBIT(sc, DC_BUSCTL, DC_CACHEALIGN_32LONG); 3465 break; 3466 case 16: 3467 DC_SETBIT(sc, DC_BUSCTL, DC_CACHEALIGN_16LONG); 3468 break; 3469 case 8: 3470 DC_SETBIT(sc, DC_BUSCTL, DC_CACHEALIGN_8LONG); 3471 break; 3472 case 0: 3473 default: 3474 DC_SETBIT(sc, DC_BUSCTL, DC_CACHEALIGN_NONE); 3475 break; 3476 } 3477 3478 if (sc->dc_flags & DC_TX_STORENFWD) 3479 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_STORENFWD); 3480 else { 3481 if (sc->dc_txthresh > DC_TXTHRESH_MAX) { 3482 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_STORENFWD); 3483 } else { 3484 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_STORENFWD); 3485 DC_SETBIT(sc, DC_NETCFG, sc->dc_txthresh); 3486 } 3487 } 3488 3489 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_NO_RXCRC); 3490 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_TX_BACKOFF); 3491 3492 if (DC_IS_MACRONIX(sc) || DC_IS_PNICII(sc)) { 3493 /* 3494 * The app notes for the 98713 and 98715A say that 3495 * in order to have the chips operate properly, a magic 3496 * number must be written to CSR16. Macronix does not 3497 * document the meaning of these bits so there's no way 3498 * to know exactly what they do. The 98713 has a magic 3499 * number all its own; the rest all use a different one. 3500 */ 3501 DC_CLRBIT(sc, DC_MX_MAGICPACKET, 0xFFFF0000); 3502 if (sc->dc_type == DC_TYPE_98713) 3503 DC_SETBIT(sc, DC_MX_MAGICPACKET, DC_MX_MAGIC_98713); 3504 else 3505 DC_SETBIT(sc, DC_MX_MAGICPACKET, DC_MX_MAGIC_98715); 3506 } 3507 3508 if (DC_IS_XIRCOM(sc)) { 3509 /* 3510 * setup General Purpose Port mode and data so the tulip 3511 * can talk to the MII. 3512 */ 3513 CSR_WRITE_4(sc, DC_SIAGP, DC_SIAGP_WRITE_EN | DC_SIAGP_INT1_EN | 3514 DC_SIAGP_MD_GP2_OUTPUT | DC_SIAGP_MD_GP0_OUTPUT); 3515 DELAY(10); 3516 CSR_WRITE_4(sc, DC_SIAGP, DC_SIAGP_INT1_EN | 3517 DC_SIAGP_MD_GP2_OUTPUT | DC_SIAGP_MD_GP0_OUTPUT); 3518 DELAY(10); 3519 } 3520 3521 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_TX_THRESH); 3522 DC_SETBIT(sc, DC_NETCFG, DC_TXTHRESH_MIN); 3523 3524 /* Init circular RX list. */ 3525 if (dc_list_rx_init(sc) == ENOBUFS) { 3526 printf("dc%d: initialization failed: no " 3527 "memory for rx buffers\n", sc->dc_unit); 3528 dc_stop(sc); 3529 DC_UNLOCK(sc); 3530 return; 3531 } 3532 3533 /* 3534 * Init TX descriptors. 3535 */ 3536 dc_list_tx_init(sc); 3537 3538 /* 3539 * Load the address of the RX list. 3540 */ 3541 CSR_WRITE_4(sc, DC_RXADDR, DC_RXDESC(sc, 0)); 3542 CSR_WRITE_4(sc, DC_TXADDR, DC_TXDESC(sc, 0)); 3543 3544 /* 3545 * Enable interrupts. 3546 */ 3547 #ifdef DEVICE_POLLING 3548 /* 3549 * ... but only if we are not polling, and make sure they are off in 3550 * the case of polling. Some cards (e.g. fxp) turn interrupts on 3551 * after a reset. 3552 */ 3553 if (ifp->if_flags & IFF_POLLING) 3554 CSR_WRITE_4(sc, DC_IMR, 0x00000000); 3555 else 3556 #endif 3557 CSR_WRITE_4(sc, DC_IMR, DC_INTRS); 3558 CSR_WRITE_4(sc, DC_ISR, 0xFFFFFFFF); 3559 3560 /* Enable transmitter. */ 3561 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_TX_ON); 3562 3563 /* 3564 * If this is an Intel 21143 and we're not using the 3565 * MII port, program the LED control pins so we get 3566 * link and activity indications. 3567 */ 3568 if (sc->dc_flags & DC_TULIP_LEDS) { 3569 CSR_WRITE_4(sc, DC_WATCHDOG, 3570 DC_WDOG_CTLWREN | DC_WDOG_LINK | DC_WDOG_ACTIVITY); 3571 CSR_WRITE_4(sc, DC_WATCHDOG, 0); 3572 } 3573 3574 /* 3575 * Load the RX/multicast filter. We do this sort of late 3576 * because the filter programming scheme on the 21143 and 3577 * some clones requires DMAing a setup frame via the TX 3578 * engine, and we need the transmitter enabled for that. 3579 */ 3580 dc_setfilt(sc); 3581 3582 /* Enable receiver. */ 3583 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_ON); 3584 CSR_WRITE_4(sc, DC_RXSTART, 0xFFFFFFFF); 3585 3586 mii_mediachg(mii); 3587 dc_setcfg(sc, sc->dc_if_media); 3588 3589 ifp->if_flags |= IFF_RUNNING; 3590 ifp->if_flags &= ~IFF_OACTIVE; 3591 3592 /* Don't start the ticker if this is a homePNA link. */ 3593 if (IFM_SUBTYPE(mii->mii_media.ifm_media) == IFM_HPNA_1) 3594 sc->dc_link = 1; 3595 else { 3596 if (sc->dc_flags & DC_21143_NWAY) 3597 callout_reset(&sc->dc_stat_ch, hz/10, dc_tick, sc); 3598 else 3599 callout_reset(&sc->dc_stat_ch, hz, dc_tick, sc); 3600 } 3601 3602 #ifdef SRM_MEDIA 3603 if(sc->dc_srm_media) { 3604 struct ifreq ifr; 3605 3606 ifr.ifr_media = sc->dc_srm_media; 3607 ifmedia_ioctl(ifp, &ifr, &mii->mii_media, SIOCSIFMEDIA); 3608 sc->dc_srm_media = 0; 3609 } 3610 #endif 3611 DC_UNLOCK(sc); 3612 } 3613 3614 /* 3615 * Set media options. 3616 */ 3617 static int 3618 dc_ifmedia_upd(struct ifnet *ifp) 3619 { 3620 struct dc_softc *sc; 3621 struct mii_data *mii; 3622 struct ifmedia *ifm; 3623 3624 sc = ifp->if_softc; 3625 mii = device_get_softc(sc->dc_miibus); 3626 mii_mediachg(mii); 3627 ifm = &mii->mii_media; 3628 3629 if (DC_IS_DAVICOM(sc) && 3630 IFM_SUBTYPE(ifm->ifm_media) == IFM_HPNA_1) 3631 dc_setcfg(sc, ifm->ifm_media); 3632 else 3633 sc->dc_link = 0; 3634 3635 return (0); 3636 } 3637 3638 /* 3639 * Report current media status. 3640 */ 3641 static void 3642 dc_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 3643 { 3644 struct dc_softc *sc; 3645 struct mii_data *mii; 3646 struct ifmedia *ifm; 3647 3648 sc = ifp->if_softc; 3649 mii = device_get_softc(sc->dc_miibus); 3650 mii_pollstat(mii); 3651 ifm = &mii->mii_media; 3652 if (DC_IS_DAVICOM(sc)) { 3653 if (IFM_SUBTYPE(ifm->ifm_media) == IFM_HPNA_1) { 3654 ifmr->ifm_active = ifm->ifm_media; 3655 ifmr->ifm_status = 0; 3656 return; 3657 } 3658 } 3659 ifmr->ifm_active = mii->mii_media_active; 3660 ifmr->ifm_status = mii->mii_media_status; 3661 } 3662 3663 static int 3664 dc_ioctl(struct ifnet *ifp, u_long command, caddr_t data) 3665 { 3666 struct dc_softc *sc = ifp->if_softc; 3667 struct ifreq *ifr = (struct ifreq *)data; 3668 struct mii_data *mii; 3669 int error = 0; 3670 3671 DC_LOCK(sc); 3672 3673 switch (command) { 3674 case SIOCSIFFLAGS: 3675 if (ifp->if_flags & IFF_UP) { 3676 int need_setfilt = (ifp->if_flags ^ sc->dc_if_flags) & 3677 (IFF_PROMISC | IFF_ALLMULTI); 3678 3679 if (ifp->if_flags & IFF_RUNNING) { 3680 if (need_setfilt) 3681 dc_setfilt(sc); 3682 } else { 3683 sc->dc_txthresh = 0; 3684 dc_init(sc); 3685 } 3686 } else { 3687 if (ifp->if_flags & IFF_RUNNING) 3688 dc_stop(sc); 3689 } 3690 sc->dc_if_flags = ifp->if_flags; 3691 error = 0; 3692 break; 3693 case SIOCADDMULTI: 3694 case SIOCDELMULTI: 3695 dc_setfilt(sc); 3696 error = 0; 3697 break; 3698 case SIOCGIFMEDIA: 3699 case SIOCSIFMEDIA: 3700 mii = device_get_softc(sc->dc_miibus); 3701 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 3702 #ifdef SRM_MEDIA 3703 if (sc->dc_srm_media) 3704 sc->dc_srm_media = 0; 3705 #endif 3706 break; 3707 default: 3708 error = ether_ioctl(ifp, command, data); 3709 break; 3710 } 3711 3712 DC_UNLOCK(sc); 3713 3714 return (error); 3715 } 3716 3717 static void 3718 dc_watchdog(struct ifnet *ifp) 3719 { 3720 struct dc_softc *sc; 3721 3722 sc = ifp->if_softc; 3723 3724 DC_LOCK(sc); 3725 3726 ifp->if_oerrors++; 3727 printf("dc%d: watchdog timeout\n", sc->dc_unit); 3728 3729 dc_stop(sc); 3730 dc_reset(sc); 3731 dc_init(sc); 3732 3733 if (ifp->if_snd.ifq_head != NULL) 3734 dc_start(ifp); 3735 3736 DC_UNLOCK(sc); 3737 } 3738 3739 /* 3740 * Stop the adapter and free any mbufs allocated to the 3741 * RX and TX lists. 3742 */ 3743 static void 3744 dc_stop(struct dc_softc *sc) 3745 { 3746 struct ifnet *ifp; 3747 struct dc_list_data *ld; 3748 struct dc_chain_data *cd; 3749 int i; 3750 u_int32_t ctl; 3751 3752 DC_LOCK(sc); 3753 3754 ifp = &sc->arpcom.ac_if; 3755 ifp->if_timer = 0; 3756 ld = sc->dc_ldata; 3757 cd = &sc->dc_cdata; 3758 3759 callout_stop(&sc->dc_stat_ch); 3760 3761 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 3762 #ifdef DEVICE_POLLING 3763 ether_poll_deregister(ifp); 3764 #endif 3765 3766 DC_CLRBIT(sc, DC_NETCFG, (DC_NETCFG_RX_ON | DC_NETCFG_TX_ON)); 3767 CSR_WRITE_4(sc, DC_IMR, 0x00000000); 3768 CSR_WRITE_4(sc, DC_TXADDR, 0x00000000); 3769 CSR_WRITE_4(sc, DC_RXADDR, 0x00000000); 3770 sc->dc_link = 0; 3771 3772 /* 3773 * Free data in the RX lists. 3774 */ 3775 for (i = 0; i < DC_RX_LIST_CNT; i++) { 3776 if (cd->dc_rx_chain[i] != NULL) { 3777 m_freem(cd->dc_rx_chain[i]); 3778 cd->dc_rx_chain[i] = NULL; 3779 } 3780 } 3781 bzero(&ld->dc_rx_list, sizeof(ld->dc_rx_list)); 3782 3783 /* 3784 * Free the TX list buffers. 3785 */ 3786 for (i = 0; i < DC_TX_LIST_CNT; i++) { 3787 if (cd->dc_tx_chain[i] != NULL) { 3788 ctl = le32toh(ld->dc_tx_list[i].dc_ctl); 3789 if ((ctl & DC_TXCTL_SETUP) || 3790 !(ctl & DC_TXCTL_LASTFRAG)) { 3791 cd->dc_tx_chain[i] = NULL; 3792 continue; 3793 } 3794 bus_dmamap_unload(sc->dc_mtag, cd->dc_tx_map[i]); 3795 m_freem(cd->dc_tx_chain[i]); 3796 cd->dc_tx_chain[i] = NULL; 3797 } 3798 } 3799 bzero(&ld->dc_tx_list, sizeof(ld->dc_tx_list)); 3800 3801 DC_UNLOCK(sc); 3802 } 3803 3804 /* 3805 * Device suspend routine. Stop the interface and save some PCI 3806 * settings in case the BIOS doesn't restore them properly on 3807 * resume. 3808 */ 3809 static int 3810 dc_suspend(device_t dev) 3811 { 3812 struct dc_softc *sc; 3813 int i, s; 3814 3815 s = splimp(); 3816 3817 sc = device_get_softc(dev); 3818 3819 dc_stop(sc); 3820 3821 for (i = 0; i < 5; i++) 3822 sc->saved_maps[i] = pci_read_config(dev, PCIR_BAR(i), 4); 3823 sc->saved_biosaddr = pci_read_config(dev, PCIR_BIOS, 4); 3824 sc->saved_intline = pci_read_config(dev, PCIR_INTLINE, 1); 3825 sc->saved_cachelnsz = pci_read_config(dev, PCIR_CACHELNSZ, 1); 3826 sc->saved_lattimer = pci_read_config(dev, PCIR_LATTIMER, 1); 3827 3828 sc->suspended = 1; 3829 3830 splx(s); 3831 return (0); 3832 } 3833 3834 /* 3835 * Device resume routine. Restore some PCI settings in case the BIOS 3836 * doesn't, re-enable busmastering, and restart the interface if 3837 * appropriate. 3838 */ 3839 static int 3840 dc_resume(device_t dev) 3841 { 3842 struct dc_softc *sc; 3843 struct ifnet *ifp; 3844 int i, s; 3845 3846 s = splimp(); 3847 3848 sc = device_get_softc(dev); 3849 ifp = &sc->arpcom.ac_if; 3850 #ifndef BURN_BRIDGES 3851 dc_acpi(dev); 3852 #endif 3853 /* better way to do this? */ 3854 for (i = 0; i < 5; i++) 3855 pci_write_config(dev, PCIR_BAR(i), sc->saved_maps[i], 4); 3856 pci_write_config(dev, PCIR_BIOS, sc->saved_biosaddr, 4); 3857 pci_write_config(dev, PCIR_INTLINE, sc->saved_intline, 1); 3858 pci_write_config(dev, PCIR_CACHELNSZ, sc->saved_cachelnsz, 1); 3859 pci_write_config(dev, PCIR_LATTIMER, sc->saved_lattimer, 1); 3860 3861 /* reenable busmastering */ 3862 pci_enable_busmaster(dev); 3863 pci_enable_io(dev, DC_RES); 3864 3865 /* reinitialize interface if necessary */ 3866 if (ifp->if_flags & IFF_UP) 3867 dc_init(sc); 3868 3869 sc->suspended = 0; 3870 3871 splx(s); 3872 return (0); 3873 } 3874 3875 /* 3876 * Stop all chip I/O so that the kernel's probe routines don't 3877 * get confused by errant DMAs when rebooting. 3878 */ 3879 static void 3880 dc_shutdown(device_t dev) 3881 { 3882 struct dc_softc *sc; 3883 3884 sc = device_get_softc(dev); 3885 3886 dc_stop(sc); 3887 } 3888