1 /* 2 * Copyright (c) 1997, 1998, 1999 3 * Bill Paul <wpaul@ee.columbia.edu>. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 3. All advertising materials mentioning features or use of this software 14 * must display the following acknowledgement: 15 * This product includes software developed by Bill Paul. 16 * 4. Neither the name of the author nor the names of any co-contributors 17 * may be used to endorse or promote products derived from this software 18 * without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30 * THE POSSIBILITY OF SUCH DAMAGE. 31 * 32 * $FreeBSD$ 33 */ 34 35 /* 36 * DEC "tulip" clone ethernet driver. Supports the DEC/Intel 21143 37 * series chips and several workalikes including the following: 38 * 39 * Macronix 98713/98715/98725/98727/98732 PMAC (www.macronix.com) 40 * Macronix/Lite-On 82c115 PNIC II (www.macronix.com) 41 * Lite-On 82c168/82c169 PNIC (www.litecom.com) 42 * ASIX Electronics AX88140A (www.asix.com.tw) 43 * ASIX Electronics AX88141 (www.asix.com.tw) 44 * ADMtek AL981 (www.admtek.com.tw) 45 * ADMtek AN985 (www.admtek.com.tw) 46 * Davicom DM9100, DM9102, DM9102A (www.davicom8.com) 47 * Accton EN1217 (www.accton.com) 48 * Xircom X3201 (www.xircom.com) 49 * Abocom FE2500 50 * Conexant LANfinity (www.conexant.com) 51 * 52 * Datasheets for the 21143 are available at developer.intel.com. 53 * Datasheets for the clone parts can be found at their respective sites. 54 * (Except for the PNIC; see www.freebsd.org/~wpaul/PNIC/pnic.ps.gz.) 55 * The PNIC II is essentially a Macronix 98715A chip; the only difference 56 * worth noting is that its multicast hash table is only 128 bits wide 57 * instead of 512. 58 * 59 * Written by Bill Paul <wpaul@ee.columbia.edu> 60 * Electrical Engineering Department 61 * Columbia University, New York City 62 */ 63 64 /* 65 * The Intel 21143 is the successor to the DEC 21140. It is basically 66 * the same as the 21140 but with a few new features. The 21143 supports 67 * three kinds of media attachments: 68 * 69 * o MII port, for 10Mbps and 100Mbps support and NWAY 70 * autonegotiation provided by an external PHY. 71 * o SYM port, for symbol mode 100Mbps support. 72 * o 10baseT port. 73 * o AUI/BNC port. 74 * 75 * The 100Mbps SYM port and 10baseT port can be used together in 76 * combination with the internal NWAY support to create a 10/100 77 * autosensing configuration. 78 * 79 * Note that not all tulip workalikes are handled in this driver: we only 80 * deal with those which are relatively well behaved. The Winbond is 81 * handled separately due to its different register offsets and the 82 * special handling needed for its various bugs. The PNIC is handled 83 * here, but I'm not thrilled about it. 84 * 85 * All of the workalike chips use some form of MII transceiver support 86 * with the exception of the Macronix chips, which also have a SYM port. 87 * The ASIX AX88140A is also documented to have a SYM port, but all 88 * the cards I've seen use an MII transceiver, probably because the 89 * AX88140A doesn't support internal NWAY. 90 */ 91 92 #include <sys/param.h> 93 #include <sys/systm.h> 94 #include <sys/sockio.h> 95 #include <sys/mbuf.h> 96 #include <sys/malloc.h> 97 #include <sys/kernel.h> 98 #include <sys/socket.h> 99 #include <sys/sysctl.h> 100 101 #include <net/if.h> 102 #include <net/if_arp.h> 103 #include <net/ethernet.h> 104 #include <net/if_dl.h> 105 #include <net/if_media.h> 106 107 #include <net/bpf.h> 108 109 #include <vm/vm.h> /* for vtophys */ 110 #include <vm/pmap.h> /* for vtophys */ 111 #include <machine/bus_pio.h> 112 #include <machine/bus_memio.h> 113 #include <machine/bus.h> 114 #include <machine/resource.h> 115 #include <sys/bus.h> 116 #include <sys/rman.h> 117 118 #include <dev/mii/mii.h> 119 #include <dev/mii/miivar.h> 120 121 #include <pci/pcireg.h> 122 #include <pci/pcivar.h> 123 124 #define DC_USEIOSPACE 125 #ifdef __alpha__ 126 #define SRM_MEDIA 127 #endif 128 129 #include <pci/if_dcreg.h> 130 131 MODULE_DEPEND(dc, miibus, 1, 1, 1); 132 133 /* "controller miibus0" required. See GENERIC if you get errors here. */ 134 #include "miibus_if.h" 135 136 #ifndef lint 137 static const char rcsid[] = 138 "$FreeBSD$"; 139 #endif 140 141 /* 142 * Various supported device vendors/types and their names. 143 */ 144 static struct dc_type dc_devs[] = { 145 { DC_VENDORID_DEC, DC_DEVICEID_21143, 146 "Intel 21143 10/100BaseTX" }, 147 { DC_VENDORID_DAVICOM, DC_DEVICEID_DM9100, 148 "Davicom DM9100 10/100BaseTX" }, 149 { DC_VENDORID_DAVICOM, DC_DEVICEID_DM9102, 150 "Davicom DM9102 10/100BaseTX" }, 151 { DC_VENDORID_DAVICOM, DC_DEVICEID_DM9102, 152 "Davicom DM9102A 10/100BaseTX" }, 153 { DC_VENDORID_ADMTEK, DC_DEVICEID_AL981, 154 "ADMtek AL981 10/100BaseTX" }, 155 { DC_VENDORID_ADMTEK, DC_DEVICEID_AN985, 156 "ADMtek AN985 10/100BaseTX" }, 157 { DC_VENDORID_ASIX, DC_DEVICEID_AX88140A, 158 "ASIX AX88140A 10/100BaseTX" }, 159 { DC_VENDORID_ASIX, DC_DEVICEID_AX88140A, 160 "ASIX AX88141 10/100BaseTX" }, 161 { DC_VENDORID_MX, DC_DEVICEID_98713, 162 "Macronix 98713 10/100BaseTX" }, 163 { DC_VENDORID_MX, DC_DEVICEID_98713, 164 "Macronix 98713A 10/100BaseTX" }, 165 { DC_VENDORID_CP, DC_DEVICEID_98713_CP, 166 "Compex RL100-TX 10/100BaseTX" }, 167 { DC_VENDORID_CP, DC_DEVICEID_98713_CP, 168 "Compex RL100-TX 10/100BaseTX" }, 169 { DC_VENDORID_MX, DC_DEVICEID_987x5, 170 "Macronix 98715/98715A 10/100BaseTX" }, 171 { DC_VENDORID_MX, DC_DEVICEID_987x5, 172 "Macronix 98715AEC-C 10/100BaseTX" }, 173 { DC_VENDORID_MX, DC_DEVICEID_987x5, 174 "Macronix 98725 10/100BaseTX" }, 175 { DC_VENDORID_MX, DC_DEVICEID_98727, 176 "Macronix 98727/98732 10/100BaseTX" }, 177 { DC_VENDORID_LO, DC_DEVICEID_82C115, 178 "LC82C115 PNIC II 10/100BaseTX" }, 179 { DC_VENDORID_LO, DC_DEVICEID_82C168, 180 "82c168 PNIC 10/100BaseTX" }, 181 { DC_VENDORID_LO, DC_DEVICEID_82C168, 182 "82c169 PNIC 10/100BaseTX" }, 183 { DC_VENDORID_ACCTON, DC_DEVICEID_EN1217, 184 "Accton EN1217 10/100BaseTX" }, 185 { DC_VENDORID_ACCTON, DC_DEVICEID_EN2242, 186 "Accton EN2242 MiniPCI 10/100BaseTX" }, 187 { DC_VENDORID_XIRCOM, DC_DEVICEID_X3201, 188 "Xircom X3201 10/100BaseTX" }, 189 { DC_VENDORID_ABOCOM, DC_DEVICEID_FE2500, 190 "Abocom FE2500 10/100BaseTX" }, 191 { DC_VENDORID_CONEXANT, DC_DEVICEID_RS7112, 192 "Conexant LANfinity MiniPCI 10/100BaseTX" }, 193 { 0, 0, NULL } 194 }; 195 196 static int dc_probe __P((device_t)); 197 static int dc_attach __P((device_t)); 198 static int dc_detach __P((device_t)); 199 static void dc_acpi __P((device_t)); 200 static struct dc_type *dc_devtype __P((device_t)); 201 static int dc_newbuf __P((struct dc_softc *, int, struct mbuf *)); 202 static int dc_encap __P((struct dc_softc *, struct mbuf *, 203 u_int32_t *)); 204 static int dc_coal __P((struct dc_softc *, struct mbuf **)); 205 static void dc_pnic_rx_bug_war __P((struct dc_softc *, int)); 206 static int dc_rx_resync __P((struct dc_softc *)); 207 static void dc_rxeof __P((struct dc_softc *)); 208 static void dc_txeof __P((struct dc_softc *)); 209 static void dc_tick __P((void *)); 210 static void dc_tx_underrun __P((struct dc_softc *)); 211 static void dc_intr __P((void *)); 212 static void dc_start __P((struct ifnet *)); 213 static int dc_ioctl __P((struct ifnet *, u_long, caddr_t)); 214 static void dc_init __P((void *)); 215 static void dc_stop __P((struct dc_softc *)); 216 static void dc_watchdog __P((struct ifnet *)); 217 static void dc_shutdown __P((device_t)); 218 static int dc_ifmedia_upd __P((struct ifnet *)); 219 static void dc_ifmedia_sts __P((struct ifnet *, struct ifmediareq *)); 220 221 static void dc_delay __P((struct dc_softc *)); 222 static void dc_eeprom_idle __P((struct dc_softc *)); 223 static void dc_eeprom_putbyte __P((struct dc_softc *, int)); 224 static void dc_eeprom_getword __P((struct dc_softc *, int, u_int16_t *)); 225 static void dc_eeprom_getword_pnic 226 __P((struct dc_softc *, int, u_int16_t *)); 227 static void dc_eeprom_getword_xircom 228 __P((struct dc_softc *, int, u_int16_t *)); 229 static void dc_read_eeprom __P((struct dc_softc *, caddr_t, int, 230 int, int)); 231 232 static void dc_mii_writebit __P((struct dc_softc *, int)); 233 static int dc_mii_readbit __P((struct dc_softc *)); 234 static void dc_mii_sync __P((struct dc_softc *)); 235 static void dc_mii_send __P((struct dc_softc *, u_int32_t, int)); 236 static int dc_mii_readreg __P((struct dc_softc *, struct dc_mii_frame *)); 237 static int dc_mii_writereg __P((struct dc_softc *, struct dc_mii_frame *)); 238 static int dc_miibus_readreg __P((device_t, int, int)); 239 static int dc_miibus_writereg __P((device_t, int, int, int)); 240 static void dc_miibus_statchg __P((device_t)); 241 static void dc_miibus_mediainit __P((device_t)); 242 243 static void dc_setcfg __P((struct dc_softc *, int)); 244 static u_int32_t dc_crc_le __P((struct dc_softc *, caddr_t)); 245 static u_int32_t dc_crc_be __P((caddr_t)); 246 static void dc_setfilt_21143 __P((struct dc_softc *)); 247 static void dc_setfilt_asix __P((struct dc_softc *)); 248 static void dc_setfilt_admtek __P((struct dc_softc *)); 249 static void dc_setfilt_xircom __P((struct dc_softc *)); 250 251 static void dc_setfilt __P((struct dc_softc *)); 252 253 static void dc_reset __P((struct dc_softc *)); 254 static int dc_list_rx_init __P((struct dc_softc *)); 255 static int dc_list_tx_init __P((struct dc_softc *)); 256 257 static void dc_parse_21143_srom __P((struct dc_softc *)); 258 static void dc_decode_leaf_sia __P((struct dc_softc *, 259 struct dc_eblock_sia *)); 260 static void dc_decode_leaf_mii __P((struct dc_softc *, 261 struct dc_eblock_mii *)); 262 static void dc_decode_leaf_sym __P((struct dc_softc *, 263 struct dc_eblock_sym *)); 264 static void dc_apply_fixup __P((struct dc_softc *, int)); 265 266 #ifdef DC_USEIOSPACE 267 #define DC_RES SYS_RES_IOPORT 268 #define DC_RID DC_PCI_CFBIO 269 #else 270 #define DC_RES SYS_RES_MEMORY 271 #define DC_RID DC_PCI_CFBMA 272 #endif 273 274 static device_method_t dc_methods[] = { 275 /* Device interface */ 276 DEVMETHOD(device_probe, dc_probe), 277 DEVMETHOD(device_attach, dc_attach), 278 DEVMETHOD(device_detach, dc_detach), 279 DEVMETHOD(device_shutdown, dc_shutdown), 280 281 /* bus interface */ 282 DEVMETHOD(bus_print_child, bus_generic_print_child), 283 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 284 285 /* MII interface */ 286 DEVMETHOD(miibus_readreg, dc_miibus_readreg), 287 DEVMETHOD(miibus_writereg, dc_miibus_writereg), 288 DEVMETHOD(miibus_statchg, dc_miibus_statchg), 289 DEVMETHOD(miibus_mediainit, dc_miibus_mediainit), 290 291 { 0, 0 } 292 }; 293 294 static driver_t dc_driver = { 295 "dc", 296 dc_methods, 297 sizeof(struct dc_softc) 298 }; 299 300 static devclass_t dc_devclass; 301 #ifdef __i386__ 302 static int dc_quick=1; 303 SYSCTL_INT(_hw, OID_AUTO, dc_quick, CTLFLAG_RW, 304 &dc_quick,0,"do not mdevget in dc driver"); 305 #endif 306 307 DRIVER_MODULE(if_dc, cardbus, dc_driver, dc_devclass, 0, 0); 308 DRIVER_MODULE(if_dc, pci, dc_driver, dc_devclass, 0, 0); 309 DRIVER_MODULE(miibus, dc, miibus_driver, miibus_devclass, 0, 0); 310 311 #define DC_SETBIT(sc, reg, x) \ 312 CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) | (x)) 313 314 #define DC_CLRBIT(sc, reg, x) \ 315 CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) & ~(x)) 316 317 #define SIO_SET(x) DC_SETBIT(sc, DC_SIO, (x)) 318 #define SIO_CLR(x) DC_CLRBIT(sc, DC_SIO, (x)) 319 320 #define IS_MPSAFE 0 321 322 static void dc_delay(sc) 323 struct dc_softc *sc; 324 { 325 int idx; 326 327 for (idx = (300 / 33) + 1; idx > 0; idx--) 328 CSR_READ_4(sc, DC_BUSCTL); 329 } 330 331 static void dc_eeprom_idle(sc) 332 struct dc_softc *sc; 333 { 334 register int i; 335 336 CSR_WRITE_4(sc, DC_SIO, DC_SIO_EESEL); 337 dc_delay(sc); 338 DC_SETBIT(sc, DC_SIO, DC_SIO_ROMCTL_READ); 339 dc_delay(sc); 340 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); 341 dc_delay(sc); 342 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CS); 343 dc_delay(sc); 344 345 for (i = 0; i < 25; i++) { 346 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); 347 dc_delay(sc); 348 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CLK); 349 dc_delay(sc); 350 } 351 352 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); 353 dc_delay(sc); 354 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CS); 355 dc_delay(sc); 356 CSR_WRITE_4(sc, DC_SIO, 0x00000000); 357 358 return; 359 } 360 361 /* 362 * Send a read command and address to the EEPROM, check for ACK. 363 */ 364 static void dc_eeprom_putbyte(sc, addr) 365 struct dc_softc *sc; 366 int addr; 367 { 368 register int d, i; 369 370 /* 371 * The AN985 has a 93C66 EEPROM on it instead of 372 * a 93C46. It uses a different bit sequence for 373 * specifying the "read" opcode. 374 */ 375 if (DC_IS_CENTAUR(sc) || DC_IS_CONEXANT(sc)) 376 d = addr | (DC_EECMD_READ << 2); 377 else 378 d = addr | DC_EECMD_READ; 379 380 /* 381 * Feed in each bit and strobe the clock. 382 */ 383 for (i = 0x400; i; i >>= 1) { 384 if (d & i) { 385 SIO_SET(DC_SIO_EE_DATAIN); 386 } else { 387 SIO_CLR(DC_SIO_EE_DATAIN); 388 } 389 dc_delay(sc); 390 SIO_SET(DC_SIO_EE_CLK); 391 dc_delay(sc); 392 SIO_CLR(DC_SIO_EE_CLK); 393 dc_delay(sc); 394 } 395 396 return; 397 } 398 399 /* 400 * Read a word of data stored in the EEPROM at address 'addr.' 401 * The PNIC 82c168/82c169 has its own non-standard way to read 402 * the EEPROM. 403 */ 404 static void dc_eeprom_getword_pnic(sc, addr, dest) 405 struct dc_softc *sc; 406 int addr; 407 u_int16_t *dest; 408 { 409 register int i; 410 u_int32_t r; 411 412 CSR_WRITE_4(sc, DC_PN_SIOCTL, DC_PN_EEOPCODE_READ|addr); 413 414 for (i = 0; i < DC_TIMEOUT; i++) { 415 DELAY(1); 416 r = CSR_READ_4(sc, DC_SIO); 417 if (!(r & DC_PN_SIOCTL_BUSY)) { 418 *dest = (u_int16_t)(r & 0xFFFF); 419 return; 420 } 421 } 422 423 return; 424 } 425 426 /* 427 * Read a word of data stored in the EEPROM at address 'addr.' 428 * The Xircom X3201 has its own non-standard way to read 429 * the EEPROM, too. 430 */ 431 static void dc_eeprom_getword_xircom(sc, addr, dest) 432 struct dc_softc *sc; 433 int addr; 434 u_int16_t *dest; 435 { 436 SIO_SET(DC_SIO_ROMSEL | DC_SIO_ROMCTL_READ); 437 438 addr *= 2; 439 CSR_WRITE_4(sc, DC_ROM, addr | 0x160); 440 *dest = (u_int16_t)CSR_READ_4(sc, DC_SIO)&0xff; 441 addr += 1; 442 CSR_WRITE_4(sc, DC_ROM, addr | 0x160); 443 *dest |= ((u_int16_t)CSR_READ_4(sc, DC_SIO)&0xff) << 8; 444 445 SIO_CLR(DC_SIO_ROMSEL | DC_SIO_ROMCTL_READ); 446 return; 447 } 448 449 /* 450 * Read a word of data stored in the EEPROM at address 'addr.' 451 */ 452 static void dc_eeprom_getword(sc, addr, dest) 453 struct dc_softc *sc; 454 int addr; 455 u_int16_t *dest; 456 { 457 register int i; 458 u_int16_t word = 0; 459 460 /* Force EEPROM to idle state. */ 461 dc_eeprom_idle(sc); 462 463 /* Enter EEPROM access mode. */ 464 CSR_WRITE_4(sc, DC_SIO, DC_SIO_EESEL); 465 dc_delay(sc); 466 DC_SETBIT(sc, DC_SIO, DC_SIO_ROMCTL_READ); 467 dc_delay(sc); 468 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); 469 dc_delay(sc); 470 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CS); 471 dc_delay(sc); 472 473 /* 474 * Send address of word we want to read. 475 */ 476 dc_eeprom_putbyte(sc, addr); 477 478 /* 479 * Start reading bits from EEPROM. 480 */ 481 for (i = 0x8000; i; i >>= 1) { 482 SIO_SET(DC_SIO_EE_CLK); 483 dc_delay(sc); 484 if (CSR_READ_4(sc, DC_SIO) & DC_SIO_EE_DATAOUT) 485 word |= i; 486 dc_delay(sc); 487 SIO_CLR(DC_SIO_EE_CLK); 488 dc_delay(sc); 489 } 490 491 /* Turn off EEPROM access mode. */ 492 dc_eeprom_idle(sc); 493 494 *dest = word; 495 496 return; 497 } 498 499 /* 500 * Read a sequence of words from the EEPROM. 501 */ 502 static void dc_read_eeprom(sc, dest, off, cnt, swap) 503 struct dc_softc *sc; 504 caddr_t dest; 505 int off; 506 int cnt; 507 int swap; 508 { 509 int i; 510 u_int16_t word = 0, *ptr; 511 512 for (i = 0; i < cnt; i++) { 513 if (DC_IS_PNIC(sc)) 514 dc_eeprom_getword_pnic(sc, off + i, &word); 515 else if (DC_IS_XIRCOM(sc)) 516 dc_eeprom_getword_xircom(sc, off + i, &word); 517 else 518 dc_eeprom_getword(sc, off + i, &word); 519 ptr = (u_int16_t *)(dest + (i * 2)); 520 if (swap) 521 *ptr = ntohs(word); 522 else 523 *ptr = word; 524 } 525 526 return; 527 } 528 529 /* 530 * The following two routines are taken from the Macronix 98713 531 * Application Notes pp.19-21. 532 */ 533 /* 534 * Write a bit to the MII bus. 535 */ 536 static void dc_mii_writebit(sc, bit) 537 struct dc_softc *sc; 538 int bit; 539 { 540 if (bit) 541 CSR_WRITE_4(sc, DC_SIO, 542 DC_SIO_ROMCTL_WRITE|DC_SIO_MII_DATAOUT); 543 else 544 CSR_WRITE_4(sc, DC_SIO, DC_SIO_ROMCTL_WRITE); 545 546 DC_SETBIT(sc, DC_SIO, DC_SIO_MII_CLK); 547 DC_CLRBIT(sc, DC_SIO, DC_SIO_MII_CLK); 548 549 return; 550 } 551 552 /* 553 * Read a bit from the MII bus. 554 */ 555 static int dc_mii_readbit(sc) 556 struct dc_softc *sc; 557 { 558 CSR_WRITE_4(sc, DC_SIO, DC_SIO_ROMCTL_READ|DC_SIO_MII_DIR); 559 CSR_READ_4(sc, DC_SIO); 560 DC_SETBIT(sc, DC_SIO, DC_SIO_MII_CLK); 561 DC_CLRBIT(sc, DC_SIO, DC_SIO_MII_CLK); 562 if (CSR_READ_4(sc, DC_SIO) & DC_SIO_MII_DATAIN) 563 return(1); 564 565 return(0); 566 } 567 568 /* 569 * Sync the PHYs by setting data bit and strobing the clock 32 times. 570 */ 571 static void dc_mii_sync(sc) 572 struct dc_softc *sc; 573 { 574 register int i; 575 576 CSR_WRITE_4(sc, DC_SIO, DC_SIO_ROMCTL_WRITE); 577 578 for (i = 0; i < 32; i++) 579 dc_mii_writebit(sc, 1); 580 581 return; 582 } 583 584 /* 585 * Clock a series of bits through the MII. 586 */ 587 static void dc_mii_send(sc, bits, cnt) 588 struct dc_softc *sc; 589 u_int32_t bits; 590 int cnt; 591 { 592 int i; 593 594 for (i = (0x1 << (cnt - 1)); i; i >>= 1) 595 dc_mii_writebit(sc, bits & i); 596 } 597 598 /* 599 * Read an PHY register through the MII. 600 */ 601 static int dc_mii_readreg(sc, frame) 602 struct dc_softc *sc; 603 struct dc_mii_frame *frame; 604 605 { 606 int i, ack; 607 608 DC_LOCK(sc); 609 610 /* 611 * Set up frame for RX. 612 */ 613 frame->mii_stdelim = DC_MII_STARTDELIM; 614 frame->mii_opcode = DC_MII_READOP; 615 frame->mii_turnaround = 0; 616 frame->mii_data = 0; 617 618 /* 619 * Sync the PHYs. 620 */ 621 dc_mii_sync(sc); 622 623 /* 624 * Send command/address info. 625 */ 626 dc_mii_send(sc, frame->mii_stdelim, 2); 627 dc_mii_send(sc, frame->mii_opcode, 2); 628 dc_mii_send(sc, frame->mii_phyaddr, 5); 629 dc_mii_send(sc, frame->mii_regaddr, 5); 630 631 #ifdef notdef 632 /* Idle bit */ 633 dc_mii_writebit(sc, 1); 634 dc_mii_writebit(sc, 0); 635 #endif 636 637 /* Check for ack */ 638 ack = dc_mii_readbit(sc); 639 640 /* 641 * Now try reading data bits. If the ack failed, we still 642 * need to clock through 16 cycles to keep the PHY(s) in sync. 643 */ 644 if (ack) { 645 for(i = 0; i < 16; i++) { 646 dc_mii_readbit(sc); 647 } 648 goto fail; 649 } 650 651 for (i = 0x8000; i; i >>= 1) { 652 if (!ack) { 653 if (dc_mii_readbit(sc)) 654 frame->mii_data |= i; 655 } 656 } 657 658 fail: 659 660 dc_mii_writebit(sc, 0); 661 dc_mii_writebit(sc, 0); 662 663 DC_UNLOCK(sc); 664 665 if (ack) 666 return(1); 667 return(0); 668 } 669 670 /* 671 * Write to a PHY register through the MII. 672 */ 673 static int dc_mii_writereg(sc, frame) 674 struct dc_softc *sc; 675 struct dc_mii_frame *frame; 676 677 { 678 DC_LOCK(sc); 679 /* 680 * Set up frame for TX. 681 */ 682 683 frame->mii_stdelim = DC_MII_STARTDELIM; 684 frame->mii_opcode = DC_MII_WRITEOP; 685 frame->mii_turnaround = DC_MII_TURNAROUND; 686 687 /* 688 * Sync the PHYs. 689 */ 690 dc_mii_sync(sc); 691 692 dc_mii_send(sc, frame->mii_stdelim, 2); 693 dc_mii_send(sc, frame->mii_opcode, 2); 694 dc_mii_send(sc, frame->mii_phyaddr, 5); 695 dc_mii_send(sc, frame->mii_regaddr, 5); 696 dc_mii_send(sc, frame->mii_turnaround, 2); 697 dc_mii_send(sc, frame->mii_data, 16); 698 699 /* Idle bit. */ 700 dc_mii_writebit(sc, 0); 701 dc_mii_writebit(sc, 0); 702 703 DC_UNLOCK(sc); 704 705 return(0); 706 } 707 708 static int dc_miibus_readreg(dev, phy, reg) 709 device_t dev; 710 int phy, reg; 711 { 712 struct dc_mii_frame frame; 713 struct dc_softc *sc; 714 int i, rval, phy_reg = 0; 715 716 sc = device_get_softc(dev); 717 bzero((char *)&frame, sizeof(frame)); 718 719 /* 720 * Note: both the AL981 and AN985 have internal PHYs, 721 * however the AL981 provides direct access to the PHY 722 * registers while the AN985 uses a serial MII interface. 723 * The AN985's MII interface is also buggy in that you 724 * can read from any MII address (0 to 31), but only address 1 725 * behaves normally. To deal with both cases, we pretend 726 * that the PHY is at MII address 1. 727 */ 728 if (DC_IS_ADMTEK(sc) && phy != DC_ADMTEK_PHYADDR) 729 return(0); 730 731 /* 732 * Note: the ukphy probes of the RS7112 report a PHY at 733 * MII address 0 (possibly HomePNA?) and 1 (ethernet) 734 * so we only respond to correct one. 735 */ 736 if (DC_IS_CONEXANT(sc) && phy != DC_CONEXANT_PHYADDR) 737 return(0); 738 739 if (sc->dc_pmode != DC_PMODE_MII) { 740 if (phy == (MII_NPHY - 1)) { 741 switch(reg) { 742 case MII_BMSR: 743 /* 744 * Fake something to make the probe 745 * code think there's a PHY here. 746 */ 747 return(BMSR_MEDIAMASK); 748 break; 749 case MII_PHYIDR1: 750 if (DC_IS_PNIC(sc)) 751 return(DC_VENDORID_LO); 752 return(DC_VENDORID_DEC); 753 break; 754 case MII_PHYIDR2: 755 if (DC_IS_PNIC(sc)) 756 return(DC_DEVICEID_82C168); 757 return(DC_DEVICEID_21143); 758 break; 759 default: 760 return(0); 761 break; 762 } 763 } else 764 return(0); 765 } 766 767 if (DC_IS_PNIC(sc)) { 768 CSR_WRITE_4(sc, DC_PN_MII, DC_PN_MIIOPCODE_READ | 769 (phy << 23) | (reg << 18)); 770 for (i = 0; i < DC_TIMEOUT; i++) { 771 DELAY(1); 772 rval = CSR_READ_4(sc, DC_PN_MII); 773 if (!(rval & DC_PN_MII_BUSY)) { 774 rval &= 0xFFFF; 775 return(rval == 0xFFFF ? 0 : rval); 776 } 777 } 778 return(0); 779 } 780 781 if (DC_IS_COMET(sc)) { 782 switch(reg) { 783 case MII_BMCR: 784 phy_reg = DC_AL_BMCR; 785 break; 786 case MII_BMSR: 787 phy_reg = DC_AL_BMSR; 788 break; 789 case MII_PHYIDR1: 790 phy_reg = DC_AL_VENID; 791 break; 792 case MII_PHYIDR2: 793 phy_reg = DC_AL_DEVID; 794 break; 795 case MII_ANAR: 796 phy_reg = DC_AL_ANAR; 797 break; 798 case MII_ANLPAR: 799 phy_reg = DC_AL_LPAR; 800 break; 801 case MII_ANER: 802 phy_reg = DC_AL_ANER; 803 break; 804 default: 805 printf("dc%d: phy_read: bad phy register %x\n", 806 sc->dc_unit, reg); 807 return(0); 808 break; 809 } 810 811 rval = CSR_READ_4(sc, phy_reg) & 0x0000FFFF; 812 813 if (rval == 0xFFFF) 814 return(0); 815 return(rval); 816 } 817 818 frame.mii_phyaddr = phy; 819 frame.mii_regaddr = reg; 820 if (sc->dc_type == DC_TYPE_98713) { 821 phy_reg = CSR_READ_4(sc, DC_NETCFG); 822 CSR_WRITE_4(sc, DC_NETCFG, phy_reg & ~DC_NETCFG_PORTSEL); 823 } 824 dc_mii_readreg(sc, &frame); 825 if (sc->dc_type == DC_TYPE_98713) 826 CSR_WRITE_4(sc, DC_NETCFG, phy_reg); 827 828 return(frame.mii_data); 829 } 830 831 static int dc_miibus_writereg(dev, phy, reg, data) 832 device_t dev; 833 int phy, reg, data; 834 { 835 struct dc_softc *sc; 836 struct dc_mii_frame frame; 837 int i, phy_reg = 0; 838 839 sc = device_get_softc(dev); 840 bzero((char *)&frame, sizeof(frame)); 841 842 if (DC_IS_ADMTEK(sc) && phy != DC_ADMTEK_PHYADDR) 843 return(0); 844 845 if (DC_IS_CONEXANT(sc) && phy != DC_CONEXANT_PHYADDR) 846 return(0); 847 848 if (DC_IS_PNIC(sc)) { 849 CSR_WRITE_4(sc, DC_PN_MII, DC_PN_MIIOPCODE_WRITE | 850 (phy << 23) | (reg << 10) | data); 851 for (i = 0; i < DC_TIMEOUT; i++) { 852 if (!(CSR_READ_4(sc, DC_PN_MII) & DC_PN_MII_BUSY)) 853 break; 854 } 855 return(0); 856 } 857 858 if (DC_IS_COMET(sc)) { 859 switch(reg) { 860 case MII_BMCR: 861 phy_reg = DC_AL_BMCR; 862 break; 863 case MII_BMSR: 864 phy_reg = DC_AL_BMSR; 865 break; 866 case MII_PHYIDR1: 867 phy_reg = DC_AL_VENID; 868 break; 869 case MII_PHYIDR2: 870 phy_reg = DC_AL_DEVID; 871 break; 872 case MII_ANAR: 873 phy_reg = DC_AL_ANAR; 874 break; 875 case MII_ANLPAR: 876 phy_reg = DC_AL_LPAR; 877 break; 878 case MII_ANER: 879 phy_reg = DC_AL_ANER; 880 break; 881 default: 882 printf("dc%d: phy_write: bad phy register %x\n", 883 sc->dc_unit, reg); 884 return(0); 885 break; 886 } 887 888 CSR_WRITE_4(sc, phy_reg, data); 889 return(0); 890 } 891 892 frame.mii_phyaddr = phy; 893 frame.mii_regaddr = reg; 894 frame.mii_data = data; 895 896 if (sc->dc_type == DC_TYPE_98713) { 897 phy_reg = CSR_READ_4(sc, DC_NETCFG); 898 CSR_WRITE_4(sc, DC_NETCFG, phy_reg & ~DC_NETCFG_PORTSEL); 899 } 900 dc_mii_writereg(sc, &frame); 901 if (sc->dc_type == DC_TYPE_98713) 902 CSR_WRITE_4(sc, DC_NETCFG, phy_reg); 903 904 return(0); 905 } 906 907 static void dc_miibus_statchg(dev) 908 device_t dev; 909 { 910 struct dc_softc *sc; 911 struct mii_data *mii; 912 struct ifmedia *ifm; 913 914 sc = device_get_softc(dev); 915 if (DC_IS_ADMTEK(sc)) 916 return; 917 918 mii = device_get_softc(sc->dc_miibus); 919 ifm = &mii->mii_media; 920 if (DC_IS_DAVICOM(sc) && 921 IFM_SUBTYPE(ifm->ifm_media) == IFM_homePNA) { 922 dc_setcfg(sc, ifm->ifm_media); 923 sc->dc_if_media = ifm->ifm_media; 924 } else { 925 dc_setcfg(sc, mii->mii_media_active); 926 sc->dc_if_media = mii->mii_media_active; 927 } 928 929 return; 930 } 931 932 /* 933 * Special support for DM9102A cards with HomePNA PHYs. Note: 934 * with the Davicom DM9102A/DM9801 eval board that I have, it seems 935 * to be impossible to talk to the management interface of the DM9801 936 * PHY (its MDIO pin is not connected to anything). Consequently, 937 * the driver has to just 'know' about the additional mode and deal 938 * with it itself. *sigh* 939 */ 940 static void dc_miibus_mediainit(dev) 941 device_t dev; 942 { 943 struct dc_softc *sc; 944 struct mii_data *mii; 945 struct ifmedia *ifm; 946 int rev; 947 948 rev = pci_read_config(dev, DC_PCI_CFRV, 4) & 0xFF; 949 950 sc = device_get_softc(dev); 951 mii = device_get_softc(sc->dc_miibus); 952 ifm = &mii->mii_media; 953 954 if (DC_IS_DAVICOM(sc) && rev >= DC_REVISION_DM9102A) 955 ifmedia_add(ifm, IFM_ETHER|IFM_homePNA, 0, NULL); 956 957 return; 958 } 959 960 #define DC_POLY 0xEDB88320 961 #define DC_BITS_512 9 962 #define DC_BITS_128 7 963 #define DC_BITS_64 6 964 965 static u_int32_t dc_crc_le(sc, addr) 966 struct dc_softc *sc; 967 caddr_t addr; 968 { 969 u_int32_t idx, bit, data, crc; 970 971 /* Compute CRC for the address value. */ 972 crc = 0xFFFFFFFF; /* initial value */ 973 974 for (idx = 0; idx < 6; idx++) { 975 for (data = *addr++, bit = 0; bit < 8; bit++, data >>= 1) 976 crc = (crc >> 1) ^ (((crc ^ data) & 1) ? DC_POLY : 0); 977 } 978 979 /* 980 * The hash table on the PNIC II and the MX98715AEC-C/D/E 981 * chips is only 128 bits wide. 982 */ 983 if (sc->dc_flags & DC_128BIT_HASH) 984 return (crc & ((1 << DC_BITS_128) - 1)); 985 986 /* The hash table on the MX98715BEC is only 64 bits wide. */ 987 if (sc->dc_flags & DC_64BIT_HASH) 988 return (crc & ((1 << DC_BITS_64) - 1)); 989 990 /* Xircom's hash filtering table is different (read: weird) */ 991 /* Xircom uses the LEAST significant bits */ 992 if (DC_IS_XIRCOM(sc)) { 993 if ((crc & 0x180) == 0x180) 994 return (crc & 0x0F) + (crc & 0x70)*3 + (14 << 4); 995 else 996 return (crc & 0x1F) + ((crc>>1) & 0xF0)*3 + (12 << 4); 997 } 998 999 return (crc & ((1 << DC_BITS_512) - 1)); 1000 } 1001 1002 /* 1003 * Calculate CRC of a multicast group address, return the lower 6 bits. 1004 */ 1005 static u_int32_t dc_crc_be(addr) 1006 caddr_t addr; 1007 { 1008 u_int32_t crc, carry; 1009 int i, j; 1010 u_int8_t c; 1011 1012 /* Compute CRC for the address value. */ 1013 crc = 0xFFFFFFFF; /* initial value */ 1014 1015 for (i = 0; i < 6; i++) { 1016 c = *(addr + i); 1017 for (j = 0; j < 8; j++) { 1018 carry = ((crc & 0x80000000) ? 1 : 0) ^ (c & 0x01); 1019 crc <<= 1; 1020 c >>= 1; 1021 if (carry) 1022 crc = (crc ^ 0x04c11db6) | carry; 1023 } 1024 } 1025 1026 /* return the filter bit position */ 1027 return((crc >> 26) & 0x0000003F); 1028 } 1029 1030 /* 1031 * 21143-style RX filter setup routine. Filter programming is done by 1032 * downloading a special setup frame into the TX engine. 21143, Macronix, 1033 * PNIC, PNIC II and Davicom chips are programmed this way. 1034 * 1035 * We always program the chip using 'hash perfect' mode, i.e. one perfect 1036 * address (our node address) and a 512-bit hash filter for multicast 1037 * frames. We also sneak the broadcast address into the hash filter since 1038 * we need that too. 1039 */ 1040 void dc_setfilt_21143(sc) 1041 struct dc_softc *sc; 1042 { 1043 struct dc_desc *sframe; 1044 u_int32_t h, *sp; 1045 struct ifmultiaddr *ifma; 1046 struct ifnet *ifp; 1047 int i; 1048 1049 ifp = &sc->arpcom.ac_if; 1050 1051 i = sc->dc_cdata.dc_tx_prod; 1052 DC_INC(sc->dc_cdata.dc_tx_prod, DC_TX_LIST_CNT); 1053 sc->dc_cdata.dc_tx_cnt++; 1054 sframe = &sc->dc_ldata->dc_tx_list[i]; 1055 sp = (u_int32_t *)&sc->dc_cdata.dc_sbuf; 1056 bzero((char *)sp, DC_SFRAME_LEN); 1057 1058 sframe->dc_data = vtophys(&sc->dc_cdata.dc_sbuf); 1059 sframe->dc_ctl = DC_SFRAME_LEN | DC_TXCTL_SETUP | DC_TXCTL_TLINK | 1060 DC_FILTER_HASHPERF | DC_TXCTL_FINT; 1061 1062 sc->dc_cdata.dc_tx_chain[i] = (struct mbuf *)&sc->dc_cdata.dc_sbuf; 1063 1064 /* If we want promiscuous mode, set the allframes bit. */ 1065 if (ifp->if_flags & IFF_PROMISC) 1066 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC); 1067 else 1068 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC); 1069 1070 if (ifp->if_flags & IFF_ALLMULTI) 1071 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI); 1072 else 1073 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI); 1074 1075 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 1076 if (ifma->ifma_addr->sa_family != AF_LINK) 1077 continue; 1078 h = dc_crc_le(sc, 1079 LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 1080 sp[h >> 4] |= 1 << (h & 0xF); 1081 } 1082 1083 if (ifp->if_flags & IFF_BROADCAST) { 1084 h = dc_crc_le(sc, (caddr_t)ðerbroadcastaddr); 1085 sp[h >> 4] |= 1 << (h & 0xF); 1086 } 1087 1088 /* Set our MAC address */ 1089 sp[39] = ((u_int16_t *)sc->arpcom.ac_enaddr)[0]; 1090 sp[40] = ((u_int16_t *)sc->arpcom.ac_enaddr)[1]; 1091 sp[41] = ((u_int16_t *)sc->arpcom.ac_enaddr)[2]; 1092 1093 sframe->dc_status = DC_TXSTAT_OWN; 1094 CSR_WRITE_4(sc, DC_TXSTART, 0xFFFFFFFF); 1095 1096 /* 1097 * The PNIC takes an exceedingly long time to process its 1098 * setup frame; wait 10ms after posting the setup frame 1099 * before proceeding, just so it has time to swallow its 1100 * medicine. 1101 */ 1102 DELAY(10000); 1103 1104 ifp->if_timer = 5; 1105 1106 return; 1107 } 1108 1109 void dc_setfilt_admtek(sc) 1110 struct dc_softc *sc; 1111 { 1112 struct ifnet *ifp; 1113 int h = 0; 1114 u_int32_t hashes[2] = { 0, 0 }; 1115 struct ifmultiaddr *ifma; 1116 1117 ifp = &sc->arpcom.ac_if; 1118 1119 /* Init our MAC address */ 1120 CSR_WRITE_4(sc, DC_AL_PAR0, *(u_int32_t *)(&sc->arpcom.ac_enaddr[0])); 1121 CSR_WRITE_4(sc, DC_AL_PAR1, *(u_int32_t *)(&sc->arpcom.ac_enaddr[4])); 1122 1123 /* If we want promiscuous mode, set the allframes bit. */ 1124 if (ifp->if_flags & IFF_PROMISC) 1125 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC); 1126 else 1127 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC); 1128 1129 if (ifp->if_flags & IFF_ALLMULTI) 1130 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI); 1131 else 1132 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI); 1133 1134 /* first, zot all the existing hash bits */ 1135 CSR_WRITE_4(sc, DC_AL_MAR0, 0); 1136 CSR_WRITE_4(sc, DC_AL_MAR1, 0); 1137 1138 /* 1139 * If we're already in promisc or allmulti mode, we 1140 * don't have to bother programming the multicast filter. 1141 */ 1142 if (ifp->if_flags & (IFF_PROMISC|IFF_ALLMULTI)) 1143 return; 1144 1145 /* now program new ones */ 1146 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 1147 if (ifma->ifma_addr->sa_family != AF_LINK) 1148 continue; 1149 h = dc_crc_be(LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 1150 if (h < 32) 1151 hashes[0] |= (1 << h); 1152 else 1153 hashes[1] |= (1 << (h - 32)); 1154 } 1155 1156 CSR_WRITE_4(sc, DC_AL_MAR0, hashes[0]); 1157 CSR_WRITE_4(sc, DC_AL_MAR1, hashes[1]); 1158 1159 return; 1160 } 1161 1162 void dc_setfilt_asix(sc) 1163 struct dc_softc *sc; 1164 { 1165 struct ifnet *ifp; 1166 int h = 0; 1167 u_int32_t hashes[2] = { 0, 0 }; 1168 struct ifmultiaddr *ifma; 1169 1170 ifp = &sc->arpcom.ac_if; 1171 1172 /* Init our MAC address */ 1173 CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_PAR0); 1174 CSR_WRITE_4(sc, DC_AX_FILTDATA, 1175 *(u_int32_t *)(&sc->arpcom.ac_enaddr[0])); 1176 CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_PAR1); 1177 CSR_WRITE_4(sc, DC_AX_FILTDATA, 1178 *(u_int32_t *)(&sc->arpcom.ac_enaddr[4])); 1179 1180 /* If we want promiscuous mode, set the allframes bit. */ 1181 if (ifp->if_flags & IFF_PROMISC) 1182 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC); 1183 else 1184 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC); 1185 1186 if (ifp->if_flags & IFF_ALLMULTI) 1187 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI); 1188 else 1189 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI); 1190 1191 /* 1192 * The ASIX chip has a special bit to enable reception 1193 * of broadcast frames. 1194 */ 1195 if (ifp->if_flags & IFF_BROADCAST) 1196 DC_SETBIT(sc, DC_NETCFG, DC_AX_NETCFG_RX_BROAD); 1197 else 1198 DC_CLRBIT(sc, DC_NETCFG, DC_AX_NETCFG_RX_BROAD); 1199 1200 /* first, zot all the existing hash bits */ 1201 CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_MAR0); 1202 CSR_WRITE_4(sc, DC_AX_FILTDATA, 0); 1203 CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_MAR1); 1204 CSR_WRITE_4(sc, DC_AX_FILTDATA, 0); 1205 1206 /* 1207 * If we're already in promisc or allmulti mode, we 1208 * don't have to bother programming the multicast filter. 1209 */ 1210 if (ifp->if_flags & (IFF_PROMISC|IFF_ALLMULTI)) 1211 return; 1212 1213 /* now program new ones */ 1214 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 1215 if (ifma->ifma_addr->sa_family != AF_LINK) 1216 continue; 1217 h = dc_crc_be(LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 1218 if (h < 32) 1219 hashes[0] |= (1 << h); 1220 else 1221 hashes[1] |= (1 << (h - 32)); 1222 } 1223 1224 CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_MAR0); 1225 CSR_WRITE_4(sc, DC_AX_FILTDATA, hashes[0]); 1226 CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_MAR1); 1227 CSR_WRITE_4(sc, DC_AX_FILTDATA, hashes[1]); 1228 1229 return; 1230 } 1231 1232 void dc_setfilt_xircom(sc) 1233 struct dc_softc *sc; 1234 { 1235 struct dc_desc *sframe; 1236 u_int32_t h, *sp; 1237 struct ifmultiaddr *ifma; 1238 struct ifnet *ifp; 1239 int i; 1240 1241 ifp = &sc->arpcom.ac_if; 1242 DC_CLRBIT(sc, DC_NETCFG, (DC_NETCFG_TX_ON|DC_NETCFG_RX_ON)); 1243 1244 i = sc->dc_cdata.dc_tx_prod; 1245 DC_INC(sc->dc_cdata.dc_tx_prod, DC_TX_LIST_CNT); 1246 sc->dc_cdata.dc_tx_cnt++; 1247 sframe = &sc->dc_ldata->dc_tx_list[i]; 1248 sp = (u_int32_t *)&sc->dc_cdata.dc_sbuf; 1249 bzero((char *)sp, DC_SFRAME_LEN); 1250 1251 sframe->dc_data = vtophys(&sc->dc_cdata.dc_sbuf); 1252 sframe->dc_ctl = DC_SFRAME_LEN | DC_TXCTL_SETUP | DC_TXCTL_TLINK | 1253 DC_FILTER_HASHPERF | DC_TXCTL_FINT; 1254 1255 sc->dc_cdata.dc_tx_chain[i] = (struct mbuf *)&sc->dc_cdata.dc_sbuf; 1256 1257 /* If we want promiscuous mode, set the allframes bit. */ 1258 if (ifp->if_flags & IFF_PROMISC) 1259 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC); 1260 else 1261 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC); 1262 1263 if (ifp->if_flags & IFF_ALLMULTI) 1264 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI); 1265 else 1266 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI); 1267 1268 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 1269 if (ifma->ifma_addr->sa_family != AF_LINK) 1270 continue; 1271 h = dc_crc_le(sc, 1272 LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 1273 sp[h >> 4] |= 1 << (h & 0xF); 1274 } 1275 1276 if (ifp->if_flags & IFF_BROADCAST) { 1277 h = dc_crc_le(sc, (caddr_t)ðerbroadcastaddr); 1278 sp[h >> 4] |= 1 << (h & 0xF); 1279 } 1280 1281 /* Set our MAC address */ 1282 sp[0] = ((u_int16_t *)sc->arpcom.ac_enaddr)[0]; 1283 sp[1] = ((u_int16_t *)sc->arpcom.ac_enaddr)[1]; 1284 sp[2] = ((u_int16_t *)sc->arpcom.ac_enaddr)[2]; 1285 1286 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_TX_ON); 1287 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_ON); 1288 ifp->if_flags |= IFF_RUNNING; 1289 sframe->dc_status = DC_TXSTAT_OWN; 1290 CSR_WRITE_4(sc, DC_TXSTART, 0xFFFFFFFF); 1291 1292 /* 1293 * wait some time... 1294 */ 1295 DELAY(1000); 1296 1297 ifp->if_timer = 5; 1298 1299 return; 1300 } 1301 1302 static void dc_setfilt(sc) 1303 struct dc_softc *sc; 1304 { 1305 if (DC_IS_INTEL(sc) || DC_IS_MACRONIX(sc) || DC_IS_PNIC(sc) || 1306 DC_IS_PNICII(sc) || DC_IS_DAVICOM(sc) || DC_IS_CONEXANT(sc)) 1307 dc_setfilt_21143(sc); 1308 1309 if (DC_IS_ASIX(sc)) 1310 dc_setfilt_asix(sc); 1311 1312 if (DC_IS_ADMTEK(sc)) 1313 dc_setfilt_admtek(sc); 1314 1315 if (DC_IS_XIRCOM(sc)) 1316 dc_setfilt_xircom(sc); 1317 1318 return; 1319 } 1320 1321 /* 1322 * In order to fiddle with the 1323 * 'full-duplex' and '100Mbps' bits in the netconfig register, we 1324 * first have to put the transmit and/or receive logic in the idle state. 1325 */ 1326 static void dc_setcfg(sc, media) 1327 struct dc_softc *sc; 1328 int media; 1329 { 1330 int i, restart = 0; 1331 u_int32_t isr; 1332 1333 if (IFM_SUBTYPE(media) == IFM_NONE) 1334 return; 1335 1336 if (CSR_READ_4(sc, DC_NETCFG) & (DC_NETCFG_TX_ON|DC_NETCFG_RX_ON)) { 1337 restart = 1; 1338 DC_CLRBIT(sc, DC_NETCFG, (DC_NETCFG_TX_ON|DC_NETCFG_RX_ON)); 1339 1340 for (i = 0; i < DC_TIMEOUT; i++) { 1341 isr = CSR_READ_4(sc, DC_ISR); 1342 if (isr & DC_ISR_TX_IDLE && 1343 (isr & DC_ISR_RX_STATE) == DC_RXSTATE_STOPPED) 1344 break; 1345 DELAY(10); 1346 } 1347 1348 if (i == DC_TIMEOUT) 1349 printf("dc%d: failed to force tx and " 1350 "rx to idle state\n", sc->dc_unit); 1351 } 1352 1353 if (IFM_SUBTYPE(media) == IFM_100_TX) { 1354 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_SPEEDSEL); 1355 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_HEARTBEAT); 1356 if (sc->dc_pmode == DC_PMODE_MII) { 1357 int watchdogreg; 1358 1359 if (DC_IS_INTEL(sc)) { 1360 /* there's a write enable bit here that reads as 1 */ 1361 watchdogreg = CSR_READ_4(sc, DC_WATCHDOG); 1362 watchdogreg &= ~DC_WDOG_CTLWREN; 1363 watchdogreg |= DC_WDOG_JABBERDIS; 1364 CSR_WRITE_4(sc, DC_WATCHDOG, watchdogreg); 1365 } else { 1366 DC_SETBIT(sc, DC_WATCHDOG, DC_WDOG_JABBERDIS); 1367 } 1368 DC_CLRBIT(sc, DC_NETCFG, (DC_NETCFG_PCS| 1369 DC_NETCFG_PORTSEL|DC_NETCFG_SCRAMBLER)); 1370 if (sc->dc_type == DC_TYPE_98713) 1371 DC_SETBIT(sc, DC_NETCFG, (DC_NETCFG_PCS| 1372 DC_NETCFG_SCRAMBLER)); 1373 if (!DC_IS_DAVICOM(sc)) 1374 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL); 1375 DC_CLRBIT(sc, DC_10BTCTRL, 0xFFFF); 1376 if (DC_IS_INTEL(sc)) 1377 dc_apply_fixup(sc, IFM_AUTO); 1378 } else { 1379 if (DC_IS_PNIC(sc)) { 1380 DC_PN_GPIO_SETBIT(sc, DC_PN_GPIO_SPEEDSEL); 1381 DC_PN_GPIO_SETBIT(sc, DC_PN_GPIO_100TX_LOOP); 1382 DC_SETBIT(sc, DC_PN_NWAY, DC_PN_NWAY_SPEEDSEL); 1383 } 1384 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL); 1385 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PCS); 1386 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_SCRAMBLER); 1387 if (DC_IS_INTEL(sc)) 1388 dc_apply_fixup(sc, 1389 (media & IFM_GMASK) == IFM_FDX ? 1390 IFM_100_TX|IFM_FDX : IFM_100_TX); 1391 } 1392 } 1393 1394 if (IFM_SUBTYPE(media) == IFM_10_T) { 1395 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_SPEEDSEL); 1396 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_HEARTBEAT); 1397 if (sc->dc_pmode == DC_PMODE_MII) { 1398 int watchdogreg; 1399 1400 /* there's a write enable bit here that reads as 1 */ 1401 if (DC_IS_INTEL(sc)) { 1402 watchdogreg = CSR_READ_4(sc, DC_WATCHDOG); 1403 watchdogreg &= ~DC_WDOG_CTLWREN; 1404 watchdogreg |= DC_WDOG_JABBERDIS; 1405 CSR_WRITE_4(sc, DC_WATCHDOG, watchdogreg); 1406 } else { 1407 DC_SETBIT(sc, DC_WATCHDOG, DC_WDOG_JABBERDIS); 1408 } 1409 DC_CLRBIT(sc, DC_NETCFG, (DC_NETCFG_PCS| 1410 DC_NETCFG_PORTSEL|DC_NETCFG_SCRAMBLER)); 1411 if (sc->dc_type == DC_TYPE_98713) 1412 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PCS); 1413 if (!DC_IS_DAVICOM(sc)) 1414 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL); 1415 DC_CLRBIT(sc, DC_10BTCTRL, 0xFFFF); 1416 if (DC_IS_INTEL(sc)) 1417 dc_apply_fixup(sc, IFM_AUTO); 1418 } else { 1419 if (DC_IS_PNIC(sc)) { 1420 DC_PN_GPIO_CLRBIT(sc, DC_PN_GPIO_SPEEDSEL); 1421 DC_PN_GPIO_SETBIT(sc, DC_PN_GPIO_100TX_LOOP); 1422 DC_CLRBIT(sc, DC_PN_NWAY, DC_PN_NWAY_SPEEDSEL); 1423 } 1424 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL); 1425 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_PCS); 1426 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_SCRAMBLER); 1427 if (DC_IS_INTEL(sc)) { 1428 DC_CLRBIT(sc, DC_SIARESET, DC_SIA_RESET); 1429 DC_CLRBIT(sc, DC_10BTCTRL, 0xFFFF); 1430 if ((media & IFM_GMASK) == IFM_FDX) 1431 DC_SETBIT(sc, DC_10BTCTRL, 0x7F3D); 1432 else 1433 DC_SETBIT(sc, DC_10BTCTRL, 0x7F3F); 1434 DC_SETBIT(sc, DC_SIARESET, DC_SIA_RESET); 1435 DC_CLRBIT(sc, DC_10BTCTRL, 1436 DC_TCTL_AUTONEGENBL); 1437 dc_apply_fixup(sc, 1438 (media & IFM_GMASK) == IFM_FDX ? 1439 IFM_10_T|IFM_FDX : IFM_10_T); 1440 DELAY(20000); 1441 } 1442 } 1443 } 1444 1445 /* 1446 * If this is a Davicom DM9102A card with a DM9801 HomePNA 1447 * PHY and we want HomePNA mode, set the portsel bit to turn 1448 * on the external MII port. 1449 */ 1450 if (DC_IS_DAVICOM(sc)) { 1451 if (IFM_SUBTYPE(media) == IFM_homePNA) { 1452 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL); 1453 sc->dc_link = 1; 1454 } else { 1455 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL); 1456 } 1457 } 1458 1459 if ((media & IFM_GMASK) == IFM_FDX) { 1460 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_FULLDUPLEX); 1461 if (sc->dc_pmode == DC_PMODE_SYM && DC_IS_PNIC(sc)) 1462 DC_SETBIT(sc, DC_PN_NWAY, DC_PN_NWAY_DUPLEX); 1463 } else { 1464 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_FULLDUPLEX); 1465 if (sc->dc_pmode == DC_PMODE_SYM && DC_IS_PNIC(sc)) 1466 DC_CLRBIT(sc, DC_PN_NWAY, DC_PN_NWAY_DUPLEX); 1467 } 1468 1469 if (restart) 1470 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_TX_ON|DC_NETCFG_RX_ON); 1471 1472 return; 1473 } 1474 1475 static void dc_reset(sc) 1476 struct dc_softc *sc; 1477 { 1478 register int i; 1479 1480 DC_SETBIT(sc, DC_BUSCTL, DC_BUSCTL_RESET); 1481 1482 for (i = 0; i < DC_TIMEOUT; i++) { 1483 DELAY(10); 1484 if (!(CSR_READ_4(sc, DC_BUSCTL) & DC_BUSCTL_RESET)) 1485 break; 1486 } 1487 1488 if (DC_IS_ASIX(sc) || DC_IS_ADMTEK(sc) || DC_IS_CONEXANT(sc) || 1489 DC_IS_XIRCOM(sc) || DC_IS_INTEL(sc)) { 1490 DELAY(10000); 1491 DC_CLRBIT(sc, DC_BUSCTL, DC_BUSCTL_RESET); 1492 i = 0; 1493 } 1494 1495 if (i == DC_TIMEOUT) 1496 printf("dc%d: reset never completed!\n", sc->dc_unit); 1497 1498 /* Wait a little while for the chip to get its brains in order. */ 1499 DELAY(1000); 1500 1501 CSR_WRITE_4(sc, DC_IMR, 0x00000000); 1502 CSR_WRITE_4(sc, DC_BUSCTL, 0x00000000); 1503 CSR_WRITE_4(sc, DC_NETCFG, 0x00000000); 1504 1505 /* 1506 * Bring the SIA out of reset. In some cases, it looks 1507 * like failing to unreset the SIA soon enough gets it 1508 * into a state where it will never come out of reset 1509 * until we reset the whole chip again. 1510 */ 1511 if (DC_IS_INTEL(sc)) { 1512 DC_SETBIT(sc, DC_SIARESET, DC_SIA_RESET); 1513 CSR_WRITE_4(sc, DC_10BTCTRL, 0); 1514 CSR_WRITE_4(sc, DC_WATCHDOG, 0); 1515 } 1516 1517 return; 1518 } 1519 1520 static struct dc_type *dc_devtype(dev) 1521 device_t dev; 1522 { 1523 struct dc_type *t; 1524 u_int32_t rev; 1525 1526 t = dc_devs; 1527 1528 while(t->dc_name != NULL) { 1529 if ((pci_get_vendor(dev) == t->dc_vid) && 1530 (pci_get_device(dev) == t->dc_did)) { 1531 /* Check the PCI revision */ 1532 rev = pci_read_config(dev, DC_PCI_CFRV, 4) & 0xFF; 1533 if (t->dc_did == DC_DEVICEID_98713 && 1534 rev >= DC_REVISION_98713A) 1535 t++; 1536 if (t->dc_did == DC_DEVICEID_98713_CP && 1537 rev >= DC_REVISION_98713A) 1538 t++; 1539 if (t->dc_did == DC_DEVICEID_987x5 && 1540 rev >= DC_REVISION_98715AEC_C) 1541 t++; 1542 if (t->dc_did == DC_DEVICEID_987x5 && 1543 rev >= DC_REVISION_98725) 1544 t++; 1545 if (t->dc_did == DC_DEVICEID_AX88140A && 1546 rev >= DC_REVISION_88141) 1547 t++; 1548 if (t->dc_did == DC_DEVICEID_82C168 && 1549 rev >= DC_REVISION_82C169) 1550 t++; 1551 if (t->dc_did == DC_DEVICEID_DM9102 && 1552 rev >= DC_REVISION_DM9102A) 1553 t++; 1554 return(t); 1555 } 1556 t++; 1557 } 1558 1559 return(NULL); 1560 } 1561 1562 /* 1563 * Probe for a 21143 or clone chip. Check the PCI vendor and device 1564 * IDs against our list and return a device name if we find a match. 1565 * We do a little bit of extra work to identify the exact type of 1566 * chip. The MX98713 and MX98713A have the same PCI vendor/device ID, 1567 * but different revision IDs. The same is true for 98715/98715A 1568 * chips and the 98725, as well as the ASIX and ADMtek chips. In some 1569 * cases, the exact chip revision affects driver behavior. 1570 */ 1571 static int dc_probe(dev) 1572 device_t dev; 1573 { 1574 struct dc_type *t; 1575 1576 t = dc_devtype(dev); 1577 1578 if (t != NULL) { 1579 device_set_desc(dev, t->dc_name); 1580 return(0); 1581 } 1582 1583 return(ENXIO); 1584 } 1585 1586 static void dc_acpi(dev) 1587 device_t dev; 1588 { 1589 int unit; 1590 1591 unit = device_get_unit(dev); 1592 1593 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) { 1594 u_int32_t iobase, membase, irq; 1595 1596 /* Save important PCI config data. */ 1597 iobase = pci_read_config(dev, DC_PCI_CFBIO, 4); 1598 membase = pci_read_config(dev, DC_PCI_CFBMA, 4); 1599 irq = pci_read_config(dev, DC_PCI_CFIT, 4); 1600 1601 /* Reset the power state. */ 1602 printf("dc%d: chip is in D%d power mode " 1603 "-- setting to D0\n", unit, 1604 pci_get_powerstate(dev)); 1605 pci_set_powerstate(dev, PCI_POWERSTATE_D0); 1606 1607 /* Restore PCI config data. */ 1608 pci_write_config(dev, DC_PCI_CFBIO, iobase, 4); 1609 pci_write_config(dev, DC_PCI_CFBMA, membase, 4); 1610 pci_write_config(dev, DC_PCI_CFIT, irq, 4); 1611 } 1612 1613 return; 1614 } 1615 1616 static void dc_apply_fixup(sc, media) 1617 struct dc_softc *sc; 1618 int media; 1619 { 1620 struct dc_mediainfo *m; 1621 u_int8_t *p; 1622 int i; 1623 u_int32_t reg; 1624 1625 m = sc->dc_mi; 1626 1627 while (m != NULL) { 1628 if (m->dc_media == media) 1629 break; 1630 m = m->dc_next; 1631 } 1632 1633 if (m == NULL) 1634 return; 1635 1636 for (i = 0, p = m->dc_reset_ptr; i < m->dc_reset_len; i++, p += 2) { 1637 reg = (p[0] | (p[1] << 8)) << 16; 1638 CSR_WRITE_4(sc, DC_WATCHDOG, reg); 1639 } 1640 1641 for (i = 0, p = m->dc_gp_ptr; i < m->dc_gp_len; i++, p += 2) { 1642 reg = (p[0] | (p[1] << 8)) << 16; 1643 CSR_WRITE_4(sc, DC_WATCHDOG, reg); 1644 } 1645 1646 return; 1647 } 1648 1649 static void dc_decode_leaf_sia(sc, l) 1650 struct dc_softc *sc; 1651 struct dc_eblock_sia *l; 1652 { 1653 struct dc_mediainfo *m; 1654 1655 m = malloc(sizeof(struct dc_mediainfo), M_DEVBUF, M_NOWAIT); 1656 bzero(m, sizeof(struct dc_mediainfo)); 1657 if (l->dc_sia_code == DC_SIA_CODE_10BT) 1658 m->dc_media = IFM_10_T; 1659 1660 if (l->dc_sia_code == DC_SIA_CODE_10BT_FDX) 1661 m->dc_media = IFM_10_T|IFM_FDX; 1662 1663 if (l->dc_sia_code == DC_SIA_CODE_10B2) 1664 m->dc_media = IFM_10_2; 1665 1666 if (l->dc_sia_code == DC_SIA_CODE_10B5) 1667 m->dc_media = IFM_10_5; 1668 1669 m->dc_gp_len = 2; 1670 m->dc_gp_ptr = (u_int8_t *)&l->dc_sia_gpio_ctl; 1671 1672 m->dc_next = sc->dc_mi; 1673 sc->dc_mi = m; 1674 1675 sc->dc_pmode = DC_PMODE_SIA; 1676 1677 return; 1678 } 1679 1680 static void dc_decode_leaf_sym(sc, l) 1681 struct dc_softc *sc; 1682 struct dc_eblock_sym *l; 1683 { 1684 struct dc_mediainfo *m; 1685 1686 m = malloc(sizeof(struct dc_mediainfo), M_DEVBUF, M_NOWAIT); 1687 bzero(m, sizeof(struct dc_mediainfo)); 1688 if (l->dc_sym_code == DC_SYM_CODE_100BT) 1689 m->dc_media = IFM_100_TX; 1690 1691 if (l->dc_sym_code == DC_SYM_CODE_100BT_FDX) 1692 m->dc_media = IFM_100_TX|IFM_FDX; 1693 1694 m->dc_gp_len = 2; 1695 m->dc_gp_ptr = (u_int8_t *)&l->dc_sym_gpio_ctl; 1696 1697 m->dc_next = sc->dc_mi; 1698 sc->dc_mi = m; 1699 1700 sc->dc_pmode = DC_PMODE_SYM; 1701 1702 return; 1703 } 1704 1705 static void dc_decode_leaf_mii(sc, l) 1706 struct dc_softc *sc; 1707 struct dc_eblock_mii *l; 1708 { 1709 u_int8_t *p; 1710 struct dc_mediainfo *m; 1711 1712 m = malloc(sizeof(struct dc_mediainfo), M_DEVBUF, M_NOWAIT); 1713 bzero(m, sizeof(struct dc_mediainfo)); 1714 /* We abuse IFM_AUTO to represent MII. */ 1715 m->dc_media = IFM_AUTO; 1716 m->dc_gp_len = l->dc_gpr_len; 1717 1718 p = (u_int8_t *)l; 1719 p += sizeof(struct dc_eblock_mii); 1720 m->dc_gp_ptr = p; 1721 p += 2 * l->dc_gpr_len; 1722 m->dc_reset_len = *p; 1723 p++; 1724 m->dc_reset_ptr = p; 1725 1726 m->dc_next = sc->dc_mi; 1727 sc->dc_mi = m; 1728 1729 return; 1730 } 1731 1732 static void dc_parse_21143_srom(sc) 1733 struct dc_softc *sc; 1734 { 1735 struct dc_leaf_hdr *lhdr; 1736 struct dc_eblock_hdr *hdr; 1737 int i, loff; 1738 char *ptr; 1739 1740 loff = sc->dc_srom[27]; 1741 lhdr = (struct dc_leaf_hdr *)&(sc->dc_srom[loff]); 1742 1743 ptr = (char *)lhdr; 1744 ptr += sizeof(struct dc_leaf_hdr) - 1; 1745 for (i = 0; i < lhdr->dc_mcnt; i++) { 1746 hdr = (struct dc_eblock_hdr *)ptr; 1747 switch(hdr->dc_type) { 1748 case DC_EBLOCK_MII: 1749 dc_decode_leaf_mii(sc, (struct dc_eblock_mii *)hdr); 1750 break; 1751 case DC_EBLOCK_SIA: 1752 dc_decode_leaf_sia(sc, (struct dc_eblock_sia *)hdr); 1753 break; 1754 case DC_EBLOCK_SYM: 1755 dc_decode_leaf_sym(sc, (struct dc_eblock_sym *)hdr); 1756 break; 1757 default: 1758 /* Don't care. Yet. */ 1759 break; 1760 } 1761 ptr += (hdr->dc_len & 0x7F); 1762 ptr++; 1763 } 1764 1765 return; 1766 } 1767 1768 /* 1769 * Attach the interface. Allocate softc structures, do ifmedia 1770 * setup and ethernet/BPF attach. 1771 */ 1772 static int dc_attach(dev) 1773 device_t dev; 1774 { 1775 int tmp = 0; 1776 u_char eaddr[ETHER_ADDR_LEN]; 1777 u_int32_t command; 1778 struct dc_softc *sc; 1779 struct ifnet *ifp; 1780 u_int32_t revision; 1781 int unit, error = 0, rid, mac_offset; 1782 1783 sc = device_get_softc(dev); 1784 unit = device_get_unit(dev); 1785 bzero(sc, sizeof(struct dc_softc)); 1786 1787 mtx_init(&sc->dc_mtx, device_get_nameunit(dev), MTX_DEF | MTX_RECURSE); 1788 DC_LOCK(sc); 1789 1790 /* 1791 * Handle power management nonsense. 1792 */ 1793 dc_acpi(dev); 1794 1795 /* 1796 * Map control/status registers. 1797 */ 1798 pci_enable_busmaster(dev); 1799 pci_enable_io(dev, SYS_RES_IOPORT); 1800 pci_enable_io(dev, SYS_RES_MEMORY); 1801 command = pci_read_config(dev, PCIR_COMMAND, 4); 1802 1803 #ifdef DC_USEIOSPACE 1804 if (!(command & PCIM_CMD_PORTEN)) { 1805 printf("dc%d: failed to enable I/O ports!\n", unit); 1806 error = ENXIO; 1807 goto fail; 1808 } 1809 #else 1810 if (!(command & PCIM_CMD_MEMEN)) { 1811 printf("dc%d: failed to enable memory mapping!\n", unit); 1812 error = ENXIO; 1813 goto fail; 1814 } 1815 #endif 1816 1817 rid = DC_RID; 1818 sc->dc_res = bus_alloc_resource(dev, DC_RES, &rid, 1819 0, ~0, 1, RF_ACTIVE); 1820 1821 if (sc->dc_res == NULL) { 1822 printf("dc%d: couldn't map ports/memory\n", unit); 1823 error = ENXIO; 1824 goto fail; 1825 } 1826 1827 sc->dc_btag = rman_get_bustag(sc->dc_res); 1828 sc->dc_bhandle = rman_get_bushandle(sc->dc_res); 1829 1830 /* Allocate interrupt */ 1831 rid = 0; 1832 sc->dc_irq = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, 0, ~0, 1, 1833 RF_SHAREABLE | RF_ACTIVE); 1834 1835 if (sc->dc_irq == NULL) { 1836 printf("dc%d: couldn't map interrupt\n", unit); 1837 bus_release_resource(dev, DC_RES, DC_RID, sc->dc_res); 1838 error = ENXIO; 1839 goto fail; 1840 } 1841 1842 error = bus_setup_intr(dev, sc->dc_irq, INTR_TYPE_NET | 1843 (IS_MPSAFE ? INTR_MPSAFE : 0), 1844 dc_intr, sc, &sc->dc_intrhand); 1845 1846 if (error) { 1847 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->dc_irq); 1848 bus_release_resource(dev, DC_RES, DC_RID, sc->dc_res); 1849 printf("dc%d: couldn't set up irq\n", unit); 1850 goto fail; 1851 } 1852 1853 /* Need this info to decide on a chip type. */ 1854 sc->dc_info = dc_devtype(dev); 1855 revision = pci_read_config(dev, DC_PCI_CFRV, 4) & 0x000000FF; 1856 1857 switch(sc->dc_info->dc_did) { 1858 case DC_DEVICEID_21143: 1859 sc->dc_type = DC_TYPE_21143; 1860 sc->dc_flags |= DC_TX_POLL|DC_TX_USE_TX_INTR; 1861 sc->dc_flags |= DC_REDUCED_MII_POLL; 1862 /* Save EEPROM contents so we can parse them later. */ 1863 dc_read_eeprom(sc, (caddr_t)&sc->dc_srom, 0, 512, 0); 1864 break; 1865 case DC_DEVICEID_DM9100: 1866 case DC_DEVICEID_DM9102: 1867 sc->dc_type = DC_TYPE_DM9102; 1868 sc->dc_flags |= DC_TX_COALESCE|DC_TX_INTR_ALWAYS; 1869 sc->dc_flags |= DC_REDUCED_MII_POLL|DC_TX_STORENFWD; 1870 sc->dc_pmode = DC_PMODE_MII; 1871 /* Increase the latency timer value. */ 1872 command = pci_read_config(dev, DC_PCI_CFLT, 4); 1873 command &= 0xFFFF00FF; 1874 command |= 0x00008000; 1875 pci_write_config(dev, DC_PCI_CFLT, command, 4); 1876 break; 1877 case DC_DEVICEID_AL981: 1878 sc->dc_type = DC_TYPE_AL981; 1879 sc->dc_flags |= DC_TX_USE_TX_INTR; 1880 sc->dc_flags |= DC_TX_ADMTEK_WAR; 1881 sc->dc_pmode = DC_PMODE_MII; 1882 break; 1883 case DC_DEVICEID_AN985: 1884 case DC_DEVICEID_FE2500: 1885 case DC_DEVICEID_EN2242: 1886 sc->dc_type = DC_TYPE_AN985; 1887 sc->dc_flags |= DC_TX_USE_TX_INTR; 1888 sc->dc_flags |= DC_TX_ADMTEK_WAR; 1889 sc->dc_pmode = DC_PMODE_MII; 1890 break; 1891 case DC_DEVICEID_98713: 1892 case DC_DEVICEID_98713_CP: 1893 if (revision < DC_REVISION_98713A) { 1894 sc->dc_type = DC_TYPE_98713; 1895 } 1896 if (revision >= DC_REVISION_98713A) { 1897 sc->dc_type = DC_TYPE_98713A; 1898 sc->dc_flags |= DC_21143_NWAY; 1899 } 1900 sc->dc_flags |= DC_REDUCED_MII_POLL; 1901 sc->dc_flags |= DC_TX_POLL|DC_TX_USE_TX_INTR; 1902 break; 1903 case DC_DEVICEID_987x5: 1904 case DC_DEVICEID_EN1217: 1905 /* 1906 * Macronix MX98715AEC-C/D/E parts have only a 1907 * 128-bit hash table. We need to deal with these 1908 * in the same manner as the PNIC II so that we 1909 * get the right number of bits out of the 1910 * CRC routine. 1911 */ 1912 if (revision >= DC_REVISION_98715AEC_C && 1913 revision < DC_REVISION_98725) 1914 sc->dc_flags |= DC_128BIT_HASH; 1915 sc->dc_type = DC_TYPE_987x5; 1916 sc->dc_flags |= DC_TX_POLL|DC_TX_USE_TX_INTR; 1917 sc->dc_flags |= DC_REDUCED_MII_POLL|DC_21143_NWAY; 1918 break; 1919 case DC_DEVICEID_98727: 1920 sc->dc_type = DC_TYPE_987x5; 1921 sc->dc_flags |= DC_TX_POLL|DC_TX_USE_TX_INTR; 1922 sc->dc_flags |= DC_REDUCED_MII_POLL|DC_21143_NWAY; 1923 break; 1924 case DC_DEVICEID_82C115: 1925 sc->dc_type = DC_TYPE_PNICII; 1926 sc->dc_flags |= DC_TX_POLL|DC_TX_USE_TX_INTR|DC_128BIT_HASH; 1927 sc->dc_flags |= DC_REDUCED_MII_POLL|DC_21143_NWAY; 1928 break; 1929 case DC_DEVICEID_82C168: 1930 sc->dc_type = DC_TYPE_PNIC; 1931 sc->dc_flags |= DC_TX_STORENFWD|DC_TX_INTR_ALWAYS; 1932 sc->dc_flags |= DC_PNIC_RX_BUG_WAR; 1933 sc->dc_pnic_rx_buf = malloc(DC_RXLEN * 5, M_DEVBUF, M_NOWAIT); 1934 if (revision < DC_REVISION_82C169) 1935 sc->dc_pmode = DC_PMODE_SYM; 1936 break; 1937 case DC_DEVICEID_AX88140A: 1938 sc->dc_type = DC_TYPE_ASIX; 1939 sc->dc_flags |= DC_TX_USE_TX_INTR|DC_TX_INTR_FIRSTFRAG; 1940 sc->dc_flags |= DC_REDUCED_MII_POLL; 1941 sc->dc_pmode = DC_PMODE_MII; 1942 break; 1943 case DC_DEVICEID_X3201: 1944 sc->dc_type = DC_TYPE_XIRCOM; 1945 sc->dc_flags |= DC_TX_INTR_ALWAYS | DC_TX_COALESCE; 1946 /* 1947 * We don't actually need to coalesce, but we're doing 1948 * it to obtain a double word aligned buffer. 1949 */ 1950 break; 1951 case DC_DEVICEID_RS7112: 1952 sc->dc_type = DC_TYPE_CONEXANT; 1953 sc->dc_flags |= DC_TX_INTR_ALWAYS; 1954 sc->dc_flags |= DC_REDUCED_MII_POLL; 1955 sc->dc_pmode = DC_PMODE_MII; 1956 dc_read_eeprom(sc, (caddr_t)&sc->dc_srom, 0, 256, 0); 1957 break; 1958 default: 1959 printf("dc%d: unknown device: %x\n", sc->dc_unit, 1960 sc->dc_info->dc_did); 1961 break; 1962 } 1963 1964 /* Save the cache line size. */ 1965 if (DC_IS_DAVICOM(sc)) 1966 sc->dc_cachesize = 0; 1967 else 1968 sc->dc_cachesize = pci_read_config(dev, 1969 DC_PCI_CFLT, 4) & 0xFF; 1970 1971 /* Reset the adapter. */ 1972 dc_reset(sc); 1973 1974 /* Take 21143 out of snooze mode */ 1975 if (DC_IS_INTEL(sc) || DC_IS_XIRCOM(sc)) { 1976 command = pci_read_config(dev, DC_PCI_CFDD, 4); 1977 command &= ~(DC_CFDD_SNOOZE_MODE|DC_CFDD_SLEEP_MODE); 1978 pci_write_config(dev, DC_PCI_CFDD, command, 4); 1979 } 1980 1981 /* 1982 * Try to learn something about the supported media. 1983 * We know that ASIX and ADMtek and Davicom devices 1984 * will *always* be using MII media, so that's a no-brainer. 1985 * The tricky ones are the Macronix/PNIC II and the 1986 * Intel 21143. 1987 */ 1988 if (DC_IS_INTEL(sc)) 1989 dc_parse_21143_srom(sc); 1990 else if (DC_IS_MACRONIX(sc) || DC_IS_PNICII(sc)) { 1991 if (sc->dc_type == DC_TYPE_98713) 1992 sc->dc_pmode = DC_PMODE_MII; 1993 else 1994 sc->dc_pmode = DC_PMODE_SYM; 1995 } else if (!sc->dc_pmode) 1996 sc->dc_pmode = DC_PMODE_MII; 1997 1998 /* 1999 * Get station address from the EEPROM. 2000 */ 2001 switch(sc->dc_type) { 2002 case DC_TYPE_98713: 2003 case DC_TYPE_98713A: 2004 case DC_TYPE_987x5: 2005 case DC_TYPE_PNICII: 2006 dc_read_eeprom(sc, (caddr_t)&mac_offset, 2007 (DC_EE_NODEADDR_OFFSET / 2), 1, 0); 2008 dc_read_eeprom(sc, (caddr_t)&eaddr, (mac_offset / 2), 3, 0); 2009 break; 2010 case DC_TYPE_PNIC: 2011 dc_read_eeprom(sc, (caddr_t)&eaddr, 0, 3, 1); 2012 break; 2013 case DC_TYPE_DM9102: 2014 case DC_TYPE_21143: 2015 case DC_TYPE_ASIX: 2016 dc_read_eeprom(sc, (caddr_t)&eaddr, DC_EE_NODEADDR, 3, 0); 2017 break; 2018 case DC_TYPE_AL981: 2019 case DC_TYPE_AN985: 2020 dc_read_eeprom(sc, (caddr_t)&eaddr, DC_AL_EE_NODEADDR, 3, 0); 2021 break; 2022 case DC_TYPE_CONEXANT: 2023 bcopy(sc->dc_srom + DC_CONEXANT_EE_NODEADDR, &eaddr, 6); 2024 break; 2025 case DC_TYPE_XIRCOM: 2026 dc_read_eeprom(sc, (caddr_t)&eaddr, 3, 3, 0); 2027 break; 2028 default: 2029 dc_read_eeprom(sc, (caddr_t)&eaddr, DC_EE_NODEADDR, 3, 0); 2030 break; 2031 } 2032 2033 /* 2034 * A 21143 or clone chip was detected. Inform the world. 2035 */ 2036 printf("dc%d: Ethernet address: %6D\n", unit, eaddr, ":"); 2037 2038 sc->dc_unit = unit; 2039 bcopy(eaddr, (char *)&sc->arpcom.ac_enaddr, ETHER_ADDR_LEN); 2040 2041 sc->dc_ldata = contigmalloc(sizeof(struct dc_list_data), M_DEVBUF, 2042 M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0); 2043 2044 if (sc->dc_ldata == NULL) { 2045 printf("dc%d: no memory for list buffers!\n", unit); 2046 bus_teardown_intr(dev, sc->dc_irq, sc->dc_intrhand); 2047 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->dc_irq); 2048 bus_release_resource(dev, DC_RES, DC_RID, sc->dc_res); 2049 error = ENXIO; 2050 goto fail; 2051 } 2052 2053 bzero(sc->dc_ldata, sizeof(struct dc_list_data)); 2054 2055 ifp = &sc->arpcom.ac_if; 2056 ifp->if_softc = sc; 2057 ifp->if_unit = unit; 2058 ifp->if_name = "dc"; 2059 /* XXX: bleah, MTU gets overwritten in ether_ifattach() */ 2060 ifp->if_mtu = ETHERMTU; 2061 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 2062 ifp->if_ioctl = dc_ioctl; 2063 ifp->if_output = ether_output; 2064 ifp->if_start = dc_start; 2065 ifp->if_watchdog = dc_watchdog; 2066 ifp->if_init = dc_init; 2067 ifp->if_baudrate = 10000000; 2068 ifp->if_snd.ifq_maxlen = DC_TX_LIST_CNT - 1; 2069 2070 /* 2071 * Do MII setup. If this is a 21143, check for a PHY on the 2072 * MII bus after applying any necessary fixups to twiddle the 2073 * GPIO bits. If we don't end up finding a PHY, restore the 2074 * old selection (SIA only or SIA/SYM) and attach the dcphy 2075 * driver instead. 2076 */ 2077 if (DC_IS_INTEL(sc)) { 2078 dc_apply_fixup(sc, IFM_AUTO); 2079 tmp = sc->dc_pmode; 2080 sc->dc_pmode = DC_PMODE_MII; 2081 } 2082 2083 error = mii_phy_probe(dev, &sc->dc_miibus, 2084 dc_ifmedia_upd, dc_ifmedia_sts); 2085 2086 if (error && DC_IS_INTEL(sc)) { 2087 sc->dc_pmode = tmp; 2088 if (sc->dc_pmode != DC_PMODE_SIA) 2089 sc->dc_pmode = DC_PMODE_SYM; 2090 sc->dc_flags |= DC_21143_NWAY; 2091 mii_phy_probe(dev, &sc->dc_miibus, 2092 dc_ifmedia_upd, dc_ifmedia_sts); 2093 /* 2094 * For non-MII cards, we need to have the 21143 2095 * drive the LEDs. Except there are some systems 2096 * like the NEC VersaPro NoteBook PC which have no 2097 * LEDs, and twiddling these bits has adverse effects 2098 * on them. (I.e. you suddenly can't get a link.) 2099 */ 2100 if (pci_read_config(dev, DC_PCI_CSID, 4) != 0x80281033) 2101 sc->dc_flags |= DC_TULIP_LEDS; 2102 error = 0; 2103 } 2104 2105 if (error) { 2106 printf("dc%d: MII without any PHY!\n", sc->dc_unit); 2107 bus_teardown_intr(dev, sc->dc_irq, sc->dc_intrhand); 2108 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->dc_irq); 2109 bus_release_resource(dev, DC_RES, DC_RID, sc->dc_res); 2110 error = ENXIO; 2111 goto fail; 2112 } 2113 2114 if (DC_IS_XIRCOM(sc)) { 2115 /* 2116 * setup General Purpose Port mode and data so the tulip 2117 * can talk to the MII. 2118 */ 2119 CSR_WRITE_4(sc, DC_SIAGP, DC_SIAGP_WRITE_EN | DC_SIAGP_INT1_EN | 2120 DC_SIAGP_MD_GP2_OUTPUT | DC_SIAGP_MD_GP0_OUTPUT); 2121 DELAY(10); 2122 CSR_WRITE_4(sc, DC_SIAGP, DC_SIAGP_INT1_EN | 2123 DC_SIAGP_MD_GP2_OUTPUT | DC_SIAGP_MD_GP0_OUTPUT); 2124 DELAY(10); 2125 } 2126 2127 /* 2128 * Call MI attach routine. 2129 */ 2130 ether_ifattach(ifp, ETHER_BPF_SUPPORTED); 2131 callout_init(&sc->dc_stat_ch, IS_MPSAFE); 2132 2133 #ifdef SRM_MEDIA 2134 sc->dc_srm_media = 0; 2135 2136 /* Remember the SRM console media setting */ 2137 if (DC_IS_INTEL(sc)) { 2138 command = pci_read_config(dev, DC_PCI_CFDD, 4); 2139 command &= ~(DC_CFDD_SNOOZE_MODE|DC_CFDD_SLEEP_MODE); 2140 switch ((command >> 8) & 0xff) { 2141 case 3: 2142 sc->dc_srm_media = IFM_10_T; 2143 break; 2144 case 4: 2145 sc->dc_srm_media = IFM_10_T | IFM_FDX; 2146 break; 2147 case 5: 2148 sc->dc_srm_media = IFM_100_TX; 2149 break; 2150 case 6: 2151 sc->dc_srm_media = IFM_100_TX | IFM_FDX; 2152 break; 2153 } 2154 if (sc->dc_srm_media) 2155 sc->dc_srm_media |= IFM_ACTIVE | IFM_ETHER; 2156 } 2157 #endif 2158 2159 DC_UNLOCK(sc); 2160 return(0); 2161 2162 fail: 2163 DC_UNLOCK(sc); 2164 mtx_destroy(&sc->dc_mtx); 2165 return(error); 2166 } 2167 2168 static int dc_detach(dev) 2169 device_t dev; 2170 { 2171 struct dc_softc *sc; 2172 struct ifnet *ifp; 2173 struct dc_mediainfo *m; 2174 2175 sc = device_get_softc(dev); 2176 2177 DC_LOCK(sc); 2178 2179 ifp = &sc->arpcom.ac_if; 2180 2181 dc_stop(sc); 2182 ether_ifdetach(ifp, ETHER_BPF_SUPPORTED); 2183 2184 bus_generic_detach(dev); 2185 device_delete_child(dev, sc->dc_miibus); 2186 2187 bus_teardown_intr(dev, sc->dc_irq, sc->dc_intrhand); 2188 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->dc_irq); 2189 bus_release_resource(dev, DC_RES, DC_RID, sc->dc_res); 2190 2191 contigfree(sc->dc_ldata, sizeof(struct dc_list_data), M_DEVBUF); 2192 if (sc->dc_pnic_rx_buf != NULL) 2193 free(sc->dc_pnic_rx_buf, M_DEVBUF); 2194 2195 while(sc->dc_mi != NULL) { 2196 m = sc->dc_mi->dc_next; 2197 free(sc->dc_mi, M_DEVBUF); 2198 sc->dc_mi = m; 2199 } 2200 2201 DC_UNLOCK(sc); 2202 mtx_destroy(&sc->dc_mtx); 2203 2204 return(0); 2205 } 2206 2207 /* 2208 * Initialize the transmit descriptors. 2209 */ 2210 static int dc_list_tx_init(sc) 2211 struct dc_softc *sc; 2212 { 2213 struct dc_chain_data *cd; 2214 struct dc_list_data *ld; 2215 int i, nexti; 2216 2217 cd = &sc->dc_cdata; 2218 ld = sc->dc_ldata; 2219 for (i = 0; i < DC_TX_LIST_CNT; i++) { 2220 nexti = (i == (DC_TX_LIST_CNT - 1)) ? 0 : i+1; 2221 ld->dc_tx_list[i].dc_next = vtophys(&ld->dc_tx_list[nexti]); 2222 cd->dc_tx_chain[i] = NULL; 2223 ld->dc_tx_list[i].dc_data = 0; 2224 ld->dc_tx_list[i].dc_ctl = 0; 2225 } 2226 2227 cd->dc_tx_prod = cd->dc_tx_cons = cd->dc_tx_cnt = 0; 2228 2229 return(0); 2230 } 2231 2232 2233 /* 2234 * Initialize the RX descriptors and allocate mbufs for them. Note that 2235 * we arrange the descriptors in a closed ring, so that the last descriptor 2236 * points back to the first. 2237 */ 2238 static int dc_list_rx_init(sc) 2239 struct dc_softc *sc; 2240 { 2241 struct dc_chain_data *cd; 2242 struct dc_list_data *ld; 2243 int i, nexti; 2244 2245 cd = &sc->dc_cdata; 2246 ld = sc->dc_ldata; 2247 2248 for (i = 0; i < DC_RX_LIST_CNT; i++) { 2249 if (dc_newbuf(sc, i, NULL) == ENOBUFS) 2250 return(ENOBUFS); 2251 nexti = (i == (DC_RX_LIST_CNT - 1)) ? 0 : i+1; 2252 ld->dc_rx_list[i].dc_next = vtophys(&ld->dc_rx_list[nexti]); 2253 } 2254 2255 cd->dc_rx_prod = 0; 2256 2257 return(0); 2258 } 2259 2260 /* 2261 * Initialize an RX descriptor and attach an MBUF cluster. 2262 */ 2263 static int dc_newbuf(sc, i, m) 2264 struct dc_softc *sc; 2265 int i; 2266 struct mbuf *m; 2267 { 2268 struct mbuf *m_new = NULL; 2269 struct dc_desc *c; 2270 2271 c = &sc->dc_ldata->dc_rx_list[i]; 2272 2273 if (m == NULL) { 2274 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 2275 if (m_new == NULL) { 2276 printf("dc%d: no memory for rx list " 2277 "-- packet dropped!\n", sc->dc_unit); 2278 return(ENOBUFS); 2279 } 2280 2281 MCLGET(m_new, M_DONTWAIT); 2282 if (!(m_new->m_flags & M_EXT)) { 2283 printf("dc%d: no memory for rx list " 2284 "-- packet dropped!\n", sc->dc_unit); 2285 m_freem(m_new); 2286 return(ENOBUFS); 2287 } 2288 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 2289 } else { 2290 m_new = m; 2291 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 2292 m_new->m_data = m_new->m_ext.ext_buf; 2293 } 2294 2295 m_adj(m_new, sizeof(u_int64_t)); 2296 2297 /* 2298 * If this is a PNIC chip, zero the buffer. This is part 2299 * of the workaround for the receive bug in the 82c168 and 2300 * 82c169 chips. 2301 */ 2302 if (sc->dc_flags & DC_PNIC_RX_BUG_WAR) 2303 bzero((char *)mtod(m_new, char *), m_new->m_len); 2304 2305 sc->dc_cdata.dc_rx_chain[i] = m_new; 2306 c->dc_data = vtophys(mtod(m_new, caddr_t)); 2307 c->dc_ctl = DC_RXCTL_RLINK | DC_RXLEN; 2308 c->dc_status = DC_RXSTAT_OWN; 2309 2310 return(0); 2311 } 2312 2313 /* 2314 * Grrrrr. 2315 * The PNIC chip has a terrible bug in it that manifests itself during 2316 * periods of heavy activity. The exact mode of failure if difficult to 2317 * pinpoint: sometimes it only happens in promiscuous mode, sometimes it 2318 * will happen on slow machines. The bug is that sometimes instead of 2319 * uploading one complete frame during reception, it uploads what looks 2320 * like the entire contents of its FIFO memory. The frame we want is at 2321 * the end of the whole mess, but we never know exactly how much data has 2322 * been uploaded, so salvaging the frame is hard. 2323 * 2324 * There is only one way to do it reliably, and it's disgusting. 2325 * Here's what we know: 2326 * 2327 * - We know there will always be somewhere between one and three extra 2328 * descriptors uploaded. 2329 * 2330 * - We know the desired received frame will always be at the end of the 2331 * total data upload. 2332 * 2333 * - We know the size of the desired received frame because it will be 2334 * provided in the length field of the status word in the last descriptor. 2335 * 2336 * Here's what we do: 2337 * 2338 * - When we allocate buffers for the receive ring, we bzero() them. 2339 * This means that we know that the buffer contents should be all 2340 * zeros, except for data uploaded by the chip. 2341 * 2342 * - We also force the PNIC chip to upload frames that include the 2343 * ethernet CRC at the end. 2344 * 2345 * - We gather all of the bogus frame data into a single buffer. 2346 * 2347 * - We then position a pointer at the end of this buffer and scan 2348 * backwards until we encounter the first non-zero byte of data. 2349 * This is the end of the received frame. We know we will encounter 2350 * some data at the end of the frame because the CRC will always be 2351 * there, so even if the sender transmits a packet of all zeros, 2352 * we won't be fooled. 2353 * 2354 * - We know the size of the actual received frame, so we subtract 2355 * that value from the current pointer location. This brings us 2356 * to the start of the actual received packet. 2357 * 2358 * - We copy this into an mbuf and pass it on, along with the actual 2359 * frame length. 2360 * 2361 * The performance hit is tremendous, but it beats dropping frames all 2362 * the time. 2363 */ 2364 2365 #define DC_WHOLEFRAME (DC_RXSTAT_FIRSTFRAG|DC_RXSTAT_LASTFRAG) 2366 static void dc_pnic_rx_bug_war(sc, idx) 2367 struct dc_softc *sc; 2368 int idx; 2369 { 2370 struct dc_desc *cur_rx; 2371 struct dc_desc *c = NULL; 2372 struct mbuf *m = NULL; 2373 unsigned char *ptr; 2374 int i, total_len; 2375 u_int32_t rxstat = 0; 2376 2377 i = sc->dc_pnic_rx_bug_save; 2378 cur_rx = &sc->dc_ldata->dc_rx_list[idx]; 2379 ptr = sc->dc_pnic_rx_buf; 2380 bzero(ptr, sizeof(DC_RXLEN * 5)); 2381 2382 /* Copy all the bytes from the bogus buffers. */ 2383 while (1) { 2384 c = &sc->dc_ldata->dc_rx_list[i]; 2385 rxstat = c->dc_status; 2386 m = sc->dc_cdata.dc_rx_chain[i]; 2387 bcopy(mtod(m, char *), ptr, DC_RXLEN); 2388 ptr += DC_RXLEN; 2389 /* If this is the last buffer, break out. */ 2390 if (i == idx || rxstat & DC_RXSTAT_LASTFRAG) 2391 break; 2392 dc_newbuf(sc, i, m); 2393 DC_INC(i, DC_RX_LIST_CNT); 2394 } 2395 2396 /* Find the length of the actual receive frame. */ 2397 total_len = DC_RXBYTES(rxstat); 2398 2399 /* Scan backwards until we hit a non-zero byte. */ 2400 while(*ptr == 0x00) 2401 ptr--; 2402 2403 /* Round off. */ 2404 if ((uintptr_t)(ptr) & 0x3) 2405 ptr -= 1; 2406 2407 /* Now find the start of the frame. */ 2408 ptr -= total_len; 2409 if (ptr < sc->dc_pnic_rx_buf) 2410 ptr = sc->dc_pnic_rx_buf; 2411 2412 /* 2413 * Now copy the salvaged frame to the last mbuf and fake up 2414 * the status word to make it look like a successful 2415 * frame reception. 2416 */ 2417 dc_newbuf(sc, i, m); 2418 bcopy(ptr, mtod(m, char *), total_len); 2419 cur_rx->dc_status = rxstat | DC_RXSTAT_FIRSTFRAG; 2420 2421 return; 2422 } 2423 2424 /* 2425 * This routine searches the RX ring for dirty descriptors in the 2426 * event that the rxeof routine falls out of sync with the chip's 2427 * current descriptor pointer. This may happen sometimes as a result 2428 * of a "no RX buffer available" condition that happens when the chip 2429 * consumes all of the RX buffers before the driver has a chance to 2430 * process the RX ring. This routine may need to be called more than 2431 * once to bring the driver back in sync with the chip, however we 2432 * should still be getting RX DONE interrupts to drive the search 2433 * for new packets in the RX ring, so we should catch up eventually. 2434 */ 2435 static int dc_rx_resync(sc) 2436 struct dc_softc *sc; 2437 { 2438 int i, pos; 2439 struct dc_desc *cur_rx; 2440 2441 pos = sc->dc_cdata.dc_rx_prod; 2442 2443 for (i = 0; i < DC_RX_LIST_CNT; i++) { 2444 cur_rx = &sc->dc_ldata->dc_rx_list[pos]; 2445 if (!(cur_rx->dc_status & DC_RXSTAT_OWN)) 2446 break; 2447 DC_INC(pos, DC_RX_LIST_CNT); 2448 } 2449 2450 /* If the ring really is empty, then just return. */ 2451 if (i == DC_RX_LIST_CNT) 2452 return(0); 2453 2454 /* We've fallen behing the chip: catch it. */ 2455 sc->dc_cdata.dc_rx_prod = pos; 2456 2457 return(EAGAIN); 2458 } 2459 2460 /* 2461 * A frame has been uploaded: pass the resulting mbuf chain up to 2462 * the higher level protocols. 2463 */ 2464 static void dc_rxeof(sc) 2465 struct dc_softc *sc; 2466 { 2467 struct ether_header *eh; 2468 struct mbuf *m; 2469 struct ifnet *ifp; 2470 struct dc_desc *cur_rx; 2471 int i, total_len = 0; 2472 u_int32_t rxstat; 2473 2474 ifp = &sc->arpcom.ac_if; 2475 i = sc->dc_cdata.dc_rx_prod; 2476 2477 while(!(sc->dc_ldata->dc_rx_list[i].dc_status & DC_RXSTAT_OWN)) { 2478 2479 cur_rx = &sc->dc_ldata->dc_rx_list[i]; 2480 rxstat = cur_rx->dc_status; 2481 m = sc->dc_cdata.dc_rx_chain[i]; 2482 total_len = DC_RXBYTES(rxstat); 2483 2484 if (sc->dc_flags & DC_PNIC_RX_BUG_WAR) { 2485 if ((rxstat & DC_WHOLEFRAME) != DC_WHOLEFRAME) { 2486 if (rxstat & DC_RXSTAT_FIRSTFRAG) 2487 sc->dc_pnic_rx_bug_save = i; 2488 if ((rxstat & DC_RXSTAT_LASTFRAG) == 0) { 2489 DC_INC(i, DC_RX_LIST_CNT); 2490 continue; 2491 } 2492 dc_pnic_rx_bug_war(sc, i); 2493 rxstat = cur_rx->dc_status; 2494 total_len = DC_RXBYTES(rxstat); 2495 } 2496 } 2497 2498 sc->dc_cdata.dc_rx_chain[i] = NULL; 2499 2500 /* 2501 * If an error occurs, update stats, clear the 2502 * status word and leave the mbuf cluster in place: 2503 * it should simply get re-used next time this descriptor 2504 * comes up in the ring. 2505 */ 2506 if (rxstat & DC_RXSTAT_RXERR) { 2507 ifp->if_ierrors++; 2508 if (rxstat & DC_RXSTAT_COLLSEEN) 2509 ifp->if_collisions++; 2510 dc_newbuf(sc, i, m); 2511 if (rxstat & DC_RXSTAT_CRCERR) { 2512 DC_INC(i, DC_RX_LIST_CNT); 2513 continue; 2514 } else { 2515 dc_init(sc); 2516 return; 2517 } 2518 } 2519 2520 /* No errors; receive the packet. */ 2521 total_len -= ETHER_CRC_LEN; 2522 #ifdef __i386__ 2523 /* 2524 * On the x86 we do not have alignment problems, so try to 2525 * allocate a new buffer for the receive ring, and pass up 2526 * the one where the packet is already, saving the expensive 2527 * copy done in m_devget(). 2528 * If we are on an architecture with alignment problems, or 2529 * if the allocation fails, then use m_devget and leave the 2530 * existing buffer in the receive ring. 2531 */ 2532 if (dc_quick && dc_newbuf(sc, i, NULL) == 0) { 2533 m->m_pkthdr.rcvif = ifp; 2534 m->m_pkthdr.len = m->m_len = total_len; 2535 DC_INC(i, DC_RX_LIST_CNT); 2536 } else 2537 #endif 2538 { 2539 struct mbuf *m0; 2540 2541 m0 = m_devget(mtod(m, char *), total_len, 2542 ETHER_ALIGN, ifp, NULL); 2543 dc_newbuf(sc, i, m); 2544 DC_INC(i, DC_RX_LIST_CNT); 2545 if (m0 == NULL) { 2546 ifp->if_ierrors++; 2547 continue; 2548 } 2549 m = m0; 2550 } 2551 2552 ifp->if_ipackets++; 2553 eh = mtod(m, struct ether_header *); 2554 2555 /* Remove header from mbuf and pass it on. */ 2556 m_adj(m, sizeof(struct ether_header)); 2557 ether_input(ifp, eh, m); 2558 } 2559 2560 sc->dc_cdata.dc_rx_prod = i; 2561 } 2562 2563 /* 2564 * A frame was downloaded to the chip. It's safe for us to clean up 2565 * the list buffers. 2566 */ 2567 2568 static void dc_txeof(sc) 2569 struct dc_softc *sc; 2570 { 2571 struct dc_desc *cur_tx = NULL; 2572 struct ifnet *ifp; 2573 int idx; 2574 2575 ifp = &sc->arpcom.ac_if; 2576 2577 /* Clear the timeout timer. */ 2578 ifp->if_timer = 0; 2579 2580 /* 2581 * Go through our tx list and free mbufs for those 2582 * frames that have been transmitted. 2583 */ 2584 idx = sc->dc_cdata.dc_tx_cons; 2585 while(idx != sc->dc_cdata.dc_tx_prod) { 2586 u_int32_t txstat; 2587 2588 cur_tx = &sc->dc_ldata->dc_tx_list[idx]; 2589 txstat = cur_tx->dc_status; 2590 2591 if (txstat & DC_TXSTAT_OWN) 2592 break; 2593 2594 if (!(cur_tx->dc_ctl & DC_TXCTL_LASTFRAG) || 2595 cur_tx->dc_ctl & DC_TXCTL_SETUP) { 2596 sc->dc_cdata.dc_tx_cnt--; 2597 if (cur_tx->dc_ctl & DC_TXCTL_SETUP) { 2598 /* 2599 * Yes, the PNIC is so brain damaged 2600 * that it will sometimes generate a TX 2601 * underrun error while DMAing the RX 2602 * filter setup frame. If we detect this, 2603 * we have to send the setup frame again, 2604 * or else the filter won't be programmed 2605 * correctly. 2606 */ 2607 if (DC_IS_PNIC(sc)) { 2608 if (txstat & DC_TXSTAT_ERRSUM) 2609 dc_setfilt(sc); 2610 } 2611 sc->dc_cdata.dc_tx_chain[idx] = NULL; 2612 } 2613 DC_INC(idx, DC_TX_LIST_CNT); 2614 continue; 2615 } 2616 2617 if (DC_IS_XIRCOM(sc)) { 2618 /* 2619 * XXX: Why does my Xircom taunt me so? 2620 * For some reason it likes setting the CARRLOST flag 2621 * even when the carrier is there. wtf?!? */ 2622 if (/*sc->dc_type == DC_TYPE_21143 &&*/ 2623 sc->dc_pmode == DC_PMODE_MII && 2624 ((txstat & 0xFFFF) & ~(DC_TXSTAT_ERRSUM| 2625 DC_TXSTAT_NOCARRIER))) 2626 txstat &= ~DC_TXSTAT_ERRSUM; 2627 } else { 2628 if (/*sc->dc_type == DC_TYPE_21143 &&*/ 2629 sc->dc_pmode == DC_PMODE_MII && 2630 ((txstat & 0xFFFF) & ~(DC_TXSTAT_ERRSUM| 2631 DC_TXSTAT_NOCARRIER|DC_TXSTAT_CARRLOST))) 2632 txstat &= ~DC_TXSTAT_ERRSUM; 2633 } 2634 2635 if (txstat & DC_TXSTAT_ERRSUM) { 2636 ifp->if_oerrors++; 2637 if (txstat & DC_TXSTAT_EXCESSCOLL) 2638 ifp->if_collisions++; 2639 if (txstat & DC_TXSTAT_LATECOLL) 2640 ifp->if_collisions++; 2641 if (!(txstat & DC_TXSTAT_UNDERRUN)) { 2642 dc_init(sc); 2643 return; 2644 } 2645 } 2646 2647 ifp->if_collisions += (txstat & DC_TXSTAT_COLLCNT) >> 3; 2648 2649 ifp->if_opackets++; 2650 if (sc->dc_cdata.dc_tx_chain[idx] != NULL) { 2651 m_freem(sc->dc_cdata.dc_tx_chain[idx]); 2652 sc->dc_cdata.dc_tx_chain[idx] = NULL; 2653 } 2654 2655 sc->dc_cdata.dc_tx_cnt--; 2656 DC_INC(idx, DC_TX_LIST_CNT); 2657 } 2658 2659 sc->dc_cdata.dc_tx_cons = idx; 2660 if (cur_tx != NULL) 2661 ifp->if_flags &= ~IFF_OACTIVE; 2662 2663 return; 2664 } 2665 2666 static void dc_tick(xsc) 2667 void *xsc; 2668 { 2669 struct dc_softc *sc; 2670 struct mii_data *mii; 2671 struct ifnet *ifp; 2672 u_int32_t r; 2673 2674 sc = xsc; 2675 DC_LOCK(sc); 2676 ifp = &sc->arpcom.ac_if; 2677 mii = device_get_softc(sc->dc_miibus); 2678 2679 if (sc->dc_flags & DC_REDUCED_MII_POLL) { 2680 if (sc->dc_flags & DC_21143_NWAY) { 2681 r = CSR_READ_4(sc, DC_10BTSTAT); 2682 if (IFM_SUBTYPE(mii->mii_media_active) == 2683 IFM_100_TX && (r & DC_TSTAT_LS100)) { 2684 sc->dc_link = 0; 2685 mii_mediachg(mii); 2686 } 2687 if (IFM_SUBTYPE(mii->mii_media_active) == 2688 IFM_10_T && (r & DC_TSTAT_LS10)) { 2689 sc->dc_link = 0; 2690 mii_mediachg(mii); 2691 } 2692 if (sc->dc_link == 0) 2693 mii_tick(mii); 2694 } else { 2695 r = CSR_READ_4(sc, DC_ISR); 2696 if ((r & DC_ISR_RX_STATE) == DC_RXSTATE_WAIT && 2697 sc->dc_cdata.dc_tx_cnt == 0) 2698 mii_tick(mii); 2699 if (!(mii->mii_media_status & IFM_ACTIVE)) 2700 sc->dc_link = 0; 2701 } 2702 } else 2703 mii_tick(mii); 2704 2705 /* 2706 * When the init routine completes, we expect to be able to send 2707 * packets right away, and in fact the network code will send a 2708 * gratuitous ARP the moment the init routine marks the interface 2709 * as running. However, even though the MAC may have been initialized, 2710 * there may be a delay of a few seconds before the PHY completes 2711 * autonegotiation and the link is brought up. Any transmissions 2712 * made during that delay will be lost. Dealing with this is tricky: 2713 * we can't just pause in the init routine while waiting for the 2714 * PHY to come ready since that would bring the whole system to 2715 * a screeching halt for several seconds. 2716 * 2717 * What we do here is prevent the TX start routine from sending 2718 * any packets until a link has been established. After the 2719 * interface has been initialized, the tick routine will poll 2720 * the state of the PHY until the IFM_ACTIVE flag is set. Until 2721 * that time, packets will stay in the send queue, and once the 2722 * link comes up, they will be flushed out to the wire. 2723 */ 2724 if (!sc->dc_link && mii->mii_media_status & IFM_ACTIVE && 2725 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) { 2726 sc->dc_link++; 2727 if (ifp->if_snd.ifq_head != NULL) 2728 dc_start(ifp); 2729 } 2730 2731 if (sc->dc_flags & DC_21143_NWAY && !sc->dc_link) 2732 callout_reset(&sc->dc_stat_ch, hz/10, dc_tick, sc); 2733 else 2734 callout_reset(&sc->dc_stat_ch, hz, dc_tick, sc); 2735 2736 DC_UNLOCK(sc); 2737 2738 return; 2739 } 2740 2741 /* 2742 * A transmit underrun has occurred. Back off the transmit threshold, 2743 * or switch to store and forward mode if we have to. 2744 */ 2745 static void dc_tx_underrun(sc) 2746 struct dc_softc *sc; 2747 { 2748 u_int32_t isr; 2749 int i; 2750 2751 if (DC_IS_DAVICOM(sc)) 2752 dc_init(sc); 2753 2754 if (DC_IS_INTEL(sc)) { 2755 /* 2756 * The real 21143 requires that the transmitter be idle 2757 * in order to change the transmit threshold or store 2758 * and forward state. 2759 */ 2760 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_TX_ON); 2761 2762 for (i = 0; i < DC_TIMEOUT; i++) { 2763 isr = CSR_READ_4(sc, DC_ISR); 2764 if (isr & DC_ISR_TX_IDLE) 2765 break; 2766 DELAY(10); 2767 } 2768 if (i == DC_TIMEOUT) { 2769 printf("dc%d: failed to force tx to idle state\n", 2770 sc->dc_unit); 2771 dc_init(sc); 2772 } 2773 } 2774 2775 printf("dc%d: TX underrun -- ", sc->dc_unit); 2776 sc->dc_txthresh += DC_TXTHRESH_INC; 2777 if (sc->dc_txthresh > DC_TXTHRESH_MAX) { 2778 printf("using store and forward mode\n"); 2779 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_STORENFWD); 2780 } else { 2781 printf("increasing TX threshold\n"); 2782 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_TX_THRESH); 2783 DC_SETBIT(sc, DC_NETCFG, sc->dc_txthresh); 2784 } 2785 2786 if (DC_IS_INTEL(sc)) 2787 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_TX_ON); 2788 2789 return; 2790 } 2791 2792 static void dc_intr(arg) 2793 void *arg; 2794 { 2795 struct dc_softc *sc; 2796 struct ifnet *ifp; 2797 u_int32_t status; 2798 2799 sc = arg; 2800 2801 if ( (CSR_READ_4(sc, DC_ISR) & DC_INTRS) == 0) 2802 return ; 2803 2804 DC_LOCK(sc); 2805 ifp = &sc->arpcom.ac_if; 2806 2807 /* Suppress unwanted interrupts */ 2808 if (!(ifp->if_flags & IFF_UP)) { 2809 if (CSR_READ_4(sc, DC_ISR) & DC_INTRS) 2810 dc_stop(sc); 2811 DC_UNLOCK(sc); 2812 return; 2813 } 2814 2815 /* Disable interrupts. */ 2816 CSR_WRITE_4(sc, DC_IMR, 0x00000000); 2817 2818 while(((status = CSR_READ_4(sc, DC_ISR)) & DC_INTRS) 2819 && status != 0xFFFFFFFF) { 2820 2821 CSR_WRITE_4(sc, DC_ISR, status); 2822 2823 if (status & DC_ISR_RX_OK) { 2824 int curpkts; 2825 curpkts = ifp->if_ipackets; 2826 dc_rxeof(sc); 2827 if (curpkts == ifp->if_ipackets) { 2828 while(dc_rx_resync(sc)) 2829 dc_rxeof(sc); 2830 } 2831 } 2832 2833 if (status & (DC_ISR_TX_OK|DC_ISR_TX_NOBUF)) 2834 dc_txeof(sc); 2835 2836 if (status & DC_ISR_TX_IDLE) { 2837 dc_txeof(sc); 2838 if (sc->dc_cdata.dc_tx_cnt) { 2839 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_TX_ON); 2840 CSR_WRITE_4(sc, DC_TXSTART, 0xFFFFFFFF); 2841 } 2842 } 2843 2844 if (status & DC_ISR_TX_UNDERRUN) 2845 dc_tx_underrun(sc); 2846 2847 if ((status & DC_ISR_RX_WATDOGTIMEO) 2848 || (status & DC_ISR_RX_NOBUF)) { 2849 int curpkts; 2850 curpkts = ifp->if_ipackets; 2851 dc_rxeof(sc); 2852 if (curpkts == ifp->if_ipackets) { 2853 while(dc_rx_resync(sc)) 2854 dc_rxeof(sc); 2855 } 2856 } 2857 2858 if (status & DC_ISR_BUS_ERR) { 2859 dc_reset(sc); 2860 dc_init(sc); 2861 } 2862 } 2863 2864 /* Re-enable interrupts. */ 2865 CSR_WRITE_4(sc, DC_IMR, DC_INTRS); 2866 2867 if (ifp->if_snd.ifq_head != NULL) 2868 dc_start(ifp); 2869 2870 DC_UNLOCK(sc); 2871 2872 return; 2873 } 2874 2875 /* 2876 * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data 2877 * pointers to the fragment pointers. 2878 */ 2879 static int dc_encap(sc, m_head, txidx) 2880 struct dc_softc *sc; 2881 struct mbuf *m_head; 2882 u_int32_t *txidx; 2883 { 2884 struct dc_desc *f = NULL; 2885 struct mbuf *m; 2886 int frag, cur, cnt = 0; 2887 2888 /* 2889 * Start packing the mbufs in this chain into 2890 * the fragment pointers. Stop when we run out 2891 * of fragments or hit the end of the mbuf chain. 2892 */ 2893 m = m_head; 2894 cur = frag = *txidx; 2895 2896 for (m = m_head; m != NULL; m = m->m_next) { 2897 if (m->m_len != 0) { 2898 if (sc->dc_flags & DC_TX_ADMTEK_WAR) { 2899 if (*txidx != sc->dc_cdata.dc_tx_prod && 2900 frag == (DC_TX_LIST_CNT - 1)) 2901 return(ENOBUFS); 2902 } 2903 if ((DC_TX_LIST_CNT - 2904 (sc->dc_cdata.dc_tx_cnt + cnt)) < 5) 2905 return(ENOBUFS); 2906 2907 f = &sc->dc_ldata->dc_tx_list[frag]; 2908 f->dc_ctl = DC_TXCTL_TLINK | m->m_len; 2909 if (cnt == 0) { 2910 f->dc_status = 0; 2911 f->dc_ctl |= DC_TXCTL_FIRSTFRAG; 2912 } else 2913 f->dc_status = DC_TXSTAT_OWN; 2914 f->dc_data = vtophys(mtod(m, vm_offset_t)); 2915 cur = frag; 2916 DC_INC(frag, DC_TX_LIST_CNT); 2917 cnt++; 2918 } 2919 } 2920 2921 if (m != NULL) 2922 return(ENOBUFS); 2923 2924 sc->dc_cdata.dc_tx_cnt += cnt; 2925 sc->dc_cdata.dc_tx_chain[cur] = m_head; 2926 sc->dc_ldata->dc_tx_list[cur].dc_ctl |= DC_TXCTL_LASTFRAG; 2927 if (sc->dc_flags & DC_TX_INTR_FIRSTFRAG) 2928 sc->dc_ldata->dc_tx_list[*txidx].dc_ctl |= DC_TXCTL_FINT; 2929 if (sc->dc_flags & DC_TX_INTR_ALWAYS) 2930 sc->dc_ldata->dc_tx_list[cur].dc_ctl |= DC_TXCTL_FINT; 2931 if (sc->dc_flags & DC_TX_USE_TX_INTR && sc->dc_cdata.dc_tx_cnt > 64) 2932 sc->dc_ldata->dc_tx_list[cur].dc_ctl |= DC_TXCTL_FINT; 2933 sc->dc_ldata->dc_tx_list[*txidx].dc_status = DC_TXSTAT_OWN; 2934 *txidx = frag; 2935 2936 return(0); 2937 } 2938 2939 /* 2940 * Coalesce an mbuf chain into a single mbuf cluster buffer. 2941 * Needed for some really badly behaved chips that just can't 2942 * do scatter/gather correctly. 2943 */ 2944 static int dc_coal(sc, m_head) 2945 struct dc_softc *sc; 2946 struct mbuf **m_head; 2947 { 2948 struct mbuf *m_new, *m; 2949 2950 m = *m_head; 2951 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 2952 if (m_new == NULL) { 2953 printf("dc%d: no memory for tx list", sc->dc_unit); 2954 return(ENOBUFS); 2955 } 2956 if (m->m_pkthdr.len > MHLEN) { 2957 MCLGET(m_new, M_DONTWAIT); 2958 if (!(m_new->m_flags & M_EXT)) { 2959 m_freem(m_new); 2960 printf("dc%d: no memory for tx list", sc->dc_unit); 2961 return(ENOBUFS); 2962 } 2963 } 2964 m_copydata(m, 0, m->m_pkthdr.len, mtod(m_new, caddr_t)); 2965 m_new->m_pkthdr.len = m_new->m_len = m->m_pkthdr.len; 2966 m_freem(m); 2967 *m_head = m_new; 2968 2969 return(0); 2970 } 2971 2972 /* 2973 * Main transmit routine. To avoid having to do mbuf copies, we put pointers 2974 * to the mbuf data regions directly in the transmit lists. We also save a 2975 * copy of the pointers since the transmit list fragment pointers are 2976 * physical addresses. 2977 */ 2978 2979 static void dc_start(ifp) 2980 struct ifnet *ifp; 2981 { 2982 struct dc_softc *sc; 2983 struct mbuf *m_head = NULL; 2984 int idx; 2985 2986 sc = ifp->if_softc; 2987 2988 DC_LOCK(sc); 2989 2990 if (!sc->dc_link && ifp->if_snd.ifq_len < 10) { 2991 DC_UNLOCK(sc); 2992 return; 2993 } 2994 2995 if (ifp->if_flags & IFF_OACTIVE) { 2996 DC_UNLOCK(sc); 2997 return; 2998 } 2999 3000 idx = sc->dc_cdata.dc_tx_prod; 3001 3002 while(sc->dc_cdata.dc_tx_chain[idx] == NULL) { 3003 IF_DEQUEUE(&ifp->if_snd, m_head); 3004 if (m_head == NULL) 3005 break; 3006 3007 if (sc->dc_flags & DC_TX_COALESCE) { 3008 if (dc_coal(sc, &m_head)) { 3009 IF_PREPEND(&ifp->if_snd, m_head); 3010 ifp->if_flags |= IFF_OACTIVE; 3011 break; 3012 } 3013 } 3014 3015 if (dc_encap(sc, m_head, &idx)) { 3016 IF_PREPEND(&ifp->if_snd, m_head); 3017 ifp->if_flags |= IFF_OACTIVE; 3018 break; 3019 } 3020 3021 /* 3022 * If there's a BPF listener, bounce a copy of this frame 3023 * to him. 3024 */ 3025 if (ifp->if_bpf) 3026 bpf_mtap(ifp, m_head); 3027 3028 if (sc->dc_flags & DC_TX_ONE) { 3029 ifp->if_flags |= IFF_OACTIVE; 3030 break; 3031 } 3032 } 3033 3034 /* Transmit */ 3035 sc->dc_cdata.dc_tx_prod = idx; 3036 if (!(sc->dc_flags & DC_TX_POLL)) 3037 CSR_WRITE_4(sc, DC_TXSTART, 0xFFFFFFFF); 3038 3039 /* 3040 * Set a timeout in case the chip goes out to lunch. 3041 */ 3042 ifp->if_timer = 5; 3043 3044 DC_UNLOCK(sc); 3045 3046 return; 3047 } 3048 3049 static void dc_init(xsc) 3050 void *xsc; 3051 { 3052 struct dc_softc *sc = xsc; 3053 struct ifnet *ifp = &sc->arpcom.ac_if; 3054 struct mii_data *mii; 3055 3056 DC_LOCK(sc); 3057 3058 mii = device_get_softc(sc->dc_miibus); 3059 3060 /* 3061 * Cancel pending I/O and free all RX/TX buffers. 3062 */ 3063 dc_stop(sc); 3064 dc_reset(sc); 3065 3066 /* 3067 * Set cache alignment and burst length. 3068 */ 3069 if (DC_IS_ASIX(sc) || DC_IS_DAVICOM(sc)) 3070 CSR_WRITE_4(sc, DC_BUSCTL, 0); 3071 else 3072 CSR_WRITE_4(sc, DC_BUSCTL, DC_BUSCTL_MRME|DC_BUSCTL_MRLE); 3073 /* 3074 * Evenly share the bus between receive and transmit process. 3075 */ 3076 if (DC_IS_INTEL(sc)) 3077 DC_SETBIT(sc, DC_BUSCTL, DC_BUSCTL_ARBITRATION); 3078 if (DC_IS_DAVICOM(sc) || DC_IS_INTEL(sc)) { 3079 DC_SETBIT(sc, DC_BUSCTL, DC_BURSTLEN_USECA); 3080 } else { 3081 DC_SETBIT(sc, DC_BUSCTL, DC_BURSTLEN_16LONG); 3082 } 3083 if (sc->dc_flags & DC_TX_POLL) 3084 DC_SETBIT(sc, DC_BUSCTL, DC_TXPOLL_1); 3085 switch(sc->dc_cachesize) { 3086 case 32: 3087 DC_SETBIT(sc, DC_BUSCTL, DC_CACHEALIGN_32LONG); 3088 break; 3089 case 16: 3090 DC_SETBIT(sc, DC_BUSCTL, DC_CACHEALIGN_16LONG); 3091 break; 3092 case 8: 3093 DC_SETBIT(sc, DC_BUSCTL, DC_CACHEALIGN_8LONG); 3094 break; 3095 case 0: 3096 default: 3097 DC_SETBIT(sc, DC_BUSCTL, DC_CACHEALIGN_NONE); 3098 break; 3099 } 3100 3101 if (sc->dc_flags & DC_TX_STORENFWD) 3102 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_STORENFWD); 3103 else { 3104 if (sc->dc_txthresh > DC_TXTHRESH_MAX) { 3105 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_STORENFWD); 3106 } else { 3107 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_STORENFWD); 3108 DC_SETBIT(sc, DC_NETCFG, sc->dc_txthresh); 3109 } 3110 } 3111 3112 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_NO_RXCRC); 3113 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_TX_BACKOFF); 3114 3115 if (DC_IS_MACRONIX(sc) || DC_IS_PNICII(sc)) { 3116 /* 3117 * The app notes for the 98713 and 98715A say that 3118 * in order to have the chips operate properly, a magic 3119 * number must be written to CSR16. Macronix does not 3120 * document the meaning of these bits so there's no way 3121 * to know exactly what they do. The 98713 has a magic 3122 * number all its own; the rest all use a different one. 3123 */ 3124 DC_CLRBIT(sc, DC_MX_MAGICPACKET, 0xFFFF0000); 3125 if (sc->dc_type == DC_TYPE_98713) 3126 DC_SETBIT(sc, DC_MX_MAGICPACKET, DC_MX_MAGIC_98713); 3127 else 3128 DC_SETBIT(sc, DC_MX_MAGICPACKET, DC_MX_MAGIC_98715); 3129 } 3130 3131 if (DC_IS_XIRCOM(sc)) { 3132 /* 3133 * setup General Purpose Port mode and data so the tulip 3134 * can talk to the MII. 3135 */ 3136 CSR_WRITE_4(sc, DC_SIAGP, DC_SIAGP_WRITE_EN | DC_SIAGP_INT1_EN | 3137 DC_SIAGP_MD_GP2_OUTPUT | DC_SIAGP_MD_GP0_OUTPUT); 3138 DELAY(10); 3139 CSR_WRITE_4(sc, DC_SIAGP, DC_SIAGP_INT1_EN | 3140 DC_SIAGP_MD_GP2_OUTPUT | DC_SIAGP_MD_GP0_OUTPUT); 3141 DELAY(10); 3142 } 3143 3144 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_TX_THRESH); 3145 DC_SETBIT(sc, DC_NETCFG, DC_TXTHRESH_MIN); 3146 3147 /* Init circular RX list. */ 3148 if (dc_list_rx_init(sc) == ENOBUFS) { 3149 printf("dc%d: initialization failed: no " 3150 "memory for rx buffers\n", sc->dc_unit); 3151 dc_stop(sc); 3152 DC_UNLOCK(sc); 3153 return; 3154 } 3155 3156 /* 3157 * Init tx descriptors. 3158 */ 3159 dc_list_tx_init(sc); 3160 3161 /* 3162 * Load the address of the RX list. 3163 */ 3164 CSR_WRITE_4(sc, DC_RXADDR, vtophys(&sc->dc_ldata->dc_rx_list[0])); 3165 CSR_WRITE_4(sc, DC_TXADDR, vtophys(&sc->dc_ldata->dc_tx_list[0])); 3166 3167 /* 3168 * Enable interrupts. 3169 */ 3170 CSR_WRITE_4(sc, DC_IMR, DC_INTRS); 3171 CSR_WRITE_4(sc, DC_ISR, 0xFFFFFFFF); 3172 3173 /* Enable transmitter. */ 3174 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_TX_ON); 3175 3176 /* 3177 * If this is an Intel 21143 and we're not using the 3178 * MII port, program the LED control pins so we get 3179 * link and activity indications. 3180 */ 3181 if (sc->dc_flags & DC_TULIP_LEDS) { 3182 CSR_WRITE_4(sc, DC_WATCHDOG, 3183 DC_WDOG_CTLWREN|DC_WDOG_LINK|DC_WDOG_ACTIVITY); 3184 CSR_WRITE_4(sc, DC_WATCHDOG, 0); 3185 } 3186 3187 /* 3188 * Load the RX/multicast filter. We do this sort of late 3189 * because the filter programming scheme on the 21143 and 3190 * some clones requires DMAing a setup frame via the TX 3191 * engine, and we need the transmitter enabled for that. 3192 */ 3193 dc_setfilt(sc); 3194 3195 /* Enable receiver. */ 3196 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_ON); 3197 CSR_WRITE_4(sc, DC_RXSTART, 0xFFFFFFFF); 3198 3199 mii_mediachg(mii); 3200 dc_setcfg(sc, sc->dc_if_media); 3201 3202 ifp->if_flags |= IFF_RUNNING; 3203 ifp->if_flags &= ~IFF_OACTIVE; 3204 3205 /* Don't start the ticker if this is a homePNA link. */ 3206 if (IFM_SUBTYPE(mii->mii_media.ifm_media) == IFM_homePNA) 3207 sc->dc_link = 1; 3208 else { 3209 if (sc->dc_flags & DC_21143_NWAY) 3210 callout_reset(&sc->dc_stat_ch, hz/10, dc_tick, sc); 3211 else 3212 callout_reset(&sc->dc_stat_ch, hz, dc_tick, sc); 3213 } 3214 3215 #ifdef SRM_MEDIA 3216 if(sc->dc_srm_media) { 3217 struct ifreq ifr; 3218 3219 ifr.ifr_media = sc->dc_srm_media; 3220 ifmedia_ioctl(ifp, &ifr, &mii->mii_media, SIOCSIFMEDIA); 3221 sc->dc_srm_media = 0; 3222 } 3223 #endif 3224 DC_UNLOCK(sc); 3225 return; 3226 } 3227 3228 /* 3229 * Set media options. 3230 */ 3231 static int dc_ifmedia_upd(ifp) 3232 struct ifnet *ifp; 3233 { 3234 struct dc_softc *sc; 3235 struct mii_data *mii; 3236 struct ifmedia *ifm; 3237 3238 sc = ifp->if_softc; 3239 mii = device_get_softc(sc->dc_miibus); 3240 mii_mediachg(mii); 3241 ifm = &mii->mii_media; 3242 3243 if (DC_IS_DAVICOM(sc) && 3244 IFM_SUBTYPE(ifm->ifm_media) == IFM_homePNA) 3245 dc_setcfg(sc, ifm->ifm_media); 3246 else 3247 sc->dc_link = 0; 3248 3249 return(0); 3250 } 3251 3252 /* 3253 * Report current media status. 3254 */ 3255 static void dc_ifmedia_sts(ifp, ifmr) 3256 struct ifnet *ifp; 3257 struct ifmediareq *ifmr; 3258 { 3259 struct dc_softc *sc; 3260 struct mii_data *mii; 3261 struct ifmedia *ifm; 3262 3263 sc = ifp->if_softc; 3264 mii = device_get_softc(sc->dc_miibus); 3265 mii_pollstat(mii); 3266 ifm = &mii->mii_media; 3267 if (DC_IS_DAVICOM(sc)) { 3268 if (IFM_SUBTYPE(ifm->ifm_media) == IFM_homePNA) { 3269 ifmr->ifm_active = ifm->ifm_media; 3270 ifmr->ifm_status = 0; 3271 return; 3272 } 3273 } 3274 ifmr->ifm_active = mii->mii_media_active; 3275 ifmr->ifm_status = mii->mii_media_status; 3276 3277 return; 3278 } 3279 3280 static int dc_ioctl(ifp, command, data) 3281 struct ifnet *ifp; 3282 u_long command; 3283 caddr_t data; 3284 { 3285 struct dc_softc *sc = ifp->if_softc; 3286 struct ifreq *ifr = (struct ifreq *) data; 3287 struct mii_data *mii; 3288 int error = 0; 3289 3290 DC_LOCK(sc); 3291 3292 switch(command) { 3293 case SIOCSIFADDR: 3294 case SIOCGIFADDR: 3295 case SIOCSIFMTU: 3296 error = ether_ioctl(ifp, command, data); 3297 break; 3298 case SIOCSIFFLAGS: 3299 if (ifp->if_flags & IFF_UP) { 3300 if (ifp->if_flags & IFF_RUNNING && 3301 ifp->if_flags & IFF_PROMISC && 3302 !(sc->dc_if_flags & IFF_PROMISC)) { 3303 dc_setfilt(sc); 3304 } else if (ifp->if_flags & IFF_RUNNING && 3305 !(ifp->if_flags & IFF_PROMISC) && 3306 sc->dc_if_flags & IFF_PROMISC) { 3307 dc_setfilt(sc); 3308 } else if (!(ifp->if_flags & IFF_RUNNING)) { 3309 sc->dc_txthresh = 0; 3310 dc_init(sc); 3311 } 3312 } else { 3313 if (ifp->if_flags & IFF_RUNNING) 3314 dc_stop(sc); 3315 } 3316 sc->dc_if_flags = ifp->if_flags; 3317 error = 0; 3318 break; 3319 case SIOCADDMULTI: 3320 case SIOCDELMULTI: 3321 dc_setfilt(sc); 3322 error = 0; 3323 break; 3324 case SIOCGIFMEDIA: 3325 case SIOCSIFMEDIA: 3326 mii = device_get_softc(sc->dc_miibus); 3327 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 3328 #ifdef SRM_MEDIA 3329 if (sc->dc_srm_media) 3330 sc->dc_srm_media = 0; 3331 #endif 3332 break; 3333 default: 3334 error = EINVAL; 3335 break; 3336 } 3337 3338 DC_UNLOCK(sc); 3339 3340 return(error); 3341 } 3342 3343 static void dc_watchdog(ifp) 3344 struct ifnet *ifp; 3345 { 3346 struct dc_softc *sc; 3347 3348 sc = ifp->if_softc; 3349 3350 DC_LOCK(sc); 3351 3352 ifp->if_oerrors++; 3353 printf("dc%d: watchdog timeout\n", sc->dc_unit); 3354 3355 dc_stop(sc); 3356 dc_reset(sc); 3357 dc_init(sc); 3358 3359 if (ifp->if_snd.ifq_head != NULL) 3360 dc_start(ifp); 3361 3362 DC_UNLOCK(sc); 3363 3364 return; 3365 } 3366 3367 /* 3368 * Stop the adapter and free any mbufs allocated to the 3369 * RX and TX lists. 3370 */ 3371 static void dc_stop(sc) 3372 struct dc_softc *sc; 3373 { 3374 register int i; 3375 struct ifnet *ifp; 3376 3377 DC_LOCK(sc); 3378 3379 ifp = &sc->arpcom.ac_if; 3380 ifp->if_timer = 0; 3381 3382 callout_stop(&sc->dc_stat_ch); 3383 3384 DC_CLRBIT(sc, DC_NETCFG, (DC_NETCFG_RX_ON|DC_NETCFG_TX_ON)); 3385 CSR_WRITE_4(sc, DC_IMR, 0x00000000); 3386 CSR_WRITE_4(sc, DC_TXADDR, 0x00000000); 3387 CSR_WRITE_4(sc, DC_RXADDR, 0x00000000); 3388 sc->dc_link = 0; 3389 3390 /* 3391 * Free data in the RX lists. 3392 */ 3393 for (i = 0; i < DC_RX_LIST_CNT; i++) { 3394 if (sc->dc_cdata.dc_rx_chain[i] != NULL) { 3395 m_freem(sc->dc_cdata.dc_rx_chain[i]); 3396 sc->dc_cdata.dc_rx_chain[i] = NULL; 3397 } 3398 } 3399 bzero((char *)&sc->dc_ldata->dc_rx_list, 3400 sizeof(sc->dc_ldata->dc_rx_list)); 3401 3402 /* 3403 * Free the TX list buffers. 3404 */ 3405 for (i = 0; i < DC_TX_LIST_CNT; i++) { 3406 if (sc->dc_cdata.dc_tx_chain[i] != NULL) { 3407 if (sc->dc_ldata->dc_tx_list[i].dc_ctl & 3408 DC_TXCTL_SETUP) { 3409 sc->dc_cdata.dc_tx_chain[i] = NULL; 3410 continue; 3411 } 3412 m_freem(sc->dc_cdata.dc_tx_chain[i]); 3413 sc->dc_cdata.dc_tx_chain[i] = NULL; 3414 } 3415 } 3416 3417 bzero((char *)&sc->dc_ldata->dc_tx_list, 3418 sizeof(sc->dc_ldata->dc_tx_list)); 3419 3420 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 3421 3422 DC_UNLOCK(sc); 3423 3424 return; 3425 } 3426 3427 /* 3428 * Stop all chip I/O so that the kernel's probe routines don't 3429 * get confused by errant DMAs when rebooting. 3430 */ 3431 static void dc_shutdown(dev) 3432 device_t dev; 3433 { 3434 struct dc_softc *sc; 3435 3436 sc = device_get_softc(dev); 3437 3438 dc_stop(sc); 3439 3440 return; 3441 } 3442