1 /*- 2 * Copyright (c) 1997, 1998, 1999 3 * Bill Paul <wpaul@ee.columbia.edu>. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 3. All advertising materials mentioning features or use of this software 14 * must display the following acknowledgement: 15 * This product includes software developed by Bill Paul. 16 * 4. Neither the name of the author nor the names of any co-contributors 17 * may be used to endorse or promote products derived from this software 18 * without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30 * THE POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33 #include <sys/cdefs.h> 34 __FBSDID("$FreeBSD$"); 35 36 /* 37 * DEC "tulip" clone ethernet driver. Supports the DEC/Intel 21143 38 * series chips and several workalikes including the following: 39 * 40 * Macronix 98713/98715/98725/98727/98732 PMAC (www.macronix.com) 41 * Macronix/Lite-On 82c115 PNIC II (www.macronix.com) 42 * Lite-On 82c168/82c169 PNIC (www.litecom.com) 43 * ASIX Electronics AX88140A (www.asix.com.tw) 44 * ASIX Electronics AX88141 (www.asix.com.tw) 45 * ADMtek AL981 (www.admtek.com.tw) 46 * ADMtek AN985 (www.admtek.com.tw) 47 * Netgear FA511 (www.netgear.com) Appears to be rebadged ADMTek AN985 48 * Davicom DM9100, DM9102, DM9102A (www.davicom8.com) 49 * Accton EN1217 (www.accton.com) 50 * Xircom X3201 (www.xircom.com) 51 * Abocom FE2500 52 * Conexant LANfinity (www.conexant.com) 53 * 3Com OfficeConnect 10/100B 3CSOHO100B (www.3com.com) 54 * 55 * Datasheets for the 21143 are available at developer.intel.com. 56 * Datasheets for the clone parts can be found at their respective sites. 57 * (Except for the PNIC; see www.freebsd.org/~wpaul/PNIC/pnic.ps.gz.) 58 * The PNIC II is essentially a Macronix 98715A chip; the only difference 59 * worth noting is that its multicast hash table is only 128 bits wide 60 * instead of 512. 61 * 62 * Written by Bill Paul <wpaul@ee.columbia.edu> 63 * Electrical Engineering Department 64 * Columbia University, New York City 65 */ 66 /* 67 * The Intel 21143 is the successor to the DEC 21140. It is basically 68 * the same as the 21140 but with a few new features. The 21143 supports 69 * three kinds of media attachments: 70 * 71 * o MII port, for 10Mbps and 100Mbps support and NWAY 72 * autonegotiation provided by an external PHY. 73 * o SYM port, for symbol mode 100Mbps support. 74 * o 10baseT port. 75 * o AUI/BNC port. 76 * 77 * The 100Mbps SYM port and 10baseT port can be used together in 78 * combination with the internal NWAY support to create a 10/100 79 * autosensing configuration. 80 * 81 * Note that not all tulip workalikes are handled in this driver: we only 82 * deal with those which are relatively well behaved. The Winbond is 83 * handled separately due to its different register offsets and the 84 * special handling needed for its various bugs. The PNIC is handled 85 * here, but I'm not thrilled about it. 86 * 87 * All of the workalike chips use some form of MII transceiver support 88 * with the exception of the Macronix chips, which also have a SYM port. 89 * The ASIX AX88140A is also documented to have a SYM port, but all 90 * the cards I've seen use an MII transceiver, probably because the 91 * AX88140A doesn't support internal NWAY. 92 */ 93 94 #ifdef HAVE_KERNEL_OPTION_HEADERS 95 #include "opt_device_polling.h" 96 #endif 97 98 #include <sys/param.h> 99 #include <sys/endian.h> 100 #include <sys/systm.h> 101 #include <sys/sockio.h> 102 #include <sys/mbuf.h> 103 #include <sys/malloc.h> 104 #include <sys/kernel.h> 105 #include <sys/module.h> 106 #include <sys/socket.h> 107 #include <sys/sysctl.h> 108 109 #include <net/if.h> 110 #include <net/if_arp.h> 111 #include <net/ethernet.h> 112 #include <net/if_dl.h> 113 #include <net/if_media.h> 114 #include <net/if_types.h> 115 #include <net/if_vlan_var.h> 116 117 #include <net/bpf.h> 118 119 #include <machine/bus.h> 120 #include <machine/resource.h> 121 #include <sys/bus.h> 122 #include <sys/rman.h> 123 124 #include <dev/mii/mii.h> 125 #include <dev/mii/miivar.h> 126 127 #include <dev/pci/pcireg.h> 128 #include <dev/pci/pcivar.h> 129 130 #define DC_USEIOSPACE 131 #ifdef __alpha__ 132 #define SRM_MEDIA 133 #endif 134 135 #include <dev/dc/if_dcreg.h> 136 137 #ifdef __sparc64__ 138 #include <dev/ofw/openfirm.h> 139 #include <machine/ofw_machdep.h> 140 #endif 141 142 MODULE_DEPEND(dc, pci, 1, 1, 1); 143 MODULE_DEPEND(dc, ether, 1, 1, 1); 144 MODULE_DEPEND(dc, miibus, 1, 1, 1); 145 146 /* 147 * "device miibus" is required in kernel config. See GENERIC if you get 148 * errors here. 149 */ 150 #include "miibus_if.h" 151 152 /* 153 * Various supported device vendors/types and their names. 154 */ 155 static struct dc_type dc_devs[] = { 156 { DC_VENDORID_DEC, DC_DEVICEID_21143, 157 "Intel 21143 10/100BaseTX" }, 158 { DC_VENDORID_DAVICOM, DC_DEVICEID_DM9009, 159 "Davicom DM9009 10/100BaseTX" }, 160 { DC_VENDORID_DAVICOM, DC_DEVICEID_DM9100, 161 "Davicom DM9100 10/100BaseTX" }, 162 { DC_VENDORID_DAVICOM, DC_DEVICEID_DM9102, 163 "Davicom DM9102 10/100BaseTX" }, 164 { DC_VENDORID_DAVICOM, DC_DEVICEID_DM9102, 165 "Davicom DM9102A 10/100BaseTX" }, 166 { DC_VENDORID_ADMTEK, DC_DEVICEID_AL981, 167 "ADMtek AL981 10/100BaseTX" }, 168 { DC_VENDORID_ADMTEK, DC_DEVICEID_AN985, 169 "ADMtek AN985 10/100BaseTX" }, 170 { DC_VENDORID_ADMTEK, DC_DEVICEID_ADM9511, 171 "ADMtek ADM9511 10/100BaseTX" }, 172 { DC_VENDORID_ADMTEK, DC_DEVICEID_ADM9513, 173 "ADMtek ADM9513 10/100BaseTX" }, 174 { DC_VENDORID_ADMTEK, DC_DEVICEID_FA511, 175 "Netgear FA511 10/100BaseTX" }, 176 { DC_VENDORID_ASIX, DC_DEVICEID_AX88140A, 177 "ASIX AX88140A 10/100BaseTX" }, 178 { DC_VENDORID_ASIX, DC_DEVICEID_AX88140A, 179 "ASIX AX88141 10/100BaseTX" }, 180 { DC_VENDORID_MX, DC_DEVICEID_98713, 181 "Macronix 98713 10/100BaseTX" }, 182 { DC_VENDORID_MX, DC_DEVICEID_98713, 183 "Macronix 98713A 10/100BaseTX" }, 184 { DC_VENDORID_CP, DC_DEVICEID_98713_CP, 185 "Compex RL100-TX 10/100BaseTX" }, 186 { DC_VENDORID_CP, DC_DEVICEID_98713_CP, 187 "Compex RL100-TX 10/100BaseTX" }, 188 { DC_VENDORID_MX, DC_DEVICEID_987x5, 189 "Macronix 98715/98715A 10/100BaseTX" }, 190 { DC_VENDORID_MX, DC_DEVICEID_987x5, 191 "Macronix 98715AEC-C 10/100BaseTX" }, 192 { DC_VENDORID_MX, DC_DEVICEID_987x5, 193 "Macronix 98725 10/100BaseTX" }, 194 { DC_VENDORID_MX, DC_DEVICEID_98727, 195 "Macronix 98727/98732 10/100BaseTX" }, 196 { DC_VENDORID_LO, DC_DEVICEID_82C115, 197 "LC82C115 PNIC II 10/100BaseTX" }, 198 { DC_VENDORID_LO, DC_DEVICEID_82C168, 199 "82c168 PNIC 10/100BaseTX" }, 200 { DC_VENDORID_LO, DC_DEVICEID_82C168, 201 "82c169 PNIC 10/100BaseTX" }, 202 { DC_VENDORID_ACCTON, DC_DEVICEID_EN1217, 203 "Accton EN1217 10/100BaseTX" }, 204 { DC_VENDORID_ACCTON, DC_DEVICEID_EN2242, 205 "Accton EN2242 MiniPCI 10/100BaseTX" }, 206 { DC_VENDORID_XIRCOM, DC_DEVICEID_X3201, 207 "Xircom X3201 10/100BaseTX" }, 208 { DC_VENDORID_DLINK, DC_DEVICEID_DRP32TXD, 209 "Neteasy DRP-32TXD Cardbus 10/100" }, 210 { DC_VENDORID_ABOCOM, DC_DEVICEID_FE2500, 211 "Abocom FE2500 10/100BaseTX" }, 212 { DC_VENDORID_ABOCOM, DC_DEVICEID_FE2500MX, 213 "Abocom FE2500MX 10/100BaseTX" }, 214 { DC_VENDORID_CONEXANT, DC_DEVICEID_RS7112, 215 "Conexant LANfinity MiniPCI 10/100BaseTX" }, 216 { DC_VENDORID_HAWKING, DC_DEVICEID_HAWKING_PN672TX, 217 "Hawking CB102 CardBus 10/100" }, 218 { DC_VENDORID_PLANEX, DC_DEVICEID_FNW3602T, 219 "PlaneX FNW-3602-T CardBus 10/100" }, 220 { DC_VENDORID_3COM, DC_DEVICEID_3CSOHOB, 221 "3Com OfficeConnect 10/100B" }, 222 { DC_VENDORID_MICROSOFT, DC_DEVICEID_MSMN120, 223 "Microsoft MN-120 CardBus 10/100" }, 224 { DC_VENDORID_MICROSOFT, DC_DEVICEID_MSMN130, 225 "Microsoft MN-130 10/100" }, 226 { DC_VENDORID_MICROSOFT, DC_DEVICEID_MSMN130_FAKE, 227 "Microsoft MN-130 10/100" }, 228 { 0, 0, NULL } 229 }; 230 231 static int dc_probe(device_t); 232 static int dc_attach(device_t); 233 static int dc_detach(device_t); 234 static int dc_suspend(device_t); 235 static int dc_resume(device_t); 236 static struct dc_type *dc_devtype(device_t); 237 static int dc_newbuf(struct dc_softc *, int, int); 238 static int dc_encap(struct dc_softc *, struct mbuf **); 239 static void dc_pnic_rx_bug_war(struct dc_softc *, int); 240 static int dc_rx_resync(struct dc_softc *); 241 static void dc_rxeof(struct dc_softc *); 242 static void dc_txeof(struct dc_softc *); 243 static void dc_tick(void *); 244 static void dc_tx_underrun(struct dc_softc *); 245 static void dc_intr(void *); 246 static void dc_start(struct ifnet *); 247 static void dc_start_locked(struct ifnet *); 248 static int dc_ioctl(struct ifnet *, u_long, caddr_t); 249 static void dc_init(void *); 250 static void dc_init_locked(struct dc_softc *); 251 static void dc_stop(struct dc_softc *); 252 static void dc_watchdog(struct ifnet *); 253 static void dc_shutdown(device_t); 254 static int dc_ifmedia_upd(struct ifnet *); 255 static void dc_ifmedia_sts(struct ifnet *, struct ifmediareq *); 256 257 static void dc_delay(struct dc_softc *); 258 static void dc_eeprom_idle(struct dc_softc *); 259 static void dc_eeprom_putbyte(struct dc_softc *, int); 260 static void dc_eeprom_getword(struct dc_softc *, int, u_int16_t *); 261 static void dc_eeprom_getword_pnic(struct dc_softc *, int, u_int16_t *); 262 static void dc_eeprom_getword_xircom(struct dc_softc *, int, u_int16_t *); 263 static void dc_eeprom_width(struct dc_softc *); 264 static void dc_read_eeprom(struct dc_softc *, caddr_t, int, int, int); 265 266 static void dc_mii_writebit(struct dc_softc *, int); 267 static int dc_mii_readbit(struct dc_softc *); 268 static void dc_mii_sync(struct dc_softc *); 269 static void dc_mii_send(struct dc_softc *, u_int32_t, int); 270 static int dc_mii_readreg(struct dc_softc *, struct dc_mii_frame *); 271 static int dc_mii_writereg(struct dc_softc *, struct dc_mii_frame *); 272 static int dc_miibus_readreg(device_t, int, int); 273 static int dc_miibus_writereg(device_t, int, int, int); 274 static void dc_miibus_statchg(device_t); 275 static void dc_miibus_mediainit(device_t); 276 277 static void dc_setcfg(struct dc_softc *, int); 278 static uint32_t dc_mchash_le(struct dc_softc *, const uint8_t *); 279 static uint32_t dc_mchash_be(const uint8_t *); 280 static void dc_setfilt_21143(struct dc_softc *); 281 static void dc_setfilt_asix(struct dc_softc *); 282 static void dc_setfilt_admtek(struct dc_softc *); 283 static void dc_setfilt_xircom(struct dc_softc *); 284 285 static void dc_setfilt(struct dc_softc *); 286 287 static void dc_reset(struct dc_softc *); 288 static int dc_list_rx_init(struct dc_softc *); 289 static int dc_list_tx_init(struct dc_softc *); 290 291 static void dc_read_srom(struct dc_softc *, int); 292 static void dc_parse_21143_srom(struct dc_softc *); 293 static void dc_decode_leaf_sia(struct dc_softc *, struct dc_eblock_sia *); 294 static void dc_decode_leaf_mii(struct dc_softc *, struct dc_eblock_mii *); 295 static void dc_decode_leaf_sym(struct dc_softc *, struct dc_eblock_sym *); 296 static void dc_apply_fixup(struct dc_softc *, int); 297 298 static void dc_dma_map_txbuf(void *, bus_dma_segment_t *, int, bus_size_t, int); 299 static void dc_dma_map_rxbuf(void *, bus_dma_segment_t *, int, bus_size_t, int); 300 301 #ifdef DC_USEIOSPACE 302 #define DC_RES SYS_RES_IOPORT 303 #define DC_RID DC_PCI_CFBIO 304 #else 305 #define DC_RES SYS_RES_MEMORY 306 #define DC_RID DC_PCI_CFBMA 307 #endif 308 309 static device_method_t dc_methods[] = { 310 /* Device interface */ 311 DEVMETHOD(device_probe, dc_probe), 312 DEVMETHOD(device_attach, dc_attach), 313 DEVMETHOD(device_detach, dc_detach), 314 DEVMETHOD(device_suspend, dc_suspend), 315 DEVMETHOD(device_resume, dc_resume), 316 DEVMETHOD(device_shutdown, dc_shutdown), 317 318 /* bus interface */ 319 DEVMETHOD(bus_print_child, bus_generic_print_child), 320 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 321 322 /* MII interface */ 323 DEVMETHOD(miibus_readreg, dc_miibus_readreg), 324 DEVMETHOD(miibus_writereg, dc_miibus_writereg), 325 DEVMETHOD(miibus_statchg, dc_miibus_statchg), 326 DEVMETHOD(miibus_mediainit, dc_miibus_mediainit), 327 328 { 0, 0 } 329 }; 330 331 static driver_t dc_driver = { 332 "dc", 333 dc_methods, 334 sizeof(struct dc_softc) 335 }; 336 337 static devclass_t dc_devclass; 338 #ifdef __i386__ 339 static int dc_quick = 1; 340 SYSCTL_INT(_hw, OID_AUTO, dc_quick, CTLFLAG_RW, &dc_quick, 0, 341 "do not m_devget() in dc driver"); 342 #endif 343 344 DRIVER_MODULE(dc, cardbus, dc_driver, dc_devclass, 0, 0); 345 DRIVER_MODULE(dc, pci, dc_driver, dc_devclass, 0, 0); 346 DRIVER_MODULE(miibus, dc, miibus_driver, miibus_devclass, 0, 0); 347 348 #define DC_SETBIT(sc, reg, x) \ 349 CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) | (x)) 350 351 #define DC_CLRBIT(sc, reg, x) \ 352 CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) & ~(x)) 353 354 #define SIO_SET(x) DC_SETBIT(sc, DC_SIO, (x)) 355 #define SIO_CLR(x) DC_CLRBIT(sc, DC_SIO, (x)) 356 357 static void 358 dc_delay(struct dc_softc *sc) 359 { 360 int idx; 361 362 for (idx = (300 / 33) + 1; idx > 0; idx--) 363 CSR_READ_4(sc, DC_BUSCTL); 364 } 365 366 static void 367 dc_eeprom_width(struct dc_softc *sc) 368 { 369 int i; 370 371 /* Force EEPROM to idle state. */ 372 dc_eeprom_idle(sc); 373 374 /* Enter EEPROM access mode. */ 375 CSR_WRITE_4(sc, DC_SIO, DC_SIO_EESEL); 376 dc_delay(sc); 377 DC_SETBIT(sc, DC_SIO, DC_SIO_ROMCTL_READ); 378 dc_delay(sc); 379 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); 380 dc_delay(sc); 381 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CS); 382 dc_delay(sc); 383 384 for (i = 3; i--;) { 385 if (6 & (1 << i)) 386 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_DATAIN); 387 else 388 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_DATAIN); 389 dc_delay(sc); 390 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CLK); 391 dc_delay(sc); 392 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); 393 dc_delay(sc); 394 } 395 396 for (i = 1; i <= 12; i++) { 397 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CLK); 398 dc_delay(sc); 399 if (!(CSR_READ_4(sc, DC_SIO) & DC_SIO_EE_DATAOUT)) { 400 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); 401 dc_delay(sc); 402 break; 403 } 404 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); 405 dc_delay(sc); 406 } 407 408 /* Turn off EEPROM access mode. */ 409 dc_eeprom_idle(sc); 410 411 if (i < 4 || i > 12) 412 sc->dc_romwidth = 6; 413 else 414 sc->dc_romwidth = i; 415 416 /* Enter EEPROM access mode. */ 417 CSR_WRITE_4(sc, DC_SIO, DC_SIO_EESEL); 418 dc_delay(sc); 419 DC_SETBIT(sc, DC_SIO, DC_SIO_ROMCTL_READ); 420 dc_delay(sc); 421 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); 422 dc_delay(sc); 423 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CS); 424 dc_delay(sc); 425 426 /* Turn off EEPROM access mode. */ 427 dc_eeprom_idle(sc); 428 } 429 430 static void 431 dc_eeprom_idle(struct dc_softc *sc) 432 { 433 int i; 434 435 CSR_WRITE_4(sc, DC_SIO, DC_SIO_EESEL); 436 dc_delay(sc); 437 DC_SETBIT(sc, DC_SIO, DC_SIO_ROMCTL_READ); 438 dc_delay(sc); 439 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); 440 dc_delay(sc); 441 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CS); 442 dc_delay(sc); 443 444 for (i = 0; i < 25; i++) { 445 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); 446 dc_delay(sc); 447 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CLK); 448 dc_delay(sc); 449 } 450 451 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); 452 dc_delay(sc); 453 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CS); 454 dc_delay(sc); 455 CSR_WRITE_4(sc, DC_SIO, 0x00000000); 456 } 457 458 /* 459 * Send a read command and address to the EEPROM, check for ACK. 460 */ 461 static void 462 dc_eeprom_putbyte(struct dc_softc *sc, int addr) 463 { 464 int d, i; 465 466 d = DC_EECMD_READ >> 6; 467 for (i = 3; i--; ) { 468 if (d & (1 << i)) 469 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_DATAIN); 470 else 471 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_DATAIN); 472 dc_delay(sc); 473 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CLK); 474 dc_delay(sc); 475 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); 476 dc_delay(sc); 477 } 478 479 /* 480 * Feed in each bit and strobe the clock. 481 */ 482 for (i = sc->dc_romwidth; i--;) { 483 if (addr & (1 << i)) { 484 SIO_SET(DC_SIO_EE_DATAIN); 485 } else { 486 SIO_CLR(DC_SIO_EE_DATAIN); 487 } 488 dc_delay(sc); 489 SIO_SET(DC_SIO_EE_CLK); 490 dc_delay(sc); 491 SIO_CLR(DC_SIO_EE_CLK); 492 dc_delay(sc); 493 } 494 } 495 496 /* 497 * Read a word of data stored in the EEPROM at address 'addr.' 498 * The PNIC 82c168/82c169 has its own non-standard way to read 499 * the EEPROM. 500 */ 501 static void 502 dc_eeprom_getword_pnic(struct dc_softc *sc, int addr, u_int16_t *dest) 503 { 504 int i; 505 u_int32_t r; 506 507 CSR_WRITE_4(sc, DC_PN_SIOCTL, DC_PN_EEOPCODE_READ | addr); 508 509 for (i = 0; i < DC_TIMEOUT; i++) { 510 DELAY(1); 511 r = CSR_READ_4(sc, DC_SIO); 512 if (!(r & DC_PN_SIOCTL_BUSY)) { 513 *dest = (u_int16_t)(r & 0xFFFF); 514 return; 515 } 516 } 517 } 518 519 /* 520 * Read a word of data stored in the EEPROM at address 'addr.' 521 * The Xircom X3201 has its own non-standard way to read 522 * the EEPROM, too. 523 */ 524 static void 525 dc_eeprom_getword_xircom(struct dc_softc *sc, int addr, u_int16_t *dest) 526 { 527 528 SIO_SET(DC_SIO_ROMSEL | DC_SIO_ROMCTL_READ); 529 530 addr *= 2; 531 CSR_WRITE_4(sc, DC_ROM, addr | 0x160); 532 *dest = (u_int16_t)CSR_READ_4(sc, DC_SIO) & 0xff; 533 addr += 1; 534 CSR_WRITE_4(sc, DC_ROM, addr | 0x160); 535 *dest |= ((u_int16_t)CSR_READ_4(sc, DC_SIO) & 0xff) << 8; 536 537 SIO_CLR(DC_SIO_ROMSEL | DC_SIO_ROMCTL_READ); 538 } 539 540 /* 541 * Read a word of data stored in the EEPROM at address 'addr.' 542 */ 543 static void 544 dc_eeprom_getword(struct dc_softc *sc, int addr, u_int16_t *dest) 545 { 546 int i; 547 u_int16_t word = 0; 548 549 /* Force EEPROM to idle state. */ 550 dc_eeprom_idle(sc); 551 552 /* Enter EEPROM access mode. */ 553 CSR_WRITE_4(sc, DC_SIO, DC_SIO_EESEL); 554 dc_delay(sc); 555 DC_SETBIT(sc, DC_SIO, DC_SIO_ROMCTL_READ); 556 dc_delay(sc); 557 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); 558 dc_delay(sc); 559 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CS); 560 dc_delay(sc); 561 562 /* 563 * Send address of word we want to read. 564 */ 565 dc_eeprom_putbyte(sc, addr); 566 567 /* 568 * Start reading bits from EEPROM. 569 */ 570 for (i = 0x8000; i; i >>= 1) { 571 SIO_SET(DC_SIO_EE_CLK); 572 dc_delay(sc); 573 if (CSR_READ_4(sc, DC_SIO) & DC_SIO_EE_DATAOUT) 574 word |= i; 575 dc_delay(sc); 576 SIO_CLR(DC_SIO_EE_CLK); 577 dc_delay(sc); 578 } 579 580 /* Turn off EEPROM access mode. */ 581 dc_eeprom_idle(sc); 582 583 *dest = word; 584 } 585 586 /* 587 * Read a sequence of words from the EEPROM. 588 */ 589 static void 590 dc_read_eeprom(struct dc_softc *sc, caddr_t dest, int off, int cnt, int be) 591 { 592 int i; 593 u_int16_t word = 0, *ptr; 594 595 for (i = 0; i < cnt; i++) { 596 if (DC_IS_PNIC(sc)) 597 dc_eeprom_getword_pnic(sc, off + i, &word); 598 else if (DC_IS_XIRCOM(sc)) 599 dc_eeprom_getword_xircom(sc, off + i, &word); 600 else 601 dc_eeprom_getword(sc, off + i, &word); 602 ptr = (u_int16_t *)(dest + (i * 2)); 603 if (be) 604 *ptr = be16toh(word); 605 else 606 *ptr = le16toh(word); 607 } 608 } 609 610 /* 611 * The following two routines are taken from the Macronix 98713 612 * Application Notes pp.19-21. 613 */ 614 /* 615 * Write a bit to the MII bus. 616 */ 617 static void 618 dc_mii_writebit(struct dc_softc *sc, int bit) 619 { 620 621 if (bit) 622 CSR_WRITE_4(sc, DC_SIO, 623 DC_SIO_ROMCTL_WRITE | DC_SIO_MII_DATAOUT); 624 else 625 CSR_WRITE_4(sc, DC_SIO, DC_SIO_ROMCTL_WRITE); 626 627 DC_SETBIT(sc, DC_SIO, DC_SIO_MII_CLK); 628 DC_CLRBIT(sc, DC_SIO, DC_SIO_MII_CLK); 629 } 630 631 /* 632 * Read a bit from the MII bus. 633 */ 634 static int 635 dc_mii_readbit(struct dc_softc *sc) 636 { 637 638 CSR_WRITE_4(sc, DC_SIO, DC_SIO_ROMCTL_READ | DC_SIO_MII_DIR); 639 CSR_READ_4(sc, DC_SIO); 640 DC_SETBIT(sc, DC_SIO, DC_SIO_MII_CLK); 641 DC_CLRBIT(sc, DC_SIO, DC_SIO_MII_CLK); 642 if (CSR_READ_4(sc, DC_SIO) & DC_SIO_MII_DATAIN) 643 return (1); 644 645 return (0); 646 } 647 648 /* 649 * Sync the PHYs by setting data bit and strobing the clock 32 times. 650 */ 651 static void 652 dc_mii_sync(struct dc_softc *sc) 653 { 654 int i; 655 656 CSR_WRITE_4(sc, DC_SIO, DC_SIO_ROMCTL_WRITE); 657 658 for (i = 0; i < 32; i++) 659 dc_mii_writebit(sc, 1); 660 } 661 662 /* 663 * Clock a series of bits through the MII. 664 */ 665 static void 666 dc_mii_send(struct dc_softc *sc, u_int32_t bits, int cnt) 667 { 668 int i; 669 670 for (i = (0x1 << (cnt - 1)); i; i >>= 1) 671 dc_mii_writebit(sc, bits & i); 672 } 673 674 /* 675 * Read an PHY register through the MII. 676 */ 677 static int 678 dc_mii_readreg(struct dc_softc *sc, struct dc_mii_frame *frame) 679 { 680 int i, ack; 681 682 /* 683 * Set up frame for RX. 684 */ 685 frame->mii_stdelim = DC_MII_STARTDELIM; 686 frame->mii_opcode = DC_MII_READOP; 687 frame->mii_turnaround = 0; 688 frame->mii_data = 0; 689 690 /* 691 * Sync the PHYs. 692 */ 693 dc_mii_sync(sc); 694 695 /* 696 * Send command/address info. 697 */ 698 dc_mii_send(sc, frame->mii_stdelim, 2); 699 dc_mii_send(sc, frame->mii_opcode, 2); 700 dc_mii_send(sc, frame->mii_phyaddr, 5); 701 dc_mii_send(sc, frame->mii_regaddr, 5); 702 703 #ifdef notdef 704 /* Idle bit */ 705 dc_mii_writebit(sc, 1); 706 dc_mii_writebit(sc, 0); 707 #endif 708 709 /* Check for ack. */ 710 ack = dc_mii_readbit(sc); 711 712 /* 713 * Now try reading data bits. If the ack failed, we still 714 * need to clock through 16 cycles to keep the PHY(s) in sync. 715 */ 716 if (ack) { 717 for (i = 0; i < 16; i++) 718 dc_mii_readbit(sc); 719 goto fail; 720 } 721 722 for (i = 0x8000; i; i >>= 1) { 723 if (!ack) { 724 if (dc_mii_readbit(sc)) 725 frame->mii_data |= i; 726 } 727 } 728 729 fail: 730 731 dc_mii_writebit(sc, 0); 732 dc_mii_writebit(sc, 0); 733 734 if (ack) 735 return (1); 736 return (0); 737 } 738 739 /* 740 * Write to a PHY register through the MII. 741 */ 742 static int 743 dc_mii_writereg(struct dc_softc *sc, struct dc_mii_frame *frame) 744 { 745 746 /* 747 * Set up frame for TX. 748 */ 749 750 frame->mii_stdelim = DC_MII_STARTDELIM; 751 frame->mii_opcode = DC_MII_WRITEOP; 752 frame->mii_turnaround = DC_MII_TURNAROUND; 753 754 /* 755 * Sync the PHYs. 756 */ 757 dc_mii_sync(sc); 758 759 dc_mii_send(sc, frame->mii_stdelim, 2); 760 dc_mii_send(sc, frame->mii_opcode, 2); 761 dc_mii_send(sc, frame->mii_phyaddr, 5); 762 dc_mii_send(sc, frame->mii_regaddr, 5); 763 dc_mii_send(sc, frame->mii_turnaround, 2); 764 dc_mii_send(sc, frame->mii_data, 16); 765 766 /* Idle bit. */ 767 dc_mii_writebit(sc, 0); 768 dc_mii_writebit(sc, 0); 769 770 return (0); 771 } 772 773 static int 774 dc_miibus_readreg(device_t dev, int phy, int reg) 775 { 776 struct dc_mii_frame frame; 777 struct dc_softc *sc; 778 int i, rval, phy_reg = 0; 779 780 sc = device_get_softc(dev); 781 bzero(&frame, sizeof(frame)); 782 783 /* 784 * Note: both the AL981 and AN985 have internal PHYs, 785 * however the AL981 provides direct access to the PHY 786 * registers while the AN985 uses a serial MII interface. 787 * The AN985's MII interface is also buggy in that you 788 * can read from any MII address (0 to 31), but only address 1 789 * behaves normally. To deal with both cases, we pretend 790 * that the PHY is at MII address 1. 791 */ 792 if (DC_IS_ADMTEK(sc) && phy != DC_ADMTEK_PHYADDR) 793 return (0); 794 795 /* 796 * Note: the ukphy probes of the RS7112 report a PHY at 797 * MII address 0 (possibly HomePNA?) and 1 (ethernet) 798 * so we only respond to correct one. 799 */ 800 if (DC_IS_CONEXANT(sc) && phy != DC_CONEXANT_PHYADDR) 801 return (0); 802 803 if (sc->dc_pmode != DC_PMODE_MII) { 804 if (phy == (MII_NPHY - 1)) { 805 switch (reg) { 806 case MII_BMSR: 807 /* 808 * Fake something to make the probe 809 * code think there's a PHY here. 810 */ 811 return (BMSR_MEDIAMASK); 812 break; 813 case MII_PHYIDR1: 814 if (DC_IS_PNIC(sc)) 815 return (DC_VENDORID_LO); 816 return (DC_VENDORID_DEC); 817 break; 818 case MII_PHYIDR2: 819 if (DC_IS_PNIC(sc)) 820 return (DC_DEVICEID_82C168); 821 return (DC_DEVICEID_21143); 822 break; 823 default: 824 return (0); 825 break; 826 } 827 } else 828 return (0); 829 } 830 831 if (DC_IS_PNIC(sc)) { 832 CSR_WRITE_4(sc, DC_PN_MII, DC_PN_MIIOPCODE_READ | 833 (phy << 23) | (reg << 18)); 834 for (i = 0; i < DC_TIMEOUT; i++) { 835 DELAY(1); 836 rval = CSR_READ_4(sc, DC_PN_MII); 837 if (!(rval & DC_PN_MII_BUSY)) { 838 rval &= 0xFFFF; 839 return (rval == 0xFFFF ? 0 : rval); 840 } 841 } 842 return (0); 843 } 844 845 if (DC_IS_COMET(sc)) { 846 switch (reg) { 847 case MII_BMCR: 848 phy_reg = DC_AL_BMCR; 849 break; 850 case MII_BMSR: 851 phy_reg = DC_AL_BMSR; 852 break; 853 case MII_PHYIDR1: 854 phy_reg = DC_AL_VENID; 855 break; 856 case MII_PHYIDR2: 857 phy_reg = DC_AL_DEVID; 858 break; 859 case MII_ANAR: 860 phy_reg = DC_AL_ANAR; 861 break; 862 case MII_ANLPAR: 863 phy_reg = DC_AL_LPAR; 864 break; 865 case MII_ANER: 866 phy_reg = DC_AL_ANER; 867 break; 868 default: 869 device_printf(dev, "phy_read: bad phy register %x\n", 870 reg); 871 return (0); 872 break; 873 } 874 875 rval = CSR_READ_4(sc, phy_reg) & 0x0000FFFF; 876 877 if (rval == 0xFFFF) 878 return (0); 879 return (rval); 880 } 881 882 frame.mii_phyaddr = phy; 883 frame.mii_regaddr = reg; 884 if (sc->dc_type == DC_TYPE_98713) { 885 phy_reg = CSR_READ_4(sc, DC_NETCFG); 886 CSR_WRITE_4(sc, DC_NETCFG, phy_reg & ~DC_NETCFG_PORTSEL); 887 } 888 dc_mii_readreg(sc, &frame); 889 if (sc->dc_type == DC_TYPE_98713) 890 CSR_WRITE_4(sc, DC_NETCFG, phy_reg); 891 892 return (frame.mii_data); 893 } 894 895 static int 896 dc_miibus_writereg(device_t dev, int phy, int reg, int data) 897 { 898 struct dc_softc *sc; 899 struct dc_mii_frame frame; 900 int i, phy_reg = 0; 901 902 sc = device_get_softc(dev); 903 bzero(&frame, sizeof(frame)); 904 905 if (DC_IS_ADMTEK(sc) && phy != DC_ADMTEK_PHYADDR) 906 return (0); 907 908 if (DC_IS_CONEXANT(sc) && phy != DC_CONEXANT_PHYADDR) 909 return (0); 910 911 if (DC_IS_PNIC(sc)) { 912 CSR_WRITE_4(sc, DC_PN_MII, DC_PN_MIIOPCODE_WRITE | 913 (phy << 23) | (reg << 10) | data); 914 for (i = 0; i < DC_TIMEOUT; i++) { 915 if (!(CSR_READ_4(sc, DC_PN_MII) & DC_PN_MII_BUSY)) 916 break; 917 } 918 return (0); 919 } 920 921 if (DC_IS_COMET(sc)) { 922 switch (reg) { 923 case MII_BMCR: 924 phy_reg = DC_AL_BMCR; 925 break; 926 case MII_BMSR: 927 phy_reg = DC_AL_BMSR; 928 break; 929 case MII_PHYIDR1: 930 phy_reg = DC_AL_VENID; 931 break; 932 case MII_PHYIDR2: 933 phy_reg = DC_AL_DEVID; 934 break; 935 case MII_ANAR: 936 phy_reg = DC_AL_ANAR; 937 break; 938 case MII_ANLPAR: 939 phy_reg = DC_AL_LPAR; 940 break; 941 case MII_ANER: 942 phy_reg = DC_AL_ANER; 943 break; 944 default: 945 device_printf(dev, "phy_write: bad phy register %x\n", 946 reg); 947 return (0); 948 break; 949 } 950 951 CSR_WRITE_4(sc, phy_reg, data); 952 return (0); 953 } 954 955 frame.mii_phyaddr = phy; 956 frame.mii_regaddr = reg; 957 frame.mii_data = data; 958 959 if (sc->dc_type == DC_TYPE_98713) { 960 phy_reg = CSR_READ_4(sc, DC_NETCFG); 961 CSR_WRITE_4(sc, DC_NETCFG, phy_reg & ~DC_NETCFG_PORTSEL); 962 } 963 dc_mii_writereg(sc, &frame); 964 if (sc->dc_type == DC_TYPE_98713) 965 CSR_WRITE_4(sc, DC_NETCFG, phy_reg); 966 967 return (0); 968 } 969 970 static void 971 dc_miibus_statchg(device_t dev) 972 { 973 struct dc_softc *sc; 974 struct mii_data *mii; 975 struct ifmedia *ifm; 976 977 sc = device_get_softc(dev); 978 if (DC_IS_ADMTEK(sc)) 979 return; 980 981 mii = device_get_softc(sc->dc_miibus); 982 ifm = &mii->mii_media; 983 if (DC_IS_DAVICOM(sc) && 984 IFM_SUBTYPE(ifm->ifm_media) == IFM_HPNA_1) { 985 dc_setcfg(sc, ifm->ifm_media); 986 sc->dc_if_media = ifm->ifm_media; 987 } else { 988 dc_setcfg(sc, mii->mii_media_active); 989 sc->dc_if_media = mii->mii_media_active; 990 } 991 } 992 993 /* 994 * Special support for DM9102A cards with HomePNA PHYs. Note: 995 * with the Davicom DM9102A/DM9801 eval board that I have, it seems 996 * to be impossible to talk to the management interface of the DM9801 997 * PHY (its MDIO pin is not connected to anything). Consequently, 998 * the driver has to just 'know' about the additional mode and deal 999 * with it itself. *sigh* 1000 */ 1001 static void 1002 dc_miibus_mediainit(device_t dev) 1003 { 1004 struct dc_softc *sc; 1005 struct mii_data *mii; 1006 struct ifmedia *ifm; 1007 int rev; 1008 1009 rev = pci_read_config(dev, DC_PCI_CFRV, 4) & 0xFF; 1010 1011 sc = device_get_softc(dev); 1012 mii = device_get_softc(sc->dc_miibus); 1013 ifm = &mii->mii_media; 1014 1015 if (DC_IS_DAVICOM(sc) && rev >= DC_REVISION_DM9102A) 1016 ifmedia_add(ifm, IFM_ETHER | IFM_HPNA_1, 0, NULL); 1017 } 1018 1019 #define DC_BITS_512 9 1020 #define DC_BITS_128 7 1021 #define DC_BITS_64 6 1022 1023 static uint32_t 1024 dc_mchash_le(struct dc_softc *sc, const uint8_t *addr) 1025 { 1026 uint32_t crc; 1027 1028 /* Compute CRC for the address value. */ 1029 crc = ether_crc32_le(addr, ETHER_ADDR_LEN); 1030 1031 /* 1032 * The hash table on the PNIC II and the MX98715AEC-C/D/E 1033 * chips is only 128 bits wide. 1034 */ 1035 if (sc->dc_flags & DC_128BIT_HASH) 1036 return (crc & ((1 << DC_BITS_128) - 1)); 1037 1038 /* The hash table on the MX98715BEC is only 64 bits wide. */ 1039 if (sc->dc_flags & DC_64BIT_HASH) 1040 return (crc & ((1 << DC_BITS_64) - 1)); 1041 1042 /* Xircom's hash filtering table is different (read: weird) */ 1043 /* Xircom uses the LEAST significant bits */ 1044 if (DC_IS_XIRCOM(sc)) { 1045 if ((crc & 0x180) == 0x180) 1046 return ((crc & 0x0F) + (crc & 0x70) * 3 + (14 << 4)); 1047 else 1048 return ((crc & 0x1F) + ((crc >> 1) & 0xF0) * 3 + 1049 (12 << 4)); 1050 } 1051 1052 return (crc & ((1 << DC_BITS_512) - 1)); 1053 } 1054 1055 /* 1056 * Calculate CRC of a multicast group address, return the lower 6 bits. 1057 */ 1058 static uint32_t 1059 dc_mchash_be(const uint8_t *addr) 1060 { 1061 uint32_t crc; 1062 1063 /* Compute CRC for the address value. */ 1064 crc = ether_crc32_be(addr, ETHER_ADDR_LEN); 1065 1066 /* Return the filter bit position. */ 1067 return ((crc >> 26) & 0x0000003F); 1068 } 1069 1070 /* 1071 * 21143-style RX filter setup routine. Filter programming is done by 1072 * downloading a special setup frame into the TX engine. 21143, Macronix, 1073 * PNIC, PNIC II and Davicom chips are programmed this way. 1074 * 1075 * We always program the chip using 'hash perfect' mode, i.e. one perfect 1076 * address (our node address) and a 512-bit hash filter for multicast 1077 * frames. We also sneak the broadcast address into the hash filter since 1078 * we need that too. 1079 */ 1080 static void 1081 dc_setfilt_21143(struct dc_softc *sc) 1082 { 1083 uint16_t eaddr[(ETHER_ADDR_LEN+1)/2]; 1084 struct dc_desc *sframe; 1085 u_int32_t h, *sp; 1086 struct ifmultiaddr *ifma; 1087 struct ifnet *ifp; 1088 int i; 1089 1090 ifp = sc->dc_ifp; 1091 1092 i = sc->dc_cdata.dc_tx_prod; 1093 DC_INC(sc->dc_cdata.dc_tx_prod, DC_TX_LIST_CNT); 1094 sc->dc_cdata.dc_tx_cnt++; 1095 sframe = &sc->dc_ldata->dc_tx_list[i]; 1096 sp = sc->dc_cdata.dc_sbuf; 1097 bzero(sp, DC_SFRAME_LEN); 1098 1099 sframe->dc_data = htole32(sc->dc_saddr); 1100 sframe->dc_ctl = htole32(DC_SFRAME_LEN | DC_TXCTL_SETUP | 1101 DC_TXCTL_TLINK | DC_FILTER_HASHPERF | DC_TXCTL_FINT); 1102 1103 sc->dc_cdata.dc_tx_chain[i] = (struct mbuf *)sc->dc_cdata.dc_sbuf; 1104 1105 /* If we want promiscuous mode, set the allframes bit. */ 1106 if (ifp->if_flags & IFF_PROMISC) 1107 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC); 1108 else 1109 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC); 1110 1111 if (ifp->if_flags & IFF_ALLMULTI) 1112 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI); 1113 else 1114 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI); 1115 1116 IF_ADDR_LOCK(ifp); 1117 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 1118 if (ifma->ifma_addr->sa_family != AF_LINK) 1119 continue; 1120 h = dc_mchash_le(sc, 1121 LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 1122 sp[h >> 4] |= htole32(1 << (h & 0xF)); 1123 } 1124 IF_ADDR_UNLOCK(ifp); 1125 1126 if (ifp->if_flags & IFF_BROADCAST) { 1127 h = dc_mchash_le(sc, ifp->if_broadcastaddr); 1128 sp[h >> 4] |= htole32(1 << (h & 0xF)); 1129 } 1130 1131 /* Set our MAC address. */ 1132 bcopy(IF_LLADDR(sc->dc_ifp), eaddr, ETHER_ADDR_LEN); 1133 sp[39] = DC_SP_MAC(eaddr[0]); 1134 sp[40] = DC_SP_MAC(eaddr[1]); 1135 sp[41] = DC_SP_MAC(eaddr[2]); 1136 1137 sframe->dc_status = htole32(DC_TXSTAT_OWN); 1138 CSR_WRITE_4(sc, DC_TXSTART, 0xFFFFFFFF); 1139 1140 /* 1141 * The PNIC takes an exceedingly long time to process its 1142 * setup frame; wait 10ms after posting the setup frame 1143 * before proceeding, just so it has time to swallow its 1144 * medicine. 1145 */ 1146 DELAY(10000); 1147 1148 ifp->if_timer = 5; 1149 } 1150 1151 static void 1152 dc_setfilt_admtek(struct dc_softc *sc) 1153 { 1154 uint32_t eaddr[(ETHER_ADDR_LEN+3)/4]; 1155 struct ifnet *ifp; 1156 struct ifmultiaddr *ifma; 1157 int h = 0; 1158 u_int32_t hashes[2] = { 0, 0 }; 1159 1160 ifp = sc->dc_ifp; 1161 1162 /* Init our MAC address. */ 1163 bcopy(IF_LLADDR(sc->dc_ifp), eaddr, ETHER_ADDR_LEN); 1164 CSR_WRITE_4(sc, DC_AL_PAR0, eaddr[0]); 1165 CSR_WRITE_4(sc, DC_AL_PAR1, eaddr[1]); 1166 1167 /* If we want promiscuous mode, set the allframes bit. */ 1168 if (ifp->if_flags & IFF_PROMISC) 1169 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC); 1170 else 1171 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC); 1172 1173 if (ifp->if_flags & IFF_ALLMULTI) 1174 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI); 1175 else 1176 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI); 1177 1178 /* First, zot all the existing hash bits. */ 1179 CSR_WRITE_4(sc, DC_AL_MAR0, 0); 1180 CSR_WRITE_4(sc, DC_AL_MAR1, 0); 1181 1182 /* 1183 * If we're already in promisc or allmulti mode, we 1184 * don't have to bother programming the multicast filter. 1185 */ 1186 if (ifp->if_flags & (IFF_PROMISC | IFF_ALLMULTI)) 1187 return; 1188 1189 /* Now program new ones. */ 1190 IF_ADDR_LOCK(ifp); 1191 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 1192 if (ifma->ifma_addr->sa_family != AF_LINK) 1193 continue; 1194 if (DC_IS_CENTAUR(sc)) 1195 h = dc_mchash_le(sc, 1196 LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 1197 else 1198 h = dc_mchash_be( 1199 LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 1200 if (h < 32) 1201 hashes[0] |= (1 << h); 1202 else 1203 hashes[1] |= (1 << (h - 32)); 1204 } 1205 IF_ADDR_UNLOCK(ifp); 1206 1207 CSR_WRITE_4(sc, DC_AL_MAR0, hashes[0]); 1208 CSR_WRITE_4(sc, DC_AL_MAR1, hashes[1]); 1209 } 1210 1211 static void 1212 dc_setfilt_asix(struct dc_softc *sc) 1213 { 1214 uint32_t eaddr[(ETHER_ADDR_LEN+3)/4]; 1215 struct ifnet *ifp; 1216 struct ifmultiaddr *ifma; 1217 int h = 0; 1218 u_int32_t hashes[2] = { 0, 0 }; 1219 1220 ifp = sc->dc_ifp; 1221 1222 /* Init our MAC address. */ 1223 bcopy(IF_LLADDR(sc->dc_ifp), eaddr, ETHER_ADDR_LEN); 1224 CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_PAR0); 1225 CSR_WRITE_4(sc, DC_AX_FILTDATA, eaddr[0]); 1226 CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_PAR1); 1227 CSR_WRITE_4(sc, DC_AX_FILTDATA, eaddr[1]); 1228 1229 /* If we want promiscuous mode, set the allframes bit. */ 1230 if (ifp->if_flags & IFF_PROMISC) 1231 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC); 1232 else 1233 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC); 1234 1235 if (ifp->if_flags & IFF_ALLMULTI) 1236 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI); 1237 else 1238 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI); 1239 1240 /* 1241 * The ASIX chip has a special bit to enable reception 1242 * of broadcast frames. 1243 */ 1244 if (ifp->if_flags & IFF_BROADCAST) 1245 DC_SETBIT(sc, DC_NETCFG, DC_AX_NETCFG_RX_BROAD); 1246 else 1247 DC_CLRBIT(sc, DC_NETCFG, DC_AX_NETCFG_RX_BROAD); 1248 1249 /* first, zot all the existing hash bits */ 1250 CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_MAR0); 1251 CSR_WRITE_4(sc, DC_AX_FILTDATA, 0); 1252 CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_MAR1); 1253 CSR_WRITE_4(sc, DC_AX_FILTDATA, 0); 1254 1255 /* 1256 * If we're already in promisc or allmulti mode, we 1257 * don't have to bother programming the multicast filter. 1258 */ 1259 if (ifp->if_flags & (IFF_PROMISC | IFF_ALLMULTI)) 1260 return; 1261 1262 /* now program new ones */ 1263 IF_ADDR_LOCK(ifp); 1264 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 1265 if (ifma->ifma_addr->sa_family != AF_LINK) 1266 continue; 1267 h = dc_mchash_be(LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 1268 if (h < 32) 1269 hashes[0] |= (1 << h); 1270 else 1271 hashes[1] |= (1 << (h - 32)); 1272 } 1273 IF_ADDR_UNLOCK(ifp); 1274 1275 CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_MAR0); 1276 CSR_WRITE_4(sc, DC_AX_FILTDATA, hashes[0]); 1277 CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_MAR1); 1278 CSR_WRITE_4(sc, DC_AX_FILTDATA, hashes[1]); 1279 } 1280 1281 static void 1282 dc_setfilt_xircom(struct dc_softc *sc) 1283 { 1284 uint16_t eaddr[(ETHER_ADDR_LEN+1)/2]; 1285 struct ifnet *ifp; 1286 struct ifmultiaddr *ifma; 1287 struct dc_desc *sframe; 1288 u_int32_t h, *sp; 1289 int i; 1290 1291 ifp = sc->dc_ifp; 1292 DC_CLRBIT(sc, DC_NETCFG, (DC_NETCFG_TX_ON | DC_NETCFG_RX_ON)); 1293 1294 i = sc->dc_cdata.dc_tx_prod; 1295 DC_INC(sc->dc_cdata.dc_tx_prod, DC_TX_LIST_CNT); 1296 sc->dc_cdata.dc_tx_cnt++; 1297 sframe = &sc->dc_ldata->dc_tx_list[i]; 1298 sp = sc->dc_cdata.dc_sbuf; 1299 bzero(sp, DC_SFRAME_LEN); 1300 1301 sframe->dc_data = htole32(sc->dc_saddr); 1302 sframe->dc_ctl = htole32(DC_SFRAME_LEN | DC_TXCTL_SETUP | 1303 DC_TXCTL_TLINK | DC_FILTER_HASHPERF | DC_TXCTL_FINT); 1304 1305 sc->dc_cdata.dc_tx_chain[i] = (struct mbuf *)sc->dc_cdata.dc_sbuf; 1306 1307 /* If we want promiscuous mode, set the allframes bit. */ 1308 if (ifp->if_flags & IFF_PROMISC) 1309 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC); 1310 else 1311 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC); 1312 1313 if (ifp->if_flags & IFF_ALLMULTI) 1314 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI); 1315 else 1316 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI); 1317 1318 IF_ADDR_LOCK(ifp); 1319 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 1320 if (ifma->ifma_addr->sa_family != AF_LINK) 1321 continue; 1322 h = dc_mchash_le(sc, 1323 LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 1324 sp[h >> 4] |= htole32(1 << (h & 0xF)); 1325 } 1326 IF_ADDR_UNLOCK(ifp); 1327 1328 if (ifp->if_flags & IFF_BROADCAST) { 1329 h = dc_mchash_le(sc, ifp->if_broadcastaddr); 1330 sp[h >> 4] |= htole32(1 << (h & 0xF)); 1331 } 1332 1333 /* Set our MAC address. */ 1334 bcopy(IF_LLADDR(sc->dc_ifp), eaddr, ETHER_ADDR_LEN); 1335 sp[0] = DC_SP_MAC(eaddr[0]); 1336 sp[1] = DC_SP_MAC(eaddr[1]); 1337 sp[2] = DC_SP_MAC(eaddr[2]); 1338 1339 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_TX_ON); 1340 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_ON); 1341 ifp->if_drv_flags |= IFF_DRV_RUNNING; 1342 sframe->dc_status = htole32(DC_TXSTAT_OWN); 1343 CSR_WRITE_4(sc, DC_TXSTART, 0xFFFFFFFF); 1344 1345 /* 1346 * Wait some time... 1347 */ 1348 DELAY(1000); 1349 1350 ifp->if_timer = 5; 1351 } 1352 1353 static void 1354 dc_setfilt(struct dc_softc *sc) 1355 { 1356 1357 if (DC_IS_INTEL(sc) || DC_IS_MACRONIX(sc) || DC_IS_PNIC(sc) || 1358 DC_IS_PNICII(sc) || DC_IS_DAVICOM(sc) || DC_IS_CONEXANT(sc)) 1359 dc_setfilt_21143(sc); 1360 1361 if (DC_IS_ASIX(sc)) 1362 dc_setfilt_asix(sc); 1363 1364 if (DC_IS_ADMTEK(sc)) 1365 dc_setfilt_admtek(sc); 1366 1367 if (DC_IS_XIRCOM(sc)) 1368 dc_setfilt_xircom(sc); 1369 } 1370 1371 /* 1372 * In order to fiddle with the 'full-duplex' and '100Mbps' bits in 1373 * the netconfig register, we first have to put the transmit and/or 1374 * receive logic in the idle state. 1375 */ 1376 static void 1377 dc_setcfg(struct dc_softc *sc, int media) 1378 { 1379 int i, restart = 0, watchdogreg; 1380 u_int32_t isr; 1381 1382 if (IFM_SUBTYPE(media) == IFM_NONE) 1383 return; 1384 1385 if (CSR_READ_4(sc, DC_NETCFG) & (DC_NETCFG_TX_ON | DC_NETCFG_RX_ON)) { 1386 restart = 1; 1387 DC_CLRBIT(sc, DC_NETCFG, (DC_NETCFG_TX_ON | DC_NETCFG_RX_ON)); 1388 1389 for (i = 0; i < DC_TIMEOUT; i++) { 1390 isr = CSR_READ_4(sc, DC_ISR); 1391 if (isr & DC_ISR_TX_IDLE && 1392 ((isr & DC_ISR_RX_STATE) == DC_RXSTATE_STOPPED || 1393 (isr & DC_ISR_RX_STATE) == DC_RXSTATE_WAIT)) 1394 break; 1395 DELAY(10); 1396 } 1397 1398 if (i == DC_TIMEOUT) 1399 if_printf(sc->dc_ifp, 1400 "failed to force tx and rx to idle state\n"); 1401 } 1402 1403 if (IFM_SUBTYPE(media) == IFM_100_TX) { 1404 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_SPEEDSEL); 1405 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_HEARTBEAT); 1406 if (sc->dc_pmode == DC_PMODE_MII) { 1407 if (DC_IS_INTEL(sc)) { 1408 /* There's a write enable bit here that reads as 1. */ 1409 watchdogreg = CSR_READ_4(sc, DC_WATCHDOG); 1410 watchdogreg &= ~DC_WDOG_CTLWREN; 1411 watchdogreg |= DC_WDOG_JABBERDIS; 1412 CSR_WRITE_4(sc, DC_WATCHDOG, watchdogreg); 1413 } else { 1414 DC_SETBIT(sc, DC_WATCHDOG, DC_WDOG_JABBERDIS); 1415 } 1416 DC_CLRBIT(sc, DC_NETCFG, (DC_NETCFG_PCS | 1417 DC_NETCFG_PORTSEL | DC_NETCFG_SCRAMBLER)); 1418 if (sc->dc_type == DC_TYPE_98713) 1419 DC_SETBIT(sc, DC_NETCFG, (DC_NETCFG_PCS | 1420 DC_NETCFG_SCRAMBLER)); 1421 if (!DC_IS_DAVICOM(sc)) 1422 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL); 1423 DC_CLRBIT(sc, DC_10BTCTRL, 0xFFFF); 1424 if (DC_IS_INTEL(sc)) 1425 dc_apply_fixup(sc, IFM_AUTO); 1426 } else { 1427 if (DC_IS_PNIC(sc)) { 1428 DC_PN_GPIO_SETBIT(sc, DC_PN_GPIO_SPEEDSEL); 1429 DC_PN_GPIO_SETBIT(sc, DC_PN_GPIO_100TX_LOOP); 1430 DC_SETBIT(sc, DC_PN_NWAY, DC_PN_NWAY_SPEEDSEL); 1431 } 1432 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL); 1433 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PCS); 1434 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_SCRAMBLER); 1435 if (DC_IS_INTEL(sc)) 1436 dc_apply_fixup(sc, 1437 (media & IFM_GMASK) == IFM_FDX ? 1438 IFM_100_TX | IFM_FDX : IFM_100_TX); 1439 } 1440 } 1441 1442 if (IFM_SUBTYPE(media) == IFM_10_T) { 1443 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_SPEEDSEL); 1444 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_HEARTBEAT); 1445 if (sc->dc_pmode == DC_PMODE_MII) { 1446 /* There's a write enable bit here that reads as 1. */ 1447 if (DC_IS_INTEL(sc)) { 1448 watchdogreg = CSR_READ_4(sc, DC_WATCHDOG); 1449 watchdogreg &= ~DC_WDOG_CTLWREN; 1450 watchdogreg |= DC_WDOG_JABBERDIS; 1451 CSR_WRITE_4(sc, DC_WATCHDOG, watchdogreg); 1452 } else { 1453 DC_SETBIT(sc, DC_WATCHDOG, DC_WDOG_JABBERDIS); 1454 } 1455 DC_CLRBIT(sc, DC_NETCFG, (DC_NETCFG_PCS | 1456 DC_NETCFG_PORTSEL | DC_NETCFG_SCRAMBLER)); 1457 if (sc->dc_type == DC_TYPE_98713) 1458 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PCS); 1459 if (!DC_IS_DAVICOM(sc)) 1460 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL); 1461 DC_CLRBIT(sc, DC_10BTCTRL, 0xFFFF); 1462 if (DC_IS_INTEL(sc)) 1463 dc_apply_fixup(sc, IFM_AUTO); 1464 } else { 1465 if (DC_IS_PNIC(sc)) { 1466 DC_PN_GPIO_CLRBIT(sc, DC_PN_GPIO_SPEEDSEL); 1467 DC_PN_GPIO_SETBIT(sc, DC_PN_GPIO_100TX_LOOP); 1468 DC_CLRBIT(sc, DC_PN_NWAY, DC_PN_NWAY_SPEEDSEL); 1469 } 1470 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL); 1471 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_PCS); 1472 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_SCRAMBLER); 1473 if (DC_IS_INTEL(sc)) { 1474 DC_CLRBIT(sc, DC_SIARESET, DC_SIA_RESET); 1475 DC_CLRBIT(sc, DC_10BTCTRL, 0xFFFF); 1476 if ((media & IFM_GMASK) == IFM_FDX) 1477 DC_SETBIT(sc, DC_10BTCTRL, 0x7F3D); 1478 else 1479 DC_SETBIT(sc, DC_10BTCTRL, 0x7F3F); 1480 DC_SETBIT(sc, DC_SIARESET, DC_SIA_RESET); 1481 DC_CLRBIT(sc, DC_10BTCTRL, 1482 DC_TCTL_AUTONEGENBL); 1483 dc_apply_fixup(sc, 1484 (media & IFM_GMASK) == IFM_FDX ? 1485 IFM_10_T | IFM_FDX : IFM_10_T); 1486 DELAY(20000); 1487 } 1488 } 1489 } 1490 1491 /* 1492 * If this is a Davicom DM9102A card with a DM9801 HomePNA 1493 * PHY and we want HomePNA mode, set the portsel bit to turn 1494 * on the external MII port. 1495 */ 1496 if (DC_IS_DAVICOM(sc)) { 1497 if (IFM_SUBTYPE(media) == IFM_HPNA_1) { 1498 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL); 1499 sc->dc_link = 1; 1500 } else { 1501 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL); 1502 } 1503 } 1504 1505 if ((media & IFM_GMASK) == IFM_FDX) { 1506 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_FULLDUPLEX); 1507 if (sc->dc_pmode == DC_PMODE_SYM && DC_IS_PNIC(sc)) 1508 DC_SETBIT(sc, DC_PN_NWAY, DC_PN_NWAY_DUPLEX); 1509 } else { 1510 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_FULLDUPLEX); 1511 if (sc->dc_pmode == DC_PMODE_SYM && DC_IS_PNIC(sc)) 1512 DC_CLRBIT(sc, DC_PN_NWAY, DC_PN_NWAY_DUPLEX); 1513 } 1514 1515 if (restart) 1516 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_TX_ON | DC_NETCFG_RX_ON); 1517 } 1518 1519 static void 1520 dc_reset(struct dc_softc *sc) 1521 { 1522 int i; 1523 1524 DC_SETBIT(sc, DC_BUSCTL, DC_BUSCTL_RESET); 1525 1526 for (i = 0; i < DC_TIMEOUT; i++) { 1527 DELAY(10); 1528 if (!(CSR_READ_4(sc, DC_BUSCTL) & DC_BUSCTL_RESET)) 1529 break; 1530 } 1531 1532 if (DC_IS_ASIX(sc) || DC_IS_ADMTEK(sc) || DC_IS_CONEXANT(sc) || 1533 DC_IS_XIRCOM(sc) || DC_IS_INTEL(sc)) { 1534 DELAY(10000); 1535 DC_CLRBIT(sc, DC_BUSCTL, DC_BUSCTL_RESET); 1536 i = 0; 1537 } 1538 1539 if (i == DC_TIMEOUT) 1540 if_printf(sc->dc_ifp, "reset never completed!\n"); 1541 1542 /* Wait a little while for the chip to get its brains in order. */ 1543 DELAY(1000); 1544 1545 CSR_WRITE_4(sc, DC_IMR, 0x00000000); 1546 CSR_WRITE_4(sc, DC_BUSCTL, 0x00000000); 1547 CSR_WRITE_4(sc, DC_NETCFG, 0x00000000); 1548 1549 /* 1550 * Bring the SIA out of reset. In some cases, it looks 1551 * like failing to unreset the SIA soon enough gets it 1552 * into a state where it will never come out of reset 1553 * until we reset the whole chip again. 1554 */ 1555 if (DC_IS_INTEL(sc)) { 1556 DC_SETBIT(sc, DC_SIARESET, DC_SIA_RESET); 1557 CSR_WRITE_4(sc, DC_10BTCTRL, 0); 1558 CSR_WRITE_4(sc, DC_WATCHDOG, 0); 1559 } 1560 } 1561 1562 static struct dc_type * 1563 dc_devtype(device_t dev) 1564 { 1565 struct dc_type *t; 1566 u_int32_t rev; 1567 1568 t = dc_devs; 1569 1570 while (t->dc_name != NULL) { 1571 if ((pci_get_vendor(dev) == t->dc_vid) && 1572 (pci_get_device(dev) == t->dc_did)) { 1573 /* Check the PCI revision */ 1574 rev = pci_read_config(dev, DC_PCI_CFRV, 4) & 0xFF; 1575 if (t->dc_did == DC_DEVICEID_98713 && 1576 rev >= DC_REVISION_98713A) 1577 t++; 1578 if (t->dc_did == DC_DEVICEID_98713_CP && 1579 rev >= DC_REVISION_98713A) 1580 t++; 1581 if (t->dc_did == DC_DEVICEID_987x5 && 1582 rev >= DC_REVISION_98715AEC_C) 1583 t++; 1584 if (t->dc_did == DC_DEVICEID_987x5 && 1585 rev >= DC_REVISION_98725) 1586 t++; 1587 if (t->dc_did == DC_DEVICEID_AX88140A && 1588 rev >= DC_REVISION_88141) 1589 t++; 1590 if (t->dc_did == DC_DEVICEID_82C168 && 1591 rev >= DC_REVISION_82C169) 1592 t++; 1593 if (t->dc_did == DC_DEVICEID_DM9102 && 1594 rev >= DC_REVISION_DM9102A) 1595 t++; 1596 /* 1597 * The Microsoft MN-130 has a device ID of 0x0002, 1598 * which happens to be the same as the PNIC 82c168. 1599 * To keep dc_attach() from getting confused, we 1600 * pretend its ID is something different. 1601 * XXX: ideally, dc_attach() should be checking 1602 * vendorid+deviceid together to avoid such 1603 * collisions. 1604 */ 1605 if (t->dc_vid == DC_VENDORID_MICROSOFT && 1606 t->dc_did == DC_DEVICEID_MSMN130) 1607 t++; 1608 return (t); 1609 } 1610 t++; 1611 } 1612 1613 return (NULL); 1614 } 1615 1616 /* 1617 * Probe for a 21143 or clone chip. Check the PCI vendor and device 1618 * IDs against our list and return a device name if we find a match. 1619 * We do a little bit of extra work to identify the exact type of 1620 * chip. The MX98713 and MX98713A have the same PCI vendor/device ID, 1621 * but different revision IDs. The same is true for 98715/98715A 1622 * chips and the 98725, as well as the ASIX and ADMtek chips. In some 1623 * cases, the exact chip revision affects driver behavior. 1624 */ 1625 static int 1626 dc_probe(device_t dev) 1627 { 1628 struct dc_type *t; 1629 1630 t = dc_devtype(dev); 1631 1632 if (t != NULL) { 1633 device_set_desc(dev, t->dc_name); 1634 return (BUS_PROBE_DEFAULT); 1635 } 1636 1637 return (ENXIO); 1638 } 1639 1640 static void 1641 dc_apply_fixup(struct dc_softc *sc, int media) 1642 { 1643 struct dc_mediainfo *m; 1644 u_int8_t *p; 1645 int i; 1646 u_int32_t reg; 1647 1648 m = sc->dc_mi; 1649 1650 while (m != NULL) { 1651 if (m->dc_media == media) 1652 break; 1653 m = m->dc_next; 1654 } 1655 1656 if (m == NULL) 1657 return; 1658 1659 for (i = 0, p = m->dc_reset_ptr; i < m->dc_reset_len; i++, p += 2) { 1660 reg = (p[0] | (p[1] << 8)) << 16; 1661 CSR_WRITE_4(sc, DC_WATCHDOG, reg); 1662 } 1663 1664 for (i = 0, p = m->dc_gp_ptr; i < m->dc_gp_len; i++, p += 2) { 1665 reg = (p[0] | (p[1] << 8)) << 16; 1666 CSR_WRITE_4(sc, DC_WATCHDOG, reg); 1667 } 1668 } 1669 1670 static void 1671 dc_decode_leaf_sia(struct dc_softc *sc, struct dc_eblock_sia *l) 1672 { 1673 struct dc_mediainfo *m; 1674 1675 m = malloc(sizeof(struct dc_mediainfo), M_DEVBUF, M_NOWAIT | M_ZERO); 1676 switch (l->dc_sia_code & ~DC_SIA_CODE_EXT) { 1677 case DC_SIA_CODE_10BT: 1678 m->dc_media = IFM_10_T; 1679 break; 1680 case DC_SIA_CODE_10BT_FDX: 1681 m->dc_media = IFM_10_T | IFM_FDX; 1682 break; 1683 case DC_SIA_CODE_10B2: 1684 m->dc_media = IFM_10_2; 1685 break; 1686 case DC_SIA_CODE_10B5: 1687 m->dc_media = IFM_10_5; 1688 break; 1689 default: 1690 break; 1691 } 1692 1693 /* 1694 * We need to ignore CSR13, CSR14, CSR15 for SIA mode. 1695 * Things apparently already work for cards that do 1696 * supply Media Specific Data. 1697 */ 1698 if (l->dc_sia_code & DC_SIA_CODE_EXT) { 1699 m->dc_gp_len = 2; 1700 m->dc_gp_ptr = 1701 (u_int8_t *)&l->dc_un.dc_sia_ext.dc_sia_gpio_ctl; 1702 } else { 1703 m->dc_gp_len = 2; 1704 m->dc_gp_ptr = 1705 (u_int8_t *)&l->dc_un.dc_sia_noext.dc_sia_gpio_ctl; 1706 } 1707 1708 m->dc_next = sc->dc_mi; 1709 sc->dc_mi = m; 1710 1711 sc->dc_pmode = DC_PMODE_SIA; 1712 } 1713 1714 static void 1715 dc_decode_leaf_sym(struct dc_softc *sc, struct dc_eblock_sym *l) 1716 { 1717 struct dc_mediainfo *m; 1718 1719 m = malloc(sizeof(struct dc_mediainfo), M_DEVBUF, M_NOWAIT | M_ZERO); 1720 if (l->dc_sym_code == DC_SYM_CODE_100BT) 1721 m->dc_media = IFM_100_TX; 1722 1723 if (l->dc_sym_code == DC_SYM_CODE_100BT_FDX) 1724 m->dc_media = IFM_100_TX | IFM_FDX; 1725 1726 m->dc_gp_len = 2; 1727 m->dc_gp_ptr = (u_int8_t *)&l->dc_sym_gpio_ctl; 1728 1729 m->dc_next = sc->dc_mi; 1730 sc->dc_mi = m; 1731 1732 sc->dc_pmode = DC_PMODE_SYM; 1733 } 1734 1735 static void 1736 dc_decode_leaf_mii(struct dc_softc *sc, struct dc_eblock_mii *l) 1737 { 1738 struct dc_mediainfo *m; 1739 u_int8_t *p; 1740 1741 m = malloc(sizeof(struct dc_mediainfo), M_DEVBUF, M_NOWAIT | M_ZERO); 1742 /* We abuse IFM_AUTO to represent MII. */ 1743 m->dc_media = IFM_AUTO; 1744 m->dc_gp_len = l->dc_gpr_len; 1745 1746 p = (u_int8_t *)l; 1747 p += sizeof(struct dc_eblock_mii); 1748 m->dc_gp_ptr = p; 1749 p += 2 * l->dc_gpr_len; 1750 m->dc_reset_len = *p; 1751 p++; 1752 m->dc_reset_ptr = p; 1753 1754 m->dc_next = sc->dc_mi; 1755 sc->dc_mi = m; 1756 } 1757 1758 static void 1759 dc_read_srom(struct dc_softc *sc, int bits) 1760 { 1761 int size; 1762 1763 size = 2 << bits; 1764 sc->dc_srom = malloc(size, M_DEVBUF, M_NOWAIT); 1765 dc_read_eeprom(sc, (caddr_t)sc->dc_srom, 0, (size / 2), 0); 1766 } 1767 1768 static void 1769 dc_parse_21143_srom(struct dc_softc *sc) 1770 { 1771 struct dc_leaf_hdr *lhdr; 1772 struct dc_eblock_hdr *hdr; 1773 int have_mii, i, loff; 1774 char *ptr; 1775 1776 have_mii = 0; 1777 loff = sc->dc_srom[27]; 1778 lhdr = (struct dc_leaf_hdr *)&(sc->dc_srom[loff]); 1779 1780 ptr = (char *)lhdr; 1781 ptr += sizeof(struct dc_leaf_hdr) - 1; 1782 /* 1783 * Look if we got a MII media block. 1784 */ 1785 for (i = 0; i < lhdr->dc_mcnt; i++) { 1786 hdr = (struct dc_eblock_hdr *)ptr; 1787 if (hdr->dc_type == DC_EBLOCK_MII) 1788 have_mii++; 1789 1790 ptr += (hdr->dc_len & 0x7F); 1791 ptr++; 1792 } 1793 1794 /* 1795 * Do the same thing again. Only use SIA and SYM media 1796 * blocks if no MII media block is available. 1797 */ 1798 ptr = (char *)lhdr; 1799 ptr += sizeof(struct dc_leaf_hdr) - 1; 1800 for (i = 0; i < lhdr->dc_mcnt; i++) { 1801 hdr = (struct dc_eblock_hdr *)ptr; 1802 switch (hdr->dc_type) { 1803 case DC_EBLOCK_MII: 1804 dc_decode_leaf_mii(sc, (struct dc_eblock_mii *)hdr); 1805 break; 1806 case DC_EBLOCK_SIA: 1807 if (! have_mii) 1808 dc_decode_leaf_sia(sc, 1809 (struct dc_eblock_sia *)hdr); 1810 break; 1811 case DC_EBLOCK_SYM: 1812 if (! have_mii) 1813 dc_decode_leaf_sym(sc, 1814 (struct dc_eblock_sym *)hdr); 1815 break; 1816 default: 1817 /* Don't care. Yet. */ 1818 break; 1819 } 1820 ptr += (hdr->dc_len & 0x7F); 1821 ptr++; 1822 } 1823 } 1824 1825 static void 1826 dc_dma_map_addr(void *arg, bus_dma_segment_t *segs, int nseg, int error) 1827 { 1828 u_int32_t *paddr; 1829 1830 KASSERT(nseg == 1, ("wrong number of segments, should be 1")); 1831 paddr = arg; 1832 *paddr = segs->ds_addr; 1833 } 1834 1835 /* 1836 * Attach the interface. Allocate softc structures, do ifmedia 1837 * setup and ethernet/BPF attach. 1838 */ 1839 static int 1840 dc_attach(device_t dev) 1841 { 1842 int tmp = 0; 1843 uint32_t eaddr[(ETHER_ADDR_LEN+3)/4]; 1844 u_int32_t command; 1845 struct dc_softc *sc; 1846 struct ifnet *ifp; 1847 u_int32_t revision; 1848 int error = 0, rid, mac_offset; 1849 int i; 1850 u_int8_t *mac; 1851 1852 sc = device_get_softc(dev); 1853 1854 mtx_init(&sc->dc_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 1855 MTX_DEF); 1856 1857 /* 1858 * Map control/status registers. 1859 */ 1860 pci_enable_busmaster(dev); 1861 1862 rid = DC_RID; 1863 sc->dc_res = bus_alloc_resource_any(dev, DC_RES, &rid, RF_ACTIVE); 1864 1865 if (sc->dc_res == NULL) { 1866 device_printf(dev, "couldn't map ports/memory\n"); 1867 error = ENXIO; 1868 goto fail; 1869 } 1870 1871 sc->dc_btag = rman_get_bustag(sc->dc_res); 1872 sc->dc_bhandle = rman_get_bushandle(sc->dc_res); 1873 1874 /* Allocate interrupt. */ 1875 rid = 0; 1876 sc->dc_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 1877 RF_SHAREABLE | RF_ACTIVE); 1878 1879 if (sc->dc_irq == NULL) { 1880 device_printf(dev, "couldn't map interrupt\n"); 1881 error = ENXIO; 1882 goto fail; 1883 } 1884 1885 /* Need this info to decide on a chip type. */ 1886 sc->dc_info = dc_devtype(dev); 1887 revision = pci_read_config(dev, DC_PCI_CFRV, 4) & 0x000000FF; 1888 1889 /* Get the eeprom width, but PNIC and XIRCOM have diff eeprom */ 1890 if (sc->dc_info->dc_did != DC_DEVICEID_82C168 && 1891 sc->dc_info->dc_did != DC_DEVICEID_X3201) 1892 dc_eeprom_width(sc); 1893 1894 switch (sc->dc_info->dc_did) { 1895 case DC_DEVICEID_21143: 1896 sc->dc_type = DC_TYPE_21143; 1897 sc->dc_flags |= DC_TX_POLL | DC_TX_USE_TX_INTR; 1898 sc->dc_flags |= DC_REDUCED_MII_POLL; 1899 /* Save EEPROM contents so we can parse them later. */ 1900 dc_read_srom(sc, sc->dc_romwidth); 1901 break; 1902 case DC_DEVICEID_DM9009: 1903 case DC_DEVICEID_DM9100: 1904 case DC_DEVICEID_DM9102: 1905 sc->dc_type = DC_TYPE_DM9102; 1906 sc->dc_flags |= DC_TX_COALESCE | DC_TX_INTR_ALWAYS; 1907 sc->dc_flags |= DC_REDUCED_MII_POLL | DC_TX_STORENFWD; 1908 sc->dc_flags |= DC_TX_ALIGN; 1909 sc->dc_pmode = DC_PMODE_MII; 1910 /* Increase the latency timer value. */ 1911 command = pci_read_config(dev, DC_PCI_CFLT, 4); 1912 command &= 0xFFFF00FF; 1913 command |= 0x00008000; 1914 pci_write_config(dev, DC_PCI_CFLT, command, 4); 1915 break; 1916 case DC_DEVICEID_AL981: 1917 sc->dc_type = DC_TYPE_AL981; 1918 sc->dc_flags |= DC_TX_USE_TX_INTR; 1919 sc->dc_flags |= DC_TX_ADMTEK_WAR; 1920 sc->dc_pmode = DC_PMODE_MII; 1921 dc_read_srom(sc, sc->dc_romwidth); 1922 break; 1923 case DC_DEVICEID_AN985: 1924 case DC_DEVICEID_ADM9511: 1925 case DC_DEVICEID_ADM9513: 1926 case DC_DEVICEID_DRP32TXD: 1927 case DC_DEVICEID_FA511: 1928 case DC_DEVICEID_FE2500: 1929 case DC_DEVICEID_EN2242: 1930 case DC_DEVICEID_HAWKING_PN672TX: 1931 case DC_DEVICEID_3CSOHOB: 1932 case DC_DEVICEID_MSMN120: 1933 case DC_DEVICEID_MSMN130_FAKE: /* XXX avoid collision with PNIC*/ 1934 sc->dc_type = DC_TYPE_AN985; 1935 sc->dc_flags |= DC_64BIT_HASH; 1936 sc->dc_flags |= DC_TX_USE_TX_INTR; 1937 sc->dc_flags |= DC_TX_ADMTEK_WAR; 1938 sc->dc_pmode = DC_PMODE_MII; 1939 /* Don't read SROM for - auto-loaded on reset */ 1940 break; 1941 case DC_DEVICEID_98713: 1942 case DC_DEVICEID_98713_CP: 1943 if (revision < DC_REVISION_98713A) { 1944 sc->dc_type = DC_TYPE_98713; 1945 } 1946 if (revision >= DC_REVISION_98713A) { 1947 sc->dc_type = DC_TYPE_98713A; 1948 sc->dc_flags |= DC_21143_NWAY; 1949 } 1950 sc->dc_flags |= DC_REDUCED_MII_POLL; 1951 sc->dc_flags |= DC_TX_POLL | DC_TX_USE_TX_INTR; 1952 break; 1953 case DC_DEVICEID_987x5: 1954 case DC_DEVICEID_EN1217: 1955 /* 1956 * Macronix MX98715AEC-C/D/E parts have only a 1957 * 128-bit hash table. We need to deal with these 1958 * in the same manner as the PNIC II so that we 1959 * get the right number of bits out of the 1960 * CRC routine. 1961 */ 1962 if (revision >= DC_REVISION_98715AEC_C && 1963 revision < DC_REVISION_98725) 1964 sc->dc_flags |= DC_128BIT_HASH; 1965 sc->dc_type = DC_TYPE_987x5; 1966 sc->dc_flags |= DC_TX_POLL | DC_TX_USE_TX_INTR; 1967 sc->dc_flags |= DC_REDUCED_MII_POLL | DC_21143_NWAY; 1968 break; 1969 case DC_DEVICEID_98727: 1970 sc->dc_type = DC_TYPE_987x5; 1971 sc->dc_flags |= DC_TX_POLL | DC_TX_USE_TX_INTR; 1972 sc->dc_flags |= DC_REDUCED_MII_POLL | DC_21143_NWAY; 1973 break; 1974 case DC_DEVICEID_82C115: 1975 sc->dc_type = DC_TYPE_PNICII; 1976 sc->dc_flags |= DC_TX_POLL | DC_TX_USE_TX_INTR | DC_128BIT_HASH; 1977 sc->dc_flags |= DC_REDUCED_MII_POLL | DC_21143_NWAY; 1978 break; 1979 case DC_DEVICEID_82C168: 1980 sc->dc_type = DC_TYPE_PNIC; 1981 sc->dc_flags |= DC_TX_STORENFWD | DC_TX_INTR_ALWAYS; 1982 sc->dc_flags |= DC_PNIC_RX_BUG_WAR; 1983 sc->dc_pnic_rx_buf = malloc(DC_RXLEN * 5, M_DEVBUF, M_NOWAIT); 1984 if (revision < DC_REVISION_82C169) 1985 sc->dc_pmode = DC_PMODE_SYM; 1986 break; 1987 case DC_DEVICEID_AX88140A: 1988 sc->dc_type = DC_TYPE_ASIX; 1989 sc->dc_flags |= DC_TX_USE_TX_INTR | DC_TX_INTR_FIRSTFRAG; 1990 sc->dc_flags |= DC_REDUCED_MII_POLL; 1991 sc->dc_pmode = DC_PMODE_MII; 1992 break; 1993 case DC_DEVICEID_X3201: 1994 sc->dc_type = DC_TYPE_XIRCOM; 1995 sc->dc_flags |= DC_TX_INTR_ALWAYS | DC_TX_COALESCE | 1996 DC_TX_ALIGN; 1997 /* 1998 * We don't actually need to coalesce, but we're doing 1999 * it to obtain a double word aligned buffer. 2000 * The DC_TX_COALESCE flag is required. 2001 */ 2002 sc->dc_pmode = DC_PMODE_MII; 2003 break; 2004 case DC_DEVICEID_RS7112: 2005 sc->dc_type = DC_TYPE_CONEXANT; 2006 sc->dc_flags |= DC_TX_INTR_ALWAYS; 2007 sc->dc_flags |= DC_REDUCED_MII_POLL; 2008 sc->dc_pmode = DC_PMODE_MII; 2009 dc_read_srom(sc, sc->dc_romwidth); 2010 break; 2011 default: 2012 device_printf(dev, "unknown device: %x\n", sc->dc_info->dc_did); 2013 break; 2014 } 2015 2016 /* Save the cache line size. */ 2017 if (DC_IS_DAVICOM(sc)) 2018 sc->dc_cachesize = 0; 2019 else 2020 sc->dc_cachesize = pci_read_config(dev, 2021 DC_PCI_CFLT, 4) & 0xFF; 2022 2023 /* Reset the adapter. */ 2024 dc_reset(sc); 2025 2026 /* Take 21143 out of snooze mode */ 2027 if (DC_IS_INTEL(sc) || DC_IS_XIRCOM(sc)) { 2028 command = pci_read_config(dev, DC_PCI_CFDD, 4); 2029 command &= ~(DC_CFDD_SNOOZE_MODE | DC_CFDD_SLEEP_MODE); 2030 pci_write_config(dev, DC_PCI_CFDD, command, 4); 2031 } 2032 2033 /* 2034 * Try to learn something about the supported media. 2035 * We know that ASIX and ADMtek and Davicom devices 2036 * will *always* be using MII media, so that's a no-brainer. 2037 * The tricky ones are the Macronix/PNIC II and the 2038 * Intel 21143. 2039 */ 2040 if (DC_IS_INTEL(sc)) 2041 dc_parse_21143_srom(sc); 2042 else if (DC_IS_MACRONIX(sc) || DC_IS_PNICII(sc)) { 2043 if (sc->dc_type == DC_TYPE_98713) 2044 sc->dc_pmode = DC_PMODE_MII; 2045 else 2046 sc->dc_pmode = DC_PMODE_SYM; 2047 } else if (!sc->dc_pmode) 2048 sc->dc_pmode = DC_PMODE_MII; 2049 2050 /* 2051 * Get station address from the EEPROM. 2052 */ 2053 switch(sc->dc_type) { 2054 case DC_TYPE_98713: 2055 case DC_TYPE_98713A: 2056 case DC_TYPE_987x5: 2057 case DC_TYPE_PNICII: 2058 dc_read_eeprom(sc, (caddr_t)&mac_offset, 2059 (DC_EE_NODEADDR_OFFSET / 2), 1, 0); 2060 dc_read_eeprom(sc, (caddr_t)&eaddr, (mac_offset / 2), 3, 0); 2061 break; 2062 case DC_TYPE_PNIC: 2063 dc_read_eeprom(sc, (caddr_t)&eaddr, 0, 3, 1); 2064 break; 2065 case DC_TYPE_DM9102: 2066 dc_read_eeprom(sc, (caddr_t)&eaddr, DC_EE_NODEADDR, 3, 0); 2067 #ifdef __sparc64__ 2068 /* 2069 * If this is an onboard dc(4) the station address read from 2070 * the EEPROM is all zero and we have to get it from the FCode. 2071 */ 2072 if (eaddr[0] == 0 && (eaddr[1] & ~0xffff) == 0) 2073 OF_getetheraddr(dev, (caddr_t)&eaddr); 2074 #endif 2075 break; 2076 case DC_TYPE_21143: 2077 case DC_TYPE_ASIX: 2078 dc_read_eeprom(sc, (caddr_t)&eaddr, DC_EE_NODEADDR, 3, 0); 2079 break; 2080 case DC_TYPE_AL981: 2081 case DC_TYPE_AN985: 2082 eaddr[0] = CSR_READ_4(sc, DC_AL_PAR0); 2083 eaddr[1] = CSR_READ_4(sc, DC_AL_PAR1); 2084 break; 2085 case DC_TYPE_CONEXANT: 2086 bcopy(sc->dc_srom + DC_CONEXANT_EE_NODEADDR, &eaddr, 2087 ETHER_ADDR_LEN); 2088 break; 2089 case DC_TYPE_XIRCOM: 2090 /* The MAC comes from the CIS. */ 2091 mac = pci_get_ether(dev); 2092 if (!mac) { 2093 device_printf(dev, "No station address in CIS!\n"); 2094 error = ENXIO; 2095 goto fail; 2096 } 2097 bcopy(mac, eaddr, ETHER_ADDR_LEN); 2098 break; 2099 default: 2100 dc_read_eeprom(sc, (caddr_t)&eaddr, DC_EE_NODEADDR, 3, 0); 2101 break; 2102 } 2103 2104 /* Allocate a busdma tag and DMA safe memory for TX/RX descriptors. */ 2105 error = bus_dma_tag_create(NULL, PAGE_SIZE, 0, BUS_SPACE_MAXADDR_32BIT, 2106 BUS_SPACE_MAXADDR, NULL, NULL, sizeof(struct dc_list_data), 1, 2107 sizeof(struct dc_list_data), 0, NULL, NULL, &sc->dc_ltag); 2108 if (error) { 2109 device_printf(dev, "failed to allocate busdma tag\n"); 2110 error = ENXIO; 2111 goto fail; 2112 } 2113 error = bus_dmamem_alloc(sc->dc_ltag, (void **)&sc->dc_ldata, 2114 BUS_DMA_NOWAIT | BUS_DMA_ZERO, &sc->dc_lmap); 2115 if (error) { 2116 device_printf(dev, "failed to allocate DMA safe memory\n"); 2117 error = ENXIO; 2118 goto fail; 2119 } 2120 error = bus_dmamap_load(sc->dc_ltag, sc->dc_lmap, sc->dc_ldata, 2121 sizeof(struct dc_list_data), dc_dma_map_addr, &sc->dc_laddr, 2122 BUS_DMA_NOWAIT); 2123 if (error) { 2124 device_printf(dev, "cannot get address of the descriptors\n"); 2125 error = ENXIO; 2126 goto fail; 2127 } 2128 2129 /* 2130 * Allocate a busdma tag and DMA safe memory for the multicast 2131 * setup frame. 2132 */ 2133 error = bus_dma_tag_create(NULL, PAGE_SIZE, 0, BUS_SPACE_MAXADDR_32BIT, 2134 BUS_SPACE_MAXADDR, NULL, NULL, DC_SFRAME_LEN + DC_MIN_FRAMELEN, 1, 2135 DC_SFRAME_LEN + DC_MIN_FRAMELEN, 0, NULL, NULL, &sc->dc_stag); 2136 if (error) { 2137 device_printf(dev, "failed to allocate busdma tag\n"); 2138 error = ENXIO; 2139 goto fail; 2140 } 2141 error = bus_dmamem_alloc(sc->dc_stag, (void **)&sc->dc_cdata.dc_sbuf, 2142 BUS_DMA_NOWAIT, &sc->dc_smap); 2143 if (error) { 2144 device_printf(dev, "failed to allocate DMA safe memory\n"); 2145 error = ENXIO; 2146 goto fail; 2147 } 2148 error = bus_dmamap_load(sc->dc_stag, sc->dc_smap, sc->dc_cdata.dc_sbuf, 2149 DC_SFRAME_LEN, dc_dma_map_addr, &sc->dc_saddr, BUS_DMA_NOWAIT); 2150 if (error) { 2151 device_printf(dev, "cannot get address of the descriptors\n"); 2152 error = ENXIO; 2153 goto fail; 2154 } 2155 2156 /* Allocate a busdma tag for mbufs. */ 2157 error = bus_dma_tag_create(NULL, 1, 0, BUS_SPACE_MAXADDR_32BIT, 2158 BUS_SPACE_MAXADDR, NULL, NULL, MCLBYTES, DC_TX_LIST_CNT, MCLBYTES, 2159 0, NULL, NULL, &sc->dc_mtag); 2160 if (error) { 2161 device_printf(dev, "failed to allocate busdma tag\n"); 2162 error = ENXIO; 2163 goto fail; 2164 } 2165 2166 /* Create the TX/RX busdma maps. */ 2167 for (i = 0; i < DC_TX_LIST_CNT; i++) { 2168 error = bus_dmamap_create(sc->dc_mtag, 0, 2169 &sc->dc_cdata.dc_tx_map[i]); 2170 if (error) { 2171 device_printf(dev, "failed to init TX ring\n"); 2172 error = ENXIO; 2173 goto fail; 2174 } 2175 } 2176 for (i = 0; i < DC_RX_LIST_CNT; i++) { 2177 error = bus_dmamap_create(sc->dc_mtag, 0, 2178 &sc->dc_cdata.dc_rx_map[i]); 2179 if (error) { 2180 device_printf(dev, "failed to init RX ring\n"); 2181 error = ENXIO; 2182 goto fail; 2183 } 2184 } 2185 error = bus_dmamap_create(sc->dc_mtag, 0, &sc->dc_sparemap); 2186 if (error) { 2187 device_printf(dev, "failed to init RX ring\n"); 2188 error = ENXIO; 2189 goto fail; 2190 } 2191 2192 ifp = sc->dc_ifp = if_alloc(IFT_ETHER); 2193 if (ifp == NULL) { 2194 device_printf(dev, "can not if_alloc()\n"); 2195 error = ENOSPC; 2196 goto fail; 2197 } 2198 ifp->if_softc = sc; 2199 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 2200 /* XXX: bleah, MTU gets overwritten in ether_ifattach() */ 2201 ifp->if_mtu = ETHERMTU; 2202 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 2203 ifp->if_ioctl = dc_ioctl; 2204 ifp->if_start = dc_start; 2205 ifp->if_watchdog = dc_watchdog; 2206 ifp->if_init = dc_init; 2207 IFQ_SET_MAXLEN(&ifp->if_snd, DC_TX_LIST_CNT - 1); 2208 ifp->if_snd.ifq_drv_maxlen = DC_TX_LIST_CNT - 1; 2209 IFQ_SET_READY(&ifp->if_snd); 2210 2211 /* 2212 * Do MII setup. If this is a 21143, check for a PHY on the 2213 * MII bus after applying any necessary fixups to twiddle the 2214 * GPIO bits. If we don't end up finding a PHY, restore the 2215 * old selection (SIA only or SIA/SYM) and attach the dcphy 2216 * driver instead. 2217 */ 2218 if (DC_IS_INTEL(sc)) { 2219 dc_apply_fixup(sc, IFM_AUTO); 2220 tmp = sc->dc_pmode; 2221 sc->dc_pmode = DC_PMODE_MII; 2222 } 2223 2224 /* 2225 * Setup General Purpose port mode and data so the tulip can talk 2226 * to the MII. This needs to be done before mii_phy_probe so that 2227 * we can actually see them. 2228 */ 2229 if (DC_IS_XIRCOM(sc)) { 2230 CSR_WRITE_4(sc, DC_SIAGP, DC_SIAGP_WRITE_EN | DC_SIAGP_INT1_EN | 2231 DC_SIAGP_MD_GP2_OUTPUT | DC_SIAGP_MD_GP0_OUTPUT); 2232 DELAY(10); 2233 CSR_WRITE_4(sc, DC_SIAGP, DC_SIAGP_INT1_EN | 2234 DC_SIAGP_MD_GP2_OUTPUT | DC_SIAGP_MD_GP0_OUTPUT); 2235 DELAY(10); 2236 } 2237 2238 error = mii_phy_probe(dev, &sc->dc_miibus, 2239 dc_ifmedia_upd, dc_ifmedia_sts); 2240 2241 if (error && DC_IS_INTEL(sc)) { 2242 sc->dc_pmode = tmp; 2243 if (sc->dc_pmode != DC_PMODE_SIA) 2244 sc->dc_pmode = DC_PMODE_SYM; 2245 sc->dc_flags |= DC_21143_NWAY; 2246 mii_phy_probe(dev, &sc->dc_miibus, 2247 dc_ifmedia_upd, dc_ifmedia_sts); 2248 /* 2249 * For non-MII cards, we need to have the 21143 2250 * drive the LEDs. Except there are some systems 2251 * like the NEC VersaPro NoteBook PC which have no 2252 * LEDs, and twiddling these bits has adverse effects 2253 * on them. (I.e. you suddenly can't get a link.) 2254 */ 2255 if (pci_read_config(dev, DC_PCI_CSID, 4) != 0x80281033) 2256 sc->dc_flags |= DC_TULIP_LEDS; 2257 error = 0; 2258 } 2259 2260 if (error) { 2261 device_printf(dev, "MII without any PHY!\n"); 2262 goto fail; 2263 } 2264 2265 if (DC_IS_ADMTEK(sc)) { 2266 /* 2267 * Set automatic TX underrun recovery for the ADMtek chips 2268 */ 2269 DC_SETBIT(sc, DC_AL_CR, DC_AL_CR_ATUR); 2270 } 2271 2272 /* 2273 * Tell the upper layer(s) we support long frames. 2274 */ 2275 ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header); 2276 ifp->if_capabilities |= IFCAP_VLAN_MTU; 2277 ifp->if_capenable = ifp->if_capabilities; 2278 #ifdef DEVICE_POLLING 2279 ifp->if_capabilities |= IFCAP_POLLING; 2280 #endif 2281 2282 callout_init_mtx(&sc->dc_stat_ch, &sc->dc_mtx, 0); 2283 2284 #ifdef SRM_MEDIA 2285 sc->dc_srm_media = 0; 2286 2287 /* Remember the SRM console media setting */ 2288 if (DC_IS_INTEL(sc)) { 2289 command = pci_read_config(dev, DC_PCI_CFDD, 4); 2290 command &= ~(DC_CFDD_SNOOZE_MODE | DC_CFDD_SLEEP_MODE); 2291 switch ((command >> 8) & 0xff) { 2292 case 3: 2293 sc->dc_srm_media = IFM_10_T; 2294 break; 2295 case 4: 2296 sc->dc_srm_media = IFM_10_T | IFM_FDX; 2297 break; 2298 case 5: 2299 sc->dc_srm_media = IFM_100_TX; 2300 break; 2301 case 6: 2302 sc->dc_srm_media = IFM_100_TX | IFM_FDX; 2303 break; 2304 } 2305 if (sc->dc_srm_media) 2306 sc->dc_srm_media |= IFM_ACTIVE | IFM_ETHER; 2307 } 2308 #endif 2309 2310 /* 2311 * Call MI attach routine. 2312 */ 2313 ether_ifattach(ifp, (caddr_t)eaddr); 2314 2315 /* Hook interrupt last to avoid having to lock softc */ 2316 error = bus_setup_intr(dev, sc->dc_irq, INTR_TYPE_NET | INTR_MPSAFE, 2317 dc_intr, sc, &sc->dc_intrhand); 2318 2319 if (error) { 2320 device_printf(dev, "couldn't set up irq\n"); 2321 ether_ifdetach(ifp); 2322 goto fail; 2323 } 2324 2325 fail: 2326 if (error) 2327 dc_detach(dev); 2328 return (error); 2329 } 2330 2331 /* 2332 * Shutdown hardware and free up resources. This can be called any 2333 * time after the mutex has been initialized. It is called in both 2334 * the error case in attach and the normal detach case so it needs 2335 * to be careful about only freeing resources that have actually been 2336 * allocated. 2337 */ 2338 static int 2339 dc_detach(device_t dev) 2340 { 2341 struct dc_softc *sc; 2342 struct ifnet *ifp; 2343 struct dc_mediainfo *m; 2344 int i; 2345 2346 sc = device_get_softc(dev); 2347 KASSERT(mtx_initialized(&sc->dc_mtx), ("dc mutex not initialized")); 2348 2349 ifp = sc->dc_ifp; 2350 2351 #ifdef DEVICE_POLLING 2352 if (ifp->if_capenable & IFCAP_POLLING) 2353 ether_poll_deregister(ifp); 2354 #endif 2355 2356 /* These should only be active if attach succeeded */ 2357 if (device_is_attached(dev)) { 2358 DC_LOCK(sc); 2359 dc_stop(sc); 2360 DC_UNLOCK(sc); 2361 callout_drain(&sc->dc_stat_ch); 2362 ether_ifdetach(ifp); 2363 } 2364 if (sc->dc_miibus) 2365 device_delete_child(dev, sc->dc_miibus); 2366 bus_generic_detach(dev); 2367 2368 if (sc->dc_intrhand) 2369 bus_teardown_intr(dev, sc->dc_irq, sc->dc_intrhand); 2370 if (sc->dc_irq) 2371 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->dc_irq); 2372 if (sc->dc_res) 2373 bus_release_resource(dev, DC_RES, DC_RID, sc->dc_res); 2374 2375 if (ifp) 2376 if_free(ifp); 2377 2378 if (sc->dc_cdata.dc_sbuf != NULL) 2379 bus_dmamem_free(sc->dc_stag, sc->dc_cdata.dc_sbuf, sc->dc_smap); 2380 if (sc->dc_ldata != NULL) 2381 bus_dmamem_free(sc->dc_ltag, sc->dc_ldata, sc->dc_lmap); 2382 if (sc->dc_mtag) { 2383 for (i = 0; i < DC_TX_LIST_CNT; i++) 2384 if (sc->dc_cdata.dc_tx_map[i] != NULL) 2385 bus_dmamap_destroy(sc->dc_mtag, 2386 sc->dc_cdata.dc_tx_map[i]); 2387 for (i = 0; i < DC_RX_LIST_CNT; i++) 2388 if (sc->dc_cdata.dc_rx_map[i] != NULL) 2389 bus_dmamap_destroy(sc->dc_mtag, 2390 sc->dc_cdata.dc_rx_map[i]); 2391 bus_dmamap_destroy(sc->dc_mtag, sc->dc_sparemap); 2392 } 2393 if (sc->dc_stag) 2394 bus_dma_tag_destroy(sc->dc_stag); 2395 if (sc->dc_mtag) 2396 bus_dma_tag_destroy(sc->dc_mtag); 2397 if (sc->dc_ltag) 2398 bus_dma_tag_destroy(sc->dc_ltag); 2399 2400 free(sc->dc_pnic_rx_buf, M_DEVBUF); 2401 2402 while (sc->dc_mi != NULL) { 2403 m = sc->dc_mi->dc_next; 2404 free(sc->dc_mi, M_DEVBUF); 2405 sc->dc_mi = m; 2406 } 2407 free(sc->dc_srom, M_DEVBUF); 2408 2409 mtx_destroy(&sc->dc_mtx); 2410 2411 return (0); 2412 } 2413 2414 /* 2415 * Initialize the transmit descriptors. 2416 */ 2417 static int 2418 dc_list_tx_init(struct dc_softc *sc) 2419 { 2420 struct dc_chain_data *cd; 2421 struct dc_list_data *ld; 2422 int i, nexti; 2423 2424 cd = &sc->dc_cdata; 2425 ld = sc->dc_ldata; 2426 for (i = 0; i < DC_TX_LIST_CNT; i++) { 2427 if (i == DC_TX_LIST_CNT - 1) 2428 nexti = 0; 2429 else 2430 nexti = i + 1; 2431 ld->dc_tx_list[i].dc_next = htole32(DC_TXDESC(sc, nexti)); 2432 cd->dc_tx_chain[i] = NULL; 2433 ld->dc_tx_list[i].dc_data = 0; 2434 ld->dc_tx_list[i].dc_ctl = 0; 2435 } 2436 2437 cd->dc_tx_prod = cd->dc_tx_cons = cd->dc_tx_cnt = 0; 2438 bus_dmamap_sync(sc->dc_ltag, sc->dc_lmap, 2439 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2440 return (0); 2441 } 2442 2443 2444 /* 2445 * Initialize the RX descriptors and allocate mbufs for them. Note that 2446 * we arrange the descriptors in a closed ring, so that the last descriptor 2447 * points back to the first. 2448 */ 2449 static int 2450 dc_list_rx_init(struct dc_softc *sc) 2451 { 2452 struct dc_chain_data *cd; 2453 struct dc_list_data *ld; 2454 int i, nexti; 2455 2456 cd = &sc->dc_cdata; 2457 ld = sc->dc_ldata; 2458 2459 for (i = 0; i < DC_RX_LIST_CNT; i++) { 2460 if (dc_newbuf(sc, i, 1) != 0) 2461 return (ENOBUFS); 2462 if (i == DC_RX_LIST_CNT - 1) 2463 nexti = 0; 2464 else 2465 nexti = i + 1; 2466 ld->dc_rx_list[i].dc_next = htole32(DC_RXDESC(sc, nexti)); 2467 } 2468 2469 cd->dc_rx_prod = 0; 2470 bus_dmamap_sync(sc->dc_ltag, sc->dc_lmap, 2471 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2472 return (0); 2473 } 2474 2475 static void 2476 dc_dma_map_rxbuf(arg, segs, nseg, mapsize, error) 2477 void *arg; 2478 bus_dma_segment_t *segs; 2479 int nseg; 2480 bus_size_t mapsize; 2481 int error; 2482 { 2483 struct dc_softc *sc; 2484 struct dc_desc *c; 2485 2486 sc = arg; 2487 c = &sc->dc_ldata->dc_rx_list[sc->dc_cdata.dc_rx_cur]; 2488 if (error) { 2489 sc->dc_cdata.dc_rx_err = error; 2490 return; 2491 } 2492 2493 KASSERT(nseg == 1, ("wrong number of segments, should be 1")); 2494 sc->dc_cdata.dc_rx_err = 0; 2495 c->dc_data = htole32(segs->ds_addr); 2496 } 2497 2498 /* 2499 * Initialize an RX descriptor and attach an MBUF cluster. 2500 */ 2501 static int 2502 dc_newbuf(struct dc_softc *sc, int i, int alloc) 2503 { 2504 struct mbuf *m_new; 2505 bus_dmamap_t tmp; 2506 int error; 2507 2508 if (alloc) { 2509 m_new = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR); 2510 if (m_new == NULL) 2511 return (ENOBUFS); 2512 } else { 2513 m_new = sc->dc_cdata.dc_rx_chain[i]; 2514 m_new->m_data = m_new->m_ext.ext_buf; 2515 } 2516 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 2517 m_adj(m_new, sizeof(u_int64_t)); 2518 2519 /* 2520 * If this is a PNIC chip, zero the buffer. This is part 2521 * of the workaround for the receive bug in the 82c168 and 2522 * 82c169 chips. 2523 */ 2524 if (sc->dc_flags & DC_PNIC_RX_BUG_WAR) 2525 bzero(mtod(m_new, char *), m_new->m_len); 2526 2527 /* No need to remap the mbuf if we're reusing it. */ 2528 if (alloc) { 2529 sc->dc_cdata.dc_rx_cur = i; 2530 error = bus_dmamap_load_mbuf(sc->dc_mtag, sc->dc_sparemap, 2531 m_new, dc_dma_map_rxbuf, sc, 0); 2532 if (error) { 2533 m_freem(m_new); 2534 return (error); 2535 } 2536 if (sc->dc_cdata.dc_rx_err != 0) { 2537 m_freem(m_new); 2538 return (sc->dc_cdata.dc_rx_err); 2539 } 2540 bus_dmamap_unload(sc->dc_mtag, sc->dc_cdata.dc_rx_map[i]); 2541 tmp = sc->dc_cdata.dc_rx_map[i]; 2542 sc->dc_cdata.dc_rx_map[i] = sc->dc_sparemap; 2543 sc->dc_sparemap = tmp; 2544 sc->dc_cdata.dc_rx_chain[i] = m_new; 2545 } 2546 2547 sc->dc_ldata->dc_rx_list[i].dc_ctl = htole32(DC_RXCTL_RLINK | DC_RXLEN); 2548 sc->dc_ldata->dc_rx_list[i].dc_status = htole32(DC_RXSTAT_OWN); 2549 bus_dmamap_sync(sc->dc_mtag, sc->dc_cdata.dc_rx_map[i], 2550 BUS_DMASYNC_PREREAD); 2551 bus_dmamap_sync(sc->dc_ltag, sc->dc_lmap, 2552 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2553 return (0); 2554 } 2555 2556 /* 2557 * Grrrrr. 2558 * The PNIC chip has a terrible bug in it that manifests itself during 2559 * periods of heavy activity. The exact mode of failure if difficult to 2560 * pinpoint: sometimes it only happens in promiscuous mode, sometimes it 2561 * will happen on slow machines. The bug is that sometimes instead of 2562 * uploading one complete frame during reception, it uploads what looks 2563 * like the entire contents of its FIFO memory. The frame we want is at 2564 * the end of the whole mess, but we never know exactly how much data has 2565 * been uploaded, so salvaging the frame is hard. 2566 * 2567 * There is only one way to do it reliably, and it's disgusting. 2568 * Here's what we know: 2569 * 2570 * - We know there will always be somewhere between one and three extra 2571 * descriptors uploaded. 2572 * 2573 * - We know the desired received frame will always be at the end of the 2574 * total data upload. 2575 * 2576 * - We know the size of the desired received frame because it will be 2577 * provided in the length field of the status word in the last descriptor. 2578 * 2579 * Here's what we do: 2580 * 2581 * - When we allocate buffers for the receive ring, we bzero() them. 2582 * This means that we know that the buffer contents should be all 2583 * zeros, except for data uploaded by the chip. 2584 * 2585 * - We also force the PNIC chip to upload frames that include the 2586 * ethernet CRC at the end. 2587 * 2588 * - We gather all of the bogus frame data into a single buffer. 2589 * 2590 * - We then position a pointer at the end of this buffer and scan 2591 * backwards until we encounter the first non-zero byte of data. 2592 * This is the end of the received frame. We know we will encounter 2593 * some data at the end of the frame because the CRC will always be 2594 * there, so even if the sender transmits a packet of all zeros, 2595 * we won't be fooled. 2596 * 2597 * - We know the size of the actual received frame, so we subtract 2598 * that value from the current pointer location. This brings us 2599 * to the start of the actual received packet. 2600 * 2601 * - We copy this into an mbuf and pass it on, along with the actual 2602 * frame length. 2603 * 2604 * The performance hit is tremendous, but it beats dropping frames all 2605 * the time. 2606 */ 2607 2608 #define DC_WHOLEFRAME (DC_RXSTAT_FIRSTFRAG | DC_RXSTAT_LASTFRAG) 2609 static void 2610 dc_pnic_rx_bug_war(struct dc_softc *sc, int idx) 2611 { 2612 struct dc_desc *cur_rx; 2613 struct dc_desc *c = NULL; 2614 struct mbuf *m = NULL; 2615 unsigned char *ptr; 2616 int i, total_len; 2617 u_int32_t rxstat = 0; 2618 2619 i = sc->dc_pnic_rx_bug_save; 2620 cur_rx = &sc->dc_ldata->dc_rx_list[idx]; 2621 ptr = sc->dc_pnic_rx_buf; 2622 bzero(ptr, DC_RXLEN * 5); 2623 2624 /* Copy all the bytes from the bogus buffers. */ 2625 while (1) { 2626 c = &sc->dc_ldata->dc_rx_list[i]; 2627 rxstat = le32toh(c->dc_status); 2628 m = sc->dc_cdata.dc_rx_chain[i]; 2629 bcopy(mtod(m, char *), ptr, DC_RXLEN); 2630 ptr += DC_RXLEN; 2631 /* If this is the last buffer, break out. */ 2632 if (i == idx || rxstat & DC_RXSTAT_LASTFRAG) 2633 break; 2634 dc_newbuf(sc, i, 0); 2635 DC_INC(i, DC_RX_LIST_CNT); 2636 } 2637 2638 /* Find the length of the actual receive frame. */ 2639 total_len = DC_RXBYTES(rxstat); 2640 2641 /* Scan backwards until we hit a non-zero byte. */ 2642 while (*ptr == 0x00) 2643 ptr--; 2644 2645 /* Round off. */ 2646 if ((uintptr_t)(ptr) & 0x3) 2647 ptr -= 1; 2648 2649 /* Now find the start of the frame. */ 2650 ptr -= total_len; 2651 if (ptr < sc->dc_pnic_rx_buf) 2652 ptr = sc->dc_pnic_rx_buf; 2653 2654 /* 2655 * Now copy the salvaged frame to the last mbuf and fake up 2656 * the status word to make it look like a successful 2657 * frame reception. 2658 */ 2659 dc_newbuf(sc, i, 0); 2660 bcopy(ptr, mtod(m, char *), total_len); 2661 cur_rx->dc_status = htole32(rxstat | DC_RXSTAT_FIRSTFRAG); 2662 } 2663 2664 /* 2665 * This routine searches the RX ring for dirty descriptors in the 2666 * event that the rxeof routine falls out of sync with the chip's 2667 * current descriptor pointer. This may happen sometimes as a result 2668 * of a "no RX buffer available" condition that happens when the chip 2669 * consumes all of the RX buffers before the driver has a chance to 2670 * process the RX ring. This routine may need to be called more than 2671 * once to bring the driver back in sync with the chip, however we 2672 * should still be getting RX DONE interrupts to drive the search 2673 * for new packets in the RX ring, so we should catch up eventually. 2674 */ 2675 static int 2676 dc_rx_resync(struct dc_softc *sc) 2677 { 2678 struct dc_desc *cur_rx; 2679 int i, pos; 2680 2681 pos = sc->dc_cdata.dc_rx_prod; 2682 2683 for (i = 0; i < DC_RX_LIST_CNT; i++) { 2684 cur_rx = &sc->dc_ldata->dc_rx_list[pos]; 2685 if (!(le32toh(cur_rx->dc_status) & DC_RXSTAT_OWN)) 2686 break; 2687 DC_INC(pos, DC_RX_LIST_CNT); 2688 } 2689 2690 /* If the ring really is empty, then just return. */ 2691 if (i == DC_RX_LIST_CNT) 2692 return (0); 2693 2694 /* We've fallen behing the chip: catch it. */ 2695 sc->dc_cdata.dc_rx_prod = pos; 2696 2697 return (EAGAIN); 2698 } 2699 2700 /* 2701 * A frame has been uploaded: pass the resulting mbuf chain up to 2702 * the higher level protocols. 2703 */ 2704 static void 2705 dc_rxeof(struct dc_softc *sc) 2706 { 2707 struct mbuf *m; 2708 struct ifnet *ifp; 2709 struct dc_desc *cur_rx; 2710 int i, total_len = 0; 2711 u_int32_t rxstat; 2712 2713 DC_LOCK_ASSERT(sc); 2714 2715 ifp = sc->dc_ifp; 2716 i = sc->dc_cdata.dc_rx_prod; 2717 2718 bus_dmamap_sync(sc->dc_ltag, sc->dc_lmap, BUS_DMASYNC_POSTREAD); 2719 while (!(le32toh(sc->dc_ldata->dc_rx_list[i].dc_status) & 2720 DC_RXSTAT_OWN)) { 2721 #ifdef DEVICE_POLLING 2722 if (ifp->if_capenable & IFCAP_POLLING) { 2723 if (sc->rxcycles <= 0) 2724 break; 2725 sc->rxcycles--; 2726 } 2727 #endif 2728 cur_rx = &sc->dc_ldata->dc_rx_list[i]; 2729 rxstat = le32toh(cur_rx->dc_status); 2730 m = sc->dc_cdata.dc_rx_chain[i]; 2731 bus_dmamap_sync(sc->dc_mtag, sc->dc_cdata.dc_rx_map[i], 2732 BUS_DMASYNC_POSTREAD); 2733 total_len = DC_RXBYTES(rxstat); 2734 2735 if (sc->dc_flags & DC_PNIC_RX_BUG_WAR) { 2736 if ((rxstat & DC_WHOLEFRAME) != DC_WHOLEFRAME) { 2737 if (rxstat & DC_RXSTAT_FIRSTFRAG) 2738 sc->dc_pnic_rx_bug_save = i; 2739 if ((rxstat & DC_RXSTAT_LASTFRAG) == 0) { 2740 DC_INC(i, DC_RX_LIST_CNT); 2741 continue; 2742 } 2743 dc_pnic_rx_bug_war(sc, i); 2744 rxstat = le32toh(cur_rx->dc_status); 2745 total_len = DC_RXBYTES(rxstat); 2746 } 2747 } 2748 2749 /* 2750 * If an error occurs, update stats, clear the 2751 * status word and leave the mbuf cluster in place: 2752 * it should simply get re-used next time this descriptor 2753 * comes up in the ring. However, don't report long 2754 * frames as errors since they could be vlans. 2755 */ 2756 if ((rxstat & DC_RXSTAT_RXERR)) { 2757 if (!(rxstat & DC_RXSTAT_GIANT) || 2758 (rxstat & (DC_RXSTAT_CRCERR | DC_RXSTAT_DRIBBLE | 2759 DC_RXSTAT_MIIERE | DC_RXSTAT_COLLSEEN | 2760 DC_RXSTAT_RUNT | DC_RXSTAT_DE))) { 2761 ifp->if_ierrors++; 2762 if (rxstat & DC_RXSTAT_COLLSEEN) 2763 ifp->if_collisions++; 2764 dc_newbuf(sc, i, 0); 2765 if (rxstat & DC_RXSTAT_CRCERR) { 2766 DC_INC(i, DC_RX_LIST_CNT); 2767 continue; 2768 } else { 2769 dc_init_locked(sc); 2770 return; 2771 } 2772 } 2773 } 2774 2775 /* No errors; receive the packet. */ 2776 total_len -= ETHER_CRC_LEN; 2777 #ifdef __i386__ 2778 /* 2779 * On the x86 we do not have alignment problems, so try to 2780 * allocate a new buffer for the receive ring, and pass up 2781 * the one where the packet is already, saving the expensive 2782 * copy done in m_devget(). 2783 * If we are on an architecture with alignment problems, or 2784 * if the allocation fails, then use m_devget and leave the 2785 * existing buffer in the receive ring. 2786 */ 2787 if (dc_quick && dc_newbuf(sc, i, 1) == 0) { 2788 m->m_pkthdr.rcvif = ifp; 2789 m->m_pkthdr.len = m->m_len = total_len; 2790 DC_INC(i, DC_RX_LIST_CNT); 2791 } else 2792 #endif 2793 { 2794 struct mbuf *m0; 2795 2796 m0 = m_devget(mtod(m, char *), total_len, 2797 ETHER_ALIGN, ifp, NULL); 2798 dc_newbuf(sc, i, 0); 2799 DC_INC(i, DC_RX_LIST_CNT); 2800 if (m0 == NULL) { 2801 ifp->if_ierrors++; 2802 continue; 2803 } 2804 m = m0; 2805 } 2806 2807 ifp->if_ipackets++; 2808 DC_UNLOCK(sc); 2809 (*ifp->if_input)(ifp, m); 2810 DC_LOCK(sc); 2811 } 2812 2813 sc->dc_cdata.dc_rx_prod = i; 2814 } 2815 2816 /* 2817 * A frame was downloaded to the chip. It's safe for us to clean up 2818 * the list buffers. 2819 */ 2820 2821 static void 2822 dc_txeof(struct dc_softc *sc) 2823 { 2824 struct dc_desc *cur_tx = NULL; 2825 struct ifnet *ifp; 2826 int idx; 2827 u_int32_t ctl, txstat; 2828 2829 ifp = sc->dc_ifp; 2830 2831 /* 2832 * Go through our tx list and free mbufs for those 2833 * frames that have been transmitted. 2834 */ 2835 bus_dmamap_sync(sc->dc_ltag, sc->dc_lmap, BUS_DMASYNC_POSTREAD); 2836 idx = sc->dc_cdata.dc_tx_cons; 2837 while (idx != sc->dc_cdata.dc_tx_prod) { 2838 2839 cur_tx = &sc->dc_ldata->dc_tx_list[idx]; 2840 txstat = le32toh(cur_tx->dc_status); 2841 ctl = le32toh(cur_tx->dc_ctl); 2842 2843 if (txstat & DC_TXSTAT_OWN) 2844 break; 2845 2846 if (!(ctl & DC_TXCTL_LASTFRAG) || ctl & DC_TXCTL_SETUP) { 2847 if (ctl & DC_TXCTL_SETUP) { 2848 /* 2849 * Yes, the PNIC is so brain damaged 2850 * that it will sometimes generate a TX 2851 * underrun error while DMAing the RX 2852 * filter setup frame. If we detect this, 2853 * we have to send the setup frame again, 2854 * or else the filter won't be programmed 2855 * correctly. 2856 */ 2857 if (DC_IS_PNIC(sc)) { 2858 if (txstat & DC_TXSTAT_ERRSUM) 2859 dc_setfilt(sc); 2860 } 2861 sc->dc_cdata.dc_tx_chain[idx] = NULL; 2862 } 2863 sc->dc_cdata.dc_tx_cnt--; 2864 DC_INC(idx, DC_TX_LIST_CNT); 2865 continue; 2866 } 2867 2868 if (DC_IS_XIRCOM(sc) || DC_IS_CONEXANT(sc)) { 2869 /* 2870 * XXX: Why does my Xircom taunt me so? 2871 * For some reason it likes setting the CARRLOST flag 2872 * even when the carrier is there. wtf?!? 2873 * Who knows, but Conexant chips have the 2874 * same problem. Maybe they took lessons 2875 * from Xircom. 2876 */ 2877 if (/*sc->dc_type == DC_TYPE_21143 &&*/ 2878 sc->dc_pmode == DC_PMODE_MII && 2879 ((txstat & 0xFFFF) & ~(DC_TXSTAT_ERRSUM | 2880 DC_TXSTAT_NOCARRIER))) 2881 txstat &= ~DC_TXSTAT_ERRSUM; 2882 } else { 2883 if (/*sc->dc_type == DC_TYPE_21143 &&*/ 2884 sc->dc_pmode == DC_PMODE_MII && 2885 ((txstat & 0xFFFF) & ~(DC_TXSTAT_ERRSUM | 2886 DC_TXSTAT_NOCARRIER | DC_TXSTAT_CARRLOST))) 2887 txstat &= ~DC_TXSTAT_ERRSUM; 2888 } 2889 2890 if (txstat & DC_TXSTAT_ERRSUM) { 2891 ifp->if_oerrors++; 2892 if (txstat & DC_TXSTAT_EXCESSCOLL) 2893 ifp->if_collisions++; 2894 if (txstat & DC_TXSTAT_LATECOLL) 2895 ifp->if_collisions++; 2896 if (!(txstat & DC_TXSTAT_UNDERRUN)) { 2897 dc_init_locked(sc); 2898 return; 2899 } 2900 } 2901 2902 ifp->if_collisions += (txstat & DC_TXSTAT_COLLCNT) >> 3; 2903 2904 ifp->if_opackets++; 2905 if (sc->dc_cdata.dc_tx_chain[idx] != NULL) { 2906 bus_dmamap_sync(sc->dc_mtag, 2907 sc->dc_cdata.dc_tx_map[idx], 2908 BUS_DMASYNC_POSTWRITE); 2909 bus_dmamap_unload(sc->dc_mtag, 2910 sc->dc_cdata.dc_tx_map[idx]); 2911 m_freem(sc->dc_cdata.dc_tx_chain[idx]); 2912 sc->dc_cdata.dc_tx_chain[idx] = NULL; 2913 } 2914 2915 sc->dc_cdata.dc_tx_cnt--; 2916 DC_INC(idx, DC_TX_LIST_CNT); 2917 } 2918 2919 if (idx != sc->dc_cdata.dc_tx_cons) { 2920 /* Some buffers have been freed. */ 2921 sc->dc_cdata.dc_tx_cons = idx; 2922 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 2923 } 2924 ifp->if_timer = (sc->dc_cdata.dc_tx_cnt == 0) ? 0 : 5; 2925 } 2926 2927 static void 2928 dc_tick(void *xsc) 2929 { 2930 struct dc_softc *sc; 2931 struct mii_data *mii; 2932 struct ifnet *ifp; 2933 u_int32_t r; 2934 2935 sc = xsc; 2936 DC_LOCK_ASSERT(sc); 2937 ifp = sc->dc_ifp; 2938 mii = device_get_softc(sc->dc_miibus); 2939 2940 if (sc->dc_flags & DC_REDUCED_MII_POLL) { 2941 if (sc->dc_flags & DC_21143_NWAY) { 2942 r = CSR_READ_4(sc, DC_10BTSTAT); 2943 if (IFM_SUBTYPE(mii->mii_media_active) == 2944 IFM_100_TX && (r & DC_TSTAT_LS100)) { 2945 sc->dc_link = 0; 2946 mii_mediachg(mii); 2947 } 2948 if (IFM_SUBTYPE(mii->mii_media_active) == 2949 IFM_10_T && (r & DC_TSTAT_LS10)) { 2950 sc->dc_link = 0; 2951 mii_mediachg(mii); 2952 } 2953 if (sc->dc_link == 0) 2954 mii_tick(mii); 2955 } else { 2956 r = CSR_READ_4(sc, DC_ISR); 2957 if ((r & DC_ISR_RX_STATE) == DC_RXSTATE_WAIT && 2958 sc->dc_cdata.dc_tx_cnt == 0) { 2959 mii_tick(mii); 2960 if (!(mii->mii_media_status & IFM_ACTIVE)) 2961 sc->dc_link = 0; 2962 } 2963 } 2964 } else 2965 mii_tick(mii); 2966 2967 /* 2968 * When the init routine completes, we expect to be able to send 2969 * packets right away, and in fact the network code will send a 2970 * gratuitous ARP the moment the init routine marks the interface 2971 * as running. However, even though the MAC may have been initialized, 2972 * there may be a delay of a few seconds before the PHY completes 2973 * autonegotiation and the link is brought up. Any transmissions 2974 * made during that delay will be lost. Dealing with this is tricky: 2975 * we can't just pause in the init routine while waiting for the 2976 * PHY to come ready since that would bring the whole system to 2977 * a screeching halt for several seconds. 2978 * 2979 * What we do here is prevent the TX start routine from sending 2980 * any packets until a link has been established. After the 2981 * interface has been initialized, the tick routine will poll 2982 * the state of the PHY until the IFM_ACTIVE flag is set. Until 2983 * that time, packets will stay in the send queue, and once the 2984 * link comes up, they will be flushed out to the wire. 2985 */ 2986 if (!sc->dc_link && mii->mii_media_status & IFM_ACTIVE && 2987 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) { 2988 sc->dc_link++; 2989 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 2990 dc_start_locked(ifp); 2991 } 2992 2993 if (sc->dc_flags & DC_21143_NWAY && !sc->dc_link) 2994 callout_reset(&sc->dc_stat_ch, hz/10, dc_tick, sc); 2995 else 2996 callout_reset(&sc->dc_stat_ch, hz, dc_tick, sc); 2997 } 2998 2999 /* 3000 * A transmit underrun has occurred. Back off the transmit threshold, 3001 * or switch to store and forward mode if we have to. 3002 */ 3003 static void 3004 dc_tx_underrun(struct dc_softc *sc) 3005 { 3006 u_int32_t isr; 3007 int i; 3008 3009 if (DC_IS_DAVICOM(sc)) 3010 dc_init_locked(sc); 3011 3012 if (DC_IS_INTEL(sc)) { 3013 /* 3014 * The real 21143 requires that the transmitter be idle 3015 * in order to change the transmit threshold or store 3016 * and forward state. 3017 */ 3018 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_TX_ON); 3019 3020 for (i = 0; i < DC_TIMEOUT; i++) { 3021 isr = CSR_READ_4(sc, DC_ISR); 3022 if (isr & DC_ISR_TX_IDLE) 3023 break; 3024 DELAY(10); 3025 } 3026 if (i == DC_TIMEOUT) { 3027 if_printf(sc->dc_ifp, 3028 "failed to force tx to idle state\n"); 3029 dc_init_locked(sc); 3030 } 3031 } 3032 3033 if_printf(sc->dc_ifp, "TX underrun -- "); 3034 sc->dc_txthresh += DC_TXTHRESH_INC; 3035 if (sc->dc_txthresh > DC_TXTHRESH_MAX) { 3036 printf("using store and forward mode\n"); 3037 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_STORENFWD); 3038 } else { 3039 printf("increasing TX threshold\n"); 3040 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_TX_THRESH); 3041 DC_SETBIT(sc, DC_NETCFG, sc->dc_txthresh); 3042 } 3043 3044 if (DC_IS_INTEL(sc)) 3045 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_TX_ON); 3046 } 3047 3048 #ifdef DEVICE_POLLING 3049 static poll_handler_t dc_poll; 3050 3051 static void 3052 dc_poll(struct ifnet *ifp, enum poll_cmd cmd, int count) 3053 { 3054 struct dc_softc *sc = ifp->if_softc; 3055 3056 DC_LOCK(sc); 3057 3058 if (!(ifp->if_drv_flags & IFF_DRV_RUNNING)) { 3059 DC_UNLOCK(sc); 3060 return; 3061 } 3062 3063 sc->rxcycles = count; 3064 dc_rxeof(sc); 3065 dc_txeof(sc); 3066 if (!IFQ_IS_EMPTY(&ifp->if_snd) && 3067 !(ifp->if_drv_flags & IFF_DRV_OACTIVE)) 3068 dc_start_locked(ifp); 3069 3070 if (cmd == POLL_AND_CHECK_STATUS) { /* also check status register */ 3071 u_int32_t status; 3072 3073 status = CSR_READ_4(sc, DC_ISR); 3074 status &= (DC_ISR_RX_WATDOGTIMEO | DC_ISR_RX_NOBUF | 3075 DC_ISR_TX_NOBUF | DC_ISR_TX_IDLE | DC_ISR_TX_UNDERRUN | 3076 DC_ISR_BUS_ERR); 3077 if (!status) { 3078 DC_UNLOCK(sc); 3079 return; 3080 } 3081 /* ack what we have */ 3082 CSR_WRITE_4(sc, DC_ISR, status); 3083 3084 if (status & (DC_ISR_RX_WATDOGTIMEO | DC_ISR_RX_NOBUF)) { 3085 u_int32_t r = CSR_READ_4(sc, DC_FRAMESDISCARDED); 3086 ifp->if_ierrors += (r & 0xffff) + ((r >> 17) & 0x7ff); 3087 3088 if (dc_rx_resync(sc)) 3089 dc_rxeof(sc); 3090 } 3091 /* restart transmit unit if necessary */ 3092 if (status & DC_ISR_TX_IDLE && sc->dc_cdata.dc_tx_cnt) 3093 CSR_WRITE_4(sc, DC_TXSTART, 0xFFFFFFFF); 3094 3095 if (status & DC_ISR_TX_UNDERRUN) 3096 dc_tx_underrun(sc); 3097 3098 if (status & DC_ISR_BUS_ERR) { 3099 if_printf(ifp, "dc_poll: bus error\n"); 3100 dc_reset(sc); 3101 dc_init_locked(sc); 3102 } 3103 } 3104 DC_UNLOCK(sc); 3105 } 3106 #endif /* DEVICE_POLLING */ 3107 3108 static void 3109 dc_intr(void *arg) 3110 { 3111 struct dc_softc *sc; 3112 struct ifnet *ifp; 3113 u_int32_t status; 3114 3115 sc = arg; 3116 3117 if (sc->suspended) 3118 return; 3119 3120 if ((CSR_READ_4(sc, DC_ISR) & DC_INTRS) == 0) 3121 return; 3122 3123 DC_LOCK(sc); 3124 ifp = sc->dc_ifp; 3125 #ifdef DEVICE_POLLING 3126 if (ifp->if_capenable & IFCAP_POLLING) { 3127 DC_UNLOCK(sc); 3128 return; 3129 } 3130 #endif 3131 3132 /* Suppress unwanted interrupts */ 3133 if (!(ifp->if_flags & IFF_UP)) { 3134 if (CSR_READ_4(sc, DC_ISR) & DC_INTRS) 3135 dc_stop(sc); 3136 DC_UNLOCK(sc); 3137 return; 3138 } 3139 3140 /* Disable interrupts. */ 3141 CSR_WRITE_4(sc, DC_IMR, 0x00000000); 3142 3143 while (((status = CSR_READ_4(sc, DC_ISR)) & DC_INTRS) && 3144 status != 0xFFFFFFFF && 3145 (ifp->if_drv_flags & IFF_DRV_RUNNING)) { 3146 3147 CSR_WRITE_4(sc, DC_ISR, status); 3148 3149 if (status & DC_ISR_RX_OK) { 3150 int curpkts; 3151 curpkts = ifp->if_ipackets; 3152 dc_rxeof(sc); 3153 if (curpkts == ifp->if_ipackets) { 3154 while (dc_rx_resync(sc)) 3155 dc_rxeof(sc); 3156 } 3157 } 3158 3159 if (status & (DC_ISR_TX_OK | DC_ISR_TX_NOBUF)) 3160 dc_txeof(sc); 3161 3162 if (status & DC_ISR_TX_IDLE) { 3163 dc_txeof(sc); 3164 if (sc->dc_cdata.dc_tx_cnt) { 3165 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_TX_ON); 3166 CSR_WRITE_4(sc, DC_TXSTART, 0xFFFFFFFF); 3167 } 3168 } 3169 3170 if (status & DC_ISR_TX_UNDERRUN) 3171 dc_tx_underrun(sc); 3172 3173 if ((status & DC_ISR_RX_WATDOGTIMEO) 3174 || (status & DC_ISR_RX_NOBUF)) { 3175 int curpkts; 3176 curpkts = ifp->if_ipackets; 3177 dc_rxeof(sc); 3178 if (curpkts == ifp->if_ipackets) { 3179 while (dc_rx_resync(sc)) 3180 dc_rxeof(sc); 3181 } 3182 } 3183 3184 if (status & DC_ISR_BUS_ERR) { 3185 dc_reset(sc); 3186 dc_init_locked(sc); 3187 } 3188 } 3189 3190 /* Re-enable interrupts. */ 3191 CSR_WRITE_4(sc, DC_IMR, DC_INTRS); 3192 3193 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 3194 dc_start_locked(ifp); 3195 3196 DC_UNLOCK(sc); 3197 } 3198 3199 static void 3200 dc_dma_map_txbuf(arg, segs, nseg, mapsize, error) 3201 void *arg; 3202 bus_dma_segment_t *segs; 3203 int nseg; 3204 bus_size_t mapsize; 3205 int error; 3206 { 3207 struct dc_softc *sc; 3208 struct dc_desc *f; 3209 int cur, first, frag, i; 3210 3211 sc = arg; 3212 if (error) { 3213 sc->dc_cdata.dc_tx_err = error; 3214 return; 3215 } 3216 3217 first = cur = frag = sc->dc_cdata.dc_tx_prod; 3218 for (i = 0; i < nseg; i++) { 3219 if ((sc->dc_flags & DC_TX_ADMTEK_WAR) && 3220 (frag == (DC_TX_LIST_CNT - 1)) && 3221 (first != sc->dc_cdata.dc_tx_first)) { 3222 bus_dmamap_unload(sc->dc_mtag, 3223 sc->dc_cdata.dc_tx_map[first]); 3224 sc->dc_cdata.dc_tx_err = ENOBUFS; 3225 return; 3226 } 3227 3228 f = &sc->dc_ldata->dc_tx_list[frag]; 3229 f->dc_ctl = htole32(DC_TXCTL_TLINK | segs[i].ds_len); 3230 if (i == 0) { 3231 f->dc_status = 0; 3232 f->dc_ctl |= htole32(DC_TXCTL_FIRSTFRAG); 3233 } else 3234 f->dc_status = htole32(DC_TXSTAT_OWN); 3235 f->dc_data = htole32(segs[i].ds_addr); 3236 cur = frag; 3237 DC_INC(frag, DC_TX_LIST_CNT); 3238 } 3239 3240 sc->dc_cdata.dc_tx_err = 0; 3241 sc->dc_cdata.dc_tx_prod = frag; 3242 sc->dc_cdata.dc_tx_cnt += nseg; 3243 sc->dc_ldata->dc_tx_list[cur].dc_ctl |= htole32(DC_TXCTL_LASTFRAG); 3244 sc->dc_cdata.dc_tx_chain[cur] = sc->dc_cdata.dc_tx_mapping; 3245 if (sc->dc_flags & DC_TX_INTR_FIRSTFRAG) 3246 sc->dc_ldata->dc_tx_list[first].dc_ctl |= 3247 htole32(DC_TXCTL_FINT); 3248 if (sc->dc_flags & DC_TX_INTR_ALWAYS) 3249 sc->dc_ldata->dc_tx_list[cur].dc_ctl |= htole32(DC_TXCTL_FINT); 3250 if (sc->dc_flags & DC_TX_USE_TX_INTR && sc->dc_cdata.dc_tx_cnt > 64) 3251 sc->dc_ldata->dc_tx_list[cur].dc_ctl |= htole32(DC_TXCTL_FINT); 3252 sc->dc_ldata->dc_tx_list[first].dc_status = htole32(DC_TXSTAT_OWN); 3253 } 3254 3255 /* 3256 * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data 3257 * pointers to the fragment pointers. 3258 */ 3259 static int 3260 dc_encap(struct dc_softc *sc, struct mbuf **m_head) 3261 { 3262 struct mbuf *m; 3263 int error, idx, chainlen = 0; 3264 3265 /* 3266 * If there's no way we can send any packets, return now. 3267 */ 3268 if (DC_TX_LIST_CNT - sc->dc_cdata.dc_tx_cnt < 6) 3269 return (ENOBUFS); 3270 3271 /* 3272 * Count the number of frags in this chain to see if 3273 * we need to m_defrag. Since the descriptor list is shared 3274 * by all packets, we'll m_defrag long chains so that they 3275 * do not use up the entire list, even if they would fit. 3276 */ 3277 for (m = *m_head; m != NULL; m = m->m_next) 3278 chainlen++; 3279 3280 if ((chainlen > DC_TX_LIST_CNT / 4) || 3281 ((DC_TX_LIST_CNT - (chainlen + sc->dc_cdata.dc_tx_cnt)) < 6)) { 3282 m = m_defrag(*m_head, M_DONTWAIT); 3283 if (m == NULL) 3284 return (ENOBUFS); 3285 *m_head = m; 3286 } 3287 3288 /* 3289 * Start packing the mbufs in this chain into 3290 * the fragment pointers. Stop when we run out 3291 * of fragments or hit the end of the mbuf chain. 3292 */ 3293 idx = sc->dc_cdata.dc_tx_prod; 3294 sc->dc_cdata.dc_tx_mapping = *m_head; 3295 error = bus_dmamap_load_mbuf(sc->dc_mtag, sc->dc_cdata.dc_tx_map[idx], 3296 *m_head, dc_dma_map_txbuf, sc, 0); 3297 if (error) 3298 return (error); 3299 if (sc->dc_cdata.dc_tx_err != 0) 3300 return (sc->dc_cdata.dc_tx_err); 3301 bus_dmamap_sync(sc->dc_mtag, sc->dc_cdata.dc_tx_map[idx], 3302 BUS_DMASYNC_PREWRITE); 3303 bus_dmamap_sync(sc->dc_ltag, sc->dc_lmap, 3304 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3305 return (0); 3306 } 3307 3308 /* 3309 * Main transmit routine. To avoid having to do mbuf copies, we put pointers 3310 * to the mbuf data regions directly in the transmit lists. We also save a 3311 * copy of the pointers since the transmit list fragment pointers are 3312 * physical addresses. 3313 */ 3314 3315 static void 3316 dc_start(struct ifnet *ifp) 3317 { 3318 struct dc_softc *sc; 3319 3320 sc = ifp->if_softc; 3321 DC_LOCK(sc); 3322 dc_start_locked(ifp); 3323 DC_UNLOCK(sc); 3324 } 3325 3326 static void 3327 dc_start_locked(struct ifnet *ifp) 3328 { 3329 struct dc_softc *sc; 3330 struct mbuf *m_head = NULL, *m; 3331 unsigned int queued = 0; 3332 int idx; 3333 3334 sc = ifp->if_softc; 3335 3336 DC_LOCK_ASSERT(sc); 3337 3338 if (!sc->dc_link && ifp->if_snd.ifq_len < 10) 3339 return; 3340 3341 if (ifp->if_drv_flags & IFF_DRV_OACTIVE) 3342 return; 3343 3344 idx = sc->dc_cdata.dc_tx_first = sc->dc_cdata.dc_tx_prod; 3345 3346 while (sc->dc_cdata.dc_tx_chain[idx] == NULL) { 3347 IFQ_DRV_DEQUEUE(&ifp->if_snd, m_head); 3348 if (m_head == NULL) 3349 break; 3350 3351 if (sc->dc_flags & DC_TX_COALESCE && 3352 (m_head->m_next != NULL || 3353 sc->dc_flags & DC_TX_ALIGN)) { 3354 m = m_defrag(m_head, M_DONTWAIT); 3355 if (m == NULL) { 3356 IFQ_DRV_PREPEND(&ifp->if_snd, m_head); 3357 ifp->if_drv_flags |= IFF_DRV_OACTIVE; 3358 break; 3359 } else { 3360 m_head = m; 3361 } 3362 } 3363 3364 if (dc_encap(sc, &m_head)) { 3365 IFQ_DRV_PREPEND(&ifp->if_snd, m_head); 3366 ifp->if_drv_flags |= IFF_DRV_OACTIVE; 3367 break; 3368 } 3369 idx = sc->dc_cdata.dc_tx_prod; 3370 3371 queued++; 3372 /* 3373 * If there's a BPF listener, bounce a copy of this frame 3374 * to him. 3375 */ 3376 BPF_MTAP(ifp, m_head); 3377 3378 if (sc->dc_flags & DC_TX_ONE) { 3379 ifp->if_drv_flags |= IFF_DRV_OACTIVE; 3380 break; 3381 } 3382 } 3383 3384 if (queued > 0) { 3385 /* Transmit */ 3386 if (!(sc->dc_flags & DC_TX_POLL)) 3387 CSR_WRITE_4(sc, DC_TXSTART, 0xFFFFFFFF); 3388 3389 /* 3390 * Set a timeout in case the chip goes out to lunch. 3391 */ 3392 ifp->if_timer = 5; 3393 } 3394 } 3395 3396 static void 3397 dc_init(void *xsc) 3398 { 3399 struct dc_softc *sc = xsc; 3400 3401 DC_LOCK(sc); 3402 dc_init_locked(sc); 3403 #ifdef SRM_MEDIA 3404 if(sc->dc_srm_media) { 3405 struct ifreq ifr; 3406 struct mii_data *mii; 3407 3408 ifr.ifr_media = sc->dc_srm_media; 3409 sc->dc_srm_media = 0; 3410 DC_UNLOCK(sc); 3411 mii = device_get_softc(sc->dc_miibus); 3412 ifmedia_ioctl(sc->dc_ifp, &ifr, &mii->mii_media, SIOCSIFMEDIA); 3413 } else 3414 #endif 3415 DC_UNLOCK(sc); 3416 } 3417 3418 static void 3419 dc_init_locked(struct dc_softc *sc) 3420 { 3421 struct ifnet *ifp = sc->dc_ifp; 3422 struct mii_data *mii; 3423 3424 DC_LOCK_ASSERT(sc); 3425 3426 mii = device_get_softc(sc->dc_miibus); 3427 3428 /* 3429 * Cancel pending I/O and free all RX/TX buffers. 3430 */ 3431 dc_stop(sc); 3432 dc_reset(sc); 3433 3434 /* 3435 * Set cache alignment and burst length. 3436 */ 3437 if (DC_IS_ASIX(sc) || DC_IS_DAVICOM(sc)) 3438 CSR_WRITE_4(sc, DC_BUSCTL, 0); 3439 else 3440 CSR_WRITE_4(sc, DC_BUSCTL, DC_BUSCTL_MRME | DC_BUSCTL_MRLE); 3441 /* 3442 * Evenly share the bus between receive and transmit process. 3443 */ 3444 if (DC_IS_INTEL(sc)) 3445 DC_SETBIT(sc, DC_BUSCTL, DC_BUSCTL_ARBITRATION); 3446 if (DC_IS_DAVICOM(sc) || DC_IS_INTEL(sc)) { 3447 DC_SETBIT(sc, DC_BUSCTL, DC_BURSTLEN_USECA); 3448 } else { 3449 DC_SETBIT(sc, DC_BUSCTL, DC_BURSTLEN_16LONG); 3450 } 3451 if (sc->dc_flags & DC_TX_POLL) 3452 DC_SETBIT(sc, DC_BUSCTL, DC_TXPOLL_1); 3453 switch(sc->dc_cachesize) { 3454 case 32: 3455 DC_SETBIT(sc, DC_BUSCTL, DC_CACHEALIGN_32LONG); 3456 break; 3457 case 16: 3458 DC_SETBIT(sc, DC_BUSCTL, DC_CACHEALIGN_16LONG); 3459 break; 3460 case 8: 3461 DC_SETBIT(sc, DC_BUSCTL, DC_CACHEALIGN_8LONG); 3462 break; 3463 case 0: 3464 default: 3465 DC_SETBIT(sc, DC_BUSCTL, DC_CACHEALIGN_NONE); 3466 break; 3467 } 3468 3469 if (sc->dc_flags & DC_TX_STORENFWD) 3470 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_STORENFWD); 3471 else { 3472 if (sc->dc_txthresh > DC_TXTHRESH_MAX) { 3473 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_STORENFWD); 3474 } else { 3475 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_STORENFWD); 3476 DC_SETBIT(sc, DC_NETCFG, sc->dc_txthresh); 3477 } 3478 } 3479 3480 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_NO_RXCRC); 3481 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_TX_BACKOFF); 3482 3483 if (DC_IS_MACRONIX(sc) || DC_IS_PNICII(sc)) { 3484 /* 3485 * The app notes for the 98713 and 98715A say that 3486 * in order to have the chips operate properly, a magic 3487 * number must be written to CSR16. Macronix does not 3488 * document the meaning of these bits so there's no way 3489 * to know exactly what they do. The 98713 has a magic 3490 * number all its own; the rest all use a different one. 3491 */ 3492 DC_CLRBIT(sc, DC_MX_MAGICPACKET, 0xFFFF0000); 3493 if (sc->dc_type == DC_TYPE_98713) 3494 DC_SETBIT(sc, DC_MX_MAGICPACKET, DC_MX_MAGIC_98713); 3495 else 3496 DC_SETBIT(sc, DC_MX_MAGICPACKET, DC_MX_MAGIC_98715); 3497 } 3498 3499 if (DC_IS_XIRCOM(sc)) { 3500 /* 3501 * setup General Purpose Port mode and data so the tulip 3502 * can talk to the MII. 3503 */ 3504 CSR_WRITE_4(sc, DC_SIAGP, DC_SIAGP_WRITE_EN | DC_SIAGP_INT1_EN | 3505 DC_SIAGP_MD_GP2_OUTPUT | DC_SIAGP_MD_GP0_OUTPUT); 3506 DELAY(10); 3507 CSR_WRITE_4(sc, DC_SIAGP, DC_SIAGP_INT1_EN | 3508 DC_SIAGP_MD_GP2_OUTPUT | DC_SIAGP_MD_GP0_OUTPUT); 3509 DELAY(10); 3510 } 3511 3512 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_TX_THRESH); 3513 DC_SETBIT(sc, DC_NETCFG, DC_TXTHRESH_MIN); 3514 3515 /* Init circular RX list. */ 3516 if (dc_list_rx_init(sc) == ENOBUFS) { 3517 if_printf(ifp, 3518 "initialization failed: no memory for rx buffers\n"); 3519 dc_stop(sc); 3520 return; 3521 } 3522 3523 /* 3524 * Init TX descriptors. 3525 */ 3526 dc_list_tx_init(sc); 3527 3528 /* 3529 * Load the address of the RX list. 3530 */ 3531 CSR_WRITE_4(sc, DC_RXADDR, DC_RXDESC(sc, 0)); 3532 CSR_WRITE_4(sc, DC_TXADDR, DC_TXDESC(sc, 0)); 3533 3534 /* 3535 * Enable interrupts. 3536 */ 3537 #ifdef DEVICE_POLLING 3538 /* 3539 * ... but only if we are not polling, and make sure they are off in 3540 * the case of polling. Some cards (e.g. fxp) turn interrupts on 3541 * after a reset. 3542 */ 3543 if (ifp->if_capenable & IFCAP_POLLING) 3544 CSR_WRITE_4(sc, DC_IMR, 0x00000000); 3545 else 3546 #endif 3547 CSR_WRITE_4(sc, DC_IMR, DC_INTRS); 3548 CSR_WRITE_4(sc, DC_ISR, 0xFFFFFFFF); 3549 3550 /* Enable transmitter. */ 3551 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_TX_ON); 3552 3553 /* 3554 * If this is an Intel 21143 and we're not using the 3555 * MII port, program the LED control pins so we get 3556 * link and activity indications. 3557 */ 3558 if (sc->dc_flags & DC_TULIP_LEDS) { 3559 CSR_WRITE_4(sc, DC_WATCHDOG, 3560 DC_WDOG_CTLWREN | DC_WDOG_LINK | DC_WDOG_ACTIVITY); 3561 CSR_WRITE_4(sc, DC_WATCHDOG, 0); 3562 } 3563 3564 /* 3565 * Load the RX/multicast filter. We do this sort of late 3566 * because the filter programming scheme on the 21143 and 3567 * some clones requires DMAing a setup frame via the TX 3568 * engine, and we need the transmitter enabled for that. 3569 */ 3570 dc_setfilt(sc); 3571 3572 /* Enable receiver. */ 3573 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_ON); 3574 CSR_WRITE_4(sc, DC_RXSTART, 0xFFFFFFFF); 3575 3576 mii_mediachg(mii); 3577 dc_setcfg(sc, sc->dc_if_media); 3578 3579 ifp->if_drv_flags |= IFF_DRV_RUNNING; 3580 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 3581 3582 /* Don't start the ticker if this is a homePNA link. */ 3583 if (IFM_SUBTYPE(mii->mii_media.ifm_media) == IFM_HPNA_1) 3584 sc->dc_link = 1; 3585 else { 3586 if (sc->dc_flags & DC_21143_NWAY) 3587 callout_reset(&sc->dc_stat_ch, hz/10, dc_tick, sc); 3588 else 3589 callout_reset(&sc->dc_stat_ch, hz, dc_tick, sc); 3590 } 3591 } 3592 3593 /* 3594 * Set media options. 3595 */ 3596 static int 3597 dc_ifmedia_upd(struct ifnet *ifp) 3598 { 3599 struct dc_softc *sc; 3600 struct mii_data *mii; 3601 struct ifmedia *ifm; 3602 3603 sc = ifp->if_softc; 3604 mii = device_get_softc(sc->dc_miibus); 3605 DC_LOCK(sc); 3606 mii_mediachg(mii); 3607 ifm = &mii->mii_media; 3608 3609 if (DC_IS_DAVICOM(sc) && 3610 IFM_SUBTYPE(ifm->ifm_media) == IFM_HPNA_1) 3611 dc_setcfg(sc, ifm->ifm_media); 3612 else 3613 sc->dc_link = 0; 3614 DC_UNLOCK(sc); 3615 3616 return (0); 3617 } 3618 3619 /* 3620 * Report current media status. 3621 */ 3622 static void 3623 dc_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 3624 { 3625 struct dc_softc *sc; 3626 struct mii_data *mii; 3627 struct ifmedia *ifm; 3628 3629 sc = ifp->if_softc; 3630 mii = device_get_softc(sc->dc_miibus); 3631 DC_LOCK(sc); 3632 mii_pollstat(mii); 3633 ifm = &mii->mii_media; 3634 if (DC_IS_DAVICOM(sc)) { 3635 if (IFM_SUBTYPE(ifm->ifm_media) == IFM_HPNA_1) { 3636 ifmr->ifm_active = ifm->ifm_media; 3637 ifmr->ifm_status = 0; 3638 return; 3639 } 3640 } 3641 ifmr->ifm_active = mii->mii_media_active; 3642 ifmr->ifm_status = mii->mii_media_status; 3643 DC_UNLOCK(sc); 3644 } 3645 3646 static int 3647 dc_ioctl(struct ifnet *ifp, u_long command, caddr_t data) 3648 { 3649 struct dc_softc *sc = ifp->if_softc; 3650 struct ifreq *ifr = (struct ifreq *)data; 3651 struct mii_data *mii; 3652 int error = 0; 3653 3654 switch (command) { 3655 case SIOCSIFFLAGS: 3656 DC_LOCK(sc); 3657 if (ifp->if_flags & IFF_UP) { 3658 int need_setfilt = (ifp->if_flags ^ sc->dc_if_flags) & 3659 (IFF_PROMISC | IFF_ALLMULTI); 3660 3661 if (ifp->if_drv_flags & IFF_DRV_RUNNING) { 3662 if (need_setfilt) 3663 dc_setfilt(sc); 3664 } else { 3665 sc->dc_txthresh = 0; 3666 dc_init_locked(sc); 3667 } 3668 } else { 3669 if (ifp->if_drv_flags & IFF_DRV_RUNNING) 3670 dc_stop(sc); 3671 } 3672 sc->dc_if_flags = ifp->if_flags; 3673 DC_UNLOCK(sc); 3674 error = 0; 3675 break; 3676 case SIOCADDMULTI: 3677 case SIOCDELMULTI: 3678 DC_LOCK(sc); 3679 dc_setfilt(sc); 3680 DC_UNLOCK(sc); 3681 error = 0; 3682 break; 3683 case SIOCGIFMEDIA: 3684 case SIOCSIFMEDIA: 3685 mii = device_get_softc(sc->dc_miibus); 3686 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 3687 #ifdef SRM_MEDIA 3688 DC_LOCK(sc); 3689 if (sc->dc_srm_media) 3690 sc->dc_srm_media = 0; 3691 DC_UNLOCK(sc); 3692 #endif 3693 break; 3694 case SIOCSIFCAP: 3695 #ifdef DEVICE_POLLING 3696 if (ifr->ifr_reqcap & IFCAP_POLLING && 3697 !(ifp->if_capenable & IFCAP_POLLING)) { 3698 error = ether_poll_register(dc_poll, ifp); 3699 if (error) 3700 return(error); 3701 DC_LOCK(sc); 3702 /* Disable interrupts */ 3703 CSR_WRITE_4(sc, DC_IMR, 0x00000000); 3704 ifp->if_capenable |= IFCAP_POLLING; 3705 DC_UNLOCK(sc); 3706 return (error); 3707 3708 } 3709 if (!(ifr->ifr_reqcap & IFCAP_POLLING) && 3710 ifp->if_capenable & IFCAP_POLLING) { 3711 error = ether_poll_deregister(ifp); 3712 /* Enable interrupts. */ 3713 DC_LOCK(sc); 3714 CSR_WRITE_4(sc, DC_IMR, DC_INTRS); 3715 ifp->if_capenable &= ~IFCAP_POLLING; 3716 DC_UNLOCK(sc); 3717 return (error); 3718 } 3719 #endif /* DEVICE_POLLING */ 3720 break; 3721 default: 3722 error = ether_ioctl(ifp, command, data); 3723 break; 3724 } 3725 3726 return (error); 3727 } 3728 3729 static void 3730 dc_watchdog(struct ifnet *ifp) 3731 { 3732 struct dc_softc *sc; 3733 3734 sc = ifp->if_softc; 3735 3736 DC_LOCK(sc); 3737 3738 ifp->if_oerrors++; 3739 if_printf(ifp, "watchdog timeout\n"); 3740 3741 dc_stop(sc); 3742 dc_reset(sc); 3743 dc_init_locked(sc); 3744 3745 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 3746 dc_start_locked(ifp); 3747 3748 DC_UNLOCK(sc); 3749 } 3750 3751 /* 3752 * Stop the adapter and free any mbufs allocated to the 3753 * RX and TX lists. 3754 */ 3755 static void 3756 dc_stop(struct dc_softc *sc) 3757 { 3758 struct ifnet *ifp; 3759 struct dc_list_data *ld; 3760 struct dc_chain_data *cd; 3761 int i; 3762 u_int32_t ctl; 3763 3764 DC_LOCK_ASSERT(sc); 3765 3766 ifp = sc->dc_ifp; 3767 ifp->if_timer = 0; 3768 ld = sc->dc_ldata; 3769 cd = &sc->dc_cdata; 3770 3771 callout_stop(&sc->dc_stat_ch); 3772 3773 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE); 3774 3775 DC_CLRBIT(sc, DC_NETCFG, (DC_NETCFG_RX_ON | DC_NETCFG_TX_ON)); 3776 CSR_WRITE_4(sc, DC_IMR, 0x00000000); 3777 CSR_WRITE_4(sc, DC_TXADDR, 0x00000000); 3778 CSR_WRITE_4(sc, DC_RXADDR, 0x00000000); 3779 sc->dc_link = 0; 3780 3781 /* 3782 * Free data in the RX lists. 3783 */ 3784 for (i = 0; i < DC_RX_LIST_CNT; i++) { 3785 if (cd->dc_rx_chain[i] != NULL) { 3786 m_freem(cd->dc_rx_chain[i]); 3787 cd->dc_rx_chain[i] = NULL; 3788 } 3789 } 3790 bzero(&ld->dc_rx_list, sizeof(ld->dc_rx_list)); 3791 3792 /* 3793 * Free the TX list buffers. 3794 */ 3795 for (i = 0; i < DC_TX_LIST_CNT; i++) { 3796 if (cd->dc_tx_chain[i] != NULL) { 3797 ctl = le32toh(ld->dc_tx_list[i].dc_ctl); 3798 if ((ctl & DC_TXCTL_SETUP) || 3799 !(ctl & DC_TXCTL_LASTFRAG)) { 3800 cd->dc_tx_chain[i] = NULL; 3801 continue; 3802 } 3803 bus_dmamap_unload(sc->dc_mtag, cd->dc_tx_map[i]); 3804 m_freem(cd->dc_tx_chain[i]); 3805 cd->dc_tx_chain[i] = NULL; 3806 } 3807 } 3808 bzero(&ld->dc_tx_list, sizeof(ld->dc_tx_list)); 3809 } 3810 3811 /* 3812 * Device suspend routine. Stop the interface and save some PCI 3813 * settings in case the BIOS doesn't restore them properly on 3814 * resume. 3815 */ 3816 static int 3817 dc_suspend(device_t dev) 3818 { 3819 struct dc_softc *sc; 3820 3821 sc = device_get_softc(dev); 3822 DC_LOCK(sc); 3823 dc_stop(sc); 3824 sc->suspended = 1; 3825 DC_UNLOCK(sc); 3826 3827 return (0); 3828 } 3829 3830 /* 3831 * Device resume routine. Restore some PCI settings in case the BIOS 3832 * doesn't, re-enable busmastering, and restart the interface if 3833 * appropriate. 3834 */ 3835 static int 3836 dc_resume(device_t dev) 3837 { 3838 struct dc_softc *sc; 3839 struct ifnet *ifp; 3840 3841 sc = device_get_softc(dev); 3842 ifp = sc->dc_ifp; 3843 3844 /* reinitialize interface if necessary */ 3845 DC_LOCK(sc); 3846 if (ifp->if_flags & IFF_UP) 3847 dc_init_locked(sc); 3848 3849 sc->suspended = 0; 3850 DC_UNLOCK(sc); 3851 3852 return (0); 3853 } 3854 3855 /* 3856 * Stop all chip I/O so that the kernel's probe routines don't 3857 * get confused by errant DMAs when rebooting. 3858 */ 3859 static void 3860 dc_shutdown(device_t dev) 3861 { 3862 struct dc_softc *sc; 3863 3864 sc = device_get_softc(dev); 3865 3866 DC_LOCK(sc); 3867 dc_stop(sc); 3868 DC_UNLOCK(sc); 3869 } 3870