1 /*- 2 * SPDX-License-Identifier: BSD-4-Clause 3 * 4 * Copyright (c) 1997, 1998, 1999 5 * Bill Paul <wpaul@ee.columbia.edu>. All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed by Bill Paul. 18 * 4. Neither the name of the author nor the names of any co-contributors 19 * may be used to endorse or promote products derived from this software 20 * without specific prior written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 23 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 25 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 26 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 27 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 28 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 29 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 30 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 31 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 32 * THE POSSIBILITY OF SUCH DAMAGE. 33 */ 34 35 #include <sys/cdefs.h> 36 __FBSDID("$FreeBSD$"); 37 38 /* 39 * DEC "tulip" clone ethernet driver. Supports the DEC/Intel 21143 40 * series chips and several workalikes including the following: 41 * 42 * Macronix 98713/98715/98725/98727/98732 PMAC (www.macronix.com) 43 * Macronix/Lite-On 82c115 PNIC II (www.macronix.com) 44 * Lite-On 82c168/82c169 PNIC (www.litecom.com) 45 * ASIX Electronics AX88140A (www.asix.com.tw) 46 * ASIX Electronics AX88141 (www.asix.com.tw) 47 * ADMtek AL981 (www.admtek.com.tw) 48 * ADMtek AN983 (www.admtek.com.tw) 49 * ADMtek CardBus AN985 (www.admtek.com.tw) 50 * Netgear FA511 (www.netgear.com) Appears to be rebadged ADMTek CardBus AN985 51 * Davicom DM9100, DM9102, DM9102A (www.davicom8.com) 52 * Accton EN1217 (www.accton.com) 53 * Xircom X3201 (www.xircom.com) 54 * Abocom FE2500 55 * Conexant LANfinity (www.conexant.com) 56 * 3Com OfficeConnect 10/100B 3CSOHO100B (www.3com.com) 57 * 58 * Datasheets for the 21143 are available at developer.intel.com. 59 * Datasheets for the clone parts can be found at their respective sites. 60 * (Except for the PNIC; see www.freebsd.org/~wpaul/PNIC/pnic.ps.gz.) 61 * The PNIC II is essentially a Macronix 98715A chip; the only difference 62 * worth noting is that its multicast hash table is only 128 bits wide 63 * instead of 512. 64 * 65 * Written by Bill Paul <wpaul@ee.columbia.edu> 66 * Electrical Engineering Department 67 * Columbia University, New York City 68 */ 69 /* 70 * The Intel 21143 is the successor to the DEC 21140. It is basically 71 * the same as the 21140 but with a few new features. The 21143 supports 72 * three kinds of media attachments: 73 * 74 * o MII port, for 10Mbps and 100Mbps support and NWAY 75 * autonegotiation provided by an external PHY. 76 * o SYM port, for symbol mode 100Mbps support. 77 * o 10baseT port. 78 * o AUI/BNC port. 79 * 80 * The 100Mbps SYM port and 10baseT port can be used together in 81 * combination with the internal NWAY support to create a 10/100 82 * autosensing configuration. 83 * 84 * Note that not all tulip workalikes are handled in this driver: we only 85 * deal with those which are relatively well behaved. The Winbond is 86 * handled separately due to its different register offsets and the 87 * special handling needed for its various bugs. The PNIC is handled 88 * here, but I'm not thrilled about it. 89 * 90 * All of the workalike chips use some form of MII transceiver support 91 * with the exception of the Macronix chips, which also have a SYM port. 92 * The ASIX AX88140A is also documented to have a SYM port, but all 93 * the cards I've seen use an MII transceiver, probably because the 94 * AX88140A doesn't support internal NWAY. 95 */ 96 97 #ifdef HAVE_KERNEL_OPTION_HEADERS 98 #include "opt_device_polling.h" 99 #endif 100 101 #include <sys/param.h> 102 #include <sys/endian.h> 103 #include <sys/systm.h> 104 #include <sys/sockio.h> 105 #include <sys/mbuf.h> 106 #include <sys/malloc.h> 107 #include <sys/kernel.h> 108 #include <sys/module.h> 109 #include <sys/socket.h> 110 111 #include <net/if.h> 112 #include <net/if_var.h> 113 #include <net/if_arp.h> 114 #include <net/ethernet.h> 115 #include <net/if_dl.h> 116 #include <net/if_media.h> 117 #include <net/if_types.h> 118 #include <net/if_vlan_var.h> 119 120 #include <net/bpf.h> 121 122 #include <machine/bus.h> 123 #include <machine/resource.h> 124 #include <sys/bus.h> 125 #include <sys/rman.h> 126 127 #include <dev/mii/mii.h> 128 #include <dev/mii/mii_bitbang.h> 129 #include <dev/mii/miivar.h> 130 131 #include <dev/pci/pcireg.h> 132 #include <dev/pci/pcivar.h> 133 134 #define DC_USEIOSPACE 135 136 #include <dev/dc/if_dcreg.h> 137 138 MODULE_DEPEND(dc, pci, 1, 1, 1); 139 MODULE_DEPEND(dc, ether, 1, 1, 1); 140 MODULE_DEPEND(dc, miibus, 1, 1, 1); 141 142 /* 143 * "device miibus" is required in kernel config. See GENERIC if you get 144 * errors here. 145 */ 146 #include "miibus_if.h" 147 148 /* 149 * Various supported device vendors/types and their names. 150 */ 151 static const struct dc_type dc_devs[] = { 152 { DC_DEVID(DC_VENDORID_DEC, DC_DEVICEID_21143), 0, 153 "Intel 21143 10/100BaseTX" }, 154 { DC_DEVID(DC_VENDORID_DAVICOM, DC_DEVICEID_DM9009), 0, 155 "Davicom DM9009 10/100BaseTX" }, 156 { DC_DEVID(DC_VENDORID_DAVICOM, DC_DEVICEID_DM9100), 0, 157 "Davicom DM9100 10/100BaseTX" }, 158 { DC_DEVID(DC_VENDORID_DAVICOM, DC_DEVICEID_DM9102), DC_REVISION_DM9102A, 159 "Davicom DM9102A 10/100BaseTX" }, 160 { DC_DEVID(DC_VENDORID_DAVICOM, DC_DEVICEID_DM9102), 0, 161 "Davicom DM9102 10/100BaseTX" }, 162 { DC_DEVID(DC_VENDORID_ADMTEK, DC_DEVICEID_AL981), 0, 163 "ADMtek AL981 10/100BaseTX" }, 164 { DC_DEVID(DC_VENDORID_ADMTEK, DC_DEVICEID_AN983), 0, 165 "ADMtek AN983 10/100BaseTX" }, 166 { DC_DEVID(DC_VENDORID_ADMTEK, DC_DEVICEID_AN985), 0, 167 "ADMtek AN985 CardBus 10/100BaseTX or clone" }, 168 { DC_DEVID(DC_VENDORID_ADMTEK, DC_DEVICEID_ADM9511), 0, 169 "ADMtek ADM9511 10/100BaseTX" }, 170 { DC_DEVID(DC_VENDORID_ADMTEK, DC_DEVICEID_ADM9513), 0, 171 "ADMtek ADM9513 10/100BaseTX" }, 172 { DC_DEVID(DC_VENDORID_ASIX, DC_DEVICEID_AX88140A), DC_REVISION_88141, 173 "ASIX AX88141 10/100BaseTX" }, 174 { DC_DEVID(DC_VENDORID_ASIX, DC_DEVICEID_AX88140A), 0, 175 "ASIX AX88140A 10/100BaseTX" }, 176 { DC_DEVID(DC_VENDORID_MX, DC_DEVICEID_98713), DC_REVISION_98713A, 177 "Macronix 98713A 10/100BaseTX" }, 178 { DC_DEVID(DC_VENDORID_MX, DC_DEVICEID_98713), 0, 179 "Macronix 98713 10/100BaseTX" }, 180 { DC_DEVID(DC_VENDORID_CP, DC_DEVICEID_98713_CP), DC_REVISION_98713A, 181 "Compex RL100-TX 10/100BaseTX" }, 182 { DC_DEVID(DC_VENDORID_CP, DC_DEVICEID_98713_CP), 0, 183 "Compex RL100-TX 10/100BaseTX" }, 184 { DC_DEVID(DC_VENDORID_MX, DC_DEVICEID_987x5), DC_REVISION_98725, 185 "Macronix 98725 10/100BaseTX" }, 186 { DC_DEVID(DC_VENDORID_MX, DC_DEVICEID_987x5), DC_REVISION_98715AEC_C, 187 "Macronix 98715AEC-C 10/100BaseTX" }, 188 { DC_DEVID(DC_VENDORID_MX, DC_DEVICEID_987x5), 0, 189 "Macronix 98715/98715A 10/100BaseTX" }, 190 { DC_DEVID(DC_VENDORID_MX, DC_DEVICEID_98727), 0, 191 "Macronix 98727/98732 10/100BaseTX" }, 192 { DC_DEVID(DC_VENDORID_LO, DC_DEVICEID_82C115), 0, 193 "LC82C115 PNIC II 10/100BaseTX" }, 194 { DC_DEVID(DC_VENDORID_LO, DC_DEVICEID_82C168), DC_REVISION_82C169, 195 "82c169 PNIC 10/100BaseTX" }, 196 { DC_DEVID(DC_VENDORID_LO, DC_DEVICEID_82C168), 0, 197 "82c168 PNIC 10/100BaseTX" }, 198 { DC_DEVID(DC_VENDORID_ACCTON, DC_DEVICEID_EN1217), 0, 199 "Accton EN1217 10/100BaseTX" }, 200 { DC_DEVID(DC_VENDORID_ACCTON, DC_DEVICEID_EN2242), 0, 201 "Accton EN2242 MiniPCI 10/100BaseTX" }, 202 { DC_DEVID(DC_VENDORID_XIRCOM, DC_DEVICEID_X3201), 0, 203 "Xircom X3201 10/100BaseTX" }, 204 { DC_DEVID(DC_VENDORID_DLINK, DC_DEVICEID_DRP32TXD), 0, 205 "Neteasy DRP-32TXD Cardbus 10/100" }, 206 { DC_DEVID(DC_VENDORID_ABOCOM, DC_DEVICEID_FE2500), 0, 207 "Abocom FE2500 10/100BaseTX" }, 208 { DC_DEVID(DC_VENDORID_ABOCOM, DC_DEVICEID_FE2500MX), 0, 209 "Abocom FE2500MX 10/100BaseTX" }, 210 { DC_DEVID(DC_VENDORID_CONEXANT, DC_DEVICEID_RS7112), 0, 211 "Conexant LANfinity MiniPCI 10/100BaseTX" }, 212 { DC_DEVID(DC_VENDORID_HAWKING, DC_DEVICEID_HAWKING_PN672TX), 0, 213 "Hawking CB102 CardBus 10/100" }, 214 { DC_DEVID(DC_VENDORID_PLANEX, DC_DEVICEID_FNW3602T), 0, 215 "PlaneX FNW-3602-T CardBus 10/100" }, 216 { DC_DEVID(DC_VENDORID_3COM, DC_DEVICEID_3CSOHOB), 0, 217 "3Com OfficeConnect 10/100B" }, 218 { DC_DEVID(DC_VENDORID_MICROSOFT, DC_DEVICEID_MSMN120), 0, 219 "Microsoft MN-120 CardBus 10/100" }, 220 { DC_DEVID(DC_VENDORID_MICROSOFT, DC_DEVICEID_MSMN130), 0, 221 "Microsoft MN-130 10/100" }, 222 { DC_DEVID(DC_VENDORID_LINKSYS, DC_DEVICEID_PCMPC200_AB08), 0, 223 "Linksys PCMPC200 CardBus 10/100" }, 224 { DC_DEVID(DC_VENDORID_LINKSYS, DC_DEVICEID_PCMPC200_AB09), 0, 225 "Linksys PCMPC200 CardBus 10/100" }, 226 { DC_DEVID(DC_VENDORID_ULI, DC_DEVICEID_M5261), 0, 227 "ULi M5261 FastEthernet" }, 228 { DC_DEVID(DC_VENDORID_ULI, DC_DEVICEID_M5263), 0, 229 "ULi M5263 FastEthernet" }, 230 { 0, 0, NULL } 231 }; 232 233 static int dc_probe(device_t); 234 static int dc_attach(device_t); 235 static int dc_detach(device_t); 236 static int dc_suspend(device_t); 237 static int dc_resume(device_t); 238 static const struct dc_type *dc_devtype(device_t); 239 static void dc_discard_rxbuf(struct dc_softc *, int); 240 static int dc_newbuf(struct dc_softc *, int); 241 static int dc_encap(struct dc_softc *, struct mbuf **); 242 static void dc_pnic_rx_bug_war(struct dc_softc *, int); 243 static int dc_rx_resync(struct dc_softc *); 244 static int dc_rxeof(struct dc_softc *); 245 static void dc_txeof(struct dc_softc *); 246 static void dc_tick(void *); 247 static void dc_tx_underrun(struct dc_softc *); 248 static void dc_intr(void *); 249 static void dc_start(if_t); 250 static void dc_start_locked(if_t); 251 static int dc_ioctl(if_t, u_long, caddr_t); 252 static void dc_init(void *); 253 static void dc_init_locked(struct dc_softc *); 254 static void dc_stop(struct dc_softc *); 255 static void dc_watchdog(void *); 256 static int dc_shutdown(device_t); 257 static int dc_ifmedia_upd(if_t); 258 static int dc_ifmedia_upd_locked(struct dc_softc *); 259 static void dc_ifmedia_sts(if_t, struct ifmediareq *); 260 261 static int dc_dma_alloc(struct dc_softc *); 262 static void dc_dma_free(struct dc_softc *); 263 static void dc_dma_map_addr(void *, bus_dma_segment_t *, int, int); 264 265 static void dc_delay(struct dc_softc *); 266 static void dc_eeprom_idle(struct dc_softc *); 267 static void dc_eeprom_putbyte(struct dc_softc *, int); 268 static void dc_eeprom_getword(struct dc_softc *, int, uint16_t *); 269 static void dc_eeprom_getword_pnic(struct dc_softc *, int, uint16_t *); 270 static void dc_eeprom_getword_xircom(struct dc_softc *, int, uint16_t *); 271 static void dc_eeprom_width(struct dc_softc *); 272 static void dc_read_eeprom(struct dc_softc *, caddr_t, int, int, int); 273 274 static int dc_miibus_readreg(device_t, int, int); 275 static int dc_miibus_writereg(device_t, int, int, int); 276 static void dc_miibus_statchg(device_t); 277 static void dc_miibus_mediainit(device_t); 278 279 static void dc_setcfg(struct dc_softc *, int); 280 static void dc_netcfg_wait(struct dc_softc *); 281 static uint32_t dc_mchash_le(struct dc_softc *, const uint8_t *); 282 static uint32_t dc_mchash_be(const uint8_t *); 283 static void dc_setfilt_21143(struct dc_softc *); 284 static void dc_setfilt_asix(struct dc_softc *); 285 static void dc_setfilt_admtek(struct dc_softc *); 286 static void dc_setfilt_uli(struct dc_softc *); 287 static void dc_setfilt_xircom(struct dc_softc *); 288 289 static void dc_setfilt(struct dc_softc *); 290 291 static void dc_reset(struct dc_softc *); 292 static int dc_list_rx_init(struct dc_softc *); 293 static int dc_list_tx_init(struct dc_softc *); 294 295 static int dc_read_srom(struct dc_softc *, int); 296 static int dc_parse_21143_srom(struct dc_softc *); 297 static int dc_decode_leaf_sia(struct dc_softc *, struct dc_eblock_sia *); 298 static int dc_decode_leaf_mii(struct dc_softc *, struct dc_eblock_mii *); 299 static int dc_decode_leaf_sym(struct dc_softc *, struct dc_eblock_sym *); 300 static void dc_apply_fixup(struct dc_softc *, int); 301 static int dc_check_multiport(struct dc_softc *); 302 303 /* 304 * MII bit-bang glue 305 */ 306 static uint32_t dc_mii_bitbang_read(device_t); 307 static void dc_mii_bitbang_write(device_t, uint32_t); 308 309 static const struct mii_bitbang_ops dc_mii_bitbang_ops = { 310 dc_mii_bitbang_read, 311 dc_mii_bitbang_write, 312 { 313 DC_SIO_MII_DATAOUT, /* MII_BIT_MDO */ 314 DC_SIO_MII_DATAIN, /* MII_BIT_MDI */ 315 DC_SIO_MII_CLK, /* MII_BIT_MDC */ 316 0, /* MII_BIT_DIR_HOST_PHY */ 317 DC_SIO_MII_DIR, /* MII_BIT_DIR_PHY_HOST */ 318 } 319 }; 320 321 #ifdef DC_USEIOSPACE 322 #define DC_RES SYS_RES_IOPORT 323 #define DC_RID DC_PCI_CFBIO 324 #else 325 #define DC_RES SYS_RES_MEMORY 326 #define DC_RID DC_PCI_CFBMA 327 #endif 328 329 static device_method_t dc_methods[] = { 330 /* Device interface */ 331 DEVMETHOD(device_probe, dc_probe), 332 DEVMETHOD(device_attach, dc_attach), 333 DEVMETHOD(device_detach, dc_detach), 334 DEVMETHOD(device_suspend, dc_suspend), 335 DEVMETHOD(device_resume, dc_resume), 336 DEVMETHOD(device_shutdown, dc_shutdown), 337 338 /* MII interface */ 339 DEVMETHOD(miibus_readreg, dc_miibus_readreg), 340 DEVMETHOD(miibus_writereg, dc_miibus_writereg), 341 DEVMETHOD(miibus_statchg, dc_miibus_statchg), 342 DEVMETHOD(miibus_mediainit, dc_miibus_mediainit), 343 344 DEVMETHOD_END 345 }; 346 347 static driver_t dc_driver = { 348 "dc", 349 dc_methods, 350 sizeof(struct dc_softc) 351 }; 352 353 DRIVER_MODULE_ORDERED(dc, pci, dc_driver, NULL, NULL, SI_ORDER_ANY); 354 MODULE_PNP_INFO("W32:vendor/device;U8:revision;D:#", pci, dc, dc_devs, 355 nitems(dc_devs) - 1); 356 DRIVER_MODULE(miibus, dc, miibus_driver, NULL, NULL); 357 358 #define DC_SETBIT(sc, reg, x) \ 359 CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) | (x)) 360 361 #define DC_CLRBIT(sc, reg, x) \ 362 CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) & ~(x)) 363 364 #define SIO_SET(x) DC_SETBIT(sc, DC_SIO, (x)) 365 #define SIO_CLR(x) DC_CLRBIT(sc, DC_SIO, (x)) 366 367 static void 368 dc_delay(struct dc_softc *sc) 369 { 370 int idx; 371 372 for (idx = (300 / 33) + 1; idx > 0; idx--) 373 CSR_READ_4(sc, DC_BUSCTL); 374 } 375 376 static void 377 dc_eeprom_width(struct dc_softc *sc) 378 { 379 int i; 380 381 /* Force EEPROM to idle state. */ 382 dc_eeprom_idle(sc); 383 384 /* Enter EEPROM access mode. */ 385 CSR_WRITE_4(sc, DC_SIO, DC_SIO_EESEL); 386 dc_delay(sc); 387 DC_SETBIT(sc, DC_SIO, DC_SIO_ROMCTL_READ); 388 dc_delay(sc); 389 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); 390 dc_delay(sc); 391 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CS); 392 dc_delay(sc); 393 394 for (i = 3; i--;) { 395 if (6 & (1 << i)) 396 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_DATAIN); 397 else 398 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_DATAIN); 399 dc_delay(sc); 400 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CLK); 401 dc_delay(sc); 402 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); 403 dc_delay(sc); 404 } 405 406 for (i = 1; i <= 12; i++) { 407 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CLK); 408 dc_delay(sc); 409 if (!(CSR_READ_4(sc, DC_SIO) & DC_SIO_EE_DATAOUT)) { 410 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); 411 dc_delay(sc); 412 break; 413 } 414 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); 415 dc_delay(sc); 416 } 417 418 /* Turn off EEPROM access mode. */ 419 dc_eeprom_idle(sc); 420 421 if (i < 4 || i > 12) 422 sc->dc_romwidth = 6; 423 else 424 sc->dc_romwidth = i; 425 426 /* Enter EEPROM access mode. */ 427 CSR_WRITE_4(sc, DC_SIO, DC_SIO_EESEL); 428 dc_delay(sc); 429 DC_SETBIT(sc, DC_SIO, DC_SIO_ROMCTL_READ); 430 dc_delay(sc); 431 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); 432 dc_delay(sc); 433 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CS); 434 dc_delay(sc); 435 436 /* Turn off EEPROM access mode. */ 437 dc_eeprom_idle(sc); 438 } 439 440 static void 441 dc_eeprom_idle(struct dc_softc *sc) 442 { 443 int i; 444 445 CSR_WRITE_4(sc, DC_SIO, DC_SIO_EESEL); 446 dc_delay(sc); 447 DC_SETBIT(sc, DC_SIO, DC_SIO_ROMCTL_READ); 448 dc_delay(sc); 449 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); 450 dc_delay(sc); 451 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CS); 452 dc_delay(sc); 453 454 for (i = 0; i < 25; i++) { 455 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); 456 dc_delay(sc); 457 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CLK); 458 dc_delay(sc); 459 } 460 461 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); 462 dc_delay(sc); 463 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CS); 464 dc_delay(sc); 465 CSR_WRITE_4(sc, DC_SIO, 0x00000000); 466 } 467 468 /* 469 * Send a read command and address to the EEPROM, check for ACK. 470 */ 471 static void 472 dc_eeprom_putbyte(struct dc_softc *sc, int addr) 473 { 474 int d, i; 475 476 d = DC_EECMD_READ >> 6; 477 for (i = 3; i--; ) { 478 if (d & (1 << i)) 479 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_DATAIN); 480 else 481 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_DATAIN); 482 dc_delay(sc); 483 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CLK); 484 dc_delay(sc); 485 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); 486 dc_delay(sc); 487 } 488 489 /* 490 * Feed in each bit and strobe the clock. 491 */ 492 for (i = sc->dc_romwidth; i--;) { 493 if (addr & (1 << i)) { 494 SIO_SET(DC_SIO_EE_DATAIN); 495 } else { 496 SIO_CLR(DC_SIO_EE_DATAIN); 497 } 498 dc_delay(sc); 499 SIO_SET(DC_SIO_EE_CLK); 500 dc_delay(sc); 501 SIO_CLR(DC_SIO_EE_CLK); 502 dc_delay(sc); 503 } 504 } 505 506 /* 507 * Read a word of data stored in the EEPROM at address 'addr.' 508 * The PNIC 82c168/82c169 has its own non-standard way to read 509 * the EEPROM. 510 */ 511 static void 512 dc_eeprom_getword_pnic(struct dc_softc *sc, int addr, uint16_t *dest) 513 { 514 int i; 515 uint32_t r; 516 517 CSR_WRITE_4(sc, DC_PN_SIOCTL, DC_PN_EEOPCODE_READ | addr); 518 519 for (i = 0; i < DC_TIMEOUT; i++) { 520 DELAY(1); 521 r = CSR_READ_4(sc, DC_SIO); 522 if (!(r & DC_PN_SIOCTL_BUSY)) { 523 *dest = (uint16_t)(r & 0xFFFF); 524 return; 525 } 526 } 527 } 528 529 /* 530 * Read a word of data stored in the EEPROM at address 'addr.' 531 * The Xircom X3201 has its own non-standard way to read 532 * the EEPROM, too. 533 */ 534 static void 535 dc_eeprom_getword_xircom(struct dc_softc *sc, int addr, uint16_t *dest) 536 { 537 538 SIO_SET(DC_SIO_ROMSEL | DC_SIO_ROMCTL_READ); 539 540 addr *= 2; 541 CSR_WRITE_4(sc, DC_ROM, addr | 0x160); 542 *dest = (uint16_t)CSR_READ_4(sc, DC_SIO) & 0xff; 543 addr += 1; 544 CSR_WRITE_4(sc, DC_ROM, addr | 0x160); 545 *dest |= ((uint16_t)CSR_READ_4(sc, DC_SIO) & 0xff) << 8; 546 547 SIO_CLR(DC_SIO_ROMSEL | DC_SIO_ROMCTL_READ); 548 } 549 550 /* 551 * Read a word of data stored in the EEPROM at address 'addr.' 552 */ 553 static void 554 dc_eeprom_getword(struct dc_softc *sc, int addr, uint16_t *dest) 555 { 556 int i; 557 uint16_t word = 0; 558 559 /* Force EEPROM to idle state. */ 560 dc_eeprom_idle(sc); 561 562 /* Enter EEPROM access mode. */ 563 CSR_WRITE_4(sc, DC_SIO, DC_SIO_EESEL); 564 dc_delay(sc); 565 DC_SETBIT(sc, DC_SIO, DC_SIO_ROMCTL_READ); 566 dc_delay(sc); 567 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); 568 dc_delay(sc); 569 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CS); 570 dc_delay(sc); 571 572 /* 573 * Send address of word we want to read. 574 */ 575 dc_eeprom_putbyte(sc, addr); 576 577 /* 578 * Start reading bits from EEPROM. 579 */ 580 for (i = 0x8000; i; i >>= 1) { 581 SIO_SET(DC_SIO_EE_CLK); 582 dc_delay(sc); 583 if (CSR_READ_4(sc, DC_SIO) & DC_SIO_EE_DATAOUT) 584 word |= i; 585 dc_delay(sc); 586 SIO_CLR(DC_SIO_EE_CLK); 587 dc_delay(sc); 588 } 589 590 /* Turn off EEPROM access mode. */ 591 dc_eeprom_idle(sc); 592 593 *dest = word; 594 } 595 596 /* 597 * Read a sequence of words from the EEPROM. 598 */ 599 static void 600 dc_read_eeprom(struct dc_softc *sc, caddr_t dest, int off, int cnt, int be) 601 { 602 int i; 603 uint16_t word = 0, *ptr; 604 605 for (i = 0; i < cnt; i++) { 606 if (DC_IS_PNIC(sc)) 607 dc_eeprom_getword_pnic(sc, off + i, &word); 608 else if (DC_IS_XIRCOM(sc)) 609 dc_eeprom_getword_xircom(sc, off + i, &word); 610 else 611 dc_eeprom_getword(sc, off + i, &word); 612 ptr = (uint16_t *)(dest + (i * 2)); 613 if (be) 614 *ptr = be16toh(word); 615 else 616 *ptr = le16toh(word); 617 } 618 } 619 620 /* 621 * Write the MII serial port for the MII bit-bang module. 622 */ 623 static void 624 dc_mii_bitbang_write(device_t dev, uint32_t val) 625 { 626 struct dc_softc *sc; 627 628 sc = device_get_softc(dev); 629 630 CSR_WRITE_4(sc, DC_SIO, val); 631 CSR_BARRIER_4(sc, DC_SIO, 632 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 633 } 634 635 /* 636 * Read the MII serial port for the MII bit-bang module. 637 */ 638 static uint32_t 639 dc_mii_bitbang_read(device_t dev) 640 { 641 struct dc_softc *sc; 642 uint32_t val; 643 644 sc = device_get_softc(dev); 645 646 val = CSR_READ_4(sc, DC_SIO); 647 CSR_BARRIER_4(sc, DC_SIO, 648 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 649 650 return (val); 651 } 652 653 static int 654 dc_miibus_readreg(device_t dev, int phy, int reg) 655 { 656 struct dc_softc *sc; 657 int i, rval, phy_reg = 0; 658 659 sc = device_get_softc(dev); 660 661 if (sc->dc_pmode != DC_PMODE_MII) { 662 if (phy == (MII_NPHY - 1)) { 663 switch (reg) { 664 case MII_BMSR: 665 /* 666 * Fake something to make the probe 667 * code think there's a PHY here. 668 */ 669 return (BMSR_MEDIAMASK); 670 case MII_PHYIDR1: 671 if (DC_IS_PNIC(sc)) 672 return (DC_VENDORID_LO); 673 return (DC_VENDORID_DEC); 674 case MII_PHYIDR2: 675 if (DC_IS_PNIC(sc)) 676 return (DC_DEVICEID_82C168); 677 return (DC_DEVICEID_21143); 678 default: 679 return (0); 680 } 681 } else 682 return (0); 683 } 684 685 if (DC_IS_PNIC(sc)) { 686 CSR_WRITE_4(sc, DC_PN_MII, DC_PN_MIIOPCODE_READ | 687 (phy << 23) | (reg << 18)); 688 for (i = 0; i < DC_TIMEOUT; i++) { 689 DELAY(1); 690 rval = CSR_READ_4(sc, DC_PN_MII); 691 if (!(rval & DC_PN_MII_BUSY)) { 692 rval &= 0xFFFF; 693 return (rval == 0xFFFF ? 0 : rval); 694 } 695 } 696 return (0); 697 } 698 699 if (sc->dc_type == DC_TYPE_ULI_M5263) { 700 CSR_WRITE_4(sc, DC_ROM, 701 ((phy << DC_ULI_PHY_ADDR_SHIFT) & DC_ULI_PHY_ADDR_MASK) | 702 ((reg << DC_ULI_PHY_REG_SHIFT) & DC_ULI_PHY_REG_MASK) | 703 DC_ULI_PHY_OP_READ); 704 for (i = 0; i < DC_TIMEOUT; i++) { 705 DELAY(1); 706 rval = CSR_READ_4(sc, DC_ROM); 707 if ((rval & DC_ULI_PHY_OP_DONE) != 0) { 708 return (rval & DC_ULI_PHY_DATA_MASK); 709 } 710 } 711 if (i == DC_TIMEOUT) 712 device_printf(dev, "phy read timed out\n"); 713 return (0); 714 } 715 716 if (DC_IS_COMET(sc)) { 717 switch (reg) { 718 case MII_BMCR: 719 phy_reg = DC_AL_BMCR; 720 break; 721 case MII_BMSR: 722 phy_reg = DC_AL_BMSR; 723 break; 724 case MII_PHYIDR1: 725 phy_reg = DC_AL_VENID; 726 break; 727 case MII_PHYIDR2: 728 phy_reg = DC_AL_DEVID; 729 break; 730 case MII_ANAR: 731 phy_reg = DC_AL_ANAR; 732 break; 733 case MII_ANLPAR: 734 phy_reg = DC_AL_LPAR; 735 break; 736 case MII_ANER: 737 phy_reg = DC_AL_ANER; 738 break; 739 default: 740 device_printf(dev, "phy_read: bad phy register %x\n", 741 reg); 742 return (0); 743 } 744 745 rval = CSR_READ_4(sc, phy_reg) & 0x0000FFFF; 746 if (rval == 0xFFFF) 747 return (0); 748 return (rval); 749 } 750 751 if (sc->dc_type == DC_TYPE_98713) { 752 phy_reg = CSR_READ_4(sc, DC_NETCFG); 753 CSR_WRITE_4(sc, DC_NETCFG, phy_reg & ~DC_NETCFG_PORTSEL); 754 } 755 rval = mii_bitbang_readreg(dev, &dc_mii_bitbang_ops, phy, reg); 756 if (sc->dc_type == DC_TYPE_98713) 757 CSR_WRITE_4(sc, DC_NETCFG, phy_reg); 758 759 return (rval); 760 } 761 762 static int 763 dc_miibus_writereg(device_t dev, int phy, int reg, int data) 764 { 765 struct dc_softc *sc; 766 int i, phy_reg = 0; 767 768 sc = device_get_softc(dev); 769 770 if (DC_IS_PNIC(sc)) { 771 CSR_WRITE_4(sc, DC_PN_MII, DC_PN_MIIOPCODE_WRITE | 772 (phy << 23) | (reg << 10) | data); 773 for (i = 0; i < DC_TIMEOUT; i++) { 774 if (!(CSR_READ_4(sc, DC_PN_MII) & DC_PN_MII_BUSY)) 775 break; 776 } 777 return (0); 778 } 779 780 if (sc->dc_type == DC_TYPE_ULI_M5263) { 781 CSR_WRITE_4(sc, DC_ROM, 782 ((phy << DC_ULI_PHY_ADDR_SHIFT) & DC_ULI_PHY_ADDR_MASK) | 783 ((reg << DC_ULI_PHY_REG_SHIFT) & DC_ULI_PHY_REG_MASK) | 784 ((data << DC_ULI_PHY_DATA_SHIFT) & DC_ULI_PHY_DATA_MASK) | 785 DC_ULI_PHY_OP_WRITE); 786 DELAY(1); 787 return (0); 788 } 789 790 if (DC_IS_COMET(sc)) { 791 switch (reg) { 792 case MII_BMCR: 793 phy_reg = DC_AL_BMCR; 794 break; 795 case MII_BMSR: 796 phy_reg = DC_AL_BMSR; 797 break; 798 case MII_PHYIDR1: 799 phy_reg = DC_AL_VENID; 800 break; 801 case MII_PHYIDR2: 802 phy_reg = DC_AL_DEVID; 803 break; 804 case MII_ANAR: 805 phy_reg = DC_AL_ANAR; 806 break; 807 case MII_ANLPAR: 808 phy_reg = DC_AL_LPAR; 809 break; 810 case MII_ANER: 811 phy_reg = DC_AL_ANER; 812 break; 813 default: 814 device_printf(dev, "phy_write: bad phy register %x\n", 815 reg); 816 return (0); 817 break; 818 } 819 820 CSR_WRITE_4(sc, phy_reg, data); 821 return (0); 822 } 823 824 if (sc->dc_type == DC_TYPE_98713) { 825 phy_reg = CSR_READ_4(sc, DC_NETCFG); 826 CSR_WRITE_4(sc, DC_NETCFG, phy_reg & ~DC_NETCFG_PORTSEL); 827 } 828 mii_bitbang_writereg(dev, &dc_mii_bitbang_ops, phy, reg, data); 829 if (sc->dc_type == DC_TYPE_98713) 830 CSR_WRITE_4(sc, DC_NETCFG, phy_reg); 831 832 return (0); 833 } 834 835 static void 836 dc_miibus_statchg(device_t dev) 837 { 838 struct dc_softc *sc; 839 if_t ifp; 840 struct mii_data *mii; 841 struct ifmedia *ifm; 842 843 sc = device_get_softc(dev); 844 845 mii = device_get_softc(sc->dc_miibus); 846 ifp = sc->dc_ifp; 847 if (mii == NULL || ifp == NULL || 848 (if_getdrvflags(ifp) & IFF_DRV_RUNNING) == 0) 849 return; 850 851 ifm = &mii->mii_media; 852 if (DC_IS_DAVICOM(sc) && IFM_SUBTYPE(ifm->ifm_media) == IFM_HPNA_1) { 853 dc_setcfg(sc, ifm->ifm_media); 854 return; 855 } else if (!DC_IS_ADMTEK(sc)) 856 dc_setcfg(sc, mii->mii_media_active); 857 858 sc->dc_link = 0; 859 if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) == 860 (IFM_ACTIVE | IFM_AVALID)) { 861 switch (IFM_SUBTYPE(mii->mii_media_active)) { 862 case IFM_10_T: 863 case IFM_100_TX: 864 sc->dc_link = 1; 865 break; 866 } 867 } 868 } 869 870 /* 871 * Special support for DM9102A cards with HomePNA PHYs. Note: 872 * with the Davicom DM9102A/DM9801 eval board that I have, it seems 873 * to be impossible to talk to the management interface of the DM9801 874 * PHY (its MDIO pin is not connected to anything). Consequently, 875 * the driver has to just 'know' about the additional mode and deal 876 * with it itself. *sigh* 877 */ 878 static void 879 dc_miibus_mediainit(device_t dev) 880 { 881 struct dc_softc *sc; 882 struct mii_data *mii; 883 struct ifmedia *ifm; 884 int rev; 885 886 rev = pci_get_revid(dev); 887 888 sc = device_get_softc(dev); 889 mii = device_get_softc(sc->dc_miibus); 890 ifm = &mii->mii_media; 891 892 if (DC_IS_DAVICOM(sc) && rev >= DC_REVISION_DM9102A) 893 ifmedia_add(ifm, IFM_ETHER | IFM_HPNA_1, 0, NULL); 894 } 895 896 #define DC_BITS_512 9 897 #define DC_BITS_128 7 898 #define DC_BITS_64 6 899 900 static uint32_t 901 dc_mchash_le(struct dc_softc *sc, const uint8_t *addr) 902 { 903 uint32_t crc; 904 905 /* Compute CRC for the address value. */ 906 crc = ether_crc32_le(addr, ETHER_ADDR_LEN); 907 908 /* 909 * The hash table on the PNIC II and the MX98715AEC-C/D/E 910 * chips is only 128 bits wide. 911 */ 912 if (sc->dc_flags & DC_128BIT_HASH) 913 return (crc & ((1 << DC_BITS_128) - 1)); 914 915 /* The hash table on the MX98715BEC is only 64 bits wide. */ 916 if (sc->dc_flags & DC_64BIT_HASH) 917 return (crc & ((1 << DC_BITS_64) - 1)); 918 919 /* Xircom's hash filtering table is different (read: weird) */ 920 /* Xircom uses the LEAST significant bits */ 921 if (DC_IS_XIRCOM(sc)) { 922 if ((crc & 0x180) == 0x180) 923 return ((crc & 0x0F) + (crc & 0x70) * 3 + (14 << 4)); 924 else 925 return ((crc & 0x1F) + ((crc >> 1) & 0xF0) * 3 + 926 (12 << 4)); 927 } 928 929 return (crc & ((1 << DC_BITS_512) - 1)); 930 } 931 932 /* 933 * Calculate CRC of a multicast group address, return the lower 6 bits. 934 */ 935 static uint32_t 936 dc_mchash_be(const uint8_t *addr) 937 { 938 uint32_t crc; 939 940 /* Compute CRC for the address value. */ 941 crc = ether_crc32_be(addr, ETHER_ADDR_LEN); 942 943 /* Return the filter bit position. */ 944 return ((crc >> 26) & 0x0000003F); 945 } 946 947 /* 948 * 21143-style RX filter setup routine. Filter programming is done by 949 * downloading a special setup frame into the TX engine. 21143, Macronix, 950 * PNIC, PNIC II and Davicom chips are programmed this way. 951 * 952 * We always program the chip using 'hash perfect' mode, i.e. one perfect 953 * address (our node address) and a 512-bit hash filter for multicast 954 * frames. We also sneak the broadcast address into the hash filter since 955 * we need that too. 956 */ 957 static u_int 958 dc_hash_maddr_21143(void *arg, struct sockaddr_dl *sdl, u_int cnt) 959 { 960 struct dc_softc *sc = arg; 961 uint32_t h; 962 963 h = dc_mchash_le(sc, LLADDR(sdl)); 964 sc->dc_cdata.dc_sbuf[h >> 4] |= htole32(1 << (h & 0xF)); 965 966 return (1); 967 } 968 969 static void 970 dc_setfilt_21143(struct dc_softc *sc) 971 { 972 uint16_t eaddr[(ETHER_ADDR_LEN+1)/2]; 973 struct dc_desc *sframe; 974 uint32_t h, *sp; 975 if_t ifp; 976 int i; 977 978 ifp = sc->dc_ifp; 979 980 i = sc->dc_cdata.dc_tx_prod; 981 DC_INC(sc->dc_cdata.dc_tx_prod, DC_TX_LIST_CNT); 982 sc->dc_cdata.dc_tx_cnt++; 983 sframe = &sc->dc_ldata.dc_tx_list[i]; 984 sp = sc->dc_cdata.dc_sbuf; 985 bzero(sp, DC_SFRAME_LEN); 986 987 sframe->dc_data = htole32(DC_ADDR_LO(sc->dc_saddr)); 988 sframe->dc_ctl = htole32(DC_SFRAME_LEN | DC_TXCTL_SETUP | 989 DC_TXCTL_TLINK | DC_FILTER_HASHPERF | DC_TXCTL_FINT); 990 991 sc->dc_cdata.dc_tx_chain[i] = (struct mbuf *)sc->dc_cdata.dc_sbuf; 992 993 /* If we want promiscuous mode, set the allframes bit. */ 994 if (if_getflags(ifp) & IFF_PROMISC) 995 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC); 996 else 997 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC); 998 999 if (if_getflags(ifp) & IFF_ALLMULTI) 1000 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI); 1001 else 1002 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI); 1003 1004 if_foreach_llmaddr(ifp, dc_hash_maddr_21143, sp); 1005 1006 if (if_getflags(ifp) & IFF_BROADCAST) { 1007 h = dc_mchash_le(sc, if_getbroadcastaddr(ifp)); 1008 sp[h >> 4] |= htole32(1 << (h & 0xF)); 1009 } 1010 1011 /* Set our MAC address. */ 1012 bcopy(if_getlladdr(sc->dc_ifp), eaddr, ETHER_ADDR_LEN); 1013 sp[39] = DC_SP_MAC(eaddr[0]); 1014 sp[40] = DC_SP_MAC(eaddr[1]); 1015 sp[41] = DC_SP_MAC(eaddr[2]); 1016 1017 sframe->dc_status = htole32(DC_TXSTAT_OWN); 1018 bus_dmamap_sync(sc->dc_tx_ltag, sc->dc_tx_lmap, BUS_DMASYNC_PREREAD | 1019 BUS_DMASYNC_PREWRITE); 1020 bus_dmamap_sync(sc->dc_stag, sc->dc_smap, BUS_DMASYNC_PREWRITE); 1021 CSR_WRITE_4(sc, DC_TXSTART, 0xFFFFFFFF); 1022 1023 /* 1024 * The PNIC takes an exceedingly long time to process its 1025 * setup frame; wait 10ms after posting the setup frame 1026 * before proceeding, just so it has time to swallow its 1027 * medicine. 1028 */ 1029 DELAY(10000); 1030 1031 sc->dc_wdog_timer = 5; 1032 } 1033 1034 static u_int 1035 dc_hash_maddr_admtek_be(void *arg, struct sockaddr_dl *sdl, u_int cnt) 1036 { 1037 uint32_t *hashes = arg; 1038 int h = 0; 1039 1040 h = dc_mchash_be(LLADDR(sdl)); 1041 if (h < 32) 1042 hashes[0] |= (1 << h); 1043 else 1044 hashes[1] |= (1 << (h - 32)); 1045 1046 return (1); 1047 } 1048 1049 struct dc_hash_maddr_admtek_le_ctx { 1050 struct dc_softc *sc; 1051 uint32_t hashes[2]; 1052 }; 1053 1054 static u_int 1055 dc_hash_maddr_admtek_le(void *arg, struct sockaddr_dl *sdl, u_int cnt) 1056 { 1057 struct dc_hash_maddr_admtek_le_ctx *ctx = arg; 1058 int h = 0; 1059 1060 h = dc_mchash_le(ctx->sc, LLADDR(sdl)); 1061 if (h < 32) 1062 ctx->hashes[0] |= (1 << h); 1063 else 1064 ctx->hashes[1] |= (1 << (h - 32)); 1065 1066 return (1); 1067 } 1068 1069 static void 1070 dc_setfilt_admtek(struct dc_softc *sc) 1071 { 1072 uint8_t eaddr[ETHER_ADDR_LEN]; 1073 if_t ifp; 1074 struct dc_hash_maddr_admtek_le_ctx ctx = { sc, { 0, 0 }}; 1075 1076 ifp = sc->dc_ifp; 1077 1078 /* Init our MAC address. */ 1079 bcopy(if_getlladdr(sc->dc_ifp), eaddr, ETHER_ADDR_LEN); 1080 CSR_WRITE_4(sc, DC_AL_PAR0, eaddr[3] << 24 | eaddr[2] << 16 | 1081 eaddr[1] << 8 | eaddr[0]); 1082 CSR_WRITE_4(sc, DC_AL_PAR1, eaddr[5] << 8 | eaddr[4]); 1083 1084 /* If we want promiscuous mode, set the allframes bit. */ 1085 if (if_getflags(ifp) & IFF_PROMISC) 1086 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC); 1087 else 1088 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC); 1089 1090 if (if_getflags(ifp) & IFF_ALLMULTI) 1091 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI); 1092 else 1093 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI); 1094 1095 /* First, zot all the existing hash bits. */ 1096 CSR_WRITE_4(sc, DC_AL_MAR0, 0); 1097 CSR_WRITE_4(sc, DC_AL_MAR1, 0); 1098 1099 /* 1100 * If we're already in promisc or allmulti mode, we 1101 * don't have to bother programming the multicast filter. 1102 */ 1103 if (if_getflags(ifp) & (IFF_PROMISC | IFF_ALLMULTI)) 1104 return; 1105 1106 /* Now program new ones. */ 1107 if (DC_IS_CENTAUR(sc)) 1108 if_foreach_llmaddr(ifp, dc_hash_maddr_admtek_le, &ctx); 1109 else 1110 if_foreach_llmaddr(ifp, dc_hash_maddr_admtek_be, &ctx.hashes); 1111 1112 CSR_WRITE_4(sc, DC_AL_MAR0, ctx.hashes[0]); 1113 CSR_WRITE_4(sc, DC_AL_MAR1, ctx.hashes[1]); 1114 } 1115 1116 static void 1117 dc_setfilt_asix(struct dc_softc *sc) 1118 { 1119 uint32_t eaddr[(ETHER_ADDR_LEN+3)/4]; 1120 if_t ifp; 1121 uint32_t hashes[2] = { 0, 0 }; 1122 1123 ifp = sc->dc_ifp; 1124 1125 /* Init our MAC address. */ 1126 bcopy(if_getlladdr(sc->dc_ifp), eaddr, ETHER_ADDR_LEN); 1127 CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_PAR0); 1128 CSR_WRITE_4(sc, DC_AX_FILTDATA, eaddr[0]); 1129 CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_PAR1); 1130 CSR_WRITE_4(sc, DC_AX_FILTDATA, eaddr[1]); 1131 1132 /* If we want promiscuous mode, set the allframes bit. */ 1133 if (if_getflags(ifp) & IFF_PROMISC) 1134 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC); 1135 else 1136 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC); 1137 1138 if (if_getflags(ifp) & IFF_ALLMULTI) 1139 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI); 1140 else 1141 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI); 1142 1143 /* 1144 * The ASIX chip has a special bit to enable reception 1145 * of broadcast frames. 1146 */ 1147 if (if_getflags(ifp) & IFF_BROADCAST) 1148 DC_SETBIT(sc, DC_NETCFG, DC_AX_NETCFG_RX_BROAD); 1149 else 1150 DC_CLRBIT(sc, DC_NETCFG, DC_AX_NETCFG_RX_BROAD); 1151 1152 /* first, zot all the existing hash bits */ 1153 CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_MAR0); 1154 CSR_WRITE_4(sc, DC_AX_FILTDATA, 0); 1155 CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_MAR1); 1156 CSR_WRITE_4(sc, DC_AX_FILTDATA, 0); 1157 1158 /* 1159 * If we're already in promisc or allmulti mode, we 1160 * don't have to bother programming the multicast filter. 1161 */ 1162 if (if_getflags(ifp) & (IFF_PROMISC | IFF_ALLMULTI)) 1163 return; 1164 1165 /* now program new ones */ 1166 if_foreach_llmaddr(ifp, dc_hash_maddr_admtek_be, hashes); 1167 1168 CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_MAR0); 1169 CSR_WRITE_4(sc, DC_AX_FILTDATA, hashes[0]); 1170 CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_MAR1); 1171 CSR_WRITE_4(sc, DC_AX_FILTDATA, hashes[1]); 1172 } 1173 1174 static u_int 1175 dc_hash_maddr_uli(void *arg, struct sockaddr_dl *sdl, u_int mcnt) 1176 { 1177 uint32_t **sp = arg; 1178 uint8_t *ma; 1179 1180 if (mcnt == DC_ULI_FILTER_NPERF) 1181 return (0); 1182 ma = LLADDR(sdl); 1183 *(*sp)++ = DC_SP_MAC(ma[1] << 8 | ma[0]); 1184 *(*sp)++ = DC_SP_MAC(ma[3] << 8 | ma[2]); 1185 *(*sp)++ = DC_SP_MAC(ma[5] << 8 | ma[4]); 1186 1187 return (1); 1188 } 1189 1190 static void 1191 dc_setfilt_uli(struct dc_softc *sc) 1192 { 1193 uint8_t eaddr[ETHER_ADDR_LEN]; 1194 if_t ifp; 1195 struct dc_desc *sframe; 1196 uint32_t filter, *sp; 1197 int i, mcnt; 1198 1199 ifp = sc->dc_ifp; 1200 1201 i = sc->dc_cdata.dc_tx_prod; 1202 DC_INC(sc->dc_cdata.dc_tx_prod, DC_TX_LIST_CNT); 1203 sc->dc_cdata.dc_tx_cnt++; 1204 sframe = &sc->dc_ldata.dc_tx_list[i]; 1205 sp = sc->dc_cdata.dc_sbuf; 1206 bzero(sp, DC_SFRAME_LEN); 1207 1208 sframe->dc_data = htole32(DC_ADDR_LO(sc->dc_saddr)); 1209 sframe->dc_ctl = htole32(DC_SFRAME_LEN | DC_TXCTL_SETUP | 1210 DC_TXCTL_TLINK | DC_FILTER_PERFECT | DC_TXCTL_FINT); 1211 1212 sc->dc_cdata.dc_tx_chain[i] = (struct mbuf *)sc->dc_cdata.dc_sbuf; 1213 1214 /* Set station address. */ 1215 bcopy(if_getlladdr(sc->dc_ifp), eaddr, ETHER_ADDR_LEN); 1216 *sp++ = DC_SP_MAC(eaddr[1] << 8 | eaddr[0]); 1217 *sp++ = DC_SP_MAC(eaddr[3] << 8 | eaddr[2]); 1218 *sp++ = DC_SP_MAC(eaddr[5] << 8 | eaddr[4]); 1219 1220 /* Set broadcast address. */ 1221 *sp++ = DC_SP_MAC(0xFFFF); 1222 *sp++ = DC_SP_MAC(0xFFFF); 1223 *sp++ = DC_SP_MAC(0xFFFF); 1224 1225 /* Extract current filter configuration. */ 1226 filter = CSR_READ_4(sc, DC_NETCFG); 1227 filter &= ~(DC_NETCFG_RX_PROMISC | DC_NETCFG_RX_ALLMULTI); 1228 1229 /* Now build perfect filters. */ 1230 mcnt = if_foreach_llmaddr(ifp, dc_hash_maddr_uli, &sp); 1231 1232 if (mcnt == DC_ULI_FILTER_NPERF) 1233 filter |= DC_NETCFG_RX_ALLMULTI; 1234 else 1235 for (; mcnt < DC_ULI_FILTER_NPERF; mcnt++) { 1236 *sp++ = DC_SP_MAC(0xFFFF); 1237 *sp++ = DC_SP_MAC(0xFFFF); 1238 *sp++ = DC_SP_MAC(0xFFFF); 1239 } 1240 1241 if (filter & (DC_NETCFG_TX_ON | DC_NETCFG_RX_ON)) 1242 CSR_WRITE_4(sc, DC_NETCFG, 1243 filter & ~(DC_NETCFG_TX_ON | DC_NETCFG_RX_ON)); 1244 if (if_getflags(ifp) & IFF_PROMISC) 1245 filter |= DC_NETCFG_RX_PROMISC | DC_NETCFG_RX_ALLMULTI; 1246 if (if_getflags(ifp) & IFF_ALLMULTI) 1247 filter |= DC_NETCFG_RX_ALLMULTI; 1248 CSR_WRITE_4(sc, DC_NETCFG, 1249 filter & ~(DC_NETCFG_TX_ON | DC_NETCFG_RX_ON)); 1250 if (filter & (DC_NETCFG_TX_ON | DC_NETCFG_RX_ON)) 1251 CSR_WRITE_4(sc, DC_NETCFG, filter); 1252 1253 sframe->dc_status = htole32(DC_TXSTAT_OWN); 1254 bus_dmamap_sync(sc->dc_tx_ltag, sc->dc_tx_lmap, BUS_DMASYNC_PREREAD | 1255 BUS_DMASYNC_PREWRITE); 1256 bus_dmamap_sync(sc->dc_stag, sc->dc_smap, BUS_DMASYNC_PREWRITE); 1257 CSR_WRITE_4(sc, DC_TXSTART, 0xFFFFFFFF); 1258 1259 /* 1260 * Wait some time... 1261 */ 1262 DELAY(1000); 1263 1264 sc->dc_wdog_timer = 5; 1265 } 1266 1267 static u_int 1268 dc_hash_maddr_xircom(void *arg, struct sockaddr_dl *sdl, u_int cnt) 1269 { 1270 struct dc_softc *sc = arg; 1271 uint32_t h; 1272 1273 h = dc_mchash_le(sc, LLADDR(sdl)); 1274 sc->dc_cdata.dc_sbuf[h >> 4] |= htole32(1 << (h & 0xF)); 1275 return (1); 1276 } 1277 1278 static void 1279 dc_setfilt_xircom(struct dc_softc *sc) 1280 { 1281 uint16_t eaddr[(ETHER_ADDR_LEN+1)/2]; 1282 if_t ifp; 1283 struct dc_desc *sframe; 1284 uint32_t h, *sp; 1285 int i; 1286 1287 ifp = sc->dc_ifp; 1288 DC_CLRBIT(sc, DC_NETCFG, (DC_NETCFG_TX_ON | DC_NETCFG_RX_ON)); 1289 1290 i = sc->dc_cdata.dc_tx_prod; 1291 DC_INC(sc->dc_cdata.dc_tx_prod, DC_TX_LIST_CNT); 1292 sc->dc_cdata.dc_tx_cnt++; 1293 sframe = &sc->dc_ldata.dc_tx_list[i]; 1294 sp = sc->dc_cdata.dc_sbuf; 1295 bzero(sp, DC_SFRAME_LEN); 1296 1297 sframe->dc_data = htole32(DC_ADDR_LO(sc->dc_saddr)); 1298 sframe->dc_ctl = htole32(DC_SFRAME_LEN | DC_TXCTL_SETUP | 1299 DC_TXCTL_TLINK | DC_FILTER_HASHPERF | DC_TXCTL_FINT); 1300 1301 sc->dc_cdata.dc_tx_chain[i] = (struct mbuf *)sc->dc_cdata.dc_sbuf; 1302 1303 /* If we want promiscuous mode, set the allframes bit. */ 1304 if (if_getflags(ifp) & IFF_PROMISC) 1305 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC); 1306 else 1307 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC); 1308 1309 if (if_getflags(ifp) & IFF_ALLMULTI) 1310 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI); 1311 else 1312 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI); 1313 1314 if_foreach_llmaddr(ifp, dc_hash_maddr_xircom, &sp); 1315 1316 if (if_getflags(ifp) & IFF_BROADCAST) { 1317 h = dc_mchash_le(sc, if_getbroadcastaddr(ifp)); 1318 sp[h >> 4] |= htole32(1 << (h & 0xF)); 1319 } 1320 1321 /* Set our MAC address. */ 1322 bcopy(if_getlladdr(sc->dc_ifp), eaddr, ETHER_ADDR_LEN); 1323 sp[0] = DC_SP_MAC(eaddr[0]); 1324 sp[1] = DC_SP_MAC(eaddr[1]); 1325 sp[2] = DC_SP_MAC(eaddr[2]); 1326 1327 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_TX_ON); 1328 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_ON); 1329 sframe->dc_status = htole32(DC_TXSTAT_OWN); 1330 bus_dmamap_sync(sc->dc_tx_ltag, sc->dc_tx_lmap, BUS_DMASYNC_PREREAD | 1331 BUS_DMASYNC_PREWRITE); 1332 bus_dmamap_sync(sc->dc_stag, sc->dc_smap, BUS_DMASYNC_PREWRITE); 1333 CSR_WRITE_4(sc, DC_TXSTART, 0xFFFFFFFF); 1334 1335 /* 1336 * Wait some time... 1337 */ 1338 DELAY(1000); 1339 1340 sc->dc_wdog_timer = 5; 1341 } 1342 1343 static void 1344 dc_setfilt(struct dc_softc *sc) 1345 { 1346 1347 if (DC_IS_INTEL(sc) || DC_IS_MACRONIX(sc) || DC_IS_PNIC(sc) || 1348 DC_IS_PNICII(sc) || DC_IS_DAVICOM(sc) || DC_IS_CONEXANT(sc)) 1349 dc_setfilt_21143(sc); 1350 1351 if (DC_IS_ASIX(sc)) 1352 dc_setfilt_asix(sc); 1353 1354 if (DC_IS_ADMTEK(sc)) 1355 dc_setfilt_admtek(sc); 1356 1357 if (DC_IS_ULI(sc)) 1358 dc_setfilt_uli(sc); 1359 1360 if (DC_IS_XIRCOM(sc)) 1361 dc_setfilt_xircom(sc); 1362 } 1363 1364 static void 1365 dc_netcfg_wait(struct dc_softc *sc) 1366 { 1367 uint32_t isr; 1368 int i; 1369 1370 for (i = 0; i < DC_TIMEOUT; i++) { 1371 isr = CSR_READ_4(sc, DC_ISR); 1372 if (isr & DC_ISR_TX_IDLE && 1373 ((isr & DC_ISR_RX_STATE) == DC_RXSTATE_STOPPED || 1374 (isr & DC_ISR_RX_STATE) == DC_RXSTATE_WAIT)) 1375 break; 1376 DELAY(10); 1377 } 1378 if (i == DC_TIMEOUT && bus_child_present(sc->dc_dev)) { 1379 if (!(isr & DC_ISR_TX_IDLE) && !DC_IS_ASIX(sc)) 1380 device_printf(sc->dc_dev, 1381 "%s: failed to force tx to idle state\n", __func__); 1382 if (!((isr & DC_ISR_RX_STATE) == DC_RXSTATE_STOPPED || 1383 (isr & DC_ISR_RX_STATE) == DC_RXSTATE_WAIT) && 1384 !DC_HAS_BROKEN_RXSTATE(sc)) 1385 device_printf(sc->dc_dev, 1386 "%s: failed to force rx to idle state\n", __func__); 1387 } 1388 } 1389 1390 /* 1391 * In order to fiddle with the 'full-duplex' and '100Mbps' bits in 1392 * the netconfig register, we first have to put the transmit and/or 1393 * receive logic in the idle state. 1394 */ 1395 static void 1396 dc_setcfg(struct dc_softc *sc, int media) 1397 { 1398 int restart = 0, watchdogreg; 1399 1400 if (IFM_SUBTYPE(media) == IFM_NONE) 1401 return; 1402 1403 if (CSR_READ_4(sc, DC_NETCFG) & (DC_NETCFG_TX_ON | DC_NETCFG_RX_ON)) { 1404 restart = 1; 1405 DC_CLRBIT(sc, DC_NETCFG, (DC_NETCFG_TX_ON | DC_NETCFG_RX_ON)); 1406 dc_netcfg_wait(sc); 1407 } 1408 1409 if (IFM_SUBTYPE(media) == IFM_100_TX) { 1410 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_SPEEDSEL); 1411 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_HEARTBEAT); 1412 if (sc->dc_pmode == DC_PMODE_MII) { 1413 if (DC_IS_INTEL(sc)) { 1414 /* There's a write enable bit here that reads as 1. */ 1415 watchdogreg = CSR_READ_4(sc, DC_WATCHDOG); 1416 watchdogreg &= ~DC_WDOG_CTLWREN; 1417 watchdogreg |= DC_WDOG_JABBERDIS; 1418 CSR_WRITE_4(sc, DC_WATCHDOG, watchdogreg); 1419 } else { 1420 DC_SETBIT(sc, DC_WATCHDOG, DC_WDOG_JABBERDIS); 1421 } 1422 DC_CLRBIT(sc, DC_NETCFG, (DC_NETCFG_PCS | 1423 DC_NETCFG_PORTSEL | DC_NETCFG_SCRAMBLER)); 1424 if (sc->dc_type == DC_TYPE_98713) 1425 DC_SETBIT(sc, DC_NETCFG, (DC_NETCFG_PCS | 1426 DC_NETCFG_SCRAMBLER)); 1427 if (!DC_IS_DAVICOM(sc)) 1428 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL); 1429 DC_CLRBIT(sc, DC_10BTCTRL, 0xFFFF); 1430 } else { 1431 if (DC_IS_PNIC(sc)) { 1432 DC_PN_GPIO_SETBIT(sc, DC_PN_GPIO_SPEEDSEL); 1433 DC_PN_GPIO_SETBIT(sc, DC_PN_GPIO_100TX_LOOP); 1434 DC_SETBIT(sc, DC_PN_NWAY, DC_PN_NWAY_SPEEDSEL); 1435 } 1436 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL); 1437 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PCS); 1438 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_SCRAMBLER); 1439 } 1440 } 1441 1442 if (IFM_SUBTYPE(media) == IFM_10_T) { 1443 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_SPEEDSEL); 1444 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_HEARTBEAT); 1445 if (sc->dc_pmode == DC_PMODE_MII) { 1446 /* There's a write enable bit here that reads as 1. */ 1447 if (DC_IS_INTEL(sc)) { 1448 watchdogreg = CSR_READ_4(sc, DC_WATCHDOG); 1449 watchdogreg &= ~DC_WDOG_CTLWREN; 1450 watchdogreg |= DC_WDOG_JABBERDIS; 1451 CSR_WRITE_4(sc, DC_WATCHDOG, watchdogreg); 1452 } else { 1453 DC_SETBIT(sc, DC_WATCHDOG, DC_WDOG_JABBERDIS); 1454 } 1455 DC_CLRBIT(sc, DC_NETCFG, (DC_NETCFG_PCS | 1456 DC_NETCFG_PORTSEL | DC_NETCFG_SCRAMBLER)); 1457 if (sc->dc_type == DC_TYPE_98713) 1458 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PCS); 1459 if (!DC_IS_DAVICOM(sc)) 1460 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL); 1461 DC_CLRBIT(sc, DC_10BTCTRL, 0xFFFF); 1462 } else { 1463 if (DC_IS_PNIC(sc)) { 1464 DC_PN_GPIO_CLRBIT(sc, DC_PN_GPIO_SPEEDSEL); 1465 DC_PN_GPIO_SETBIT(sc, DC_PN_GPIO_100TX_LOOP); 1466 DC_CLRBIT(sc, DC_PN_NWAY, DC_PN_NWAY_SPEEDSEL); 1467 } 1468 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL); 1469 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_PCS); 1470 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_SCRAMBLER); 1471 if (DC_IS_INTEL(sc)) { 1472 DC_CLRBIT(sc, DC_SIARESET, DC_SIA_RESET); 1473 DC_CLRBIT(sc, DC_10BTCTRL, 0xFFFF); 1474 if ((media & IFM_GMASK) == IFM_FDX) 1475 DC_SETBIT(sc, DC_10BTCTRL, 0x7F3D); 1476 else 1477 DC_SETBIT(sc, DC_10BTCTRL, 0x7F3F); 1478 DC_SETBIT(sc, DC_SIARESET, DC_SIA_RESET); 1479 DC_CLRBIT(sc, DC_10BTCTRL, 1480 DC_TCTL_AUTONEGENBL); 1481 DELAY(20000); 1482 } 1483 } 1484 } 1485 1486 /* 1487 * If this is a Davicom DM9102A card with a DM9801 HomePNA 1488 * PHY and we want HomePNA mode, set the portsel bit to turn 1489 * on the external MII port. 1490 */ 1491 if (DC_IS_DAVICOM(sc)) { 1492 if (IFM_SUBTYPE(media) == IFM_HPNA_1) { 1493 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL); 1494 sc->dc_link = 1; 1495 } else { 1496 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL); 1497 } 1498 } 1499 1500 if ((media & IFM_GMASK) == IFM_FDX) { 1501 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_FULLDUPLEX); 1502 if (sc->dc_pmode == DC_PMODE_SYM && DC_IS_PNIC(sc)) 1503 DC_SETBIT(sc, DC_PN_NWAY, DC_PN_NWAY_DUPLEX); 1504 } else { 1505 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_FULLDUPLEX); 1506 if (sc->dc_pmode == DC_PMODE_SYM && DC_IS_PNIC(sc)) 1507 DC_CLRBIT(sc, DC_PN_NWAY, DC_PN_NWAY_DUPLEX); 1508 } 1509 1510 if (restart) 1511 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_TX_ON | DC_NETCFG_RX_ON); 1512 } 1513 1514 static void 1515 dc_reset(struct dc_softc *sc) 1516 { 1517 int i; 1518 1519 DC_SETBIT(sc, DC_BUSCTL, DC_BUSCTL_RESET); 1520 1521 for (i = 0; i < DC_TIMEOUT; i++) { 1522 DELAY(10); 1523 if (!(CSR_READ_4(sc, DC_BUSCTL) & DC_BUSCTL_RESET)) 1524 break; 1525 } 1526 1527 if (DC_IS_ASIX(sc) || DC_IS_ADMTEK(sc) || DC_IS_CONEXANT(sc) || 1528 DC_IS_XIRCOM(sc) || DC_IS_INTEL(sc) || DC_IS_ULI(sc)) { 1529 DELAY(10000); 1530 DC_CLRBIT(sc, DC_BUSCTL, DC_BUSCTL_RESET); 1531 i = 0; 1532 } 1533 1534 if (i == DC_TIMEOUT) 1535 device_printf(sc->dc_dev, "reset never completed!\n"); 1536 1537 /* Wait a little while for the chip to get its brains in order. */ 1538 DELAY(1000); 1539 1540 CSR_WRITE_4(sc, DC_IMR, 0x00000000); 1541 CSR_WRITE_4(sc, DC_BUSCTL, 0x00000000); 1542 CSR_WRITE_4(sc, DC_NETCFG, 0x00000000); 1543 1544 /* 1545 * Bring the SIA out of reset. In some cases, it looks 1546 * like failing to unreset the SIA soon enough gets it 1547 * into a state where it will never come out of reset 1548 * until we reset the whole chip again. 1549 */ 1550 if (DC_IS_INTEL(sc)) { 1551 DC_SETBIT(sc, DC_SIARESET, DC_SIA_RESET); 1552 CSR_WRITE_4(sc, DC_10BTCTRL, 0xFFFFFFFF); 1553 CSR_WRITE_4(sc, DC_WATCHDOG, 0); 1554 } 1555 } 1556 1557 static const struct dc_type * 1558 dc_devtype(device_t dev) 1559 { 1560 const struct dc_type *t; 1561 uint32_t devid; 1562 uint8_t rev; 1563 1564 t = dc_devs; 1565 devid = pci_get_devid(dev); 1566 rev = pci_get_revid(dev); 1567 1568 while (t->dc_name != NULL) { 1569 if (devid == t->dc_devid && rev >= t->dc_minrev) 1570 return (t); 1571 t++; 1572 } 1573 1574 return (NULL); 1575 } 1576 1577 /* 1578 * Probe for a 21143 or clone chip. Check the PCI vendor and device 1579 * IDs against our list and return a device name if we find a match. 1580 * We do a little bit of extra work to identify the exact type of 1581 * chip. The MX98713 and MX98713A have the same PCI vendor/device ID, 1582 * but different revision IDs. The same is true for 98715/98715A 1583 * chips and the 98725, as well as the ASIX and ADMtek chips. In some 1584 * cases, the exact chip revision affects driver behavior. 1585 */ 1586 static int 1587 dc_probe(device_t dev) 1588 { 1589 const struct dc_type *t; 1590 1591 t = dc_devtype(dev); 1592 1593 if (t != NULL) { 1594 device_set_desc(dev, t->dc_name); 1595 return (BUS_PROBE_DEFAULT); 1596 } 1597 1598 return (ENXIO); 1599 } 1600 1601 static void 1602 dc_apply_fixup(struct dc_softc *sc, int media) 1603 { 1604 struct dc_mediainfo *m; 1605 uint8_t *p; 1606 int i; 1607 uint32_t reg; 1608 1609 m = sc->dc_mi; 1610 1611 while (m != NULL) { 1612 if (m->dc_media == media) 1613 break; 1614 m = m->dc_next; 1615 } 1616 1617 if (m == NULL) 1618 return; 1619 1620 for (i = 0, p = m->dc_reset_ptr; i < m->dc_reset_len; i++, p += 2) { 1621 reg = (p[0] | (p[1] << 8)) << 16; 1622 CSR_WRITE_4(sc, DC_WATCHDOG, reg); 1623 } 1624 1625 for (i = 0, p = m->dc_gp_ptr; i < m->dc_gp_len; i++, p += 2) { 1626 reg = (p[0] | (p[1] << 8)) << 16; 1627 CSR_WRITE_4(sc, DC_WATCHDOG, reg); 1628 } 1629 } 1630 1631 static int 1632 dc_decode_leaf_sia(struct dc_softc *sc, struct dc_eblock_sia *l) 1633 { 1634 struct dc_mediainfo *m; 1635 1636 m = malloc(sizeof(struct dc_mediainfo), M_DEVBUF, M_NOWAIT | M_ZERO); 1637 if (m == NULL) { 1638 device_printf(sc->dc_dev, "Could not allocate mediainfo\n"); 1639 return (ENOMEM); 1640 } 1641 switch (l->dc_sia_code & ~DC_SIA_CODE_EXT) { 1642 case DC_SIA_CODE_10BT: 1643 m->dc_media = IFM_10_T; 1644 break; 1645 case DC_SIA_CODE_10BT_FDX: 1646 m->dc_media = IFM_10_T | IFM_FDX; 1647 break; 1648 case DC_SIA_CODE_10B2: 1649 m->dc_media = IFM_10_2; 1650 break; 1651 case DC_SIA_CODE_10B5: 1652 m->dc_media = IFM_10_5; 1653 break; 1654 default: 1655 break; 1656 } 1657 1658 /* 1659 * We need to ignore CSR13, CSR14, CSR15 for SIA mode. 1660 * Things apparently already work for cards that do 1661 * supply Media Specific Data. 1662 */ 1663 if (l->dc_sia_code & DC_SIA_CODE_EXT) { 1664 m->dc_gp_len = 2; 1665 m->dc_gp_ptr = 1666 (uint8_t *)&l->dc_un.dc_sia_ext.dc_sia_gpio_ctl; 1667 } else { 1668 m->dc_gp_len = 2; 1669 m->dc_gp_ptr = 1670 (uint8_t *)&l->dc_un.dc_sia_noext.dc_sia_gpio_ctl; 1671 } 1672 1673 m->dc_next = sc->dc_mi; 1674 sc->dc_mi = m; 1675 1676 sc->dc_pmode = DC_PMODE_SIA; 1677 return (0); 1678 } 1679 1680 static int 1681 dc_decode_leaf_sym(struct dc_softc *sc, struct dc_eblock_sym *l) 1682 { 1683 struct dc_mediainfo *m; 1684 1685 m = malloc(sizeof(struct dc_mediainfo), M_DEVBUF, M_NOWAIT | M_ZERO); 1686 if (m == NULL) { 1687 device_printf(sc->dc_dev, "Could not allocate mediainfo\n"); 1688 return (ENOMEM); 1689 } 1690 if (l->dc_sym_code == DC_SYM_CODE_100BT) 1691 m->dc_media = IFM_100_TX; 1692 1693 if (l->dc_sym_code == DC_SYM_CODE_100BT_FDX) 1694 m->dc_media = IFM_100_TX | IFM_FDX; 1695 1696 m->dc_gp_len = 2; 1697 m->dc_gp_ptr = (uint8_t *)&l->dc_sym_gpio_ctl; 1698 1699 m->dc_next = sc->dc_mi; 1700 sc->dc_mi = m; 1701 1702 sc->dc_pmode = DC_PMODE_SYM; 1703 return (0); 1704 } 1705 1706 static int 1707 dc_decode_leaf_mii(struct dc_softc *sc, struct dc_eblock_mii *l) 1708 { 1709 struct dc_mediainfo *m; 1710 uint8_t *p; 1711 1712 m = malloc(sizeof(struct dc_mediainfo), M_DEVBUF, M_NOWAIT | M_ZERO); 1713 if (m == NULL) { 1714 device_printf(sc->dc_dev, "Could not allocate mediainfo\n"); 1715 return (ENOMEM); 1716 } 1717 /* We abuse IFM_AUTO to represent MII. */ 1718 m->dc_media = IFM_AUTO; 1719 m->dc_gp_len = l->dc_gpr_len; 1720 1721 p = (uint8_t *)l; 1722 p += sizeof(struct dc_eblock_mii); 1723 m->dc_gp_ptr = p; 1724 p += 2 * l->dc_gpr_len; 1725 m->dc_reset_len = *p; 1726 p++; 1727 m->dc_reset_ptr = p; 1728 1729 m->dc_next = sc->dc_mi; 1730 sc->dc_mi = m; 1731 return (0); 1732 } 1733 1734 static int 1735 dc_read_srom(struct dc_softc *sc, int bits) 1736 { 1737 int size; 1738 1739 size = DC_ROM_SIZE(bits); 1740 sc->dc_srom = malloc(size, M_DEVBUF, M_NOWAIT | M_ZERO); 1741 if (sc->dc_srom == NULL) { 1742 device_printf(sc->dc_dev, "Could not allocate SROM buffer\n"); 1743 return (ENOMEM); 1744 } 1745 dc_read_eeprom(sc, (caddr_t)sc->dc_srom, 0, (size / 2), 0); 1746 return (0); 1747 } 1748 1749 static int 1750 dc_parse_21143_srom(struct dc_softc *sc) 1751 { 1752 struct dc_leaf_hdr *lhdr; 1753 struct dc_eblock_hdr *hdr; 1754 int error, have_mii, i, loff; 1755 char *ptr; 1756 1757 have_mii = 0; 1758 loff = sc->dc_srom[27]; 1759 lhdr = (struct dc_leaf_hdr *)&(sc->dc_srom[loff]); 1760 1761 ptr = (char *)lhdr; 1762 ptr += sizeof(struct dc_leaf_hdr) - 1; 1763 /* 1764 * Look if we got a MII media block. 1765 */ 1766 for (i = 0; i < lhdr->dc_mcnt; i++) { 1767 hdr = (struct dc_eblock_hdr *)ptr; 1768 if (hdr->dc_type == DC_EBLOCK_MII) 1769 have_mii++; 1770 1771 ptr += (hdr->dc_len & 0x7F); 1772 ptr++; 1773 } 1774 1775 /* 1776 * Do the same thing again. Only use SIA and SYM media 1777 * blocks if no MII media block is available. 1778 */ 1779 ptr = (char *)lhdr; 1780 ptr += sizeof(struct dc_leaf_hdr) - 1; 1781 error = 0; 1782 for (i = 0; i < lhdr->dc_mcnt; i++) { 1783 hdr = (struct dc_eblock_hdr *)ptr; 1784 switch (hdr->dc_type) { 1785 case DC_EBLOCK_MII: 1786 error = dc_decode_leaf_mii(sc, (struct dc_eblock_mii *)hdr); 1787 break; 1788 case DC_EBLOCK_SIA: 1789 if (! have_mii) 1790 error = dc_decode_leaf_sia(sc, 1791 (struct dc_eblock_sia *)hdr); 1792 break; 1793 case DC_EBLOCK_SYM: 1794 if (! have_mii) 1795 error = dc_decode_leaf_sym(sc, 1796 (struct dc_eblock_sym *)hdr); 1797 break; 1798 default: 1799 /* Don't care. Yet. */ 1800 break; 1801 } 1802 ptr += (hdr->dc_len & 0x7F); 1803 ptr++; 1804 } 1805 return (error); 1806 } 1807 1808 static void 1809 dc_dma_map_addr(void *arg, bus_dma_segment_t *segs, int nseg, int error) 1810 { 1811 bus_addr_t *paddr; 1812 1813 KASSERT(nseg == 1, 1814 ("%s: wrong number of segments (%d)", __func__, nseg)); 1815 paddr = arg; 1816 *paddr = segs->ds_addr; 1817 } 1818 1819 static int 1820 dc_dma_alloc(struct dc_softc *sc) 1821 { 1822 int error, i; 1823 1824 error = bus_dma_tag_create(bus_get_dma_tag(sc->dc_dev), 1, 0, 1825 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL, 1826 BUS_SPACE_MAXSIZE_32BIT, 0, BUS_SPACE_MAXSIZE_32BIT, 0, 1827 NULL, NULL, &sc->dc_ptag); 1828 if (error) { 1829 device_printf(sc->dc_dev, 1830 "failed to allocate parent DMA tag\n"); 1831 goto fail; 1832 } 1833 1834 /* Allocate a busdma tag and DMA safe memory for TX/RX descriptors. */ 1835 error = bus_dma_tag_create(sc->dc_ptag, DC_LIST_ALIGN, 0, 1836 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL, DC_RX_LIST_SZ, 1, 1837 DC_RX_LIST_SZ, 0, NULL, NULL, &sc->dc_rx_ltag); 1838 if (error) { 1839 device_printf(sc->dc_dev, "failed to create RX list DMA tag\n"); 1840 goto fail; 1841 } 1842 1843 error = bus_dma_tag_create(sc->dc_ptag, DC_LIST_ALIGN, 0, 1844 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL, DC_TX_LIST_SZ, 1, 1845 DC_TX_LIST_SZ, 0, NULL, NULL, &sc->dc_tx_ltag); 1846 if (error) { 1847 device_printf(sc->dc_dev, "failed to create TX list DMA tag\n"); 1848 goto fail; 1849 } 1850 1851 /* RX descriptor list. */ 1852 error = bus_dmamem_alloc(sc->dc_rx_ltag, 1853 (void **)&sc->dc_ldata.dc_rx_list, BUS_DMA_NOWAIT | 1854 BUS_DMA_ZERO | BUS_DMA_COHERENT, &sc->dc_rx_lmap); 1855 if (error) { 1856 device_printf(sc->dc_dev, 1857 "failed to allocate DMA'able memory for RX list\n"); 1858 goto fail; 1859 } 1860 error = bus_dmamap_load(sc->dc_rx_ltag, sc->dc_rx_lmap, 1861 sc->dc_ldata.dc_rx_list, DC_RX_LIST_SZ, dc_dma_map_addr, 1862 &sc->dc_ldata.dc_rx_list_paddr, BUS_DMA_NOWAIT); 1863 if (error) { 1864 device_printf(sc->dc_dev, 1865 "failed to load DMA'able memory for RX list\n"); 1866 goto fail; 1867 } 1868 /* TX descriptor list. */ 1869 error = bus_dmamem_alloc(sc->dc_tx_ltag, 1870 (void **)&sc->dc_ldata.dc_tx_list, BUS_DMA_NOWAIT | 1871 BUS_DMA_ZERO | BUS_DMA_COHERENT, &sc->dc_tx_lmap); 1872 if (error) { 1873 device_printf(sc->dc_dev, 1874 "failed to allocate DMA'able memory for TX list\n"); 1875 goto fail; 1876 } 1877 error = bus_dmamap_load(sc->dc_tx_ltag, sc->dc_tx_lmap, 1878 sc->dc_ldata.dc_tx_list, DC_TX_LIST_SZ, dc_dma_map_addr, 1879 &sc->dc_ldata.dc_tx_list_paddr, BUS_DMA_NOWAIT); 1880 if (error) { 1881 device_printf(sc->dc_dev, 1882 "cannot load DMA'able memory for TX list\n"); 1883 goto fail; 1884 } 1885 1886 /* 1887 * Allocate a busdma tag and DMA safe memory for the multicast 1888 * setup frame. 1889 */ 1890 error = bus_dma_tag_create(sc->dc_ptag, DC_LIST_ALIGN, 0, 1891 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL, 1892 DC_SFRAME_LEN + DC_MIN_FRAMELEN, 1, DC_SFRAME_LEN + DC_MIN_FRAMELEN, 1893 0, NULL, NULL, &sc->dc_stag); 1894 if (error) { 1895 device_printf(sc->dc_dev, 1896 "failed to create DMA tag for setup frame\n"); 1897 goto fail; 1898 } 1899 error = bus_dmamem_alloc(sc->dc_stag, (void **)&sc->dc_cdata.dc_sbuf, 1900 BUS_DMA_NOWAIT, &sc->dc_smap); 1901 if (error) { 1902 device_printf(sc->dc_dev, 1903 "failed to allocate DMA'able memory for setup frame\n"); 1904 goto fail; 1905 } 1906 error = bus_dmamap_load(sc->dc_stag, sc->dc_smap, sc->dc_cdata.dc_sbuf, 1907 DC_SFRAME_LEN, dc_dma_map_addr, &sc->dc_saddr, BUS_DMA_NOWAIT); 1908 if (error) { 1909 device_printf(sc->dc_dev, 1910 "cannot load DMA'able memory for setup frame\n"); 1911 goto fail; 1912 } 1913 1914 /* Allocate a busdma tag for RX mbufs. */ 1915 error = bus_dma_tag_create(sc->dc_ptag, DC_RXBUF_ALIGN, 0, 1916 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL, 1917 MCLBYTES, 1, MCLBYTES, 0, NULL, NULL, &sc->dc_rx_mtag); 1918 if (error) { 1919 device_printf(sc->dc_dev, "failed to create RX mbuf tag\n"); 1920 goto fail; 1921 } 1922 1923 /* Allocate a busdma tag for TX mbufs. */ 1924 error = bus_dma_tag_create(sc->dc_ptag, 1, 0, 1925 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL, 1926 MCLBYTES * DC_MAXFRAGS, DC_MAXFRAGS, MCLBYTES, 1927 0, NULL, NULL, &sc->dc_tx_mtag); 1928 if (error) { 1929 device_printf(sc->dc_dev, "failed to create TX mbuf tag\n"); 1930 goto fail; 1931 } 1932 1933 /* Create the TX/RX busdma maps. */ 1934 for (i = 0; i < DC_TX_LIST_CNT; i++) { 1935 error = bus_dmamap_create(sc->dc_tx_mtag, 0, 1936 &sc->dc_cdata.dc_tx_map[i]); 1937 if (error) { 1938 device_printf(sc->dc_dev, 1939 "failed to create TX mbuf dmamap\n"); 1940 goto fail; 1941 } 1942 } 1943 for (i = 0; i < DC_RX_LIST_CNT; i++) { 1944 error = bus_dmamap_create(sc->dc_rx_mtag, 0, 1945 &sc->dc_cdata.dc_rx_map[i]); 1946 if (error) { 1947 device_printf(sc->dc_dev, 1948 "failed to create RX mbuf dmamap\n"); 1949 goto fail; 1950 } 1951 } 1952 error = bus_dmamap_create(sc->dc_rx_mtag, 0, &sc->dc_sparemap); 1953 if (error) { 1954 device_printf(sc->dc_dev, 1955 "failed to create spare RX mbuf dmamap\n"); 1956 goto fail; 1957 } 1958 1959 fail: 1960 return (error); 1961 } 1962 1963 static void 1964 dc_dma_free(struct dc_softc *sc) 1965 { 1966 int i; 1967 1968 /* RX buffers. */ 1969 if (sc->dc_rx_mtag != NULL) { 1970 for (i = 0; i < DC_RX_LIST_CNT; i++) { 1971 if (sc->dc_cdata.dc_rx_map[i] != NULL) 1972 bus_dmamap_destroy(sc->dc_rx_mtag, 1973 sc->dc_cdata.dc_rx_map[i]); 1974 } 1975 if (sc->dc_sparemap != NULL) 1976 bus_dmamap_destroy(sc->dc_rx_mtag, sc->dc_sparemap); 1977 bus_dma_tag_destroy(sc->dc_rx_mtag); 1978 } 1979 1980 /* TX buffers. */ 1981 if (sc->dc_rx_mtag != NULL) { 1982 for (i = 0; i < DC_TX_LIST_CNT; i++) { 1983 if (sc->dc_cdata.dc_tx_map[i] != NULL) 1984 bus_dmamap_destroy(sc->dc_tx_mtag, 1985 sc->dc_cdata.dc_tx_map[i]); 1986 } 1987 bus_dma_tag_destroy(sc->dc_tx_mtag); 1988 } 1989 1990 /* RX descriptor list. */ 1991 if (sc->dc_rx_ltag) { 1992 if (sc->dc_ldata.dc_rx_list_paddr != 0) 1993 bus_dmamap_unload(sc->dc_rx_ltag, sc->dc_rx_lmap); 1994 if (sc->dc_ldata.dc_rx_list != NULL) 1995 bus_dmamem_free(sc->dc_rx_ltag, sc->dc_ldata.dc_rx_list, 1996 sc->dc_rx_lmap); 1997 bus_dma_tag_destroy(sc->dc_rx_ltag); 1998 } 1999 2000 /* TX descriptor list. */ 2001 if (sc->dc_tx_ltag) { 2002 if (sc->dc_ldata.dc_tx_list_paddr != 0) 2003 bus_dmamap_unload(sc->dc_tx_ltag, sc->dc_tx_lmap); 2004 if (sc->dc_ldata.dc_tx_list != NULL) 2005 bus_dmamem_free(sc->dc_tx_ltag, sc->dc_ldata.dc_tx_list, 2006 sc->dc_tx_lmap); 2007 bus_dma_tag_destroy(sc->dc_tx_ltag); 2008 } 2009 2010 /* multicast setup frame. */ 2011 if (sc->dc_stag) { 2012 if (sc->dc_saddr != 0) 2013 bus_dmamap_unload(sc->dc_stag, sc->dc_smap); 2014 if (sc->dc_cdata.dc_sbuf != NULL) 2015 bus_dmamem_free(sc->dc_stag, sc->dc_cdata.dc_sbuf, 2016 sc->dc_smap); 2017 bus_dma_tag_destroy(sc->dc_stag); 2018 } 2019 } 2020 2021 /* 2022 * Attach the interface. Allocate softc structures, do ifmedia 2023 * setup and ethernet/BPF attach. 2024 */ 2025 static int 2026 dc_attach(device_t dev) 2027 { 2028 uint32_t eaddr[(ETHER_ADDR_LEN+3)/4]; 2029 uint32_t command; 2030 struct dc_softc *sc; 2031 if_t ifp; 2032 struct dc_mediainfo *m; 2033 uint32_t reg, revision; 2034 uint16_t *srom; 2035 int error, mac_offset, n, phy, rid, tmp; 2036 uint8_t *mac; 2037 2038 sc = device_get_softc(dev); 2039 sc->dc_dev = dev; 2040 2041 mtx_init(&sc->dc_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 2042 MTX_DEF); 2043 2044 /* 2045 * Map control/status registers. 2046 */ 2047 pci_enable_busmaster(dev); 2048 2049 rid = DC_RID; 2050 sc->dc_res = bus_alloc_resource_any(dev, DC_RES, &rid, RF_ACTIVE); 2051 2052 if (sc->dc_res == NULL) { 2053 device_printf(dev, "couldn't map ports/memory\n"); 2054 error = ENXIO; 2055 goto fail; 2056 } 2057 2058 sc->dc_btag = rman_get_bustag(sc->dc_res); 2059 sc->dc_bhandle = rman_get_bushandle(sc->dc_res); 2060 2061 /* Allocate interrupt. */ 2062 rid = 0; 2063 sc->dc_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 2064 RF_SHAREABLE | RF_ACTIVE); 2065 2066 if (sc->dc_irq == NULL) { 2067 device_printf(dev, "couldn't map interrupt\n"); 2068 error = ENXIO; 2069 goto fail; 2070 } 2071 2072 /* Need this info to decide on a chip type. */ 2073 sc->dc_info = dc_devtype(dev); 2074 revision = pci_get_revid(dev); 2075 2076 error = 0; 2077 /* Get the eeprom width, but PNIC and XIRCOM have diff eeprom */ 2078 if (sc->dc_info->dc_devid != 2079 DC_DEVID(DC_VENDORID_LO, DC_DEVICEID_82C168) && 2080 sc->dc_info->dc_devid != 2081 DC_DEVID(DC_VENDORID_XIRCOM, DC_DEVICEID_X3201)) 2082 dc_eeprom_width(sc); 2083 2084 switch (sc->dc_info->dc_devid) { 2085 case DC_DEVID(DC_VENDORID_DEC, DC_DEVICEID_21143): 2086 sc->dc_type = DC_TYPE_21143; 2087 sc->dc_flags |= DC_TX_POLL | DC_TX_USE_TX_INTR; 2088 sc->dc_flags |= DC_REDUCED_MII_POLL; 2089 /* Save EEPROM contents so we can parse them later. */ 2090 error = dc_read_srom(sc, sc->dc_romwidth); 2091 if (error != 0) 2092 goto fail; 2093 break; 2094 case DC_DEVID(DC_VENDORID_DAVICOM, DC_DEVICEID_DM9009): 2095 case DC_DEVID(DC_VENDORID_DAVICOM, DC_DEVICEID_DM9100): 2096 case DC_DEVID(DC_VENDORID_DAVICOM, DC_DEVICEID_DM9102): 2097 sc->dc_type = DC_TYPE_DM9102; 2098 sc->dc_flags |= DC_TX_COALESCE | DC_TX_INTR_ALWAYS; 2099 sc->dc_flags |= DC_REDUCED_MII_POLL | DC_TX_STORENFWD; 2100 sc->dc_flags |= DC_TX_ALIGN; 2101 sc->dc_pmode = DC_PMODE_MII; 2102 2103 /* Increase the latency timer value. */ 2104 pci_write_config(dev, PCIR_LATTIMER, 0x80, 1); 2105 break; 2106 case DC_DEVID(DC_VENDORID_ADMTEK, DC_DEVICEID_AL981): 2107 sc->dc_type = DC_TYPE_AL981; 2108 sc->dc_flags |= DC_TX_USE_TX_INTR; 2109 sc->dc_flags |= DC_TX_ADMTEK_WAR; 2110 sc->dc_pmode = DC_PMODE_MII; 2111 error = dc_read_srom(sc, sc->dc_romwidth); 2112 if (error != 0) 2113 goto fail; 2114 break; 2115 case DC_DEVID(DC_VENDORID_ADMTEK, DC_DEVICEID_AN983): 2116 case DC_DEVID(DC_VENDORID_ADMTEK, DC_DEVICEID_AN985): 2117 case DC_DEVID(DC_VENDORID_ADMTEK, DC_DEVICEID_ADM9511): 2118 case DC_DEVID(DC_VENDORID_ADMTEK, DC_DEVICEID_ADM9513): 2119 case DC_DEVID(DC_VENDORID_DLINK, DC_DEVICEID_DRP32TXD): 2120 case DC_DEVID(DC_VENDORID_ABOCOM, DC_DEVICEID_FE2500): 2121 case DC_DEVID(DC_VENDORID_ABOCOM, DC_DEVICEID_FE2500MX): 2122 case DC_DEVID(DC_VENDORID_ACCTON, DC_DEVICEID_EN2242): 2123 case DC_DEVID(DC_VENDORID_HAWKING, DC_DEVICEID_HAWKING_PN672TX): 2124 case DC_DEVID(DC_VENDORID_PLANEX, DC_DEVICEID_FNW3602T): 2125 case DC_DEVID(DC_VENDORID_3COM, DC_DEVICEID_3CSOHOB): 2126 case DC_DEVID(DC_VENDORID_MICROSOFT, DC_DEVICEID_MSMN120): 2127 case DC_DEVID(DC_VENDORID_MICROSOFT, DC_DEVICEID_MSMN130): 2128 case DC_DEVID(DC_VENDORID_LINKSYS, DC_DEVICEID_PCMPC200_AB08): 2129 case DC_DEVID(DC_VENDORID_LINKSYS, DC_DEVICEID_PCMPC200_AB09): 2130 sc->dc_type = DC_TYPE_AN983; 2131 sc->dc_flags |= DC_64BIT_HASH; 2132 sc->dc_flags |= DC_TX_USE_TX_INTR; 2133 sc->dc_flags |= DC_TX_ADMTEK_WAR; 2134 sc->dc_pmode = DC_PMODE_MII; 2135 /* Don't read SROM for - auto-loaded on reset */ 2136 break; 2137 case DC_DEVID(DC_VENDORID_MX, DC_DEVICEID_98713): 2138 case DC_DEVID(DC_VENDORID_CP, DC_DEVICEID_98713_CP): 2139 if (revision < DC_REVISION_98713A) { 2140 sc->dc_type = DC_TYPE_98713; 2141 } 2142 if (revision >= DC_REVISION_98713A) { 2143 sc->dc_type = DC_TYPE_98713A; 2144 sc->dc_flags |= DC_21143_NWAY; 2145 } 2146 sc->dc_flags |= DC_REDUCED_MII_POLL; 2147 sc->dc_flags |= DC_TX_POLL | DC_TX_USE_TX_INTR; 2148 break; 2149 case DC_DEVID(DC_VENDORID_MX, DC_DEVICEID_987x5): 2150 case DC_DEVID(DC_VENDORID_ACCTON, DC_DEVICEID_EN1217): 2151 /* 2152 * Macronix MX98715AEC-C/D/E parts have only a 2153 * 128-bit hash table. We need to deal with these 2154 * in the same manner as the PNIC II so that we 2155 * get the right number of bits out of the 2156 * CRC routine. 2157 */ 2158 if (revision >= DC_REVISION_98715AEC_C && 2159 revision < DC_REVISION_98725) 2160 sc->dc_flags |= DC_128BIT_HASH; 2161 sc->dc_type = DC_TYPE_987x5; 2162 sc->dc_flags |= DC_TX_POLL | DC_TX_USE_TX_INTR; 2163 sc->dc_flags |= DC_REDUCED_MII_POLL | DC_21143_NWAY; 2164 break; 2165 case DC_DEVID(DC_VENDORID_MX, DC_DEVICEID_98727): 2166 sc->dc_type = DC_TYPE_987x5; 2167 sc->dc_flags |= DC_TX_POLL | DC_TX_USE_TX_INTR; 2168 sc->dc_flags |= DC_REDUCED_MII_POLL | DC_21143_NWAY; 2169 break; 2170 case DC_DEVID(DC_VENDORID_LO, DC_DEVICEID_82C115): 2171 sc->dc_type = DC_TYPE_PNICII; 2172 sc->dc_flags |= DC_TX_POLL | DC_TX_USE_TX_INTR | DC_128BIT_HASH; 2173 sc->dc_flags |= DC_REDUCED_MII_POLL | DC_21143_NWAY; 2174 break; 2175 case DC_DEVID(DC_VENDORID_LO, DC_DEVICEID_82C168): 2176 sc->dc_type = DC_TYPE_PNIC; 2177 sc->dc_flags |= DC_TX_STORENFWD | DC_TX_INTR_ALWAYS; 2178 sc->dc_flags |= DC_PNIC_RX_BUG_WAR; 2179 sc->dc_pnic_rx_buf = malloc(DC_RXLEN * 5, M_DEVBUF, M_NOWAIT); 2180 if (sc->dc_pnic_rx_buf == NULL) { 2181 device_printf(sc->dc_dev, 2182 "Could not allocate PNIC RX buffer\n"); 2183 error = ENOMEM; 2184 goto fail; 2185 } 2186 if (revision < DC_REVISION_82C169) 2187 sc->dc_pmode = DC_PMODE_SYM; 2188 break; 2189 case DC_DEVID(DC_VENDORID_ASIX, DC_DEVICEID_AX88140A): 2190 sc->dc_type = DC_TYPE_ASIX; 2191 sc->dc_flags |= DC_TX_USE_TX_INTR | DC_TX_INTR_FIRSTFRAG; 2192 sc->dc_flags |= DC_REDUCED_MII_POLL; 2193 sc->dc_pmode = DC_PMODE_MII; 2194 break; 2195 case DC_DEVID(DC_VENDORID_XIRCOM, DC_DEVICEID_X3201): 2196 sc->dc_type = DC_TYPE_XIRCOM; 2197 sc->dc_flags |= DC_TX_INTR_ALWAYS | DC_TX_COALESCE | 2198 DC_TX_ALIGN; 2199 /* 2200 * We don't actually need to coalesce, but we're doing 2201 * it to obtain a double word aligned buffer. 2202 * The DC_TX_COALESCE flag is required. 2203 */ 2204 sc->dc_pmode = DC_PMODE_MII; 2205 break; 2206 case DC_DEVID(DC_VENDORID_CONEXANT, DC_DEVICEID_RS7112): 2207 sc->dc_type = DC_TYPE_CONEXANT; 2208 sc->dc_flags |= DC_TX_INTR_ALWAYS; 2209 sc->dc_flags |= DC_REDUCED_MII_POLL; 2210 sc->dc_pmode = DC_PMODE_MII; 2211 error = dc_read_srom(sc, sc->dc_romwidth); 2212 if (error != 0) 2213 goto fail; 2214 break; 2215 case DC_DEVID(DC_VENDORID_ULI, DC_DEVICEID_M5261): 2216 case DC_DEVID(DC_VENDORID_ULI, DC_DEVICEID_M5263): 2217 if (sc->dc_info->dc_devid == 2218 DC_DEVID(DC_VENDORID_ULI, DC_DEVICEID_M5261)) 2219 sc->dc_type = DC_TYPE_ULI_M5261; 2220 else 2221 sc->dc_type = DC_TYPE_ULI_M5263; 2222 /* TX buffers should be aligned on 4 byte boundary. */ 2223 sc->dc_flags |= DC_TX_INTR_ALWAYS | DC_TX_COALESCE | 2224 DC_TX_ALIGN; 2225 sc->dc_pmode = DC_PMODE_MII; 2226 error = dc_read_srom(sc, sc->dc_romwidth); 2227 if (error != 0) 2228 goto fail; 2229 break; 2230 default: 2231 device_printf(dev, "unknown device: %x\n", 2232 sc->dc_info->dc_devid); 2233 break; 2234 } 2235 2236 /* Save the cache line size. */ 2237 if (DC_IS_DAVICOM(sc)) 2238 sc->dc_cachesize = 0; 2239 else 2240 sc->dc_cachesize = pci_get_cachelnsz(dev); 2241 2242 /* Reset the adapter. */ 2243 dc_reset(sc); 2244 2245 /* Take 21143 out of snooze mode */ 2246 if (DC_IS_INTEL(sc) || DC_IS_XIRCOM(sc)) { 2247 command = pci_read_config(dev, DC_PCI_CFDD, 4); 2248 command &= ~(DC_CFDD_SNOOZE_MODE | DC_CFDD_SLEEP_MODE); 2249 pci_write_config(dev, DC_PCI_CFDD, command, 4); 2250 } 2251 2252 /* 2253 * Try to learn something about the supported media. 2254 * We know that ASIX and ADMtek and Davicom devices 2255 * will *always* be using MII media, so that's a no-brainer. 2256 * The tricky ones are the Macronix/PNIC II and the 2257 * Intel 21143. 2258 */ 2259 if (DC_IS_INTEL(sc)) { 2260 error = dc_parse_21143_srom(sc); 2261 if (error != 0) 2262 goto fail; 2263 } else if (DC_IS_MACRONIX(sc) || DC_IS_PNICII(sc)) { 2264 if (sc->dc_type == DC_TYPE_98713) 2265 sc->dc_pmode = DC_PMODE_MII; 2266 else 2267 sc->dc_pmode = DC_PMODE_SYM; 2268 } else if (!sc->dc_pmode) 2269 sc->dc_pmode = DC_PMODE_MII; 2270 2271 /* 2272 * Get station address from the EEPROM. 2273 */ 2274 switch(sc->dc_type) { 2275 case DC_TYPE_98713: 2276 case DC_TYPE_98713A: 2277 case DC_TYPE_987x5: 2278 case DC_TYPE_PNICII: 2279 dc_read_eeprom(sc, (caddr_t)&mac_offset, 2280 (DC_EE_NODEADDR_OFFSET / 2), 1, 0); 2281 dc_read_eeprom(sc, (caddr_t)&eaddr, (mac_offset / 2), 3, 0); 2282 break; 2283 case DC_TYPE_PNIC: 2284 dc_read_eeprom(sc, (caddr_t)&eaddr, 0, 3, 1); 2285 break; 2286 case DC_TYPE_DM9102: 2287 dc_read_eeprom(sc, (caddr_t)&eaddr, DC_EE_NODEADDR, 3, 0); 2288 break; 2289 case DC_TYPE_21143: 2290 case DC_TYPE_ASIX: 2291 dc_read_eeprom(sc, (caddr_t)&eaddr, DC_EE_NODEADDR, 3, 0); 2292 break; 2293 case DC_TYPE_AL981: 2294 case DC_TYPE_AN983: 2295 reg = CSR_READ_4(sc, DC_AL_PAR0); 2296 mac = (uint8_t *)&eaddr[0]; 2297 mac[0] = (reg >> 0) & 0xff; 2298 mac[1] = (reg >> 8) & 0xff; 2299 mac[2] = (reg >> 16) & 0xff; 2300 mac[3] = (reg >> 24) & 0xff; 2301 reg = CSR_READ_4(sc, DC_AL_PAR1); 2302 mac[4] = (reg >> 0) & 0xff; 2303 mac[5] = (reg >> 8) & 0xff; 2304 break; 2305 case DC_TYPE_CONEXANT: 2306 bcopy(sc->dc_srom + DC_CONEXANT_EE_NODEADDR, &eaddr, 2307 ETHER_ADDR_LEN); 2308 break; 2309 case DC_TYPE_XIRCOM: 2310 /* The MAC comes from the CIS. */ 2311 mac = pci_get_ether(dev); 2312 if (!mac) { 2313 device_printf(dev, "No station address in CIS!\n"); 2314 error = ENXIO; 2315 goto fail; 2316 } 2317 bcopy(mac, eaddr, ETHER_ADDR_LEN); 2318 break; 2319 case DC_TYPE_ULI_M5261: 2320 case DC_TYPE_ULI_M5263: 2321 srom = (uint16_t *)sc->dc_srom; 2322 if (srom == NULL || *srom == 0xFFFF || *srom == 0) { 2323 /* 2324 * No valid SROM present, read station address 2325 * from ID Table. 2326 */ 2327 device_printf(dev, 2328 "Reading station address from ID Table.\n"); 2329 CSR_WRITE_4(sc, DC_BUSCTL, 0x10000); 2330 CSR_WRITE_4(sc, DC_SIARESET, 0x01C0); 2331 CSR_WRITE_4(sc, DC_10BTCTRL, 0x0000); 2332 CSR_WRITE_4(sc, DC_10BTCTRL, 0x0010); 2333 CSR_WRITE_4(sc, DC_10BTCTRL, 0x0000); 2334 CSR_WRITE_4(sc, DC_SIARESET, 0x0000); 2335 CSR_WRITE_4(sc, DC_SIARESET, 0x01B0); 2336 mac = (uint8_t *)eaddr; 2337 for (n = 0; n < ETHER_ADDR_LEN; n++) 2338 mac[n] = (uint8_t)CSR_READ_4(sc, DC_10BTCTRL); 2339 CSR_WRITE_4(sc, DC_SIARESET, 0x0000); 2340 CSR_WRITE_4(sc, DC_BUSCTL, 0x0000); 2341 DELAY(10); 2342 } else 2343 dc_read_eeprom(sc, (caddr_t)&eaddr, DC_EE_NODEADDR, 3, 2344 0); 2345 break; 2346 default: 2347 dc_read_eeprom(sc, (caddr_t)&eaddr, DC_EE_NODEADDR, 3, 0); 2348 break; 2349 } 2350 2351 bcopy(eaddr, sc->dc_eaddr, sizeof(eaddr)); 2352 /* 2353 * If we still have invalid station address, see whether we can 2354 * find station address for chip 0. Some multi-port controllers 2355 * just store station address for chip 0 if they have a shared 2356 * SROM. 2357 */ 2358 if ((sc->dc_eaddr[0] == 0 && (sc->dc_eaddr[1] & ~0xffff) == 0) || 2359 (sc->dc_eaddr[0] == 0xffffffff && 2360 (sc->dc_eaddr[1] & 0xffff) == 0xffff)) { 2361 error = dc_check_multiport(sc); 2362 if (error == 0) { 2363 bcopy(sc->dc_eaddr, eaddr, sizeof(eaddr)); 2364 /* Extract media information. */ 2365 if (DC_IS_INTEL(sc) && sc->dc_srom != NULL) { 2366 while (sc->dc_mi != NULL) { 2367 m = sc->dc_mi->dc_next; 2368 free(sc->dc_mi, M_DEVBUF); 2369 sc->dc_mi = m; 2370 } 2371 error = dc_parse_21143_srom(sc); 2372 if (error != 0) 2373 goto fail; 2374 } 2375 } else if (error == ENOMEM) 2376 goto fail; 2377 else 2378 error = 0; 2379 } 2380 2381 if ((error = dc_dma_alloc(sc)) != 0) 2382 goto fail; 2383 2384 ifp = sc->dc_ifp = if_alloc(IFT_ETHER); 2385 if (ifp == NULL) { 2386 device_printf(dev, "can not if_alloc()\n"); 2387 error = ENOSPC; 2388 goto fail; 2389 } 2390 if_setsoftc(ifp, sc); 2391 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 2392 if_setflags(ifp, IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST); 2393 if_setioctlfn(ifp, dc_ioctl); 2394 if_setstartfn(ifp, dc_start); 2395 if_setinitfn(ifp, dc_init); 2396 if_setsendqlen(ifp, DC_TX_LIST_CNT - 1); 2397 if_setsendqready(ifp); 2398 2399 /* 2400 * Do MII setup. If this is a 21143, check for a PHY on the 2401 * MII bus after applying any necessary fixups to twiddle the 2402 * GPIO bits. If we don't end up finding a PHY, restore the 2403 * old selection (SIA only or SIA/SYM) and attach the dcphy 2404 * driver instead. 2405 */ 2406 tmp = 0; 2407 if (DC_IS_INTEL(sc)) { 2408 dc_apply_fixup(sc, IFM_AUTO); 2409 tmp = sc->dc_pmode; 2410 sc->dc_pmode = DC_PMODE_MII; 2411 } 2412 2413 /* 2414 * Setup General Purpose port mode and data so the tulip can talk 2415 * to the MII. This needs to be done before mii_attach so that 2416 * we can actually see them. 2417 */ 2418 if (DC_IS_XIRCOM(sc)) { 2419 CSR_WRITE_4(sc, DC_SIAGP, DC_SIAGP_WRITE_EN | DC_SIAGP_INT1_EN | 2420 DC_SIAGP_MD_GP2_OUTPUT | DC_SIAGP_MD_GP0_OUTPUT); 2421 DELAY(10); 2422 CSR_WRITE_4(sc, DC_SIAGP, DC_SIAGP_INT1_EN | 2423 DC_SIAGP_MD_GP2_OUTPUT | DC_SIAGP_MD_GP0_OUTPUT); 2424 DELAY(10); 2425 } 2426 2427 phy = MII_PHY_ANY; 2428 /* 2429 * Note: both the AL981 and AN983 have internal PHYs, however the 2430 * AL981 provides direct access to the PHY registers while the AN983 2431 * uses a serial MII interface. The AN983's MII interface is also 2432 * buggy in that you can read from any MII address (0 to 31), but 2433 * only address 1 behaves normally. To deal with both cases, we 2434 * pretend that the PHY is at MII address 1. 2435 */ 2436 if (DC_IS_ADMTEK(sc)) 2437 phy = DC_ADMTEK_PHYADDR; 2438 2439 /* 2440 * Note: the ukphy probes of the RS7112 report a PHY at MII address 2441 * 0 (possibly HomePNA?) and 1 (ethernet) so we only respond to the 2442 * correct one. 2443 */ 2444 if (DC_IS_CONEXANT(sc)) 2445 phy = DC_CONEXANT_PHYADDR; 2446 2447 error = mii_attach(dev, &sc->dc_miibus, ifp, dc_ifmedia_upd, 2448 dc_ifmedia_sts, BMSR_DEFCAPMASK, phy, MII_OFFSET_ANY, 0); 2449 2450 if (error && DC_IS_INTEL(sc)) { 2451 sc->dc_pmode = tmp; 2452 if (sc->dc_pmode != DC_PMODE_SIA) 2453 sc->dc_pmode = DC_PMODE_SYM; 2454 sc->dc_flags |= DC_21143_NWAY; 2455 /* 2456 * For non-MII cards, we need to have the 21143 2457 * drive the LEDs. Except there are some systems 2458 * like the NEC VersaPro NoteBook PC which have no 2459 * LEDs, and twiddling these bits has adverse effects 2460 * on them. (I.e. you suddenly can't get a link.) 2461 */ 2462 if (!(pci_get_subvendor(dev) == 0x1033 && 2463 pci_get_subdevice(dev) == 0x8028)) 2464 sc->dc_flags |= DC_TULIP_LEDS; 2465 error = mii_attach(dev, &sc->dc_miibus, ifp, dc_ifmedia_upd, 2466 dc_ifmedia_sts, BMSR_DEFCAPMASK, MII_PHY_ANY, 2467 MII_OFFSET_ANY, 0); 2468 } 2469 2470 if (error) { 2471 device_printf(dev, "attaching PHYs failed\n"); 2472 goto fail; 2473 } 2474 2475 if (DC_IS_ADMTEK(sc)) { 2476 /* 2477 * Set automatic TX underrun recovery for the ADMtek chips 2478 */ 2479 DC_SETBIT(sc, DC_AL_CR, DC_AL_CR_ATUR); 2480 } 2481 2482 /* 2483 * Tell the upper layer(s) we support long frames. 2484 */ 2485 if_setifheaderlen(ifp, sizeof(struct ether_vlan_header)); 2486 if_setcapabilitiesbit(ifp, IFCAP_VLAN_MTU, 0); 2487 if_setcapenable(ifp, if_getcapabilities(ifp)); 2488 #ifdef DEVICE_POLLING 2489 if_setcapabilitiesbit(ifp, IFCAP_POLLING, 0); 2490 #endif 2491 2492 callout_init_mtx(&sc->dc_stat_ch, &sc->dc_mtx, 0); 2493 callout_init_mtx(&sc->dc_wdog_ch, &sc->dc_mtx, 0); 2494 2495 /* 2496 * Call MI attach routine. 2497 */ 2498 ether_ifattach(ifp, (caddr_t)eaddr); 2499 2500 /* Hook interrupt last to avoid having to lock softc */ 2501 error = bus_setup_intr(dev, sc->dc_irq, INTR_TYPE_NET | INTR_MPSAFE, 2502 NULL, dc_intr, sc, &sc->dc_intrhand); 2503 2504 if (error) { 2505 device_printf(dev, "couldn't set up irq\n"); 2506 ether_ifdetach(ifp); 2507 goto fail; 2508 } 2509 2510 fail: 2511 if (error) 2512 dc_detach(dev); 2513 return (error); 2514 } 2515 2516 /* 2517 * Shutdown hardware and free up resources. This can be called any 2518 * time after the mutex has been initialized. It is called in both 2519 * the error case in attach and the normal detach case so it needs 2520 * to be careful about only freeing resources that have actually been 2521 * allocated. 2522 */ 2523 static int 2524 dc_detach(device_t dev) 2525 { 2526 struct dc_softc *sc; 2527 if_t ifp; 2528 struct dc_mediainfo *m; 2529 2530 sc = device_get_softc(dev); 2531 KASSERT(mtx_initialized(&sc->dc_mtx), ("dc mutex not initialized")); 2532 2533 ifp = sc->dc_ifp; 2534 2535 #ifdef DEVICE_POLLING 2536 if (ifp != NULL && if_getcapenable(ifp) & IFCAP_POLLING) 2537 ether_poll_deregister(ifp); 2538 #endif 2539 2540 /* These should only be active if attach succeeded */ 2541 if (device_is_attached(dev)) { 2542 DC_LOCK(sc); 2543 dc_stop(sc); 2544 DC_UNLOCK(sc); 2545 callout_drain(&sc->dc_stat_ch); 2546 callout_drain(&sc->dc_wdog_ch); 2547 ether_ifdetach(ifp); 2548 } 2549 if (sc->dc_miibus) 2550 device_delete_child(dev, sc->dc_miibus); 2551 bus_generic_detach(dev); 2552 2553 if (sc->dc_intrhand) 2554 bus_teardown_intr(dev, sc->dc_irq, sc->dc_intrhand); 2555 if (sc->dc_irq) 2556 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->dc_irq); 2557 if (sc->dc_res) 2558 bus_release_resource(dev, DC_RES, DC_RID, sc->dc_res); 2559 2560 if (ifp != NULL) 2561 if_free(ifp); 2562 2563 dc_dma_free(sc); 2564 2565 free(sc->dc_pnic_rx_buf, M_DEVBUF); 2566 2567 while (sc->dc_mi != NULL) { 2568 m = sc->dc_mi->dc_next; 2569 free(sc->dc_mi, M_DEVBUF); 2570 sc->dc_mi = m; 2571 } 2572 free(sc->dc_srom, M_DEVBUF); 2573 2574 mtx_destroy(&sc->dc_mtx); 2575 2576 return (0); 2577 } 2578 2579 /* 2580 * Initialize the transmit descriptors. 2581 */ 2582 static int 2583 dc_list_tx_init(struct dc_softc *sc) 2584 { 2585 struct dc_chain_data *cd; 2586 struct dc_list_data *ld; 2587 int i, nexti; 2588 2589 cd = &sc->dc_cdata; 2590 ld = &sc->dc_ldata; 2591 for (i = 0; i < DC_TX_LIST_CNT; i++) { 2592 if (i == DC_TX_LIST_CNT - 1) 2593 nexti = 0; 2594 else 2595 nexti = i + 1; 2596 ld->dc_tx_list[i].dc_status = 0; 2597 ld->dc_tx_list[i].dc_ctl = 0; 2598 ld->dc_tx_list[i].dc_data = 0; 2599 ld->dc_tx_list[i].dc_next = htole32(DC_TXDESC(sc, nexti)); 2600 cd->dc_tx_chain[i] = NULL; 2601 } 2602 2603 cd->dc_tx_prod = cd->dc_tx_cons = cd->dc_tx_cnt = 0; 2604 cd->dc_tx_pkts = 0; 2605 bus_dmamap_sync(sc->dc_tx_ltag, sc->dc_tx_lmap, 2606 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2607 return (0); 2608 } 2609 2610 /* 2611 * Initialize the RX descriptors and allocate mbufs for them. Note that 2612 * we arrange the descriptors in a closed ring, so that the last descriptor 2613 * points back to the first. 2614 */ 2615 static int 2616 dc_list_rx_init(struct dc_softc *sc) 2617 { 2618 struct dc_chain_data *cd; 2619 struct dc_list_data *ld; 2620 int i, nexti; 2621 2622 cd = &sc->dc_cdata; 2623 ld = &sc->dc_ldata; 2624 2625 for (i = 0; i < DC_RX_LIST_CNT; i++) { 2626 if (dc_newbuf(sc, i) != 0) 2627 return (ENOBUFS); 2628 if (i == DC_RX_LIST_CNT - 1) 2629 nexti = 0; 2630 else 2631 nexti = i + 1; 2632 ld->dc_rx_list[i].dc_next = htole32(DC_RXDESC(sc, nexti)); 2633 } 2634 2635 cd->dc_rx_prod = 0; 2636 bus_dmamap_sync(sc->dc_rx_ltag, sc->dc_rx_lmap, 2637 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2638 return (0); 2639 } 2640 2641 /* 2642 * Initialize an RX descriptor and attach an MBUF cluster. 2643 */ 2644 static int 2645 dc_newbuf(struct dc_softc *sc, int i) 2646 { 2647 struct mbuf *m; 2648 bus_dmamap_t map; 2649 bus_dma_segment_t segs[1]; 2650 int error, nseg; 2651 2652 m = m_getcl(M_NOWAIT, MT_DATA, M_PKTHDR); 2653 if (m == NULL) 2654 return (ENOBUFS); 2655 m->m_len = m->m_pkthdr.len = MCLBYTES; 2656 m_adj(m, sizeof(u_int64_t)); 2657 2658 /* 2659 * If this is a PNIC chip, zero the buffer. This is part 2660 * of the workaround for the receive bug in the 82c168 and 2661 * 82c169 chips. 2662 */ 2663 if (sc->dc_flags & DC_PNIC_RX_BUG_WAR) 2664 bzero(mtod(m, char *), m->m_len); 2665 2666 error = bus_dmamap_load_mbuf_sg(sc->dc_rx_mtag, sc->dc_sparemap, 2667 m, segs, &nseg, 0); 2668 if (error) { 2669 m_freem(m); 2670 return (error); 2671 } 2672 KASSERT(nseg == 1, ("%s: wrong number of segments (%d)", __func__, 2673 nseg)); 2674 if (sc->dc_cdata.dc_rx_chain[i] != NULL) 2675 bus_dmamap_unload(sc->dc_rx_mtag, sc->dc_cdata.dc_rx_map[i]); 2676 2677 map = sc->dc_cdata.dc_rx_map[i]; 2678 sc->dc_cdata.dc_rx_map[i] = sc->dc_sparemap; 2679 sc->dc_sparemap = map; 2680 sc->dc_cdata.dc_rx_chain[i] = m; 2681 bus_dmamap_sync(sc->dc_rx_mtag, sc->dc_cdata.dc_rx_map[i], 2682 BUS_DMASYNC_PREREAD); 2683 2684 sc->dc_ldata.dc_rx_list[i].dc_ctl = htole32(DC_RXCTL_RLINK | DC_RXLEN); 2685 sc->dc_ldata.dc_rx_list[i].dc_data = 2686 htole32(DC_ADDR_LO(segs[0].ds_addr)); 2687 sc->dc_ldata.dc_rx_list[i].dc_status = htole32(DC_RXSTAT_OWN); 2688 bus_dmamap_sync(sc->dc_rx_ltag, sc->dc_rx_lmap, 2689 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2690 return (0); 2691 } 2692 2693 /* 2694 * Grrrrr. 2695 * The PNIC chip has a terrible bug in it that manifests itself during 2696 * periods of heavy activity. The exact mode of failure if difficult to 2697 * pinpoint: sometimes it only happens in promiscuous mode, sometimes it 2698 * will happen on slow machines. The bug is that sometimes instead of 2699 * uploading one complete frame during reception, it uploads what looks 2700 * like the entire contents of its FIFO memory. The frame we want is at 2701 * the end of the whole mess, but we never know exactly how much data has 2702 * been uploaded, so salvaging the frame is hard. 2703 * 2704 * There is only one way to do it reliably, and it's disgusting. 2705 * Here's what we know: 2706 * 2707 * - We know there will always be somewhere between one and three extra 2708 * descriptors uploaded. 2709 * 2710 * - We know the desired received frame will always be at the end of the 2711 * total data upload. 2712 * 2713 * - We know the size of the desired received frame because it will be 2714 * provided in the length field of the status word in the last descriptor. 2715 * 2716 * Here's what we do: 2717 * 2718 * - When we allocate buffers for the receive ring, we bzero() them. 2719 * This means that we know that the buffer contents should be all 2720 * zeros, except for data uploaded by the chip. 2721 * 2722 * - We also force the PNIC chip to upload frames that include the 2723 * ethernet CRC at the end. 2724 * 2725 * - We gather all of the bogus frame data into a single buffer. 2726 * 2727 * - We then position a pointer at the end of this buffer and scan 2728 * backwards until we encounter the first non-zero byte of data. 2729 * This is the end of the received frame. We know we will encounter 2730 * some data at the end of the frame because the CRC will always be 2731 * there, so even if the sender transmits a packet of all zeros, 2732 * we won't be fooled. 2733 * 2734 * - We know the size of the actual received frame, so we subtract 2735 * that value from the current pointer location. This brings us 2736 * to the start of the actual received packet. 2737 * 2738 * - We copy this into an mbuf and pass it on, along with the actual 2739 * frame length. 2740 * 2741 * The performance hit is tremendous, but it beats dropping frames all 2742 * the time. 2743 */ 2744 2745 #define DC_WHOLEFRAME (DC_RXSTAT_FIRSTFRAG | DC_RXSTAT_LASTFRAG) 2746 static void 2747 dc_pnic_rx_bug_war(struct dc_softc *sc, int idx) 2748 { 2749 struct dc_desc *cur_rx; 2750 struct dc_desc *c = NULL; 2751 struct mbuf *m = NULL; 2752 unsigned char *ptr; 2753 int i, total_len; 2754 uint32_t rxstat = 0; 2755 2756 i = sc->dc_pnic_rx_bug_save; 2757 cur_rx = &sc->dc_ldata.dc_rx_list[idx]; 2758 ptr = sc->dc_pnic_rx_buf; 2759 bzero(ptr, DC_RXLEN * 5); 2760 2761 /* Copy all the bytes from the bogus buffers. */ 2762 while (1) { 2763 c = &sc->dc_ldata.dc_rx_list[i]; 2764 rxstat = le32toh(c->dc_status); 2765 m = sc->dc_cdata.dc_rx_chain[i]; 2766 bcopy(mtod(m, char *), ptr, DC_RXLEN); 2767 ptr += DC_RXLEN; 2768 /* If this is the last buffer, break out. */ 2769 if (i == idx || rxstat & DC_RXSTAT_LASTFRAG) 2770 break; 2771 dc_discard_rxbuf(sc, i); 2772 DC_INC(i, DC_RX_LIST_CNT); 2773 } 2774 2775 /* Find the length of the actual receive frame. */ 2776 total_len = DC_RXBYTES(rxstat); 2777 2778 /* Scan backwards until we hit a non-zero byte. */ 2779 while (*ptr == 0x00) 2780 ptr--; 2781 2782 /* Round off. */ 2783 if ((uintptr_t)(ptr) & 0x3) 2784 ptr -= 1; 2785 2786 /* Now find the start of the frame. */ 2787 ptr -= total_len; 2788 if (ptr < sc->dc_pnic_rx_buf) 2789 ptr = sc->dc_pnic_rx_buf; 2790 2791 /* 2792 * Now copy the salvaged frame to the last mbuf and fake up 2793 * the status word to make it look like a successful 2794 * frame reception. 2795 */ 2796 bcopy(ptr, mtod(m, char *), total_len); 2797 cur_rx->dc_status = htole32(rxstat | DC_RXSTAT_FIRSTFRAG); 2798 } 2799 2800 /* 2801 * This routine searches the RX ring for dirty descriptors in the 2802 * event that the rxeof routine falls out of sync with the chip's 2803 * current descriptor pointer. This may happen sometimes as a result 2804 * of a "no RX buffer available" condition that happens when the chip 2805 * consumes all of the RX buffers before the driver has a chance to 2806 * process the RX ring. This routine may need to be called more than 2807 * once to bring the driver back in sync with the chip, however we 2808 * should still be getting RX DONE interrupts to drive the search 2809 * for new packets in the RX ring, so we should catch up eventually. 2810 */ 2811 static int 2812 dc_rx_resync(struct dc_softc *sc) 2813 { 2814 struct dc_desc *cur_rx; 2815 int i, pos; 2816 2817 pos = sc->dc_cdata.dc_rx_prod; 2818 2819 for (i = 0; i < DC_RX_LIST_CNT; i++) { 2820 cur_rx = &sc->dc_ldata.dc_rx_list[pos]; 2821 if (!(le32toh(cur_rx->dc_status) & DC_RXSTAT_OWN)) 2822 break; 2823 DC_INC(pos, DC_RX_LIST_CNT); 2824 } 2825 2826 /* If the ring really is empty, then just return. */ 2827 if (i == DC_RX_LIST_CNT) 2828 return (0); 2829 2830 /* We've fallen behing the chip: catch it. */ 2831 sc->dc_cdata.dc_rx_prod = pos; 2832 2833 return (EAGAIN); 2834 } 2835 2836 static void 2837 dc_discard_rxbuf(struct dc_softc *sc, int i) 2838 { 2839 struct mbuf *m; 2840 2841 if (sc->dc_flags & DC_PNIC_RX_BUG_WAR) { 2842 m = sc->dc_cdata.dc_rx_chain[i]; 2843 bzero(mtod(m, char *), m->m_len); 2844 } 2845 2846 sc->dc_ldata.dc_rx_list[i].dc_ctl = htole32(DC_RXCTL_RLINK | DC_RXLEN); 2847 sc->dc_ldata.dc_rx_list[i].dc_status = htole32(DC_RXSTAT_OWN); 2848 bus_dmamap_sync(sc->dc_rx_ltag, sc->dc_rx_lmap, BUS_DMASYNC_PREREAD | 2849 BUS_DMASYNC_PREWRITE); 2850 } 2851 2852 /* 2853 * A frame has been uploaded: pass the resulting mbuf chain up to 2854 * the higher level protocols. 2855 */ 2856 static int 2857 dc_rxeof(struct dc_softc *sc) 2858 { 2859 struct mbuf *m; 2860 if_t ifp; 2861 struct dc_desc *cur_rx; 2862 int i, total_len, rx_npkts; 2863 uint32_t rxstat; 2864 2865 DC_LOCK_ASSERT(sc); 2866 2867 ifp = sc->dc_ifp; 2868 rx_npkts = 0; 2869 2870 bus_dmamap_sync(sc->dc_rx_ltag, sc->dc_rx_lmap, BUS_DMASYNC_POSTREAD | 2871 BUS_DMASYNC_POSTWRITE); 2872 for (i = sc->dc_cdata.dc_rx_prod; 2873 (if_getdrvflags(ifp) & IFF_DRV_RUNNING) != 0; 2874 DC_INC(i, DC_RX_LIST_CNT)) { 2875 #ifdef DEVICE_POLLING 2876 if (if_getcapenable(ifp) & IFCAP_POLLING) { 2877 if (sc->rxcycles <= 0) 2878 break; 2879 sc->rxcycles--; 2880 } 2881 #endif 2882 cur_rx = &sc->dc_ldata.dc_rx_list[i]; 2883 rxstat = le32toh(cur_rx->dc_status); 2884 if ((rxstat & DC_RXSTAT_OWN) != 0) 2885 break; 2886 m = sc->dc_cdata.dc_rx_chain[i]; 2887 bus_dmamap_sync(sc->dc_rx_mtag, sc->dc_cdata.dc_rx_map[i], 2888 BUS_DMASYNC_POSTREAD); 2889 total_len = DC_RXBYTES(rxstat); 2890 rx_npkts++; 2891 2892 if (sc->dc_flags & DC_PNIC_RX_BUG_WAR) { 2893 if ((rxstat & DC_WHOLEFRAME) != DC_WHOLEFRAME) { 2894 if (rxstat & DC_RXSTAT_FIRSTFRAG) 2895 sc->dc_pnic_rx_bug_save = i; 2896 if ((rxstat & DC_RXSTAT_LASTFRAG) == 0) 2897 continue; 2898 dc_pnic_rx_bug_war(sc, i); 2899 rxstat = le32toh(cur_rx->dc_status); 2900 total_len = DC_RXBYTES(rxstat); 2901 } 2902 } 2903 2904 /* 2905 * If an error occurs, update stats, clear the 2906 * status word and leave the mbuf cluster in place: 2907 * it should simply get re-used next time this descriptor 2908 * comes up in the ring. However, don't report long 2909 * frames as errors since they could be vlans. 2910 */ 2911 if ((rxstat & DC_RXSTAT_RXERR)) { 2912 if (!(rxstat & DC_RXSTAT_GIANT) || 2913 (rxstat & (DC_RXSTAT_CRCERR | DC_RXSTAT_DRIBBLE | 2914 DC_RXSTAT_MIIERE | DC_RXSTAT_COLLSEEN | 2915 DC_RXSTAT_RUNT | DC_RXSTAT_DE))) { 2916 if_inc_counter(ifp, IFCOUNTER_IERRORS, 1); 2917 if (rxstat & DC_RXSTAT_COLLSEEN) 2918 if_inc_counter(ifp, IFCOUNTER_COLLISIONS, 1); 2919 dc_discard_rxbuf(sc, i); 2920 if (rxstat & DC_RXSTAT_CRCERR) 2921 continue; 2922 else { 2923 if_setdrvflagbits(ifp, 0, IFF_DRV_RUNNING); 2924 dc_init_locked(sc); 2925 return (rx_npkts); 2926 } 2927 } 2928 } 2929 2930 /* No errors; receive the packet. */ 2931 total_len -= ETHER_CRC_LEN; 2932 #ifdef __NO_STRICT_ALIGNMENT 2933 /* 2934 * On architectures without alignment problems we try to 2935 * allocate a new buffer for the receive ring, and pass up 2936 * the one where the packet is already, saving the expensive 2937 * copy done in m_devget(). 2938 * If we are on an architecture with alignment problems, or 2939 * if the allocation fails, then use m_devget and leave the 2940 * existing buffer in the receive ring. 2941 */ 2942 if (dc_newbuf(sc, i) != 0) { 2943 dc_discard_rxbuf(sc, i); 2944 if_inc_counter(ifp, IFCOUNTER_IQDROPS, 1); 2945 continue; 2946 } 2947 m->m_pkthdr.rcvif = ifp; 2948 m->m_pkthdr.len = m->m_len = total_len; 2949 #else 2950 { 2951 struct mbuf *m0; 2952 2953 m0 = m_devget(mtod(m, char *), total_len, 2954 ETHER_ALIGN, ifp, NULL); 2955 dc_discard_rxbuf(sc, i); 2956 if (m0 == NULL) { 2957 if_inc_counter(ifp, IFCOUNTER_IQDROPS, 1); 2958 continue; 2959 } 2960 m = m0; 2961 } 2962 #endif 2963 2964 if_inc_counter(ifp, IFCOUNTER_IPACKETS, 1); 2965 DC_UNLOCK(sc); 2966 if_input(ifp, m); 2967 DC_LOCK(sc); 2968 } 2969 2970 sc->dc_cdata.dc_rx_prod = i; 2971 return (rx_npkts); 2972 } 2973 2974 /* 2975 * A frame was downloaded to the chip. It's safe for us to clean up 2976 * the list buffers. 2977 */ 2978 static void 2979 dc_txeof(struct dc_softc *sc) 2980 { 2981 struct dc_desc *cur_tx; 2982 if_t ifp; 2983 int idx, setup; 2984 uint32_t ctl, txstat; 2985 2986 if (sc->dc_cdata.dc_tx_cnt == 0) 2987 return; 2988 2989 ifp = sc->dc_ifp; 2990 2991 /* 2992 * Go through our tx list and free mbufs for those 2993 * frames that have been transmitted. 2994 */ 2995 bus_dmamap_sync(sc->dc_tx_ltag, sc->dc_tx_lmap, BUS_DMASYNC_POSTREAD | 2996 BUS_DMASYNC_POSTWRITE); 2997 setup = 0; 2998 for (idx = sc->dc_cdata.dc_tx_cons; idx != sc->dc_cdata.dc_tx_prod; 2999 DC_INC(idx, DC_TX_LIST_CNT), sc->dc_cdata.dc_tx_cnt--) { 3000 cur_tx = &sc->dc_ldata.dc_tx_list[idx]; 3001 txstat = le32toh(cur_tx->dc_status); 3002 ctl = le32toh(cur_tx->dc_ctl); 3003 3004 if (txstat & DC_TXSTAT_OWN) 3005 break; 3006 3007 if (sc->dc_cdata.dc_tx_chain[idx] == NULL) 3008 continue; 3009 3010 if (ctl & DC_TXCTL_SETUP) { 3011 cur_tx->dc_ctl = htole32(ctl & ~DC_TXCTL_SETUP); 3012 setup++; 3013 bus_dmamap_sync(sc->dc_stag, sc->dc_smap, 3014 BUS_DMASYNC_POSTWRITE); 3015 /* 3016 * Yes, the PNIC is so brain damaged 3017 * that it will sometimes generate a TX 3018 * underrun error while DMAing the RX 3019 * filter setup frame. If we detect this, 3020 * we have to send the setup frame again, 3021 * or else the filter won't be programmed 3022 * correctly. 3023 */ 3024 if (DC_IS_PNIC(sc)) { 3025 if (txstat & DC_TXSTAT_ERRSUM) 3026 dc_setfilt(sc); 3027 } 3028 sc->dc_cdata.dc_tx_chain[idx] = NULL; 3029 continue; 3030 } 3031 3032 if (DC_IS_XIRCOM(sc) || DC_IS_CONEXANT(sc)) { 3033 /* 3034 * XXX: Why does my Xircom taunt me so? 3035 * For some reason it likes setting the CARRLOST flag 3036 * even when the carrier is there. wtf?!? 3037 * Who knows, but Conexant chips have the 3038 * same problem. Maybe they took lessons 3039 * from Xircom. 3040 */ 3041 if (/*sc->dc_type == DC_TYPE_21143 &&*/ 3042 sc->dc_pmode == DC_PMODE_MII && 3043 ((txstat & 0xFFFF) & ~(DC_TXSTAT_ERRSUM | 3044 DC_TXSTAT_NOCARRIER))) 3045 txstat &= ~DC_TXSTAT_ERRSUM; 3046 } else { 3047 if (/*sc->dc_type == DC_TYPE_21143 &&*/ 3048 sc->dc_pmode == DC_PMODE_MII && 3049 ((txstat & 0xFFFF) & ~(DC_TXSTAT_ERRSUM | 3050 DC_TXSTAT_NOCARRIER | DC_TXSTAT_CARRLOST))) 3051 txstat &= ~DC_TXSTAT_ERRSUM; 3052 } 3053 3054 if (txstat & DC_TXSTAT_ERRSUM) { 3055 if_inc_counter(ifp, IFCOUNTER_OERRORS, 1); 3056 if (txstat & DC_TXSTAT_EXCESSCOLL) 3057 if_inc_counter(ifp, IFCOUNTER_COLLISIONS, 1); 3058 if (txstat & DC_TXSTAT_LATECOLL) 3059 if_inc_counter(ifp, IFCOUNTER_COLLISIONS, 1); 3060 if (!(txstat & DC_TXSTAT_UNDERRUN)) { 3061 if_setdrvflagbits(ifp, 0, IFF_DRV_RUNNING); 3062 dc_init_locked(sc); 3063 return; 3064 } 3065 } else 3066 if_inc_counter(ifp, IFCOUNTER_OPACKETS, 1); 3067 if_inc_counter(ifp, IFCOUNTER_COLLISIONS, (txstat & DC_TXSTAT_COLLCNT) >> 3); 3068 3069 bus_dmamap_sync(sc->dc_tx_mtag, sc->dc_cdata.dc_tx_map[idx], 3070 BUS_DMASYNC_POSTWRITE); 3071 bus_dmamap_unload(sc->dc_tx_mtag, sc->dc_cdata.dc_tx_map[idx]); 3072 m_freem(sc->dc_cdata.dc_tx_chain[idx]); 3073 sc->dc_cdata.dc_tx_chain[idx] = NULL; 3074 } 3075 sc->dc_cdata.dc_tx_cons = idx; 3076 3077 if (sc->dc_cdata.dc_tx_cnt <= DC_TX_LIST_CNT - DC_TX_LIST_RSVD) { 3078 if_setdrvflagbits(ifp, 0, IFF_DRV_OACTIVE); 3079 if (sc->dc_cdata.dc_tx_cnt == 0) 3080 sc->dc_wdog_timer = 0; 3081 } 3082 if (setup > 0) 3083 bus_dmamap_sync(sc->dc_tx_ltag, sc->dc_tx_lmap, 3084 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 3085 } 3086 3087 static void 3088 dc_tick(void *xsc) 3089 { 3090 struct dc_softc *sc; 3091 struct mii_data *mii; 3092 if_t ifp; 3093 uint32_t r; 3094 3095 sc = xsc; 3096 DC_LOCK_ASSERT(sc); 3097 ifp = sc->dc_ifp; 3098 mii = device_get_softc(sc->dc_miibus); 3099 3100 /* 3101 * Reclaim transmitted frames for controllers that do 3102 * not generate TX completion interrupt for every frame. 3103 */ 3104 if (sc->dc_flags & DC_TX_USE_TX_INTR) 3105 dc_txeof(sc); 3106 3107 if (sc->dc_flags & DC_REDUCED_MII_POLL) { 3108 if (sc->dc_flags & DC_21143_NWAY) { 3109 r = CSR_READ_4(sc, DC_10BTSTAT); 3110 if (IFM_SUBTYPE(mii->mii_media_active) == 3111 IFM_100_TX && (r & DC_TSTAT_LS100)) { 3112 sc->dc_link = 0; 3113 mii_mediachg(mii); 3114 } 3115 if (IFM_SUBTYPE(mii->mii_media_active) == 3116 IFM_10_T && (r & DC_TSTAT_LS10)) { 3117 sc->dc_link = 0; 3118 mii_mediachg(mii); 3119 } 3120 if (sc->dc_link == 0) 3121 mii_tick(mii); 3122 } else { 3123 /* 3124 * For NICs which never report DC_RXSTATE_WAIT, we 3125 * have to bite the bullet... 3126 */ 3127 if ((DC_HAS_BROKEN_RXSTATE(sc) || (CSR_READ_4(sc, 3128 DC_ISR) & DC_ISR_RX_STATE) == DC_RXSTATE_WAIT) && 3129 sc->dc_cdata.dc_tx_cnt == 0) 3130 mii_tick(mii); 3131 } 3132 } else 3133 mii_tick(mii); 3134 3135 /* 3136 * When the init routine completes, we expect to be able to send 3137 * packets right away, and in fact the network code will send a 3138 * gratuitous ARP the moment the init routine marks the interface 3139 * as running. However, even though the MAC may have been initialized, 3140 * there may be a delay of a few seconds before the PHY completes 3141 * autonegotiation and the link is brought up. Any transmissions 3142 * made during that delay will be lost. Dealing with this is tricky: 3143 * we can't just pause in the init routine while waiting for the 3144 * PHY to come ready since that would bring the whole system to 3145 * a screeching halt for several seconds. 3146 * 3147 * What we do here is prevent the TX start routine from sending 3148 * any packets until a link has been established. After the 3149 * interface has been initialized, the tick routine will poll 3150 * the state of the PHY until the IFM_ACTIVE flag is set. Until 3151 * that time, packets will stay in the send queue, and once the 3152 * link comes up, they will be flushed out to the wire. 3153 */ 3154 if (sc->dc_link != 0 && !if_sendq_empty(ifp)) 3155 dc_start_locked(ifp); 3156 3157 if (sc->dc_flags & DC_21143_NWAY && !sc->dc_link) 3158 callout_reset(&sc->dc_stat_ch, hz/10, dc_tick, sc); 3159 else 3160 callout_reset(&sc->dc_stat_ch, hz, dc_tick, sc); 3161 } 3162 3163 /* 3164 * A transmit underrun has occurred. Back off the transmit threshold, 3165 * or switch to store and forward mode if we have to. 3166 */ 3167 static void 3168 dc_tx_underrun(struct dc_softc *sc) 3169 { 3170 uint32_t netcfg, isr; 3171 int i, reinit; 3172 3173 reinit = 0; 3174 netcfg = CSR_READ_4(sc, DC_NETCFG); 3175 device_printf(sc->dc_dev, "TX underrun -- "); 3176 if ((sc->dc_flags & DC_TX_STORENFWD) == 0) { 3177 if (sc->dc_txthresh + DC_TXTHRESH_INC > DC_TXTHRESH_MAX) { 3178 printf("using store and forward mode\n"); 3179 netcfg |= DC_NETCFG_STORENFWD; 3180 } else { 3181 printf("increasing TX threshold\n"); 3182 sc->dc_txthresh += DC_TXTHRESH_INC; 3183 netcfg &= ~DC_NETCFG_TX_THRESH; 3184 netcfg |= sc->dc_txthresh; 3185 } 3186 3187 if (DC_IS_INTEL(sc)) { 3188 /* 3189 * The real 21143 requires that the transmitter be idle 3190 * in order to change the transmit threshold or store 3191 * and forward state. 3192 */ 3193 CSR_WRITE_4(sc, DC_NETCFG, netcfg & ~DC_NETCFG_TX_ON); 3194 3195 for (i = 0; i < DC_TIMEOUT; i++) { 3196 isr = CSR_READ_4(sc, DC_ISR); 3197 if (isr & DC_ISR_TX_IDLE) 3198 break; 3199 DELAY(10); 3200 } 3201 if (i == DC_TIMEOUT) { 3202 device_printf(sc->dc_dev, 3203 "%s: failed to force tx to idle state\n", 3204 __func__); 3205 reinit++; 3206 } 3207 } 3208 } else { 3209 printf("resetting\n"); 3210 reinit++; 3211 } 3212 3213 if (reinit == 0) { 3214 CSR_WRITE_4(sc, DC_NETCFG, netcfg); 3215 if (DC_IS_INTEL(sc)) 3216 CSR_WRITE_4(sc, DC_NETCFG, netcfg | DC_NETCFG_TX_ON); 3217 } else { 3218 if_setdrvflagbits(sc->dc_ifp, 0, IFF_DRV_RUNNING); 3219 dc_init_locked(sc); 3220 } 3221 } 3222 3223 #ifdef DEVICE_POLLING 3224 static poll_handler_t dc_poll; 3225 3226 static int 3227 dc_poll(if_t ifp, enum poll_cmd cmd, int count) 3228 { 3229 struct dc_softc *sc = if_getsoftc(ifp); 3230 int rx_npkts = 0; 3231 3232 DC_LOCK(sc); 3233 3234 if (!(if_getdrvflags(ifp) & IFF_DRV_RUNNING)) { 3235 DC_UNLOCK(sc); 3236 return (rx_npkts); 3237 } 3238 3239 sc->rxcycles = count; 3240 rx_npkts = dc_rxeof(sc); 3241 dc_txeof(sc); 3242 if (!if_sendq_empty(ifp) && 3243 !(if_getdrvflags(ifp) & IFF_DRV_OACTIVE)) 3244 dc_start_locked(ifp); 3245 3246 if (cmd == POLL_AND_CHECK_STATUS) { /* also check status register */ 3247 uint32_t status; 3248 3249 status = CSR_READ_4(sc, DC_ISR); 3250 status &= (DC_ISR_RX_WATDOGTIMEO | DC_ISR_RX_NOBUF | 3251 DC_ISR_TX_NOBUF | DC_ISR_TX_IDLE | DC_ISR_TX_UNDERRUN | 3252 DC_ISR_BUS_ERR); 3253 if (!status) { 3254 DC_UNLOCK(sc); 3255 return (rx_npkts); 3256 } 3257 /* ack what we have */ 3258 CSR_WRITE_4(sc, DC_ISR, status); 3259 3260 if (status & (DC_ISR_RX_WATDOGTIMEO | DC_ISR_RX_NOBUF)) { 3261 uint32_t r = CSR_READ_4(sc, DC_FRAMESDISCARDED); 3262 if_inc_counter(ifp, IFCOUNTER_IERRORS, (r & 0xffff) + ((r >> 17) & 0x7ff)); 3263 3264 if (dc_rx_resync(sc)) 3265 dc_rxeof(sc); 3266 } 3267 /* restart transmit unit if necessary */ 3268 if (status & DC_ISR_TX_IDLE && sc->dc_cdata.dc_tx_cnt) 3269 CSR_WRITE_4(sc, DC_TXSTART, 0xFFFFFFFF); 3270 3271 if (status & DC_ISR_TX_UNDERRUN) 3272 dc_tx_underrun(sc); 3273 3274 if (status & DC_ISR_BUS_ERR) { 3275 if_printf(ifp, "%s: bus error\n", __func__); 3276 if_setdrvflagbits(ifp, 0, IFF_DRV_RUNNING); 3277 dc_init_locked(sc); 3278 } 3279 } 3280 DC_UNLOCK(sc); 3281 return (rx_npkts); 3282 } 3283 #endif /* DEVICE_POLLING */ 3284 3285 static void 3286 dc_intr(void *arg) 3287 { 3288 struct dc_softc *sc; 3289 if_t ifp; 3290 uint32_t r, status; 3291 int n; 3292 3293 sc = arg; 3294 3295 if (sc->suspended) 3296 return; 3297 3298 DC_LOCK(sc); 3299 status = CSR_READ_4(sc, DC_ISR); 3300 if (status == 0xFFFFFFFF || (status & DC_INTRS) == 0) { 3301 DC_UNLOCK(sc); 3302 return; 3303 } 3304 ifp = sc->dc_ifp; 3305 #ifdef DEVICE_POLLING 3306 if (if_getcapenable(ifp) & IFCAP_POLLING) { 3307 DC_UNLOCK(sc); 3308 return; 3309 } 3310 #endif 3311 /* Disable interrupts. */ 3312 CSR_WRITE_4(sc, DC_IMR, 0x00000000); 3313 3314 for (n = 16; n > 0; n--) { 3315 if ((if_getdrvflags(ifp) & IFF_DRV_RUNNING) == 0) 3316 break; 3317 /* Ack interrupts. */ 3318 CSR_WRITE_4(sc, DC_ISR, status); 3319 3320 if (status & DC_ISR_RX_OK) { 3321 if (dc_rxeof(sc) == 0) { 3322 while (dc_rx_resync(sc)) 3323 dc_rxeof(sc); 3324 } 3325 } 3326 3327 if (status & (DC_ISR_TX_OK | DC_ISR_TX_NOBUF)) 3328 dc_txeof(sc); 3329 3330 if (status & DC_ISR_TX_IDLE) { 3331 dc_txeof(sc); 3332 if (sc->dc_cdata.dc_tx_cnt) { 3333 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_TX_ON); 3334 CSR_WRITE_4(sc, DC_TXSTART, 0xFFFFFFFF); 3335 } 3336 } 3337 3338 if (status & DC_ISR_TX_UNDERRUN) 3339 dc_tx_underrun(sc); 3340 3341 if ((status & DC_ISR_RX_WATDOGTIMEO) 3342 || (status & DC_ISR_RX_NOBUF)) { 3343 r = CSR_READ_4(sc, DC_FRAMESDISCARDED); 3344 if_inc_counter(ifp, IFCOUNTER_IERRORS, (r & 0xffff) + ((r >> 17) & 0x7ff)); 3345 if (dc_rxeof(sc) == 0) { 3346 while (dc_rx_resync(sc)) 3347 dc_rxeof(sc); 3348 } 3349 } 3350 3351 if (!if_sendq_empty(ifp)) 3352 dc_start_locked(ifp); 3353 3354 if (status & DC_ISR_BUS_ERR) { 3355 if_setdrvflagbits(ifp, 0, IFF_DRV_RUNNING); 3356 dc_init_locked(sc); 3357 DC_UNLOCK(sc); 3358 return; 3359 } 3360 status = CSR_READ_4(sc, DC_ISR); 3361 if (status == 0xFFFFFFFF || (status & DC_INTRS) == 0) 3362 break; 3363 } 3364 3365 /* Re-enable interrupts. */ 3366 if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) 3367 CSR_WRITE_4(sc, DC_IMR, DC_INTRS); 3368 3369 DC_UNLOCK(sc); 3370 } 3371 3372 /* 3373 * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data 3374 * pointers to the fragment pointers. 3375 */ 3376 static int 3377 dc_encap(struct dc_softc *sc, struct mbuf **m_head) 3378 { 3379 bus_dma_segment_t segs[DC_MAXFRAGS]; 3380 bus_dmamap_t map; 3381 struct dc_desc *f; 3382 struct mbuf *m; 3383 int cur, defragged, error, first, frag, i, idx, nseg; 3384 3385 m = NULL; 3386 defragged = 0; 3387 if (sc->dc_flags & DC_TX_COALESCE && 3388 ((*m_head)->m_next != NULL || sc->dc_flags & DC_TX_ALIGN)) { 3389 m = m_defrag(*m_head, M_NOWAIT); 3390 defragged = 1; 3391 } else { 3392 /* 3393 * Count the number of frags in this chain to see if we 3394 * need to m_collapse. Since the descriptor list is shared 3395 * by all packets, we'll m_collapse long chains so that they 3396 * do not use up the entire list, even if they would fit. 3397 */ 3398 i = 0; 3399 for (m = *m_head; m != NULL; m = m->m_next) 3400 i++; 3401 if (i > DC_TX_LIST_CNT / 4 || 3402 DC_TX_LIST_CNT - i + sc->dc_cdata.dc_tx_cnt <= 3403 DC_TX_LIST_RSVD) { 3404 m = m_collapse(*m_head, M_NOWAIT, DC_MAXFRAGS); 3405 defragged = 1; 3406 } 3407 } 3408 if (defragged != 0) { 3409 if (m == NULL) { 3410 m_freem(*m_head); 3411 *m_head = NULL; 3412 return (ENOBUFS); 3413 } 3414 *m_head = m; 3415 } 3416 3417 idx = sc->dc_cdata.dc_tx_prod; 3418 error = bus_dmamap_load_mbuf_sg(sc->dc_tx_mtag, 3419 sc->dc_cdata.dc_tx_map[idx], *m_head, segs, &nseg, 0); 3420 if (error == EFBIG) { 3421 if (defragged != 0 || (m = m_collapse(*m_head, M_NOWAIT, 3422 DC_MAXFRAGS)) == NULL) { 3423 m_freem(*m_head); 3424 *m_head = NULL; 3425 return (defragged != 0 ? error : ENOBUFS); 3426 } 3427 *m_head = m; 3428 error = bus_dmamap_load_mbuf_sg(sc->dc_tx_mtag, 3429 sc->dc_cdata.dc_tx_map[idx], *m_head, segs, &nseg, 0); 3430 if (error != 0) { 3431 m_freem(*m_head); 3432 *m_head = NULL; 3433 return (error); 3434 } 3435 } else if (error != 0) 3436 return (error); 3437 KASSERT(nseg <= DC_MAXFRAGS, 3438 ("%s: wrong number of segments (%d)", __func__, nseg)); 3439 if (nseg == 0) { 3440 m_freem(*m_head); 3441 *m_head = NULL; 3442 return (EIO); 3443 } 3444 3445 /* Check descriptor overruns. */ 3446 if (sc->dc_cdata.dc_tx_cnt + nseg > DC_TX_LIST_CNT - DC_TX_LIST_RSVD) { 3447 bus_dmamap_unload(sc->dc_tx_mtag, sc->dc_cdata.dc_tx_map[idx]); 3448 return (ENOBUFS); 3449 } 3450 bus_dmamap_sync(sc->dc_tx_mtag, sc->dc_cdata.dc_tx_map[idx], 3451 BUS_DMASYNC_PREWRITE); 3452 3453 first = cur = frag = sc->dc_cdata.dc_tx_prod; 3454 for (i = 0; i < nseg; i++) { 3455 if ((sc->dc_flags & DC_TX_ADMTEK_WAR) && 3456 (frag == (DC_TX_LIST_CNT - 1)) && 3457 (first != sc->dc_cdata.dc_tx_first)) { 3458 bus_dmamap_unload(sc->dc_tx_mtag, 3459 sc->dc_cdata.dc_tx_map[first]); 3460 m_freem(*m_head); 3461 *m_head = NULL; 3462 return (ENOBUFS); 3463 } 3464 3465 f = &sc->dc_ldata.dc_tx_list[frag]; 3466 f->dc_ctl = htole32(DC_TXCTL_TLINK | segs[i].ds_len); 3467 if (i == 0) { 3468 f->dc_status = 0; 3469 f->dc_ctl |= htole32(DC_TXCTL_FIRSTFRAG); 3470 } else 3471 f->dc_status = htole32(DC_TXSTAT_OWN); 3472 f->dc_data = htole32(DC_ADDR_LO(segs[i].ds_addr)); 3473 cur = frag; 3474 DC_INC(frag, DC_TX_LIST_CNT); 3475 } 3476 3477 sc->dc_cdata.dc_tx_prod = frag; 3478 sc->dc_cdata.dc_tx_cnt += nseg; 3479 sc->dc_cdata.dc_tx_chain[cur] = *m_head; 3480 sc->dc_ldata.dc_tx_list[cur].dc_ctl |= htole32(DC_TXCTL_LASTFRAG); 3481 if (sc->dc_flags & DC_TX_INTR_FIRSTFRAG) 3482 sc->dc_ldata.dc_tx_list[first].dc_ctl |= 3483 htole32(DC_TXCTL_FINT); 3484 if (sc->dc_flags & DC_TX_INTR_ALWAYS) 3485 sc->dc_ldata.dc_tx_list[cur].dc_ctl |= htole32(DC_TXCTL_FINT); 3486 if (sc->dc_flags & DC_TX_USE_TX_INTR && 3487 ++sc->dc_cdata.dc_tx_pkts >= 8) { 3488 sc->dc_cdata.dc_tx_pkts = 0; 3489 sc->dc_ldata.dc_tx_list[cur].dc_ctl |= htole32(DC_TXCTL_FINT); 3490 } 3491 sc->dc_ldata.dc_tx_list[first].dc_status = htole32(DC_TXSTAT_OWN); 3492 3493 bus_dmamap_sync(sc->dc_tx_ltag, sc->dc_tx_lmap, 3494 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 3495 3496 /* 3497 * Swap the last and the first dmamaps to ensure the map for 3498 * this transmission is placed at the last descriptor. 3499 */ 3500 map = sc->dc_cdata.dc_tx_map[cur]; 3501 sc->dc_cdata.dc_tx_map[cur] = sc->dc_cdata.dc_tx_map[first]; 3502 sc->dc_cdata.dc_tx_map[first] = map; 3503 3504 return (0); 3505 } 3506 3507 static void 3508 dc_start(if_t ifp) 3509 { 3510 struct dc_softc *sc; 3511 3512 sc = if_getsoftc(ifp); 3513 DC_LOCK(sc); 3514 dc_start_locked(ifp); 3515 DC_UNLOCK(sc); 3516 } 3517 3518 /* 3519 * Main transmit routine 3520 * To avoid having to do mbuf copies, we put pointers to the mbuf data 3521 * regions directly in the transmit lists. We also save a copy of the 3522 * pointers since the transmit list fragment pointers are physical 3523 * addresses. 3524 */ 3525 static void 3526 dc_start_locked(if_t ifp) 3527 { 3528 struct dc_softc *sc; 3529 struct mbuf *m_head; 3530 int queued; 3531 3532 sc = if_getsoftc(ifp); 3533 3534 DC_LOCK_ASSERT(sc); 3535 3536 if ((if_getdrvflags(ifp) & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) != 3537 IFF_DRV_RUNNING || sc->dc_link == 0) 3538 return; 3539 3540 sc->dc_cdata.dc_tx_first = sc->dc_cdata.dc_tx_prod; 3541 3542 for (queued = 0; !if_sendq_empty(ifp); ) { 3543 /* 3544 * If there's no way we can send any packets, return now. 3545 */ 3546 if (sc->dc_cdata.dc_tx_cnt > DC_TX_LIST_CNT - DC_TX_LIST_RSVD) { 3547 if_setdrvflagbits(ifp, IFF_DRV_OACTIVE, 0); 3548 break; 3549 } 3550 m_head = if_dequeue(ifp); 3551 if (m_head == NULL) 3552 break; 3553 3554 if (dc_encap(sc, &m_head)) { 3555 if (m_head == NULL) 3556 break; 3557 if_sendq_prepend(ifp, m_head); 3558 if_setdrvflagbits(ifp, IFF_DRV_OACTIVE, 0); 3559 break; 3560 } 3561 3562 queued++; 3563 /* 3564 * If there's a BPF listener, bounce a copy of this frame 3565 * to him. 3566 */ 3567 BPF_MTAP(ifp, m_head); 3568 } 3569 3570 if (queued > 0) { 3571 /* Transmit */ 3572 if (!(sc->dc_flags & DC_TX_POLL)) 3573 CSR_WRITE_4(sc, DC_TXSTART, 0xFFFFFFFF); 3574 3575 /* 3576 * Set a timeout in case the chip goes out to lunch. 3577 */ 3578 sc->dc_wdog_timer = 5; 3579 } 3580 } 3581 3582 static void 3583 dc_init(void *xsc) 3584 { 3585 struct dc_softc *sc = xsc; 3586 3587 DC_LOCK(sc); 3588 dc_init_locked(sc); 3589 DC_UNLOCK(sc); 3590 } 3591 3592 static void 3593 dc_init_locked(struct dc_softc *sc) 3594 { 3595 if_t ifp = sc->dc_ifp; 3596 struct mii_data *mii; 3597 struct ifmedia *ifm; 3598 3599 DC_LOCK_ASSERT(sc); 3600 3601 if ((if_getdrvflags(ifp) & IFF_DRV_RUNNING) != 0) 3602 return; 3603 3604 mii = device_get_softc(sc->dc_miibus); 3605 3606 /* 3607 * Cancel pending I/O and free all RX/TX buffers. 3608 */ 3609 dc_stop(sc); 3610 dc_reset(sc); 3611 if (DC_IS_INTEL(sc)) { 3612 ifm = &mii->mii_media; 3613 dc_apply_fixup(sc, ifm->ifm_media); 3614 } 3615 3616 /* 3617 * Set cache alignment and burst length. 3618 */ 3619 if (DC_IS_ASIX(sc) || DC_IS_DAVICOM(sc) || DC_IS_ULI(sc)) 3620 CSR_WRITE_4(sc, DC_BUSCTL, 0); 3621 else 3622 CSR_WRITE_4(sc, DC_BUSCTL, DC_BUSCTL_MRME | DC_BUSCTL_MRLE); 3623 /* 3624 * Evenly share the bus between receive and transmit process. 3625 */ 3626 if (DC_IS_INTEL(sc)) 3627 DC_SETBIT(sc, DC_BUSCTL, DC_BUSCTL_ARBITRATION); 3628 if (DC_IS_DAVICOM(sc) || DC_IS_INTEL(sc)) { 3629 DC_SETBIT(sc, DC_BUSCTL, DC_BURSTLEN_USECA); 3630 } else { 3631 DC_SETBIT(sc, DC_BUSCTL, DC_BURSTLEN_16LONG); 3632 } 3633 if (sc->dc_flags & DC_TX_POLL) 3634 DC_SETBIT(sc, DC_BUSCTL, DC_TXPOLL_1); 3635 switch(sc->dc_cachesize) { 3636 case 32: 3637 DC_SETBIT(sc, DC_BUSCTL, DC_CACHEALIGN_32LONG); 3638 break; 3639 case 16: 3640 DC_SETBIT(sc, DC_BUSCTL, DC_CACHEALIGN_16LONG); 3641 break; 3642 case 8: 3643 DC_SETBIT(sc, DC_BUSCTL, DC_CACHEALIGN_8LONG); 3644 break; 3645 case 0: 3646 default: 3647 DC_SETBIT(sc, DC_BUSCTL, DC_CACHEALIGN_NONE); 3648 break; 3649 } 3650 3651 if (sc->dc_flags & DC_TX_STORENFWD) 3652 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_STORENFWD); 3653 else { 3654 if (sc->dc_txthresh > DC_TXTHRESH_MAX) { 3655 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_STORENFWD); 3656 } else { 3657 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_STORENFWD); 3658 DC_SETBIT(sc, DC_NETCFG, sc->dc_txthresh); 3659 } 3660 } 3661 3662 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_NO_RXCRC); 3663 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_TX_BACKOFF); 3664 3665 if (DC_IS_MACRONIX(sc) || DC_IS_PNICII(sc)) { 3666 /* 3667 * The app notes for the 98713 and 98715A say that 3668 * in order to have the chips operate properly, a magic 3669 * number must be written to CSR16. Macronix does not 3670 * document the meaning of these bits so there's no way 3671 * to know exactly what they do. The 98713 has a magic 3672 * number all its own; the rest all use a different one. 3673 */ 3674 DC_CLRBIT(sc, DC_MX_MAGICPACKET, 0xFFFF0000); 3675 if (sc->dc_type == DC_TYPE_98713) 3676 DC_SETBIT(sc, DC_MX_MAGICPACKET, DC_MX_MAGIC_98713); 3677 else 3678 DC_SETBIT(sc, DC_MX_MAGICPACKET, DC_MX_MAGIC_98715); 3679 } 3680 3681 if (DC_IS_XIRCOM(sc)) { 3682 /* 3683 * setup General Purpose Port mode and data so the tulip 3684 * can talk to the MII. 3685 */ 3686 CSR_WRITE_4(sc, DC_SIAGP, DC_SIAGP_WRITE_EN | DC_SIAGP_INT1_EN | 3687 DC_SIAGP_MD_GP2_OUTPUT | DC_SIAGP_MD_GP0_OUTPUT); 3688 DELAY(10); 3689 CSR_WRITE_4(sc, DC_SIAGP, DC_SIAGP_INT1_EN | 3690 DC_SIAGP_MD_GP2_OUTPUT | DC_SIAGP_MD_GP0_OUTPUT); 3691 DELAY(10); 3692 } 3693 3694 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_TX_THRESH); 3695 DC_SETBIT(sc, DC_NETCFG, DC_TXTHRESH_MIN); 3696 3697 /* Init circular RX list. */ 3698 if (dc_list_rx_init(sc) == ENOBUFS) { 3699 device_printf(sc->dc_dev, 3700 "initialization failed: no memory for rx buffers\n"); 3701 dc_stop(sc); 3702 return; 3703 } 3704 3705 /* 3706 * Init TX descriptors. 3707 */ 3708 dc_list_tx_init(sc); 3709 3710 /* 3711 * Load the address of the RX list. 3712 */ 3713 CSR_WRITE_4(sc, DC_RXADDR, DC_RXDESC(sc, 0)); 3714 CSR_WRITE_4(sc, DC_TXADDR, DC_TXDESC(sc, 0)); 3715 3716 /* 3717 * Enable interrupts. 3718 */ 3719 #ifdef DEVICE_POLLING 3720 /* 3721 * ... but only if we are not polling, and make sure they are off in 3722 * the case of polling. Some cards (e.g. fxp) turn interrupts on 3723 * after a reset. 3724 */ 3725 if (if_getcapenable(ifp) & IFCAP_POLLING) 3726 CSR_WRITE_4(sc, DC_IMR, 0x00000000); 3727 else 3728 #endif 3729 CSR_WRITE_4(sc, DC_IMR, DC_INTRS); 3730 CSR_WRITE_4(sc, DC_ISR, 0xFFFFFFFF); 3731 3732 /* Initialize TX jabber and RX watchdog timer. */ 3733 if (DC_IS_ULI(sc)) 3734 CSR_WRITE_4(sc, DC_WATCHDOG, DC_WDOG_JABBERCLK | 3735 DC_WDOG_HOSTUNJAB); 3736 3737 /* Enable transmitter. */ 3738 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_TX_ON); 3739 3740 /* 3741 * If this is an Intel 21143 and we're not using the 3742 * MII port, program the LED control pins so we get 3743 * link and activity indications. 3744 */ 3745 if (sc->dc_flags & DC_TULIP_LEDS) { 3746 CSR_WRITE_4(sc, DC_WATCHDOG, 3747 DC_WDOG_CTLWREN | DC_WDOG_LINK | DC_WDOG_ACTIVITY); 3748 CSR_WRITE_4(sc, DC_WATCHDOG, 0); 3749 } 3750 3751 /* 3752 * Load the RX/multicast filter. We do this sort of late 3753 * because the filter programming scheme on the 21143 and 3754 * some clones requires DMAing a setup frame via the TX 3755 * engine, and we need the transmitter enabled for that. 3756 */ 3757 dc_setfilt(sc); 3758 3759 /* Enable receiver. */ 3760 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_ON); 3761 CSR_WRITE_4(sc, DC_RXSTART, 0xFFFFFFFF); 3762 3763 if_setdrvflagbits(ifp, IFF_DRV_RUNNING, 0); 3764 if_setdrvflagbits(ifp, 0, IFF_DRV_OACTIVE); 3765 3766 dc_ifmedia_upd_locked(sc); 3767 3768 /* Clear missed frames and overflow counter. */ 3769 CSR_READ_4(sc, DC_FRAMESDISCARDED); 3770 3771 /* Don't start the ticker if this is a homePNA link. */ 3772 if (IFM_SUBTYPE(mii->mii_media.ifm_media) == IFM_HPNA_1) 3773 sc->dc_link = 1; 3774 else { 3775 if (sc->dc_flags & DC_21143_NWAY) 3776 callout_reset(&sc->dc_stat_ch, hz/10, dc_tick, sc); 3777 else 3778 callout_reset(&sc->dc_stat_ch, hz, dc_tick, sc); 3779 } 3780 3781 sc->dc_wdog_timer = 0; 3782 callout_reset(&sc->dc_wdog_ch, hz, dc_watchdog, sc); 3783 } 3784 3785 /* 3786 * Set media options. 3787 */ 3788 static int 3789 dc_ifmedia_upd(if_t ifp) 3790 { 3791 struct dc_softc *sc; 3792 int error; 3793 3794 sc = if_getsoftc(ifp); 3795 DC_LOCK(sc); 3796 error = dc_ifmedia_upd_locked(sc); 3797 DC_UNLOCK(sc); 3798 return (error); 3799 } 3800 3801 static int 3802 dc_ifmedia_upd_locked(struct dc_softc *sc) 3803 { 3804 struct mii_data *mii; 3805 struct ifmedia *ifm; 3806 int error; 3807 3808 DC_LOCK_ASSERT(sc); 3809 3810 sc->dc_link = 0; 3811 mii = device_get_softc(sc->dc_miibus); 3812 error = mii_mediachg(mii); 3813 if (error == 0) { 3814 ifm = &mii->mii_media; 3815 if (DC_IS_INTEL(sc)) 3816 dc_setcfg(sc, ifm->ifm_media); 3817 else if (DC_IS_DAVICOM(sc) && 3818 IFM_SUBTYPE(ifm->ifm_media) == IFM_HPNA_1) 3819 dc_setcfg(sc, ifm->ifm_media); 3820 } 3821 3822 return (error); 3823 } 3824 3825 /* 3826 * Report current media status. 3827 */ 3828 static void 3829 dc_ifmedia_sts(if_t ifp, struct ifmediareq *ifmr) 3830 { 3831 struct dc_softc *sc; 3832 struct mii_data *mii; 3833 struct ifmedia *ifm; 3834 3835 sc = if_getsoftc(ifp); 3836 mii = device_get_softc(sc->dc_miibus); 3837 DC_LOCK(sc); 3838 mii_pollstat(mii); 3839 ifm = &mii->mii_media; 3840 if (DC_IS_DAVICOM(sc)) { 3841 if (IFM_SUBTYPE(ifm->ifm_media) == IFM_HPNA_1) { 3842 ifmr->ifm_active = ifm->ifm_media; 3843 ifmr->ifm_status = 0; 3844 DC_UNLOCK(sc); 3845 return; 3846 } 3847 } 3848 ifmr->ifm_active = mii->mii_media_active; 3849 ifmr->ifm_status = mii->mii_media_status; 3850 DC_UNLOCK(sc); 3851 } 3852 3853 static int 3854 dc_ioctl(if_t ifp, u_long command, caddr_t data) 3855 { 3856 struct dc_softc *sc = if_getsoftc(ifp); 3857 struct ifreq *ifr = (struct ifreq *)data; 3858 struct mii_data *mii; 3859 int error = 0; 3860 3861 switch (command) { 3862 case SIOCSIFFLAGS: 3863 DC_LOCK(sc); 3864 if (if_getflags(ifp) & IFF_UP) { 3865 int need_setfilt = (if_getflags(ifp) ^ sc->dc_if_flags) & 3866 (IFF_PROMISC | IFF_ALLMULTI); 3867 3868 if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) { 3869 if (need_setfilt) 3870 dc_setfilt(sc); 3871 } else { 3872 if_setdrvflagbits(ifp, 0, IFF_DRV_RUNNING); 3873 dc_init_locked(sc); 3874 } 3875 } else { 3876 if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) 3877 dc_stop(sc); 3878 } 3879 sc->dc_if_flags = if_getflags(ifp); 3880 DC_UNLOCK(sc); 3881 break; 3882 case SIOCADDMULTI: 3883 case SIOCDELMULTI: 3884 DC_LOCK(sc); 3885 if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) 3886 dc_setfilt(sc); 3887 DC_UNLOCK(sc); 3888 break; 3889 case SIOCGIFMEDIA: 3890 case SIOCSIFMEDIA: 3891 mii = device_get_softc(sc->dc_miibus); 3892 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 3893 break; 3894 case SIOCSIFCAP: 3895 #ifdef DEVICE_POLLING 3896 if (ifr->ifr_reqcap & IFCAP_POLLING && 3897 !(if_getcapenable(ifp) & IFCAP_POLLING)) { 3898 error = ether_poll_register(dc_poll, ifp); 3899 if (error) 3900 return(error); 3901 DC_LOCK(sc); 3902 /* Disable interrupts */ 3903 CSR_WRITE_4(sc, DC_IMR, 0x00000000); 3904 if_setcapenablebit(ifp, IFCAP_POLLING, 0); 3905 DC_UNLOCK(sc); 3906 return (error); 3907 } 3908 if (!(ifr->ifr_reqcap & IFCAP_POLLING) && 3909 if_getcapenable(ifp) & IFCAP_POLLING) { 3910 error = ether_poll_deregister(ifp); 3911 /* Enable interrupts. */ 3912 DC_LOCK(sc); 3913 CSR_WRITE_4(sc, DC_IMR, DC_INTRS); 3914 if_setcapenablebit(ifp, 0, IFCAP_POLLING); 3915 DC_UNLOCK(sc); 3916 return (error); 3917 } 3918 #endif /* DEVICE_POLLING */ 3919 break; 3920 default: 3921 error = ether_ioctl(ifp, command, data); 3922 break; 3923 } 3924 3925 return (error); 3926 } 3927 3928 static void 3929 dc_watchdog(void *xsc) 3930 { 3931 struct dc_softc *sc = xsc; 3932 if_t ifp; 3933 3934 DC_LOCK_ASSERT(sc); 3935 3936 if (sc->dc_wdog_timer == 0 || --sc->dc_wdog_timer != 0) { 3937 callout_reset(&sc->dc_wdog_ch, hz, dc_watchdog, sc); 3938 return; 3939 } 3940 3941 ifp = sc->dc_ifp; 3942 if_inc_counter(ifp, IFCOUNTER_OERRORS, 1); 3943 device_printf(sc->dc_dev, "watchdog timeout\n"); 3944 3945 if_setdrvflagbits(ifp, 0, IFF_DRV_RUNNING); 3946 dc_init_locked(sc); 3947 3948 if (!if_sendq_empty(ifp)) 3949 dc_start_locked(ifp); 3950 } 3951 3952 /* 3953 * Stop the adapter and free any mbufs allocated to the 3954 * RX and TX lists. 3955 */ 3956 static void 3957 dc_stop(struct dc_softc *sc) 3958 { 3959 if_t ifp; 3960 struct dc_list_data *ld; 3961 struct dc_chain_data *cd; 3962 int i; 3963 uint32_t ctl, netcfg; 3964 3965 DC_LOCK_ASSERT(sc); 3966 3967 ifp = sc->dc_ifp; 3968 ld = &sc->dc_ldata; 3969 cd = &sc->dc_cdata; 3970 3971 callout_stop(&sc->dc_stat_ch); 3972 callout_stop(&sc->dc_wdog_ch); 3973 sc->dc_wdog_timer = 0; 3974 sc->dc_link = 0; 3975 3976 if_setdrvflagbits(ifp, 0, (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)); 3977 3978 netcfg = CSR_READ_4(sc, DC_NETCFG); 3979 if (netcfg & (DC_NETCFG_RX_ON | DC_NETCFG_TX_ON)) 3980 CSR_WRITE_4(sc, DC_NETCFG, 3981 netcfg & ~(DC_NETCFG_RX_ON | DC_NETCFG_TX_ON)); 3982 CSR_WRITE_4(sc, DC_IMR, 0x00000000); 3983 /* Wait the completion of TX/RX SM. */ 3984 if (netcfg & (DC_NETCFG_RX_ON | DC_NETCFG_TX_ON)) 3985 dc_netcfg_wait(sc); 3986 3987 CSR_WRITE_4(sc, DC_TXADDR, 0x00000000); 3988 CSR_WRITE_4(sc, DC_RXADDR, 0x00000000); 3989 3990 /* 3991 * Free data in the RX lists. 3992 */ 3993 for (i = 0; i < DC_RX_LIST_CNT; i++) { 3994 if (cd->dc_rx_chain[i] != NULL) { 3995 bus_dmamap_sync(sc->dc_rx_mtag, 3996 cd->dc_rx_map[i], BUS_DMASYNC_POSTREAD); 3997 bus_dmamap_unload(sc->dc_rx_mtag, 3998 cd->dc_rx_map[i]); 3999 m_freem(cd->dc_rx_chain[i]); 4000 cd->dc_rx_chain[i] = NULL; 4001 } 4002 } 4003 bzero(ld->dc_rx_list, DC_RX_LIST_SZ); 4004 bus_dmamap_sync(sc->dc_rx_ltag, sc->dc_rx_lmap, 4005 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 4006 4007 /* 4008 * Free the TX list buffers. 4009 */ 4010 for (i = 0; i < DC_TX_LIST_CNT; i++) { 4011 if (cd->dc_tx_chain[i] != NULL) { 4012 ctl = le32toh(ld->dc_tx_list[i].dc_ctl); 4013 if (ctl & DC_TXCTL_SETUP) { 4014 bus_dmamap_sync(sc->dc_stag, sc->dc_smap, 4015 BUS_DMASYNC_POSTWRITE); 4016 } else { 4017 bus_dmamap_sync(sc->dc_tx_mtag, 4018 cd->dc_tx_map[i], BUS_DMASYNC_POSTWRITE); 4019 bus_dmamap_unload(sc->dc_tx_mtag, 4020 cd->dc_tx_map[i]); 4021 m_freem(cd->dc_tx_chain[i]); 4022 } 4023 cd->dc_tx_chain[i] = NULL; 4024 } 4025 } 4026 bzero(ld->dc_tx_list, DC_TX_LIST_SZ); 4027 bus_dmamap_sync(sc->dc_tx_ltag, sc->dc_tx_lmap, 4028 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 4029 } 4030 4031 /* 4032 * Device suspend routine. Stop the interface and save some PCI 4033 * settings in case the BIOS doesn't restore them properly on 4034 * resume. 4035 */ 4036 static int 4037 dc_suspend(device_t dev) 4038 { 4039 struct dc_softc *sc; 4040 4041 sc = device_get_softc(dev); 4042 DC_LOCK(sc); 4043 dc_stop(sc); 4044 sc->suspended = 1; 4045 DC_UNLOCK(sc); 4046 4047 return (0); 4048 } 4049 4050 /* 4051 * Device resume routine. Restore some PCI settings in case the BIOS 4052 * doesn't, re-enable busmastering, and restart the interface if 4053 * appropriate. 4054 */ 4055 static int 4056 dc_resume(device_t dev) 4057 { 4058 struct dc_softc *sc; 4059 if_t ifp; 4060 4061 sc = device_get_softc(dev); 4062 ifp = sc->dc_ifp; 4063 4064 /* reinitialize interface if necessary */ 4065 DC_LOCK(sc); 4066 if (if_getflags(ifp) & IFF_UP) 4067 dc_init_locked(sc); 4068 4069 sc->suspended = 0; 4070 DC_UNLOCK(sc); 4071 4072 return (0); 4073 } 4074 4075 /* 4076 * Stop all chip I/O so that the kernel's probe routines don't 4077 * get confused by errant DMAs when rebooting. 4078 */ 4079 static int 4080 dc_shutdown(device_t dev) 4081 { 4082 struct dc_softc *sc; 4083 4084 sc = device_get_softc(dev); 4085 4086 DC_LOCK(sc); 4087 dc_stop(sc); 4088 DC_UNLOCK(sc); 4089 4090 return (0); 4091 } 4092 4093 static int 4094 dc_check_multiport(struct dc_softc *sc) 4095 { 4096 struct dc_softc *dsc; 4097 devclass_t dc; 4098 device_t child; 4099 uint8_t *eaddr; 4100 int unit; 4101 4102 dc = devclass_find("dc"); 4103 for (unit = 0; unit < devclass_get_maxunit(dc); unit++) { 4104 child = devclass_get_device(dc, unit); 4105 if (child == NULL) 4106 continue; 4107 if (child == sc->dc_dev) 4108 continue; 4109 if (device_get_parent(child) != device_get_parent(sc->dc_dev)) 4110 continue; 4111 if (unit > device_get_unit(sc->dc_dev)) 4112 continue; 4113 if (device_is_attached(child) == 0) 4114 continue; 4115 dsc = device_get_softc(child); 4116 device_printf(sc->dc_dev, 4117 "Using station address of %s as base\n", 4118 device_get_nameunit(child)); 4119 bcopy(dsc->dc_eaddr, sc->dc_eaddr, ETHER_ADDR_LEN); 4120 eaddr = (uint8_t *)sc->dc_eaddr; 4121 eaddr[5]++; 4122 /* Prepare SROM to parse again. */ 4123 if (DC_IS_INTEL(sc) && dsc->dc_srom != NULL && 4124 sc->dc_romwidth != 0) { 4125 free(sc->dc_srom, M_DEVBUF); 4126 sc->dc_romwidth = dsc->dc_romwidth; 4127 sc->dc_srom = malloc(DC_ROM_SIZE(sc->dc_romwidth), 4128 M_DEVBUF, M_NOWAIT); 4129 if (sc->dc_srom == NULL) { 4130 device_printf(sc->dc_dev, 4131 "Could not allocate SROM buffer\n"); 4132 return (ENOMEM); 4133 } 4134 bcopy(dsc->dc_srom, sc->dc_srom, 4135 DC_ROM_SIZE(sc->dc_romwidth)); 4136 } 4137 return (0); 4138 } 4139 return (ENOENT); 4140 } 4141