1 /*- 2 * Copyright (c) 1997, 1998, 1999 3 * Bill Paul <wpaul@ee.columbia.edu>. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 3. All advertising materials mentioning features or use of this software 14 * must display the following acknowledgement: 15 * This product includes software developed by Bill Paul. 16 * 4. Neither the name of the author nor the names of any co-contributors 17 * may be used to endorse or promote products derived from this software 18 * without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30 * THE POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33 #include <sys/cdefs.h> 34 __FBSDID("$FreeBSD$"); 35 36 /* 37 * DEC "tulip" clone ethernet driver. Supports the DEC/Intel 21143 38 * series chips and several workalikes including the following: 39 * 40 * Macronix 98713/98715/98725/98727/98732 PMAC (www.macronix.com) 41 * Macronix/Lite-On 82c115 PNIC II (www.macronix.com) 42 * Lite-On 82c168/82c169 PNIC (www.litecom.com) 43 * ASIX Electronics AX88140A (www.asix.com.tw) 44 * ASIX Electronics AX88141 (www.asix.com.tw) 45 * ADMtek AL981 (www.admtek.com.tw) 46 * ADMtek AN983 (www.admtek.com.tw) 47 * ADMtek CardBus AN985 (www.admtek.com.tw) 48 * Netgear FA511 (www.netgear.com) Appears to be rebadged ADMTek CardBus AN985 49 * Davicom DM9100, DM9102, DM9102A (www.davicom8.com) 50 * Accton EN1217 (www.accton.com) 51 * Xircom X3201 (www.xircom.com) 52 * Abocom FE2500 53 * Conexant LANfinity (www.conexant.com) 54 * 3Com OfficeConnect 10/100B 3CSOHO100B (www.3com.com) 55 * 56 * Datasheets for the 21143 are available at developer.intel.com. 57 * Datasheets for the clone parts can be found at their respective sites. 58 * (Except for the PNIC; see www.freebsd.org/~wpaul/PNIC/pnic.ps.gz.) 59 * The PNIC II is essentially a Macronix 98715A chip; the only difference 60 * worth noting is that its multicast hash table is only 128 bits wide 61 * instead of 512. 62 * 63 * Written by Bill Paul <wpaul@ee.columbia.edu> 64 * Electrical Engineering Department 65 * Columbia University, New York City 66 */ 67 /* 68 * The Intel 21143 is the successor to the DEC 21140. It is basically 69 * the same as the 21140 but with a few new features. The 21143 supports 70 * three kinds of media attachments: 71 * 72 * o MII port, for 10Mbps and 100Mbps support and NWAY 73 * autonegotiation provided by an external PHY. 74 * o SYM port, for symbol mode 100Mbps support. 75 * o 10baseT port. 76 * o AUI/BNC port. 77 * 78 * The 100Mbps SYM port and 10baseT port can be used together in 79 * combination with the internal NWAY support to create a 10/100 80 * autosensing configuration. 81 * 82 * Note that not all tulip workalikes are handled in this driver: we only 83 * deal with those which are relatively well behaved. The Winbond is 84 * handled separately due to its different register offsets and the 85 * special handling needed for its various bugs. The PNIC is handled 86 * here, but I'm not thrilled about it. 87 * 88 * All of the workalike chips use some form of MII transceiver support 89 * with the exception of the Macronix chips, which also have a SYM port. 90 * The ASIX AX88140A is also documented to have a SYM port, but all 91 * the cards I've seen use an MII transceiver, probably because the 92 * AX88140A doesn't support internal NWAY. 93 */ 94 95 #ifdef HAVE_KERNEL_OPTION_HEADERS 96 #include "opt_device_polling.h" 97 #endif 98 99 #include <sys/param.h> 100 #include <sys/endian.h> 101 #include <sys/systm.h> 102 #include <sys/sockio.h> 103 #include <sys/mbuf.h> 104 #include <sys/malloc.h> 105 #include <sys/kernel.h> 106 #include <sys/module.h> 107 #include <sys/socket.h> 108 109 #include <net/if.h> 110 #include <net/if_arp.h> 111 #include <net/ethernet.h> 112 #include <net/if_dl.h> 113 #include <net/if_media.h> 114 #include <net/if_types.h> 115 #include <net/if_vlan_var.h> 116 117 #include <net/bpf.h> 118 119 #include <machine/bus.h> 120 #include <machine/resource.h> 121 #include <sys/bus.h> 122 #include <sys/rman.h> 123 124 #include <dev/mii/mii.h> 125 #include <dev/mii/miivar.h> 126 127 #include <dev/pci/pcireg.h> 128 #include <dev/pci/pcivar.h> 129 130 #define DC_USEIOSPACE 131 132 #include <dev/dc/if_dcreg.h> 133 134 #ifdef __sparc64__ 135 #include <dev/ofw/openfirm.h> 136 #include <machine/ofw_machdep.h> 137 #endif 138 139 MODULE_DEPEND(dc, pci, 1, 1, 1); 140 MODULE_DEPEND(dc, ether, 1, 1, 1); 141 MODULE_DEPEND(dc, miibus, 1, 1, 1); 142 143 /* 144 * "device miibus" is required in kernel config. See GENERIC if you get 145 * errors here. 146 */ 147 #include "miibus_if.h" 148 149 /* 150 * Various supported device vendors/types and their names. 151 */ 152 static const struct dc_type dc_devs[] = { 153 { DC_DEVID(DC_VENDORID_DEC, DC_DEVICEID_21143), 0, 154 "Intel 21143 10/100BaseTX" }, 155 { DC_DEVID(DC_VENDORID_DAVICOM, DC_DEVICEID_DM9009), 0, 156 "Davicom DM9009 10/100BaseTX" }, 157 { DC_DEVID(DC_VENDORID_DAVICOM, DC_DEVICEID_DM9100), 0, 158 "Davicom DM9100 10/100BaseTX" }, 159 { DC_DEVID(DC_VENDORID_DAVICOM, DC_DEVICEID_DM9102), DC_REVISION_DM9102A, 160 "Davicom DM9102A 10/100BaseTX" }, 161 { DC_DEVID(DC_VENDORID_DAVICOM, DC_DEVICEID_DM9102), 0, 162 "Davicom DM9102 10/100BaseTX" }, 163 { DC_DEVID(DC_VENDORID_ADMTEK, DC_DEVICEID_AL981), 0, 164 "ADMtek AL981 10/100BaseTX" }, 165 { DC_DEVID(DC_VENDORID_ADMTEK, DC_DEVICEID_AN983), 0, 166 "ADMtek AN983 10/100BaseTX" }, 167 { DC_DEVID(DC_VENDORID_ADMTEK, DC_DEVICEID_AN985), 0, 168 "ADMtek AN985 CardBus 10/100BaseTX or clone" }, 169 { DC_DEVID(DC_VENDORID_ADMTEK, DC_DEVICEID_ADM9511), 0, 170 "ADMtek ADM9511 10/100BaseTX" }, 171 { DC_DEVID(DC_VENDORID_ADMTEK, DC_DEVICEID_ADM9513), 0, 172 "ADMtek ADM9513 10/100BaseTX" }, 173 { DC_DEVID(DC_VENDORID_ASIX, DC_DEVICEID_AX88140A), DC_REVISION_88141, 174 "ASIX AX88141 10/100BaseTX" }, 175 { DC_DEVID(DC_VENDORID_ASIX, DC_DEVICEID_AX88140A), 0, 176 "ASIX AX88140A 10/100BaseTX" }, 177 { DC_DEVID(DC_VENDORID_MX, DC_DEVICEID_98713), DC_REVISION_98713A, 178 "Macronix 98713A 10/100BaseTX" }, 179 { DC_DEVID(DC_VENDORID_MX, DC_DEVICEID_98713), 0, 180 "Macronix 98713 10/100BaseTX" }, 181 { DC_DEVID(DC_VENDORID_CP, DC_DEVICEID_98713_CP), DC_REVISION_98713A, 182 "Compex RL100-TX 10/100BaseTX" }, 183 { DC_DEVID(DC_VENDORID_CP, DC_DEVICEID_98713_CP), 0, 184 "Compex RL100-TX 10/100BaseTX" }, 185 { DC_DEVID(DC_VENDORID_MX, DC_DEVICEID_987x5), DC_REVISION_98725, 186 "Macronix 98725 10/100BaseTX" }, 187 { DC_DEVID(DC_VENDORID_MX, DC_DEVICEID_987x5), DC_REVISION_98715AEC_C, 188 "Macronix 98715AEC-C 10/100BaseTX" }, 189 { DC_DEVID(DC_VENDORID_MX, DC_DEVICEID_987x5), 0, 190 "Macronix 98715/98715A 10/100BaseTX" }, 191 { DC_DEVID(DC_VENDORID_MX, DC_DEVICEID_98727), 0, 192 "Macronix 98727/98732 10/100BaseTX" }, 193 { DC_DEVID(DC_VENDORID_LO, DC_DEVICEID_82C115), 0, 194 "LC82C115 PNIC II 10/100BaseTX" }, 195 { DC_DEVID(DC_VENDORID_LO, DC_DEVICEID_82C168), DC_REVISION_82C169, 196 "82c169 PNIC 10/100BaseTX" }, 197 { DC_DEVID(DC_VENDORID_LO, DC_DEVICEID_82C168), 0, 198 "82c168 PNIC 10/100BaseTX" }, 199 { DC_DEVID(DC_VENDORID_ACCTON, DC_DEVICEID_EN1217), 0, 200 "Accton EN1217 10/100BaseTX" }, 201 { DC_DEVID(DC_VENDORID_ACCTON, DC_DEVICEID_EN2242), 0, 202 "Accton EN2242 MiniPCI 10/100BaseTX" }, 203 { DC_DEVID(DC_VENDORID_XIRCOM, DC_DEVICEID_X3201), 0, 204 "Xircom X3201 10/100BaseTX" }, 205 { DC_DEVID(DC_VENDORID_DLINK, DC_DEVICEID_DRP32TXD), 0, 206 "Neteasy DRP-32TXD Cardbus 10/100" }, 207 { DC_DEVID(DC_VENDORID_ABOCOM, DC_DEVICEID_FE2500), 0, 208 "Abocom FE2500 10/100BaseTX" }, 209 { DC_DEVID(DC_VENDORID_ABOCOM, DC_DEVICEID_FE2500MX), 0, 210 "Abocom FE2500MX 10/100BaseTX" }, 211 { DC_DEVID(DC_VENDORID_CONEXANT, DC_DEVICEID_RS7112), 0, 212 "Conexant LANfinity MiniPCI 10/100BaseTX" }, 213 { DC_DEVID(DC_VENDORID_HAWKING, DC_DEVICEID_HAWKING_PN672TX), 0, 214 "Hawking CB102 CardBus 10/100" }, 215 { DC_DEVID(DC_VENDORID_PLANEX, DC_DEVICEID_FNW3602T), 0, 216 "PlaneX FNW-3602-T CardBus 10/100" }, 217 { DC_DEVID(DC_VENDORID_3COM, DC_DEVICEID_3CSOHOB), 0, 218 "3Com OfficeConnect 10/100B" }, 219 { DC_DEVID(DC_VENDORID_MICROSOFT, DC_DEVICEID_MSMN120), 0, 220 "Microsoft MN-120 CardBus 10/100" }, 221 { DC_DEVID(DC_VENDORID_MICROSOFT, DC_DEVICEID_MSMN130), 0, 222 "Microsoft MN-130 10/100" }, 223 { DC_DEVID(DC_VENDORID_LINKSYS, DC_DEVICEID_PCMPC200_AB08), 0, 224 "Linksys PCMPC200 CardBus 10/100" }, 225 { DC_DEVID(DC_VENDORID_LINKSYS, DC_DEVICEID_PCMPC200_AB09), 0, 226 "Linksys PCMPC200 CardBus 10/100" }, 227 { 0, 0, NULL } 228 }; 229 230 static int dc_probe(device_t); 231 static int dc_attach(device_t); 232 static int dc_detach(device_t); 233 static int dc_suspend(device_t); 234 static int dc_resume(device_t); 235 static const struct dc_type *dc_devtype(device_t); 236 static void dc_discard_rxbuf(struct dc_softc *, int); 237 static int dc_newbuf(struct dc_softc *, int); 238 static int dc_encap(struct dc_softc *, struct mbuf **); 239 static void dc_pnic_rx_bug_war(struct dc_softc *, int); 240 static int dc_rx_resync(struct dc_softc *); 241 static int dc_rxeof(struct dc_softc *); 242 static void dc_txeof(struct dc_softc *); 243 static void dc_tick(void *); 244 static void dc_tx_underrun(struct dc_softc *); 245 static void dc_intr(void *); 246 static void dc_start(struct ifnet *); 247 static void dc_start_locked(struct ifnet *); 248 static int dc_ioctl(struct ifnet *, u_long, caddr_t); 249 static void dc_init(void *); 250 static void dc_init_locked(struct dc_softc *); 251 static void dc_stop(struct dc_softc *); 252 static void dc_watchdog(void *); 253 static int dc_shutdown(device_t); 254 static int dc_ifmedia_upd(struct ifnet *); 255 static void dc_ifmedia_sts(struct ifnet *, struct ifmediareq *); 256 257 static int dc_dma_alloc(struct dc_softc *); 258 static void dc_dma_free(struct dc_softc *); 259 static void dc_dma_map_addr(void *, bus_dma_segment_t *, int, int); 260 261 static void dc_delay(struct dc_softc *); 262 static void dc_eeprom_idle(struct dc_softc *); 263 static void dc_eeprom_putbyte(struct dc_softc *, int); 264 static void dc_eeprom_getword(struct dc_softc *, int, uint16_t *); 265 static void dc_eeprom_getword_pnic(struct dc_softc *, int, uint16_t *); 266 static void dc_eeprom_getword_xircom(struct dc_softc *, int, uint16_t *); 267 static void dc_eeprom_width(struct dc_softc *); 268 static void dc_read_eeprom(struct dc_softc *, caddr_t, int, int, int); 269 270 static void dc_mii_writebit(struct dc_softc *, int); 271 static int dc_mii_readbit(struct dc_softc *); 272 static void dc_mii_sync(struct dc_softc *); 273 static void dc_mii_send(struct dc_softc *, uint32_t, int); 274 static int dc_mii_readreg(struct dc_softc *, struct dc_mii_frame *); 275 static int dc_mii_writereg(struct dc_softc *, struct dc_mii_frame *); 276 static int dc_miibus_readreg(device_t, int, int); 277 static int dc_miibus_writereg(device_t, int, int, int); 278 static void dc_miibus_statchg(device_t); 279 static void dc_miibus_mediainit(device_t); 280 281 static void dc_setcfg(struct dc_softc *, int); 282 static void dc_netcfg_wait(struct dc_softc *); 283 static uint32_t dc_mchash_le(struct dc_softc *, const uint8_t *); 284 static uint32_t dc_mchash_be(const uint8_t *); 285 static void dc_setfilt_21143(struct dc_softc *); 286 static void dc_setfilt_asix(struct dc_softc *); 287 static void dc_setfilt_admtek(struct dc_softc *); 288 static void dc_setfilt_xircom(struct dc_softc *); 289 290 static void dc_setfilt(struct dc_softc *); 291 292 static void dc_reset(struct dc_softc *); 293 static int dc_list_rx_init(struct dc_softc *); 294 static int dc_list_tx_init(struct dc_softc *); 295 296 static int dc_read_srom(struct dc_softc *, int); 297 static int dc_parse_21143_srom(struct dc_softc *); 298 static int dc_decode_leaf_sia(struct dc_softc *, struct dc_eblock_sia *); 299 static int dc_decode_leaf_mii(struct dc_softc *, struct dc_eblock_mii *); 300 static int dc_decode_leaf_sym(struct dc_softc *, struct dc_eblock_sym *); 301 static void dc_apply_fixup(struct dc_softc *, int); 302 static int dc_check_multiport(struct dc_softc *); 303 304 #ifdef DC_USEIOSPACE 305 #define DC_RES SYS_RES_IOPORT 306 #define DC_RID DC_PCI_CFBIO 307 #else 308 #define DC_RES SYS_RES_MEMORY 309 #define DC_RID DC_PCI_CFBMA 310 #endif 311 312 static device_method_t dc_methods[] = { 313 /* Device interface */ 314 DEVMETHOD(device_probe, dc_probe), 315 DEVMETHOD(device_attach, dc_attach), 316 DEVMETHOD(device_detach, dc_detach), 317 DEVMETHOD(device_suspend, dc_suspend), 318 DEVMETHOD(device_resume, dc_resume), 319 DEVMETHOD(device_shutdown, dc_shutdown), 320 321 /* bus interface */ 322 DEVMETHOD(bus_print_child, bus_generic_print_child), 323 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 324 325 /* MII interface */ 326 DEVMETHOD(miibus_readreg, dc_miibus_readreg), 327 DEVMETHOD(miibus_writereg, dc_miibus_writereg), 328 DEVMETHOD(miibus_statchg, dc_miibus_statchg), 329 DEVMETHOD(miibus_mediainit, dc_miibus_mediainit), 330 331 { 0, 0 } 332 }; 333 334 static driver_t dc_driver = { 335 "dc", 336 dc_methods, 337 sizeof(struct dc_softc) 338 }; 339 340 static devclass_t dc_devclass; 341 342 DRIVER_MODULE(dc, pci, dc_driver, dc_devclass, 0, 0); 343 DRIVER_MODULE(miibus, dc, miibus_driver, miibus_devclass, 0, 0); 344 345 #define DC_SETBIT(sc, reg, x) \ 346 CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) | (x)) 347 348 #define DC_CLRBIT(sc, reg, x) \ 349 CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) & ~(x)) 350 351 #define SIO_SET(x) DC_SETBIT(sc, DC_SIO, (x)) 352 #define SIO_CLR(x) DC_CLRBIT(sc, DC_SIO, (x)) 353 354 static void 355 dc_delay(struct dc_softc *sc) 356 { 357 int idx; 358 359 for (idx = (300 / 33) + 1; idx > 0; idx--) 360 CSR_READ_4(sc, DC_BUSCTL); 361 } 362 363 static void 364 dc_eeprom_width(struct dc_softc *sc) 365 { 366 int i; 367 368 /* Force EEPROM to idle state. */ 369 dc_eeprom_idle(sc); 370 371 /* Enter EEPROM access mode. */ 372 CSR_WRITE_4(sc, DC_SIO, DC_SIO_EESEL); 373 dc_delay(sc); 374 DC_SETBIT(sc, DC_SIO, DC_SIO_ROMCTL_READ); 375 dc_delay(sc); 376 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); 377 dc_delay(sc); 378 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CS); 379 dc_delay(sc); 380 381 for (i = 3; i--;) { 382 if (6 & (1 << i)) 383 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_DATAIN); 384 else 385 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_DATAIN); 386 dc_delay(sc); 387 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CLK); 388 dc_delay(sc); 389 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); 390 dc_delay(sc); 391 } 392 393 for (i = 1; i <= 12; i++) { 394 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CLK); 395 dc_delay(sc); 396 if (!(CSR_READ_4(sc, DC_SIO) & DC_SIO_EE_DATAOUT)) { 397 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); 398 dc_delay(sc); 399 break; 400 } 401 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); 402 dc_delay(sc); 403 } 404 405 /* Turn off EEPROM access mode. */ 406 dc_eeprom_idle(sc); 407 408 if (i < 4 || i > 12) 409 sc->dc_romwidth = 6; 410 else 411 sc->dc_romwidth = i; 412 413 /* Enter EEPROM access mode. */ 414 CSR_WRITE_4(sc, DC_SIO, DC_SIO_EESEL); 415 dc_delay(sc); 416 DC_SETBIT(sc, DC_SIO, DC_SIO_ROMCTL_READ); 417 dc_delay(sc); 418 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); 419 dc_delay(sc); 420 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CS); 421 dc_delay(sc); 422 423 /* Turn off EEPROM access mode. */ 424 dc_eeprom_idle(sc); 425 } 426 427 static void 428 dc_eeprom_idle(struct dc_softc *sc) 429 { 430 int i; 431 432 CSR_WRITE_4(sc, DC_SIO, DC_SIO_EESEL); 433 dc_delay(sc); 434 DC_SETBIT(sc, DC_SIO, DC_SIO_ROMCTL_READ); 435 dc_delay(sc); 436 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); 437 dc_delay(sc); 438 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CS); 439 dc_delay(sc); 440 441 for (i = 0; i < 25; i++) { 442 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); 443 dc_delay(sc); 444 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CLK); 445 dc_delay(sc); 446 } 447 448 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); 449 dc_delay(sc); 450 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CS); 451 dc_delay(sc); 452 CSR_WRITE_4(sc, DC_SIO, 0x00000000); 453 } 454 455 /* 456 * Send a read command and address to the EEPROM, check for ACK. 457 */ 458 static void 459 dc_eeprom_putbyte(struct dc_softc *sc, int addr) 460 { 461 int d, i; 462 463 d = DC_EECMD_READ >> 6; 464 for (i = 3; i--; ) { 465 if (d & (1 << i)) 466 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_DATAIN); 467 else 468 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_DATAIN); 469 dc_delay(sc); 470 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CLK); 471 dc_delay(sc); 472 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); 473 dc_delay(sc); 474 } 475 476 /* 477 * Feed in each bit and strobe the clock. 478 */ 479 for (i = sc->dc_romwidth; i--;) { 480 if (addr & (1 << i)) { 481 SIO_SET(DC_SIO_EE_DATAIN); 482 } else { 483 SIO_CLR(DC_SIO_EE_DATAIN); 484 } 485 dc_delay(sc); 486 SIO_SET(DC_SIO_EE_CLK); 487 dc_delay(sc); 488 SIO_CLR(DC_SIO_EE_CLK); 489 dc_delay(sc); 490 } 491 } 492 493 /* 494 * Read a word of data stored in the EEPROM at address 'addr.' 495 * The PNIC 82c168/82c169 has its own non-standard way to read 496 * the EEPROM. 497 */ 498 static void 499 dc_eeprom_getword_pnic(struct dc_softc *sc, int addr, uint16_t *dest) 500 { 501 int i; 502 uint32_t r; 503 504 CSR_WRITE_4(sc, DC_PN_SIOCTL, DC_PN_EEOPCODE_READ | addr); 505 506 for (i = 0; i < DC_TIMEOUT; i++) { 507 DELAY(1); 508 r = CSR_READ_4(sc, DC_SIO); 509 if (!(r & DC_PN_SIOCTL_BUSY)) { 510 *dest = (uint16_t)(r & 0xFFFF); 511 return; 512 } 513 } 514 } 515 516 /* 517 * Read a word of data stored in the EEPROM at address 'addr.' 518 * The Xircom X3201 has its own non-standard way to read 519 * the EEPROM, too. 520 */ 521 static void 522 dc_eeprom_getword_xircom(struct dc_softc *sc, int addr, uint16_t *dest) 523 { 524 525 SIO_SET(DC_SIO_ROMSEL | DC_SIO_ROMCTL_READ); 526 527 addr *= 2; 528 CSR_WRITE_4(sc, DC_ROM, addr | 0x160); 529 *dest = (uint16_t)CSR_READ_4(sc, DC_SIO) & 0xff; 530 addr += 1; 531 CSR_WRITE_4(sc, DC_ROM, addr | 0x160); 532 *dest |= ((uint16_t)CSR_READ_4(sc, DC_SIO) & 0xff) << 8; 533 534 SIO_CLR(DC_SIO_ROMSEL | DC_SIO_ROMCTL_READ); 535 } 536 537 /* 538 * Read a word of data stored in the EEPROM at address 'addr.' 539 */ 540 static void 541 dc_eeprom_getword(struct dc_softc *sc, int addr, uint16_t *dest) 542 { 543 int i; 544 uint16_t word = 0; 545 546 /* Force EEPROM to idle state. */ 547 dc_eeprom_idle(sc); 548 549 /* Enter EEPROM access mode. */ 550 CSR_WRITE_4(sc, DC_SIO, DC_SIO_EESEL); 551 dc_delay(sc); 552 DC_SETBIT(sc, DC_SIO, DC_SIO_ROMCTL_READ); 553 dc_delay(sc); 554 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); 555 dc_delay(sc); 556 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CS); 557 dc_delay(sc); 558 559 /* 560 * Send address of word we want to read. 561 */ 562 dc_eeprom_putbyte(sc, addr); 563 564 /* 565 * Start reading bits from EEPROM. 566 */ 567 for (i = 0x8000; i; i >>= 1) { 568 SIO_SET(DC_SIO_EE_CLK); 569 dc_delay(sc); 570 if (CSR_READ_4(sc, DC_SIO) & DC_SIO_EE_DATAOUT) 571 word |= i; 572 dc_delay(sc); 573 SIO_CLR(DC_SIO_EE_CLK); 574 dc_delay(sc); 575 } 576 577 /* Turn off EEPROM access mode. */ 578 dc_eeprom_idle(sc); 579 580 *dest = word; 581 } 582 583 /* 584 * Read a sequence of words from the EEPROM. 585 */ 586 static void 587 dc_read_eeprom(struct dc_softc *sc, caddr_t dest, int off, int cnt, int be) 588 { 589 int i; 590 uint16_t word = 0, *ptr; 591 592 for (i = 0; i < cnt; i++) { 593 if (DC_IS_PNIC(sc)) 594 dc_eeprom_getword_pnic(sc, off + i, &word); 595 else if (DC_IS_XIRCOM(sc)) 596 dc_eeprom_getword_xircom(sc, off + i, &word); 597 else 598 dc_eeprom_getword(sc, off + i, &word); 599 ptr = (uint16_t *)(dest + (i * 2)); 600 if (be) 601 *ptr = be16toh(word); 602 else 603 *ptr = le16toh(word); 604 } 605 } 606 607 /* 608 * The following two routines are taken from the Macronix 98713 609 * Application Notes pp.19-21. 610 */ 611 /* 612 * Write a bit to the MII bus. 613 */ 614 static void 615 dc_mii_writebit(struct dc_softc *sc, int bit) 616 { 617 uint32_t reg; 618 619 reg = DC_SIO_ROMCTL_WRITE | (bit != 0 ? DC_SIO_MII_DATAOUT : 0); 620 CSR_WRITE_4(sc, DC_SIO, reg); 621 CSR_BARRIER_4(sc, DC_SIO, 622 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 623 DELAY(1); 624 625 CSR_WRITE_4(sc, DC_SIO, reg | DC_SIO_MII_CLK); 626 CSR_BARRIER_4(sc, DC_SIO, 627 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 628 DELAY(1); 629 CSR_WRITE_4(sc, DC_SIO, reg); 630 CSR_BARRIER_4(sc, DC_SIO, 631 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 632 DELAY(1); 633 } 634 635 /* 636 * Read a bit from the MII bus. 637 */ 638 static int 639 dc_mii_readbit(struct dc_softc *sc) 640 { 641 uint32_t reg; 642 643 reg = DC_SIO_ROMCTL_READ | DC_SIO_MII_DIR; 644 CSR_WRITE_4(sc, DC_SIO, reg); 645 CSR_BARRIER_4(sc, DC_SIO, 646 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 647 DELAY(1); 648 (void)CSR_READ_4(sc, DC_SIO); 649 CSR_WRITE_4(sc, DC_SIO, reg | DC_SIO_MII_CLK); 650 CSR_BARRIER_4(sc, DC_SIO, 651 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 652 DELAY(1); 653 CSR_WRITE_4(sc, DC_SIO, reg); 654 CSR_BARRIER_4(sc, DC_SIO, 655 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 656 DELAY(1); 657 if (CSR_READ_4(sc, DC_SIO) & DC_SIO_MII_DATAIN) 658 return (1); 659 660 return (0); 661 } 662 663 /* 664 * Sync the PHYs by setting data bit and strobing the clock 32 times. 665 */ 666 static void 667 dc_mii_sync(struct dc_softc *sc) 668 { 669 int i; 670 671 CSR_WRITE_4(sc, DC_SIO, DC_SIO_ROMCTL_WRITE); 672 CSR_BARRIER_4(sc, DC_SIO, 673 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 674 DELAY(1); 675 676 for (i = 0; i < 32; i++) 677 dc_mii_writebit(sc, 1); 678 } 679 680 /* 681 * Clock a series of bits through the MII. 682 */ 683 static void 684 dc_mii_send(struct dc_softc *sc, uint32_t bits, int cnt) 685 { 686 int i; 687 688 for (i = (0x1 << (cnt - 1)); i; i >>= 1) 689 dc_mii_writebit(sc, bits & i); 690 } 691 692 /* 693 * Read an PHY register through the MII. 694 */ 695 static int 696 dc_mii_readreg(struct dc_softc *sc, struct dc_mii_frame *frame) 697 { 698 int i; 699 700 /* 701 * Set up frame for RX. 702 */ 703 frame->mii_stdelim = DC_MII_STARTDELIM; 704 frame->mii_opcode = DC_MII_READOP; 705 706 /* 707 * Sync the PHYs. 708 */ 709 dc_mii_sync(sc); 710 711 /* 712 * Send command/address info. 713 */ 714 dc_mii_send(sc, frame->mii_stdelim, 2); 715 dc_mii_send(sc, frame->mii_opcode, 2); 716 dc_mii_send(sc, frame->mii_phyaddr, 5); 717 dc_mii_send(sc, frame->mii_regaddr, 5); 718 719 /* 720 * Now try reading data bits. If the turnaround failed, we still 721 * need to clock through 16 cycles to keep the PHY(s) in sync. 722 */ 723 frame->mii_turnaround = dc_mii_readbit(sc); 724 if (frame->mii_turnaround != 0) { 725 for (i = 0; i < 16; i++) 726 dc_mii_readbit(sc); 727 goto fail; 728 } 729 for (i = 0x8000; i; i >>= 1) { 730 if (dc_mii_readbit(sc)) 731 frame->mii_data |= i; 732 } 733 734 fail: 735 736 /* Clock the idle bits. */ 737 dc_mii_writebit(sc, 0); 738 dc_mii_writebit(sc, 0); 739 740 if (frame->mii_turnaround != 0) 741 return (1); 742 return (0); 743 } 744 745 /* 746 * Write to a PHY register through the MII. 747 */ 748 static int 749 dc_mii_writereg(struct dc_softc *sc, struct dc_mii_frame *frame) 750 { 751 752 /* 753 * Set up frame for TX. 754 */ 755 frame->mii_stdelim = DC_MII_STARTDELIM; 756 frame->mii_opcode = DC_MII_WRITEOP; 757 frame->mii_turnaround = DC_MII_TURNAROUND; 758 759 /* 760 * Sync the PHYs. 761 */ 762 dc_mii_sync(sc); 763 764 dc_mii_send(sc, frame->mii_stdelim, 2); 765 dc_mii_send(sc, frame->mii_opcode, 2); 766 dc_mii_send(sc, frame->mii_phyaddr, 5); 767 dc_mii_send(sc, frame->mii_regaddr, 5); 768 dc_mii_send(sc, frame->mii_turnaround, 2); 769 dc_mii_send(sc, frame->mii_data, 16); 770 771 /* Clock the idle bits. */ 772 dc_mii_writebit(sc, 0); 773 dc_mii_writebit(sc, 0); 774 775 return (0); 776 } 777 778 static int 779 dc_miibus_readreg(device_t dev, int phy, int reg) 780 { 781 struct dc_mii_frame frame; 782 struct dc_softc *sc; 783 int i, rval, phy_reg = 0; 784 785 sc = device_get_softc(dev); 786 bzero(&frame, sizeof(frame)); 787 788 if (sc->dc_pmode != DC_PMODE_MII) { 789 if (phy == (MII_NPHY - 1)) { 790 switch (reg) { 791 case MII_BMSR: 792 /* 793 * Fake something to make the probe 794 * code think there's a PHY here. 795 */ 796 return (BMSR_MEDIAMASK); 797 break; 798 case MII_PHYIDR1: 799 if (DC_IS_PNIC(sc)) 800 return (DC_VENDORID_LO); 801 return (DC_VENDORID_DEC); 802 break; 803 case MII_PHYIDR2: 804 if (DC_IS_PNIC(sc)) 805 return (DC_DEVICEID_82C168); 806 return (DC_DEVICEID_21143); 807 break; 808 default: 809 return (0); 810 break; 811 } 812 } else 813 return (0); 814 } 815 816 if (DC_IS_PNIC(sc)) { 817 CSR_WRITE_4(sc, DC_PN_MII, DC_PN_MIIOPCODE_READ | 818 (phy << 23) | (reg << 18)); 819 for (i = 0; i < DC_TIMEOUT; i++) { 820 DELAY(1); 821 rval = CSR_READ_4(sc, DC_PN_MII); 822 if (!(rval & DC_PN_MII_BUSY)) { 823 rval &= 0xFFFF; 824 return (rval == 0xFFFF ? 0 : rval); 825 } 826 } 827 return (0); 828 } 829 830 if (DC_IS_COMET(sc)) { 831 switch (reg) { 832 case MII_BMCR: 833 phy_reg = DC_AL_BMCR; 834 break; 835 case MII_BMSR: 836 phy_reg = DC_AL_BMSR; 837 break; 838 case MII_PHYIDR1: 839 phy_reg = DC_AL_VENID; 840 break; 841 case MII_PHYIDR2: 842 phy_reg = DC_AL_DEVID; 843 break; 844 case MII_ANAR: 845 phy_reg = DC_AL_ANAR; 846 break; 847 case MII_ANLPAR: 848 phy_reg = DC_AL_LPAR; 849 break; 850 case MII_ANER: 851 phy_reg = DC_AL_ANER; 852 break; 853 default: 854 device_printf(dev, "phy_read: bad phy register %x\n", 855 reg); 856 return (0); 857 break; 858 } 859 860 rval = CSR_READ_4(sc, phy_reg) & 0x0000FFFF; 861 862 if (rval == 0xFFFF) 863 return (0); 864 return (rval); 865 } 866 867 frame.mii_phyaddr = phy; 868 frame.mii_regaddr = reg; 869 if (sc->dc_type == DC_TYPE_98713) { 870 phy_reg = CSR_READ_4(sc, DC_NETCFG); 871 CSR_WRITE_4(sc, DC_NETCFG, phy_reg & ~DC_NETCFG_PORTSEL); 872 } 873 dc_mii_readreg(sc, &frame); 874 if (sc->dc_type == DC_TYPE_98713) 875 CSR_WRITE_4(sc, DC_NETCFG, phy_reg); 876 877 return (frame.mii_data); 878 } 879 880 static int 881 dc_miibus_writereg(device_t dev, int phy, int reg, int data) 882 { 883 struct dc_softc *sc; 884 struct dc_mii_frame frame; 885 int i, phy_reg = 0; 886 887 sc = device_get_softc(dev); 888 bzero(&frame, sizeof(frame)); 889 890 if (DC_IS_PNIC(sc)) { 891 CSR_WRITE_4(sc, DC_PN_MII, DC_PN_MIIOPCODE_WRITE | 892 (phy << 23) | (reg << 10) | data); 893 for (i = 0; i < DC_TIMEOUT; i++) { 894 if (!(CSR_READ_4(sc, DC_PN_MII) & DC_PN_MII_BUSY)) 895 break; 896 } 897 return (0); 898 } 899 900 if (DC_IS_COMET(sc)) { 901 switch (reg) { 902 case MII_BMCR: 903 phy_reg = DC_AL_BMCR; 904 break; 905 case MII_BMSR: 906 phy_reg = DC_AL_BMSR; 907 break; 908 case MII_PHYIDR1: 909 phy_reg = DC_AL_VENID; 910 break; 911 case MII_PHYIDR2: 912 phy_reg = DC_AL_DEVID; 913 break; 914 case MII_ANAR: 915 phy_reg = DC_AL_ANAR; 916 break; 917 case MII_ANLPAR: 918 phy_reg = DC_AL_LPAR; 919 break; 920 case MII_ANER: 921 phy_reg = DC_AL_ANER; 922 break; 923 default: 924 device_printf(dev, "phy_write: bad phy register %x\n", 925 reg); 926 return (0); 927 break; 928 } 929 930 CSR_WRITE_4(sc, phy_reg, data); 931 return (0); 932 } 933 934 frame.mii_phyaddr = phy; 935 frame.mii_regaddr = reg; 936 frame.mii_data = data; 937 938 if (sc->dc_type == DC_TYPE_98713) { 939 phy_reg = CSR_READ_4(sc, DC_NETCFG); 940 CSR_WRITE_4(sc, DC_NETCFG, phy_reg & ~DC_NETCFG_PORTSEL); 941 } 942 dc_mii_writereg(sc, &frame); 943 if (sc->dc_type == DC_TYPE_98713) 944 CSR_WRITE_4(sc, DC_NETCFG, phy_reg); 945 946 return (0); 947 } 948 949 static void 950 dc_miibus_statchg(device_t dev) 951 { 952 struct dc_softc *sc; 953 struct ifnet *ifp; 954 struct mii_data *mii; 955 struct ifmedia *ifm; 956 957 sc = device_get_softc(dev); 958 959 mii = device_get_softc(sc->dc_miibus); 960 ifp = sc->dc_ifp; 961 if (mii == NULL || ifp == NULL || 962 (ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) 963 return; 964 965 ifm = &mii->mii_media; 966 if (DC_IS_DAVICOM(sc) && 967 IFM_SUBTYPE(ifm->ifm_media) == IFM_HPNA_1) { 968 dc_setcfg(sc, ifm->ifm_media); 969 sc->dc_if_media = ifm->ifm_media; 970 return; 971 } 972 973 sc->dc_link = 0; 974 if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) == 975 (IFM_ACTIVE | IFM_AVALID)) { 976 switch (IFM_SUBTYPE(mii->mii_media_active)) { 977 case IFM_10_T: 978 case IFM_100_TX: 979 sc->dc_link = 1; 980 break; 981 default: 982 break; 983 } 984 } 985 if (sc->dc_link == 0) 986 return; 987 988 sc->dc_if_media = mii->mii_media_active; 989 if (DC_IS_ADMTEK(sc)) 990 return; 991 dc_setcfg(sc, mii->mii_media_active); 992 } 993 994 /* 995 * Special support for DM9102A cards with HomePNA PHYs. Note: 996 * with the Davicom DM9102A/DM9801 eval board that I have, it seems 997 * to be impossible to talk to the management interface of the DM9801 998 * PHY (its MDIO pin is not connected to anything). Consequently, 999 * the driver has to just 'know' about the additional mode and deal 1000 * with it itself. *sigh* 1001 */ 1002 static void 1003 dc_miibus_mediainit(device_t dev) 1004 { 1005 struct dc_softc *sc; 1006 struct mii_data *mii; 1007 struct ifmedia *ifm; 1008 int rev; 1009 1010 rev = pci_get_revid(dev); 1011 1012 sc = device_get_softc(dev); 1013 mii = device_get_softc(sc->dc_miibus); 1014 ifm = &mii->mii_media; 1015 1016 if (DC_IS_DAVICOM(sc) && rev >= DC_REVISION_DM9102A) 1017 ifmedia_add(ifm, IFM_ETHER | IFM_HPNA_1, 0, NULL); 1018 } 1019 1020 #define DC_BITS_512 9 1021 #define DC_BITS_128 7 1022 #define DC_BITS_64 6 1023 1024 static uint32_t 1025 dc_mchash_le(struct dc_softc *sc, const uint8_t *addr) 1026 { 1027 uint32_t crc; 1028 1029 /* Compute CRC for the address value. */ 1030 crc = ether_crc32_le(addr, ETHER_ADDR_LEN); 1031 1032 /* 1033 * The hash table on the PNIC II and the MX98715AEC-C/D/E 1034 * chips is only 128 bits wide. 1035 */ 1036 if (sc->dc_flags & DC_128BIT_HASH) 1037 return (crc & ((1 << DC_BITS_128) - 1)); 1038 1039 /* The hash table on the MX98715BEC is only 64 bits wide. */ 1040 if (sc->dc_flags & DC_64BIT_HASH) 1041 return (crc & ((1 << DC_BITS_64) - 1)); 1042 1043 /* Xircom's hash filtering table is different (read: weird) */ 1044 /* Xircom uses the LEAST significant bits */ 1045 if (DC_IS_XIRCOM(sc)) { 1046 if ((crc & 0x180) == 0x180) 1047 return ((crc & 0x0F) + (crc & 0x70) * 3 + (14 << 4)); 1048 else 1049 return ((crc & 0x1F) + ((crc >> 1) & 0xF0) * 3 + 1050 (12 << 4)); 1051 } 1052 1053 return (crc & ((1 << DC_BITS_512) - 1)); 1054 } 1055 1056 /* 1057 * Calculate CRC of a multicast group address, return the lower 6 bits. 1058 */ 1059 static uint32_t 1060 dc_mchash_be(const uint8_t *addr) 1061 { 1062 uint32_t crc; 1063 1064 /* Compute CRC for the address value. */ 1065 crc = ether_crc32_be(addr, ETHER_ADDR_LEN); 1066 1067 /* Return the filter bit position. */ 1068 return ((crc >> 26) & 0x0000003F); 1069 } 1070 1071 /* 1072 * 21143-style RX filter setup routine. Filter programming is done by 1073 * downloading a special setup frame into the TX engine. 21143, Macronix, 1074 * PNIC, PNIC II and Davicom chips are programmed this way. 1075 * 1076 * We always program the chip using 'hash perfect' mode, i.e. one perfect 1077 * address (our node address) and a 512-bit hash filter for multicast 1078 * frames. We also sneak the broadcast address into the hash filter since 1079 * we need that too. 1080 */ 1081 static void 1082 dc_setfilt_21143(struct dc_softc *sc) 1083 { 1084 uint16_t eaddr[(ETHER_ADDR_LEN+1)/2]; 1085 struct dc_desc *sframe; 1086 uint32_t h, *sp; 1087 struct ifmultiaddr *ifma; 1088 struct ifnet *ifp; 1089 int i; 1090 1091 ifp = sc->dc_ifp; 1092 1093 i = sc->dc_cdata.dc_tx_prod; 1094 DC_INC(sc->dc_cdata.dc_tx_prod, DC_TX_LIST_CNT); 1095 sc->dc_cdata.dc_tx_cnt++; 1096 sframe = &sc->dc_ldata.dc_tx_list[i]; 1097 sp = sc->dc_cdata.dc_sbuf; 1098 bzero(sp, DC_SFRAME_LEN); 1099 1100 sframe->dc_data = htole32(DC_ADDR_LO(sc->dc_saddr)); 1101 sframe->dc_ctl = htole32(DC_SFRAME_LEN | DC_TXCTL_SETUP | 1102 DC_TXCTL_TLINK | DC_FILTER_HASHPERF | DC_TXCTL_FINT); 1103 1104 sc->dc_cdata.dc_tx_chain[i] = (struct mbuf *)sc->dc_cdata.dc_sbuf; 1105 1106 /* If we want promiscuous mode, set the allframes bit. */ 1107 if (ifp->if_flags & IFF_PROMISC) 1108 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC); 1109 else 1110 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC); 1111 1112 if (ifp->if_flags & IFF_ALLMULTI) 1113 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI); 1114 else 1115 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI); 1116 1117 if_maddr_rlock(ifp); 1118 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 1119 if (ifma->ifma_addr->sa_family != AF_LINK) 1120 continue; 1121 h = dc_mchash_le(sc, 1122 LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 1123 sp[h >> 4] |= htole32(1 << (h & 0xF)); 1124 } 1125 if_maddr_runlock(ifp); 1126 1127 if (ifp->if_flags & IFF_BROADCAST) { 1128 h = dc_mchash_le(sc, ifp->if_broadcastaddr); 1129 sp[h >> 4] |= htole32(1 << (h & 0xF)); 1130 } 1131 1132 /* Set our MAC address. */ 1133 bcopy(IF_LLADDR(sc->dc_ifp), eaddr, ETHER_ADDR_LEN); 1134 sp[39] = DC_SP_MAC(eaddr[0]); 1135 sp[40] = DC_SP_MAC(eaddr[1]); 1136 sp[41] = DC_SP_MAC(eaddr[2]); 1137 1138 sframe->dc_status = htole32(DC_TXSTAT_OWN); 1139 bus_dmamap_sync(sc->dc_stag, sc->dc_smap, BUS_DMASYNC_PREWRITE); 1140 CSR_WRITE_4(sc, DC_TXSTART, 0xFFFFFFFF); 1141 1142 /* 1143 * The PNIC takes an exceedingly long time to process its 1144 * setup frame; wait 10ms after posting the setup frame 1145 * before proceeding, just so it has time to swallow its 1146 * medicine. 1147 */ 1148 DELAY(10000); 1149 1150 sc->dc_wdog_timer = 5; 1151 } 1152 1153 static void 1154 dc_setfilt_admtek(struct dc_softc *sc) 1155 { 1156 uint8_t eaddr[ETHER_ADDR_LEN]; 1157 struct ifnet *ifp; 1158 struct ifmultiaddr *ifma; 1159 int h = 0; 1160 uint32_t hashes[2] = { 0, 0 }; 1161 1162 ifp = sc->dc_ifp; 1163 1164 /* Init our MAC address. */ 1165 bcopy(IF_LLADDR(sc->dc_ifp), eaddr, ETHER_ADDR_LEN); 1166 CSR_WRITE_4(sc, DC_AL_PAR0, eaddr[3] << 24 | eaddr[2] << 16 | 1167 eaddr[1] << 8 | eaddr[0]); 1168 CSR_WRITE_4(sc, DC_AL_PAR1, eaddr[5] << 8 | eaddr[4]); 1169 1170 /* If we want promiscuous mode, set the allframes bit. */ 1171 if (ifp->if_flags & IFF_PROMISC) 1172 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC); 1173 else 1174 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC); 1175 1176 if (ifp->if_flags & IFF_ALLMULTI) 1177 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI); 1178 else 1179 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI); 1180 1181 /* First, zot all the existing hash bits. */ 1182 CSR_WRITE_4(sc, DC_AL_MAR0, 0); 1183 CSR_WRITE_4(sc, DC_AL_MAR1, 0); 1184 1185 /* 1186 * If we're already in promisc or allmulti mode, we 1187 * don't have to bother programming the multicast filter. 1188 */ 1189 if (ifp->if_flags & (IFF_PROMISC | IFF_ALLMULTI)) 1190 return; 1191 1192 /* Now program new ones. */ 1193 if_maddr_rlock(ifp); 1194 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 1195 if (ifma->ifma_addr->sa_family != AF_LINK) 1196 continue; 1197 if (DC_IS_CENTAUR(sc)) 1198 h = dc_mchash_le(sc, 1199 LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 1200 else 1201 h = dc_mchash_be( 1202 LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 1203 if (h < 32) 1204 hashes[0] |= (1 << h); 1205 else 1206 hashes[1] |= (1 << (h - 32)); 1207 } 1208 if_maddr_runlock(ifp); 1209 1210 CSR_WRITE_4(sc, DC_AL_MAR0, hashes[0]); 1211 CSR_WRITE_4(sc, DC_AL_MAR1, hashes[1]); 1212 } 1213 1214 static void 1215 dc_setfilt_asix(struct dc_softc *sc) 1216 { 1217 uint32_t eaddr[(ETHER_ADDR_LEN+3)/4]; 1218 struct ifnet *ifp; 1219 struct ifmultiaddr *ifma; 1220 int h = 0; 1221 uint32_t hashes[2] = { 0, 0 }; 1222 1223 ifp = sc->dc_ifp; 1224 1225 /* Init our MAC address. */ 1226 bcopy(IF_LLADDR(sc->dc_ifp), eaddr, ETHER_ADDR_LEN); 1227 CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_PAR0); 1228 CSR_WRITE_4(sc, DC_AX_FILTDATA, eaddr[0]); 1229 CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_PAR1); 1230 CSR_WRITE_4(sc, DC_AX_FILTDATA, eaddr[1]); 1231 1232 /* If we want promiscuous mode, set the allframes bit. */ 1233 if (ifp->if_flags & IFF_PROMISC) 1234 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC); 1235 else 1236 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC); 1237 1238 if (ifp->if_flags & IFF_ALLMULTI) 1239 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI); 1240 else 1241 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI); 1242 1243 /* 1244 * The ASIX chip has a special bit to enable reception 1245 * of broadcast frames. 1246 */ 1247 if (ifp->if_flags & IFF_BROADCAST) 1248 DC_SETBIT(sc, DC_NETCFG, DC_AX_NETCFG_RX_BROAD); 1249 else 1250 DC_CLRBIT(sc, DC_NETCFG, DC_AX_NETCFG_RX_BROAD); 1251 1252 /* first, zot all the existing hash bits */ 1253 CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_MAR0); 1254 CSR_WRITE_4(sc, DC_AX_FILTDATA, 0); 1255 CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_MAR1); 1256 CSR_WRITE_4(sc, DC_AX_FILTDATA, 0); 1257 1258 /* 1259 * If we're already in promisc or allmulti mode, we 1260 * don't have to bother programming the multicast filter. 1261 */ 1262 if (ifp->if_flags & (IFF_PROMISC | IFF_ALLMULTI)) 1263 return; 1264 1265 /* now program new ones */ 1266 if_maddr_rlock(ifp); 1267 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 1268 if (ifma->ifma_addr->sa_family != AF_LINK) 1269 continue; 1270 h = dc_mchash_be(LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 1271 if (h < 32) 1272 hashes[0] |= (1 << h); 1273 else 1274 hashes[1] |= (1 << (h - 32)); 1275 } 1276 if_maddr_runlock(ifp); 1277 1278 CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_MAR0); 1279 CSR_WRITE_4(sc, DC_AX_FILTDATA, hashes[0]); 1280 CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_MAR1); 1281 CSR_WRITE_4(sc, DC_AX_FILTDATA, hashes[1]); 1282 } 1283 1284 static void 1285 dc_setfilt_xircom(struct dc_softc *sc) 1286 { 1287 uint16_t eaddr[(ETHER_ADDR_LEN+1)/2]; 1288 struct ifnet *ifp; 1289 struct ifmultiaddr *ifma; 1290 struct dc_desc *sframe; 1291 uint32_t h, *sp; 1292 int i; 1293 1294 ifp = sc->dc_ifp; 1295 DC_CLRBIT(sc, DC_NETCFG, (DC_NETCFG_TX_ON | DC_NETCFG_RX_ON)); 1296 1297 i = sc->dc_cdata.dc_tx_prod; 1298 DC_INC(sc->dc_cdata.dc_tx_prod, DC_TX_LIST_CNT); 1299 sc->dc_cdata.dc_tx_cnt++; 1300 sframe = &sc->dc_ldata.dc_tx_list[i]; 1301 sp = sc->dc_cdata.dc_sbuf; 1302 bzero(sp, DC_SFRAME_LEN); 1303 1304 sframe->dc_data = htole32(DC_ADDR_LO(sc->dc_saddr)); 1305 sframe->dc_ctl = htole32(DC_SFRAME_LEN | DC_TXCTL_SETUP | 1306 DC_TXCTL_TLINK | DC_FILTER_HASHPERF | DC_TXCTL_FINT); 1307 1308 sc->dc_cdata.dc_tx_chain[i] = (struct mbuf *)sc->dc_cdata.dc_sbuf; 1309 1310 /* If we want promiscuous mode, set the allframes bit. */ 1311 if (ifp->if_flags & IFF_PROMISC) 1312 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC); 1313 else 1314 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC); 1315 1316 if (ifp->if_flags & IFF_ALLMULTI) 1317 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI); 1318 else 1319 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI); 1320 1321 if_maddr_rlock(ifp); 1322 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 1323 if (ifma->ifma_addr->sa_family != AF_LINK) 1324 continue; 1325 h = dc_mchash_le(sc, 1326 LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 1327 sp[h >> 4] |= htole32(1 << (h & 0xF)); 1328 } 1329 if_maddr_runlock(ifp); 1330 1331 if (ifp->if_flags & IFF_BROADCAST) { 1332 h = dc_mchash_le(sc, ifp->if_broadcastaddr); 1333 sp[h >> 4] |= htole32(1 << (h & 0xF)); 1334 } 1335 1336 /* Set our MAC address. */ 1337 bcopy(IF_LLADDR(sc->dc_ifp), eaddr, ETHER_ADDR_LEN); 1338 sp[0] = DC_SP_MAC(eaddr[0]); 1339 sp[1] = DC_SP_MAC(eaddr[1]); 1340 sp[2] = DC_SP_MAC(eaddr[2]); 1341 1342 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_TX_ON); 1343 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_ON); 1344 sframe->dc_status = htole32(DC_TXSTAT_OWN); 1345 bus_dmamap_sync(sc->dc_stag, sc->dc_smap, BUS_DMASYNC_PREWRITE); 1346 CSR_WRITE_4(sc, DC_TXSTART, 0xFFFFFFFF); 1347 1348 /* 1349 * Wait some time... 1350 */ 1351 DELAY(1000); 1352 1353 sc->dc_wdog_timer = 5; 1354 } 1355 1356 static void 1357 dc_setfilt(struct dc_softc *sc) 1358 { 1359 1360 if (DC_IS_INTEL(sc) || DC_IS_MACRONIX(sc) || DC_IS_PNIC(sc) || 1361 DC_IS_PNICII(sc) || DC_IS_DAVICOM(sc) || DC_IS_CONEXANT(sc)) 1362 dc_setfilt_21143(sc); 1363 1364 if (DC_IS_ASIX(sc)) 1365 dc_setfilt_asix(sc); 1366 1367 if (DC_IS_ADMTEK(sc)) 1368 dc_setfilt_admtek(sc); 1369 1370 if (DC_IS_XIRCOM(sc)) 1371 dc_setfilt_xircom(sc); 1372 } 1373 1374 static void 1375 dc_netcfg_wait(struct dc_softc *sc) 1376 { 1377 uint32_t isr; 1378 int i; 1379 1380 for (i = 0; i < DC_TIMEOUT; i++) { 1381 isr = CSR_READ_4(sc, DC_ISR); 1382 if (isr & DC_ISR_TX_IDLE && 1383 ((isr & DC_ISR_RX_STATE) == DC_RXSTATE_STOPPED || 1384 (isr & DC_ISR_RX_STATE) == DC_RXSTATE_WAIT)) 1385 break; 1386 DELAY(10); 1387 } 1388 if (i == DC_TIMEOUT) { 1389 if (!(isr & DC_ISR_TX_IDLE) && !DC_IS_ASIX(sc)) 1390 device_printf(sc->dc_dev, 1391 "%s: failed to force tx to idle state\n", __func__); 1392 if (!((isr & DC_ISR_RX_STATE) == DC_RXSTATE_STOPPED || 1393 (isr & DC_ISR_RX_STATE) == DC_RXSTATE_WAIT) && 1394 !DC_HAS_BROKEN_RXSTATE(sc)) 1395 device_printf(sc->dc_dev, 1396 "%s: failed to force rx to idle state\n", __func__); 1397 } 1398 } 1399 1400 /* 1401 * In order to fiddle with the 'full-duplex' and '100Mbps' bits in 1402 * the netconfig register, we first have to put the transmit and/or 1403 * receive logic in the idle state. 1404 */ 1405 static void 1406 dc_setcfg(struct dc_softc *sc, int media) 1407 { 1408 int restart = 0, watchdogreg; 1409 1410 if (IFM_SUBTYPE(media) == IFM_NONE) 1411 return; 1412 1413 if (CSR_READ_4(sc, DC_NETCFG) & (DC_NETCFG_TX_ON | DC_NETCFG_RX_ON)) { 1414 restart = 1; 1415 DC_CLRBIT(sc, DC_NETCFG, (DC_NETCFG_TX_ON | DC_NETCFG_RX_ON)); 1416 dc_netcfg_wait(sc); 1417 } 1418 1419 if (IFM_SUBTYPE(media) == IFM_100_TX) { 1420 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_SPEEDSEL); 1421 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_HEARTBEAT); 1422 if (sc->dc_pmode == DC_PMODE_MII) { 1423 if (DC_IS_INTEL(sc)) { 1424 /* There's a write enable bit here that reads as 1. */ 1425 watchdogreg = CSR_READ_4(sc, DC_WATCHDOG); 1426 watchdogreg &= ~DC_WDOG_CTLWREN; 1427 watchdogreg |= DC_WDOG_JABBERDIS; 1428 CSR_WRITE_4(sc, DC_WATCHDOG, watchdogreg); 1429 } else { 1430 DC_SETBIT(sc, DC_WATCHDOG, DC_WDOG_JABBERDIS); 1431 } 1432 DC_CLRBIT(sc, DC_NETCFG, (DC_NETCFG_PCS | 1433 DC_NETCFG_PORTSEL | DC_NETCFG_SCRAMBLER)); 1434 if (sc->dc_type == DC_TYPE_98713) 1435 DC_SETBIT(sc, DC_NETCFG, (DC_NETCFG_PCS | 1436 DC_NETCFG_SCRAMBLER)); 1437 if (!DC_IS_DAVICOM(sc)) 1438 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL); 1439 DC_CLRBIT(sc, DC_10BTCTRL, 0xFFFF); 1440 } else { 1441 if (DC_IS_PNIC(sc)) { 1442 DC_PN_GPIO_SETBIT(sc, DC_PN_GPIO_SPEEDSEL); 1443 DC_PN_GPIO_SETBIT(sc, DC_PN_GPIO_100TX_LOOP); 1444 DC_SETBIT(sc, DC_PN_NWAY, DC_PN_NWAY_SPEEDSEL); 1445 } 1446 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL); 1447 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PCS); 1448 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_SCRAMBLER); 1449 } 1450 } 1451 1452 if (IFM_SUBTYPE(media) == IFM_10_T) { 1453 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_SPEEDSEL); 1454 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_HEARTBEAT); 1455 if (sc->dc_pmode == DC_PMODE_MII) { 1456 /* There's a write enable bit here that reads as 1. */ 1457 if (DC_IS_INTEL(sc)) { 1458 watchdogreg = CSR_READ_4(sc, DC_WATCHDOG); 1459 watchdogreg &= ~DC_WDOG_CTLWREN; 1460 watchdogreg |= DC_WDOG_JABBERDIS; 1461 CSR_WRITE_4(sc, DC_WATCHDOG, watchdogreg); 1462 } else { 1463 DC_SETBIT(sc, DC_WATCHDOG, DC_WDOG_JABBERDIS); 1464 } 1465 DC_CLRBIT(sc, DC_NETCFG, (DC_NETCFG_PCS | 1466 DC_NETCFG_PORTSEL | DC_NETCFG_SCRAMBLER)); 1467 if (sc->dc_type == DC_TYPE_98713) 1468 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PCS); 1469 if (!DC_IS_DAVICOM(sc)) 1470 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL); 1471 DC_CLRBIT(sc, DC_10BTCTRL, 0xFFFF); 1472 } else { 1473 if (DC_IS_PNIC(sc)) { 1474 DC_PN_GPIO_CLRBIT(sc, DC_PN_GPIO_SPEEDSEL); 1475 DC_PN_GPIO_SETBIT(sc, DC_PN_GPIO_100TX_LOOP); 1476 DC_CLRBIT(sc, DC_PN_NWAY, DC_PN_NWAY_SPEEDSEL); 1477 } 1478 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL); 1479 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_PCS); 1480 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_SCRAMBLER); 1481 if (DC_IS_INTEL(sc)) { 1482 DC_CLRBIT(sc, DC_SIARESET, DC_SIA_RESET); 1483 DC_CLRBIT(sc, DC_10BTCTRL, 0xFFFF); 1484 if ((media & IFM_GMASK) == IFM_FDX) 1485 DC_SETBIT(sc, DC_10BTCTRL, 0x7F3D); 1486 else 1487 DC_SETBIT(sc, DC_10BTCTRL, 0x7F3F); 1488 DC_SETBIT(sc, DC_SIARESET, DC_SIA_RESET); 1489 DC_CLRBIT(sc, DC_10BTCTRL, 1490 DC_TCTL_AUTONEGENBL); 1491 DELAY(20000); 1492 } 1493 } 1494 } 1495 1496 /* 1497 * If this is a Davicom DM9102A card with a DM9801 HomePNA 1498 * PHY and we want HomePNA mode, set the portsel bit to turn 1499 * on the external MII port. 1500 */ 1501 if (DC_IS_DAVICOM(sc)) { 1502 if (IFM_SUBTYPE(media) == IFM_HPNA_1) { 1503 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL); 1504 sc->dc_link = 1; 1505 } else { 1506 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL); 1507 } 1508 } 1509 1510 if ((media & IFM_GMASK) == IFM_FDX) { 1511 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_FULLDUPLEX); 1512 if (sc->dc_pmode == DC_PMODE_SYM && DC_IS_PNIC(sc)) 1513 DC_SETBIT(sc, DC_PN_NWAY, DC_PN_NWAY_DUPLEX); 1514 } else { 1515 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_FULLDUPLEX); 1516 if (sc->dc_pmode == DC_PMODE_SYM && DC_IS_PNIC(sc)) 1517 DC_CLRBIT(sc, DC_PN_NWAY, DC_PN_NWAY_DUPLEX); 1518 } 1519 1520 if (restart) 1521 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_TX_ON | DC_NETCFG_RX_ON); 1522 } 1523 1524 static void 1525 dc_reset(struct dc_softc *sc) 1526 { 1527 int i; 1528 1529 DC_SETBIT(sc, DC_BUSCTL, DC_BUSCTL_RESET); 1530 1531 for (i = 0; i < DC_TIMEOUT; i++) { 1532 DELAY(10); 1533 if (!(CSR_READ_4(sc, DC_BUSCTL) & DC_BUSCTL_RESET)) 1534 break; 1535 } 1536 1537 if (DC_IS_ASIX(sc) || DC_IS_ADMTEK(sc) || DC_IS_CONEXANT(sc) || 1538 DC_IS_XIRCOM(sc) || DC_IS_INTEL(sc)) { 1539 DELAY(10000); 1540 DC_CLRBIT(sc, DC_BUSCTL, DC_BUSCTL_RESET); 1541 i = 0; 1542 } 1543 1544 if (i == DC_TIMEOUT) 1545 device_printf(sc->dc_dev, "reset never completed!\n"); 1546 1547 /* Wait a little while for the chip to get its brains in order. */ 1548 DELAY(1000); 1549 1550 CSR_WRITE_4(sc, DC_IMR, 0x00000000); 1551 CSR_WRITE_4(sc, DC_BUSCTL, 0x00000000); 1552 CSR_WRITE_4(sc, DC_NETCFG, 0x00000000); 1553 1554 /* 1555 * Bring the SIA out of reset. In some cases, it looks 1556 * like failing to unreset the SIA soon enough gets it 1557 * into a state where it will never come out of reset 1558 * until we reset the whole chip again. 1559 */ 1560 if (DC_IS_INTEL(sc)) { 1561 DC_SETBIT(sc, DC_SIARESET, DC_SIA_RESET); 1562 CSR_WRITE_4(sc, DC_10BTCTRL, 0xFFFFFFFF); 1563 CSR_WRITE_4(sc, DC_WATCHDOG, 0); 1564 } 1565 } 1566 1567 static const struct dc_type * 1568 dc_devtype(device_t dev) 1569 { 1570 const struct dc_type *t; 1571 uint32_t devid; 1572 uint8_t rev; 1573 1574 t = dc_devs; 1575 devid = pci_get_devid(dev); 1576 rev = pci_get_revid(dev); 1577 1578 while (t->dc_name != NULL) { 1579 if (devid == t->dc_devid && rev >= t->dc_minrev) 1580 return (t); 1581 t++; 1582 } 1583 1584 return (NULL); 1585 } 1586 1587 /* 1588 * Probe for a 21143 or clone chip. Check the PCI vendor and device 1589 * IDs against our list and return a device name if we find a match. 1590 * We do a little bit of extra work to identify the exact type of 1591 * chip. The MX98713 and MX98713A have the same PCI vendor/device ID, 1592 * but different revision IDs. The same is true for 98715/98715A 1593 * chips and the 98725, as well as the ASIX and ADMtek chips. In some 1594 * cases, the exact chip revision affects driver behavior. 1595 */ 1596 static int 1597 dc_probe(device_t dev) 1598 { 1599 const struct dc_type *t; 1600 1601 t = dc_devtype(dev); 1602 1603 if (t != NULL) { 1604 device_set_desc(dev, t->dc_name); 1605 return (BUS_PROBE_DEFAULT); 1606 } 1607 1608 return (ENXIO); 1609 } 1610 1611 static void 1612 dc_apply_fixup(struct dc_softc *sc, int media) 1613 { 1614 struct dc_mediainfo *m; 1615 uint8_t *p; 1616 int i; 1617 uint32_t reg; 1618 1619 m = sc->dc_mi; 1620 1621 while (m != NULL) { 1622 if (m->dc_media == media) 1623 break; 1624 m = m->dc_next; 1625 } 1626 1627 if (m == NULL) 1628 return; 1629 1630 for (i = 0, p = m->dc_reset_ptr; i < m->dc_reset_len; i++, p += 2) { 1631 reg = (p[0] | (p[1] << 8)) << 16; 1632 CSR_WRITE_4(sc, DC_WATCHDOG, reg); 1633 } 1634 1635 for (i = 0, p = m->dc_gp_ptr; i < m->dc_gp_len; i++, p += 2) { 1636 reg = (p[0] | (p[1] << 8)) << 16; 1637 CSR_WRITE_4(sc, DC_WATCHDOG, reg); 1638 } 1639 } 1640 1641 static int 1642 dc_decode_leaf_sia(struct dc_softc *sc, struct dc_eblock_sia *l) 1643 { 1644 struct dc_mediainfo *m; 1645 1646 m = malloc(sizeof(struct dc_mediainfo), M_DEVBUF, M_NOWAIT | M_ZERO); 1647 if (m == NULL) { 1648 device_printf(sc->dc_dev, "Could not allocate mediainfo\n"); 1649 return (ENOMEM); 1650 } 1651 switch (l->dc_sia_code & ~DC_SIA_CODE_EXT) { 1652 case DC_SIA_CODE_10BT: 1653 m->dc_media = IFM_10_T; 1654 break; 1655 case DC_SIA_CODE_10BT_FDX: 1656 m->dc_media = IFM_10_T | IFM_FDX; 1657 break; 1658 case DC_SIA_CODE_10B2: 1659 m->dc_media = IFM_10_2; 1660 break; 1661 case DC_SIA_CODE_10B5: 1662 m->dc_media = IFM_10_5; 1663 break; 1664 default: 1665 break; 1666 } 1667 1668 /* 1669 * We need to ignore CSR13, CSR14, CSR15 for SIA mode. 1670 * Things apparently already work for cards that do 1671 * supply Media Specific Data. 1672 */ 1673 if (l->dc_sia_code & DC_SIA_CODE_EXT) { 1674 m->dc_gp_len = 2; 1675 m->dc_gp_ptr = 1676 (uint8_t *)&l->dc_un.dc_sia_ext.dc_sia_gpio_ctl; 1677 } else { 1678 m->dc_gp_len = 2; 1679 m->dc_gp_ptr = 1680 (uint8_t *)&l->dc_un.dc_sia_noext.dc_sia_gpio_ctl; 1681 } 1682 1683 m->dc_next = sc->dc_mi; 1684 sc->dc_mi = m; 1685 1686 sc->dc_pmode = DC_PMODE_SIA; 1687 return (0); 1688 } 1689 1690 static int 1691 dc_decode_leaf_sym(struct dc_softc *sc, struct dc_eblock_sym *l) 1692 { 1693 struct dc_mediainfo *m; 1694 1695 m = malloc(sizeof(struct dc_mediainfo), M_DEVBUF, M_NOWAIT | M_ZERO); 1696 if (m == NULL) { 1697 device_printf(sc->dc_dev, "Could not allocate mediainfo\n"); 1698 return (ENOMEM); 1699 } 1700 if (l->dc_sym_code == DC_SYM_CODE_100BT) 1701 m->dc_media = IFM_100_TX; 1702 1703 if (l->dc_sym_code == DC_SYM_CODE_100BT_FDX) 1704 m->dc_media = IFM_100_TX | IFM_FDX; 1705 1706 m->dc_gp_len = 2; 1707 m->dc_gp_ptr = (uint8_t *)&l->dc_sym_gpio_ctl; 1708 1709 m->dc_next = sc->dc_mi; 1710 sc->dc_mi = m; 1711 1712 sc->dc_pmode = DC_PMODE_SYM; 1713 return (0); 1714 } 1715 1716 static int 1717 dc_decode_leaf_mii(struct dc_softc *sc, struct dc_eblock_mii *l) 1718 { 1719 struct dc_mediainfo *m; 1720 uint8_t *p; 1721 1722 m = malloc(sizeof(struct dc_mediainfo), M_DEVBUF, M_NOWAIT | M_ZERO); 1723 if (m == NULL) { 1724 device_printf(sc->dc_dev, "Could not allocate mediainfo\n"); 1725 return (ENOMEM); 1726 } 1727 /* We abuse IFM_AUTO to represent MII. */ 1728 m->dc_media = IFM_AUTO; 1729 m->dc_gp_len = l->dc_gpr_len; 1730 1731 p = (uint8_t *)l; 1732 p += sizeof(struct dc_eblock_mii); 1733 m->dc_gp_ptr = p; 1734 p += 2 * l->dc_gpr_len; 1735 m->dc_reset_len = *p; 1736 p++; 1737 m->dc_reset_ptr = p; 1738 1739 m->dc_next = sc->dc_mi; 1740 sc->dc_mi = m; 1741 return (0); 1742 } 1743 1744 static int 1745 dc_read_srom(struct dc_softc *sc, int bits) 1746 { 1747 int size; 1748 1749 size = DC_ROM_SIZE(bits); 1750 sc->dc_srom = malloc(size, M_DEVBUF, M_NOWAIT); 1751 if (sc->dc_srom == NULL) { 1752 device_printf(sc->dc_dev, "Could not allocate SROM buffer\n"); 1753 return (ENOMEM); 1754 } 1755 dc_read_eeprom(sc, (caddr_t)sc->dc_srom, 0, (size / 2), 0); 1756 return (0); 1757 } 1758 1759 static int 1760 dc_parse_21143_srom(struct dc_softc *sc) 1761 { 1762 struct dc_leaf_hdr *lhdr; 1763 struct dc_eblock_hdr *hdr; 1764 int error, have_mii, i, loff; 1765 char *ptr; 1766 1767 have_mii = 0; 1768 loff = sc->dc_srom[27]; 1769 lhdr = (struct dc_leaf_hdr *)&(sc->dc_srom[loff]); 1770 1771 ptr = (char *)lhdr; 1772 ptr += sizeof(struct dc_leaf_hdr) - 1; 1773 /* 1774 * Look if we got a MII media block. 1775 */ 1776 for (i = 0; i < lhdr->dc_mcnt; i++) { 1777 hdr = (struct dc_eblock_hdr *)ptr; 1778 if (hdr->dc_type == DC_EBLOCK_MII) 1779 have_mii++; 1780 1781 ptr += (hdr->dc_len & 0x7F); 1782 ptr++; 1783 } 1784 1785 /* 1786 * Do the same thing again. Only use SIA and SYM media 1787 * blocks if no MII media block is available. 1788 */ 1789 ptr = (char *)lhdr; 1790 ptr += sizeof(struct dc_leaf_hdr) - 1; 1791 error = 0; 1792 for (i = 0; i < lhdr->dc_mcnt; i++) { 1793 hdr = (struct dc_eblock_hdr *)ptr; 1794 switch (hdr->dc_type) { 1795 case DC_EBLOCK_MII: 1796 error = dc_decode_leaf_mii(sc, (struct dc_eblock_mii *)hdr); 1797 break; 1798 case DC_EBLOCK_SIA: 1799 if (! have_mii) 1800 error = dc_decode_leaf_sia(sc, 1801 (struct dc_eblock_sia *)hdr); 1802 break; 1803 case DC_EBLOCK_SYM: 1804 if (! have_mii) 1805 error = dc_decode_leaf_sym(sc, 1806 (struct dc_eblock_sym *)hdr); 1807 break; 1808 default: 1809 /* Don't care. Yet. */ 1810 break; 1811 } 1812 ptr += (hdr->dc_len & 0x7F); 1813 ptr++; 1814 } 1815 return (error); 1816 } 1817 1818 static void 1819 dc_dma_map_addr(void *arg, bus_dma_segment_t *segs, int nseg, int error) 1820 { 1821 bus_addr_t *paddr; 1822 1823 KASSERT(nseg == 1, 1824 ("%s: wrong number of segments (%d)", __func__, nseg)); 1825 paddr = arg; 1826 *paddr = segs->ds_addr; 1827 } 1828 1829 static int 1830 dc_dma_alloc(struct dc_softc *sc) 1831 { 1832 int error, i; 1833 1834 error = bus_dma_tag_create(bus_get_dma_tag(sc->dc_dev), 1, 0, 1835 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL, 1836 BUS_SPACE_MAXSIZE_32BIT, 0, BUS_SPACE_MAXSIZE_32BIT, 0, 1837 NULL, NULL, &sc->dc_ptag); 1838 if (error) { 1839 device_printf(sc->dc_dev, 1840 "failed to allocate parent DMA tag\n"); 1841 goto fail; 1842 } 1843 1844 /* Allocate a busdma tag and DMA safe memory for TX/RX descriptors. */ 1845 error = bus_dma_tag_create(sc->dc_ptag, DC_LIST_ALIGN, 0, 1846 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL, DC_RX_LIST_SZ, 1, 1847 DC_RX_LIST_SZ, 0, NULL, NULL, &sc->dc_rx_ltag); 1848 if (error) { 1849 device_printf(sc->dc_dev, "failed to create RX list DMA tag\n"); 1850 goto fail; 1851 } 1852 1853 error = bus_dma_tag_create(sc->dc_ptag, DC_LIST_ALIGN, 0, 1854 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL, DC_TX_LIST_SZ, 1, 1855 DC_TX_LIST_SZ, 0, NULL, NULL, &sc->dc_tx_ltag); 1856 if (error) { 1857 device_printf(sc->dc_dev, "failed to create TX list DMA tag\n"); 1858 goto fail; 1859 } 1860 1861 /* RX descriptor list. */ 1862 error = bus_dmamem_alloc(sc->dc_rx_ltag, 1863 (void **)&sc->dc_ldata.dc_rx_list, BUS_DMA_NOWAIT | 1864 BUS_DMA_ZERO | BUS_DMA_COHERENT, &sc->dc_rx_lmap); 1865 if (error) { 1866 device_printf(sc->dc_dev, 1867 "failed to allocate DMA'able memory for RX list\n"); 1868 goto fail; 1869 } 1870 error = bus_dmamap_load(sc->dc_rx_ltag, sc->dc_rx_lmap, 1871 sc->dc_ldata.dc_rx_list, DC_RX_LIST_SZ, dc_dma_map_addr, 1872 &sc->dc_ldata.dc_rx_list_paddr, BUS_DMA_NOWAIT); 1873 if (error) { 1874 device_printf(sc->dc_dev, 1875 "failed to load DMA'able memory for RX list\n"); 1876 goto fail; 1877 } 1878 /* TX descriptor list. */ 1879 error = bus_dmamem_alloc(sc->dc_tx_ltag, 1880 (void **)&sc->dc_ldata.dc_tx_list, BUS_DMA_NOWAIT | 1881 BUS_DMA_ZERO | BUS_DMA_COHERENT, &sc->dc_tx_lmap); 1882 if (error) { 1883 device_printf(sc->dc_dev, 1884 "failed to allocate DMA'able memory for TX list\n"); 1885 goto fail; 1886 } 1887 error = bus_dmamap_load(sc->dc_tx_ltag, sc->dc_tx_lmap, 1888 sc->dc_ldata.dc_tx_list, DC_TX_LIST_SZ, dc_dma_map_addr, 1889 &sc->dc_ldata.dc_tx_list_paddr, BUS_DMA_NOWAIT); 1890 if (error) { 1891 device_printf(sc->dc_dev, 1892 "cannot load DMA'able memory for TX list\n"); 1893 goto fail; 1894 } 1895 1896 /* 1897 * Allocate a busdma tag and DMA safe memory for the multicast 1898 * setup frame. 1899 */ 1900 error = bus_dma_tag_create(sc->dc_ptag, DC_LIST_ALIGN, 0, 1901 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL, 1902 DC_SFRAME_LEN + DC_MIN_FRAMELEN, 1, DC_SFRAME_LEN + DC_MIN_FRAMELEN, 1903 0, NULL, NULL, &sc->dc_stag); 1904 if (error) { 1905 device_printf(sc->dc_dev, 1906 "failed to create DMA tag for setup frame\n"); 1907 goto fail; 1908 } 1909 error = bus_dmamem_alloc(sc->dc_stag, (void **)&sc->dc_cdata.dc_sbuf, 1910 BUS_DMA_NOWAIT, &sc->dc_smap); 1911 if (error) { 1912 device_printf(sc->dc_dev, 1913 "failed to allocate DMA'able memory for setup frame\n"); 1914 goto fail; 1915 } 1916 error = bus_dmamap_load(sc->dc_stag, sc->dc_smap, sc->dc_cdata.dc_sbuf, 1917 DC_SFRAME_LEN, dc_dma_map_addr, &sc->dc_saddr, BUS_DMA_NOWAIT); 1918 if (error) { 1919 device_printf(sc->dc_dev, 1920 "cannot load DMA'able memory for setup frame\n"); 1921 goto fail; 1922 } 1923 1924 /* Allocate a busdma tag for RX mbufs. */ 1925 error = bus_dma_tag_create(sc->dc_ptag, DC_RXBUF_ALIGN, 0, 1926 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL, 1927 MCLBYTES, 1, MCLBYTES, 0, NULL, NULL, &sc->dc_rx_mtag); 1928 if (error) { 1929 device_printf(sc->dc_dev, "failed to create RX mbuf tag\n"); 1930 goto fail; 1931 } 1932 1933 /* Allocate a busdma tag for TX mbufs. */ 1934 error = bus_dma_tag_create(sc->dc_ptag, 1, 0, 1935 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL, 1936 MCLBYTES * DC_MAXFRAGS, DC_MAXFRAGS, MCLBYTES, 1937 0, NULL, NULL, &sc->dc_tx_mtag); 1938 if (error) { 1939 device_printf(sc->dc_dev, "failed to create TX mbuf tag\n"); 1940 goto fail; 1941 } 1942 1943 /* Create the TX/RX busdma maps. */ 1944 for (i = 0; i < DC_TX_LIST_CNT; i++) { 1945 error = bus_dmamap_create(sc->dc_tx_mtag, 0, 1946 &sc->dc_cdata.dc_tx_map[i]); 1947 if (error) { 1948 device_printf(sc->dc_dev, 1949 "failed to create TX mbuf dmamap\n"); 1950 goto fail; 1951 } 1952 } 1953 for (i = 0; i < DC_RX_LIST_CNT; i++) { 1954 error = bus_dmamap_create(sc->dc_rx_mtag, 0, 1955 &sc->dc_cdata.dc_rx_map[i]); 1956 if (error) { 1957 device_printf(sc->dc_dev, 1958 "failed to create RX mbuf dmamap\n"); 1959 goto fail; 1960 } 1961 } 1962 error = bus_dmamap_create(sc->dc_rx_mtag, 0, &sc->dc_sparemap); 1963 if (error) { 1964 device_printf(sc->dc_dev, 1965 "failed to create spare RX mbuf dmamap\n"); 1966 goto fail; 1967 } 1968 1969 fail: 1970 return (error); 1971 } 1972 1973 static void 1974 dc_dma_free(struct dc_softc *sc) 1975 { 1976 int i; 1977 1978 /* RX buffers. */ 1979 if (sc->dc_rx_mtag != NULL) { 1980 for (i = 0; i < DC_RX_LIST_CNT; i++) { 1981 if (sc->dc_cdata.dc_rx_map[i] != NULL) 1982 bus_dmamap_destroy(sc->dc_rx_mtag, 1983 sc->dc_cdata.dc_rx_map[i]); 1984 } 1985 if (sc->dc_sparemap != NULL) 1986 bus_dmamap_destroy(sc->dc_rx_mtag, sc->dc_sparemap); 1987 bus_dma_tag_destroy(sc->dc_rx_mtag); 1988 } 1989 1990 /* TX buffers. */ 1991 if (sc->dc_rx_mtag != NULL) { 1992 for (i = 0; i < DC_TX_LIST_CNT; i++) { 1993 if (sc->dc_cdata.dc_tx_map[i] != NULL) 1994 bus_dmamap_destroy(sc->dc_tx_mtag, 1995 sc->dc_cdata.dc_tx_map[i]); 1996 } 1997 bus_dma_tag_destroy(sc->dc_tx_mtag); 1998 } 1999 2000 /* RX descriptor list. */ 2001 if (sc->dc_rx_ltag) { 2002 if (sc->dc_rx_lmap != NULL) 2003 bus_dmamap_unload(sc->dc_rx_ltag, sc->dc_rx_lmap); 2004 if (sc->dc_rx_lmap != NULL && sc->dc_ldata.dc_rx_list != NULL) 2005 bus_dmamem_free(sc->dc_rx_ltag, sc->dc_ldata.dc_rx_list, 2006 sc->dc_rx_lmap); 2007 bus_dma_tag_destroy(sc->dc_rx_ltag); 2008 } 2009 2010 /* TX descriptor list. */ 2011 if (sc->dc_tx_ltag) { 2012 if (sc->dc_tx_lmap != NULL) 2013 bus_dmamap_unload(sc->dc_tx_ltag, sc->dc_tx_lmap); 2014 if (sc->dc_tx_lmap != NULL && sc->dc_ldata.dc_tx_list != NULL) 2015 bus_dmamem_free(sc->dc_tx_ltag, sc->dc_ldata.dc_tx_list, 2016 sc->dc_tx_lmap); 2017 bus_dma_tag_destroy(sc->dc_tx_ltag); 2018 } 2019 2020 /* multicast setup frame. */ 2021 if (sc->dc_stag) { 2022 if (sc->dc_smap != NULL) 2023 bus_dmamap_unload(sc->dc_stag, sc->dc_smap); 2024 if (sc->dc_smap != NULL && sc->dc_cdata.dc_sbuf != NULL) 2025 bus_dmamem_free(sc->dc_stag, sc->dc_cdata.dc_sbuf, 2026 sc->dc_smap); 2027 bus_dma_tag_destroy(sc->dc_stag); 2028 } 2029 } 2030 2031 /* 2032 * Attach the interface. Allocate softc structures, do ifmedia 2033 * setup and ethernet/BPF attach. 2034 */ 2035 static int 2036 dc_attach(device_t dev) 2037 { 2038 uint32_t eaddr[(ETHER_ADDR_LEN+3)/4]; 2039 uint32_t command; 2040 struct dc_softc *sc; 2041 struct ifnet *ifp; 2042 struct dc_mediainfo *m; 2043 uint32_t reg, revision; 2044 int error, mac_offset, phy, rid, tmp; 2045 uint8_t *mac; 2046 2047 sc = device_get_softc(dev); 2048 sc->dc_dev = dev; 2049 2050 mtx_init(&sc->dc_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 2051 MTX_DEF); 2052 2053 /* 2054 * Map control/status registers. 2055 */ 2056 pci_enable_busmaster(dev); 2057 2058 rid = DC_RID; 2059 sc->dc_res = bus_alloc_resource_any(dev, DC_RES, &rid, RF_ACTIVE); 2060 2061 if (sc->dc_res == NULL) { 2062 device_printf(dev, "couldn't map ports/memory\n"); 2063 error = ENXIO; 2064 goto fail; 2065 } 2066 2067 sc->dc_btag = rman_get_bustag(sc->dc_res); 2068 sc->dc_bhandle = rman_get_bushandle(sc->dc_res); 2069 2070 /* Allocate interrupt. */ 2071 rid = 0; 2072 sc->dc_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 2073 RF_SHAREABLE | RF_ACTIVE); 2074 2075 if (sc->dc_irq == NULL) { 2076 device_printf(dev, "couldn't map interrupt\n"); 2077 error = ENXIO; 2078 goto fail; 2079 } 2080 2081 /* Need this info to decide on a chip type. */ 2082 sc->dc_info = dc_devtype(dev); 2083 revision = pci_get_revid(dev); 2084 2085 error = 0; 2086 /* Get the eeprom width, but PNIC and XIRCOM have diff eeprom */ 2087 if (sc->dc_info->dc_devid != 2088 DC_DEVID(DC_VENDORID_LO, DC_DEVICEID_82C168) && 2089 sc->dc_info->dc_devid != 2090 DC_DEVID(DC_VENDORID_XIRCOM, DC_DEVICEID_X3201)) 2091 dc_eeprom_width(sc); 2092 2093 switch (sc->dc_info->dc_devid) { 2094 case DC_DEVID(DC_VENDORID_DEC, DC_DEVICEID_21143): 2095 sc->dc_type = DC_TYPE_21143; 2096 sc->dc_flags |= DC_TX_POLL | DC_TX_USE_TX_INTR; 2097 sc->dc_flags |= DC_REDUCED_MII_POLL; 2098 /* Save EEPROM contents so we can parse them later. */ 2099 error = dc_read_srom(sc, sc->dc_romwidth); 2100 if (error != 0) 2101 goto fail; 2102 break; 2103 case DC_DEVID(DC_VENDORID_DAVICOM, DC_DEVICEID_DM9009): 2104 case DC_DEVID(DC_VENDORID_DAVICOM, DC_DEVICEID_DM9100): 2105 case DC_DEVID(DC_VENDORID_DAVICOM, DC_DEVICEID_DM9102): 2106 sc->dc_type = DC_TYPE_DM9102; 2107 sc->dc_flags |= DC_TX_COALESCE | DC_TX_INTR_ALWAYS; 2108 sc->dc_flags |= DC_REDUCED_MII_POLL | DC_TX_STORENFWD; 2109 sc->dc_flags |= DC_TX_ALIGN; 2110 sc->dc_pmode = DC_PMODE_MII; 2111 2112 /* Increase the latency timer value. */ 2113 pci_write_config(dev, PCIR_LATTIMER, 0x80, 1); 2114 break; 2115 case DC_DEVID(DC_VENDORID_ADMTEK, DC_DEVICEID_AL981): 2116 sc->dc_type = DC_TYPE_AL981; 2117 sc->dc_flags |= DC_TX_USE_TX_INTR; 2118 sc->dc_flags |= DC_TX_ADMTEK_WAR; 2119 sc->dc_pmode = DC_PMODE_MII; 2120 error = dc_read_srom(sc, sc->dc_romwidth); 2121 if (error != 0) 2122 goto fail; 2123 break; 2124 case DC_DEVID(DC_VENDORID_ADMTEK, DC_DEVICEID_AN983): 2125 case DC_DEVID(DC_VENDORID_ADMTEK, DC_DEVICEID_AN985): 2126 case DC_DEVID(DC_VENDORID_ADMTEK, DC_DEVICEID_ADM9511): 2127 case DC_DEVID(DC_VENDORID_ADMTEK, DC_DEVICEID_ADM9513): 2128 case DC_DEVID(DC_VENDORID_DLINK, DC_DEVICEID_DRP32TXD): 2129 case DC_DEVID(DC_VENDORID_ABOCOM, DC_DEVICEID_FE2500): 2130 case DC_DEVID(DC_VENDORID_ABOCOM, DC_DEVICEID_FE2500MX): 2131 case DC_DEVID(DC_VENDORID_ACCTON, DC_DEVICEID_EN2242): 2132 case DC_DEVID(DC_VENDORID_HAWKING, DC_DEVICEID_HAWKING_PN672TX): 2133 case DC_DEVID(DC_VENDORID_PLANEX, DC_DEVICEID_FNW3602T): 2134 case DC_DEVID(DC_VENDORID_3COM, DC_DEVICEID_3CSOHOB): 2135 case DC_DEVID(DC_VENDORID_MICROSOFT, DC_DEVICEID_MSMN120): 2136 case DC_DEVID(DC_VENDORID_MICROSOFT, DC_DEVICEID_MSMN130): 2137 case DC_DEVID(DC_VENDORID_LINKSYS, DC_DEVICEID_PCMPC200_AB08): 2138 case DC_DEVID(DC_VENDORID_LINKSYS, DC_DEVICEID_PCMPC200_AB09): 2139 sc->dc_type = DC_TYPE_AN983; 2140 sc->dc_flags |= DC_64BIT_HASH; 2141 sc->dc_flags |= DC_TX_USE_TX_INTR; 2142 sc->dc_flags |= DC_TX_ADMTEK_WAR; 2143 sc->dc_pmode = DC_PMODE_MII; 2144 /* Don't read SROM for - auto-loaded on reset */ 2145 break; 2146 case DC_DEVID(DC_VENDORID_MX, DC_DEVICEID_98713): 2147 case DC_DEVID(DC_VENDORID_CP, DC_DEVICEID_98713_CP): 2148 if (revision < DC_REVISION_98713A) { 2149 sc->dc_type = DC_TYPE_98713; 2150 } 2151 if (revision >= DC_REVISION_98713A) { 2152 sc->dc_type = DC_TYPE_98713A; 2153 sc->dc_flags |= DC_21143_NWAY; 2154 } 2155 sc->dc_flags |= DC_REDUCED_MII_POLL; 2156 sc->dc_flags |= DC_TX_POLL | DC_TX_USE_TX_INTR; 2157 break; 2158 case DC_DEVID(DC_VENDORID_MX, DC_DEVICEID_987x5): 2159 case DC_DEVID(DC_VENDORID_ACCTON, DC_DEVICEID_EN1217): 2160 /* 2161 * Macronix MX98715AEC-C/D/E parts have only a 2162 * 128-bit hash table. We need to deal with these 2163 * in the same manner as the PNIC II so that we 2164 * get the right number of bits out of the 2165 * CRC routine. 2166 */ 2167 if (revision >= DC_REVISION_98715AEC_C && 2168 revision < DC_REVISION_98725) 2169 sc->dc_flags |= DC_128BIT_HASH; 2170 sc->dc_type = DC_TYPE_987x5; 2171 sc->dc_flags |= DC_TX_POLL | DC_TX_USE_TX_INTR; 2172 sc->dc_flags |= DC_REDUCED_MII_POLL | DC_21143_NWAY; 2173 break; 2174 case DC_DEVID(DC_VENDORID_MX, DC_DEVICEID_98727): 2175 sc->dc_type = DC_TYPE_987x5; 2176 sc->dc_flags |= DC_TX_POLL | DC_TX_USE_TX_INTR; 2177 sc->dc_flags |= DC_REDUCED_MII_POLL | DC_21143_NWAY; 2178 break; 2179 case DC_DEVID(DC_VENDORID_LO, DC_DEVICEID_82C115): 2180 sc->dc_type = DC_TYPE_PNICII; 2181 sc->dc_flags |= DC_TX_POLL | DC_TX_USE_TX_INTR | DC_128BIT_HASH; 2182 sc->dc_flags |= DC_REDUCED_MII_POLL | DC_21143_NWAY; 2183 break; 2184 case DC_DEVID(DC_VENDORID_LO, DC_DEVICEID_82C168): 2185 sc->dc_type = DC_TYPE_PNIC; 2186 sc->dc_flags |= DC_TX_STORENFWD | DC_TX_INTR_ALWAYS; 2187 sc->dc_flags |= DC_PNIC_RX_BUG_WAR; 2188 sc->dc_pnic_rx_buf = malloc(DC_RXLEN * 5, M_DEVBUF, M_NOWAIT); 2189 if (sc->dc_pnic_rx_buf == NULL) { 2190 device_printf(sc->dc_dev, 2191 "Could not allocate PNIC RX buffer\n"); 2192 error = ENOMEM; 2193 goto fail; 2194 } 2195 if (revision < DC_REVISION_82C169) 2196 sc->dc_pmode = DC_PMODE_SYM; 2197 break; 2198 case DC_DEVID(DC_VENDORID_ASIX, DC_DEVICEID_AX88140A): 2199 sc->dc_type = DC_TYPE_ASIX; 2200 sc->dc_flags |= DC_TX_USE_TX_INTR | DC_TX_INTR_FIRSTFRAG; 2201 sc->dc_flags |= DC_REDUCED_MII_POLL; 2202 sc->dc_pmode = DC_PMODE_MII; 2203 break; 2204 case DC_DEVID(DC_VENDORID_XIRCOM, DC_DEVICEID_X3201): 2205 sc->dc_type = DC_TYPE_XIRCOM; 2206 sc->dc_flags |= DC_TX_INTR_ALWAYS | DC_TX_COALESCE | 2207 DC_TX_ALIGN; 2208 /* 2209 * We don't actually need to coalesce, but we're doing 2210 * it to obtain a double word aligned buffer. 2211 * The DC_TX_COALESCE flag is required. 2212 */ 2213 sc->dc_pmode = DC_PMODE_MII; 2214 break; 2215 case DC_DEVID(DC_VENDORID_CONEXANT, DC_DEVICEID_RS7112): 2216 sc->dc_type = DC_TYPE_CONEXANT; 2217 sc->dc_flags |= DC_TX_INTR_ALWAYS; 2218 sc->dc_flags |= DC_REDUCED_MII_POLL; 2219 sc->dc_pmode = DC_PMODE_MII; 2220 error = dc_read_srom(sc, sc->dc_romwidth); 2221 if (error != 0) 2222 goto fail; 2223 break; 2224 default: 2225 device_printf(dev, "unknown device: %x\n", 2226 sc->dc_info->dc_devid); 2227 break; 2228 } 2229 2230 /* Save the cache line size. */ 2231 if (DC_IS_DAVICOM(sc)) 2232 sc->dc_cachesize = 0; 2233 else 2234 sc->dc_cachesize = pci_get_cachelnsz(dev); 2235 2236 /* Reset the adapter. */ 2237 dc_reset(sc); 2238 2239 /* Take 21143 out of snooze mode */ 2240 if (DC_IS_INTEL(sc) || DC_IS_XIRCOM(sc)) { 2241 command = pci_read_config(dev, DC_PCI_CFDD, 4); 2242 command &= ~(DC_CFDD_SNOOZE_MODE | DC_CFDD_SLEEP_MODE); 2243 pci_write_config(dev, DC_PCI_CFDD, command, 4); 2244 } 2245 2246 /* 2247 * Try to learn something about the supported media. 2248 * We know that ASIX and ADMtek and Davicom devices 2249 * will *always* be using MII media, so that's a no-brainer. 2250 * The tricky ones are the Macronix/PNIC II and the 2251 * Intel 21143. 2252 */ 2253 if (DC_IS_INTEL(sc)) { 2254 error = dc_parse_21143_srom(sc); 2255 if (error != 0) 2256 goto fail; 2257 } else if (DC_IS_MACRONIX(sc) || DC_IS_PNICII(sc)) { 2258 if (sc->dc_type == DC_TYPE_98713) 2259 sc->dc_pmode = DC_PMODE_MII; 2260 else 2261 sc->dc_pmode = DC_PMODE_SYM; 2262 } else if (!sc->dc_pmode) 2263 sc->dc_pmode = DC_PMODE_MII; 2264 2265 /* 2266 * Get station address from the EEPROM. 2267 */ 2268 switch(sc->dc_type) { 2269 case DC_TYPE_98713: 2270 case DC_TYPE_98713A: 2271 case DC_TYPE_987x5: 2272 case DC_TYPE_PNICII: 2273 dc_read_eeprom(sc, (caddr_t)&mac_offset, 2274 (DC_EE_NODEADDR_OFFSET / 2), 1, 0); 2275 dc_read_eeprom(sc, (caddr_t)&eaddr, (mac_offset / 2), 3, 0); 2276 break; 2277 case DC_TYPE_PNIC: 2278 dc_read_eeprom(sc, (caddr_t)&eaddr, 0, 3, 1); 2279 break; 2280 case DC_TYPE_DM9102: 2281 dc_read_eeprom(sc, (caddr_t)&eaddr, DC_EE_NODEADDR, 3, 0); 2282 #ifdef __sparc64__ 2283 /* 2284 * If this is an onboard dc(4) the station address read from 2285 * the EEPROM is all zero and we have to get it from the FCode. 2286 */ 2287 if (eaddr[0] == 0 && (eaddr[1] & ~0xffff) == 0) 2288 OF_getetheraddr(dev, (caddr_t)&eaddr); 2289 #endif 2290 break; 2291 case DC_TYPE_21143: 2292 case DC_TYPE_ASIX: 2293 dc_read_eeprom(sc, (caddr_t)&eaddr, DC_EE_NODEADDR, 3, 0); 2294 break; 2295 case DC_TYPE_AL981: 2296 case DC_TYPE_AN983: 2297 reg = CSR_READ_4(sc, DC_AL_PAR0); 2298 mac = (uint8_t *)&eaddr[0]; 2299 mac[0] = (reg >> 0) & 0xff; 2300 mac[1] = (reg >> 8) & 0xff; 2301 mac[2] = (reg >> 16) & 0xff; 2302 mac[3] = (reg >> 24) & 0xff; 2303 reg = CSR_READ_4(sc, DC_AL_PAR1); 2304 mac[4] = (reg >> 0) & 0xff; 2305 mac[5] = (reg >> 8) & 0xff; 2306 break; 2307 case DC_TYPE_CONEXANT: 2308 bcopy(sc->dc_srom + DC_CONEXANT_EE_NODEADDR, &eaddr, 2309 ETHER_ADDR_LEN); 2310 break; 2311 case DC_TYPE_XIRCOM: 2312 /* The MAC comes from the CIS. */ 2313 mac = pci_get_ether(dev); 2314 if (!mac) { 2315 device_printf(dev, "No station address in CIS!\n"); 2316 error = ENXIO; 2317 goto fail; 2318 } 2319 bcopy(mac, eaddr, ETHER_ADDR_LEN); 2320 break; 2321 default: 2322 dc_read_eeprom(sc, (caddr_t)&eaddr, DC_EE_NODEADDR, 3, 0); 2323 break; 2324 } 2325 2326 bcopy(eaddr, sc->dc_eaddr, sizeof(eaddr)); 2327 /* 2328 * If we still have invalid station address, see whether we can 2329 * find station address for chip 0. Some multi-port controllers 2330 * just store station address for chip 0 if they have a shared 2331 * SROM. 2332 */ 2333 if ((sc->dc_eaddr[0] == 0 && (sc->dc_eaddr[1] & ~0xffff) == 0) || 2334 (sc->dc_eaddr[0] == 0xffffffff && 2335 (sc->dc_eaddr[1] & 0xffff) == 0xffff)) { 2336 error = dc_check_multiport(sc); 2337 if (error == 0) { 2338 bcopy(sc->dc_eaddr, eaddr, sizeof(eaddr)); 2339 /* Extract media information. */ 2340 if (DC_IS_INTEL(sc) && sc->dc_srom != NULL) { 2341 while (sc->dc_mi != NULL) { 2342 m = sc->dc_mi->dc_next; 2343 free(sc->dc_mi, M_DEVBUF); 2344 sc->dc_mi = m; 2345 } 2346 error = dc_parse_21143_srom(sc); 2347 if (error != 0) 2348 goto fail; 2349 } 2350 } else if (error == ENOMEM) 2351 goto fail; 2352 else 2353 error = 0; 2354 } 2355 2356 if ((error = dc_dma_alloc(sc)) != 0) 2357 goto fail; 2358 2359 ifp = sc->dc_ifp = if_alloc(IFT_ETHER); 2360 if (ifp == NULL) { 2361 device_printf(dev, "can not if_alloc()\n"); 2362 error = ENOSPC; 2363 goto fail; 2364 } 2365 ifp->if_softc = sc; 2366 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 2367 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 2368 ifp->if_ioctl = dc_ioctl; 2369 ifp->if_start = dc_start; 2370 ifp->if_init = dc_init; 2371 IFQ_SET_MAXLEN(&ifp->if_snd, DC_TX_LIST_CNT - 1); 2372 ifp->if_snd.ifq_drv_maxlen = DC_TX_LIST_CNT - 1; 2373 IFQ_SET_READY(&ifp->if_snd); 2374 2375 /* 2376 * Do MII setup. If this is a 21143, check for a PHY on the 2377 * MII bus after applying any necessary fixups to twiddle the 2378 * GPIO bits. If we don't end up finding a PHY, restore the 2379 * old selection (SIA only or SIA/SYM) and attach the dcphy 2380 * driver instead. 2381 */ 2382 tmp = 0; 2383 if (DC_IS_INTEL(sc)) { 2384 dc_apply_fixup(sc, IFM_AUTO); 2385 tmp = sc->dc_pmode; 2386 sc->dc_pmode = DC_PMODE_MII; 2387 } 2388 2389 /* 2390 * Setup General Purpose port mode and data so the tulip can talk 2391 * to the MII. This needs to be done before mii_attach so that 2392 * we can actually see them. 2393 */ 2394 if (DC_IS_XIRCOM(sc)) { 2395 CSR_WRITE_4(sc, DC_SIAGP, DC_SIAGP_WRITE_EN | DC_SIAGP_INT1_EN | 2396 DC_SIAGP_MD_GP2_OUTPUT | DC_SIAGP_MD_GP0_OUTPUT); 2397 DELAY(10); 2398 CSR_WRITE_4(sc, DC_SIAGP, DC_SIAGP_INT1_EN | 2399 DC_SIAGP_MD_GP2_OUTPUT | DC_SIAGP_MD_GP0_OUTPUT); 2400 DELAY(10); 2401 } 2402 2403 phy = MII_PHY_ANY; 2404 /* 2405 * Note: both the AL981 and AN983 have internal PHYs, however the 2406 * AL981 provides direct access to the PHY registers while the AN983 2407 * uses a serial MII interface. The AN983's MII interface is also 2408 * buggy in that you can read from any MII address (0 to 31), but 2409 * only address 1 behaves normally. To deal with both cases, we 2410 * pretend that the PHY is at MII address 1. 2411 */ 2412 if (DC_IS_ADMTEK(sc)) 2413 phy = DC_ADMTEK_PHYADDR; 2414 2415 /* 2416 * Note: the ukphy probes of the RS7112 report a PHY at MII address 2417 * 0 (possibly HomePNA?) and 1 (ethernet) so we only respond to the 2418 * correct one. 2419 */ 2420 if (DC_IS_CONEXANT(sc)) 2421 phy = DC_CONEXANT_PHYADDR; 2422 2423 error = mii_attach(dev, &sc->dc_miibus, ifp, dc_ifmedia_upd, 2424 dc_ifmedia_sts, BMSR_DEFCAPMASK, phy, MII_OFFSET_ANY, 0); 2425 2426 if (error && DC_IS_INTEL(sc)) { 2427 sc->dc_pmode = tmp; 2428 if (sc->dc_pmode != DC_PMODE_SIA) 2429 sc->dc_pmode = DC_PMODE_SYM; 2430 sc->dc_flags |= DC_21143_NWAY; 2431 mii_attach(dev, &sc->dc_miibus, ifp, dc_ifmedia_upd, 2432 dc_ifmedia_sts, BMSR_DEFCAPMASK, MII_PHY_ANY, 2433 MII_OFFSET_ANY, 0); 2434 /* 2435 * For non-MII cards, we need to have the 21143 2436 * drive the LEDs. Except there are some systems 2437 * like the NEC VersaPro NoteBook PC which have no 2438 * LEDs, and twiddling these bits has adverse effects 2439 * on them. (I.e. you suddenly can't get a link.) 2440 */ 2441 if (!(pci_get_subvendor(dev) == 0x1033 && 2442 pci_get_subdevice(dev) == 0x8028)) 2443 sc->dc_flags |= DC_TULIP_LEDS; 2444 error = 0; 2445 } 2446 2447 if (error) { 2448 device_printf(dev, "attaching PHYs failed\n"); 2449 goto fail; 2450 } 2451 2452 if (DC_IS_ADMTEK(sc)) { 2453 /* 2454 * Set automatic TX underrun recovery for the ADMtek chips 2455 */ 2456 DC_SETBIT(sc, DC_AL_CR, DC_AL_CR_ATUR); 2457 } 2458 2459 /* 2460 * Tell the upper layer(s) we support long frames. 2461 */ 2462 ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header); 2463 ifp->if_capabilities |= IFCAP_VLAN_MTU; 2464 ifp->if_capenable = ifp->if_capabilities; 2465 #ifdef DEVICE_POLLING 2466 ifp->if_capabilities |= IFCAP_POLLING; 2467 #endif 2468 2469 callout_init_mtx(&sc->dc_stat_ch, &sc->dc_mtx, 0); 2470 callout_init_mtx(&sc->dc_wdog_ch, &sc->dc_mtx, 0); 2471 2472 /* 2473 * Call MI attach routine. 2474 */ 2475 ether_ifattach(ifp, (caddr_t)eaddr); 2476 2477 /* Hook interrupt last to avoid having to lock softc */ 2478 error = bus_setup_intr(dev, sc->dc_irq, INTR_TYPE_NET | INTR_MPSAFE, 2479 NULL, dc_intr, sc, &sc->dc_intrhand); 2480 2481 if (error) { 2482 device_printf(dev, "couldn't set up irq\n"); 2483 ether_ifdetach(ifp); 2484 goto fail; 2485 } 2486 2487 fail: 2488 if (error) 2489 dc_detach(dev); 2490 return (error); 2491 } 2492 2493 /* 2494 * Shutdown hardware and free up resources. This can be called any 2495 * time after the mutex has been initialized. It is called in both 2496 * the error case in attach and the normal detach case so it needs 2497 * to be careful about only freeing resources that have actually been 2498 * allocated. 2499 */ 2500 static int 2501 dc_detach(device_t dev) 2502 { 2503 struct dc_softc *sc; 2504 struct ifnet *ifp; 2505 struct dc_mediainfo *m; 2506 2507 sc = device_get_softc(dev); 2508 KASSERT(mtx_initialized(&sc->dc_mtx), ("dc mutex not initialized")); 2509 2510 ifp = sc->dc_ifp; 2511 2512 #ifdef DEVICE_POLLING 2513 if (ifp->if_capenable & IFCAP_POLLING) 2514 ether_poll_deregister(ifp); 2515 #endif 2516 2517 /* These should only be active if attach succeeded */ 2518 if (device_is_attached(dev)) { 2519 DC_LOCK(sc); 2520 dc_stop(sc); 2521 DC_UNLOCK(sc); 2522 callout_drain(&sc->dc_stat_ch); 2523 callout_drain(&sc->dc_wdog_ch); 2524 ether_ifdetach(ifp); 2525 } 2526 if (sc->dc_miibus) 2527 device_delete_child(dev, sc->dc_miibus); 2528 bus_generic_detach(dev); 2529 2530 if (sc->dc_intrhand) 2531 bus_teardown_intr(dev, sc->dc_irq, sc->dc_intrhand); 2532 if (sc->dc_irq) 2533 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->dc_irq); 2534 if (sc->dc_res) 2535 bus_release_resource(dev, DC_RES, DC_RID, sc->dc_res); 2536 2537 if (ifp) 2538 if_free(ifp); 2539 2540 dc_dma_free(sc); 2541 2542 free(sc->dc_pnic_rx_buf, M_DEVBUF); 2543 2544 while (sc->dc_mi != NULL) { 2545 m = sc->dc_mi->dc_next; 2546 free(sc->dc_mi, M_DEVBUF); 2547 sc->dc_mi = m; 2548 } 2549 free(sc->dc_srom, M_DEVBUF); 2550 2551 mtx_destroy(&sc->dc_mtx); 2552 2553 return (0); 2554 } 2555 2556 /* 2557 * Initialize the transmit descriptors. 2558 */ 2559 static int 2560 dc_list_tx_init(struct dc_softc *sc) 2561 { 2562 struct dc_chain_data *cd; 2563 struct dc_list_data *ld; 2564 int i, nexti; 2565 2566 cd = &sc->dc_cdata; 2567 ld = &sc->dc_ldata; 2568 for (i = 0; i < DC_TX_LIST_CNT; i++) { 2569 if (i == DC_TX_LIST_CNT - 1) 2570 nexti = 0; 2571 else 2572 nexti = i + 1; 2573 ld->dc_tx_list[i].dc_status = 0; 2574 ld->dc_tx_list[i].dc_ctl = 0; 2575 ld->dc_tx_list[i].dc_data = 0; 2576 ld->dc_tx_list[i].dc_next = htole32(DC_TXDESC(sc, nexti)); 2577 cd->dc_tx_chain[i] = NULL; 2578 } 2579 2580 cd->dc_tx_prod = cd->dc_tx_cons = cd->dc_tx_cnt = 0; 2581 cd->dc_tx_pkts = 0; 2582 bus_dmamap_sync(sc->dc_tx_ltag, sc->dc_tx_lmap, 2583 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2584 return (0); 2585 } 2586 2587 2588 /* 2589 * Initialize the RX descriptors and allocate mbufs for them. Note that 2590 * we arrange the descriptors in a closed ring, so that the last descriptor 2591 * points back to the first. 2592 */ 2593 static int 2594 dc_list_rx_init(struct dc_softc *sc) 2595 { 2596 struct dc_chain_data *cd; 2597 struct dc_list_data *ld; 2598 int i, nexti; 2599 2600 cd = &sc->dc_cdata; 2601 ld = &sc->dc_ldata; 2602 2603 for (i = 0; i < DC_RX_LIST_CNT; i++) { 2604 if (dc_newbuf(sc, i) != 0) 2605 return (ENOBUFS); 2606 if (i == DC_RX_LIST_CNT - 1) 2607 nexti = 0; 2608 else 2609 nexti = i + 1; 2610 ld->dc_rx_list[i].dc_next = htole32(DC_RXDESC(sc, nexti)); 2611 } 2612 2613 cd->dc_rx_prod = 0; 2614 bus_dmamap_sync(sc->dc_rx_ltag, sc->dc_rx_lmap, 2615 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2616 return (0); 2617 } 2618 2619 /* 2620 * Initialize an RX descriptor and attach an MBUF cluster. 2621 */ 2622 static int 2623 dc_newbuf(struct dc_softc *sc, int i) 2624 { 2625 struct mbuf *m; 2626 bus_dmamap_t map; 2627 bus_dma_segment_t segs[1]; 2628 int error, nseg; 2629 2630 m = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR); 2631 if (m == NULL) 2632 return (ENOBUFS); 2633 m->m_len = m->m_pkthdr.len = MCLBYTES; 2634 m_adj(m, sizeof(u_int64_t)); 2635 2636 /* 2637 * If this is a PNIC chip, zero the buffer. This is part 2638 * of the workaround for the receive bug in the 82c168 and 2639 * 82c169 chips. 2640 */ 2641 if (sc->dc_flags & DC_PNIC_RX_BUG_WAR) 2642 bzero(mtod(m, char *), m->m_len); 2643 2644 error = bus_dmamap_load_mbuf_sg(sc->dc_rx_mtag, sc->dc_sparemap, 2645 m, segs, &nseg, 0); 2646 if (error) { 2647 m_freem(m); 2648 return (error); 2649 } 2650 KASSERT(nseg == 1, ("%s: wrong number of segments (%d)", __func__, 2651 nseg)); 2652 if (sc->dc_cdata.dc_rx_chain[i] != NULL) 2653 bus_dmamap_unload(sc->dc_rx_mtag, sc->dc_cdata.dc_rx_map[i]); 2654 2655 map = sc->dc_cdata.dc_rx_map[i]; 2656 sc->dc_cdata.dc_rx_map[i] = sc->dc_sparemap; 2657 sc->dc_sparemap = map; 2658 sc->dc_cdata.dc_rx_chain[i] = m; 2659 bus_dmamap_sync(sc->dc_rx_mtag, sc->dc_cdata.dc_rx_map[i], 2660 BUS_DMASYNC_PREREAD); 2661 2662 sc->dc_ldata.dc_rx_list[i].dc_ctl = htole32(DC_RXCTL_RLINK | DC_RXLEN); 2663 sc->dc_ldata.dc_rx_list[i].dc_data = 2664 htole32(DC_ADDR_LO(segs[0].ds_addr)); 2665 sc->dc_ldata.dc_rx_list[i].dc_status = htole32(DC_RXSTAT_OWN); 2666 bus_dmamap_sync(sc->dc_rx_ltag, sc->dc_rx_lmap, 2667 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2668 return (0); 2669 } 2670 2671 /* 2672 * Grrrrr. 2673 * The PNIC chip has a terrible bug in it that manifests itself during 2674 * periods of heavy activity. The exact mode of failure if difficult to 2675 * pinpoint: sometimes it only happens in promiscuous mode, sometimes it 2676 * will happen on slow machines. The bug is that sometimes instead of 2677 * uploading one complete frame during reception, it uploads what looks 2678 * like the entire contents of its FIFO memory. The frame we want is at 2679 * the end of the whole mess, but we never know exactly how much data has 2680 * been uploaded, so salvaging the frame is hard. 2681 * 2682 * There is only one way to do it reliably, and it's disgusting. 2683 * Here's what we know: 2684 * 2685 * - We know there will always be somewhere between one and three extra 2686 * descriptors uploaded. 2687 * 2688 * - We know the desired received frame will always be at the end of the 2689 * total data upload. 2690 * 2691 * - We know the size of the desired received frame because it will be 2692 * provided in the length field of the status word in the last descriptor. 2693 * 2694 * Here's what we do: 2695 * 2696 * - When we allocate buffers for the receive ring, we bzero() them. 2697 * This means that we know that the buffer contents should be all 2698 * zeros, except for data uploaded by the chip. 2699 * 2700 * - We also force the PNIC chip to upload frames that include the 2701 * ethernet CRC at the end. 2702 * 2703 * - We gather all of the bogus frame data into a single buffer. 2704 * 2705 * - We then position a pointer at the end of this buffer and scan 2706 * backwards until we encounter the first non-zero byte of data. 2707 * This is the end of the received frame. We know we will encounter 2708 * some data at the end of the frame because the CRC will always be 2709 * there, so even if the sender transmits a packet of all zeros, 2710 * we won't be fooled. 2711 * 2712 * - We know the size of the actual received frame, so we subtract 2713 * that value from the current pointer location. This brings us 2714 * to the start of the actual received packet. 2715 * 2716 * - We copy this into an mbuf and pass it on, along with the actual 2717 * frame length. 2718 * 2719 * The performance hit is tremendous, but it beats dropping frames all 2720 * the time. 2721 */ 2722 2723 #define DC_WHOLEFRAME (DC_RXSTAT_FIRSTFRAG | DC_RXSTAT_LASTFRAG) 2724 static void 2725 dc_pnic_rx_bug_war(struct dc_softc *sc, int idx) 2726 { 2727 struct dc_desc *cur_rx; 2728 struct dc_desc *c = NULL; 2729 struct mbuf *m = NULL; 2730 unsigned char *ptr; 2731 int i, total_len; 2732 uint32_t rxstat = 0; 2733 2734 i = sc->dc_pnic_rx_bug_save; 2735 cur_rx = &sc->dc_ldata.dc_rx_list[idx]; 2736 ptr = sc->dc_pnic_rx_buf; 2737 bzero(ptr, DC_RXLEN * 5); 2738 2739 /* Copy all the bytes from the bogus buffers. */ 2740 while (1) { 2741 c = &sc->dc_ldata.dc_rx_list[i]; 2742 rxstat = le32toh(c->dc_status); 2743 m = sc->dc_cdata.dc_rx_chain[i]; 2744 bcopy(mtod(m, char *), ptr, DC_RXLEN); 2745 ptr += DC_RXLEN; 2746 /* If this is the last buffer, break out. */ 2747 if (i == idx || rxstat & DC_RXSTAT_LASTFRAG) 2748 break; 2749 dc_discard_rxbuf(sc, i); 2750 DC_INC(i, DC_RX_LIST_CNT); 2751 } 2752 2753 /* Find the length of the actual receive frame. */ 2754 total_len = DC_RXBYTES(rxstat); 2755 2756 /* Scan backwards until we hit a non-zero byte. */ 2757 while (*ptr == 0x00) 2758 ptr--; 2759 2760 /* Round off. */ 2761 if ((uintptr_t)(ptr) & 0x3) 2762 ptr -= 1; 2763 2764 /* Now find the start of the frame. */ 2765 ptr -= total_len; 2766 if (ptr < sc->dc_pnic_rx_buf) 2767 ptr = sc->dc_pnic_rx_buf; 2768 2769 /* 2770 * Now copy the salvaged frame to the last mbuf and fake up 2771 * the status word to make it look like a successful 2772 * frame reception. 2773 */ 2774 bcopy(ptr, mtod(m, char *), total_len); 2775 cur_rx->dc_status = htole32(rxstat | DC_RXSTAT_FIRSTFRAG); 2776 } 2777 2778 /* 2779 * This routine searches the RX ring for dirty descriptors in the 2780 * event that the rxeof routine falls out of sync with the chip's 2781 * current descriptor pointer. This may happen sometimes as a result 2782 * of a "no RX buffer available" condition that happens when the chip 2783 * consumes all of the RX buffers before the driver has a chance to 2784 * process the RX ring. This routine may need to be called more than 2785 * once to bring the driver back in sync with the chip, however we 2786 * should still be getting RX DONE interrupts to drive the search 2787 * for new packets in the RX ring, so we should catch up eventually. 2788 */ 2789 static int 2790 dc_rx_resync(struct dc_softc *sc) 2791 { 2792 struct dc_desc *cur_rx; 2793 int i, pos; 2794 2795 pos = sc->dc_cdata.dc_rx_prod; 2796 2797 for (i = 0; i < DC_RX_LIST_CNT; i++) { 2798 cur_rx = &sc->dc_ldata.dc_rx_list[pos]; 2799 if (!(le32toh(cur_rx->dc_status) & DC_RXSTAT_OWN)) 2800 break; 2801 DC_INC(pos, DC_RX_LIST_CNT); 2802 } 2803 2804 /* If the ring really is empty, then just return. */ 2805 if (i == DC_RX_LIST_CNT) 2806 return (0); 2807 2808 /* We've fallen behing the chip: catch it. */ 2809 sc->dc_cdata.dc_rx_prod = pos; 2810 2811 return (EAGAIN); 2812 } 2813 2814 static void 2815 dc_discard_rxbuf(struct dc_softc *sc, int i) 2816 { 2817 struct mbuf *m; 2818 2819 if (sc->dc_flags & DC_PNIC_RX_BUG_WAR) { 2820 m = sc->dc_cdata.dc_rx_chain[i]; 2821 bzero(mtod(m, char *), m->m_len); 2822 } 2823 2824 sc->dc_ldata.dc_rx_list[i].dc_ctl = htole32(DC_RXCTL_RLINK | DC_RXLEN); 2825 sc->dc_ldata.dc_rx_list[i].dc_status = htole32(DC_RXSTAT_OWN); 2826 bus_dmamap_sync(sc->dc_rx_ltag, sc->dc_rx_lmap, BUS_DMASYNC_PREREAD | 2827 BUS_DMASYNC_PREWRITE); 2828 } 2829 2830 /* 2831 * A frame has been uploaded: pass the resulting mbuf chain up to 2832 * the higher level protocols. 2833 */ 2834 static int 2835 dc_rxeof(struct dc_softc *sc) 2836 { 2837 struct mbuf *m; 2838 struct ifnet *ifp; 2839 struct dc_desc *cur_rx; 2840 int i, total_len, rx_npkts; 2841 uint32_t rxstat; 2842 2843 DC_LOCK_ASSERT(sc); 2844 2845 ifp = sc->dc_ifp; 2846 rx_npkts = 0; 2847 2848 bus_dmamap_sync(sc->dc_rx_ltag, sc->dc_rx_lmap, BUS_DMASYNC_POSTREAD | 2849 BUS_DMASYNC_POSTWRITE); 2850 for (i = sc->dc_cdata.dc_rx_prod; 2851 (ifp->if_drv_flags & IFF_DRV_RUNNING) != 0; 2852 DC_INC(i, DC_RX_LIST_CNT)) { 2853 #ifdef DEVICE_POLLING 2854 if (ifp->if_capenable & IFCAP_POLLING) { 2855 if (sc->rxcycles <= 0) 2856 break; 2857 sc->rxcycles--; 2858 } 2859 #endif 2860 cur_rx = &sc->dc_ldata.dc_rx_list[i]; 2861 rxstat = le32toh(cur_rx->dc_status); 2862 if ((rxstat & DC_RXSTAT_OWN) != 0) 2863 break; 2864 m = sc->dc_cdata.dc_rx_chain[i]; 2865 bus_dmamap_sync(sc->dc_rx_mtag, sc->dc_cdata.dc_rx_map[i], 2866 BUS_DMASYNC_POSTREAD); 2867 total_len = DC_RXBYTES(rxstat); 2868 rx_npkts++; 2869 2870 if (sc->dc_flags & DC_PNIC_RX_BUG_WAR) { 2871 if ((rxstat & DC_WHOLEFRAME) != DC_WHOLEFRAME) { 2872 if (rxstat & DC_RXSTAT_FIRSTFRAG) 2873 sc->dc_pnic_rx_bug_save = i; 2874 if ((rxstat & DC_RXSTAT_LASTFRAG) == 0) 2875 continue; 2876 dc_pnic_rx_bug_war(sc, i); 2877 rxstat = le32toh(cur_rx->dc_status); 2878 total_len = DC_RXBYTES(rxstat); 2879 } 2880 } 2881 2882 /* 2883 * If an error occurs, update stats, clear the 2884 * status word and leave the mbuf cluster in place: 2885 * it should simply get re-used next time this descriptor 2886 * comes up in the ring. However, don't report long 2887 * frames as errors since they could be vlans. 2888 */ 2889 if ((rxstat & DC_RXSTAT_RXERR)) { 2890 if (!(rxstat & DC_RXSTAT_GIANT) || 2891 (rxstat & (DC_RXSTAT_CRCERR | DC_RXSTAT_DRIBBLE | 2892 DC_RXSTAT_MIIERE | DC_RXSTAT_COLLSEEN | 2893 DC_RXSTAT_RUNT | DC_RXSTAT_DE))) { 2894 ifp->if_ierrors++; 2895 if (rxstat & DC_RXSTAT_COLLSEEN) 2896 ifp->if_collisions++; 2897 dc_discard_rxbuf(sc, i); 2898 if (rxstat & DC_RXSTAT_CRCERR) 2899 continue; 2900 else { 2901 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 2902 dc_init_locked(sc); 2903 return (rx_npkts); 2904 } 2905 } 2906 } 2907 2908 /* No errors; receive the packet. */ 2909 total_len -= ETHER_CRC_LEN; 2910 #ifdef __NO_STRICT_ALIGNMENT 2911 /* 2912 * On architectures without alignment problems we try to 2913 * allocate a new buffer for the receive ring, and pass up 2914 * the one where the packet is already, saving the expensive 2915 * copy done in m_devget(). 2916 * If we are on an architecture with alignment problems, or 2917 * if the allocation fails, then use m_devget and leave the 2918 * existing buffer in the receive ring. 2919 */ 2920 if (dc_newbuf(sc, i) != 0) { 2921 dc_discard_rxbuf(sc, i); 2922 ifp->if_iqdrops++; 2923 continue; 2924 } 2925 m->m_pkthdr.rcvif = ifp; 2926 m->m_pkthdr.len = m->m_len = total_len; 2927 #else 2928 { 2929 struct mbuf *m0; 2930 2931 m0 = m_devget(mtod(m, char *), total_len, 2932 ETHER_ALIGN, ifp, NULL); 2933 dc_discard_rxbuf(sc, i); 2934 if (m0 == NULL) { 2935 ifp->if_iqdrops++; 2936 continue; 2937 } 2938 m = m0; 2939 } 2940 #endif 2941 2942 ifp->if_ipackets++; 2943 DC_UNLOCK(sc); 2944 (*ifp->if_input)(ifp, m); 2945 DC_LOCK(sc); 2946 } 2947 2948 sc->dc_cdata.dc_rx_prod = i; 2949 return (rx_npkts); 2950 } 2951 2952 /* 2953 * A frame was downloaded to the chip. It's safe for us to clean up 2954 * the list buffers. 2955 */ 2956 static void 2957 dc_txeof(struct dc_softc *sc) 2958 { 2959 struct dc_desc *cur_tx; 2960 struct ifnet *ifp; 2961 int idx, setup; 2962 uint32_t ctl, txstat; 2963 2964 if (sc->dc_cdata.dc_tx_cnt == 0) 2965 return; 2966 2967 ifp = sc->dc_ifp; 2968 2969 /* 2970 * Go through our tx list and free mbufs for those 2971 * frames that have been transmitted. 2972 */ 2973 bus_dmamap_sync(sc->dc_rx_ltag, sc->dc_tx_lmap, BUS_DMASYNC_POSTREAD | 2974 BUS_DMASYNC_POSTWRITE); 2975 setup = 0; 2976 for (idx = sc->dc_cdata.dc_tx_cons; idx != sc->dc_cdata.dc_tx_prod; 2977 DC_INC(idx, DC_TX_LIST_CNT), sc->dc_cdata.dc_tx_cnt--) { 2978 cur_tx = &sc->dc_ldata.dc_tx_list[idx]; 2979 txstat = le32toh(cur_tx->dc_status); 2980 ctl = le32toh(cur_tx->dc_ctl); 2981 2982 if (txstat & DC_TXSTAT_OWN) 2983 break; 2984 2985 if (sc->dc_cdata.dc_tx_chain[idx] == NULL) 2986 continue; 2987 2988 if (ctl & DC_TXCTL_SETUP) { 2989 cur_tx->dc_ctl = htole32(ctl & ~DC_TXCTL_SETUP); 2990 setup++; 2991 bus_dmamap_sync(sc->dc_stag, sc->dc_smap, 2992 BUS_DMASYNC_POSTWRITE); 2993 /* 2994 * Yes, the PNIC is so brain damaged 2995 * that it will sometimes generate a TX 2996 * underrun error while DMAing the RX 2997 * filter setup frame. If we detect this, 2998 * we have to send the setup frame again, 2999 * or else the filter won't be programmed 3000 * correctly. 3001 */ 3002 if (DC_IS_PNIC(sc)) { 3003 if (txstat & DC_TXSTAT_ERRSUM) 3004 dc_setfilt(sc); 3005 } 3006 sc->dc_cdata.dc_tx_chain[idx] = NULL; 3007 continue; 3008 } 3009 3010 if (DC_IS_XIRCOM(sc) || DC_IS_CONEXANT(sc)) { 3011 /* 3012 * XXX: Why does my Xircom taunt me so? 3013 * For some reason it likes setting the CARRLOST flag 3014 * even when the carrier is there. wtf?!? 3015 * Who knows, but Conexant chips have the 3016 * same problem. Maybe they took lessons 3017 * from Xircom. 3018 */ 3019 if (/*sc->dc_type == DC_TYPE_21143 &&*/ 3020 sc->dc_pmode == DC_PMODE_MII && 3021 ((txstat & 0xFFFF) & ~(DC_TXSTAT_ERRSUM | 3022 DC_TXSTAT_NOCARRIER))) 3023 txstat &= ~DC_TXSTAT_ERRSUM; 3024 } else { 3025 if (/*sc->dc_type == DC_TYPE_21143 &&*/ 3026 sc->dc_pmode == DC_PMODE_MII && 3027 ((txstat & 0xFFFF) & ~(DC_TXSTAT_ERRSUM | 3028 DC_TXSTAT_NOCARRIER | DC_TXSTAT_CARRLOST))) 3029 txstat &= ~DC_TXSTAT_ERRSUM; 3030 } 3031 3032 if (txstat & DC_TXSTAT_ERRSUM) { 3033 ifp->if_oerrors++; 3034 if (txstat & DC_TXSTAT_EXCESSCOLL) 3035 ifp->if_collisions++; 3036 if (txstat & DC_TXSTAT_LATECOLL) 3037 ifp->if_collisions++; 3038 if (!(txstat & DC_TXSTAT_UNDERRUN)) { 3039 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 3040 dc_init_locked(sc); 3041 return; 3042 } 3043 } else 3044 ifp->if_opackets++; 3045 ifp->if_collisions += (txstat & DC_TXSTAT_COLLCNT) >> 3; 3046 3047 bus_dmamap_sync(sc->dc_tx_mtag, sc->dc_cdata.dc_tx_map[idx], 3048 BUS_DMASYNC_POSTWRITE); 3049 bus_dmamap_unload(sc->dc_tx_mtag, sc->dc_cdata.dc_tx_map[idx]); 3050 m_freem(sc->dc_cdata.dc_tx_chain[idx]); 3051 sc->dc_cdata.dc_tx_chain[idx] = NULL; 3052 } 3053 sc->dc_cdata.dc_tx_cons = idx; 3054 3055 if (sc->dc_cdata.dc_tx_cnt <= DC_TX_LIST_CNT - DC_TX_LIST_RSVD) { 3056 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 3057 if (sc->dc_cdata.dc_tx_cnt == 0) 3058 sc->dc_wdog_timer = 0; 3059 } 3060 if (setup > 0) 3061 bus_dmamap_sync(sc->dc_tx_ltag, sc->dc_tx_lmap, 3062 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 3063 } 3064 3065 static void 3066 dc_tick(void *xsc) 3067 { 3068 struct dc_softc *sc; 3069 struct mii_data *mii; 3070 struct ifnet *ifp; 3071 uint32_t r; 3072 3073 sc = xsc; 3074 DC_LOCK_ASSERT(sc); 3075 ifp = sc->dc_ifp; 3076 mii = device_get_softc(sc->dc_miibus); 3077 3078 /* 3079 * Reclaim transmitted frames for controllers that do 3080 * not generate TX completion interrupt for every frame. 3081 */ 3082 if (sc->dc_flags & DC_TX_USE_TX_INTR) 3083 dc_txeof(sc); 3084 3085 if (sc->dc_flags & DC_REDUCED_MII_POLL) { 3086 if (sc->dc_flags & DC_21143_NWAY) { 3087 r = CSR_READ_4(sc, DC_10BTSTAT); 3088 if (IFM_SUBTYPE(mii->mii_media_active) == 3089 IFM_100_TX && (r & DC_TSTAT_LS100)) { 3090 sc->dc_link = 0; 3091 mii_mediachg(mii); 3092 } 3093 if (IFM_SUBTYPE(mii->mii_media_active) == 3094 IFM_10_T && (r & DC_TSTAT_LS10)) { 3095 sc->dc_link = 0; 3096 mii_mediachg(mii); 3097 } 3098 if (sc->dc_link == 0) 3099 mii_tick(mii); 3100 } else { 3101 /* 3102 * For NICs which never report DC_RXSTATE_WAIT, we 3103 * have to bite the bullet... 3104 */ 3105 if ((DC_HAS_BROKEN_RXSTATE(sc) || (CSR_READ_4(sc, 3106 DC_ISR) & DC_ISR_RX_STATE) == DC_RXSTATE_WAIT) && 3107 sc->dc_cdata.dc_tx_cnt == 0) 3108 mii_tick(mii); 3109 } 3110 } else 3111 mii_tick(mii); 3112 3113 /* 3114 * When the init routine completes, we expect to be able to send 3115 * packets right away, and in fact the network code will send a 3116 * gratuitous ARP the moment the init routine marks the interface 3117 * as running. However, even though the MAC may have been initialized, 3118 * there may be a delay of a few seconds before the PHY completes 3119 * autonegotiation and the link is brought up. Any transmissions 3120 * made during that delay will be lost. Dealing with this is tricky: 3121 * we can't just pause in the init routine while waiting for the 3122 * PHY to come ready since that would bring the whole system to 3123 * a screeching halt for several seconds. 3124 * 3125 * What we do here is prevent the TX start routine from sending 3126 * any packets until a link has been established. After the 3127 * interface has been initialized, the tick routine will poll 3128 * the state of the PHY until the IFM_ACTIVE flag is set. Until 3129 * that time, packets will stay in the send queue, and once the 3130 * link comes up, they will be flushed out to the wire. 3131 */ 3132 if (sc->dc_link != 0 && !IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 3133 dc_start_locked(ifp); 3134 3135 if (sc->dc_flags & DC_21143_NWAY && !sc->dc_link) 3136 callout_reset(&sc->dc_stat_ch, hz/10, dc_tick, sc); 3137 else 3138 callout_reset(&sc->dc_stat_ch, hz, dc_tick, sc); 3139 } 3140 3141 /* 3142 * A transmit underrun has occurred. Back off the transmit threshold, 3143 * or switch to store and forward mode if we have to. 3144 */ 3145 static void 3146 dc_tx_underrun(struct dc_softc *sc) 3147 { 3148 uint32_t netcfg, isr; 3149 int i, reinit; 3150 3151 reinit = 0; 3152 netcfg = CSR_READ_4(sc, DC_NETCFG); 3153 device_printf(sc->dc_dev, "TX underrun -- "); 3154 if ((sc->dc_flags & DC_TX_STORENFWD) == 0) { 3155 if (sc->dc_txthresh + DC_TXTHRESH_INC > DC_TXTHRESH_MAX) { 3156 printf("using store and forward mode\n"); 3157 netcfg |= DC_NETCFG_STORENFWD; 3158 } else { 3159 printf("increasing TX threshold\n"); 3160 sc->dc_txthresh += DC_TXTHRESH_INC; 3161 netcfg &= ~DC_NETCFG_TX_THRESH; 3162 netcfg |= sc->dc_txthresh; 3163 } 3164 3165 if (DC_IS_INTEL(sc)) { 3166 /* 3167 * The real 21143 requires that the transmitter be idle 3168 * in order to change the transmit threshold or store 3169 * and forward state. 3170 */ 3171 CSR_WRITE_4(sc, DC_NETCFG, netcfg & ~DC_NETCFG_TX_ON); 3172 3173 for (i = 0; i < DC_TIMEOUT; i++) { 3174 isr = CSR_READ_4(sc, DC_ISR); 3175 if (isr & DC_ISR_TX_IDLE) 3176 break; 3177 DELAY(10); 3178 } 3179 if (i == DC_TIMEOUT) { 3180 device_printf(sc->dc_dev, 3181 "%s: failed to force tx to idle state\n", 3182 __func__); 3183 reinit++; 3184 } 3185 } 3186 } else { 3187 printf("resetting\n"); 3188 reinit++; 3189 } 3190 3191 if (reinit == 0) { 3192 CSR_WRITE_4(sc, DC_NETCFG, netcfg); 3193 if (DC_IS_INTEL(sc)) 3194 CSR_WRITE_4(sc, DC_NETCFG, netcfg | DC_NETCFG_TX_ON); 3195 } else { 3196 sc->dc_ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 3197 dc_init_locked(sc); 3198 } 3199 } 3200 3201 #ifdef DEVICE_POLLING 3202 static poll_handler_t dc_poll; 3203 3204 static int 3205 dc_poll(struct ifnet *ifp, enum poll_cmd cmd, int count) 3206 { 3207 struct dc_softc *sc = ifp->if_softc; 3208 int rx_npkts = 0; 3209 3210 DC_LOCK(sc); 3211 3212 if (!(ifp->if_drv_flags & IFF_DRV_RUNNING)) { 3213 DC_UNLOCK(sc); 3214 return (rx_npkts); 3215 } 3216 3217 sc->rxcycles = count; 3218 rx_npkts = dc_rxeof(sc); 3219 dc_txeof(sc); 3220 if (!IFQ_IS_EMPTY(&ifp->if_snd) && 3221 !(ifp->if_drv_flags & IFF_DRV_OACTIVE)) 3222 dc_start_locked(ifp); 3223 3224 if (cmd == POLL_AND_CHECK_STATUS) { /* also check status register */ 3225 uint32_t status; 3226 3227 status = CSR_READ_4(sc, DC_ISR); 3228 status &= (DC_ISR_RX_WATDOGTIMEO | DC_ISR_RX_NOBUF | 3229 DC_ISR_TX_NOBUF | DC_ISR_TX_IDLE | DC_ISR_TX_UNDERRUN | 3230 DC_ISR_BUS_ERR); 3231 if (!status) { 3232 DC_UNLOCK(sc); 3233 return (rx_npkts); 3234 } 3235 /* ack what we have */ 3236 CSR_WRITE_4(sc, DC_ISR, status); 3237 3238 if (status & (DC_ISR_RX_WATDOGTIMEO | DC_ISR_RX_NOBUF)) { 3239 uint32_t r = CSR_READ_4(sc, DC_FRAMESDISCARDED); 3240 ifp->if_ierrors += (r & 0xffff) + ((r >> 17) & 0x7ff); 3241 3242 if (dc_rx_resync(sc)) 3243 dc_rxeof(sc); 3244 } 3245 /* restart transmit unit if necessary */ 3246 if (status & DC_ISR_TX_IDLE && sc->dc_cdata.dc_tx_cnt) 3247 CSR_WRITE_4(sc, DC_TXSTART, 0xFFFFFFFF); 3248 3249 if (status & DC_ISR_TX_UNDERRUN) 3250 dc_tx_underrun(sc); 3251 3252 if (status & DC_ISR_BUS_ERR) { 3253 if_printf(ifp, "%s: bus error\n", __func__); 3254 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 3255 dc_init_locked(sc); 3256 } 3257 } 3258 DC_UNLOCK(sc); 3259 return (rx_npkts); 3260 } 3261 #endif /* DEVICE_POLLING */ 3262 3263 static void 3264 dc_intr(void *arg) 3265 { 3266 struct dc_softc *sc; 3267 struct ifnet *ifp; 3268 uint32_t r, status; 3269 int n; 3270 3271 sc = arg; 3272 3273 if (sc->suspended) 3274 return; 3275 3276 DC_LOCK(sc); 3277 status = CSR_READ_4(sc, DC_ISR); 3278 if (status == 0xFFFFFFFF || (status & DC_INTRS) == 0) { 3279 DC_UNLOCK(sc); 3280 return; 3281 } 3282 ifp = sc->dc_ifp; 3283 #ifdef DEVICE_POLLING 3284 if (ifp->if_capenable & IFCAP_POLLING) { 3285 DC_UNLOCK(sc); 3286 return; 3287 } 3288 #endif 3289 /* Disable interrupts. */ 3290 CSR_WRITE_4(sc, DC_IMR, 0x00000000); 3291 3292 for (n = 16; n > 0; n--) { 3293 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) 3294 break; 3295 /* Ack interrupts. */ 3296 CSR_WRITE_4(sc, DC_ISR, status); 3297 3298 if (status & DC_ISR_RX_OK) { 3299 if (dc_rxeof(sc) == 0) { 3300 while (dc_rx_resync(sc)) 3301 dc_rxeof(sc); 3302 } 3303 } 3304 3305 if (status & (DC_ISR_TX_OK | DC_ISR_TX_NOBUF)) 3306 dc_txeof(sc); 3307 3308 if (status & DC_ISR_TX_IDLE) { 3309 dc_txeof(sc); 3310 if (sc->dc_cdata.dc_tx_cnt) { 3311 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_TX_ON); 3312 CSR_WRITE_4(sc, DC_TXSTART, 0xFFFFFFFF); 3313 } 3314 } 3315 3316 if (status & DC_ISR_TX_UNDERRUN) 3317 dc_tx_underrun(sc); 3318 3319 if ((status & DC_ISR_RX_WATDOGTIMEO) 3320 || (status & DC_ISR_RX_NOBUF)) { 3321 r = CSR_READ_4(sc, DC_FRAMESDISCARDED); 3322 ifp->if_ierrors += (r & 0xffff) + ((r >> 17) & 0x7ff); 3323 if (dc_rxeof(sc) == 0) { 3324 while (dc_rx_resync(sc)) 3325 dc_rxeof(sc); 3326 } 3327 } 3328 3329 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 3330 dc_start_locked(ifp); 3331 3332 if (status & DC_ISR_BUS_ERR) { 3333 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 3334 dc_init_locked(sc); 3335 DC_UNLOCK(sc); 3336 return; 3337 } 3338 status = CSR_READ_4(sc, DC_ISR); 3339 if (status == 0xFFFFFFFF || (status & DC_INTRS) == 0) 3340 break; 3341 } 3342 3343 /* Re-enable interrupts. */ 3344 if (ifp->if_drv_flags & IFF_DRV_RUNNING) 3345 CSR_WRITE_4(sc, DC_IMR, DC_INTRS); 3346 3347 DC_UNLOCK(sc); 3348 } 3349 3350 /* 3351 * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data 3352 * pointers to the fragment pointers. 3353 */ 3354 static int 3355 dc_encap(struct dc_softc *sc, struct mbuf **m_head) 3356 { 3357 bus_dma_segment_t segs[DC_MAXFRAGS]; 3358 bus_dmamap_t map; 3359 struct dc_desc *f; 3360 struct mbuf *m; 3361 int cur, defragged, error, first, frag, i, idx, nseg; 3362 3363 m = NULL; 3364 defragged = 0; 3365 if (sc->dc_flags & DC_TX_COALESCE && 3366 ((*m_head)->m_next != NULL || sc->dc_flags & DC_TX_ALIGN)) { 3367 m = m_defrag(*m_head, M_DONTWAIT); 3368 defragged = 1; 3369 } else { 3370 /* 3371 * Count the number of frags in this chain to see if we 3372 * need to m_collapse. Since the descriptor list is shared 3373 * by all packets, we'll m_collapse long chains so that they 3374 * do not use up the entire list, even if they would fit. 3375 */ 3376 i = 0; 3377 for (m = *m_head; m != NULL; m = m->m_next) 3378 i++; 3379 if (i > DC_TX_LIST_CNT / 4 || 3380 DC_TX_LIST_CNT - i + sc->dc_cdata.dc_tx_cnt <= 3381 DC_TX_LIST_RSVD) { 3382 m = m_collapse(*m_head, M_DONTWAIT, DC_MAXFRAGS); 3383 defragged = 1; 3384 } 3385 } 3386 if (defragged != 0) { 3387 if (m == NULL) { 3388 m_freem(*m_head); 3389 *m_head = NULL; 3390 return (ENOBUFS); 3391 } 3392 *m_head = m; 3393 } 3394 3395 idx = sc->dc_cdata.dc_tx_prod; 3396 error = bus_dmamap_load_mbuf_sg(sc->dc_tx_mtag, 3397 sc->dc_cdata.dc_tx_map[idx], *m_head, segs, &nseg, 0); 3398 if (error == EFBIG) { 3399 if (defragged != 0 || (m = m_collapse(*m_head, M_DONTWAIT, 3400 DC_MAXFRAGS)) == NULL) { 3401 m_freem(*m_head); 3402 *m_head = NULL; 3403 return (defragged != 0 ? error : ENOBUFS); 3404 } 3405 *m_head = m; 3406 error = bus_dmamap_load_mbuf_sg(sc->dc_tx_mtag, 3407 sc->dc_cdata.dc_tx_map[idx], *m_head, segs, &nseg, 0); 3408 if (error != 0) { 3409 m_freem(*m_head); 3410 *m_head = NULL; 3411 return (error); 3412 } 3413 } else if (error != 0) 3414 return (error); 3415 KASSERT(nseg <= DC_MAXFRAGS, 3416 ("%s: wrong number of segments (%d)", __func__, nseg)); 3417 if (nseg == 0) { 3418 m_freem(*m_head); 3419 *m_head = NULL; 3420 return (EIO); 3421 } 3422 3423 /* Check descriptor overruns. */ 3424 if (sc->dc_cdata.dc_tx_cnt + nseg > DC_TX_LIST_CNT - DC_TX_LIST_RSVD) { 3425 bus_dmamap_unload(sc->dc_tx_mtag, sc->dc_cdata.dc_tx_map[idx]); 3426 return (ENOBUFS); 3427 } 3428 bus_dmamap_sync(sc->dc_tx_mtag, sc->dc_cdata.dc_tx_map[idx], 3429 BUS_DMASYNC_PREWRITE); 3430 3431 first = cur = frag = sc->dc_cdata.dc_tx_prod; 3432 for (i = 0; i < nseg; i++) { 3433 if ((sc->dc_flags & DC_TX_ADMTEK_WAR) && 3434 (frag == (DC_TX_LIST_CNT - 1)) && 3435 (first != sc->dc_cdata.dc_tx_first)) { 3436 bus_dmamap_unload(sc->dc_tx_mtag, 3437 sc->dc_cdata.dc_tx_map[first]); 3438 m_freem(*m_head); 3439 *m_head = NULL; 3440 return (ENOBUFS); 3441 } 3442 3443 f = &sc->dc_ldata.dc_tx_list[frag]; 3444 f->dc_ctl = htole32(DC_TXCTL_TLINK | segs[i].ds_len); 3445 if (i == 0) { 3446 f->dc_status = 0; 3447 f->dc_ctl |= htole32(DC_TXCTL_FIRSTFRAG); 3448 } else 3449 f->dc_status = htole32(DC_TXSTAT_OWN); 3450 f->dc_data = htole32(DC_ADDR_LO(segs[i].ds_addr)); 3451 cur = frag; 3452 DC_INC(frag, DC_TX_LIST_CNT); 3453 } 3454 3455 sc->dc_cdata.dc_tx_prod = frag; 3456 sc->dc_cdata.dc_tx_cnt += nseg; 3457 sc->dc_cdata.dc_tx_chain[cur] = *m_head; 3458 sc->dc_ldata.dc_tx_list[cur].dc_ctl |= htole32(DC_TXCTL_LASTFRAG); 3459 if (sc->dc_flags & DC_TX_INTR_FIRSTFRAG) 3460 sc->dc_ldata.dc_tx_list[first].dc_ctl |= 3461 htole32(DC_TXCTL_FINT); 3462 if (sc->dc_flags & DC_TX_INTR_ALWAYS) 3463 sc->dc_ldata.dc_tx_list[cur].dc_ctl |= htole32(DC_TXCTL_FINT); 3464 if (sc->dc_flags & DC_TX_USE_TX_INTR && 3465 ++sc->dc_cdata.dc_tx_pkts >= 8) { 3466 sc->dc_cdata.dc_tx_pkts = 0; 3467 sc->dc_ldata.dc_tx_list[cur].dc_ctl |= htole32(DC_TXCTL_FINT); 3468 } 3469 sc->dc_ldata.dc_tx_list[first].dc_status = htole32(DC_TXSTAT_OWN); 3470 3471 bus_dmamap_sync(sc->dc_tx_ltag, sc->dc_tx_lmap, 3472 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 3473 3474 /* 3475 * Swap the last and the first dmamaps to ensure the map for 3476 * this transmission is placed at the last descriptor. 3477 */ 3478 map = sc->dc_cdata.dc_tx_map[cur]; 3479 sc->dc_cdata.dc_tx_map[cur] = sc->dc_cdata.dc_tx_map[first]; 3480 sc->dc_cdata.dc_tx_map[first] = map; 3481 3482 return (0); 3483 } 3484 3485 static void 3486 dc_start(struct ifnet *ifp) 3487 { 3488 struct dc_softc *sc; 3489 3490 sc = ifp->if_softc; 3491 DC_LOCK(sc); 3492 dc_start_locked(ifp); 3493 DC_UNLOCK(sc); 3494 } 3495 3496 /* 3497 * Main transmit routine 3498 * To avoid having to do mbuf copies, we put pointers to the mbuf data 3499 * regions directly in the transmit lists. We also save a copy of the 3500 * pointers since the transmit list fragment pointers are physical 3501 * addresses. 3502 */ 3503 static void 3504 dc_start_locked(struct ifnet *ifp) 3505 { 3506 struct dc_softc *sc; 3507 struct mbuf *m_head; 3508 int queued; 3509 3510 sc = ifp->if_softc; 3511 3512 DC_LOCK_ASSERT(sc); 3513 3514 if ((ifp->if_drv_flags & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) != 3515 IFF_DRV_RUNNING || sc->dc_link == 0) 3516 return; 3517 3518 sc->dc_cdata.dc_tx_first = sc->dc_cdata.dc_tx_prod; 3519 3520 for (queued = 0; !IFQ_DRV_IS_EMPTY(&ifp->if_snd); ) { 3521 /* 3522 * If there's no way we can send any packets, return now. 3523 */ 3524 if (sc->dc_cdata.dc_tx_cnt > DC_TX_LIST_CNT - DC_TX_LIST_RSVD) { 3525 ifp->if_drv_flags |= IFF_DRV_OACTIVE; 3526 break; 3527 } 3528 IFQ_DRV_DEQUEUE(&ifp->if_snd, m_head); 3529 if (m_head == NULL) 3530 break; 3531 3532 if (dc_encap(sc, &m_head)) { 3533 if (m_head == NULL) 3534 break; 3535 IFQ_DRV_PREPEND(&ifp->if_snd, m_head); 3536 ifp->if_drv_flags |= IFF_DRV_OACTIVE; 3537 break; 3538 } 3539 3540 queued++; 3541 /* 3542 * If there's a BPF listener, bounce a copy of this frame 3543 * to him. 3544 */ 3545 BPF_MTAP(ifp, m_head); 3546 } 3547 3548 if (queued > 0) { 3549 /* Transmit */ 3550 if (!(sc->dc_flags & DC_TX_POLL)) 3551 CSR_WRITE_4(sc, DC_TXSTART, 0xFFFFFFFF); 3552 3553 /* 3554 * Set a timeout in case the chip goes out to lunch. 3555 */ 3556 sc->dc_wdog_timer = 5; 3557 } 3558 } 3559 3560 static void 3561 dc_init(void *xsc) 3562 { 3563 struct dc_softc *sc = xsc; 3564 3565 DC_LOCK(sc); 3566 dc_init_locked(sc); 3567 DC_UNLOCK(sc); 3568 } 3569 3570 static void 3571 dc_init_locked(struct dc_softc *sc) 3572 { 3573 struct ifnet *ifp = sc->dc_ifp; 3574 struct mii_data *mii; 3575 struct ifmedia *ifm; 3576 3577 DC_LOCK_ASSERT(sc); 3578 3579 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) 3580 return; 3581 3582 mii = device_get_softc(sc->dc_miibus); 3583 3584 /* 3585 * Cancel pending I/O and free all RX/TX buffers. 3586 */ 3587 dc_stop(sc); 3588 dc_reset(sc); 3589 if (DC_IS_INTEL(sc)) { 3590 ifm = &mii->mii_media; 3591 dc_apply_fixup(sc, ifm->ifm_media); 3592 } 3593 3594 /* 3595 * Set cache alignment and burst length. 3596 */ 3597 if (DC_IS_ASIX(sc) || DC_IS_DAVICOM(sc)) 3598 CSR_WRITE_4(sc, DC_BUSCTL, 0); 3599 else 3600 CSR_WRITE_4(sc, DC_BUSCTL, DC_BUSCTL_MRME | DC_BUSCTL_MRLE); 3601 /* 3602 * Evenly share the bus between receive and transmit process. 3603 */ 3604 if (DC_IS_INTEL(sc)) 3605 DC_SETBIT(sc, DC_BUSCTL, DC_BUSCTL_ARBITRATION); 3606 if (DC_IS_DAVICOM(sc) || DC_IS_INTEL(sc)) { 3607 DC_SETBIT(sc, DC_BUSCTL, DC_BURSTLEN_USECA); 3608 } else { 3609 DC_SETBIT(sc, DC_BUSCTL, DC_BURSTLEN_16LONG); 3610 } 3611 if (sc->dc_flags & DC_TX_POLL) 3612 DC_SETBIT(sc, DC_BUSCTL, DC_TXPOLL_1); 3613 switch(sc->dc_cachesize) { 3614 case 32: 3615 DC_SETBIT(sc, DC_BUSCTL, DC_CACHEALIGN_32LONG); 3616 break; 3617 case 16: 3618 DC_SETBIT(sc, DC_BUSCTL, DC_CACHEALIGN_16LONG); 3619 break; 3620 case 8: 3621 DC_SETBIT(sc, DC_BUSCTL, DC_CACHEALIGN_8LONG); 3622 break; 3623 case 0: 3624 default: 3625 DC_SETBIT(sc, DC_BUSCTL, DC_CACHEALIGN_NONE); 3626 break; 3627 } 3628 3629 if (sc->dc_flags & DC_TX_STORENFWD) 3630 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_STORENFWD); 3631 else { 3632 if (sc->dc_txthresh > DC_TXTHRESH_MAX) { 3633 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_STORENFWD); 3634 } else { 3635 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_STORENFWD); 3636 DC_SETBIT(sc, DC_NETCFG, sc->dc_txthresh); 3637 } 3638 } 3639 3640 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_NO_RXCRC); 3641 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_TX_BACKOFF); 3642 3643 if (DC_IS_MACRONIX(sc) || DC_IS_PNICII(sc)) { 3644 /* 3645 * The app notes for the 98713 and 98715A say that 3646 * in order to have the chips operate properly, a magic 3647 * number must be written to CSR16. Macronix does not 3648 * document the meaning of these bits so there's no way 3649 * to know exactly what they do. The 98713 has a magic 3650 * number all its own; the rest all use a different one. 3651 */ 3652 DC_CLRBIT(sc, DC_MX_MAGICPACKET, 0xFFFF0000); 3653 if (sc->dc_type == DC_TYPE_98713) 3654 DC_SETBIT(sc, DC_MX_MAGICPACKET, DC_MX_MAGIC_98713); 3655 else 3656 DC_SETBIT(sc, DC_MX_MAGICPACKET, DC_MX_MAGIC_98715); 3657 } 3658 3659 if (DC_IS_XIRCOM(sc)) { 3660 /* 3661 * setup General Purpose Port mode and data so the tulip 3662 * can talk to the MII. 3663 */ 3664 CSR_WRITE_4(sc, DC_SIAGP, DC_SIAGP_WRITE_EN | DC_SIAGP_INT1_EN | 3665 DC_SIAGP_MD_GP2_OUTPUT | DC_SIAGP_MD_GP0_OUTPUT); 3666 DELAY(10); 3667 CSR_WRITE_4(sc, DC_SIAGP, DC_SIAGP_INT1_EN | 3668 DC_SIAGP_MD_GP2_OUTPUT | DC_SIAGP_MD_GP0_OUTPUT); 3669 DELAY(10); 3670 } 3671 3672 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_TX_THRESH); 3673 DC_SETBIT(sc, DC_NETCFG, DC_TXTHRESH_MIN); 3674 3675 /* Init circular RX list. */ 3676 if (dc_list_rx_init(sc) == ENOBUFS) { 3677 device_printf(sc->dc_dev, 3678 "initialization failed: no memory for rx buffers\n"); 3679 dc_stop(sc); 3680 return; 3681 } 3682 3683 /* 3684 * Init TX descriptors. 3685 */ 3686 dc_list_tx_init(sc); 3687 3688 /* 3689 * Load the address of the RX list. 3690 */ 3691 CSR_WRITE_4(sc, DC_RXADDR, DC_RXDESC(sc, 0)); 3692 CSR_WRITE_4(sc, DC_TXADDR, DC_TXDESC(sc, 0)); 3693 3694 /* 3695 * Enable interrupts. 3696 */ 3697 #ifdef DEVICE_POLLING 3698 /* 3699 * ... but only if we are not polling, and make sure they are off in 3700 * the case of polling. Some cards (e.g. fxp) turn interrupts on 3701 * after a reset. 3702 */ 3703 if (ifp->if_capenable & IFCAP_POLLING) 3704 CSR_WRITE_4(sc, DC_IMR, 0x00000000); 3705 else 3706 #endif 3707 CSR_WRITE_4(sc, DC_IMR, DC_INTRS); 3708 CSR_WRITE_4(sc, DC_ISR, 0xFFFFFFFF); 3709 3710 /* Enable transmitter. */ 3711 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_TX_ON); 3712 3713 /* 3714 * If this is an Intel 21143 and we're not using the 3715 * MII port, program the LED control pins so we get 3716 * link and activity indications. 3717 */ 3718 if (sc->dc_flags & DC_TULIP_LEDS) { 3719 CSR_WRITE_4(sc, DC_WATCHDOG, 3720 DC_WDOG_CTLWREN | DC_WDOG_LINK | DC_WDOG_ACTIVITY); 3721 CSR_WRITE_4(sc, DC_WATCHDOG, 0); 3722 } 3723 3724 /* 3725 * Load the RX/multicast filter. We do this sort of late 3726 * because the filter programming scheme on the 21143 and 3727 * some clones requires DMAing a setup frame via the TX 3728 * engine, and we need the transmitter enabled for that. 3729 */ 3730 dc_setfilt(sc); 3731 3732 /* Enable receiver. */ 3733 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_ON); 3734 CSR_WRITE_4(sc, DC_RXSTART, 0xFFFFFFFF); 3735 3736 ifp->if_drv_flags |= IFF_DRV_RUNNING; 3737 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 3738 3739 mii_mediachg(mii); 3740 dc_setcfg(sc, sc->dc_if_media); 3741 3742 /* Clear missed frames and overflow counter. */ 3743 CSR_READ_4(sc, DC_FRAMESDISCARDED); 3744 3745 /* Don't start the ticker if this is a homePNA link. */ 3746 if (IFM_SUBTYPE(mii->mii_media.ifm_media) == IFM_HPNA_1) 3747 sc->dc_link = 1; 3748 else { 3749 if (sc->dc_flags & DC_21143_NWAY) 3750 callout_reset(&sc->dc_stat_ch, hz/10, dc_tick, sc); 3751 else 3752 callout_reset(&sc->dc_stat_ch, hz, dc_tick, sc); 3753 } 3754 3755 sc->dc_wdog_timer = 0; 3756 callout_reset(&sc->dc_wdog_ch, hz, dc_watchdog, sc); 3757 } 3758 3759 /* 3760 * Set media options. 3761 */ 3762 static int 3763 dc_ifmedia_upd(struct ifnet *ifp) 3764 { 3765 struct dc_softc *sc; 3766 struct mii_data *mii; 3767 struct ifmedia *ifm; 3768 3769 sc = ifp->if_softc; 3770 mii = device_get_softc(sc->dc_miibus); 3771 DC_LOCK(sc); 3772 mii_mediachg(mii); 3773 ifm = &mii->mii_media; 3774 3775 if (DC_IS_INTEL(sc)) 3776 dc_setcfg(sc, ifm->ifm_media); 3777 else if (DC_IS_DAVICOM(sc) && 3778 IFM_SUBTYPE(ifm->ifm_media) == IFM_HPNA_1) 3779 dc_setcfg(sc, ifm->ifm_media); 3780 else 3781 sc->dc_link = 0; 3782 DC_UNLOCK(sc); 3783 3784 return (0); 3785 } 3786 3787 /* 3788 * Report current media status. 3789 */ 3790 static void 3791 dc_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 3792 { 3793 struct dc_softc *sc; 3794 struct mii_data *mii; 3795 struct ifmedia *ifm; 3796 3797 sc = ifp->if_softc; 3798 mii = device_get_softc(sc->dc_miibus); 3799 DC_LOCK(sc); 3800 mii_pollstat(mii); 3801 ifm = &mii->mii_media; 3802 if (DC_IS_DAVICOM(sc)) { 3803 if (IFM_SUBTYPE(ifm->ifm_media) == IFM_HPNA_1) { 3804 ifmr->ifm_active = ifm->ifm_media; 3805 ifmr->ifm_status = 0; 3806 DC_UNLOCK(sc); 3807 return; 3808 } 3809 } 3810 ifmr->ifm_active = mii->mii_media_active; 3811 ifmr->ifm_status = mii->mii_media_status; 3812 DC_UNLOCK(sc); 3813 } 3814 3815 static int 3816 dc_ioctl(struct ifnet *ifp, u_long command, caddr_t data) 3817 { 3818 struct dc_softc *sc = ifp->if_softc; 3819 struct ifreq *ifr = (struct ifreq *)data; 3820 struct mii_data *mii; 3821 int error = 0; 3822 3823 switch (command) { 3824 case SIOCSIFFLAGS: 3825 DC_LOCK(sc); 3826 if (ifp->if_flags & IFF_UP) { 3827 int need_setfilt = (ifp->if_flags ^ sc->dc_if_flags) & 3828 (IFF_PROMISC | IFF_ALLMULTI); 3829 3830 if (ifp->if_drv_flags & IFF_DRV_RUNNING) { 3831 if (need_setfilt) 3832 dc_setfilt(sc); 3833 } else { 3834 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 3835 dc_init_locked(sc); 3836 } 3837 } else { 3838 if (ifp->if_drv_flags & IFF_DRV_RUNNING) 3839 dc_stop(sc); 3840 } 3841 sc->dc_if_flags = ifp->if_flags; 3842 DC_UNLOCK(sc); 3843 break; 3844 case SIOCADDMULTI: 3845 case SIOCDELMULTI: 3846 DC_LOCK(sc); 3847 if (ifp->if_drv_flags & IFF_DRV_RUNNING) 3848 dc_setfilt(sc); 3849 DC_UNLOCK(sc); 3850 break; 3851 case SIOCGIFMEDIA: 3852 case SIOCSIFMEDIA: 3853 mii = device_get_softc(sc->dc_miibus); 3854 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 3855 break; 3856 case SIOCSIFCAP: 3857 #ifdef DEVICE_POLLING 3858 if (ifr->ifr_reqcap & IFCAP_POLLING && 3859 !(ifp->if_capenable & IFCAP_POLLING)) { 3860 error = ether_poll_register(dc_poll, ifp); 3861 if (error) 3862 return(error); 3863 DC_LOCK(sc); 3864 /* Disable interrupts */ 3865 CSR_WRITE_4(sc, DC_IMR, 0x00000000); 3866 ifp->if_capenable |= IFCAP_POLLING; 3867 DC_UNLOCK(sc); 3868 return (error); 3869 } 3870 if (!(ifr->ifr_reqcap & IFCAP_POLLING) && 3871 ifp->if_capenable & IFCAP_POLLING) { 3872 error = ether_poll_deregister(ifp); 3873 /* Enable interrupts. */ 3874 DC_LOCK(sc); 3875 CSR_WRITE_4(sc, DC_IMR, DC_INTRS); 3876 ifp->if_capenable &= ~IFCAP_POLLING; 3877 DC_UNLOCK(sc); 3878 return (error); 3879 } 3880 #endif /* DEVICE_POLLING */ 3881 break; 3882 default: 3883 error = ether_ioctl(ifp, command, data); 3884 break; 3885 } 3886 3887 return (error); 3888 } 3889 3890 static void 3891 dc_watchdog(void *xsc) 3892 { 3893 struct dc_softc *sc = xsc; 3894 struct ifnet *ifp; 3895 3896 DC_LOCK_ASSERT(sc); 3897 3898 if (sc->dc_wdog_timer == 0 || --sc->dc_wdog_timer != 0) { 3899 callout_reset(&sc->dc_wdog_ch, hz, dc_watchdog, sc); 3900 return; 3901 } 3902 3903 ifp = sc->dc_ifp; 3904 ifp->if_oerrors++; 3905 device_printf(sc->dc_dev, "watchdog timeout\n"); 3906 3907 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 3908 dc_init_locked(sc); 3909 3910 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 3911 dc_start_locked(ifp); 3912 } 3913 3914 /* 3915 * Stop the adapter and free any mbufs allocated to the 3916 * RX and TX lists. 3917 */ 3918 static void 3919 dc_stop(struct dc_softc *sc) 3920 { 3921 struct ifnet *ifp; 3922 struct dc_list_data *ld; 3923 struct dc_chain_data *cd; 3924 int i; 3925 uint32_t ctl, netcfg; 3926 3927 DC_LOCK_ASSERT(sc); 3928 3929 ifp = sc->dc_ifp; 3930 ld = &sc->dc_ldata; 3931 cd = &sc->dc_cdata; 3932 3933 callout_stop(&sc->dc_stat_ch); 3934 callout_stop(&sc->dc_wdog_ch); 3935 sc->dc_wdog_timer = 0; 3936 sc->dc_link = 0; 3937 3938 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE); 3939 3940 netcfg = CSR_READ_4(sc, DC_NETCFG); 3941 if (netcfg & (DC_NETCFG_RX_ON | DC_NETCFG_TX_ON)) 3942 CSR_WRITE_4(sc, DC_NETCFG, 3943 netcfg & ~(DC_NETCFG_RX_ON | DC_NETCFG_TX_ON)); 3944 CSR_WRITE_4(sc, DC_IMR, 0x00000000); 3945 /* Wait the completion of TX/RX SM. */ 3946 if (netcfg & (DC_NETCFG_RX_ON | DC_NETCFG_TX_ON)) 3947 dc_netcfg_wait(sc); 3948 3949 CSR_WRITE_4(sc, DC_TXADDR, 0x00000000); 3950 CSR_WRITE_4(sc, DC_RXADDR, 0x00000000); 3951 3952 /* 3953 * Free data in the RX lists. 3954 */ 3955 for (i = 0; i < DC_RX_LIST_CNT; i++) { 3956 if (cd->dc_rx_chain[i] != NULL) { 3957 bus_dmamap_sync(sc->dc_rx_mtag, 3958 cd->dc_rx_map[i], BUS_DMASYNC_POSTREAD); 3959 bus_dmamap_unload(sc->dc_rx_mtag, 3960 cd->dc_rx_map[i]); 3961 m_freem(cd->dc_rx_chain[i]); 3962 cd->dc_rx_chain[i] = NULL; 3963 } 3964 } 3965 bzero(ld->dc_rx_list, DC_RX_LIST_SZ); 3966 bus_dmamap_sync(sc->dc_rx_ltag, sc->dc_rx_lmap, 3967 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 3968 3969 /* 3970 * Free the TX list buffers. 3971 */ 3972 for (i = 0; i < DC_TX_LIST_CNT; i++) { 3973 if (cd->dc_tx_chain[i] != NULL) { 3974 ctl = le32toh(ld->dc_tx_list[i].dc_ctl); 3975 if (ctl & DC_TXCTL_SETUP) { 3976 bus_dmamap_sync(sc->dc_stag, sc->dc_smap, 3977 BUS_DMASYNC_POSTWRITE); 3978 } else { 3979 bus_dmamap_sync(sc->dc_tx_mtag, 3980 cd->dc_tx_map[i], BUS_DMASYNC_POSTWRITE); 3981 bus_dmamap_unload(sc->dc_tx_mtag, 3982 cd->dc_tx_map[i]); 3983 m_freem(cd->dc_tx_chain[i]); 3984 } 3985 cd->dc_tx_chain[i] = NULL; 3986 } 3987 } 3988 bzero(ld->dc_tx_list, DC_TX_LIST_SZ); 3989 bus_dmamap_sync(sc->dc_tx_ltag, sc->dc_tx_lmap, 3990 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 3991 } 3992 3993 /* 3994 * Device suspend routine. Stop the interface and save some PCI 3995 * settings in case the BIOS doesn't restore them properly on 3996 * resume. 3997 */ 3998 static int 3999 dc_suspend(device_t dev) 4000 { 4001 struct dc_softc *sc; 4002 4003 sc = device_get_softc(dev); 4004 DC_LOCK(sc); 4005 dc_stop(sc); 4006 sc->suspended = 1; 4007 DC_UNLOCK(sc); 4008 4009 return (0); 4010 } 4011 4012 /* 4013 * Device resume routine. Restore some PCI settings in case the BIOS 4014 * doesn't, re-enable busmastering, and restart the interface if 4015 * appropriate. 4016 */ 4017 static int 4018 dc_resume(device_t dev) 4019 { 4020 struct dc_softc *sc; 4021 struct ifnet *ifp; 4022 4023 sc = device_get_softc(dev); 4024 ifp = sc->dc_ifp; 4025 4026 /* reinitialize interface if necessary */ 4027 DC_LOCK(sc); 4028 if (ifp->if_flags & IFF_UP) 4029 dc_init_locked(sc); 4030 4031 sc->suspended = 0; 4032 DC_UNLOCK(sc); 4033 4034 return (0); 4035 } 4036 4037 /* 4038 * Stop all chip I/O so that the kernel's probe routines don't 4039 * get confused by errant DMAs when rebooting. 4040 */ 4041 static int 4042 dc_shutdown(device_t dev) 4043 { 4044 struct dc_softc *sc; 4045 4046 sc = device_get_softc(dev); 4047 4048 DC_LOCK(sc); 4049 dc_stop(sc); 4050 DC_UNLOCK(sc); 4051 4052 return (0); 4053 } 4054 4055 static int 4056 dc_check_multiport(struct dc_softc *sc) 4057 { 4058 struct dc_softc *dsc; 4059 devclass_t dc; 4060 device_t child; 4061 uint8_t *eaddr; 4062 int unit; 4063 4064 dc = devclass_find("dc"); 4065 for (unit = 0; unit < devclass_get_maxunit(dc); unit++) { 4066 child = devclass_get_device(dc, unit); 4067 if (child == NULL) 4068 continue; 4069 if (child == sc->dc_dev) 4070 continue; 4071 if (device_get_parent(child) != device_get_parent(sc->dc_dev)) 4072 continue; 4073 if (unit > device_get_unit(sc->dc_dev)) 4074 continue; 4075 if (device_is_attached(child) == 0) 4076 continue; 4077 dsc = device_get_softc(child); 4078 device_printf(sc->dc_dev, 4079 "Using station address of %s as base\n", 4080 device_get_nameunit(child)); 4081 bcopy(dsc->dc_eaddr, sc->dc_eaddr, ETHER_ADDR_LEN); 4082 eaddr = (uint8_t *)sc->dc_eaddr; 4083 eaddr[5]++; 4084 /* Prepare SROM to parse again. */ 4085 if (DC_IS_INTEL(sc) && dsc->dc_srom != NULL && 4086 sc->dc_romwidth != 0) { 4087 free(sc->dc_srom, M_DEVBUF); 4088 sc->dc_romwidth = dsc->dc_romwidth; 4089 sc->dc_srom = malloc(DC_ROM_SIZE(sc->dc_romwidth), 4090 M_DEVBUF, M_NOWAIT); 4091 if (sc->dc_srom == NULL) { 4092 device_printf(sc->dc_dev, 4093 "Could not allocate SROM buffer\n"); 4094 return (ENOMEM); 4095 } 4096 bcopy(dsc->dc_srom, sc->dc_srom, 4097 DC_ROM_SIZE(sc->dc_romwidth)); 4098 } 4099 return (0); 4100 } 4101 return (ENOENT); 4102 } 4103