1 /* 2 * Copyright (c) 1997, 1998, 1999 3 * Bill Paul <wpaul@ee.columbia.edu>. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 3. All advertising materials mentioning features or use of this software 14 * must display the following acknowledgement: 15 * This product includes software developed by Bill Paul. 16 * 4. Neither the name of the author nor the names of any co-contributors 17 * may be used to endorse or promote products derived from this software 18 * without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30 * THE POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33 /* 34 * DEC "tulip" clone ethernet driver. Supports the DEC/Intel 21143 35 * series chips and several workalikes including the following: 36 * 37 * Macronix 98713/98715/98725/98727/98732 PMAC (www.macronix.com) 38 * Macronix/Lite-On 82c115 PNIC II (www.macronix.com) 39 * Lite-On 82c168/82c169 PNIC (www.litecom.com) 40 * ASIX Electronics AX88140A (www.asix.com.tw) 41 * ASIX Electronics AX88141 (www.asix.com.tw) 42 * ADMtek AL981 (www.admtek.com.tw) 43 * ADMtek AN985 (www.admtek.com.tw) 44 * Davicom DM9100, DM9102, DM9102A (www.davicom8.com) 45 * Accton EN1217 (www.accton.com) 46 * Xircom X3201 (www.xircom.com) 47 * Abocom FE2500 48 * Conexant LANfinity (www.conexant.com) 49 * 50 * Datasheets for the 21143 are available at developer.intel.com. 51 * Datasheets for the clone parts can be found at their respective sites. 52 * (Except for the PNIC; see www.freebsd.org/~wpaul/PNIC/pnic.ps.gz.) 53 * The PNIC II is essentially a Macronix 98715A chip; the only difference 54 * worth noting is that its multicast hash table is only 128 bits wide 55 * instead of 512. 56 * 57 * Written by Bill Paul <wpaul@ee.columbia.edu> 58 * Electrical Engineering Department 59 * Columbia University, New York City 60 */ 61 62 /* 63 * The Intel 21143 is the successor to the DEC 21140. It is basically 64 * the same as the 21140 but with a few new features. The 21143 supports 65 * three kinds of media attachments: 66 * 67 * o MII port, for 10Mbps and 100Mbps support and NWAY 68 * autonegotiation provided by an external PHY. 69 * o SYM port, for symbol mode 100Mbps support. 70 * o 10baseT port. 71 * o AUI/BNC port. 72 * 73 * The 100Mbps SYM port and 10baseT port can be used together in 74 * combination with the internal NWAY support to create a 10/100 75 * autosensing configuration. 76 * 77 * Note that not all tulip workalikes are handled in this driver: we only 78 * deal with those which are relatively well behaved. The Winbond is 79 * handled separately due to its different register offsets and the 80 * special handling needed for its various bugs. The PNIC is handled 81 * here, but I'm not thrilled about it. 82 * 83 * All of the workalike chips use some form of MII transceiver support 84 * with the exception of the Macronix chips, which also have a SYM port. 85 * The ASIX AX88140A is also documented to have a SYM port, but all 86 * the cards I've seen use an MII transceiver, probably because the 87 * AX88140A doesn't support internal NWAY. 88 */ 89 90 #include <sys/cdefs.h> 91 __FBSDID("$FreeBSD$"); 92 93 #include <sys/param.h> 94 #include <sys/systm.h> 95 #include <sys/sockio.h> 96 #include <sys/mbuf.h> 97 #include <sys/malloc.h> 98 #include <sys/kernel.h> 99 #include <sys/socket.h> 100 #include <sys/sysctl.h> 101 102 #include <net/if.h> 103 #include <net/if_arp.h> 104 #include <net/ethernet.h> 105 #include <net/if_dl.h> 106 #include <net/if_media.h> 107 #include <net/if_types.h> 108 #include <net/if_vlan_var.h> 109 110 #include <net/bpf.h> 111 112 #include <vm/vm.h> /* for vtophys */ 113 #include <vm/pmap.h> /* for vtophys */ 114 #include <machine/bus_pio.h> 115 #include <machine/bus_memio.h> 116 #include <machine/bus.h> 117 #include <machine/resource.h> 118 #include <sys/bus.h> 119 #include <sys/rman.h> 120 121 #include <dev/mii/mii.h> 122 #include <dev/mii/miivar.h> 123 124 #include <pci/pcireg.h> 125 #include <pci/pcivar.h> 126 127 #define DC_USEIOSPACE 128 #ifdef __alpha__ 129 #define SRM_MEDIA 130 #endif 131 132 #include <pci/if_dcreg.h> 133 134 MODULE_DEPEND(dc, pci, 1, 1, 1); 135 MODULE_DEPEND(dc, ether, 1, 1, 1); 136 MODULE_DEPEND(dc, miibus, 1, 1, 1); 137 138 /* "controller miibus0" required. See GENERIC if you get errors here. */ 139 #include "miibus_if.h" 140 141 /* 142 * Various supported device vendors/types and their names. 143 */ 144 static struct dc_type dc_devs[] = { 145 { DC_VENDORID_DEC, DC_DEVICEID_21143, 146 "Intel 21143 10/100BaseTX" }, 147 { DC_VENDORID_DAVICOM, DC_DEVICEID_DM9009, 148 "Davicom DM9009 10/100BaseTX" }, 149 { DC_VENDORID_DAVICOM, DC_DEVICEID_DM9100, 150 "Davicom DM9100 10/100BaseTX" }, 151 { DC_VENDORID_DAVICOM, DC_DEVICEID_DM9102, 152 "Davicom DM9102 10/100BaseTX" }, 153 { DC_VENDORID_DAVICOM, DC_DEVICEID_DM9102, 154 "Davicom DM9102A 10/100BaseTX" }, 155 { DC_VENDORID_ADMTEK, DC_DEVICEID_AL981, 156 "ADMtek AL981 10/100BaseTX" }, 157 { DC_VENDORID_ADMTEK, DC_DEVICEID_AN985, 158 "ADMtek AN985 10/100BaseTX" }, 159 { DC_VENDORID_ASIX, DC_DEVICEID_AX88140A, 160 "ASIX AX88140A 10/100BaseTX" }, 161 { DC_VENDORID_ASIX, DC_DEVICEID_AX88140A, 162 "ASIX AX88141 10/100BaseTX" }, 163 { DC_VENDORID_MX, DC_DEVICEID_98713, 164 "Macronix 98713 10/100BaseTX" }, 165 { DC_VENDORID_MX, DC_DEVICEID_98713, 166 "Macronix 98713A 10/100BaseTX" }, 167 { DC_VENDORID_CP, DC_DEVICEID_98713_CP, 168 "Compex RL100-TX 10/100BaseTX" }, 169 { DC_VENDORID_CP, DC_DEVICEID_98713_CP, 170 "Compex RL100-TX 10/100BaseTX" }, 171 { DC_VENDORID_MX, DC_DEVICEID_987x5, 172 "Macronix 98715/98715A 10/100BaseTX" }, 173 { DC_VENDORID_MX, DC_DEVICEID_987x5, 174 "Macronix 98715AEC-C 10/100BaseTX" }, 175 { DC_VENDORID_MX, DC_DEVICEID_987x5, 176 "Macronix 98725 10/100BaseTX" }, 177 { DC_VENDORID_MX, DC_DEVICEID_98727, 178 "Macronix 98727/98732 10/100BaseTX" }, 179 { DC_VENDORID_LO, DC_DEVICEID_82C115, 180 "LC82C115 PNIC II 10/100BaseTX" }, 181 { DC_VENDORID_LO, DC_DEVICEID_82C168, 182 "82c168 PNIC 10/100BaseTX" }, 183 { DC_VENDORID_LO, DC_DEVICEID_82C168, 184 "82c169 PNIC 10/100BaseTX" }, 185 { DC_VENDORID_ACCTON, DC_DEVICEID_EN1217, 186 "Accton EN1217 10/100BaseTX" }, 187 { DC_VENDORID_ACCTON, DC_DEVICEID_EN2242, 188 "Accton EN2242 MiniPCI 10/100BaseTX" }, 189 { DC_VENDORID_XIRCOM, DC_DEVICEID_X3201, 190 "Xircom X3201 10/100BaseTX" }, 191 { DC_VENDORID_ABOCOM, DC_DEVICEID_FE2500, 192 "Abocom FE2500 10/100BaseTX" }, 193 { DC_VENDORID_CONEXANT, DC_DEVICEID_RS7112, 194 "Conexant LANfinity MiniPCI 10/100BaseTX" }, 195 { DC_VENDORID_HAWKING, DC_DEVICEID_HAWKING_PN672TX, 196 "Hawking CB102 CardBus 10/100" }, 197 { DC_VENDORID_PLANEX, DC_DEVICEID_FNW3602T, 198 "PlaneX FNW-3602-T CardBus 10/100" }, 199 { 0, 0, NULL } 200 }; 201 202 static int dc_probe (device_t); 203 static int dc_attach (device_t); 204 static int dc_detach (device_t); 205 static int dc_suspend (device_t); 206 static int dc_resume (device_t); 207 static void dc_acpi (device_t); 208 static struct dc_type *dc_devtype (device_t); 209 static int dc_newbuf (struct dc_softc *, int, struct mbuf *); 210 static int dc_encap (struct dc_softc *, struct mbuf *, u_int32_t *); 211 static void dc_pnic_rx_bug_war (struct dc_softc *, int); 212 static int dc_rx_resync (struct dc_softc *); 213 static void dc_rxeof (struct dc_softc *); 214 static void dc_txeof (struct dc_softc *); 215 static void dc_tick (void *); 216 static void dc_tx_underrun (struct dc_softc *); 217 static void dc_intr (void *); 218 static void dc_start (struct ifnet *); 219 static int dc_ioctl (struct ifnet *, u_long, caddr_t); 220 static void dc_init (void *); 221 static void dc_stop (struct dc_softc *); 222 static void dc_watchdog (struct ifnet *); 223 static void dc_shutdown (device_t); 224 static int dc_ifmedia_upd (struct ifnet *); 225 static void dc_ifmedia_sts (struct ifnet *, struct ifmediareq *); 226 227 static void dc_delay (struct dc_softc *); 228 static void dc_eeprom_idle (struct dc_softc *); 229 static void dc_eeprom_putbyte (struct dc_softc *, int); 230 static void dc_eeprom_getword (struct dc_softc *, int, u_int16_t *); 231 static void dc_eeprom_getword_pnic 232 (struct dc_softc *, int, u_int16_t *); 233 static void dc_eeprom_getword_xircom 234 (struct dc_softc *, int, u_int16_t *); 235 static void dc_eeprom_width (struct dc_softc *); 236 static void dc_read_eeprom (struct dc_softc *, caddr_t, int, int, int); 237 238 static void dc_mii_writebit (struct dc_softc *, int); 239 static int dc_mii_readbit (struct dc_softc *); 240 static void dc_mii_sync (struct dc_softc *); 241 static void dc_mii_send (struct dc_softc *, u_int32_t, int); 242 static int dc_mii_readreg (struct dc_softc *, struct dc_mii_frame *); 243 static int dc_mii_writereg (struct dc_softc *, struct dc_mii_frame *); 244 static int dc_miibus_readreg (device_t, int, int); 245 static int dc_miibus_writereg (device_t, int, int, int); 246 static void dc_miibus_statchg (device_t); 247 static void dc_miibus_mediainit (device_t); 248 249 static void dc_setcfg (struct dc_softc *, int); 250 static u_int32_t dc_crc_le (struct dc_softc *, caddr_t); 251 static u_int32_t dc_crc_be (caddr_t); 252 static void dc_setfilt_21143 (struct dc_softc *); 253 static void dc_setfilt_asix (struct dc_softc *); 254 static void dc_setfilt_admtek (struct dc_softc *); 255 static void dc_setfilt_xircom (struct dc_softc *); 256 257 static void dc_setfilt (struct dc_softc *); 258 259 static void dc_reset (struct dc_softc *); 260 static int dc_list_rx_init (struct dc_softc *); 261 static int dc_list_tx_init (struct dc_softc *); 262 263 static void dc_read_srom (struct dc_softc *, int); 264 static void dc_parse_21143_srom (struct dc_softc *); 265 static void dc_decode_leaf_sia (struct dc_softc *, struct dc_eblock_sia *); 266 static void dc_decode_leaf_mii (struct dc_softc *, struct dc_eblock_mii *); 267 static void dc_decode_leaf_sym (struct dc_softc *, struct dc_eblock_sym *); 268 static void dc_apply_fixup (struct dc_softc *, int); 269 270 #ifdef DC_USEIOSPACE 271 #define DC_RES SYS_RES_IOPORT 272 #define DC_RID DC_PCI_CFBIO 273 #else 274 #define DC_RES SYS_RES_MEMORY 275 #define DC_RID DC_PCI_CFBMA 276 #endif 277 278 static device_method_t dc_methods[] = { 279 /* Device interface */ 280 DEVMETHOD(device_probe, dc_probe), 281 DEVMETHOD(device_attach, dc_attach), 282 DEVMETHOD(device_detach, dc_detach), 283 DEVMETHOD(device_suspend, dc_suspend), 284 DEVMETHOD(device_resume, dc_resume), 285 DEVMETHOD(device_shutdown, dc_shutdown), 286 287 /* bus interface */ 288 DEVMETHOD(bus_print_child, bus_generic_print_child), 289 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 290 291 /* MII interface */ 292 DEVMETHOD(miibus_readreg, dc_miibus_readreg), 293 DEVMETHOD(miibus_writereg, dc_miibus_writereg), 294 DEVMETHOD(miibus_statchg, dc_miibus_statchg), 295 DEVMETHOD(miibus_mediainit, dc_miibus_mediainit), 296 297 { 0, 0 } 298 }; 299 300 static driver_t dc_driver = { 301 "dc", 302 dc_methods, 303 sizeof(struct dc_softc) 304 }; 305 306 static devclass_t dc_devclass; 307 #ifdef __i386__ 308 static int dc_quick=1; 309 SYSCTL_INT(_hw, OID_AUTO, dc_quick, CTLFLAG_RW, 310 &dc_quick,0,"do not mdevget in dc driver"); 311 #endif 312 313 DRIVER_MODULE(dc, cardbus, dc_driver, dc_devclass, 0, 0); 314 DRIVER_MODULE(dc, pci, dc_driver, dc_devclass, 0, 0); 315 DRIVER_MODULE(miibus, dc, miibus_driver, miibus_devclass, 0, 0); 316 317 #define DC_SETBIT(sc, reg, x) \ 318 CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) | (x)) 319 320 #define DC_CLRBIT(sc, reg, x) \ 321 CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) & ~(x)) 322 323 #define SIO_SET(x) DC_SETBIT(sc, DC_SIO, (x)) 324 #define SIO_CLR(x) DC_CLRBIT(sc, DC_SIO, (x)) 325 326 #define IS_MPSAFE 0 327 328 static void 329 dc_delay(sc) 330 struct dc_softc *sc; 331 { 332 int idx; 333 334 for (idx = (300 / 33) + 1; idx > 0; idx--) 335 CSR_READ_4(sc, DC_BUSCTL); 336 } 337 338 static void 339 dc_eeprom_width(sc) 340 struct dc_softc *sc; 341 { 342 int i; 343 344 /* Force EEPROM to idle state. */ 345 dc_eeprom_idle(sc); 346 347 /* Enter EEPROM access mode. */ 348 CSR_WRITE_4(sc, DC_SIO, DC_SIO_EESEL); 349 dc_delay(sc); 350 DC_SETBIT(sc, DC_SIO, DC_SIO_ROMCTL_READ); 351 dc_delay(sc); 352 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); 353 dc_delay(sc); 354 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CS); 355 dc_delay(sc); 356 357 for (i = 3; i--;) { 358 if (6 & (1 << i)) 359 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_DATAIN); 360 else 361 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_DATAIN); 362 dc_delay(sc); 363 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CLK); 364 dc_delay(sc); 365 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); 366 dc_delay(sc); 367 } 368 369 for (i = 1; i <= 12; i++) { 370 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CLK); 371 dc_delay(sc); 372 if (!(CSR_READ_4(sc, DC_SIO) & DC_SIO_EE_DATAOUT)) { 373 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); 374 dc_delay(sc); 375 break; 376 } 377 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); 378 dc_delay(sc); 379 } 380 381 /* Turn off EEPROM access mode. */ 382 dc_eeprom_idle(sc); 383 384 if (i < 4 || i > 12) 385 sc->dc_romwidth = 6; 386 else 387 sc->dc_romwidth = i; 388 389 /* Enter EEPROM access mode. */ 390 CSR_WRITE_4(sc, DC_SIO, DC_SIO_EESEL); 391 dc_delay(sc); 392 DC_SETBIT(sc, DC_SIO, DC_SIO_ROMCTL_READ); 393 dc_delay(sc); 394 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); 395 dc_delay(sc); 396 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CS); 397 dc_delay(sc); 398 399 /* Turn off EEPROM access mode. */ 400 dc_eeprom_idle(sc); 401 } 402 403 static void 404 dc_eeprom_idle(sc) 405 struct dc_softc *sc; 406 { 407 register int i; 408 409 CSR_WRITE_4(sc, DC_SIO, DC_SIO_EESEL); 410 dc_delay(sc); 411 DC_SETBIT(sc, DC_SIO, DC_SIO_ROMCTL_READ); 412 dc_delay(sc); 413 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); 414 dc_delay(sc); 415 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CS); 416 dc_delay(sc); 417 418 for (i = 0; i < 25; i++) { 419 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); 420 dc_delay(sc); 421 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CLK); 422 dc_delay(sc); 423 } 424 425 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); 426 dc_delay(sc); 427 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CS); 428 dc_delay(sc); 429 CSR_WRITE_4(sc, DC_SIO, 0x00000000); 430 431 return; 432 } 433 434 /* 435 * Send a read command and address to the EEPROM, check for ACK. 436 */ 437 static void 438 dc_eeprom_putbyte(sc, addr) 439 struct dc_softc *sc; 440 int addr; 441 { 442 register int d, i; 443 444 d = DC_EECMD_READ >> 6; 445 for (i = 3; i--; ) { 446 if (d & (1 << i)) 447 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_DATAIN); 448 else 449 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_DATAIN); 450 dc_delay(sc); 451 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CLK); 452 dc_delay(sc); 453 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); 454 dc_delay(sc); 455 } 456 457 /* 458 * Feed in each bit and strobe the clock. 459 */ 460 for (i = sc->dc_romwidth; i--;) { 461 if (addr & (1 << i)) { 462 SIO_SET(DC_SIO_EE_DATAIN); 463 } else { 464 SIO_CLR(DC_SIO_EE_DATAIN); 465 } 466 dc_delay(sc); 467 SIO_SET(DC_SIO_EE_CLK); 468 dc_delay(sc); 469 SIO_CLR(DC_SIO_EE_CLK); 470 dc_delay(sc); 471 } 472 473 return; 474 } 475 476 /* 477 * Read a word of data stored in the EEPROM at address 'addr.' 478 * The PNIC 82c168/82c169 has its own non-standard way to read 479 * the EEPROM. 480 */ 481 static void 482 dc_eeprom_getword_pnic(sc, addr, dest) 483 struct dc_softc *sc; 484 int addr; 485 u_int16_t *dest; 486 { 487 register int i; 488 u_int32_t r; 489 490 CSR_WRITE_4(sc, DC_PN_SIOCTL, DC_PN_EEOPCODE_READ|addr); 491 492 for (i = 0; i < DC_TIMEOUT; i++) { 493 DELAY(1); 494 r = CSR_READ_4(sc, DC_SIO); 495 if (!(r & DC_PN_SIOCTL_BUSY)) { 496 *dest = (u_int16_t)(r & 0xFFFF); 497 return; 498 } 499 } 500 501 return; 502 } 503 504 /* 505 * Read a word of data stored in the EEPROM at address 'addr.' 506 * The Xircom X3201 has its own non-standard way to read 507 * the EEPROM, too. 508 */ 509 static void 510 dc_eeprom_getword_xircom(sc, addr, dest) 511 struct dc_softc *sc; 512 int addr; 513 u_int16_t *dest; 514 { 515 SIO_SET(DC_SIO_ROMSEL | DC_SIO_ROMCTL_READ); 516 517 addr *= 2; 518 CSR_WRITE_4(sc, DC_ROM, addr | 0x160); 519 *dest = (u_int16_t)CSR_READ_4(sc, DC_SIO)&0xff; 520 addr += 1; 521 CSR_WRITE_4(sc, DC_ROM, addr | 0x160); 522 *dest |= ((u_int16_t)CSR_READ_4(sc, DC_SIO)&0xff) << 8; 523 524 SIO_CLR(DC_SIO_ROMSEL | DC_SIO_ROMCTL_READ); 525 return; 526 } 527 528 /* 529 * Read a word of data stored in the EEPROM at address 'addr.' 530 */ 531 static void 532 dc_eeprom_getword(sc, addr, dest) 533 struct dc_softc *sc; 534 int addr; 535 u_int16_t *dest; 536 { 537 register int i; 538 u_int16_t word = 0; 539 540 /* Force EEPROM to idle state. */ 541 dc_eeprom_idle(sc); 542 543 /* Enter EEPROM access mode. */ 544 CSR_WRITE_4(sc, DC_SIO, DC_SIO_EESEL); 545 dc_delay(sc); 546 DC_SETBIT(sc, DC_SIO, DC_SIO_ROMCTL_READ); 547 dc_delay(sc); 548 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); 549 dc_delay(sc); 550 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CS); 551 dc_delay(sc); 552 553 /* 554 * Send address of word we want to read. 555 */ 556 dc_eeprom_putbyte(sc, addr); 557 558 /* 559 * Start reading bits from EEPROM. 560 */ 561 for (i = 0x8000; i; i >>= 1) { 562 SIO_SET(DC_SIO_EE_CLK); 563 dc_delay(sc); 564 if (CSR_READ_4(sc, DC_SIO) & DC_SIO_EE_DATAOUT) 565 word |= i; 566 dc_delay(sc); 567 SIO_CLR(DC_SIO_EE_CLK); 568 dc_delay(sc); 569 } 570 571 /* Turn off EEPROM access mode. */ 572 dc_eeprom_idle(sc); 573 574 *dest = word; 575 576 return; 577 } 578 579 /* 580 * Read a sequence of words from the EEPROM. 581 */ 582 static void 583 dc_read_eeprom(sc, dest, off, cnt, swap) 584 struct dc_softc *sc; 585 caddr_t dest; 586 int off; 587 int cnt; 588 int swap; 589 { 590 int i; 591 u_int16_t word = 0, *ptr; 592 593 for (i = 0; i < cnt; i++) { 594 if (DC_IS_PNIC(sc)) 595 dc_eeprom_getword_pnic(sc, off + i, &word); 596 else if (DC_IS_XIRCOM(sc)) 597 dc_eeprom_getword_xircom(sc, off + i, &word); 598 else 599 dc_eeprom_getword(sc, off + i, &word); 600 ptr = (u_int16_t *)(dest + (i * 2)); 601 if (swap) 602 *ptr = ntohs(word); 603 else 604 *ptr = word; 605 } 606 607 return; 608 } 609 610 /* 611 * The following two routines are taken from the Macronix 98713 612 * Application Notes pp.19-21. 613 */ 614 /* 615 * Write a bit to the MII bus. 616 */ 617 static void 618 dc_mii_writebit(sc, bit) 619 struct dc_softc *sc; 620 int bit; 621 { 622 if (bit) 623 CSR_WRITE_4(sc, DC_SIO, 624 DC_SIO_ROMCTL_WRITE|DC_SIO_MII_DATAOUT); 625 else 626 CSR_WRITE_4(sc, DC_SIO, DC_SIO_ROMCTL_WRITE); 627 628 DC_SETBIT(sc, DC_SIO, DC_SIO_MII_CLK); 629 DC_CLRBIT(sc, DC_SIO, DC_SIO_MII_CLK); 630 631 return; 632 } 633 634 /* 635 * Read a bit from the MII bus. 636 */ 637 static int 638 dc_mii_readbit(sc) 639 struct dc_softc *sc; 640 { 641 CSR_WRITE_4(sc, DC_SIO, DC_SIO_ROMCTL_READ|DC_SIO_MII_DIR); 642 CSR_READ_4(sc, DC_SIO); 643 DC_SETBIT(sc, DC_SIO, DC_SIO_MII_CLK); 644 DC_CLRBIT(sc, DC_SIO, DC_SIO_MII_CLK); 645 if (CSR_READ_4(sc, DC_SIO) & DC_SIO_MII_DATAIN) 646 return(1); 647 648 return(0); 649 } 650 651 /* 652 * Sync the PHYs by setting data bit and strobing the clock 32 times. 653 */ 654 static void 655 dc_mii_sync(sc) 656 struct dc_softc *sc; 657 { 658 register int i; 659 660 CSR_WRITE_4(sc, DC_SIO, DC_SIO_ROMCTL_WRITE); 661 662 for (i = 0; i < 32; i++) 663 dc_mii_writebit(sc, 1); 664 665 return; 666 } 667 668 /* 669 * Clock a series of bits through the MII. 670 */ 671 static void 672 dc_mii_send(sc, bits, cnt) 673 struct dc_softc *sc; 674 u_int32_t bits; 675 int cnt; 676 { 677 int i; 678 679 for (i = (0x1 << (cnt - 1)); i; i >>= 1) 680 dc_mii_writebit(sc, bits & i); 681 } 682 683 /* 684 * Read an PHY register through the MII. 685 */ 686 static int 687 dc_mii_readreg(sc, frame) 688 struct dc_softc *sc; 689 struct dc_mii_frame *frame; 690 691 { 692 int i, ack; 693 694 DC_LOCK(sc); 695 696 /* 697 * Set up frame for RX. 698 */ 699 frame->mii_stdelim = DC_MII_STARTDELIM; 700 frame->mii_opcode = DC_MII_READOP; 701 frame->mii_turnaround = 0; 702 frame->mii_data = 0; 703 704 /* 705 * Sync the PHYs. 706 */ 707 dc_mii_sync(sc); 708 709 /* 710 * Send command/address info. 711 */ 712 dc_mii_send(sc, frame->mii_stdelim, 2); 713 dc_mii_send(sc, frame->mii_opcode, 2); 714 dc_mii_send(sc, frame->mii_phyaddr, 5); 715 dc_mii_send(sc, frame->mii_regaddr, 5); 716 717 #ifdef notdef 718 /* Idle bit */ 719 dc_mii_writebit(sc, 1); 720 dc_mii_writebit(sc, 0); 721 #endif 722 723 /* Check for ack */ 724 ack = dc_mii_readbit(sc); 725 726 /* 727 * Now try reading data bits. If the ack failed, we still 728 * need to clock through 16 cycles to keep the PHY(s) in sync. 729 */ 730 if (ack) { 731 for(i = 0; i < 16; i++) { 732 dc_mii_readbit(sc); 733 } 734 goto fail; 735 } 736 737 for (i = 0x8000; i; i >>= 1) { 738 if (!ack) { 739 if (dc_mii_readbit(sc)) 740 frame->mii_data |= i; 741 } 742 } 743 744 fail: 745 746 dc_mii_writebit(sc, 0); 747 dc_mii_writebit(sc, 0); 748 749 DC_UNLOCK(sc); 750 751 if (ack) 752 return(1); 753 return(0); 754 } 755 756 /* 757 * Write to a PHY register through the MII. 758 */ 759 static int 760 dc_mii_writereg(sc, frame) 761 struct dc_softc *sc; 762 struct dc_mii_frame *frame; 763 764 { 765 DC_LOCK(sc); 766 /* 767 * Set up frame for TX. 768 */ 769 770 frame->mii_stdelim = DC_MII_STARTDELIM; 771 frame->mii_opcode = DC_MII_WRITEOP; 772 frame->mii_turnaround = DC_MII_TURNAROUND; 773 774 /* 775 * Sync the PHYs. 776 */ 777 dc_mii_sync(sc); 778 779 dc_mii_send(sc, frame->mii_stdelim, 2); 780 dc_mii_send(sc, frame->mii_opcode, 2); 781 dc_mii_send(sc, frame->mii_phyaddr, 5); 782 dc_mii_send(sc, frame->mii_regaddr, 5); 783 dc_mii_send(sc, frame->mii_turnaround, 2); 784 dc_mii_send(sc, frame->mii_data, 16); 785 786 /* Idle bit. */ 787 dc_mii_writebit(sc, 0); 788 dc_mii_writebit(sc, 0); 789 790 DC_UNLOCK(sc); 791 792 return(0); 793 } 794 795 static int 796 dc_miibus_readreg(dev, phy, reg) 797 device_t dev; 798 int phy, reg; 799 { 800 struct dc_mii_frame frame; 801 struct dc_softc *sc; 802 int i, rval, phy_reg = 0; 803 804 sc = device_get_softc(dev); 805 bzero((char *)&frame, sizeof(frame)); 806 807 /* 808 * Note: both the AL981 and AN985 have internal PHYs, 809 * however the AL981 provides direct access to the PHY 810 * registers while the AN985 uses a serial MII interface. 811 * The AN985's MII interface is also buggy in that you 812 * can read from any MII address (0 to 31), but only address 1 813 * behaves normally. To deal with both cases, we pretend 814 * that the PHY is at MII address 1. 815 */ 816 if (DC_IS_ADMTEK(sc) && phy != DC_ADMTEK_PHYADDR) 817 return(0); 818 819 /* 820 * Note: the ukphy probes of the RS7112 report a PHY at 821 * MII address 0 (possibly HomePNA?) and 1 (ethernet) 822 * so we only respond to correct one. 823 */ 824 if (DC_IS_CONEXANT(sc) && phy != DC_CONEXANT_PHYADDR) 825 return(0); 826 827 if (sc->dc_pmode != DC_PMODE_MII) { 828 if (phy == (MII_NPHY - 1)) { 829 switch(reg) { 830 case MII_BMSR: 831 /* 832 * Fake something to make the probe 833 * code think there's a PHY here. 834 */ 835 return(BMSR_MEDIAMASK); 836 break; 837 case MII_PHYIDR1: 838 if (DC_IS_PNIC(sc)) 839 return(DC_VENDORID_LO); 840 return(DC_VENDORID_DEC); 841 break; 842 case MII_PHYIDR2: 843 if (DC_IS_PNIC(sc)) 844 return(DC_DEVICEID_82C168); 845 return(DC_DEVICEID_21143); 846 break; 847 default: 848 return(0); 849 break; 850 } 851 } else 852 return(0); 853 } 854 855 if (DC_IS_PNIC(sc)) { 856 CSR_WRITE_4(sc, DC_PN_MII, DC_PN_MIIOPCODE_READ | 857 (phy << 23) | (reg << 18)); 858 for (i = 0; i < DC_TIMEOUT; i++) { 859 DELAY(1); 860 rval = CSR_READ_4(sc, DC_PN_MII); 861 if (!(rval & DC_PN_MII_BUSY)) { 862 rval &= 0xFFFF; 863 return(rval == 0xFFFF ? 0 : rval); 864 } 865 } 866 return(0); 867 } 868 869 if (DC_IS_COMET(sc)) { 870 switch(reg) { 871 case MII_BMCR: 872 phy_reg = DC_AL_BMCR; 873 break; 874 case MII_BMSR: 875 phy_reg = DC_AL_BMSR; 876 break; 877 case MII_PHYIDR1: 878 phy_reg = DC_AL_VENID; 879 break; 880 case MII_PHYIDR2: 881 phy_reg = DC_AL_DEVID; 882 break; 883 case MII_ANAR: 884 phy_reg = DC_AL_ANAR; 885 break; 886 case MII_ANLPAR: 887 phy_reg = DC_AL_LPAR; 888 break; 889 case MII_ANER: 890 phy_reg = DC_AL_ANER; 891 break; 892 default: 893 printf("dc%d: phy_read: bad phy register %x\n", 894 sc->dc_unit, reg); 895 return(0); 896 break; 897 } 898 899 rval = CSR_READ_4(sc, phy_reg) & 0x0000FFFF; 900 901 if (rval == 0xFFFF) 902 return(0); 903 return(rval); 904 } 905 906 frame.mii_phyaddr = phy; 907 frame.mii_regaddr = reg; 908 if (sc->dc_type == DC_TYPE_98713) { 909 phy_reg = CSR_READ_4(sc, DC_NETCFG); 910 CSR_WRITE_4(sc, DC_NETCFG, phy_reg & ~DC_NETCFG_PORTSEL); 911 } 912 dc_mii_readreg(sc, &frame); 913 if (sc->dc_type == DC_TYPE_98713) 914 CSR_WRITE_4(sc, DC_NETCFG, phy_reg); 915 916 return(frame.mii_data); 917 } 918 919 static int 920 dc_miibus_writereg(dev, phy, reg, data) 921 device_t dev; 922 int phy, reg, data; 923 { 924 struct dc_softc *sc; 925 struct dc_mii_frame frame; 926 int i, phy_reg = 0; 927 928 sc = device_get_softc(dev); 929 bzero((char *)&frame, sizeof(frame)); 930 931 if (DC_IS_ADMTEK(sc) && phy != DC_ADMTEK_PHYADDR) 932 return(0); 933 934 if (DC_IS_CONEXANT(sc) && phy != DC_CONEXANT_PHYADDR) 935 return(0); 936 937 if (DC_IS_PNIC(sc)) { 938 CSR_WRITE_4(sc, DC_PN_MII, DC_PN_MIIOPCODE_WRITE | 939 (phy << 23) | (reg << 10) | data); 940 for (i = 0; i < DC_TIMEOUT; i++) { 941 if (!(CSR_READ_4(sc, DC_PN_MII) & DC_PN_MII_BUSY)) 942 break; 943 } 944 return(0); 945 } 946 947 if (DC_IS_COMET(sc)) { 948 switch(reg) { 949 case MII_BMCR: 950 phy_reg = DC_AL_BMCR; 951 break; 952 case MII_BMSR: 953 phy_reg = DC_AL_BMSR; 954 break; 955 case MII_PHYIDR1: 956 phy_reg = DC_AL_VENID; 957 break; 958 case MII_PHYIDR2: 959 phy_reg = DC_AL_DEVID; 960 break; 961 case MII_ANAR: 962 phy_reg = DC_AL_ANAR; 963 break; 964 case MII_ANLPAR: 965 phy_reg = DC_AL_LPAR; 966 break; 967 case MII_ANER: 968 phy_reg = DC_AL_ANER; 969 break; 970 default: 971 printf("dc%d: phy_write: bad phy register %x\n", 972 sc->dc_unit, reg); 973 return(0); 974 break; 975 } 976 977 CSR_WRITE_4(sc, phy_reg, data); 978 return(0); 979 } 980 981 frame.mii_phyaddr = phy; 982 frame.mii_regaddr = reg; 983 frame.mii_data = data; 984 985 if (sc->dc_type == DC_TYPE_98713) { 986 phy_reg = CSR_READ_4(sc, DC_NETCFG); 987 CSR_WRITE_4(sc, DC_NETCFG, phy_reg & ~DC_NETCFG_PORTSEL); 988 } 989 dc_mii_writereg(sc, &frame); 990 if (sc->dc_type == DC_TYPE_98713) 991 CSR_WRITE_4(sc, DC_NETCFG, phy_reg); 992 993 return(0); 994 } 995 996 static void 997 dc_miibus_statchg(dev) 998 device_t dev; 999 { 1000 struct dc_softc *sc; 1001 struct mii_data *mii; 1002 struct ifmedia *ifm; 1003 1004 sc = device_get_softc(dev); 1005 if (DC_IS_ADMTEK(sc)) 1006 return; 1007 1008 mii = device_get_softc(sc->dc_miibus); 1009 ifm = &mii->mii_media; 1010 if (DC_IS_DAVICOM(sc) && 1011 IFM_SUBTYPE(ifm->ifm_media) == IFM_HPNA_1) { 1012 dc_setcfg(sc, ifm->ifm_media); 1013 sc->dc_if_media = ifm->ifm_media; 1014 } else { 1015 dc_setcfg(sc, mii->mii_media_active); 1016 sc->dc_if_media = mii->mii_media_active; 1017 } 1018 1019 return; 1020 } 1021 1022 /* 1023 * Special support for DM9102A cards with HomePNA PHYs. Note: 1024 * with the Davicom DM9102A/DM9801 eval board that I have, it seems 1025 * to be impossible to talk to the management interface of the DM9801 1026 * PHY (its MDIO pin is not connected to anything). Consequently, 1027 * the driver has to just 'know' about the additional mode and deal 1028 * with it itself. *sigh* 1029 */ 1030 static void 1031 dc_miibus_mediainit(dev) 1032 device_t dev; 1033 { 1034 struct dc_softc *sc; 1035 struct mii_data *mii; 1036 struct ifmedia *ifm; 1037 int rev; 1038 1039 rev = pci_read_config(dev, DC_PCI_CFRV, 4) & 0xFF; 1040 1041 sc = device_get_softc(dev); 1042 mii = device_get_softc(sc->dc_miibus); 1043 ifm = &mii->mii_media; 1044 1045 if (DC_IS_DAVICOM(sc) && rev >= DC_REVISION_DM9102A) 1046 ifmedia_add(ifm, IFM_ETHER|IFM_HPNA_1, 0, NULL); 1047 1048 return; 1049 } 1050 1051 #define DC_POLY 0xEDB88320 1052 #define DC_BITS_512 9 1053 #define DC_BITS_128 7 1054 #define DC_BITS_64 6 1055 1056 static u_int32_t 1057 dc_crc_le(sc, addr) 1058 struct dc_softc *sc; 1059 caddr_t addr; 1060 { 1061 u_int32_t idx, bit, data, crc; 1062 1063 /* Compute CRC for the address value. */ 1064 crc = 0xFFFFFFFF; /* initial value */ 1065 1066 for (idx = 0; idx < 6; idx++) { 1067 for (data = *addr++, bit = 0; bit < 8; bit++, data >>= 1) 1068 crc = (crc >> 1) ^ (((crc ^ data) & 1) ? DC_POLY : 0); 1069 } 1070 1071 /* 1072 * The hash table on the PNIC II and the MX98715AEC-C/D/E 1073 * chips is only 128 bits wide. 1074 */ 1075 if (sc->dc_flags & DC_128BIT_HASH) 1076 return (crc & ((1 << DC_BITS_128) - 1)); 1077 1078 /* The hash table on the MX98715BEC is only 64 bits wide. */ 1079 if (sc->dc_flags & DC_64BIT_HASH) 1080 return (crc & ((1 << DC_BITS_64) - 1)); 1081 1082 /* Xircom's hash filtering table is different (read: weird) */ 1083 /* Xircom uses the LEAST significant bits */ 1084 if (DC_IS_XIRCOM(sc)) { 1085 if ((crc & 0x180) == 0x180) 1086 return (crc & 0x0F) + (crc & 0x70)*3 + (14 << 4); 1087 else 1088 return (crc & 0x1F) + ((crc>>1) & 0xF0)*3 + (12 << 4); 1089 } 1090 1091 return (crc & ((1 << DC_BITS_512) - 1)); 1092 } 1093 1094 /* 1095 * Calculate CRC of a multicast group address, return the lower 6 bits. 1096 */ 1097 static u_int32_t 1098 dc_crc_be(addr) 1099 caddr_t addr; 1100 { 1101 u_int32_t crc, carry; 1102 int i, j; 1103 u_int8_t c; 1104 1105 /* Compute CRC for the address value. */ 1106 crc = 0xFFFFFFFF; /* initial value */ 1107 1108 for (i = 0; i < 6; i++) { 1109 c = *(addr + i); 1110 for (j = 0; j < 8; j++) { 1111 carry = ((crc & 0x80000000) ? 1 : 0) ^ (c & 0x01); 1112 crc <<= 1; 1113 c >>= 1; 1114 if (carry) 1115 crc = (crc ^ 0x04c11db6) | carry; 1116 } 1117 } 1118 1119 /* return the filter bit position */ 1120 return((crc >> 26) & 0x0000003F); 1121 } 1122 1123 /* 1124 * 21143-style RX filter setup routine. Filter programming is done by 1125 * downloading a special setup frame into the TX engine. 21143, Macronix, 1126 * PNIC, PNIC II and Davicom chips are programmed this way. 1127 * 1128 * We always program the chip using 'hash perfect' mode, i.e. one perfect 1129 * address (our node address) and a 512-bit hash filter for multicast 1130 * frames. We also sneak the broadcast address into the hash filter since 1131 * we need that too. 1132 */ 1133 static void 1134 dc_setfilt_21143(sc) 1135 struct dc_softc *sc; 1136 { 1137 struct dc_desc *sframe; 1138 u_int32_t h, *sp; 1139 struct ifmultiaddr *ifma; 1140 struct ifnet *ifp; 1141 int i; 1142 1143 ifp = &sc->arpcom.ac_if; 1144 1145 i = sc->dc_cdata.dc_tx_prod; 1146 DC_INC(sc->dc_cdata.dc_tx_prod, DC_TX_LIST_CNT); 1147 sc->dc_cdata.dc_tx_cnt++; 1148 sframe = &sc->dc_ldata->dc_tx_list[i]; 1149 sp = (u_int32_t *)&sc->dc_cdata.dc_sbuf; 1150 bzero((char *)sp, DC_SFRAME_LEN); 1151 1152 sframe->dc_data = vtophys(&sc->dc_cdata.dc_sbuf); 1153 sframe->dc_ctl = DC_SFRAME_LEN | DC_TXCTL_SETUP | DC_TXCTL_TLINK | 1154 DC_FILTER_HASHPERF | DC_TXCTL_FINT; 1155 1156 sc->dc_cdata.dc_tx_chain[i] = (struct mbuf *)&sc->dc_cdata.dc_sbuf; 1157 1158 /* If we want promiscuous mode, set the allframes bit. */ 1159 if (ifp->if_flags & IFF_PROMISC) 1160 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC); 1161 else 1162 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC); 1163 1164 if (ifp->if_flags & IFF_ALLMULTI) 1165 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI); 1166 else 1167 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI); 1168 1169 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 1170 if (ifma->ifma_addr->sa_family != AF_LINK) 1171 continue; 1172 h = dc_crc_le(sc, 1173 LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 1174 sp[h >> 4] |= 1 << (h & 0xF); 1175 } 1176 1177 if (ifp->if_flags & IFF_BROADCAST) { 1178 h = dc_crc_le(sc, (caddr_t)ifp->if_broadcastaddr); 1179 sp[h >> 4] |= 1 << (h & 0xF); 1180 } 1181 1182 /* Set our MAC address */ 1183 sp[39] = ((u_int16_t *)sc->arpcom.ac_enaddr)[0]; 1184 sp[40] = ((u_int16_t *)sc->arpcom.ac_enaddr)[1]; 1185 sp[41] = ((u_int16_t *)sc->arpcom.ac_enaddr)[2]; 1186 1187 sframe->dc_status = DC_TXSTAT_OWN; 1188 CSR_WRITE_4(sc, DC_TXSTART, 0xFFFFFFFF); 1189 1190 /* 1191 * The PNIC takes an exceedingly long time to process its 1192 * setup frame; wait 10ms after posting the setup frame 1193 * before proceeding, just so it has time to swallow its 1194 * medicine. 1195 */ 1196 DELAY(10000); 1197 1198 ifp->if_timer = 5; 1199 1200 return; 1201 } 1202 1203 static void 1204 dc_setfilt_admtek(sc) 1205 struct dc_softc *sc; 1206 { 1207 struct ifnet *ifp; 1208 int h = 0; 1209 u_int32_t hashes[2] = { 0, 0 }; 1210 struct ifmultiaddr *ifma; 1211 1212 ifp = &sc->arpcom.ac_if; 1213 1214 /* Init our MAC address */ 1215 CSR_WRITE_4(sc, DC_AL_PAR0, *(u_int32_t *)(&sc->arpcom.ac_enaddr[0])); 1216 CSR_WRITE_4(sc, DC_AL_PAR1, *(u_int32_t *)(&sc->arpcom.ac_enaddr[4])); 1217 1218 /* If we want promiscuous mode, set the allframes bit. */ 1219 if (ifp->if_flags & IFF_PROMISC) 1220 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC); 1221 else 1222 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC); 1223 1224 if (ifp->if_flags & IFF_ALLMULTI) 1225 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI); 1226 else 1227 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI); 1228 1229 /* first, zot all the existing hash bits */ 1230 CSR_WRITE_4(sc, DC_AL_MAR0, 0); 1231 CSR_WRITE_4(sc, DC_AL_MAR1, 0); 1232 1233 /* 1234 * If we're already in promisc or allmulti mode, we 1235 * don't have to bother programming the multicast filter. 1236 */ 1237 if (ifp->if_flags & (IFF_PROMISC|IFF_ALLMULTI)) 1238 return; 1239 1240 /* now program new ones */ 1241 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 1242 if (ifma->ifma_addr->sa_family != AF_LINK) 1243 continue; 1244 if (DC_IS_CENTAUR(sc)) 1245 h = dc_crc_le(sc, LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 1246 else 1247 h = dc_crc_be(LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 1248 if (h < 32) 1249 hashes[0] |= (1 << h); 1250 else 1251 hashes[1] |= (1 << (h - 32)); 1252 } 1253 1254 CSR_WRITE_4(sc, DC_AL_MAR0, hashes[0]); 1255 CSR_WRITE_4(sc, DC_AL_MAR1, hashes[1]); 1256 1257 return; 1258 } 1259 1260 static void 1261 dc_setfilt_asix(sc) 1262 struct dc_softc *sc; 1263 { 1264 struct ifnet *ifp; 1265 int h = 0; 1266 u_int32_t hashes[2] = { 0, 0 }; 1267 struct ifmultiaddr *ifma; 1268 1269 ifp = &sc->arpcom.ac_if; 1270 1271 /* Init our MAC address */ 1272 CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_PAR0); 1273 CSR_WRITE_4(sc, DC_AX_FILTDATA, 1274 *(u_int32_t *)(&sc->arpcom.ac_enaddr[0])); 1275 CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_PAR1); 1276 CSR_WRITE_4(sc, DC_AX_FILTDATA, 1277 *(u_int32_t *)(&sc->arpcom.ac_enaddr[4])); 1278 1279 /* If we want promiscuous mode, set the allframes bit. */ 1280 if (ifp->if_flags & IFF_PROMISC) 1281 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC); 1282 else 1283 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC); 1284 1285 if (ifp->if_flags & IFF_ALLMULTI) 1286 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI); 1287 else 1288 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI); 1289 1290 /* 1291 * The ASIX chip has a special bit to enable reception 1292 * of broadcast frames. 1293 */ 1294 if (ifp->if_flags & IFF_BROADCAST) 1295 DC_SETBIT(sc, DC_NETCFG, DC_AX_NETCFG_RX_BROAD); 1296 else 1297 DC_CLRBIT(sc, DC_NETCFG, DC_AX_NETCFG_RX_BROAD); 1298 1299 /* first, zot all the existing hash bits */ 1300 CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_MAR0); 1301 CSR_WRITE_4(sc, DC_AX_FILTDATA, 0); 1302 CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_MAR1); 1303 CSR_WRITE_4(sc, DC_AX_FILTDATA, 0); 1304 1305 /* 1306 * If we're already in promisc or allmulti mode, we 1307 * don't have to bother programming the multicast filter. 1308 */ 1309 if (ifp->if_flags & (IFF_PROMISC|IFF_ALLMULTI)) 1310 return; 1311 1312 /* now program new ones */ 1313 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 1314 if (ifma->ifma_addr->sa_family != AF_LINK) 1315 continue; 1316 h = dc_crc_be(LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 1317 if (h < 32) 1318 hashes[0] |= (1 << h); 1319 else 1320 hashes[1] |= (1 << (h - 32)); 1321 } 1322 1323 CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_MAR0); 1324 CSR_WRITE_4(sc, DC_AX_FILTDATA, hashes[0]); 1325 CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_MAR1); 1326 CSR_WRITE_4(sc, DC_AX_FILTDATA, hashes[1]); 1327 1328 return; 1329 } 1330 1331 static void 1332 dc_setfilt_xircom(sc) 1333 struct dc_softc *sc; 1334 { 1335 struct dc_desc *sframe; 1336 u_int32_t h, *sp; 1337 struct ifmultiaddr *ifma; 1338 struct ifnet *ifp; 1339 int i; 1340 1341 ifp = &sc->arpcom.ac_if; 1342 DC_CLRBIT(sc, DC_NETCFG, (DC_NETCFG_TX_ON|DC_NETCFG_RX_ON)); 1343 1344 i = sc->dc_cdata.dc_tx_prod; 1345 DC_INC(sc->dc_cdata.dc_tx_prod, DC_TX_LIST_CNT); 1346 sc->dc_cdata.dc_tx_cnt++; 1347 sframe = &sc->dc_ldata->dc_tx_list[i]; 1348 sp = (u_int32_t *)&sc->dc_cdata.dc_sbuf; 1349 bzero((char *)sp, DC_SFRAME_LEN); 1350 1351 sframe->dc_data = vtophys(&sc->dc_cdata.dc_sbuf); 1352 sframe->dc_ctl = DC_SFRAME_LEN | DC_TXCTL_SETUP | DC_TXCTL_TLINK | 1353 DC_FILTER_HASHPERF | DC_TXCTL_FINT; 1354 1355 sc->dc_cdata.dc_tx_chain[i] = (struct mbuf *)&sc->dc_cdata.dc_sbuf; 1356 1357 /* If we want promiscuous mode, set the allframes bit. */ 1358 if (ifp->if_flags & IFF_PROMISC) 1359 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC); 1360 else 1361 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC); 1362 1363 if (ifp->if_flags & IFF_ALLMULTI) 1364 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI); 1365 else 1366 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI); 1367 1368 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 1369 if (ifma->ifma_addr->sa_family != AF_LINK) 1370 continue; 1371 h = dc_crc_le(sc, 1372 LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 1373 sp[h >> 4] |= 1 << (h & 0xF); 1374 } 1375 1376 if (ifp->if_flags & IFF_BROADCAST) { 1377 h = dc_crc_le(sc, (caddr_t)ifp->if_broadcastaddr); 1378 sp[h >> 4] |= 1 << (h & 0xF); 1379 } 1380 1381 /* Set our MAC address */ 1382 sp[0] = ((u_int16_t *)sc->arpcom.ac_enaddr)[0]; 1383 sp[1] = ((u_int16_t *)sc->arpcom.ac_enaddr)[1]; 1384 sp[2] = ((u_int16_t *)sc->arpcom.ac_enaddr)[2]; 1385 1386 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_TX_ON); 1387 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_ON); 1388 ifp->if_flags |= IFF_RUNNING; 1389 sframe->dc_status = DC_TXSTAT_OWN; 1390 CSR_WRITE_4(sc, DC_TXSTART, 0xFFFFFFFF); 1391 1392 /* 1393 * wait some time... 1394 */ 1395 DELAY(1000); 1396 1397 ifp->if_timer = 5; 1398 1399 return; 1400 } 1401 1402 static void 1403 dc_setfilt(sc) 1404 struct dc_softc *sc; 1405 { 1406 if (DC_IS_INTEL(sc) || DC_IS_MACRONIX(sc) || DC_IS_PNIC(sc) || 1407 DC_IS_PNICII(sc) || DC_IS_DAVICOM(sc) || DC_IS_CONEXANT(sc)) 1408 dc_setfilt_21143(sc); 1409 1410 if (DC_IS_ASIX(sc)) 1411 dc_setfilt_asix(sc); 1412 1413 if (DC_IS_ADMTEK(sc)) 1414 dc_setfilt_admtek(sc); 1415 1416 if (DC_IS_XIRCOM(sc)) 1417 dc_setfilt_xircom(sc); 1418 1419 return; 1420 } 1421 1422 /* 1423 * In order to fiddle with the 1424 * 'full-duplex' and '100Mbps' bits in the netconfig register, we 1425 * first have to put the transmit and/or receive logic in the idle state. 1426 */ 1427 static void 1428 dc_setcfg(sc, media) 1429 struct dc_softc *sc; 1430 int media; 1431 { 1432 int i, restart = 0; 1433 u_int32_t isr; 1434 1435 if (IFM_SUBTYPE(media) == IFM_NONE) 1436 return; 1437 1438 if (CSR_READ_4(sc, DC_NETCFG) & (DC_NETCFG_TX_ON|DC_NETCFG_RX_ON)) { 1439 restart = 1; 1440 DC_CLRBIT(sc, DC_NETCFG, (DC_NETCFG_TX_ON|DC_NETCFG_RX_ON)); 1441 1442 for (i = 0; i < DC_TIMEOUT; i++) { 1443 isr = CSR_READ_4(sc, DC_ISR); 1444 if (isr & DC_ISR_TX_IDLE && 1445 ((isr & DC_ISR_RX_STATE) == DC_RXSTATE_STOPPED || 1446 (isr & DC_ISR_RX_STATE) == DC_RXSTATE_WAIT)) 1447 break; 1448 DELAY(10); 1449 } 1450 1451 if (i == DC_TIMEOUT) 1452 printf("dc%d: failed to force tx and " 1453 "rx to idle state\n", sc->dc_unit); 1454 } 1455 1456 if (IFM_SUBTYPE(media) == IFM_100_TX) { 1457 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_SPEEDSEL); 1458 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_HEARTBEAT); 1459 if (sc->dc_pmode == DC_PMODE_MII) { 1460 int watchdogreg; 1461 1462 if (DC_IS_INTEL(sc)) { 1463 /* there's a write enable bit here that reads as 1 */ 1464 watchdogreg = CSR_READ_4(sc, DC_WATCHDOG); 1465 watchdogreg &= ~DC_WDOG_CTLWREN; 1466 watchdogreg |= DC_WDOG_JABBERDIS; 1467 CSR_WRITE_4(sc, DC_WATCHDOG, watchdogreg); 1468 } else { 1469 DC_SETBIT(sc, DC_WATCHDOG, DC_WDOG_JABBERDIS); 1470 } 1471 DC_CLRBIT(sc, DC_NETCFG, (DC_NETCFG_PCS| 1472 DC_NETCFG_PORTSEL|DC_NETCFG_SCRAMBLER)); 1473 if (sc->dc_type == DC_TYPE_98713) 1474 DC_SETBIT(sc, DC_NETCFG, (DC_NETCFG_PCS| 1475 DC_NETCFG_SCRAMBLER)); 1476 if (!DC_IS_DAVICOM(sc)) 1477 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL); 1478 DC_CLRBIT(sc, DC_10BTCTRL, 0xFFFF); 1479 if (DC_IS_INTEL(sc)) 1480 dc_apply_fixup(sc, IFM_AUTO); 1481 } else { 1482 if (DC_IS_PNIC(sc)) { 1483 DC_PN_GPIO_SETBIT(sc, DC_PN_GPIO_SPEEDSEL); 1484 DC_PN_GPIO_SETBIT(sc, DC_PN_GPIO_100TX_LOOP); 1485 DC_SETBIT(sc, DC_PN_NWAY, DC_PN_NWAY_SPEEDSEL); 1486 } 1487 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL); 1488 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PCS); 1489 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_SCRAMBLER); 1490 if (DC_IS_INTEL(sc)) 1491 dc_apply_fixup(sc, 1492 (media & IFM_GMASK) == IFM_FDX ? 1493 IFM_100_TX|IFM_FDX : IFM_100_TX); 1494 } 1495 } 1496 1497 if (IFM_SUBTYPE(media) == IFM_10_T) { 1498 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_SPEEDSEL); 1499 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_HEARTBEAT); 1500 if (sc->dc_pmode == DC_PMODE_MII) { 1501 int watchdogreg; 1502 1503 /* there's a write enable bit here that reads as 1 */ 1504 if (DC_IS_INTEL(sc)) { 1505 watchdogreg = CSR_READ_4(sc, DC_WATCHDOG); 1506 watchdogreg &= ~DC_WDOG_CTLWREN; 1507 watchdogreg |= DC_WDOG_JABBERDIS; 1508 CSR_WRITE_4(sc, DC_WATCHDOG, watchdogreg); 1509 } else { 1510 DC_SETBIT(sc, DC_WATCHDOG, DC_WDOG_JABBERDIS); 1511 } 1512 DC_CLRBIT(sc, DC_NETCFG, (DC_NETCFG_PCS| 1513 DC_NETCFG_PORTSEL|DC_NETCFG_SCRAMBLER)); 1514 if (sc->dc_type == DC_TYPE_98713) 1515 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PCS); 1516 if (!DC_IS_DAVICOM(sc)) 1517 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL); 1518 DC_CLRBIT(sc, DC_10BTCTRL, 0xFFFF); 1519 if (DC_IS_INTEL(sc)) 1520 dc_apply_fixup(sc, IFM_AUTO); 1521 } else { 1522 if (DC_IS_PNIC(sc)) { 1523 DC_PN_GPIO_CLRBIT(sc, DC_PN_GPIO_SPEEDSEL); 1524 DC_PN_GPIO_SETBIT(sc, DC_PN_GPIO_100TX_LOOP); 1525 DC_CLRBIT(sc, DC_PN_NWAY, DC_PN_NWAY_SPEEDSEL); 1526 } 1527 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL); 1528 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_PCS); 1529 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_SCRAMBLER); 1530 if (DC_IS_INTEL(sc)) { 1531 DC_CLRBIT(sc, DC_SIARESET, DC_SIA_RESET); 1532 DC_CLRBIT(sc, DC_10BTCTRL, 0xFFFF); 1533 if ((media & IFM_GMASK) == IFM_FDX) 1534 DC_SETBIT(sc, DC_10BTCTRL, 0x7F3D); 1535 else 1536 DC_SETBIT(sc, DC_10BTCTRL, 0x7F3F); 1537 DC_SETBIT(sc, DC_SIARESET, DC_SIA_RESET); 1538 DC_CLRBIT(sc, DC_10BTCTRL, 1539 DC_TCTL_AUTONEGENBL); 1540 dc_apply_fixup(sc, 1541 (media & IFM_GMASK) == IFM_FDX ? 1542 IFM_10_T|IFM_FDX : IFM_10_T); 1543 DELAY(20000); 1544 } 1545 } 1546 } 1547 1548 /* 1549 * If this is a Davicom DM9102A card with a DM9801 HomePNA 1550 * PHY and we want HomePNA mode, set the portsel bit to turn 1551 * on the external MII port. 1552 */ 1553 if (DC_IS_DAVICOM(sc)) { 1554 if (IFM_SUBTYPE(media) == IFM_HPNA_1) { 1555 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL); 1556 sc->dc_link = 1; 1557 } else { 1558 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL); 1559 } 1560 } 1561 1562 if ((media & IFM_GMASK) == IFM_FDX) { 1563 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_FULLDUPLEX); 1564 if (sc->dc_pmode == DC_PMODE_SYM && DC_IS_PNIC(sc)) 1565 DC_SETBIT(sc, DC_PN_NWAY, DC_PN_NWAY_DUPLEX); 1566 } else { 1567 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_FULLDUPLEX); 1568 if (sc->dc_pmode == DC_PMODE_SYM && DC_IS_PNIC(sc)) 1569 DC_CLRBIT(sc, DC_PN_NWAY, DC_PN_NWAY_DUPLEX); 1570 } 1571 1572 if (restart) 1573 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_TX_ON|DC_NETCFG_RX_ON); 1574 1575 return; 1576 } 1577 1578 static void 1579 dc_reset(sc) 1580 struct dc_softc *sc; 1581 { 1582 register int i; 1583 1584 DC_SETBIT(sc, DC_BUSCTL, DC_BUSCTL_RESET); 1585 1586 for (i = 0; i < DC_TIMEOUT; i++) { 1587 DELAY(10); 1588 if (!(CSR_READ_4(sc, DC_BUSCTL) & DC_BUSCTL_RESET)) 1589 break; 1590 } 1591 1592 if (DC_IS_ASIX(sc) || DC_IS_ADMTEK(sc) || DC_IS_CONEXANT(sc) || 1593 DC_IS_XIRCOM(sc) || DC_IS_INTEL(sc)) { 1594 DELAY(10000); 1595 DC_CLRBIT(sc, DC_BUSCTL, DC_BUSCTL_RESET); 1596 i = 0; 1597 } 1598 1599 if (i == DC_TIMEOUT) 1600 printf("dc%d: reset never completed!\n", sc->dc_unit); 1601 1602 /* Wait a little while for the chip to get its brains in order. */ 1603 DELAY(1000); 1604 1605 CSR_WRITE_4(sc, DC_IMR, 0x00000000); 1606 CSR_WRITE_4(sc, DC_BUSCTL, 0x00000000); 1607 CSR_WRITE_4(sc, DC_NETCFG, 0x00000000); 1608 1609 /* 1610 * Bring the SIA out of reset. In some cases, it looks 1611 * like failing to unreset the SIA soon enough gets it 1612 * into a state where it will never come out of reset 1613 * until we reset the whole chip again. 1614 */ 1615 if (DC_IS_INTEL(sc)) { 1616 DC_SETBIT(sc, DC_SIARESET, DC_SIA_RESET); 1617 CSR_WRITE_4(sc, DC_10BTCTRL, 0); 1618 CSR_WRITE_4(sc, DC_WATCHDOG, 0); 1619 } 1620 1621 return; 1622 } 1623 1624 static struct dc_type * 1625 dc_devtype(dev) 1626 device_t dev; 1627 { 1628 struct dc_type *t; 1629 u_int32_t rev; 1630 1631 t = dc_devs; 1632 1633 while(t->dc_name != NULL) { 1634 if ((pci_get_vendor(dev) == t->dc_vid) && 1635 (pci_get_device(dev) == t->dc_did)) { 1636 /* Check the PCI revision */ 1637 rev = pci_read_config(dev, DC_PCI_CFRV, 4) & 0xFF; 1638 if (t->dc_did == DC_DEVICEID_98713 && 1639 rev >= DC_REVISION_98713A) 1640 t++; 1641 if (t->dc_did == DC_DEVICEID_98713_CP && 1642 rev >= DC_REVISION_98713A) 1643 t++; 1644 if (t->dc_did == DC_DEVICEID_987x5 && 1645 rev >= DC_REVISION_98715AEC_C) 1646 t++; 1647 if (t->dc_did == DC_DEVICEID_987x5 && 1648 rev >= DC_REVISION_98725) 1649 t++; 1650 if (t->dc_did == DC_DEVICEID_AX88140A && 1651 rev >= DC_REVISION_88141) 1652 t++; 1653 if (t->dc_did == DC_DEVICEID_82C168 && 1654 rev >= DC_REVISION_82C169) 1655 t++; 1656 if (t->dc_did == DC_DEVICEID_DM9102 && 1657 rev >= DC_REVISION_DM9102A) 1658 t++; 1659 return(t); 1660 } 1661 t++; 1662 } 1663 1664 return(NULL); 1665 } 1666 1667 /* 1668 * Probe for a 21143 or clone chip. Check the PCI vendor and device 1669 * IDs against our list and return a device name if we find a match. 1670 * We do a little bit of extra work to identify the exact type of 1671 * chip. The MX98713 and MX98713A have the same PCI vendor/device ID, 1672 * but different revision IDs. The same is true for 98715/98715A 1673 * chips and the 98725, as well as the ASIX and ADMtek chips. In some 1674 * cases, the exact chip revision affects driver behavior. 1675 */ 1676 static int 1677 dc_probe(dev) 1678 device_t dev; 1679 { 1680 struct dc_type *t; 1681 1682 t = dc_devtype(dev); 1683 1684 if (t != NULL) { 1685 device_set_desc(dev, t->dc_name); 1686 return(0); 1687 } 1688 1689 return(ENXIO); 1690 } 1691 1692 static void 1693 dc_acpi(dev) 1694 device_t dev; 1695 { 1696 int unit; 1697 1698 unit = device_get_unit(dev); 1699 1700 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) { 1701 u_int32_t iobase, membase, irq; 1702 1703 /* Save important PCI config data. */ 1704 iobase = pci_read_config(dev, DC_PCI_CFBIO, 4); 1705 membase = pci_read_config(dev, DC_PCI_CFBMA, 4); 1706 irq = pci_read_config(dev, DC_PCI_CFIT, 4); 1707 1708 /* Reset the power state. */ 1709 printf("dc%d: chip is in D%d power mode " 1710 "-- setting to D0\n", unit, 1711 pci_get_powerstate(dev)); 1712 pci_set_powerstate(dev, PCI_POWERSTATE_D0); 1713 1714 /* Restore PCI config data. */ 1715 pci_write_config(dev, DC_PCI_CFBIO, iobase, 4); 1716 pci_write_config(dev, DC_PCI_CFBMA, membase, 4); 1717 pci_write_config(dev, DC_PCI_CFIT, irq, 4); 1718 } 1719 1720 return; 1721 } 1722 1723 static void 1724 dc_apply_fixup(sc, media) 1725 struct dc_softc *sc; 1726 int media; 1727 { 1728 struct dc_mediainfo *m; 1729 u_int8_t *p; 1730 int i; 1731 u_int32_t reg; 1732 1733 m = sc->dc_mi; 1734 1735 while (m != NULL) { 1736 if (m->dc_media == media) 1737 break; 1738 m = m->dc_next; 1739 } 1740 1741 if (m == NULL) 1742 return; 1743 1744 for (i = 0, p = m->dc_reset_ptr; i < m->dc_reset_len; i++, p += 2) { 1745 reg = (p[0] | (p[1] << 8)) << 16; 1746 CSR_WRITE_4(sc, DC_WATCHDOG, reg); 1747 } 1748 1749 for (i = 0, p = m->dc_gp_ptr; i < m->dc_gp_len; i++, p += 2) { 1750 reg = (p[0] | (p[1] << 8)) << 16; 1751 CSR_WRITE_4(sc, DC_WATCHDOG, reg); 1752 } 1753 1754 return; 1755 } 1756 1757 static void 1758 dc_decode_leaf_sia(sc, l) 1759 struct dc_softc *sc; 1760 struct dc_eblock_sia *l; 1761 { 1762 struct dc_mediainfo *m; 1763 1764 m = malloc(sizeof(struct dc_mediainfo), M_DEVBUF, M_NOWAIT); 1765 bzero(m, sizeof(struct dc_mediainfo)); 1766 if (l->dc_sia_code == DC_SIA_CODE_10BT) 1767 m->dc_media = IFM_10_T; 1768 1769 if (l->dc_sia_code == DC_SIA_CODE_10BT_FDX) 1770 m->dc_media = IFM_10_T|IFM_FDX; 1771 1772 if (l->dc_sia_code == DC_SIA_CODE_10B2) 1773 m->dc_media = IFM_10_2; 1774 1775 if (l->dc_sia_code == DC_SIA_CODE_10B5) 1776 m->dc_media = IFM_10_5; 1777 1778 m->dc_gp_len = 2; 1779 m->dc_gp_ptr = (u_int8_t *)&l->dc_sia_gpio_ctl; 1780 1781 m->dc_next = sc->dc_mi; 1782 sc->dc_mi = m; 1783 1784 sc->dc_pmode = DC_PMODE_SIA; 1785 1786 return; 1787 } 1788 1789 static void 1790 dc_decode_leaf_sym(sc, l) 1791 struct dc_softc *sc; 1792 struct dc_eblock_sym *l; 1793 { 1794 struct dc_mediainfo *m; 1795 1796 m = malloc(sizeof(struct dc_mediainfo), M_DEVBUF, M_NOWAIT); 1797 bzero(m, sizeof(struct dc_mediainfo)); 1798 if (l->dc_sym_code == DC_SYM_CODE_100BT) 1799 m->dc_media = IFM_100_TX; 1800 1801 if (l->dc_sym_code == DC_SYM_CODE_100BT_FDX) 1802 m->dc_media = IFM_100_TX|IFM_FDX; 1803 1804 m->dc_gp_len = 2; 1805 m->dc_gp_ptr = (u_int8_t *)&l->dc_sym_gpio_ctl; 1806 1807 m->dc_next = sc->dc_mi; 1808 sc->dc_mi = m; 1809 1810 sc->dc_pmode = DC_PMODE_SYM; 1811 1812 return; 1813 } 1814 1815 static void 1816 dc_decode_leaf_mii(sc, l) 1817 struct dc_softc *sc; 1818 struct dc_eblock_mii *l; 1819 { 1820 u_int8_t *p; 1821 struct dc_mediainfo *m; 1822 1823 m = malloc(sizeof(struct dc_mediainfo), M_DEVBUF, M_NOWAIT); 1824 bzero(m, sizeof(struct dc_mediainfo)); 1825 /* We abuse IFM_AUTO to represent MII. */ 1826 m->dc_media = IFM_AUTO; 1827 m->dc_gp_len = l->dc_gpr_len; 1828 1829 p = (u_int8_t *)l; 1830 p += sizeof(struct dc_eblock_mii); 1831 m->dc_gp_ptr = p; 1832 p += 2 * l->dc_gpr_len; 1833 m->dc_reset_len = *p; 1834 p++; 1835 m->dc_reset_ptr = p; 1836 1837 m->dc_next = sc->dc_mi; 1838 sc->dc_mi = m; 1839 1840 return; 1841 } 1842 1843 static void 1844 dc_read_srom(sc, bits) 1845 struct dc_softc *sc; 1846 int bits; 1847 { 1848 int size; 1849 1850 size = 2 << bits; 1851 sc->dc_srom = malloc(size, M_DEVBUF, M_NOWAIT); 1852 dc_read_eeprom(sc, (caddr_t)sc->dc_srom, 0, (size / 2), 0); 1853 } 1854 1855 static void 1856 dc_parse_21143_srom(sc) 1857 struct dc_softc *sc; 1858 { 1859 struct dc_leaf_hdr *lhdr; 1860 struct dc_eblock_hdr *hdr; 1861 int i, loff; 1862 char *ptr; 1863 1864 loff = sc->dc_srom[27]; 1865 lhdr = (struct dc_leaf_hdr *)&(sc->dc_srom[loff]); 1866 1867 ptr = (char *)lhdr; 1868 ptr += sizeof(struct dc_leaf_hdr) - 1; 1869 for (i = 0; i < lhdr->dc_mcnt; i++) { 1870 hdr = (struct dc_eblock_hdr *)ptr; 1871 switch(hdr->dc_type) { 1872 case DC_EBLOCK_MII: 1873 dc_decode_leaf_mii(sc, (struct dc_eblock_mii *)hdr); 1874 break; 1875 case DC_EBLOCK_SIA: 1876 dc_decode_leaf_sia(sc, (struct dc_eblock_sia *)hdr); 1877 break; 1878 case DC_EBLOCK_SYM: 1879 dc_decode_leaf_sym(sc, (struct dc_eblock_sym *)hdr); 1880 break; 1881 default: 1882 /* Don't care. Yet. */ 1883 break; 1884 } 1885 ptr += (hdr->dc_len & 0x7F); 1886 ptr++; 1887 } 1888 1889 return; 1890 } 1891 1892 /* 1893 * Attach the interface. Allocate softc structures, do ifmedia 1894 * setup and ethernet/BPF attach. 1895 */ 1896 static int 1897 dc_attach(dev) 1898 device_t dev; 1899 { 1900 int tmp = 0; 1901 u_char eaddr[ETHER_ADDR_LEN]; 1902 u_int32_t command; 1903 struct dc_softc *sc; 1904 struct ifnet *ifp; 1905 u_int32_t revision; 1906 int unit, error = 0, rid, mac_offset; 1907 u_int8_t *mac; 1908 1909 sc = device_get_softc(dev); 1910 unit = device_get_unit(dev); 1911 1912 mtx_init(&sc->dc_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 1913 MTX_DEF | MTX_RECURSE); 1914 1915 /* 1916 * Handle power management nonsense. 1917 */ 1918 dc_acpi(dev); 1919 1920 /* 1921 * Map control/status registers. 1922 */ 1923 pci_enable_busmaster(dev); 1924 1925 rid = DC_RID; 1926 sc->dc_res = bus_alloc_resource(dev, DC_RES, &rid, 1927 0, ~0, 1, RF_ACTIVE); 1928 1929 if (sc->dc_res == NULL) { 1930 printf("dc%d: couldn't map ports/memory\n", unit); 1931 error = ENXIO; 1932 goto fail; 1933 } 1934 1935 sc->dc_btag = rman_get_bustag(sc->dc_res); 1936 sc->dc_bhandle = rman_get_bushandle(sc->dc_res); 1937 1938 /* Allocate interrupt */ 1939 rid = 0; 1940 sc->dc_irq = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, 0, ~0, 1, 1941 RF_SHAREABLE | RF_ACTIVE); 1942 1943 if (sc->dc_irq == NULL) { 1944 printf("dc%d: couldn't map interrupt\n", unit); 1945 error = ENXIO; 1946 goto fail; 1947 } 1948 1949 /* Need this info to decide on a chip type. */ 1950 sc->dc_info = dc_devtype(dev); 1951 revision = pci_read_config(dev, DC_PCI_CFRV, 4) & 0x000000FF; 1952 1953 /* Get the eeprom width, but PNIC and XIRCOM have diff eeprom */ 1954 if (sc->dc_info->dc_did != DC_DEVICEID_82C168 && 1955 sc->dc_info->dc_did != DC_DEVICEID_X3201) 1956 dc_eeprom_width(sc); 1957 1958 switch(sc->dc_info->dc_did) { 1959 case DC_DEVICEID_21143: 1960 sc->dc_type = DC_TYPE_21143; 1961 sc->dc_flags |= DC_TX_POLL|DC_TX_USE_TX_INTR; 1962 sc->dc_flags |= DC_REDUCED_MII_POLL; 1963 /* Save EEPROM contents so we can parse them later. */ 1964 dc_read_srom(sc, sc->dc_romwidth); 1965 break; 1966 case DC_DEVICEID_DM9009: 1967 case DC_DEVICEID_DM9100: 1968 case DC_DEVICEID_DM9102: 1969 sc->dc_type = DC_TYPE_DM9102; 1970 sc->dc_flags |= DC_TX_COALESCE|DC_TX_INTR_ALWAYS; 1971 sc->dc_flags |= DC_REDUCED_MII_POLL|DC_TX_STORENFWD; 1972 sc->dc_pmode = DC_PMODE_MII; 1973 /* Increase the latency timer value. */ 1974 command = pci_read_config(dev, DC_PCI_CFLT, 4); 1975 command &= 0xFFFF00FF; 1976 command |= 0x00008000; 1977 pci_write_config(dev, DC_PCI_CFLT, command, 4); 1978 break; 1979 case DC_DEVICEID_AL981: 1980 sc->dc_type = DC_TYPE_AL981; 1981 sc->dc_flags |= DC_TX_USE_TX_INTR; 1982 sc->dc_flags |= DC_TX_ADMTEK_WAR; 1983 sc->dc_pmode = DC_PMODE_MII; 1984 dc_read_srom(sc, sc->dc_romwidth); 1985 break; 1986 case DC_DEVICEID_AN985: 1987 case DC_DEVICEID_FE2500: 1988 case DC_DEVICEID_EN2242: 1989 case DC_DEVICEID_HAWKING_PN672TX: 1990 sc->dc_type = DC_TYPE_AN985; 1991 sc->dc_flags |= DC_64BIT_HASH; 1992 sc->dc_flags |= DC_TX_USE_TX_INTR; 1993 sc->dc_flags |= DC_TX_ADMTEK_WAR; 1994 sc->dc_pmode = DC_PMODE_MII; 1995 dc_read_srom(sc, sc->dc_romwidth); 1996 break; 1997 case DC_DEVICEID_98713: 1998 case DC_DEVICEID_98713_CP: 1999 if (revision < DC_REVISION_98713A) { 2000 sc->dc_type = DC_TYPE_98713; 2001 } 2002 if (revision >= DC_REVISION_98713A) { 2003 sc->dc_type = DC_TYPE_98713A; 2004 sc->dc_flags |= DC_21143_NWAY; 2005 } 2006 sc->dc_flags |= DC_REDUCED_MII_POLL; 2007 sc->dc_flags |= DC_TX_POLL|DC_TX_USE_TX_INTR; 2008 break; 2009 case DC_DEVICEID_987x5: 2010 case DC_DEVICEID_EN1217: 2011 /* 2012 * Macronix MX98715AEC-C/D/E parts have only a 2013 * 128-bit hash table. We need to deal with these 2014 * in the same manner as the PNIC II so that we 2015 * get the right number of bits out of the 2016 * CRC routine. 2017 */ 2018 if (revision >= DC_REVISION_98715AEC_C && 2019 revision < DC_REVISION_98725) 2020 sc->dc_flags |= DC_128BIT_HASH; 2021 sc->dc_type = DC_TYPE_987x5; 2022 sc->dc_flags |= DC_TX_POLL|DC_TX_USE_TX_INTR; 2023 sc->dc_flags |= DC_REDUCED_MII_POLL|DC_21143_NWAY; 2024 break; 2025 case DC_DEVICEID_98727: 2026 sc->dc_type = DC_TYPE_987x5; 2027 sc->dc_flags |= DC_TX_POLL|DC_TX_USE_TX_INTR; 2028 sc->dc_flags |= DC_REDUCED_MII_POLL|DC_21143_NWAY; 2029 break; 2030 case DC_DEVICEID_82C115: 2031 sc->dc_type = DC_TYPE_PNICII; 2032 sc->dc_flags |= DC_TX_POLL|DC_TX_USE_TX_INTR|DC_128BIT_HASH; 2033 sc->dc_flags |= DC_REDUCED_MII_POLL|DC_21143_NWAY; 2034 break; 2035 case DC_DEVICEID_82C168: 2036 sc->dc_type = DC_TYPE_PNIC; 2037 sc->dc_flags |= DC_TX_STORENFWD|DC_TX_INTR_ALWAYS; 2038 sc->dc_flags |= DC_PNIC_RX_BUG_WAR; 2039 sc->dc_pnic_rx_buf = malloc(DC_RXLEN * 5, M_DEVBUF, M_NOWAIT); 2040 if (revision < DC_REVISION_82C169) 2041 sc->dc_pmode = DC_PMODE_SYM; 2042 break; 2043 case DC_DEVICEID_AX88140A: 2044 sc->dc_type = DC_TYPE_ASIX; 2045 sc->dc_flags |= DC_TX_USE_TX_INTR|DC_TX_INTR_FIRSTFRAG; 2046 sc->dc_flags |= DC_REDUCED_MII_POLL; 2047 sc->dc_pmode = DC_PMODE_MII; 2048 break; 2049 case DC_DEVICEID_X3201: 2050 sc->dc_type = DC_TYPE_XIRCOM; 2051 sc->dc_flags |= DC_TX_INTR_ALWAYS | DC_TX_COALESCE | 2052 DC_TX_ALIGN; 2053 /* 2054 * We don't actually need to coalesce, but we're doing 2055 * it to obtain a double word aligned buffer. 2056 * The DC_TX_COALESCE flag is required. 2057 */ 2058 sc->dc_pmode = DC_PMODE_MII; 2059 break; 2060 case DC_DEVICEID_RS7112: 2061 sc->dc_type = DC_TYPE_CONEXANT; 2062 sc->dc_flags |= DC_TX_INTR_ALWAYS; 2063 sc->dc_flags |= DC_REDUCED_MII_POLL; 2064 sc->dc_pmode = DC_PMODE_MII; 2065 dc_read_srom(sc, sc->dc_romwidth); 2066 break; 2067 default: 2068 printf("dc%d: unknown device: %x\n", sc->dc_unit, 2069 sc->dc_info->dc_did); 2070 break; 2071 } 2072 2073 /* Save the cache line size. */ 2074 if (DC_IS_DAVICOM(sc)) 2075 sc->dc_cachesize = 0; 2076 else 2077 sc->dc_cachesize = pci_read_config(dev, 2078 DC_PCI_CFLT, 4) & 0xFF; 2079 2080 /* Reset the adapter. */ 2081 dc_reset(sc); 2082 2083 /* Take 21143 out of snooze mode */ 2084 if (DC_IS_INTEL(sc) || DC_IS_XIRCOM(sc)) { 2085 command = pci_read_config(dev, DC_PCI_CFDD, 4); 2086 command &= ~(DC_CFDD_SNOOZE_MODE|DC_CFDD_SLEEP_MODE); 2087 pci_write_config(dev, DC_PCI_CFDD, command, 4); 2088 } 2089 2090 /* 2091 * Try to learn something about the supported media. 2092 * We know that ASIX and ADMtek and Davicom devices 2093 * will *always* be using MII media, so that's a no-brainer. 2094 * The tricky ones are the Macronix/PNIC II and the 2095 * Intel 21143. 2096 */ 2097 if (DC_IS_INTEL(sc)) 2098 dc_parse_21143_srom(sc); 2099 else if (DC_IS_MACRONIX(sc) || DC_IS_PNICII(sc)) { 2100 if (sc->dc_type == DC_TYPE_98713) 2101 sc->dc_pmode = DC_PMODE_MII; 2102 else 2103 sc->dc_pmode = DC_PMODE_SYM; 2104 } else if (!sc->dc_pmode) 2105 sc->dc_pmode = DC_PMODE_MII; 2106 2107 /* 2108 * Get station address from the EEPROM. 2109 */ 2110 switch(sc->dc_type) { 2111 case DC_TYPE_98713: 2112 case DC_TYPE_98713A: 2113 case DC_TYPE_987x5: 2114 case DC_TYPE_PNICII: 2115 dc_read_eeprom(sc, (caddr_t)&mac_offset, 2116 (DC_EE_NODEADDR_OFFSET / 2), 1, 0); 2117 dc_read_eeprom(sc, (caddr_t)&eaddr, (mac_offset / 2), 3, 0); 2118 break; 2119 case DC_TYPE_PNIC: 2120 dc_read_eeprom(sc, (caddr_t)&eaddr, 0, 3, 1); 2121 break; 2122 case DC_TYPE_DM9102: 2123 case DC_TYPE_21143: 2124 case DC_TYPE_ASIX: 2125 dc_read_eeprom(sc, (caddr_t)&eaddr, DC_EE_NODEADDR, 3, 0); 2126 break; 2127 case DC_TYPE_AL981: 2128 case DC_TYPE_AN985: 2129 bcopy(&sc->dc_srom[DC_AL_EE_NODEADDR], (caddr_t)&eaddr, 2130 ETHER_ADDR_LEN); 2131 dc_read_eeprom(sc, (caddr_t)&eaddr, DC_AL_EE_NODEADDR, 3, 0); 2132 break; 2133 case DC_TYPE_CONEXANT: 2134 bcopy(sc->dc_srom + DC_CONEXANT_EE_NODEADDR, &eaddr, 6); 2135 break; 2136 case DC_TYPE_XIRCOM: 2137 /* The MAC comes from the CIS */ 2138 mac = pci_get_ether(dev); 2139 if (!mac) { 2140 device_printf(dev, "No station address in CIS!\n"); 2141 error = ENXIO; 2142 goto fail; 2143 } 2144 bcopy(mac, eaddr, ETHER_ADDR_LEN); 2145 break; 2146 default: 2147 dc_read_eeprom(sc, (caddr_t)&eaddr, DC_EE_NODEADDR, 3, 0); 2148 break; 2149 } 2150 2151 /* 2152 * A 21143 or clone chip was detected. Inform the world. 2153 */ 2154 printf("dc%d: Ethernet address: %6D\n", unit, eaddr, ":"); 2155 2156 sc->dc_unit = unit; 2157 bcopy(eaddr, (char *)&sc->arpcom.ac_enaddr, ETHER_ADDR_LEN); 2158 2159 sc->dc_ldata = contigmalloc(sizeof(struct dc_list_data), M_DEVBUF, 2160 M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0); 2161 2162 if (sc->dc_ldata == NULL) { 2163 printf("dc%d: no memory for list buffers!\n", unit); 2164 error = ENXIO; 2165 goto fail; 2166 } 2167 2168 bzero(sc->dc_ldata, sizeof(struct dc_list_data)); 2169 2170 ifp = &sc->arpcom.ac_if; 2171 ifp->if_softc = sc; 2172 ifp->if_unit = unit; 2173 ifp->if_name = "dc"; 2174 /* XXX: bleah, MTU gets overwritten in ether_ifattach() */ 2175 ifp->if_mtu = ETHERMTU; 2176 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 2177 ifp->if_ioctl = dc_ioctl; 2178 ifp->if_output = ether_output; 2179 ifp->if_start = dc_start; 2180 ifp->if_watchdog = dc_watchdog; 2181 ifp->if_init = dc_init; 2182 ifp->if_baudrate = 10000000; 2183 ifp->if_snd.ifq_maxlen = DC_TX_LIST_CNT - 1; 2184 2185 /* 2186 * Do MII setup. If this is a 21143, check for a PHY on the 2187 * MII bus after applying any necessary fixups to twiddle the 2188 * GPIO bits. If we don't end up finding a PHY, restore the 2189 * old selection (SIA only or SIA/SYM) and attach the dcphy 2190 * driver instead. 2191 */ 2192 if (DC_IS_INTEL(sc)) { 2193 dc_apply_fixup(sc, IFM_AUTO); 2194 tmp = sc->dc_pmode; 2195 sc->dc_pmode = DC_PMODE_MII; 2196 } 2197 2198 error = mii_phy_probe(dev, &sc->dc_miibus, 2199 dc_ifmedia_upd, dc_ifmedia_sts); 2200 2201 if (error && DC_IS_INTEL(sc)) { 2202 sc->dc_pmode = tmp; 2203 if (sc->dc_pmode != DC_PMODE_SIA) 2204 sc->dc_pmode = DC_PMODE_SYM; 2205 sc->dc_flags |= DC_21143_NWAY; 2206 mii_phy_probe(dev, &sc->dc_miibus, 2207 dc_ifmedia_upd, dc_ifmedia_sts); 2208 /* 2209 * For non-MII cards, we need to have the 21143 2210 * drive the LEDs. Except there are some systems 2211 * like the NEC VersaPro NoteBook PC which have no 2212 * LEDs, and twiddling these bits has adverse effects 2213 * on them. (I.e. you suddenly can't get a link.) 2214 */ 2215 if (pci_read_config(dev, DC_PCI_CSID, 4) != 0x80281033) 2216 sc->dc_flags |= DC_TULIP_LEDS; 2217 error = 0; 2218 } 2219 2220 if (error) { 2221 printf("dc%d: MII without any PHY!\n", sc->dc_unit); 2222 goto fail; 2223 } 2224 2225 if (DC_IS_XIRCOM(sc)) { 2226 /* 2227 * setup General Purpose Port mode and data so the tulip 2228 * can talk to the MII. 2229 */ 2230 CSR_WRITE_4(sc, DC_SIAGP, DC_SIAGP_WRITE_EN | DC_SIAGP_INT1_EN | 2231 DC_SIAGP_MD_GP2_OUTPUT | DC_SIAGP_MD_GP0_OUTPUT); 2232 DELAY(10); 2233 CSR_WRITE_4(sc, DC_SIAGP, DC_SIAGP_INT1_EN | 2234 DC_SIAGP_MD_GP2_OUTPUT | DC_SIAGP_MD_GP0_OUTPUT); 2235 DELAY(10); 2236 } 2237 2238 if (DC_IS_ADMTEK(sc)) { 2239 /* 2240 * Set automatic TX underrun recovery for the ADMtek chips 2241 */ 2242 DC_SETBIT(sc, DC_AL_CR, DC_AL_CR_ATUR); 2243 } 2244 2245 /* 2246 * Tell the upper layer(s) we support long frames. 2247 */ 2248 ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header); 2249 ifp->if_capabilities |= IFCAP_VLAN_MTU; 2250 2251 callout_init(&sc->dc_stat_ch, IS_MPSAFE); 2252 2253 #ifdef SRM_MEDIA 2254 sc->dc_srm_media = 0; 2255 2256 /* Remember the SRM console media setting */ 2257 if (DC_IS_INTEL(sc)) { 2258 command = pci_read_config(dev, DC_PCI_CFDD, 4); 2259 command &= ~(DC_CFDD_SNOOZE_MODE|DC_CFDD_SLEEP_MODE); 2260 switch ((command >> 8) & 0xff) { 2261 case 3: 2262 sc->dc_srm_media = IFM_10_T; 2263 break; 2264 case 4: 2265 sc->dc_srm_media = IFM_10_T | IFM_FDX; 2266 break; 2267 case 5: 2268 sc->dc_srm_media = IFM_100_TX; 2269 break; 2270 case 6: 2271 sc->dc_srm_media = IFM_100_TX | IFM_FDX; 2272 break; 2273 } 2274 if (sc->dc_srm_media) 2275 sc->dc_srm_media |= IFM_ACTIVE | IFM_ETHER; 2276 } 2277 #endif 2278 2279 /* 2280 * Call MI attach routine. 2281 */ 2282 ether_ifattach(ifp, eaddr); 2283 2284 /* Hook interrupt last to avoid having to lock softc */ 2285 error = bus_setup_intr(dev, sc->dc_irq, INTR_TYPE_NET | 2286 (IS_MPSAFE ? INTR_MPSAFE : 0), 2287 dc_intr, sc, &sc->dc_intrhand); 2288 2289 if (error) { 2290 printf("dc%d: couldn't set up irq\n", unit); 2291 ether_ifdetach(ifp); 2292 goto fail; 2293 } 2294 2295 fail: 2296 if (error) 2297 dc_detach(dev); 2298 return (error); 2299 } 2300 2301 /* 2302 * Shutdown hardware and free up resources. This can be called any 2303 * time after the mutex has been initialized. It is called in both 2304 * the error case in attach and the normal detach case so it needs 2305 * to be careful about only freeing resources that have actually been 2306 * allocated. 2307 */ 2308 static int 2309 dc_detach(dev) 2310 device_t dev; 2311 { 2312 struct dc_softc *sc; 2313 struct ifnet *ifp; 2314 struct dc_mediainfo *m; 2315 2316 sc = device_get_softc(dev); 2317 KASSERT(mtx_initialized(&sc->dc_mtx), ("dc mutex not initialized")); 2318 DC_LOCK(sc); 2319 2320 ifp = &sc->arpcom.ac_if; 2321 2322 /* These should only be active if attach succeeded */ 2323 if (device_is_attached(dev)) { 2324 dc_stop(sc); 2325 ether_ifdetach(ifp); 2326 } 2327 if (sc->dc_miibus) 2328 device_delete_child(dev, sc->dc_miibus); 2329 bus_generic_detach(dev); 2330 2331 if (sc->dc_intrhand) 2332 bus_teardown_intr(dev, sc->dc_irq, sc->dc_intrhand); 2333 if (sc->dc_irq) 2334 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->dc_irq); 2335 if (sc->dc_res) 2336 bus_release_resource(dev, DC_RES, DC_RID, sc->dc_res); 2337 2338 if (sc->dc_ldata) 2339 contigfree(sc->dc_ldata, sizeof(struct dc_list_data), M_DEVBUF); 2340 free(sc->dc_pnic_rx_buf, M_DEVBUF); 2341 2342 while(sc->dc_mi != NULL) { 2343 m = sc->dc_mi->dc_next; 2344 free(sc->dc_mi, M_DEVBUF); 2345 sc->dc_mi = m; 2346 } 2347 free(sc->dc_srom, M_DEVBUF); 2348 2349 DC_UNLOCK(sc); 2350 mtx_destroy(&sc->dc_mtx); 2351 2352 return(0); 2353 } 2354 2355 /* 2356 * Initialize the transmit descriptors. 2357 */ 2358 static int 2359 dc_list_tx_init(sc) 2360 struct dc_softc *sc; 2361 { 2362 struct dc_chain_data *cd; 2363 struct dc_list_data *ld; 2364 int i, nexti; 2365 2366 cd = &sc->dc_cdata; 2367 ld = sc->dc_ldata; 2368 for (i = 0; i < DC_TX_LIST_CNT; i++) { 2369 nexti = (i == (DC_TX_LIST_CNT - 1)) ? 0 : i+1; 2370 ld->dc_tx_list[i].dc_next = vtophys(&ld->dc_tx_list[nexti]); 2371 cd->dc_tx_chain[i] = NULL; 2372 ld->dc_tx_list[i].dc_data = 0; 2373 ld->dc_tx_list[i].dc_ctl = 0; 2374 } 2375 2376 cd->dc_tx_prod = cd->dc_tx_cons = cd->dc_tx_cnt = 0; 2377 2378 return(0); 2379 } 2380 2381 2382 /* 2383 * Initialize the RX descriptors and allocate mbufs for them. Note that 2384 * we arrange the descriptors in a closed ring, so that the last descriptor 2385 * points back to the first. 2386 */ 2387 static int 2388 dc_list_rx_init(sc) 2389 struct dc_softc *sc; 2390 { 2391 struct dc_chain_data *cd; 2392 struct dc_list_data *ld; 2393 int i, nexti; 2394 2395 cd = &sc->dc_cdata; 2396 ld = sc->dc_ldata; 2397 2398 for (i = 0; i < DC_RX_LIST_CNT; i++) { 2399 if (dc_newbuf(sc, i, NULL) == ENOBUFS) 2400 return(ENOBUFS); 2401 nexti = (i == (DC_RX_LIST_CNT - 1)) ? 0 : i+1; 2402 ld->dc_rx_list[i].dc_next = vtophys(&ld->dc_rx_list[nexti]); 2403 } 2404 2405 cd->dc_rx_prod = 0; 2406 2407 return(0); 2408 } 2409 2410 /* 2411 * Initialize an RX descriptor and attach an MBUF cluster. 2412 */ 2413 static int 2414 dc_newbuf(sc, i, m) 2415 struct dc_softc *sc; 2416 int i; 2417 struct mbuf *m; 2418 { 2419 struct mbuf *m_new = NULL; 2420 struct dc_desc *c; 2421 2422 c = &sc->dc_ldata->dc_rx_list[i]; 2423 2424 if (m == NULL) { 2425 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 2426 if (m_new == NULL) 2427 return(ENOBUFS); 2428 2429 MCLGET(m_new, M_DONTWAIT); 2430 if (!(m_new->m_flags & M_EXT)) { 2431 m_freem(m_new); 2432 return(ENOBUFS); 2433 } 2434 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 2435 } else { 2436 m_new = m; 2437 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 2438 m_new->m_data = m_new->m_ext.ext_buf; 2439 } 2440 2441 m_adj(m_new, sizeof(u_int64_t)); 2442 2443 /* 2444 * If this is a PNIC chip, zero the buffer. This is part 2445 * of the workaround for the receive bug in the 82c168 and 2446 * 82c169 chips. 2447 */ 2448 if (sc->dc_flags & DC_PNIC_RX_BUG_WAR) 2449 bzero((char *)mtod(m_new, char *), m_new->m_len); 2450 2451 sc->dc_cdata.dc_rx_chain[i] = m_new; 2452 c->dc_data = vtophys(mtod(m_new, caddr_t)); 2453 c->dc_ctl = DC_RXCTL_RLINK | DC_RXLEN; 2454 c->dc_status = DC_RXSTAT_OWN; 2455 2456 return(0); 2457 } 2458 2459 /* 2460 * Grrrrr. 2461 * The PNIC chip has a terrible bug in it that manifests itself during 2462 * periods of heavy activity. The exact mode of failure if difficult to 2463 * pinpoint: sometimes it only happens in promiscuous mode, sometimes it 2464 * will happen on slow machines. The bug is that sometimes instead of 2465 * uploading one complete frame during reception, it uploads what looks 2466 * like the entire contents of its FIFO memory. The frame we want is at 2467 * the end of the whole mess, but we never know exactly how much data has 2468 * been uploaded, so salvaging the frame is hard. 2469 * 2470 * There is only one way to do it reliably, and it's disgusting. 2471 * Here's what we know: 2472 * 2473 * - We know there will always be somewhere between one and three extra 2474 * descriptors uploaded. 2475 * 2476 * - We know the desired received frame will always be at the end of the 2477 * total data upload. 2478 * 2479 * - We know the size of the desired received frame because it will be 2480 * provided in the length field of the status word in the last descriptor. 2481 * 2482 * Here's what we do: 2483 * 2484 * - When we allocate buffers for the receive ring, we bzero() them. 2485 * This means that we know that the buffer contents should be all 2486 * zeros, except for data uploaded by the chip. 2487 * 2488 * - We also force the PNIC chip to upload frames that include the 2489 * ethernet CRC at the end. 2490 * 2491 * - We gather all of the bogus frame data into a single buffer. 2492 * 2493 * - We then position a pointer at the end of this buffer and scan 2494 * backwards until we encounter the first non-zero byte of data. 2495 * This is the end of the received frame. We know we will encounter 2496 * some data at the end of the frame because the CRC will always be 2497 * there, so even if the sender transmits a packet of all zeros, 2498 * we won't be fooled. 2499 * 2500 * - We know the size of the actual received frame, so we subtract 2501 * that value from the current pointer location. This brings us 2502 * to the start of the actual received packet. 2503 * 2504 * - We copy this into an mbuf and pass it on, along with the actual 2505 * frame length. 2506 * 2507 * The performance hit is tremendous, but it beats dropping frames all 2508 * the time. 2509 */ 2510 2511 #define DC_WHOLEFRAME (DC_RXSTAT_FIRSTFRAG|DC_RXSTAT_LASTFRAG) 2512 static void 2513 dc_pnic_rx_bug_war(sc, idx) 2514 struct dc_softc *sc; 2515 int idx; 2516 { 2517 struct dc_desc *cur_rx; 2518 struct dc_desc *c = NULL; 2519 struct mbuf *m = NULL; 2520 unsigned char *ptr; 2521 int i, total_len; 2522 u_int32_t rxstat = 0; 2523 2524 i = sc->dc_pnic_rx_bug_save; 2525 cur_rx = &sc->dc_ldata->dc_rx_list[idx]; 2526 ptr = sc->dc_pnic_rx_buf; 2527 bzero(ptr, sizeof(DC_RXLEN * 5)); 2528 2529 /* Copy all the bytes from the bogus buffers. */ 2530 while (1) { 2531 c = &sc->dc_ldata->dc_rx_list[i]; 2532 rxstat = c->dc_status; 2533 m = sc->dc_cdata.dc_rx_chain[i]; 2534 bcopy(mtod(m, char *), ptr, DC_RXLEN); 2535 ptr += DC_RXLEN; 2536 /* If this is the last buffer, break out. */ 2537 if (i == idx || rxstat & DC_RXSTAT_LASTFRAG) 2538 break; 2539 dc_newbuf(sc, i, m); 2540 DC_INC(i, DC_RX_LIST_CNT); 2541 } 2542 2543 /* Find the length of the actual receive frame. */ 2544 total_len = DC_RXBYTES(rxstat); 2545 2546 /* Scan backwards until we hit a non-zero byte. */ 2547 while(*ptr == 0x00) 2548 ptr--; 2549 2550 /* Round off. */ 2551 if ((uintptr_t)(ptr) & 0x3) 2552 ptr -= 1; 2553 2554 /* Now find the start of the frame. */ 2555 ptr -= total_len; 2556 if (ptr < sc->dc_pnic_rx_buf) 2557 ptr = sc->dc_pnic_rx_buf; 2558 2559 /* 2560 * Now copy the salvaged frame to the last mbuf and fake up 2561 * the status word to make it look like a successful 2562 * frame reception. 2563 */ 2564 dc_newbuf(sc, i, m); 2565 bcopy(ptr, mtod(m, char *), total_len); 2566 cur_rx->dc_status = rxstat | DC_RXSTAT_FIRSTFRAG; 2567 2568 return; 2569 } 2570 2571 /* 2572 * This routine searches the RX ring for dirty descriptors in the 2573 * event that the rxeof routine falls out of sync with the chip's 2574 * current descriptor pointer. This may happen sometimes as a result 2575 * of a "no RX buffer available" condition that happens when the chip 2576 * consumes all of the RX buffers before the driver has a chance to 2577 * process the RX ring. This routine may need to be called more than 2578 * once to bring the driver back in sync with the chip, however we 2579 * should still be getting RX DONE interrupts to drive the search 2580 * for new packets in the RX ring, so we should catch up eventually. 2581 */ 2582 static int 2583 dc_rx_resync(sc) 2584 struct dc_softc *sc; 2585 { 2586 int i, pos; 2587 struct dc_desc *cur_rx; 2588 2589 pos = sc->dc_cdata.dc_rx_prod; 2590 2591 for (i = 0; i < DC_RX_LIST_CNT; i++) { 2592 cur_rx = &sc->dc_ldata->dc_rx_list[pos]; 2593 if (!(cur_rx->dc_status & DC_RXSTAT_OWN)) 2594 break; 2595 DC_INC(pos, DC_RX_LIST_CNT); 2596 } 2597 2598 /* If the ring really is empty, then just return. */ 2599 if (i == DC_RX_LIST_CNT) 2600 return(0); 2601 2602 /* We've fallen behing the chip: catch it. */ 2603 sc->dc_cdata.dc_rx_prod = pos; 2604 2605 return(EAGAIN); 2606 } 2607 2608 /* 2609 * A frame has been uploaded: pass the resulting mbuf chain up to 2610 * the higher level protocols. 2611 */ 2612 static void 2613 dc_rxeof(sc) 2614 struct dc_softc *sc; 2615 { 2616 struct mbuf *m; 2617 struct ifnet *ifp; 2618 struct dc_desc *cur_rx; 2619 int i, total_len = 0; 2620 u_int32_t rxstat; 2621 2622 ifp = &sc->arpcom.ac_if; 2623 i = sc->dc_cdata.dc_rx_prod; 2624 2625 while(!(sc->dc_ldata->dc_rx_list[i].dc_status & DC_RXSTAT_OWN)) { 2626 2627 #ifdef DEVICE_POLLING 2628 if (ifp->if_flags & IFF_POLLING) { 2629 if (sc->rxcycles <= 0) 2630 break; 2631 sc->rxcycles--; 2632 } 2633 #endif /* DEVICE_POLLING */ 2634 cur_rx = &sc->dc_ldata->dc_rx_list[i]; 2635 rxstat = cur_rx->dc_status; 2636 m = sc->dc_cdata.dc_rx_chain[i]; 2637 total_len = DC_RXBYTES(rxstat); 2638 2639 if (sc->dc_flags & DC_PNIC_RX_BUG_WAR) { 2640 if ((rxstat & DC_WHOLEFRAME) != DC_WHOLEFRAME) { 2641 if (rxstat & DC_RXSTAT_FIRSTFRAG) 2642 sc->dc_pnic_rx_bug_save = i; 2643 if ((rxstat & DC_RXSTAT_LASTFRAG) == 0) { 2644 DC_INC(i, DC_RX_LIST_CNT); 2645 continue; 2646 } 2647 dc_pnic_rx_bug_war(sc, i); 2648 rxstat = cur_rx->dc_status; 2649 total_len = DC_RXBYTES(rxstat); 2650 } 2651 } 2652 2653 sc->dc_cdata.dc_rx_chain[i] = NULL; 2654 2655 /* 2656 * If an error occurs, update stats, clear the 2657 * status word and leave the mbuf cluster in place: 2658 * it should simply get re-used next time this descriptor 2659 * comes up in the ring. However, don't report long 2660 * frames as errors since they could be vlans 2661 */ 2662 if ((rxstat & DC_RXSTAT_RXERR)){ 2663 if (!(rxstat & DC_RXSTAT_GIANT) || 2664 (rxstat & (DC_RXSTAT_CRCERR | DC_RXSTAT_DRIBBLE | 2665 DC_RXSTAT_MIIERE | DC_RXSTAT_COLLSEEN | 2666 DC_RXSTAT_RUNT | DC_RXSTAT_DE))) { 2667 ifp->if_ierrors++; 2668 if (rxstat & DC_RXSTAT_COLLSEEN) 2669 ifp->if_collisions++; 2670 dc_newbuf(sc, i, m); 2671 if (rxstat & DC_RXSTAT_CRCERR) { 2672 DC_INC(i, DC_RX_LIST_CNT); 2673 continue; 2674 } else { 2675 dc_init(sc); 2676 return; 2677 } 2678 } 2679 } 2680 2681 /* No errors; receive the packet. */ 2682 total_len -= ETHER_CRC_LEN; 2683 #ifdef __i386__ 2684 /* 2685 * On the x86 we do not have alignment problems, so try to 2686 * allocate a new buffer for the receive ring, and pass up 2687 * the one where the packet is already, saving the expensive 2688 * copy done in m_devget(). 2689 * If we are on an architecture with alignment problems, or 2690 * if the allocation fails, then use m_devget and leave the 2691 * existing buffer in the receive ring. 2692 */ 2693 if (dc_quick && dc_newbuf(sc, i, NULL) == 0) { 2694 m->m_pkthdr.rcvif = ifp; 2695 m->m_pkthdr.len = m->m_len = total_len; 2696 DC_INC(i, DC_RX_LIST_CNT); 2697 } else 2698 #endif 2699 { 2700 struct mbuf *m0; 2701 2702 m0 = m_devget(mtod(m, char *), total_len, 2703 ETHER_ALIGN, ifp, NULL); 2704 dc_newbuf(sc, i, m); 2705 DC_INC(i, DC_RX_LIST_CNT); 2706 if (m0 == NULL) { 2707 ifp->if_ierrors++; 2708 continue; 2709 } 2710 m = m0; 2711 } 2712 2713 ifp->if_ipackets++; 2714 (*ifp->if_input)(ifp, m); 2715 } 2716 2717 sc->dc_cdata.dc_rx_prod = i; 2718 } 2719 2720 /* 2721 * A frame was downloaded to the chip. It's safe for us to clean up 2722 * the list buffers. 2723 */ 2724 2725 static void 2726 dc_txeof(sc) 2727 struct dc_softc *sc; 2728 { 2729 struct dc_desc *cur_tx = NULL; 2730 struct ifnet *ifp; 2731 int idx; 2732 2733 ifp = &sc->arpcom.ac_if; 2734 2735 /* 2736 * Go through our tx list and free mbufs for those 2737 * frames that have been transmitted. 2738 */ 2739 idx = sc->dc_cdata.dc_tx_cons; 2740 while(idx != sc->dc_cdata.dc_tx_prod) { 2741 u_int32_t txstat; 2742 2743 cur_tx = &sc->dc_ldata->dc_tx_list[idx]; 2744 txstat = cur_tx->dc_status; 2745 2746 if (txstat & DC_TXSTAT_OWN) 2747 break; 2748 2749 if (!(cur_tx->dc_ctl & DC_TXCTL_LASTFRAG) || 2750 cur_tx->dc_ctl & DC_TXCTL_SETUP) { 2751 if (cur_tx->dc_ctl & DC_TXCTL_SETUP) { 2752 /* 2753 * Yes, the PNIC is so brain damaged 2754 * that it will sometimes generate a TX 2755 * underrun error while DMAing the RX 2756 * filter setup frame. If we detect this, 2757 * we have to send the setup frame again, 2758 * or else the filter won't be programmed 2759 * correctly. 2760 */ 2761 if (DC_IS_PNIC(sc)) { 2762 if (txstat & DC_TXSTAT_ERRSUM) 2763 dc_setfilt(sc); 2764 } 2765 sc->dc_cdata.dc_tx_chain[idx] = NULL; 2766 } 2767 sc->dc_cdata.dc_tx_cnt--; 2768 DC_INC(idx, DC_TX_LIST_CNT); 2769 continue; 2770 } 2771 2772 if (DC_IS_XIRCOM(sc) || DC_IS_CONEXANT(sc)) { 2773 /* 2774 * XXX: Why does my Xircom taunt me so? 2775 * For some reason it likes setting the CARRLOST flag 2776 * even when the carrier is there. wtf?!? 2777 * Who knows, but Conexant chips have the 2778 * same problem. Maybe they took lessons 2779 * from Xircom. 2780 */ 2781 if (/*sc->dc_type == DC_TYPE_21143 &&*/ 2782 sc->dc_pmode == DC_PMODE_MII && 2783 ((txstat & 0xFFFF) & ~(DC_TXSTAT_ERRSUM| 2784 DC_TXSTAT_NOCARRIER))) 2785 txstat &= ~DC_TXSTAT_ERRSUM; 2786 } else { 2787 if (/*sc->dc_type == DC_TYPE_21143 &&*/ 2788 sc->dc_pmode == DC_PMODE_MII && 2789 ((txstat & 0xFFFF) & ~(DC_TXSTAT_ERRSUM| 2790 DC_TXSTAT_NOCARRIER|DC_TXSTAT_CARRLOST))) 2791 txstat &= ~DC_TXSTAT_ERRSUM; 2792 } 2793 2794 if (txstat & DC_TXSTAT_ERRSUM) { 2795 ifp->if_oerrors++; 2796 if (txstat & DC_TXSTAT_EXCESSCOLL) 2797 ifp->if_collisions++; 2798 if (txstat & DC_TXSTAT_LATECOLL) 2799 ifp->if_collisions++; 2800 if (!(txstat & DC_TXSTAT_UNDERRUN)) { 2801 dc_init(sc); 2802 return; 2803 } 2804 } 2805 2806 ifp->if_collisions += (txstat & DC_TXSTAT_COLLCNT) >> 3; 2807 2808 ifp->if_opackets++; 2809 if (sc->dc_cdata.dc_tx_chain[idx] != NULL) { 2810 m_freem(sc->dc_cdata.dc_tx_chain[idx]); 2811 sc->dc_cdata.dc_tx_chain[idx] = NULL; 2812 } 2813 2814 sc->dc_cdata.dc_tx_cnt--; 2815 DC_INC(idx, DC_TX_LIST_CNT); 2816 } 2817 2818 if (idx != sc->dc_cdata.dc_tx_cons) { 2819 /* some buffers have been freed */ 2820 sc->dc_cdata.dc_tx_cons = idx; 2821 ifp->if_flags &= ~IFF_OACTIVE; 2822 } 2823 ifp->if_timer = (sc->dc_cdata.dc_tx_cnt == 0) ? 0 : 5; 2824 2825 return; 2826 } 2827 2828 static void 2829 dc_tick(xsc) 2830 void *xsc; 2831 { 2832 struct dc_softc *sc; 2833 struct mii_data *mii; 2834 struct ifnet *ifp; 2835 u_int32_t r; 2836 2837 sc = xsc; 2838 DC_LOCK(sc); 2839 ifp = &sc->arpcom.ac_if; 2840 mii = device_get_softc(sc->dc_miibus); 2841 2842 if (sc->dc_flags & DC_REDUCED_MII_POLL) { 2843 if (sc->dc_flags & DC_21143_NWAY) { 2844 r = CSR_READ_4(sc, DC_10BTSTAT); 2845 if (IFM_SUBTYPE(mii->mii_media_active) == 2846 IFM_100_TX && (r & DC_TSTAT_LS100)) { 2847 sc->dc_link = 0; 2848 mii_mediachg(mii); 2849 } 2850 if (IFM_SUBTYPE(mii->mii_media_active) == 2851 IFM_10_T && (r & DC_TSTAT_LS10)) { 2852 sc->dc_link = 0; 2853 mii_mediachg(mii); 2854 } 2855 if (sc->dc_link == 0) 2856 mii_tick(mii); 2857 } else { 2858 r = CSR_READ_4(sc, DC_ISR); 2859 if ((r & DC_ISR_RX_STATE) == DC_RXSTATE_WAIT && 2860 sc->dc_cdata.dc_tx_cnt == 0) { 2861 mii_tick(mii); 2862 if (!(mii->mii_media_status & IFM_ACTIVE)) 2863 sc->dc_link = 0; 2864 } 2865 } 2866 } else 2867 mii_tick(mii); 2868 2869 /* 2870 * When the init routine completes, we expect to be able to send 2871 * packets right away, and in fact the network code will send a 2872 * gratuitous ARP the moment the init routine marks the interface 2873 * as running. However, even though the MAC may have been initialized, 2874 * there may be a delay of a few seconds before the PHY completes 2875 * autonegotiation and the link is brought up. Any transmissions 2876 * made during that delay will be lost. Dealing with this is tricky: 2877 * we can't just pause in the init routine while waiting for the 2878 * PHY to come ready since that would bring the whole system to 2879 * a screeching halt for several seconds. 2880 * 2881 * What we do here is prevent the TX start routine from sending 2882 * any packets until a link has been established. After the 2883 * interface has been initialized, the tick routine will poll 2884 * the state of the PHY until the IFM_ACTIVE flag is set. Until 2885 * that time, packets will stay in the send queue, and once the 2886 * link comes up, they will be flushed out to the wire. 2887 */ 2888 if (!sc->dc_link && mii->mii_media_status & IFM_ACTIVE && 2889 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) { 2890 sc->dc_link++; 2891 if (ifp->if_snd.ifq_head != NULL) 2892 dc_start(ifp); 2893 } 2894 2895 if (sc->dc_flags & DC_21143_NWAY && !sc->dc_link) 2896 callout_reset(&sc->dc_stat_ch, hz/10, dc_tick, sc); 2897 else 2898 callout_reset(&sc->dc_stat_ch, hz, dc_tick, sc); 2899 2900 DC_UNLOCK(sc); 2901 2902 return; 2903 } 2904 2905 /* 2906 * A transmit underrun has occurred. Back off the transmit threshold, 2907 * or switch to store and forward mode if we have to. 2908 */ 2909 static void 2910 dc_tx_underrun(sc) 2911 struct dc_softc *sc; 2912 { 2913 u_int32_t isr; 2914 int i; 2915 2916 if (DC_IS_DAVICOM(sc)) 2917 dc_init(sc); 2918 2919 if (DC_IS_INTEL(sc)) { 2920 /* 2921 * The real 21143 requires that the transmitter be idle 2922 * in order to change the transmit threshold or store 2923 * and forward state. 2924 */ 2925 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_TX_ON); 2926 2927 for (i = 0; i < DC_TIMEOUT; i++) { 2928 isr = CSR_READ_4(sc, DC_ISR); 2929 if (isr & DC_ISR_TX_IDLE) 2930 break; 2931 DELAY(10); 2932 } 2933 if (i == DC_TIMEOUT) { 2934 printf("dc%d: failed to force tx to idle state\n", 2935 sc->dc_unit); 2936 dc_init(sc); 2937 } 2938 } 2939 2940 printf("dc%d: TX underrun -- ", sc->dc_unit); 2941 sc->dc_txthresh += DC_TXTHRESH_INC; 2942 if (sc->dc_txthresh > DC_TXTHRESH_MAX) { 2943 printf("using store and forward mode\n"); 2944 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_STORENFWD); 2945 } else { 2946 printf("increasing TX threshold\n"); 2947 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_TX_THRESH); 2948 DC_SETBIT(sc, DC_NETCFG, sc->dc_txthresh); 2949 } 2950 2951 if (DC_IS_INTEL(sc)) 2952 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_TX_ON); 2953 2954 return; 2955 } 2956 2957 #ifdef DEVICE_POLLING 2958 static poll_handler_t dc_poll; 2959 2960 static void 2961 dc_poll(struct ifnet *ifp, enum poll_cmd cmd, int count) 2962 { 2963 struct dc_softc *sc = ifp->if_softc; 2964 2965 if (cmd == POLL_DEREGISTER) { /* final call, enable interrupts */ 2966 /* Re-enable interrupts. */ 2967 CSR_WRITE_4(sc, DC_IMR, DC_INTRS); 2968 return; 2969 } 2970 sc->rxcycles = count; 2971 dc_rxeof(sc); 2972 dc_txeof(sc); 2973 if (ifp->if_snd.ifq_head != NULL && !(ifp->if_flags & IFF_OACTIVE)) 2974 dc_start(ifp); 2975 2976 if (cmd == POLL_AND_CHECK_STATUS) { /* also check status register */ 2977 u_int32_t status; 2978 2979 status = CSR_READ_4(sc, DC_ISR); 2980 status &= (DC_ISR_RX_WATDOGTIMEO|DC_ISR_RX_NOBUF| 2981 DC_ISR_TX_NOBUF|DC_ISR_TX_IDLE|DC_ISR_TX_UNDERRUN| 2982 DC_ISR_BUS_ERR); 2983 if (!status) 2984 return; 2985 /* ack what we have */ 2986 CSR_WRITE_4(sc, DC_ISR, status); 2987 2988 if (status & (DC_ISR_RX_WATDOGTIMEO|DC_ISR_RX_NOBUF)) { 2989 u_int32_t r = CSR_READ_4(sc, DC_FRAMESDISCARDED); 2990 ifp->if_ierrors += (r & 0xffff) + ((r >> 17) & 0x7ff); 2991 2992 if (dc_rx_resync(sc)) 2993 dc_rxeof(sc); 2994 } 2995 /* restart transmit unit if necessary */ 2996 if (status & DC_ISR_TX_IDLE && sc->dc_cdata.dc_tx_cnt) 2997 CSR_WRITE_4(sc, DC_TXSTART, 0xFFFFFFFF); 2998 2999 if (status & DC_ISR_TX_UNDERRUN) 3000 dc_tx_underrun(sc); 3001 3002 if (status & DC_ISR_BUS_ERR) { 3003 printf("dc_poll: dc%d bus error\n", sc->dc_unit); 3004 dc_reset(sc); 3005 dc_init(sc); 3006 } 3007 } 3008 } 3009 #endif /* DEVICE_POLLING */ 3010 3011 static void 3012 dc_intr(arg) 3013 void *arg; 3014 { 3015 struct dc_softc *sc; 3016 struct ifnet *ifp; 3017 u_int32_t status; 3018 3019 sc = arg; 3020 3021 if (sc->suspended) { 3022 return; 3023 } 3024 3025 if ((CSR_READ_4(sc, DC_ISR) & DC_INTRS) == 0) 3026 return; 3027 3028 DC_LOCK(sc); 3029 ifp = &sc->arpcom.ac_if; 3030 #ifdef DEVICE_POLLING 3031 if (ifp->if_flags & IFF_POLLING) 3032 goto done; 3033 if (ether_poll_register(dc_poll, ifp)) { /* ok, disable interrupts */ 3034 CSR_WRITE_4(sc, DC_IMR, 0x00000000); 3035 goto done; 3036 } 3037 #endif /* DEVICE_POLLING */ 3038 3039 /* Suppress unwanted interrupts */ 3040 if (!(ifp->if_flags & IFF_UP)) { 3041 if (CSR_READ_4(sc, DC_ISR) & DC_INTRS) 3042 dc_stop(sc); 3043 DC_UNLOCK(sc); 3044 return; 3045 } 3046 3047 /* Disable interrupts. */ 3048 CSR_WRITE_4(sc, DC_IMR, 0x00000000); 3049 3050 while(((status = CSR_READ_4(sc, DC_ISR)) & DC_INTRS) 3051 && status != 0xFFFFFFFF) { 3052 3053 CSR_WRITE_4(sc, DC_ISR, status); 3054 3055 if (status & DC_ISR_RX_OK) { 3056 int curpkts; 3057 curpkts = ifp->if_ipackets; 3058 dc_rxeof(sc); 3059 if (curpkts == ifp->if_ipackets) { 3060 while(dc_rx_resync(sc)) 3061 dc_rxeof(sc); 3062 } 3063 } 3064 3065 if (status & (DC_ISR_TX_OK|DC_ISR_TX_NOBUF)) 3066 dc_txeof(sc); 3067 3068 if (status & DC_ISR_TX_IDLE) { 3069 dc_txeof(sc); 3070 if (sc->dc_cdata.dc_tx_cnt) { 3071 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_TX_ON); 3072 CSR_WRITE_4(sc, DC_TXSTART, 0xFFFFFFFF); 3073 } 3074 } 3075 3076 if (status & DC_ISR_TX_UNDERRUN) 3077 dc_tx_underrun(sc); 3078 3079 if ((status & DC_ISR_RX_WATDOGTIMEO) 3080 || (status & DC_ISR_RX_NOBUF)) { 3081 int curpkts; 3082 curpkts = ifp->if_ipackets; 3083 dc_rxeof(sc); 3084 if (curpkts == ifp->if_ipackets) { 3085 while(dc_rx_resync(sc)) 3086 dc_rxeof(sc); 3087 } 3088 } 3089 3090 if (status & DC_ISR_BUS_ERR) { 3091 dc_reset(sc); 3092 dc_init(sc); 3093 } 3094 } 3095 3096 /* Re-enable interrupts. */ 3097 CSR_WRITE_4(sc, DC_IMR, DC_INTRS); 3098 3099 if (ifp->if_snd.ifq_head != NULL) 3100 dc_start(ifp); 3101 3102 #ifdef DEVICE_POLLING 3103 done: 3104 #endif /* DEVICE_POLLING */ 3105 3106 DC_UNLOCK(sc); 3107 3108 return; 3109 } 3110 3111 /* 3112 * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data 3113 * pointers to the fragment pointers. 3114 */ 3115 static int 3116 dc_encap(sc, m_head, txidx) 3117 struct dc_softc *sc; 3118 struct mbuf *m_head; 3119 u_int32_t *txidx; 3120 { 3121 struct dc_desc *f = NULL; 3122 struct mbuf *m; 3123 int frag, cur, cnt = 0, chainlen = 0; 3124 3125 /* 3126 * If there's no way we can send any packets, return now. 3127 */ 3128 if (DC_TX_LIST_CNT - sc->dc_cdata.dc_tx_cnt < 6) 3129 return (ENOBUFS); 3130 3131 /* 3132 * Count the number of frags in this chain to see if 3133 * we need to m_defrag. Since the descriptor list is shared 3134 * by all packets, we'll m_defrag long chains so that they 3135 * do not use up the entire list, even if they would fit. 3136 */ 3137 3138 for (m = m_head; m != NULL; m = m->m_next) 3139 chainlen++; 3140 3141 if ((chainlen > DC_TX_LIST_CNT / 4) || 3142 ((DC_TX_LIST_CNT - (chainlen + sc->dc_cdata.dc_tx_cnt)) < 6)) { 3143 m = m_defrag(m_head, M_DONTWAIT); 3144 if (m == NULL) 3145 return (ENOBUFS); 3146 m_head = m; 3147 } 3148 3149 /* 3150 * Start packing the mbufs in this chain into 3151 * the fragment pointers. Stop when we run out 3152 * of fragments or hit the end of the mbuf chain. 3153 */ 3154 m = m_head; 3155 cur = frag = *txidx; 3156 3157 for (m = m_head; m != NULL; m = m->m_next) { 3158 if (m->m_len != 0) { 3159 if (sc->dc_flags & DC_TX_ADMTEK_WAR) { 3160 if (*txidx != sc->dc_cdata.dc_tx_prod && 3161 frag == (DC_TX_LIST_CNT - 1)) 3162 return(ENOBUFS); 3163 } 3164 if ((DC_TX_LIST_CNT - 3165 (sc->dc_cdata.dc_tx_cnt + cnt)) < 5) 3166 return(ENOBUFS); 3167 3168 f = &sc->dc_ldata->dc_tx_list[frag]; 3169 f->dc_ctl = DC_TXCTL_TLINK | m->m_len; 3170 if (cnt == 0) { 3171 f->dc_status = 0; 3172 f->dc_ctl |= DC_TXCTL_FIRSTFRAG; 3173 } else 3174 f->dc_status = DC_TXSTAT_OWN; 3175 f->dc_data = vtophys(mtod(m, vm_offset_t)); 3176 cur = frag; 3177 DC_INC(frag, DC_TX_LIST_CNT); 3178 cnt++; 3179 } 3180 } 3181 3182 if (m != NULL) 3183 return(ENOBUFS); 3184 3185 sc->dc_cdata.dc_tx_cnt += cnt; 3186 sc->dc_cdata.dc_tx_chain[cur] = m_head; 3187 sc->dc_ldata->dc_tx_list[cur].dc_ctl |= DC_TXCTL_LASTFRAG; 3188 if (sc->dc_flags & DC_TX_INTR_FIRSTFRAG) 3189 sc->dc_ldata->dc_tx_list[*txidx].dc_ctl |= DC_TXCTL_FINT; 3190 if (sc->dc_flags & DC_TX_INTR_ALWAYS) 3191 sc->dc_ldata->dc_tx_list[cur].dc_ctl |= DC_TXCTL_FINT; 3192 if (sc->dc_flags & DC_TX_USE_TX_INTR && sc->dc_cdata.dc_tx_cnt > 64) 3193 sc->dc_ldata->dc_tx_list[cur].dc_ctl |= DC_TXCTL_FINT; 3194 sc->dc_ldata->dc_tx_list[*txidx].dc_status = DC_TXSTAT_OWN; 3195 *txidx = frag; 3196 3197 return(0); 3198 } 3199 3200 /* 3201 * Main transmit routine. To avoid having to do mbuf copies, we put pointers 3202 * to the mbuf data regions directly in the transmit lists. We also save a 3203 * copy of the pointers since the transmit list fragment pointers are 3204 * physical addresses. 3205 */ 3206 3207 static void 3208 dc_start(ifp) 3209 struct ifnet *ifp; 3210 { 3211 struct dc_softc *sc; 3212 struct mbuf *m_head = NULL, *m; 3213 int idx; 3214 3215 sc = ifp->if_softc; 3216 3217 DC_LOCK(sc); 3218 3219 if (!sc->dc_link && ifp->if_snd.ifq_len < 10) { 3220 DC_UNLOCK(sc); 3221 return; 3222 } 3223 3224 if (ifp->if_flags & IFF_OACTIVE) { 3225 DC_UNLOCK(sc); 3226 return; 3227 } 3228 3229 idx = sc->dc_cdata.dc_tx_prod; 3230 3231 while(sc->dc_cdata.dc_tx_chain[idx] == NULL) { 3232 IF_DEQUEUE(&ifp->if_snd, m_head); 3233 if (m_head == NULL) 3234 break; 3235 3236 if (sc->dc_flags & DC_TX_COALESCE && 3237 (m_head->m_next != NULL || 3238 sc->dc_flags & DC_TX_ALIGN)) { 3239 m = m_defrag(m_head, M_DONTWAIT); 3240 if (m == NULL) { 3241 IF_PREPEND(&ifp->if_snd, m_head); 3242 ifp->if_flags |= IFF_OACTIVE; 3243 break; 3244 } else { 3245 m_head = m; 3246 } 3247 } 3248 3249 if (dc_encap(sc, m_head, &idx)) { 3250 IF_PREPEND(&ifp->if_snd, m_head); 3251 ifp->if_flags |= IFF_OACTIVE; 3252 break; 3253 } 3254 3255 /* 3256 * If there's a BPF listener, bounce a copy of this frame 3257 * to him. 3258 */ 3259 BPF_MTAP(ifp, m_head); 3260 3261 if (sc->dc_flags & DC_TX_ONE) { 3262 ifp->if_flags |= IFF_OACTIVE; 3263 break; 3264 } 3265 } 3266 3267 /* Transmit */ 3268 sc->dc_cdata.dc_tx_prod = idx; 3269 if (!(sc->dc_flags & DC_TX_POLL)) 3270 CSR_WRITE_4(sc, DC_TXSTART, 0xFFFFFFFF); 3271 3272 /* 3273 * Set a timeout in case the chip goes out to lunch. 3274 */ 3275 ifp->if_timer = 5; 3276 3277 DC_UNLOCK(sc); 3278 3279 return; 3280 } 3281 3282 static void 3283 dc_init(xsc) 3284 void *xsc; 3285 { 3286 struct dc_softc *sc = xsc; 3287 struct ifnet *ifp = &sc->arpcom.ac_if; 3288 struct mii_data *mii; 3289 3290 DC_LOCK(sc); 3291 3292 mii = device_get_softc(sc->dc_miibus); 3293 3294 /* 3295 * Cancel pending I/O and free all RX/TX buffers. 3296 */ 3297 dc_stop(sc); 3298 dc_reset(sc); 3299 3300 /* 3301 * Set cache alignment and burst length. 3302 */ 3303 if (DC_IS_ASIX(sc) || DC_IS_DAVICOM(sc)) 3304 CSR_WRITE_4(sc, DC_BUSCTL, 0); 3305 else 3306 CSR_WRITE_4(sc, DC_BUSCTL, DC_BUSCTL_MRME|DC_BUSCTL_MRLE); 3307 /* 3308 * Evenly share the bus between receive and transmit process. 3309 */ 3310 if (DC_IS_INTEL(sc)) 3311 DC_SETBIT(sc, DC_BUSCTL, DC_BUSCTL_ARBITRATION); 3312 if (DC_IS_DAVICOM(sc) || DC_IS_INTEL(sc)) { 3313 DC_SETBIT(sc, DC_BUSCTL, DC_BURSTLEN_USECA); 3314 } else { 3315 DC_SETBIT(sc, DC_BUSCTL, DC_BURSTLEN_16LONG); 3316 } 3317 if (sc->dc_flags & DC_TX_POLL) 3318 DC_SETBIT(sc, DC_BUSCTL, DC_TXPOLL_1); 3319 switch(sc->dc_cachesize) { 3320 case 32: 3321 DC_SETBIT(sc, DC_BUSCTL, DC_CACHEALIGN_32LONG); 3322 break; 3323 case 16: 3324 DC_SETBIT(sc, DC_BUSCTL, DC_CACHEALIGN_16LONG); 3325 break; 3326 case 8: 3327 DC_SETBIT(sc, DC_BUSCTL, DC_CACHEALIGN_8LONG); 3328 break; 3329 case 0: 3330 default: 3331 DC_SETBIT(sc, DC_BUSCTL, DC_CACHEALIGN_NONE); 3332 break; 3333 } 3334 3335 if (sc->dc_flags & DC_TX_STORENFWD) 3336 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_STORENFWD); 3337 else { 3338 if (sc->dc_txthresh > DC_TXTHRESH_MAX) { 3339 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_STORENFWD); 3340 } else { 3341 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_STORENFWD); 3342 DC_SETBIT(sc, DC_NETCFG, sc->dc_txthresh); 3343 } 3344 } 3345 3346 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_NO_RXCRC); 3347 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_TX_BACKOFF); 3348 3349 if (DC_IS_MACRONIX(sc) || DC_IS_PNICII(sc)) { 3350 /* 3351 * The app notes for the 98713 and 98715A say that 3352 * in order to have the chips operate properly, a magic 3353 * number must be written to CSR16. Macronix does not 3354 * document the meaning of these bits so there's no way 3355 * to know exactly what they do. The 98713 has a magic 3356 * number all its own; the rest all use a different one. 3357 */ 3358 DC_CLRBIT(sc, DC_MX_MAGICPACKET, 0xFFFF0000); 3359 if (sc->dc_type == DC_TYPE_98713) 3360 DC_SETBIT(sc, DC_MX_MAGICPACKET, DC_MX_MAGIC_98713); 3361 else 3362 DC_SETBIT(sc, DC_MX_MAGICPACKET, DC_MX_MAGIC_98715); 3363 } 3364 3365 if (DC_IS_XIRCOM(sc)) { 3366 /* 3367 * setup General Purpose Port mode and data so the tulip 3368 * can talk to the MII. 3369 */ 3370 CSR_WRITE_4(sc, DC_SIAGP, DC_SIAGP_WRITE_EN | DC_SIAGP_INT1_EN | 3371 DC_SIAGP_MD_GP2_OUTPUT | DC_SIAGP_MD_GP0_OUTPUT); 3372 DELAY(10); 3373 CSR_WRITE_4(sc, DC_SIAGP, DC_SIAGP_INT1_EN | 3374 DC_SIAGP_MD_GP2_OUTPUT | DC_SIAGP_MD_GP0_OUTPUT); 3375 DELAY(10); 3376 } 3377 3378 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_TX_THRESH); 3379 DC_SETBIT(sc, DC_NETCFG, DC_TXTHRESH_MIN); 3380 3381 /* Init circular RX list. */ 3382 if (dc_list_rx_init(sc) == ENOBUFS) { 3383 printf("dc%d: initialization failed: no " 3384 "memory for rx buffers\n", sc->dc_unit); 3385 dc_stop(sc); 3386 DC_UNLOCK(sc); 3387 return; 3388 } 3389 3390 /* 3391 * Init tx descriptors. 3392 */ 3393 dc_list_tx_init(sc); 3394 3395 /* 3396 * Load the address of the RX list. 3397 */ 3398 CSR_WRITE_4(sc, DC_RXADDR, vtophys(&sc->dc_ldata->dc_rx_list[0])); 3399 CSR_WRITE_4(sc, DC_TXADDR, vtophys(&sc->dc_ldata->dc_tx_list[0])); 3400 3401 /* 3402 * Enable interrupts. 3403 */ 3404 #ifdef DEVICE_POLLING 3405 /* 3406 * ... but only if we are not polling, and make sure they are off in 3407 * the case of polling. Some cards (e.g. fxp) turn interrupts on 3408 * after a reset. 3409 */ 3410 if (ifp->if_flags & IFF_POLLING) 3411 CSR_WRITE_4(sc, DC_IMR, 0x00000000); 3412 else 3413 #endif 3414 CSR_WRITE_4(sc, DC_IMR, DC_INTRS); 3415 CSR_WRITE_4(sc, DC_ISR, 0xFFFFFFFF); 3416 3417 /* Enable transmitter. */ 3418 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_TX_ON); 3419 3420 /* 3421 * If this is an Intel 21143 and we're not using the 3422 * MII port, program the LED control pins so we get 3423 * link and activity indications. 3424 */ 3425 if (sc->dc_flags & DC_TULIP_LEDS) { 3426 CSR_WRITE_4(sc, DC_WATCHDOG, 3427 DC_WDOG_CTLWREN|DC_WDOG_LINK|DC_WDOG_ACTIVITY); 3428 CSR_WRITE_4(sc, DC_WATCHDOG, 0); 3429 } 3430 3431 /* 3432 * Load the RX/multicast filter. We do this sort of late 3433 * because the filter programming scheme on the 21143 and 3434 * some clones requires DMAing a setup frame via the TX 3435 * engine, and we need the transmitter enabled for that. 3436 */ 3437 dc_setfilt(sc); 3438 3439 /* Enable receiver. */ 3440 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_ON); 3441 CSR_WRITE_4(sc, DC_RXSTART, 0xFFFFFFFF); 3442 3443 mii_mediachg(mii); 3444 dc_setcfg(sc, sc->dc_if_media); 3445 3446 ifp->if_flags |= IFF_RUNNING; 3447 ifp->if_flags &= ~IFF_OACTIVE; 3448 3449 /* Don't start the ticker if this is a homePNA link. */ 3450 if (IFM_SUBTYPE(mii->mii_media.ifm_media) == IFM_HPNA_1) 3451 sc->dc_link = 1; 3452 else { 3453 if (sc->dc_flags & DC_21143_NWAY) 3454 callout_reset(&sc->dc_stat_ch, hz/10, dc_tick, sc); 3455 else 3456 callout_reset(&sc->dc_stat_ch, hz, dc_tick, sc); 3457 } 3458 3459 #ifdef SRM_MEDIA 3460 if(sc->dc_srm_media) { 3461 struct ifreq ifr; 3462 3463 ifr.ifr_media = sc->dc_srm_media; 3464 ifmedia_ioctl(ifp, &ifr, &mii->mii_media, SIOCSIFMEDIA); 3465 sc->dc_srm_media = 0; 3466 } 3467 #endif 3468 DC_UNLOCK(sc); 3469 return; 3470 } 3471 3472 /* 3473 * Set media options. 3474 */ 3475 static int 3476 dc_ifmedia_upd(ifp) 3477 struct ifnet *ifp; 3478 { 3479 struct dc_softc *sc; 3480 struct mii_data *mii; 3481 struct ifmedia *ifm; 3482 3483 sc = ifp->if_softc; 3484 mii = device_get_softc(sc->dc_miibus); 3485 mii_mediachg(mii); 3486 ifm = &mii->mii_media; 3487 3488 if (DC_IS_DAVICOM(sc) && 3489 IFM_SUBTYPE(ifm->ifm_media) == IFM_HPNA_1) 3490 dc_setcfg(sc, ifm->ifm_media); 3491 else 3492 sc->dc_link = 0; 3493 3494 return(0); 3495 } 3496 3497 /* 3498 * Report current media status. 3499 */ 3500 static void 3501 dc_ifmedia_sts(ifp, ifmr) 3502 struct ifnet *ifp; 3503 struct ifmediareq *ifmr; 3504 { 3505 struct dc_softc *sc; 3506 struct mii_data *mii; 3507 struct ifmedia *ifm; 3508 3509 sc = ifp->if_softc; 3510 mii = device_get_softc(sc->dc_miibus); 3511 mii_pollstat(mii); 3512 ifm = &mii->mii_media; 3513 if (DC_IS_DAVICOM(sc)) { 3514 if (IFM_SUBTYPE(ifm->ifm_media) == IFM_HPNA_1) { 3515 ifmr->ifm_active = ifm->ifm_media; 3516 ifmr->ifm_status = 0; 3517 return; 3518 } 3519 } 3520 ifmr->ifm_active = mii->mii_media_active; 3521 ifmr->ifm_status = mii->mii_media_status; 3522 3523 return; 3524 } 3525 3526 static int 3527 dc_ioctl(ifp, command, data) 3528 struct ifnet *ifp; 3529 u_long command; 3530 caddr_t data; 3531 { 3532 struct dc_softc *sc = ifp->if_softc; 3533 struct ifreq *ifr = (struct ifreq *) data; 3534 struct mii_data *mii; 3535 int error = 0; 3536 3537 DC_LOCK(sc); 3538 3539 switch(command) { 3540 case SIOCSIFFLAGS: 3541 if (ifp->if_flags & IFF_UP) { 3542 int need_setfilt = (ifp->if_flags ^ sc->dc_if_flags) & 3543 (IFF_PROMISC | IFF_ALLMULTI); 3544 3545 if (ifp->if_flags & IFF_RUNNING) { 3546 if (need_setfilt) 3547 dc_setfilt(sc); 3548 } else { 3549 sc->dc_txthresh = 0; 3550 dc_init(sc); 3551 } 3552 } else { 3553 if (ifp->if_flags & IFF_RUNNING) 3554 dc_stop(sc); 3555 } 3556 sc->dc_if_flags = ifp->if_flags; 3557 error = 0; 3558 break; 3559 case SIOCADDMULTI: 3560 case SIOCDELMULTI: 3561 dc_setfilt(sc); 3562 error = 0; 3563 break; 3564 case SIOCGIFMEDIA: 3565 case SIOCSIFMEDIA: 3566 mii = device_get_softc(sc->dc_miibus); 3567 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 3568 #ifdef SRM_MEDIA 3569 if (sc->dc_srm_media) 3570 sc->dc_srm_media = 0; 3571 #endif 3572 break; 3573 default: 3574 error = ether_ioctl(ifp, command, data); 3575 break; 3576 } 3577 3578 DC_UNLOCK(sc); 3579 3580 return(error); 3581 } 3582 3583 static void 3584 dc_watchdog(ifp) 3585 struct ifnet *ifp; 3586 { 3587 struct dc_softc *sc; 3588 3589 sc = ifp->if_softc; 3590 3591 DC_LOCK(sc); 3592 3593 ifp->if_oerrors++; 3594 printf("dc%d: watchdog timeout\n", sc->dc_unit); 3595 3596 dc_stop(sc); 3597 dc_reset(sc); 3598 dc_init(sc); 3599 3600 if (ifp->if_snd.ifq_head != NULL) 3601 dc_start(ifp); 3602 3603 DC_UNLOCK(sc); 3604 3605 return; 3606 } 3607 3608 /* 3609 * Stop the adapter and free any mbufs allocated to the 3610 * RX and TX lists. 3611 */ 3612 static void 3613 dc_stop(sc) 3614 struct dc_softc *sc; 3615 { 3616 register int i; 3617 struct ifnet *ifp; 3618 3619 DC_LOCK(sc); 3620 3621 ifp = &sc->arpcom.ac_if; 3622 ifp->if_timer = 0; 3623 3624 callout_stop(&sc->dc_stat_ch); 3625 3626 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 3627 #ifdef DEVICE_POLLING 3628 ether_poll_deregister(ifp); 3629 #endif 3630 3631 DC_CLRBIT(sc, DC_NETCFG, (DC_NETCFG_RX_ON|DC_NETCFG_TX_ON)); 3632 CSR_WRITE_4(sc, DC_IMR, 0x00000000); 3633 CSR_WRITE_4(sc, DC_TXADDR, 0x00000000); 3634 CSR_WRITE_4(sc, DC_RXADDR, 0x00000000); 3635 sc->dc_link = 0; 3636 3637 /* 3638 * Free data in the RX lists. 3639 */ 3640 for (i = 0; i < DC_RX_LIST_CNT; i++) { 3641 if (sc->dc_cdata.dc_rx_chain[i] != NULL) { 3642 m_freem(sc->dc_cdata.dc_rx_chain[i]); 3643 sc->dc_cdata.dc_rx_chain[i] = NULL; 3644 } 3645 } 3646 bzero((char *)&sc->dc_ldata->dc_rx_list, 3647 sizeof(sc->dc_ldata->dc_rx_list)); 3648 3649 /* 3650 * Free the TX list buffers. 3651 */ 3652 for (i = 0; i < DC_TX_LIST_CNT; i++) { 3653 if (sc->dc_cdata.dc_tx_chain[i] != NULL) { 3654 if (sc->dc_ldata->dc_tx_list[i].dc_ctl & 3655 DC_TXCTL_SETUP) { 3656 sc->dc_cdata.dc_tx_chain[i] = NULL; 3657 continue; 3658 } 3659 m_freem(sc->dc_cdata.dc_tx_chain[i]); 3660 sc->dc_cdata.dc_tx_chain[i] = NULL; 3661 } 3662 } 3663 3664 bzero((char *)&sc->dc_ldata->dc_tx_list, 3665 sizeof(sc->dc_ldata->dc_tx_list)); 3666 3667 DC_UNLOCK(sc); 3668 3669 return; 3670 } 3671 3672 /* 3673 * Device suspend routine. Stop the interface and save some PCI 3674 * settings in case the BIOS doesn't restore them properly on 3675 * resume. 3676 */ 3677 static int 3678 dc_suspend(dev) 3679 device_t dev; 3680 { 3681 register int i; 3682 int s; 3683 struct dc_softc *sc; 3684 3685 s = splimp(); 3686 3687 sc = device_get_softc(dev); 3688 3689 dc_stop(sc); 3690 3691 for (i = 0; i < 5; i++) 3692 sc->saved_maps[i] = pci_read_config(dev, PCIR_MAPS + i * 4, 4); 3693 sc->saved_biosaddr = pci_read_config(dev, PCIR_BIOS, 4); 3694 sc->saved_intline = pci_read_config(dev, PCIR_INTLINE, 1); 3695 sc->saved_cachelnsz = pci_read_config(dev, PCIR_CACHELNSZ, 1); 3696 sc->saved_lattimer = pci_read_config(dev, PCIR_LATTIMER, 1); 3697 3698 sc->suspended = 1; 3699 3700 splx(s); 3701 return (0); 3702 } 3703 3704 /* 3705 * Device resume routine. Restore some PCI settings in case the BIOS 3706 * doesn't, re-enable busmastering, and restart the interface if 3707 * appropriate. 3708 */ 3709 static int 3710 dc_resume(dev) 3711 device_t dev; 3712 { 3713 register int i; 3714 int s; 3715 struct dc_softc *sc; 3716 struct ifnet *ifp; 3717 3718 s = splimp(); 3719 3720 sc = device_get_softc(dev); 3721 ifp = &sc->arpcom.ac_if; 3722 3723 dc_acpi(dev); 3724 3725 /* better way to do this? */ 3726 for (i = 0; i < 5; i++) 3727 pci_write_config(dev, PCIR_MAPS + i * 4, sc->saved_maps[i], 4); 3728 pci_write_config(dev, PCIR_BIOS, sc->saved_biosaddr, 4); 3729 pci_write_config(dev, PCIR_INTLINE, sc->saved_intline, 1); 3730 pci_write_config(dev, PCIR_CACHELNSZ, sc->saved_cachelnsz, 1); 3731 pci_write_config(dev, PCIR_LATTIMER, sc->saved_lattimer, 1); 3732 3733 /* reenable busmastering */ 3734 pci_enable_busmaster(dev); 3735 pci_enable_io(dev, DC_RES); 3736 3737 /* reinitialize interface if necessary */ 3738 if (ifp->if_flags & IFF_UP) 3739 dc_init(sc); 3740 3741 sc->suspended = 0; 3742 3743 splx(s); 3744 return (0); 3745 } 3746 3747 /* 3748 * Stop all chip I/O so that the kernel's probe routines don't 3749 * get confused by errant DMAs when rebooting. 3750 */ 3751 static void 3752 dc_shutdown(dev) 3753 device_t dev; 3754 { 3755 struct dc_softc *sc; 3756 3757 sc = device_get_softc(dev); 3758 3759 dc_stop(sc); 3760 3761 return; 3762 } 3763