1 /* 2 * Copyright (c) 1997, 1998, 1999 3 * Bill Paul <wpaul@ee.columbia.edu>. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 3. All advertising materials mentioning features or use of this software 14 * must display the following acknowledgement: 15 * This product includes software developed by Bill Paul. 16 * 4. Neither the name of the author nor the names of any co-contributors 17 * may be used to endorse or promote products derived from this software 18 * without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30 * THE POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33 /* 34 * DEC "tulip" clone ethernet driver. Supports the DEC/Intel 21143 35 * series chips and several workalikes including the following: 36 * 37 * Macronix 98713/98715/98725/98727/98732 PMAC (www.macronix.com) 38 * Macronix/Lite-On 82c115 PNIC II (www.macronix.com) 39 * Lite-On 82c168/82c169 PNIC (www.litecom.com) 40 * ASIX Electronics AX88140A (www.asix.com.tw) 41 * ASIX Electronics AX88141 (www.asix.com.tw) 42 * ADMtek AL981 (www.admtek.com.tw) 43 * ADMtek AN985 (www.admtek.com.tw) 44 * Netgear FA511 (www.netgear.com) Appears to be rebadged ADMTek AN985 45 * Davicom DM9100, DM9102, DM9102A (www.davicom8.com) 46 * Accton EN1217 (www.accton.com) 47 * Xircom X3201 (www.xircom.com) 48 * Abocom FE2500 49 * Conexant LANfinity (www.conexant.com) 50 * 3Com OfficeConnect 10/100B 3CSOHO100B (www.3com.com) 51 * 52 * Datasheets for the 21143 are available at developer.intel.com. 53 * Datasheets for the clone parts can be found at their respective sites. 54 * (Except for the PNIC; see www.freebsd.org/~wpaul/PNIC/pnic.ps.gz.) 55 * The PNIC II is essentially a Macronix 98715A chip; the only difference 56 * worth noting is that its multicast hash table is only 128 bits wide 57 * instead of 512. 58 * 59 * Written by Bill Paul <wpaul@ee.columbia.edu> 60 * Electrical Engineering Department 61 * Columbia University, New York City 62 */ 63 64 /* 65 * The Intel 21143 is the successor to the DEC 21140. It is basically 66 * the same as the 21140 but with a few new features. The 21143 supports 67 * three kinds of media attachments: 68 * 69 * o MII port, for 10Mbps and 100Mbps support and NWAY 70 * autonegotiation provided by an external PHY. 71 * o SYM port, for symbol mode 100Mbps support. 72 * o 10baseT port. 73 * o AUI/BNC port. 74 * 75 * The 100Mbps SYM port and 10baseT port can be used together in 76 * combination with the internal NWAY support to create a 10/100 77 * autosensing configuration. 78 * 79 * Note that not all tulip workalikes are handled in this driver: we only 80 * deal with those which are relatively well behaved. The Winbond is 81 * handled separately due to its different register offsets and the 82 * special handling needed for its various bugs. The PNIC is handled 83 * here, but I'm not thrilled about it. 84 * 85 * All of the workalike chips use some form of MII transceiver support 86 * with the exception of the Macronix chips, which also have a SYM port. 87 * The ASIX AX88140A is also documented to have a SYM port, but all 88 * the cards I've seen use an MII transceiver, probably because the 89 * AX88140A doesn't support internal NWAY. 90 */ 91 92 #include <sys/cdefs.h> 93 __FBSDID("$FreeBSD$"); 94 95 #include <sys/param.h> 96 #include <sys/endian.h> 97 #include <sys/systm.h> 98 #include <sys/sockio.h> 99 #include <sys/mbuf.h> 100 #include <sys/malloc.h> 101 #include <sys/kernel.h> 102 #include <sys/socket.h> 103 #include <sys/sysctl.h> 104 105 #include <net/if.h> 106 #include <net/if_arp.h> 107 #include <net/ethernet.h> 108 #include <net/if_dl.h> 109 #include <net/if_media.h> 110 #include <net/if_types.h> 111 #include <net/if_vlan_var.h> 112 113 #include <net/bpf.h> 114 115 #include <machine/bus_pio.h> 116 #include <machine/bus_memio.h> 117 #include <machine/bus.h> 118 #include <machine/resource.h> 119 #include <sys/bus.h> 120 #include <sys/rman.h> 121 122 #include <dev/mii/mii.h> 123 #include <dev/mii/miivar.h> 124 125 #include <dev/pci/pcireg.h> 126 #include <dev/pci/pcivar.h> 127 128 #define DC_USEIOSPACE 129 #ifdef __alpha__ 130 #define SRM_MEDIA 131 #endif 132 133 #include <pci/if_dcreg.h> 134 135 MODULE_DEPEND(dc, pci, 1, 1, 1); 136 MODULE_DEPEND(dc, ether, 1, 1, 1); 137 MODULE_DEPEND(dc, miibus, 1, 1, 1); 138 139 /* "controller miibus0" required. See GENERIC if you get errors here. */ 140 #include "miibus_if.h" 141 142 /* 143 * Various supported device vendors/types and their names. 144 */ 145 static struct dc_type dc_devs[] = { 146 { DC_VENDORID_DEC, DC_DEVICEID_21143, 147 "Intel 21143 10/100BaseTX" }, 148 { DC_VENDORID_DAVICOM, DC_DEVICEID_DM9009, 149 "Davicom DM9009 10/100BaseTX" }, 150 { DC_VENDORID_DAVICOM, DC_DEVICEID_DM9100, 151 "Davicom DM9100 10/100BaseTX" }, 152 { DC_VENDORID_DAVICOM, DC_DEVICEID_DM9102, 153 "Davicom DM9102 10/100BaseTX" }, 154 { DC_VENDORID_DAVICOM, DC_DEVICEID_DM9102, 155 "Davicom DM9102A 10/100BaseTX" }, 156 { DC_VENDORID_ADMTEK, DC_DEVICEID_AL981, 157 "ADMtek AL981 10/100BaseTX" }, 158 { DC_VENDORID_ADMTEK, DC_DEVICEID_AN985, 159 "ADMtek AN985 10/100BaseTX" }, 160 { DC_VENDORID_ADMTEK, DC_DEVICEID_ADM9511, 161 "ADMtek ADM9511 10/100BaseTX" }, 162 { DC_VENDORID_ADMTEK, DC_DEVICEID_ADM9513, 163 "ADMtek ADM9513 10/100BaseTX" }, 164 { DC_VENDORID_ADMTEK, DC_DEVICEID_FA511, 165 "Netgear FA511 10/100BaseTX" }, 166 { DC_VENDORID_ASIX, DC_DEVICEID_AX88140A, 167 "ASIX AX88140A 10/100BaseTX" }, 168 { DC_VENDORID_ASIX, DC_DEVICEID_AX88140A, 169 "ASIX AX88141 10/100BaseTX" }, 170 { DC_VENDORID_MX, DC_DEVICEID_98713, 171 "Macronix 98713 10/100BaseTX" }, 172 { DC_VENDORID_MX, DC_DEVICEID_98713, 173 "Macronix 98713A 10/100BaseTX" }, 174 { DC_VENDORID_CP, DC_DEVICEID_98713_CP, 175 "Compex RL100-TX 10/100BaseTX" }, 176 { DC_VENDORID_CP, DC_DEVICEID_98713_CP, 177 "Compex RL100-TX 10/100BaseTX" }, 178 { DC_VENDORID_MX, DC_DEVICEID_987x5, 179 "Macronix 98715/98715A 10/100BaseTX" }, 180 { DC_VENDORID_MX, DC_DEVICEID_987x5, 181 "Macronix 98715AEC-C 10/100BaseTX" }, 182 { DC_VENDORID_MX, DC_DEVICEID_987x5, 183 "Macronix 98725 10/100BaseTX" }, 184 { DC_VENDORID_MX, DC_DEVICEID_98727, 185 "Macronix 98727/98732 10/100BaseTX" }, 186 { DC_VENDORID_LO, DC_DEVICEID_82C115, 187 "LC82C115 PNIC II 10/100BaseTX" }, 188 { DC_VENDORID_LO, DC_DEVICEID_82C168, 189 "82c168 PNIC 10/100BaseTX" }, 190 { DC_VENDORID_LO, DC_DEVICEID_82C168, 191 "82c169 PNIC 10/100BaseTX" }, 192 { DC_VENDORID_ACCTON, DC_DEVICEID_EN1217, 193 "Accton EN1217 10/100BaseTX" }, 194 { DC_VENDORID_ACCTON, DC_DEVICEID_EN2242, 195 "Accton EN2242 MiniPCI 10/100BaseTX" }, 196 { DC_VENDORID_XIRCOM, DC_DEVICEID_X3201, 197 "Xircom X3201 10/100BaseTX" }, 198 { DC_VENDORID_ABOCOM, DC_DEVICEID_FE2500, 199 "Abocom FE2500 10/100BaseTX" }, 200 { DC_VENDORID_CONEXANT, DC_DEVICEID_RS7112, 201 "Conexant LANfinity MiniPCI 10/100BaseTX" }, 202 { DC_VENDORID_HAWKING, DC_DEVICEID_HAWKING_PN672TX, 203 "Hawking CB102 CardBus 10/100" }, 204 { DC_VENDORID_PLANEX, DC_DEVICEID_FNW3602T, 205 "PlaneX FNW-3602-T CardBus 10/100" }, 206 { DC_VENDORID_3COM, DC_DEVICEID_3CSOHOB, 207 "3Com OfficeConnect 10/100B" }, 208 { DC_VENDORID_MICROSOFT, DC_DEVICEID_MSMN120, 209 "Microsoft MN-120 CardBus 10/100" }, 210 { DC_VENDORID_MICROSOFT, DC_DEVICEID_MSMN130, 211 "Microsoft MN-130 10/100" }, 212 { DC_VENDORID_MICROSOFT, DC_DEVICEID_MSMN130_FAKE, 213 "Microsoft MN-130 10/100" }, 214 { 0, 0, NULL } 215 }; 216 217 static int dc_probe (device_t); 218 static int dc_attach (device_t); 219 static int dc_detach (device_t); 220 static int dc_suspend (device_t); 221 static int dc_resume (device_t); 222 #ifndef BURN_BRIDGES 223 static void dc_acpi (device_t); 224 #endif 225 static struct dc_type *dc_devtype (device_t); 226 static int dc_newbuf (struct dc_softc *, int, int); 227 static int dc_encap (struct dc_softc *, struct mbuf **); 228 static void dc_pnic_rx_bug_war (struct dc_softc *, int); 229 static int dc_rx_resync (struct dc_softc *); 230 static void dc_rxeof (struct dc_softc *); 231 static void dc_txeof (struct dc_softc *); 232 static void dc_tick (void *); 233 static void dc_tx_underrun (struct dc_softc *); 234 static void dc_intr (void *); 235 static void dc_start (struct ifnet *); 236 static int dc_ioctl (struct ifnet *, u_long, caddr_t); 237 static void dc_init (void *); 238 static void dc_stop (struct dc_softc *); 239 static void dc_watchdog (struct ifnet *); 240 static void dc_shutdown (device_t); 241 static int dc_ifmedia_upd (struct ifnet *); 242 static void dc_ifmedia_sts (struct ifnet *, struct ifmediareq *); 243 244 static void dc_delay (struct dc_softc *); 245 static void dc_eeprom_idle (struct dc_softc *); 246 static void dc_eeprom_putbyte (struct dc_softc *, int); 247 static void dc_eeprom_getword (struct dc_softc *, int, u_int16_t *); 248 static void dc_eeprom_getword_pnic 249 (struct dc_softc *, int, u_int16_t *); 250 static void dc_eeprom_getword_xircom 251 (struct dc_softc *, int, u_int16_t *); 252 static void dc_eeprom_width (struct dc_softc *); 253 static void dc_read_eeprom (struct dc_softc *, caddr_t, int, int, int); 254 255 static void dc_mii_writebit (struct dc_softc *, int); 256 static int dc_mii_readbit (struct dc_softc *); 257 static void dc_mii_sync (struct dc_softc *); 258 static void dc_mii_send (struct dc_softc *, u_int32_t, int); 259 static int dc_mii_readreg (struct dc_softc *, struct dc_mii_frame *); 260 static int dc_mii_writereg (struct dc_softc *, struct dc_mii_frame *); 261 static int dc_miibus_readreg (device_t, int, int); 262 static int dc_miibus_writereg (device_t, int, int, int); 263 static void dc_miibus_statchg (device_t); 264 static void dc_miibus_mediainit (device_t); 265 266 static void dc_setcfg (struct dc_softc *, int); 267 static u_int32_t dc_crc_le (struct dc_softc *, const uint8_t *); 268 static u_int32_t dc_crc_be (const uint8_t *); 269 static void dc_setfilt_21143 (struct dc_softc *); 270 static void dc_setfilt_asix (struct dc_softc *); 271 static void dc_setfilt_admtek (struct dc_softc *); 272 static void dc_setfilt_xircom (struct dc_softc *); 273 274 static void dc_setfilt (struct dc_softc *); 275 276 static void dc_reset (struct dc_softc *); 277 static int dc_list_rx_init (struct dc_softc *); 278 static int dc_list_tx_init (struct dc_softc *); 279 280 static void dc_read_srom (struct dc_softc *, int); 281 static void dc_parse_21143_srom (struct dc_softc *); 282 static void dc_decode_leaf_sia (struct dc_softc *, struct dc_eblock_sia *); 283 static void dc_decode_leaf_mii (struct dc_softc *, struct dc_eblock_mii *); 284 static void dc_decode_leaf_sym (struct dc_softc *, struct dc_eblock_sym *); 285 static void dc_apply_fixup (struct dc_softc *, int); 286 287 static void dc_dma_map_txbuf (void *, bus_dma_segment_t *, int, bus_size_t, 288 int); 289 static void dc_dma_map_rxbuf (void *, bus_dma_segment_t *, int, bus_size_t, 290 int); 291 292 #ifdef DC_USEIOSPACE 293 #define DC_RES SYS_RES_IOPORT 294 #define DC_RID DC_PCI_CFBIO 295 #else 296 #define DC_RES SYS_RES_MEMORY 297 #define DC_RID DC_PCI_CFBMA 298 #endif 299 300 static device_method_t dc_methods[] = { 301 /* Device interface */ 302 DEVMETHOD(device_probe, dc_probe), 303 DEVMETHOD(device_attach, dc_attach), 304 DEVMETHOD(device_detach, dc_detach), 305 DEVMETHOD(device_suspend, dc_suspend), 306 DEVMETHOD(device_resume, dc_resume), 307 DEVMETHOD(device_shutdown, dc_shutdown), 308 309 /* bus interface */ 310 DEVMETHOD(bus_print_child, bus_generic_print_child), 311 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 312 313 /* MII interface */ 314 DEVMETHOD(miibus_readreg, dc_miibus_readreg), 315 DEVMETHOD(miibus_writereg, dc_miibus_writereg), 316 DEVMETHOD(miibus_statchg, dc_miibus_statchg), 317 DEVMETHOD(miibus_mediainit, dc_miibus_mediainit), 318 319 { 0, 0 } 320 }; 321 322 static driver_t dc_driver = { 323 "dc", 324 dc_methods, 325 sizeof(struct dc_softc) 326 }; 327 328 static devclass_t dc_devclass; 329 #ifdef __i386__ 330 static int dc_quick = 1; 331 SYSCTL_INT(_hw, OID_AUTO, dc_quick, CTLFLAG_RW, &dc_quick, 0, 332 "do not m_devget() in dc driver"); 333 #endif 334 335 DRIVER_MODULE(dc, pci, dc_driver, dc_devclass, 0, 0); 336 DRIVER_MODULE(miibus, dc, miibus_driver, miibus_devclass, 0, 0); 337 338 #define DC_SETBIT(sc, reg, x) \ 339 CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) | (x)) 340 341 #define DC_CLRBIT(sc, reg, x) \ 342 CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) & ~(x)) 343 344 #define SIO_SET(x) DC_SETBIT(sc, DC_SIO, (x)) 345 #define SIO_CLR(x) DC_CLRBIT(sc, DC_SIO, (x)) 346 347 #define IS_MPSAFE 0 348 349 static void 350 dc_delay(struct dc_softc *sc) 351 { 352 int idx; 353 354 for (idx = (300 / 33) + 1; idx > 0; idx--) 355 CSR_READ_4(sc, DC_BUSCTL); 356 } 357 358 static void 359 dc_eeprom_width(struct dc_softc *sc) 360 { 361 int i; 362 363 /* Force EEPROM to idle state. */ 364 dc_eeprom_idle(sc); 365 366 /* Enter EEPROM access mode. */ 367 CSR_WRITE_4(sc, DC_SIO, DC_SIO_EESEL); 368 dc_delay(sc); 369 DC_SETBIT(sc, DC_SIO, DC_SIO_ROMCTL_READ); 370 dc_delay(sc); 371 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); 372 dc_delay(sc); 373 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CS); 374 dc_delay(sc); 375 376 for (i = 3; i--;) { 377 if (6 & (1 << i)) 378 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_DATAIN); 379 else 380 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_DATAIN); 381 dc_delay(sc); 382 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CLK); 383 dc_delay(sc); 384 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); 385 dc_delay(sc); 386 } 387 388 for (i = 1; i <= 12; i++) { 389 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CLK); 390 dc_delay(sc); 391 if (!(CSR_READ_4(sc, DC_SIO) & DC_SIO_EE_DATAOUT)) { 392 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); 393 dc_delay(sc); 394 break; 395 } 396 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); 397 dc_delay(sc); 398 } 399 400 /* Turn off EEPROM access mode. */ 401 dc_eeprom_idle(sc); 402 403 if (i < 4 || i > 12) 404 sc->dc_romwidth = 6; 405 else 406 sc->dc_romwidth = i; 407 408 /* Enter EEPROM access mode. */ 409 CSR_WRITE_4(sc, DC_SIO, DC_SIO_EESEL); 410 dc_delay(sc); 411 DC_SETBIT(sc, DC_SIO, DC_SIO_ROMCTL_READ); 412 dc_delay(sc); 413 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); 414 dc_delay(sc); 415 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CS); 416 dc_delay(sc); 417 418 /* Turn off EEPROM access mode. */ 419 dc_eeprom_idle(sc); 420 } 421 422 static void 423 dc_eeprom_idle(struct dc_softc *sc) 424 { 425 int i; 426 427 CSR_WRITE_4(sc, DC_SIO, DC_SIO_EESEL); 428 dc_delay(sc); 429 DC_SETBIT(sc, DC_SIO, DC_SIO_ROMCTL_READ); 430 dc_delay(sc); 431 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); 432 dc_delay(sc); 433 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CS); 434 dc_delay(sc); 435 436 for (i = 0; i < 25; i++) { 437 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); 438 dc_delay(sc); 439 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CLK); 440 dc_delay(sc); 441 } 442 443 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); 444 dc_delay(sc); 445 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CS); 446 dc_delay(sc); 447 CSR_WRITE_4(sc, DC_SIO, 0x00000000); 448 } 449 450 /* 451 * Send a read command and address to the EEPROM, check for ACK. 452 */ 453 static void 454 dc_eeprom_putbyte(struct dc_softc *sc, int addr) 455 { 456 int d, i; 457 458 d = DC_EECMD_READ >> 6; 459 for (i = 3; i--; ) { 460 if (d & (1 << i)) 461 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_DATAIN); 462 else 463 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_DATAIN); 464 dc_delay(sc); 465 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CLK); 466 dc_delay(sc); 467 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); 468 dc_delay(sc); 469 } 470 471 /* 472 * Feed in each bit and strobe the clock. 473 */ 474 for (i = sc->dc_romwidth; i--;) { 475 if (addr & (1 << i)) { 476 SIO_SET(DC_SIO_EE_DATAIN); 477 } else { 478 SIO_CLR(DC_SIO_EE_DATAIN); 479 } 480 dc_delay(sc); 481 SIO_SET(DC_SIO_EE_CLK); 482 dc_delay(sc); 483 SIO_CLR(DC_SIO_EE_CLK); 484 dc_delay(sc); 485 } 486 } 487 488 /* 489 * Read a word of data stored in the EEPROM at address 'addr.' 490 * The PNIC 82c168/82c169 has its own non-standard way to read 491 * the EEPROM. 492 */ 493 static void 494 dc_eeprom_getword_pnic(struct dc_softc *sc, int addr, u_int16_t *dest) 495 { 496 int i; 497 u_int32_t r; 498 499 CSR_WRITE_4(sc, DC_PN_SIOCTL, DC_PN_EEOPCODE_READ | addr); 500 501 for (i = 0; i < DC_TIMEOUT; i++) { 502 DELAY(1); 503 r = CSR_READ_4(sc, DC_SIO); 504 if (!(r & DC_PN_SIOCTL_BUSY)) { 505 *dest = (u_int16_t)(r & 0xFFFF); 506 return; 507 } 508 } 509 } 510 511 /* 512 * Read a word of data stored in the EEPROM at address 'addr.' 513 * The Xircom X3201 has its own non-standard way to read 514 * the EEPROM, too. 515 */ 516 static void 517 dc_eeprom_getword_xircom(struct dc_softc *sc, int addr, u_int16_t *dest) 518 { 519 520 SIO_SET(DC_SIO_ROMSEL | DC_SIO_ROMCTL_READ); 521 522 addr *= 2; 523 CSR_WRITE_4(sc, DC_ROM, addr | 0x160); 524 *dest = (u_int16_t)CSR_READ_4(sc, DC_SIO) & 0xff; 525 addr += 1; 526 CSR_WRITE_4(sc, DC_ROM, addr | 0x160); 527 *dest |= ((u_int16_t)CSR_READ_4(sc, DC_SIO) & 0xff) << 8; 528 529 SIO_CLR(DC_SIO_ROMSEL | DC_SIO_ROMCTL_READ); 530 } 531 532 /* 533 * Read a word of data stored in the EEPROM at address 'addr.' 534 */ 535 static void 536 dc_eeprom_getword(struct dc_softc *sc, int addr, u_int16_t *dest) 537 { 538 int i; 539 u_int16_t word = 0; 540 541 /* Force EEPROM to idle state. */ 542 dc_eeprom_idle(sc); 543 544 /* Enter EEPROM access mode. */ 545 CSR_WRITE_4(sc, DC_SIO, DC_SIO_EESEL); 546 dc_delay(sc); 547 DC_SETBIT(sc, DC_SIO, DC_SIO_ROMCTL_READ); 548 dc_delay(sc); 549 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); 550 dc_delay(sc); 551 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CS); 552 dc_delay(sc); 553 554 /* 555 * Send address of word we want to read. 556 */ 557 dc_eeprom_putbyte(sc, addr); 558 559 /* 560 * Start reading bits from EEPROM. 561 */ 562 for (i = 0x8000; i; i >>= 1) { 563 SIO_SET(DC_SIO_EE_CLK); 564 dc_delay(sc); 565 if (CSR_READ_4(sc, DC_SIO) & DC_SIO_EE_DATAOUT) 566 word |= i; 567 dc_delay(sc); 568 SIO_CLR(DC_SIO_EE_CLK); 569 dc_delay(sc); 570 } 571 572 /* Turn off EEPROM access mode. */ 573 dc_eeprom_idle(sc); 574 575 *dest = word; 576 } 577 578 /* 579 * Read a sequence of words from the EEPROM. 580 */ 581 static void 582 dc_read_eeprom(struct dc_softc *sc, caddr_t dest, int off, int cnt, int swap) 583 { 584 int i; 585 u_int16_t word = 0, *ptr; 586 587 for (i = 0; i < cnt; i++) { 588 if (DC_IS_PNIC(sc)) 589 dc_eeprom_getword_pnic(sc, off + i, &word); 590 else if (DC_IS_XIRCOM(sc)) 591 dc_eeprom_getword_xircom(sc, off + i, &word); 592 else 593 dc_eeprom_getword(sc, off + i, &word); 594 ptr = (u_int16_t *)(dest + (i * 2)); 595 if (swap) 596 *ptr = ntohs(word); 597 else 598 *ptr = word; 599 } 600 } 601 602 /* 603 * The following two routines are taken from the Macronix 98713 604 * Application Notes pp.19-21. 605 */ 606 /* 607 * Write a bit to the MII bus. 608 */ 609 static void 610 dc_mii_writebit(struct dc_softc *sc, int bit) 611 { 612 613 if (bit) 614 CSR_WRITE_4(sc, DC_SIO, 615 DC_SIO_ROMCTL_WRITE | DC_SIO_MII_DATAOUT); 616 else 617 CSR_WRITE_4(sc, DC_SIO, DC_SIO_ROMCTL_WRITE); 618 619 DC_SETBIT(sc, DC_SIO, DC_SIO_MII_CLK); 620 DC_CLRBIT(sc, DC_SIO, DC_SIO_MII_CLK); 621 } 622 623 /* 624 * Read a bit from the MII bus. 625 */ 626 static int 627 dc_mii_readbit(struct dc_softc *sc) 628 { 629 630 CSR_WRITE_4(sc, DC_SIO, DC_SIO_ROMCTL_READ | DC_SIO_MII_DIR); 631 CSR_READ_4(sc, DC_SIO); 632 DC_SETBIT(sc, DC_SIO, DC_SIO_MII_CLK); 633 DC_CLRBIT(sc, DC_SIO, DC_SIO_MII_CLK); 634 if (CSR_READ_4(sc, DC_SIO) & DC_SIO_MII_DATAIN) 635 return (1); 636 637 return (0); 638 } 639 640 /* 641 * Sync the PHYs by setting data bit and strobing the clock 32 times. 642 */ 643 static void 644 dc_mii_sync(struct dc_softc *sc) 645 { 646 int i; 647 648 CSR_WRITE_4(sc, DC_SIO, DC_SIO_ROMCTL_WRITE); 649 650 for (i = 0; i < 32; i++) 651 dc_mii_writebit(sc, 1); 652 } 653 654 /* 655 * Clock a series of bits through the MII. 656 */ 657 static void 658 dc_mii_send(struct dc_softc *sc, u_int32_t bits, int cnt) 659 { 660 int i; 661 662 for (i = (0x1 << (cnt - 1)); i; i >>= 1) 663 dc_mii_writebit(sc, bits & i); 664 } 665 666 /* 667 * Read an PHY register through the MII. 668 */ 669 static int 670 dc_mii_readreg(struct dc_softc *sc, struct dc_mii_frame *frame) 671 { 672 int i, ack; 673 674 DC_LOCK(sc); 675 676 /* 677 * Set up frame for RX. 678 */ 679 frame->mii_stdelim = DC_MII_STARTDELIM; 680 frame->mii_opcode = DC_MII_READOP; 681 frame->mii_turnaround = 0; 682 frame->mii_data = 0; 683 684 /* 685 * Sync the PHYs. 686 */ 687 dc_mii_sync(sc); 688 689 /* 690 * Send command/address info. 691 */ 692 dc_mii_send(sc, frame->mii_stdelim, 2); 693 dc_mii_send(sc, frame->mii_opcode, 2); 694 dc_mii_send(sc, frame->mii_phyaddr, 5); 695 dc_mii_send(sc, frame->mii_regaddr, 5); 696 697 #ifdef notdef 698 /* Idle bit */ 699 dc_mii_writebit(sc, 1); 700 dc_mii_writebit(sc, 0); 701 #endif 702 703 /* Check for ack. */ 704 ack = dc_mii_readbit(sc); 705 706 /* 707 * Now try reading data bits. If the ack failed, we still 708 * need to clock through 16 cycles to keep the PHY(s) in sync. 709 */ 710 if (ack) { 711 for (i = 0; i < 16; i++) 712 dc_mii_readbit(sc); 713 goto fail; 714 } 715 716 for (i = 0x8000; i; i >>= 1) { 717 if (!ack) { 718 if (dc_mii_readbit(sc)) 719 frame->mii_data |= i; 720 } 721 } 722 723 fail: 724 725 dc_mii_writebit(sc, 0); 726 dc_mii_writebit(sc, 0); 727 728 DC_UNLOCK(sc); 729 730 if (ack) 731 return (1); 732 return (0); 733 } 734 735 /* 736 * Write to a PHY register through the MII. 737 */ 738 static int 739 dc_mii_writereg(struct dc_softc *sc, struct dc_mii_frame *frame) 740 { 741 742 DC_LOCK(sc); 743 /* 744 * Set up frame for TX. 745 */ 746 747 frame->mii_stdelim = DC_MII_STARTDELIM; 748 frame->mii_opcode = DC_MII_WRITEOP; 749 frame->mii_turnaround = DC_MII_TURNAROUND; 750 751 /* 752 * Sync the PHYs. 753 */ 754 dc_mii_sync(sc); 755 756 dc_mii_send(sc, frame->mii_stdelim, 2); 757 dc_mii_send(sc, frame->mii_opcode, 2); 758 dc_mii_send(sc, frame->mii_phyaddr, 5); 759 dc_mii_send(sc, frame->mii_regaddr, 5); 760 dc_mii_send(sc, frame->mii_turnaround, 2); 761 dc_mii_send(sc, frame->mii_data, 16); 762 763 /* Idle bit. */ 764 dc_mii_writebit(sc, 0); 765 dc_mii_writebit(sc, 0); 766 767 DC_UNLOCK(sc); 768 769 return (0); 770 } 771 772 static int 773 dc_miibus_readreg(device_t dev, int phy, int reg) 774 { 775 struct dc_mii_frame frame; 776 struct dc_softc *sc; 777 int i, rval, phy_reg = 0; 778 779 sc = device_get_softc(dev); 780 bzero(&frame, sizeof(frame)); 781 782 /* 783 * Note: both the AL981 and AN985 have internal PHYs, 784 * however the AL981 provides direct access to the PHY 785 * registers while the AN985 uses a serial MII interface. 786 * The AN985's MII interface is also buggy in that you 787 * can read from any MII address (0 to 31), but only address 1 788 * behaves normally. To deal with both cases, we pretend 789 * that the PHY is at MII address 1. 790 */ 791 if (DC_IS_ADMTEK(sc) && phy != DC_ADMTEK_PHYADDR) 792 return (0); 793 794 /* 795 * Note: the ukphy probes of the RS7112 report a PHY at 796 * MII address 0 (possibly HomePNA?) and 1 (ethernet) 797 * so we only respond to correct one. 798 */ 799 if (DC_IS_CONEXANT(sc) && phy != DC_CONEXANT_PHYADDR) 800 return (0); 801 802 if (sc->dc_pmode != DC_PMODE_MII) { 803 if (phy == (MII_NPHY - 1)) { 804 switch (reg) { 805 case MII_BMSR: 806 /* 807 * Fake something to make the probe 808 * code think there's a PHY here. 809 */ 810 return (BMSR_MEDIAMASK); 811 break; 812 case MII_PHYIDR1: 813 if (DC_IS_PNIC(sc)) 814 return (DC_VENDORID_LO); 815 return (DC_VENDORID_DEC); 816 break; 817 case MII_PHYIDR2: 818 if (DC_IS_PNIC(sc)) 819 return (DC_DEVICEID_82C168); 820 return (DC_DEVICEID_21143); 821 break; 822 default: 823 return (0); 824 break; 825 } 826 } else 827 return (0); 828 } 829 830 if (DC_IS_PNIC(sc)) { 831 CSR_WRITE_4(sc, DC_PN_MII, DC_PN_MIIOPCODE_READ | 832 (phy << 23) | (reg << 18)); 833 for (i = 0; i < DC_TIMEOUT; i++) { 834 DELAY(1); 835 rval = CSR_READ_4(sc, DC_PN_MII); 836 if (!(rval & DC_PN_MII_BUSY)) { 837 rval &= 0xFFFF; 838 return (rval == 0xFFFF ? 0 : rval); 839 } 840 } 841 return (0); 842 } 843 844 if (DC_IS_COMET(sc)) { 845 switch (reg) { 846 case MII_BMCR: 847 phy_reg = DC_AL_BMCR; 848 break; 849 case MII_BMSR: 850 phy_reg = DC_AL_BMSR; 851 break; 852 case MII_PHYIDR1: 853 phy_reg = DC_AL_VENID; 854 break; 855 case MII_PHYIDR2: 856 phy_reg = DC_AL_DEVID; 857 break; 858 case MII_ANAR: 859 phy_reg = DC_AL_ANAR; 860 break; 861 case MII_ANLPAR: 862 phy_reg = DC_AL_LPAR; 863 break; 864 case MII_ANER: 865 phy_reg = DC_AL_ANER; 866 break; 867 default: 868 printf("dc%d: phy_read: bad phy register %x\n", 869 sc->dc_unit, reg); 870 return (0); 871 break; 872 } 873 874 rval = CSR_READ_4(sc, phy_reg) & 0x0000FFFF; 875 876 if (rval == 0xFFFF) 877 return (0); 878 return (rval); 879 } 880 881 frame.mii_phyaddr = phy; 882 frame.mii_regaddr = reg; 883 if (sc->dc_type == DC_TYPE_98713) { 884 phy_reg = CSR_READ_4(sc, DC_NETCFG); 885 CSR_WRITE_4(sc, DC_NETCFG, phy_reg & ~DC_NETCFG_PORTSEL); 886 } 887 dc_mii_readreg(sc, &frame); 888 if (sc->dc_type == DC_TYPE_98713) 889 CSR_WRITE_4(sc, DC_NETCFG, phy_reg); 890 891 return (frame.mii_data); 892 } 893 894 static int 895 dc_miibus_writereg(device_t dev, int phy, int reg, int data) 896 { 897 struct dc_softc *sc; 898 struct dc_mii_frame frame; 899 int i, phy_reg = 0; 900 901 sc = device_get_softc(dev); 902 bzero(&frame, sizeof(frame)); 903 904 if (DC_IS_ADMTEK(sc) && phy != DC_ADMTEK_PHYADDR) 905 return (0); 906 907 if (DC_IS_CONEXANT(sc) && phy != DC_CONEXANT_PHYADDR) 908 return (0); 909 910 if (DC_IS_PNIC(sc)) { 911 CSR_WRITE_4(sc, DC_PN_MII, DC_PN_MIIOPCODE_WRITE | 912 (phy << 23) | (reg << 10) | data); 913 for (i = 0; i < DC_TIMEOUT; i++) { 914 if (!(CSR_READ_4(sc, DC_PN_MII) & DC_PN_MII_BUSY)) 915 break; 916 } 917 return (0); 918 } 919 920 if (DC_IS_COMET(sc)) { 921 switch (reg) { 922 case MII_BMCR: 923 phy_reg = DC_AL_BMCR; 924 break; 925 case MII_BMSR: 926 phy_reg = DC_AL_BMSR; 927 break; 928 case MII_PHYIDR1: 929 phy_reg = DC_AL_VENID; 930 break; 931 case MII_PHYIDR2: 932 phy_reg = DC_AL_DEVID; 933 break; 934 case MII_ANAR: 935 phy_reg = DC_AL_ANAR; 936 break; 937 case MII_ANLPAR: 938 phy_reg = DC_AL_LPAR; 939 break; 940 case MII_ANER: 941 phy_reg = DC_AL_ANER; 942 break; 943 default: 944 printf("dc%d: phy_write: bad phy register %x\n", 945 sc->dc_unit, reg); 946 return (0); 947 break; 948 } 949 950 CSR_WRITE_4(sc, phy_reg, data); 951 return (0); 952 } 953 954 frame.mii_phyaddr = phy; 955 frame.mii_regaddr = reg; 956 frame.mii_data = data; 957 958 if (sc->dc_type == DC_TYPE_98713) { 959 phy_reg = CSR_READ_4(sc, DC_NETCFG); 960 CSR_WRITE_4(sc, DC_NETCFG, phy_reg & ~DC_NETCFG_PORTSEL); 961 } 962 dc_mii_writereg(sc, &frame); 963 if (sc->dc_type == DC_TYPE_98713) 964 CSR_WRITE_4(sc, DC_NETCFG, phy_reg); 965 966 return (0); 967 } 968 969 static void 970 dc_miibus_statchg(device_t dev) 971 { 972 struct dc_softc *sc; 973 struct mii_data *mii; 974 struct ifmedia *ifm; 975 976 sc = device_get_softc(dev); 977 if (DC_IS_ADMTEK(sc)) 978 return; 979 980 mii = device_get_softc(sc->dc_miibus); 981 ifm = &mii->mii_media; 982 if (DC_IS_DAVICOM(sc) && 983 IFM_SUBTYPE(ifm->ifm_media) == IFM_HPNA_1) { 984 dc_setcfg(sc, ifm->ifm_media); 985 sc->dc_if_media = ifm->ifm_media; 986 } else { 987 dc_setcfg(sc, mii->mii_media_active); 988 sc->dc_if_media = mii->mii_media_active; 989 } 990 } 991 992 /* 993 * Special support for DM9102A cards with HomePNA PHYs. Note: 994 * with the Davicom DM9102A/DM9801 eval board that I have, it seems 995 * to be impossible to talk to the management interface of the DM9801 996 * PHY (its MDIO pin is not connected to anything). Consequently, 997 * the driver has to just 'know' about the additional mode and deal 998 * with it itself. *sigh* 999 */ 1000 static void 1001 dc_miibus_mediainit(device_t dev) 1002 { 1003 struct dc_softc *sc; 1004 struct mii_data *mii; 1005 struct ifmedia *ifm; 1006 int rev; 1007 1008 rev = pci_read_config(dev, DC_PCI_CFRV, 4) & 0xFF; 1009 1010 sc = device_get_softc(dev); 1011 mii = device_get_softc(sc->dc_miibus); 1012 ifm = &mii->mii_media; 1013 1014 if (DC_IS_DAVICOM(sc) && rev >= DC_REVISION_DM9102A) 1015 ifmedia_add(ifm, IFM_ETHER | IFM_HPNA_1, 0, NULL); 1016 } 1017 1018 #define DC_POLY 0xEDB88320 1019 #define DC_BITS_512 9 1020 #define DC_BITS_128 7 1021 #define DC_BITS_64 6 1022 1023 static u_int32_t 1024 dc_crc_le(struct dc_softc *sc, const uint8_t *addr) 1025 { 1026 uint32_t idx, bit, data, crc; 1027 1028 /* Compute CRC for the address value. */ 1029 crc = 0xFFFFFFFF; /* initial value */ 1030 1031 for (idx = 0; idx < 6; idx++) { 1032 for (data = *addr++, bit = 0; bit < 8; bit++, data >>= 1) 1033 crc = (crc >> 1) ^ (((crc ^ data) & 1) ? DC_POLY : 0); 1034 } 1035 1036 /* 1037 * The hash table on the PNIC II and the MX98715AEC-C/D/E 1038 * chips is only 128 bits wide. 1039 */ 1040 if (sc->dc_flags & DC_128BIT_HASH) 1041 return (crc & ((1 << DC_BITS_128) - 1)); 1042 1043 /* The hash table on the MX98715BEC is only 64 bits wide. */ 1044 if (sc->dc_flags & DC_64BIT_HASH) 1045 return (crc & ((1 << DC_BITS_64) - 1)); 1046 1047 /* Xircom's hash filtering table is different (read: weird) */ 1048 /* Xircom uses the LEAST significant bits */ 1049 if (DC_IS_XIRCOM(sc)) { 1050 if ((crc & 0x180) == 0x180) 1051 return ((crc & 0x0F) + (crc & 0x70) * 3 + (14 << 4)); 1052 else 1053 return ((crc & 0x1F) + ((crc >> 1) & 0xF0) * 3 + 1054 (12 << 4)); 1055 } 1056 1057 return (crc & ((1 << DC_BITS_512) - 1)); 1058 } 1059 1060 /* 1061 * Calculate CRC of a multicast group address, return the lower 6 bits. 1062 */ 1063 static u_int32_t 1064 dc_crc_be(const uint8_t *addr) 1065 { 1066 uint32_t crc, carry; 1067 int i, j; 1068 uint8_t c; 1069 1070 /* Compute CRC for the address value. */ 1071 crc = 0xFFFFFFFF; /* initial value */ 1072 1073 for (i = 0; i < 6; i++) { 1074 c = *(addr + i); 1075 for (j = 0; j < 8; j++) { 1076 carry = ((crc & 0x80000000) ? 1 : 0) ^ (c & 0x01); 1077 crc <<= 1; 1078 c >>= 1; 1079 if (carry) 1080 crc = (crc ^ 0x04c11db6) | carry; 1081 } 1082 } 1083 1084 /* Return the filter bit position. */ 1085 return ((crc >> 26) & 0x0000003F); 1086 } 1087 1088 /* 1089 * 21143-style RX filter setup routine. Filter programming is done by 1090 * downloading a special setup frame into the TX engine. 21143, Macronix, 1091 * PNIC, PNIC II and Davicom chips are programmed this way. 1092 * 1093 * We always program the chip using 'hash perfect' mode, i.e. one perfect 1094 * address (our node address) and a 512-bit hash filter for multicast 1095 * frames. We also sneak the broadcast address into the hash filter since 1096 * we need that too. 1097 */ 1098 static void 1099 dc_setfilt_21143(struct dc_softc *sc) 1100 { 1101 struct dc_desc *sframe; 1102 u_int32_t h, *sp; 1103 struct ifmultiaddr *ifma; 1104 struct ifnet *ifp; 1105 int i; 1106 1107 ifp = &sc->arpcom.ac_if; 1108 1109 i = sc->dc_cdata.dc_tx_prod; 1110 DC_INC(sc->dc_cdata.dc_tx_prod, DC_TX_LIST_CNT); 1111 sc->dc_cdata.dc_tx_cnt++; 1112 sframe = &sc->dc_ldata->dc_tx_list[i]; 1113 sp = sc->dc_cdata.dc_sbuf; 1114 bzero(sp, DC_SFRAME_LEN); 1115 1116 sframe->dc_data = htole32(sc->dc_saddr); 1117 sframe->dc_ctl = htole32(DC_SFRAME_LEN | DC_TXCTL_SETUP | 1118 DC_TXCTL_TLINK | DC_FILTER_HASHPERF | DC_TXCTL_FINT); 1119 1120 sc->dc_cdata.dc_tx_chain[i] = (struct mbuf *)sc->dc_cdata.dc_sbuf; 1121 1122 /* If we want promiscuous mode, set the allframes bit. */ 1123 if (ifp->if_flags & IFF_PROMISC) 1124 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC); 1125 else 1126 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC); 1127 1128 if (ifp->if_flags & IFF_ALLMULTI) 1129 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI); 1130 else 1131 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI); 1132 1133 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 1134 if (ifma->ifma_addr->sa_family != AF_LINK) 1135 continue; 1136 h = dc_crc_le(sc, 1137 LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 1138 sp[h >> 4] |= htole32(1 << (h & 0xF)); 1139 } 1140 1141 if (ifp->if_flags & IFF_BROADCAST) { 1142 h = dc_crc_le(sc, ifp->if_broadcastaddr); 1143 sp[h >> 4] |= htole32(1 << (h & 0xF)); 1144 } 1145 1146 /* Set our MAC address */ 1147 sp[39] = DC_SP_MAC(((u_int16_t *)sc->arpcom.ac_enaddr)[0]); 1148 sp[40] = DC_SP_MAC(((u_int16_t *)sc->arpcom.ac_enaddr)[1]); 1149 sp[41] = DC_SP_MAC(((u_int16_t *)sc->arpcom.ac_enaddr)[2]); 1150 1151 sframe->dc_status = htole32(DC_TXSTAT_OWN); 1152 CSR_WRITE_4(sc, DC_TXSTART, 0xFFFFFFFF); 1153 1154 /* 1155 * The PNIC takes an exceedingly long time to process its 1156 * setup frame; wait 10ms after posting the setup frame 1157 * before proceeding, just so it has time to swallow its 1158 * medicine. 1159 */ 1160 DELAY(10000); 1161 1162 ifp->if_timer = 5; 1163 } 1164 1165 static void 1166 dc_setfilt_admtek(struct dc_softc *sc) 1167 { 1168 struct ifnet *ifp; 1169 struct ifmultiaddr *ifma; 1170 int h = 0; 1171 u_int32_t hashes[2] = { 0, 0 }; 1172 1173 ifp = &sc->arpcom.ac_if; 1174 1175 /* Init our MAC address. */ 1176 CSR_WRITE_4(sc, DC_AL_PAR0, *(u_int32_t *)(&sc->arpcom.ac_enaddr[0])); 1177 CSR_WRITE_4(sc, DC_AL_PAR1, *(u_int32_t *)(&sc->arpcom.ac_enaddr[4])); 1178 1179 /* If we want promiscuous mode, set the allframes bit. */ 1180 if (ifp->if_flags & IFF_PROMISC) 1181 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC); 1182 else 1183 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC); 1184 1185 if (ifp->if_flags & IFF_ALLMULTI) 1186 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI); 1187 else 1188 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI); 1189 1190 /* First, zot all the existing hash bits. */ 1191 CSR_WRITE_4(sc, DC_AL_MAR0, 0); 1192 CSR_WRITE_4(sc, DC_AL_MAR1, 0); 1193 1194 /* 1195 * If we're already in promisc or allmulti mode, we 1196 * don't have to bother programming the multicast filter. 1197 */ 1198 if (ifp->if_flags & (IFF_PROMISC | IFF_ALLMULTI)) 1199 return; 1200 1201 /* Now program new ones. */ 1202 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 1203 if (ifma->ifma_addr->sa_family != AF_LINK) 1204 continue; 1205 if (DC_IS_CENTAUR(sc)) 1206 h = dc_crc_le(sc, LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 1207 else 1208 h = dc_crc_be(LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 1209 if (h < 32) 1210 hashes[0] |= (1 << h); 1211 else 1212 hashes[1] |= (1 << (h - 32)); 1213 } 1214 1215 CSR_WRITE_4(sc, DC_AL_MAR0, hashes[0]); 1216 CSR_WRITE_4(sc, DC_AL_MAR1, hashes[1]); 1217 } 1218 1219 static void 1220 dc_setfilt_asix(struct dc_softc *sc) 1221 { 1222 struct ifnet *ifp; 1223 struct ifmultiaddr *ifma; 1224 int h = 0; 1225 u_int32_t hashes[2] = { 0, 0 }; 1226 1227 ifp = &sc->arpcom.ac_if; 1228 1229 /* Init our MAC address */ 1230 CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_PAR0); 1231 CSR_WRITE_4(sc, DC_AX_FILTDATA, 1232 *(u_int32_t *)(&sc->arpcom.ac_enaddr[0])); 1233 CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_PAR1); 1234 CSR_WRITE_4(sc, DC_AX_FILTDATA, 1235 *(u_int32_t *)(&sc->arpcom.ac_enaddr[4])); 1236 1237 /* If we want promiscuous mode, set the allframes bit. */ 1238 if (ifp->if_flags & IFF_PROMISC) 1239 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC); 1240 else 1241 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC); 1242 1243 if (ifp->if_flags & IFF_ALLMULTI) 1244 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI); 1245 else 1246 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI); 1247 1248 /* 1249 * The ASIX chip has a special bit to enable reception 1250 * of broadcast frames. 1251 */ 1252 if (ifp->if_flags & IFF_BROADCAST) 1253 DC_SETBIT(sc, DC_NETCFG, DC_AX_NETCFG_RX_BROAD); 1254 else 1255 DC_CLRBIT(sc, DC_NETCFG, DC_AX_NETCFG_RX_BROAD); 1256 1257 /* first, zot all the existing hash bits */ 1258 CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_MAR0); 1259 CSR_WRITE_4(sc, DC_AX_FILTDATA, 0); 1260 CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_MAR1); 1261 CSR_WRITE_4(sc, DC_AX_FILTDATA, 0); 1262 1263 /* 1264 * If we're already in promisc or allmulti mode, we 1265 * don't have to bother programming the multicast filter. 1266 */ 1267 if (ifp->if_flags & (IFF_PROMISC | IFF_ALLMULTI)) 1268 return; 1269 1270 /* now program new ones */ 1271 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 1272 if (ifma->ifma_addr->sa_family != AF_LINK) 1273 continue; 1274 h = dc_crc_be(LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 1275 if (h < 32) 1276 hashes[0] |= (1 << h); 1277 else 1278 hashes[1] |= (1 << (h - 32)); 1279 } 1280 1281 CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_MAR0); 1282 CSR_WRITE_4(sc, DC_AX_FILTDATA, hashes[0]); 1283 CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_MAR1); 1284 CSR_WRITE_4(sc, DC_AX_FILTDATA, hashes[1]); 1285 } 1286 1287 static void 1288 dc_setfilt_xircom(struct dc_softc *sc) 1289 { 1290 struct ifnet *ifp; 1291 struct ifmultiaddr *ifma; 1292 struct dc_desc *sframe; 1293 u_int32_t h, *sp; 1294 int i; 1295 1296 ifp = &sc->arpcom.ac_if; 1297 DC_CLRBIT(sc, DC_NETCFG, (DC_NETCFG_TX_ON | DC_NETCFG_RX_ON)); 1298 1299 i = sc->dc_cdata.dc_tx_prod; 1300 DC_INC(sc->dc_cdata.dc_tx_prod, DC_TX_LIST_CNT); 1301 sc->dc_cdata.dc_tx_cnt++; 1302 sframe = &sc->dc_ldata->dc_tx_list[i]; 1303 sp = sc->dc_cdata.dc_sbuf; 1304 bzero(sp, DC_SFRAME_LEN); 1305 1306 sframe->dc_data = htole32(sc->dc_saddr); 1307 sframe->dc_ctl = htole32(DC_SFRAME_LEN | DC_TXCTL_SETUP | 1308 DC_TXCTL_TLINK | DC_FILTER_HASHPERF | DC_TXCTL_FINT); 1309 1310 sc->dc_cdata.dc_tx_chain[i] = (struct mbuf *)sc->dc_cdata.dc_sbuf; 1311 1312 /* If we want promiscuous mode, set the allframes bit. */ 1313 if (ifp->if_flags & IFF_PROMISC) 1314 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC); 1315 else 1316 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC); 1317 1318 if (ifp->if_flags & IFF_ALLMULTI) 1319 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI); 1320 else 1321 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI); 1322 1323 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 1324 if (ifma->ifma_addr->sa_family != AF_LINK) 1325 continue; 1326 h = dc_crc_le(sc, 1327 LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 1328 sp[h >> 4] |= htole32(1 << (h & 0xF)); 1329 } 1330 1331 if (ifp->if_flags & IFF_BROADCAST) { 1332 h = dc_crc_le(sc, ifp->if_broadcastaddr); 1333 sp[h >> 4] |= htole32(1 << (h & 0xF)); 1334 } 1335 1336 /* Set our MAC address */ 1337 sp[0] = DC_SP_MAC(((u_int16_t *)sc->arpcom.ac_enaddr)[0]); 1338 sp[1] = DC_SP_MAC(((u_int16_t *)sc->arpcom.ac_enaddr)[1]); 1339 sp[2] = DC_SP_MAC(((u_int16_t *)sc->arpcom.ac_enaddr)[2]); 1340 1341 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_TX_ON); 1342 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_ON); 1343 ifp->if_flags |= IFF_RUNNING; 1344 sframe->dc_status = htole32(DC_TXSTAT_OWN); 1345 CSR_WRITE_4(sc, DC_TXSTART, 0xFFFFFFFF); 1346 1347 /* 1348 * Wait some time... 1349 */ 1350 DELAY(1000); 1351 1352 ifp->if_timer = 5; 1353 } 1354 1355 static void 1356 dc_setfilt(struct dc_softc *sc) 1357 { 1358 1359 if (DC_IS_INTEL(sc) || DC_IS_MACRONIX(sc) || DC_IS_PNIC(sc) || 1360 DC_IS_PNICII(sc) || DC_IS_DAVICOM(sc) || DC_IS_CONEXANT(sc)) 1361 dc_setfilt_21143(sc); 1362 1363 if (DC_IS_ASIX(sc)) 1364 dc_setfilt_asix(sc); 1365 1366 if (DC_IS_ADMTEK(sc)) 1367 dc_setfilt_admtek(sc); 1368 1369 if (DC_IS_XIRCOM(sc)) 1370 dc_setfilt_xircom(sc); 1371 } 1372 1373 /* 1374 * In order to fiddle with the 'full-duplex' and '100Mbps' bits in 1375 * the netconfig register, we first have to put the transmit and/or 1376 * receive logic in the idle state. 1377 */ 1378 static void 1379 dc_setcfg(struct dc_softc *sc, int media) 1380 { 1381 int i, restart = 0, watchdogreg; 1382 u_int32_t isr; 1383 1384 if (IFM_SUBTYPE(media) == IFM_NONE) 1385 return; 1386 1387 if (CSR_READ_4(sc, DC_NETCFG) & (DC_NETCFG_TX_ON | DC_NETCFG_RX_ON)) { 1388 restart = 1; 1389 DC_CLRBIT(sc, DC_NETCFG, (DC_NETCFG_TX_ON | DC_NETCFG_RX_ON)); 1390 1391 for (i = 0; i < DC_TIMEOUT; i++) { 1392 isr = CSR_READ_4(sc, DC_ISR); 1393 if (isr & DC_ISR_TX_IDLE && 1394 ((isr & DC_ISR_RX_STATE) == DC_RXSTATE_STOPPED || 1395 (isr & DC_ISR_RX_STATE) == DC_RXSTATE_WAIT)) 1396 break; 1397 DELAY(10); 1398 } 1399 1400 if (i == DC_TIMEOUT) 1401 printf("dc%d: failed to force tx and " 1402 "rx to idle state\n", sc->dc_unit); 1403 } 1404 1405 if (IFM_SUBTYPE(media) == IFM_100_TX) { 1406 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_SPEEDSEL); 1407 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_HEARTBEAT); 1408 if (sc->dc_pmode == DC_PMODE_MII) { 1409 if (DC_IS_INTEL(sc)) { 1410 /* There's a write enable bit here that reads as 1. */ 1411 watchdogreg = CSR_READ_4(sc, DC_WATCHDOG); 1412 watchdogreg &= ~DC_WDOG_CTLWREN; 1413 watchdogreg |= DC_WDOG_JABBERDIS; 1414 CSR_WRITE_4(sc, DC_WATCHDOG, watchdogreg); 1415 } else { 1416 DC_SETBIT(sc, DC_WATCHDOG, DC_WDOG_JABBERDIS); 1417 } 1418 DC_CLRBIT(sc, DC_NETCFG, (DC_NETCFG_PCS | 1419 DC_NETCFG_PORTSEL | DC_NETCFG_SCRAMBLER)); 1420 if (sc->dc_type == DC_TYPE_98713) 1421 DC_SETBIT(sc, DC_NETCFG, (DC_NETCFG_PCS | 1422 DC_NETCFG_SCRAMBLER)); 1423 if (!DC_IS_DAVICOM(sc)) 1424 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL); 1425 DC_CLRBIT(sc, DC_10BTCTRL, 0xFFFF); 1426 if (DC_IS_INTEL(sc)) 1427 dc_apply_fixup(sc, IFM_AUTO); 1428 } else { 1429 if (DC_IS_PNIC(sc)) { 1430 DC_PN_GPIO_SETBIT(sc, DC_PN_GPIO_SPEEDSEL); 1431 DC_PN_GPIO_SETBIT(sc, DC_PN_GPIO_100TX_LOOP); 1432 DC_SETBIT(sc, DC_PN_NWAY, DC_PN_NWAY_SPEEDSEL); 1433 } 1434 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL); 1435 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PCS); 1436 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_SCRAMBLER); 1437 if (DC_IS_INTEL(sc)) 1438 dc_apply_fixup(sc, 1439 (media & IFM_GMASK) == IFM_FDX ? 1440 IFM_100_TX | IFM_FDX : IFM_100_TX); 1441 } 1442 } 1443 1444 if (IFM_SUBTYPE(media) == IFM_10_T) { 1445 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_SPEEDSEL); 1446 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_HEARTBEAT); 1447 if (sc->dc_pmode == DC_PMODE_MII) { 1448 /* There's a write enable bit here that reads as 1. */ 1449 if (DC_IS_INTEL(sc)) { 1450 watchdogreg = CSR_READ_4(sc, DC_WATCHDOG); 1451 watchdogreg &= ~DC_WDOG_CTLWREN; 1452 watchdogreg |= DC_WDOG_JABBERDIS; 1453 CSR_WRITE_4(sc, DC_WATCHDOG, watchdogreg); 1454 } else { 1455 DC_SETBIT(sc, DC_WATCHDOG, DC_WDOG_JABBERDIS); 1456 } 1457 DC_CLRBIT(sc, DC_NETCFG, (DC_NETCFG_PCS | 1458 DC_NETCFG_PORTSEL | DC_NETCFG_SCRAMBLER)); 1459 if (sc->dc_type == DC_TYPE_98713) 1460 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PCS); 1461 if (!DC_IS_DAVICOM(sc)) 1462 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL); 1463 DC_CLRBIT(sc, DC_10BTCTRL, 0xFFFF); 1464 if (DC_IS_INTEL(sc)) 1465 dc_apply_fixup(sc, IFM_AUTO); 1466 } else { 1467 if (DC_IS_PNIC(sc)) { 1468 DC_PN_GPIO_CLRBIT(sc, DC_PN_GPIO_SPEEDSEL); 1469 DC_PN_GPIO_SETBIT(sc, DC_PN_GPIO_100TX_LOOP); 1470 DC_CLRBIT(sc, DC_PN_NWAY, DC_PN_NWAY_SPEEDSEL); 1471 } 1472 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL); 1473 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_PCS); 1474 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_SCRAMBLER); 1475 if (DC_IS_INTEL(sc)) { 1476 DC_CLRBIT(sc, DC_SIARESET, DC_SIA_RESET); 1477 DC_CLRBIT(sc, DC_10BTCTRL, 0xFFFF); 1478 if ((media & IFM_GMASK) == IFM_FDX) 1479 DC_SETBIT(sc, DC_10BTCTRL, 0x7F3D); 1480 else 1481 DC_SETBIT(sc, DC_10BTCTRL, 0x7F3F); 1482 DC_SETBIT(sc, DC_SIARESET, DC_SIA_RESET); 1483 DC_CLRBIT(sc, DC_10BTCTRL, 1484 DC_TCTL_AUTONEGENBL); 1485 dc_apply_fixup(sc, 1486 (media & IFM_GMASK) == IFM_FDX ? 1487 IFM_10_T | IFM_FDX : IFM_10_T); 1488 DELAY(20000); 1489 } 1490 } 1491 } 1492 1493 /* 1494 * If this is a Davicom DM9102A card with a DM9801 HomePNA 1495 * PHY and we want HomePNA mode, set the portsel bit to turn 1496 * on the external MII port. 1497 */ 1498 if (DC_IS_DAVICOM(sc)) { 1499 if (IFM_SUBTYPE(media) == IFM_HPNA_1) { 1500 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL); 1501 sc->dc_link = 1; 1502 } else { 1503 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL); 1504 } 1505 } 1506 1507 if ((media & IFM_GMASK) == IFM_FDX) { 1508 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_FULLDUPLEX); 1509 if (sc->dc_pmode == DC_PMODE_SYM && DC_IS_PNIC(sc)) 1510 DC_SETBIT(sc, DC_PN_NWAY, DC_PN_NWAY_DUPLEX); 1511 } else { 1512 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_FULLDUPLEX); 1513 if (sc->dc_pmode == DC_PMODE_SYM && DC_IS_PNIC(sc)) 1514 DC_CLRBIT(sc, DC_PN_NWAY, DC_PN_NWAY_DUPLEX); 1515 } 1516 1517 if (restart) 1518 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_TX_ON | DC_NETCFG_RX_ON); 1519 } 1520 1521 static void 1522 dc_reset(struct dc_softc *sc) 1523 { 1524 int i; 1525 1526 DC_SETBIT(sc, DC_BUSCTL, DC_BUSCTL_RESET); 1527 1528 for (i = 0; i < DC_TIMEOUT; i++) { 1529 DELAY(10); 1530 if (!(CSR_READ_4(sc, DC_BUSCTL) & DC_BUSCTL_RESET)) 1531 break; 1532 } 1533 1534 if (DC_IS_ASIX(sc) || DC_IS_ADMTEK(sc) || DC_IS_CONEXANT(sc) || 1535 DC_IS_XIRCOM(sc) || DC_IS_INTEL(sc)) { 1536 DELAY(10000); 1537 DC_CLRBIT(sc, DC_BUSCTL, DC_BUSCTL_RESET); 1538 i = 0; 1539 } 1540 1541 if (i == DC_TIMEOUT) 1542 printf("dc%d: reset never completed!\n", sc->dc_unit); 1543 1544 /* Wait a little while for the chip to get its brains in order. */ 1545 DELAY(1000); 1546 1547 CSR_WRITE_4(sc, DC_IMR, 0x00000000); 1548 CSR_WRITE_4(sc, DC_BUSCTL, 0x00000000); 1549 CSR_WRITE_4(sc, DC_NETCFG, 0x00000000); 1550 1551 /* 1552 * Bring the SIA out of reset. In some cases, it looks 1553 * like failing to unreset the SIA soon enough gets it 1554 * into a state where it will never come out of reset 1555 * until we reset the whole chip again. 1556 */ 1557 if (DC_IS_INTEL(sc)) { 1558 DC_SETBIT(sc, DC_SIARESET, DC_SIA_RESET); 1559 CSR_WRITE_4(sc, DC_10BTCTRL, 0); 1560 CSR_WRITE_4(sc, DC_WATCHDOG, 0); 1561 } 1562 } 1563 1564 static struct dc_type * 1565 dc_devtype(device_t dev) 1566 { 1567 struct dc_type *t; 1568 u_int32_t rev; 1569 1570 t = dc_devs; 1571 1572 while (t->dc_name != NULL) { 1573 if ((pci_get_vendor(dev) == t->dc_vid) && 1574 (pci_get_device(dev) == t->dc_did)) { 1575 /* Check the PCI revision */ 1576 rev = pci_read_config(dev, DC_PCI_CFRV, 4) & 0xFF; 1577 if (t->dc_did == DC_DEVICEID_98713 && 1578 rev >= DC_REVISION_98713A) 1579 t++; 1580 if (t->dc_did == DC_DEVICEID_98713_CP && 1581 rev >= DC_REVISION_98713A) 1582 t++; 1583 if (t->dc_did == DC_DEVICEID_987x5 && 1584 rev >= DC_REVISION_98715AEC_C) 1585 t++; 1586 if (t->dc_did == DC_DEVICEID_987x5 && 1587 rev >= DC_REVISION_98725) 1588 t++; 1589 if (t->dc_did == DC_DEVICEID_AX88140A && 1590 rev >= DC_REVISION_88141) 1591 t++; 1592 if (t->dc_did == DC_DEVICEID_82C168 && 1593 rev >= DC_REVISION_82C169) 1594 t++; 1595 if (t->dc_did == DC_DEVICEID_DM9102 && 1596 rev >= DC_REVISION_DM9102A) 1597 t++; 1598 /* 1599 * The Microsoft MN-130 has a device ID of 0x0002, 1600 * which happens to be the same as the PNIC 82c168. 1601 * To keep dc_attach() from getting confused, we 1602 * pretend its ID is something different. 1603 * XXX: ideally, dc_attach() should be checking 1604 * vendorid+deviceid together to avoid such 1605 * collisions. 1606 */ 1607 if (t->dc_vid == DC_VENDORID_MICROSOFT && 1608 t->dc_did == DC_DEVICEID_MSMN130) 1609 t++; 1610 return (t); 1611 } 1612 t++; 1613 } 1614 1615 return (NULL); 1616 } 1617 1618 /* 1619 * Probe for a 21143 or clone chip. Check the PCI vendor and device 1620 * IDs against our list and return a device name if we find a match. 1621 * We do a little bit of extra work to identify the exact type of 1622 * chip. The MX98713 and MX98713A have the same PCI vendor/device ID, 1623 * but different revision IDs. The same is true for 98715/98715A 1624 * chips and the 98725, as well as the ASIX and ADMtek chips. In some 1625 * cases, the exact chip revision affects driver behavior. 1626 */ 1627 static int 1628 dc_probe(device_t dev) 1629 { 1630 struct dc_type *t; 1631 1632 t = dc_devtype(dev); 1633 1634 if (t != NULL) { 1635 device_set_desc(dev, t->dc_name); 1636 return (0); 1637 } 1638 1639 return (ENXIO); 1640 } 1641 1642 #ifndef BURN_BRIDGES 1643 static void 1644 dc_acpi(device_t dev) 1645 { 1646 int unit; 1647 u_int32_t iobase, membase, irq; 1648 1649 unit = device_get_unit(dev); 1650 1651 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) { 1652 /* Save important PCI config data. */ 1653 iobase = pci_read_config(dev, DC_PCI_CFBIO, 4); 1654 membase = pci_read_config(dev, DC_PCI_CFBMA, 4); 1655 irq = pci_read_config(dev, DC_PCI_CFIT, 4); 1656 1657 /* Reset the power state. */ 1658 printf("dc%d: chip is in D%d power mode " 1659 "-- setting to D0\n", unit, 1660 pci_get_powerstate(dev)); 1661 pci_set_powerstate(dev, PCI_POWERSTATE_D0); 1662 1663 /* Restore PCI config data. */ 1664 pci_write_config(dev, DC_PCI_CFBIO, iobase, 4); 1665 pci_write_config(dev, DC_PCI_CFBMA, membase, 4); 1666 pci_write_config(dev, DC_PCI_CFIT, irq, 4); 1667 } 1668 } 1669 #endif 1670 1671 static void 1672 dc_apply_fixup(struct dc_softc *sc, int media) 1673 { 1674 struct dc_mediainfo *m; 1675 u_int8_t *p; 1676 int i; 1677 u_int32_t reg; 1678 1679 m = sc->dc_mi; 1680 1681 while (m != NULL) { 1682 if (m->dc_media == media) 1683 break; 1684 m = m->dc_next; 1685 } 1686 1687 if (m == NULL) 1688 return; 1689 1690 for (i = 0, p = m->dc_reset_ptr; i < m->dc_reset_len; i++, p += 2) { 1691 reg = (p[0] | (p[1] << 8)) << 16; 1692 CSR_WRITE_4(sc, DC_WATCHDOG, reg); 1693 } 1694 1695 for (i = 0, p = m->dc_gp_ptr; i < m->dc_gp_len; i++, p += 2) { 1696 reg = (p[0] | (p[1] << 8)) << 16; 1697 CSR_WRITE_4(sc, DC_WATCHDOG, reg); 1698 } 1699 } 1700 1701 static void 1702 dc_decode_leaf_sia(struct dc_softc *sc, struct dc_eblock_sia *l) 1703 { 1704 struct dc_mediainfo *m; 1705 1706 m = malloc(sizeof(struct dc_mediainfo), M_DEVBUF, M_NOWAIT | M_ZERO); 1707 switch (l->dc_sia_code & ~DC_SIA_CODE_EXT) { 1708 case DC_SIA_CODE_10BT: 1709 m->dc_media = IFM_10_T; 1710 break; 1711 case DC_SIA_CODE_10BT_FDX: 1712 m->dc_media = IFM_10_T | IFM_FDX; 1713 break; 1714 case DC_SIA_CODE_10B2: 1715 m->dc_media = IFM_10_2; 1716 break; 1717 case DC_SIA_CODE_10B5: 1718 m->dc_media = IFM_10_5; 1719 break; 1720 default: 1721 break; 1722 } 1723 1724 /* 1725 * We need to ignore CSR13, CSR14, CSR15 for SIA mode. 1726 * Things apparently already work for cards that do 1727 * supply Media Specific Data. 1728 */ 1729 if (l->dc_sia_code & DC_SIA_CODE_EXT) { 1730 m->dc_gp_len = 2; 1731 m->dc_gp_ptr = 1732 (u_int8_t *)&l->dc_un.dc_sia_ext.dc_sia_gpio_ctl; 1733 } else { 1734 m->dc_gp_len = 2; 1735 m->dc_gp_ptr = 1736 (u_int8_t *)&l->dc_un.dc_sia_noext.dc_sia_gpio_ctl; 1737 } 1738 1739 m->dc_next = sc->dc_mi; 1740 sc->dc_mi = m; 1741 1742 sc->dc_pmode = DC_PMODE_SIA; 1743 } 1744 1745 static void 1746 dc_decode_leaf_sym(struct dc_softc *sc, struct dc_eblock_sym *l) 1747 { 1748 struct dc_mediainfo *m; 1749 1750 m = malloc(sizeof(struct dc_mediainfo), M_DEVBUF, M_NOWAIT | M_ZERO); 1751 if (l->dc_sym_code == DC_SYM_CODE_100BT) 1752 m->dc_media = IFM_100_TX; 1753 1754 if (l->dc_sym_code == DC_SYM_CODE_100BT_FDX) 1755 m->dc_media = IFM_100_TX | IFM_FDX; 1756 1757 m->dc_gp_len = 2; 1758 m->dc_gp_ptr = (u_int8_t *)&l->dc_sym_gpio_ctl; 1759 1760 m->dc_next = sc->dc_mi; 1761 sc->dc_mi = m; 1762 1763 sc->dc_pmode = DC_PMODE_SYM; 1764 } 1765 1766 static void 1767 dc_decode_leaf_mii(struct dc_softc *sc, struct dc_eblock_mii *l) 1768 { 1769 struct dc_mediainfo *m; 1770 u_int8_t *p; 1771 1772 m = malloc(sizeof(struct dc_mediainfo), M_DEVBUF, M_NOWAIT | M_ZERO); 1773 /* We abuse IFM_AUTO to represent MII. */ 1774 m->dc_media = IFM_AUTO; 1775 m->dc_gp_len = l->dc_gpr_len; 1776 1777 p = (u_int8_t *)l; 1778 p += sizeof(struct dc_eblock_mii); 1779 m->dc_gp_ptr = p; 1780 p += 2 * l->dc_gpr_len; 1781 m->dc_reset_len = *p; 1782 p++; 1783 m->dc_reset_ptr = p; 1784 1785 m->dc_next = sc->dc_mi; 1786 sc->dc_mi = m; 1787 } 1788 1789 static void 1790 dc_read_srom(struct dc_softc *sc, int bits) 1791 { 1792 int size; 1793 1794 size = 2 << bits; 1795 sc->dc_srom = malloc(size, M_DEVBUF, M_NOWAIT); 1796 dc_read_eeprom(sc, (caddr_t)sc->dc_srom, 0, (size / 2), 0); 1797 } 1798 1799 static void 1800 dc_parse_21143_srom(struct dc_softc *sc) 1801 { 1802 struct dc_leaf_hdr *lhdr; 1803 struct dc_eblock_hdr *hdr; 1804 int have_mii, i, loff; 1805 char *ptr; 1806 1807 have_mii = 0; 1808 loff = sc->dc_srom[27]; 1809 lhdr = (struct dc_leaf_hdr *)&(sc->dc_srom[loff]); 1810 1811 ptr = (char *)lhdr; 1812 ptr += sizeof(struct dc_leaf_hdr) - 1; 1813 /* 1814 * Look if we got a MII media block. 1815 */ 1816 for (i = 0; i < lhdr->dc_mcnt; i++) { 1817 hdr = (struct dc_eblock_hdr *)ptr; 1818 if (hdr->dc_type == DC_EBLOCK_MII) 1819 have_mii++; 1820 1821 ptr += (hdr->dc_len & 0x7F); 1822 ptr++; 1823 } 1824 1825 /* 1826 * Do the same thing again. Only use SIA and SYM media 1827 * blocks if no MII media block is available. 1828 */ 1829 ptr = (char *)lhdr; 1830 ptr += sizeof(struct dc_leaf_hdr) - 1; 1831 for (i = 0; i < lhdr->dc_mcnt; i++) { 1832 hdr = (struct dc_eblock_hdr *)ptr; 1833 switch (hdr->dc_type) { 1834 case DC_EBLOCK_MII: 1835 dc_decode_leaf_mii(sc, (struct dc_eblock_mii *)hdr); 1836 break; 1837 case DC_EBLOCK_SIA: 1838 if (! have_mii) 1839 dc_decode_leaf_sia(sc, 1840 (struct dc_eblock_sia *)hdr); 1841 break; 1842 case DC_EBLOCK_SYM: 1843 if (! have_mii) 1844 dc_decode_leaf_sym(sc, 1845 (struct dc_eblock_sym *)hdr); 1846 break; 1847 default: 1848 /* Don't care. Yet. */ 1849 break; 1850 } 1851 ptr += (hdr->dc_len & 0x7F); 1852 ptr++; 1853 } 1854 } 1855 1856 static void 1857 dc_dma_map_addr(void *arg, bus_dma_segment_t *segs, int nseg, int error) 1858 { 1859 u_int32_t *paddr; 1860 1861 KASSERT(nseg == 1, ("wrong number of segments, should be 1")); 1862 paddr = arg; 1863 *paddr = segs->ds_addr; 1864 } 1865 1866 /* 1867 * Attach the interface. Allocate softc structures, do ifmedia 1868 * setup and ethernet/BPF attach. 1869 */ 1870 static int 1871 dc_attach(device_t dev) 1872 { 1873 int tmp = 0; 1874 u_char eaddr[ETHER_ADDR_LEN]; 1875 u_int32_t command; 1876 struct dc_softc *sc; 1877 struct ifnet *ifp; 1878 u_int32_t revision; 1879 int unit, error = 0, rid, mac_offset; 1880 int i; 1881 u_int8_t *mac; 1882 1883 sc = device_get_softc(dev); 1884 unit = device_get_unit(dev); 1885 1886 mtx_init(&sc->dc_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 1887 MTX_DEF | MTX_RECURSE); 1888 #ifndef BURN_BRIDGES 1889 /* 1890 * Handle power management nonsense. 1891 */ 1892 dc_acpi(dev); 1893 #endif 1894 /* 1895 * Map control/status registers. 1896 */ 1897 pci_enable_busmaster(dev); 1898 1899 rid = DC_RID; 1900 sc->dc_res = bus_alloc_resource(dev, DC_RES, &rid, 1901 0, ~0, 1, RF_ACTIVE); 1902 1903 if (sc->dc_res == NULL) { 1904 printf("dc%d: couldn't map ports/memory\n", unit); 1905 error = ENXIO; 1906 goto fail; 1907 } 1908 1909 sc->dc_btag = rman_get_bustag(sc->dc_res); 1910 sc->dc_bhandle = rman_get_bushandle(sc->dc_res); 1911 1912 /* Allocate interrupt. */ 1913 rid = 0; 1914 sc->dc_irq = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, 0, ~0, 1, 1915 RF_SHAREABLE | RF_ACTIVE); 1916 1917 if (sc->dc_irq == NULL) { 1918 printf("dc%d: couldn't map interrupt\n", unit); 1919 error = ENXIO; 1920 goto fail; 1921 } 1922 1923 /* Need this info to decide on a chip type. */ 1924 sc->dc_info = dc_devtype(dev); 1925 revision = pci_read_config(dev, DC_PCI_CFRV, 4) & 0x000000FF; 1926 1927 /* Get the eeprom width, but PNIC and XIRCOM have diff eeprom */ 1928 if (sc->dc_info->dc_did != DC_DEVICEID_82C168 && 1929 sc->dc_info->dc_did != DC_DEVICEID_X3201) 1930 dc_eeprom_width(sc); 1931 1932 switch (sc->dc_info->dc_did) { 1933 case DC_DEVICEID_21143: 1934 sc->dc_type = DC_TYPE_21143; 1935 sc->dc_flags |= DC_TX_POLL | DC_TX_USE_TX_INTR; 1936 sc->dc_flags |= DC_REDUCED_MII_POLL; 1937 /* Save EEPROM contents so we can parse them later. */ 1938 dc_read_srom(sc, sc->dc_romwidth); 1939 break; 1940 case DC_DEVICEID_DM9009: 1941 case DC_DEVICEID_DM9100: 1942 case DC_DEVICEID_DM9102: 1943 sc->dc_type = DC_TYPE_DM9102; 1944 sc->dc_flags |= DC_TX_COALESCE | DC_TX_INTR_ALWAYS; 1945 sc->dc_flags |= DC_REDUCED_MII_POLL | DC_TX_STORENFWD; 1946 sc->dc_flags |= DC_TX_ALIGN; 1947 sc->dc_pmode = DC_PMODE_MII; 1948 /* Increase the latency timer value. */ 1949 command = pci_read_config(dev, DC_PCI_CFLT, 4); 1950 command &= 0xFFFF00FF; 1951 command |= 0x00008000; 1952 pci_write_config(dev, DC_PCI_CFLT, command, 4); 1953 break; 1954 case DC_DEVICEID_AL981: 1955 sc->dc_type = DC_TYPE_AL981; 1956 sc->dc_flags |= DC_TX_USE_TX_INTR; 1957 sc->dc_flags |= DC_TX_ADMTEK_WAR; 1958 sc->dc_pmode = DC_PMODE_MII; 1959 dc_read_srom(sc, sc->dc_romwidth); 1960 break; 1961 case DC_DEVICEID_AN985: 1962 case DC_DEVICEID_ADM9511: 1963 case DC_DEVICEID_ADM9513: 1964 case DC_DEVICEID_FA511: 1965 case DC_DEVICEID_FE2500: 1966 case DC_DEVICEID_EN2242: 1967 case DC_DEVICEID_HAWKING_PN672TX: 1968 case DC_DEVICEID_3CSOHOB: 1969 case DC_DEVICEID_MSMN120: 1970 case DC_DEVICEID_MSMN130_FAKE: /* XXX avoid collision with PNIC*/ 1971 sc->dc_type = DC_TYPE_AN985; 1972 sc->dc_flags |= DC_64BIT_HASH; 1973 sc->dc_flags |= DC_TX_USE_TX_INTR; 1974 sc->dc_flags |= DC_TX_ADMTEK_WAR; 1975 sc->dc_pmode = DC_PMODE_MII; 1976 /* Don't read SROM for - auto-loaded on reset */ 1977 break; 1978 case DC_DEVICEID_98713: 1979 case DC_DEVICEID_98713_CP: 1980 if (revision < DC_REVISION_98713A) { 1981 sc->dc_type = DC_TYPE_98713; 1982 } 1983 if (revision >= DC_REVISION_98713A) { 1984 sc->dc_type = DC_TYPE_98713A; 1985 sc->dc_flags |= DC_21143_NWAY; 1986 } 1987 sc->dc_flags |= DC_REDUCED_MII_POLL; 1988 sc->dc_flags |= DC_TX_POLL | DC_TX_USE_TX_INTR; 1989 break; 1990 case DC_DEVICEID_987x5: 1991 case DC_DEVICEID_EN1217: 1992 /* 1993 * Macronix MX98715AEC-C/D/E parts have only a 1994 * 128-bit hash table. We need to deal with these 1995 * in the same manner as the PNIC II so that we 1996 * get the right number of bits out of the 1997 * CRC routine. 1998 */ 1999 if (revision >= DC_REVISION_98715AEC_C && 2000 revision < DC_REVISION_98725) 2001 sc->dc_flags |= DC_128BIT_HASH; 2002 sc->dc_type = DC_TYPE_987x5; 2003 sc->dc_flags |= DC_TX_POLL | DC_TX_USE_TX_INTR; 2004 sc->dc_flags |= DC_REDUCED_MII_POLL | DC_21143_NWAY; 2005 break; 2006 case DC_DEVICEID_98727: 2007 sc->dc_type = DC_TYPE_987x5; 2008 sc->dc_flags |= DC_TX_POLL | DC_TX_USE_TX_INTR; 2009 sc->dc_flags |= DC_REDUCED_MII_POLL | DC_21143_NWAY; 2010 break; 2011 case DC_DEVICEID_82C115: 2012 sc->dc_type = DC_TYPE_PNICII; 2013 sc->dc_flags |= DC_TX_POLL | DC_TX_USE_TX_INTR | DC_128BIT_HASH; 2014 sc->dc_flags |= DC_REDUCED_MII_POLL | DC_21143_NWAY; 2015 break; 2016 case DC_DEVICEID_82C168: 2017 sc->dc_type = DC_TYPE_PNIC; 2018 sc->dc_flags |= DC_TX_STORENFWD | DC_TX_INTR_ALWAYS; 2019 sc->dc_flags |= DC_PNIC_RX_BUG_WAR; 2020 sc->dc_pnic_rx_buf = malloc(DC_RXLEN * 5, M_DEVBUF, M_NOWAIT); 2021 if (revision < DC_REVISION_82C169) 2022 sc->dc_pmode = DC_PMODE_SYM; 2023 break; 2024 case DC_DEVICEID_AX88140A: 2025 sc->dc_type = DC_TYPE_ASIX; 2026 sc->dc_flags |= DC_TX_USE_TX_INTR | DC_TX_INTR_FIRSTFRAG; 2027 sc->dc_flags |= DC_REDUCED_MII_POLL; 2028 sc->dc_pmode = DC_PMODE_MII; 2029 break; 2030 case DC_DEVICEID_X3201: 2031 sc->dc_type = DC_TYPE_XIRCOM; 2032 sc->dc_flags |= DC_TX_INTR_ALWAYS | DC_TX_COALESCE | 2033 DC_TX_ALIGN; 2034 /* 2035 * We don't actually need to coalesce, but we're doing 2036 * it to obtain a double word aligned buffer. 2037 * The DC_TX_COALESCE flag is required. 2038 */ 2039 sc->dc_pmode = DC_PMODE_MII; 2040 break; 2041 case DC_DEVICEID_RS7112: 2042 sc->dc_type = DC_TYPE_CONEXANT; 2043 sc->dc_flags |= DC_TX_INTR_ALWAYS; 2044 sc->dc_flags |= DC_REDUCED_MII_POLL; 2045 sc->dc_pmode = DC_PMODE_MII; 2046 dc_read_srom(sc, sc->dc_romwidth); 2047 break; 2048 default: 2049 printf("dc%d: unknown device: %x\n", sc->dc_unit, 2050 sc->dc_info->dc_did); 2051 break; 2052 } 2053 2054 /* Save the cache line size. */ 2055 if (DC_IS_DAVICOM(sc)) 2056 sc->dc_cachesize = 0; 2057 else 2058 sc->dc_cachesize = pci_read_config(dev, 2059 DC_PCI_CFLT, 4) & 0xFF; 2060 2061 /* Reset the adapter. */ 2062 dc_reset(sc); 2063 2064 /* Take 21143 out of snooze mode */ 2065 if (DC_IS_INTEL(sc) || DC_IS_XIRCOM(sc)) { 2066 command = pci_read_config(dev, DC_PCI_CFDD, 4); 2067 command &= ~(DC_CFDD_SNOOZE_MODE | DC_CFDD_SLEEP_MODE); 2068 pci_write_config(dev, DC_PCI_CFDD, command, 4); 2069 } 2070 2071 /* 2072 * Try to learn something about the supported media. 2073 * We know that ASIX and ADMtek and Davicom devices 2074 * will *always* be using MII media, so that's a no-brainer. 2075 * The tricky ones are the Macronix/PNIC II and the 2076 * Intel 21143. 2077 */ 2078 if (DC_IS_INTEL(sc)) 2079 dc_parse_21143_srom(sc); 2080 else if (DC_IS_MACRONIX(sc) || DC_IS_PNICII(sc)) { 2081 if (sc->dc_type == DC_TYPE_98713) 2082 sc->dc_pmode = DC_PMODE_MII; 2083 else 2084 sc->dc_pmode = DC_PMODE_SYM; 2085 } else if (!sc->dc_pmode) 2086 sc->dc_pmode = DC_PMODE_MII; 2087 2088 /* 2089 * Get station address from the EEPROM. 2090 */ 2091 switch(sc->dc_type) { 2092 case DC_TYPE_98713: 2093 case DC_TYPE_98713A: 2094 case DC_TYPE_987x5: 2095 case DC_TYPE_PNICII: 2096 dc_read_eeprom(sc, (caddr_t)&mac_offset, 2097 (DC_EE_NODEADDR_OFFSET / 2), 1, 0); 2098 dc_read_eeprom(sc, (caddr_t)&eaddr, (mac_offset / 2), 3, 0); 2099 break; 2100 case DC_TYPE_PNIC: 2101 dc_read_eeprom(sc, (caddr_t)&eaddr, 0, 3, 1); 2102 break; 2103 case DC_TYPE_DM9102: 2104 case DC_TYPE_21143: 2105 case DC_TYPE_ASIX: 2106 dc_read_eeprom(sc, (caddr_t)&eaddr, DC_EE_NODEADDR, 3, 0); 2107 break; 2108 case DC_TYPE_AL981: 2109 case DC_TYPE_AN985: 2110 *(u_int32_t *)(&eaddr[0]) = CSR_READ_4(sc, DC_AL_PAR0); 2111 *(u_int16_t *)(&eaddr[4]) = CSR_READ_4(sc, DC_AL_PAR1); 2112 break; 2113 case DC_TYPE_CONEXANT: 2114 bcopy(sc->dc_srom + DC_CONEXANT_EE_NODEADDR, &eaddr, 2115 ETHER_ADDR_LEN); 2116 break; 2117 case DC_TYPE_XIRCOM: 2118 /* The MAC comes from the CIS. */ 2119 mac = pci_get_ether(dev); 2120 if (!mac) { 2121 device_printf(dev, "No station address in CIS!\n"); 2122 error = ENXIO; 2123 goto fail; 2124 } 2125 bcopy(mac, eaddr, ETHER_ADDR_LEN); 2126 break; 2127 default: 2128 dc_read_eeprom(sc, (caddr_t)&eaddr, DC_EE_NODEADDR, 3, 0); 2129 break; 2130 } 2131 2132 /* 2133 * A 21143 or clone chip was detected. Inform the world. 2134 */ 2135 printf("dc%d: Ethernet address: %6D\n", unit, eaddr, ":"); 2136 2137 sc->dc_unit = unit; 2138 bcopy(eaddr, &sc->arpcom.ac_enaddr, ETHER_ADDR_LEN); 2139 2140 /* Allocate a busdma tag and DMA safe memory for TX/RX descriptors. */ 2141 error = bus_dma_tag_create(NULL, PAGE_SIZE, 0, BUS_SPACE_MAXADDR_32BIT, 2142 BUS_SPACE_MAXADDR, NULL, NULL, sizeof(struct dc_list_data), 1, 2143 sizeof(struct dc_list_data), 0, NULL, NULL, &sc->dc_ltag); 2144 if (error) { 2145 printf("dc%d: failed to allocate busdma tag\n", unit); 2146 error = ENXIO; 2147 goto fail; 2148 } 2149 error = bus_dmamem_alloc(sc->dc_ltag, (void **)&sc->dc_ldata, 2150 BUS_DMA_NOWAIT | BUS_DMA_ZERO, &sc->dc_lmap); 2151 if (error) { 2152 printf("dc%d: failed to allocate DMA safe memory\n", unit); 2153 error = ENXIO; 2154 goto fail; 2155 } 2156 error = bus_dmamap_load(sc->dc_ltag, sc->dc_lmap, sc->dc_ldata, 2157 sizeof(struct dc_list_data), dc_dma_map_addr, &sc->dc_laddr, 2158 BUS_DMA_NOWAIT); 2159 if (error) { 2160 printf("dc%d: cannot get address of the descriptors\n", unit); 2161 error = ENXIO; 2162 goto fail; 2163 } 2164 2165 /* 2166 * Allocate a busdma tag and DMA safe memory for the multicast 2167 * setup frame. 2168 */ 2169 error = bus_dma_tag_create(NULL, PAGE_SIZE, 0, BUS_SPACE_MAXADDR_32BIT, 2170 BUS_SPACE_MAXADDR, NULL, NULL, DC_SFRAME_LEN + DC_MIN_FRAMELEN, 1, 2171 DC_SFRAME_LEN + DC_MIN_FRAMELEN, 0, NULL, NULL, &sc->dc_stag); 2172 if (error) { 2173 printf("dc%d: failed to allocate busdma tag\n", unit); 2174 error = ENXIO; 2175 goto fail; 2176 } 2177 error = bus_dmamem_alloc(sc->dc_stag, (void **)&sc->dc_cdata.dc_sbuf, 2178 BUS_DMA_NOWAIT, &sc->dc_smap); 2179 if (error) { 2180 printf("dc%d: failed to allocate DMA safe memory\n", unit); 2181 error = ENXIO; 2182 goto fail; 2183 } 2184 error = bus_dmamap_load(sc->dc_stag, sc->dc_smap, sc->dc_cdata.dc_sbuf, 2185 DC_SFRAME_LEN, dc_dma_map_addr, &sc->dc_saddr, BUS_DMA_NOWAIT); 2186 if (error) { 2187 printf("dc%d: cannot get address of the descriptors\n", unit); 2188 error = ENXIO; 2189 goto fail; 2190 } 2191 2192 /* Allocate a busdma tag for mbufs. */ 2193 error = bus_dma_tag_create(NULL, PAGE_SIZE, 0, BUS_SPACE_MAXADDR_32BIT, 2194 BUS_SPACE_MAXADDR, NULL, NULL, MCLBYTES * DC_TX_LIST_CNT, 2195 DC_TX_LIST_CNT, MCLBYTES, 0, NULL, NULL, &sc->dc_mtag); 2196 if (error) { 2197 printf("dc%d: failed to allocate busdma tag\n", unit); 2198 error = ENXIO; 2199 goto fail; 2200 } 2201 2202 /* Create the TX/RX busdma maps. */ 2203 for (i = 0; i < DC_TX_LIST_CNT; i++) { 2204 error = bus_dmamap_create(sc->dc_mtag, 0, 2205 &sc->dc_cdata.dc_tx_map[i]); 2206 if (error) { 2207 printf("dc%d: failed to init TX ring\n", unit); 2208 error = ENXIO; 2209 goto fail; 2210 } 2211 } 2212 for (i = 0; i < DC_RX_LIST_CNT; i++) { 2213 error = bus_dmamap_create(sc->dc_mtag, 0, 2214 &sc->dc_cdata.dc_rx_map[i]); 2215 if (error) { 2216 printf("dc%d: failed to init RX ring\n", unit); 2217 error = ENXIO; 2218 goto fail; 2219 } 2220 } 2221 error = bus_dmamap_create(sc->dc_mtag, 0, &sc->dc_sparemap); 2222 if (error) { 2223 printf("dc%d: failed to init RX ring\n", unit); 2224 error = ENXIO; 2225 goto fail; 2226 } 2227 2228 ifp = &sc->arpcom.ac_if; 2229 ifp->if_softc = sc; 2230 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 2231 /* XXX: bleah, MTU gets overwritten in ether_ifattach() */ 2232 ifp->if_mtu = ETHERMTU; 2233 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 2234 ifp->if_ioctl = dc_ioctl; 2235 ifp->if_start = dc_start; 2236 ifp->if_watchdog = dc_watchdog; 2237 ifp->if_init = dc_init; 2238 ifp->if_baudrate = 10000000; 2239 ifp->if_snd.ifq_maxlen = DC_TX_LIST_CNT - 1; 2240 2241 /* 2242 * Do MII setup. If this is a 21143, check for a PHY on the 2243 * MII bus after applying any necessary fixups to twiddle the 2244 * GPIO bits. If we don't end up finding a PHY, restore the 2245 * old selection (SIA only or SIA/SYM) and attach the dcphy 2246 * driver instead. 2247 */ 2248 if (DC_IS_INTEL(sc)) { 2249 dc_apply_fixup(sc, IFM_AUTO); 2250 tmp = sc->dc_pmode; 2251 sc->dc_pmode = DC_PMODE_MII; 2252 } 2253 2254 error = mii_phy_probe(dev, &sc->dc_miibus, 2255 dc_ifmedia_upd, dc_ifmedia_sts); 2256 2257 if (error && DC_IS_INTEL(sc)) { 2258 sc->dc_pmode = tmp; 2259 if (sc->dc_pmode != DC_PMODE_SIA) 2260 sc->dc_pmode = DC_PMODE_SYM; 2261 sc->dc_flags |= DC_21143_NWAY; 2262 mii_phy_probe(dev, &sc->dc_miibus, 2263 dc_ifmedia_upd, dc_ifmedia_sts); 2264 /* 2265 * For non-MII cards, we need to have the 21143 2266 * drive the LEDs. Except there are some systems 2267 * like the NEC VersaPro NoteBook PC which have no 2268 * LEDs, and twiddling these bits has adverse effects 2269 * on them. (I.e. you suddenly can't get a link.) 2270 */ 2271 if (pci_read_config(dev, DC_PCI_CSID, 4) != 0x80281033) 2272 sc->dc_flags |= DC_TULIP_LEDS; 2273 error = 0; 2274 } 2275 2276 if (error) { 2277 printf("dc%d: MII without any PHY!\n", sc->dc_unit); 2278 goto fail; 2279 } 2280 2281 if (DC_IS_XIRCOM(sc)) { 2282 /* 2283 * setup General Purpose Port mode and data so the tulip 2284 * can talk to the MII. 2285 */ 2286 CSR_WRITE_4(sc, DC_SIAGP, DC_SIAGP_WRITE_EN | DC_SIAGP_INT1_EN | 2287 DC_SIAGP_MD_GP2_OUTPUT | DC_SIAGP_MD_GP0_OUTPUT); 2288 DELAY(10); 2289 CSR_WRITE_4(sc, DC_SIAGP, DC_SIAGP_INT1_EN | 2290 DC_SIAGP_MD_GP2_OUTPUT | DC_SIAGP_MD_GP0_OUTPUT); 2291 DELAY(10); 2292 } 2293 2294 if (DC_IS_ADMTEK(sc)) { 2295 /* 2296 * Set automatic TX underrun recovery for the ADMtek chips 2297 */ 2298 DC_SETBIT(sc, DC_AL_CR, DC_AL_CR_ATUR); 2299 } 2300 2301 /* 2302 * Tell the upper layer(s) we support long frames. 2303 */ 2304 ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header); 2305 ifp->if_capabilities |= IFCAP_VLAN_MTU; 2306 2307 callout_init(&sc->dc_stat_ch, IS_MPSAFE ? CALLOUT_MPSAFE : 0); 2308 2309 #ifdef SRM_MEDIA 2310 sc->dc_srm_media = 0; 2311 2312 /* Remember the SRM console media setting */ 2313 if (DC_IS_INTEL(sc)) { 2314 command = pci_read_config(dev, DC_PCI_CFDD, 4); 2315 command &= ~(DC_CFDD_SNOOZE_MODE | DC_CFDD_SLEEP_MODE); 2316 switch ((command >> 8) & 0xff) { 2317 case 3: 2318 sc->dc_srm_media = IFM_10_T; 2319 break; 2320 case 4: 2321 sc->dc_srm_media = IFM_10_T | IFM_FDX; 2322 break; 2323 case 5: 2324 sc->dc_srm_media = IFM_100_TX; 2325 break; 2326 case 6: 2327 sc->dc_srm_media = IFM_100_TX | IFM_FDX; 2328 break; 2329 } 2330 if (sc->dc_srm_media) 2331 sc->dc_srm_media |= IFM_ACTIVE | IFM_ETHER; 2332 } 2333 #endif 2334 2335 /* 2336 * Call MI attach routine. 2337 */ 2338 ether_ifattach(ifp, eaddr); 2339 2340 /* Hook interrupt last to avoid having to lock softc */ 2341 error = bus_setup_intr(dev, sc->dc_irq, INTR_TYPE_NET | 2342 (IS_MPSAFE ? INTR_MPSAFE : 0), 2343 dc_intr, sc, &sc->dc_intrhand); 2344 2345 if (error) { 2346 printf("dc%d: couldn't set up irq\n", unit); 2347 ether_ifdetach(ifp); 2348 goto fail; 2349 } 2350 2351 fail: 2352 if (error) 2353 dc_detach(dev); 2354 return (error); 2355 } 2356 2357 /* 2358 * Shutdown hardware and free up resources. This can be called any 2359 * time after the mutex has been initialized. It is called in both 2360 * the error case in attach and the normal detach case so it needs 2361 * to be careful about only freeing resources that have actually been 2362 * allocated. 2363 */ 2364 static int 2365 dc_detach(device_t dev) 2366 { 2367 struct dc_softc *sc; 2368 struct ifnet *ifp; 2369 struct dc_mediainfo *m; 2370 int i; 2371 2372 sc = device_get_softc(dev); 2373 KASSERT(mtx_initialized(&sc->dc_mtx), ("dc mutex not initialized")); 2374 DC_LOCK(sc); 2375 2376 ifp = &sc->arpcom.ac_if; 2377 2378 /* These should only be active if attach succeeded */ 2379 if (device_is_attached(dev)) { 2380 dc_stop(sc); 2381 ether_ifdetach(ifp); 2382 } 2383 if (sc->dc_miibus) 2384 device_delete_child(dev, sc->dc_miibus); 2385 bus_generic_detach(dev); 2386 2387 if (sc->dc_intrhand) 2388 bus_teardown_intr(dev, sc->dc_irq, sc->dc_intrhand); 2389 if (sc->dc_irq) 2390 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->dc_irq); 2391 if (sc->dc_res) 2392 bus_release_resource(dev, DC_RES, DC_RID, sc->dc_res); 2393 2394 if (sc->dc_cdata.dc_sbuf != NULL) 2395 bus_dmamem_free(sc->dc_stag, sc->dc_cdata.dc_sbuf, sc->dc_smap); 2396 if (sc->dc_ldata != NULL) 2397 bus_dmamem_free(sc->dc_ltag, sc->dc_ldata, sc->dc_lmap); 2398 for (i = 0; i < DC_TX_LIST_CNT; i++) 2399 bus_dmamap_destroy(sc->dc_mtag, sc->dc_cdata.dc_tx_map[i]); 2400 for (i = 0; i < DC_RX_LIST_CNT; i++) 2401 bus_dmamap_destroy(sc->dc_mtag, sc->dc_cdata.dc_rx_map[i]); 2402 bus_dmamap_destroy(sc->dc_mtag, sc->dc_sparemap); 2403 if (sc->dc_stag) 2404 bus_dma_tag_destroy(sc->dc_stag); 2405 if (sc->dc_mtag) 2406 bus_dma_tag_destroy(sc->dc_mtag); 2407 if (sc->dc_ltag) 2408 bus_dma_tag_destroy(sc->dc_ltag); 2409 2410 free(sc->dc_pnic_rx_buf, M_DEVBUF); 2411 2412 while (sc->dc_mi != NULL) { 2413 m = sc->dc_mi->dc_next; 2414 free(sc->dc_mi, M_DEVBUF); 2415 sc->dc_mi = m; 2416 } 2417 free(sc->dc_srom, M_DEVBUF); 2418 2419 DC_UNLOCK(sc); 2420 mtx_destroy(&sc->dc_mtx); 2421 2422 return (0); 2423 } 2424 2425 /* 2426 * Initialize the transmit descriptors. 2427 */ 2428 static int 2429 dc_list_tx_init(struct dc_softc *sc) 2430 { 2431 struct dc_chain_data *cd; 2432 struct dc_list_data *ld; 2433 int i, nexti; 2434 2435 cd = &sc->dc_cdata; 2436 ld = sc->dc_ldata; 2437 for (i = 0; i < DC_TX_LIST_CNT; i++) { 2438 if (i == DC_TX_LIST_CNT - 1) 2439 nexti = 0; 2440 else 2441 nexti = i + 1; 2442 ld->dc_tx_list[i].dc_next = htole32(DC_TXDESC(sc, nexti)); 2443 cd->dc_tx_chain[i] = NULL; 2444 ld->dc_tx_list[i].dc_data = 0; 2445 ld->dc_tx_list[i].dc_ctl = 0; 2446 } 2447 2448 cd->dc_tx_prod = cd->dc_tx_cons = cd->dc_tx_cnt = 0; 2449 bus_dmamap_sync(sc->dc_ltag, sc->dc_lmap, 2450 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2451 return (0); 2452 } 2453 2454 2455 /* 2456 * Initialize the RX descriptors and allocate mbufs for them. Note that 2457 * we arrange the descriptors in a closed ring, so that the last descriptor 2458 * points back to the first. 2459 */ 2460 static int 2461 dc_list_rx_init(struct dc_softc *sc) 2462 { 2463 struct dc_chain_data *cd; 2464 struct dc_list_data *ld; 2465 int i, nexti; 2466 2467 cd = &sc->dc_cdata; 2468 ld = sc->dc_ldata; 2469 2470 for (i = 0; i < DC_RX_LIST_CNT; i++) { 2471 if (dc_newbuf(sc, i, 1) != 0) 2472 return (ENOBUFS); 2473 if (i == DC_RX_LIST_CNT - 1) 2474 nexti = 0; 2475 else 2476 nexti = i + 1; 2477 ld->dc_rx_list[i].dc_next = htole32(DC_RXDESC(sc, nexti)); 2478 } 2479 2480 cd->dc_rx_prod = 0; 2481 bus_dmamap_sync(sc->dc_ltag, sc->dc_lmap, 2482 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2483 return (0); 2484 } 2485 2486 static void 2487 dc_dma_map_rxbuf(arg, segs, nseg, mapsize, error) 2488 void *arg; 2489 bus_dma_segment_t *segs; 2490 int nseg; 2491 bus_size_t mapsize; 2492 int error; 2493 { 2494 struct dc_softc *sc; 2495 struct dc_desc *c; 2496 2497 sc = arg; 2498 c = &sc->dc_ldata->dc_rx_list[sc->dc_cdata.dc_rx_cur]; 2499 if (error) { 2500 sc->dc_cdata.dc_rx_err = error; 2501 return; 2502 } 2503 2504 KASSERT(nseg == 1, ("wrong number of segments, should be 1")); 2505 sc->dc_cdata.dc_rx_err = 0; 2506 c->dc_data = htole32(segs->ds_addr); 2507 } 2508 2509 /* 2510 * Initialize an RX descriptor and attach an MBUF cluster. 2511 */ 2512 static int 2513 dc_newbuf(struct dc_softc *sc, int i, int alloc) 2514 { 2515 struct mbuf *m_new; 2516 bus_dmamap_t tmp; 2517 int error; 2518 2519 if (alloc) { 2520 m_new = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR); 2521 if (m_new == NULL) 2522 return (ENOBUFS); 2523 } else { 2524 m_new = sc->dc_cdata.dc_rx_chain[i]; 2525 m_new->m_data = m_new->m_ext.ext_buf; 2526 } 2527 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 2528 m_adj(m_new, sizeof(u_int64_t)); 2529 2530 /* 2531 * If this is a PNIC chip, zero the buffer. This is part 2532 * of the workaround for the receive bug in the 82c168 and 2533 * 82c169 chips. 2534 */ 2535 if (sc->dc_flags & DC_PNIC_RX_BUG_WAR) 2536 bzero(mtod(m_new, char *), m_new->m_len); 2537 2538 /* No need to remap the mbuf if we're reusing it. */ 2539 if (alloc) { 2540 sc->dc_cdata.dc_rx_cur = i; 2541 error = bus_dmamap_load_mbuf(sc->dc_mtag, sc->dc_sparemap, 2542 m_new, dc_dma_map_rxbuf, sc, 0); 2543 if (error) { 2544 m_freem(m_new); 2545 return (error); 2546 } 2547 if (sc->dc_cdata.dc_rx_err != 0) { 2548 m_freem(m_new); 2549 return (sc->dc_cdata.dc_rx_err); 2550 } 2551 bus_dmamap_unload(sc->dc_mtag, sc->dc_cdata.dc_rx_map[i]); 2552 tmp = sc->dc_cdata.dc_rx_map[i]; 2553 sc->dc_cdata.dc_rx_map[i] = sc->dc_sparemap; 2554 sc->dc_sparemap = tmp; 2555 sc->dc_cdata.dc_rx_chain[i] = m_new; 2556 } 2557 2558 sc->dc_ldata->dc_rx_list[i].dc_ctl = htole32(DC_RXCTL_RLINK | DC_RXLEN); 2559 sc->dc_ldata->dc_rx_list[i].dc_status = htole32(DC_RXSTAT_OWN); 2560 bus_dmamap_sync(sc->dc_mtag, sc->dc_cdata.dc_rx_map[i], 2561 BUS_DMASYNC_PREREAD); 2562 bus_dmamap_sync(sc->dc_ltag, sc->dc_lmap, 2563 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2564 return (0); 2565 } 2566 2567 /* 2568 * Grrrrr. 2569 * The PNIC chip has a terrible bug in it that manifests itself during 2570 * periods of heavy activity. The exact mode of failure if difficult to 2571 * pinpoint: sometimes it only happens in promiscuous mode, sometimes it 2572 * will happen on slow machines. The bug is that sometimes instead of 2573 * uploading one complete frame during reception, it uploads what looks 2574 * like the entire contents of its FIFO memory. The frame we want is at 2575 * the end of the whole mess, but we never know exactly how much data has 2576 * been uploaded, so salvaging the frame is hard. 2577 * 2578 * There is only one way to do it reliably, and it's disgusting. 2579 * Here's what we know: 2580 * 2581 * - We know there will always be somewhere between one and three extra 2582 * descriptors uploaded. 2583 * 2584 * - We know the desired received frame will always be at the end of the 2585 * total data upload. 2586 * 2587 * - We know the size of the desired received frame because it will be 2588 * provided in the length field of the status word in the last descriptor. 2589 * 2590 * Here's what we do: 2591 * 2592 * - When we allocate buffers for the receive ring, we bzero() them. 2593 * This means that we know that the buffer contents should be all 2594 * zeros, except for data uploaded by the chip. 2595 * 2596 * - We also force the PNIC chip to upload frames that include the 2597 * ethernet CRC at the end. 2598 * 2599 * - We gather all of the bogus frame data into a single buffer. 2600 * 2601 * - We then position a pointer at the end of this buffer and scan 2602 * backwards until we encounter the first non-zero byte of data. 2603 * This is the end of the received frame. We know we will encounter 2604 * some data at the end of the frame because the CRC will always be 2605 * there, so even if the sender transmits a packet of all zeros, 2606 * we won't be fooled. 2607 * 2608 * - We know the size of the actual received frame, so we subtract 2609 * that value from the current pointer location. This brings us 2610 * to the start of the actual received packet. 2611 * 2612 * - We copy this into an mbuf and pass it on, along with the actual 2613 * frame length. 2614 * 2615 * The performance hit is tremendous, but it beats dropping frames all 2616 * the time. 2617 */ 2618 2619 #define DC_WHOLEFRAME (DC_RXSTAT_FIRSTFRAG | DC_RXSTAT_LASTFRAG) 2620 static void 2621 dc_pnic_rx_bug_war(struct dc_softc *sc, int idx) 2622 { 2623 struct dc_desc *cur_rx; 2624 struct dc_desc *c = NULL; 2625 struct mbuf *m = NULL; 2626 unsigned char *ptr; 2627 int i, total_len; 2628 u_int32_t rxstat = 0; 2629 2630 i = sc->dc_pnic_rx_bug_save; 2631 cur_rx = &sc->dc_ldata->dc_rx_list[idx]; 2632 ptr = sc->dc_pnic_rx_buf; 2633 bzero(ptr, DC_RXLEN * 5); 2634 2635 /* Copy all the bytes from the bogus buffers. */ 2636 while (1) { 2637 c = &sc->dc_ldata->dc_rx_list[i]; 2638 rxstat = le32toh(c->dc_status); 2639 m = sc->dc_cdata.dc_rx_chain[i]; 2640 bcopy(mtod(m, char *), ptr, DC_RXLEN); 2641 ptr += DC_RXLEN; 2642 /* If this is the last buffer, break out. */ 2643 if (i == idx || rxstat & DC_RXSTAT_LASTFRAG) 2644 break; 2645 dc_newbuf(sc, i, 0); 2646 DC_INC(i, DC_RX_LIST_CNT); 2647 } 2648 2649 /* Find the length of the actual receive frame. */ 2650 total_len = DC_RXBYTES(rxstat); 2651 2652 /* Scan backwards until we hit a non-zero byte. */ 2653 while (*ptr == 0x00) 2654 ptr--; 2655 2656 /* Round off. */ 2657 if ((uintptr_t)(ptr) & 0x3) 2658 ptr -= 1; 2659 2660 /* Now find the start of the frame. */ 2661 ptr -= total_len; 2662 if (ptr < sc->dc_pnic_rx_buf) 2663 ptr = sc->dc_pnic_rx_buf; 2664 2665 /* 2666 * Now copy the salvaged frame to the last mbuf and fake up 2667 * the status word to make it look like a successful 2668 * frame reception. 2669 */ 2670 dc_newbuf(sc, i, 0); 2671 bcopy(ptr, mtod(m, char *), total_len); 2672 cur_rx->dc_status = htole32(rxstat | DC_RXSTAT_FIRSTFRAG); 2673 } 2674 2675 /* 2676 * This routine searches the RX ring for dirty descriptors in the 2677 * event that the rxeof routine falls out of sync with the chip's 2678 * current descriptor pointer. This may happen sometimes as a result 2679 * of a "no RX buffer available" condition that happens when the chip 2680 * consumes all of the RX buffers before the driver has a chance to 2681 * process the RX ring. This routine may need to be called more than 2682 * once to bring the driver back in sync with the chip, however we 2683 * should still be getting RX DONE interrupts to drive the search 2684 * for new packets in the RX ring, so we should catch up eventually. 2685 */ 2686 static int 2687 dc_rx_resync(struct dc_softc *sc) 2688 { 2689 struct dc_desc *cur_rx; 2690 int i, pos; 2691 2692 pos = sc->dc_cdata.dc_rx_prod; 2693 2694 for (i = 0; i < DC_RX_LIST_CNT; i++) { 2695 cur_rx = &sc->dc_ldata->dc_rx_list[pos]; 2696 if (!(le32toh(cur_rx->dc_status) & DC_RXSTAT_OWN)) 2697 break; 2698 DC_INC(pos, DC_RX_LIST_CNT); 2699 } 2700 2701 /* If the ring really is empty, then just return. */ 2702 if (i == DC_RX_LIST_CNT) 2703 return (0); 2704 2705 /* We've fallen behing the chip: catch it. */ 2706 sc->dc_cdata.dc_rx_prod = pos; 2707 2708 return (EAGAIN); 2709 } 2710 2711 /* 2712 * A frame has been uploaded: pass the resulting mbuf chain up to 2713 * the higher level protocols. 2714 */ 2715 static void 2716 dc_rxeof(struct dc_softc *sc) 2717 { 2718 struct mbuf *m; 2719 struct ifnet *ifp; 2720 struct dc_desc *cur_rx; 2721 int i, total_len = 0; 2722 u_int32_t rxstat; 2723 2724 ifp = &sc->arpcom.ac_if; 2725 i = sc->dc_cdata.dc_rx_prod; 2726 2727 bus_dmamap_sync(sc->dc_ltag, sc->dc_lmap, BUS_DMASYNC_POSTREAD); 2728 while (!(le32toh(sc->dc_ldata->dc_rx_list[i].dc_status) & 2729 DC_RXSTAT_OWN)) { 2730 #ifdef DEVICE_POLLING 2731 if (ifp->if_flags & IFF_POLLING) { 2732 if (sc->rxcycles <= 0) 2733 break; 2734 sc->rxcycles--; 2735 } 2736 #endif 2737 cur_rx = &sc->dc_ldata->dc_rx_list[i]; 2738 rxstat = le32toh(cur_rx->dc_status); 2739 m = sc->dc_cdata.dc_rx_chain[i]; 2740 bus_dmamap_sync(sc->dc_mtag, sc->dc_cdata.dc_rx_map[i], 2741 BUS_DMASYNC_POSTREAD); 2742 total_len = DC_RXBYTES(rxstat); 2743 2744 if (sc->dc_flags & DC_PNIC_RX_BUG_WAR) { 2745 if ((rxstat & DC_WHOLEFRAME) != DC_WHOLEFRAME) { 2746 if (rxstat & DC_RXSTAT_FIRSTFRAG) 2747 sc->dc_pnic_rx_bug_save = i; 2748 if ((rxstat & DC_RXSTAT_LASTFRAG) == 0) { 2749 DC_INC(i, DC_RX_LIST_CNT); 2750 continue; 2751 } 2752 dc_pnic_rx_bug_war(sc, i); 2753 rxstat = le32toh(cur_rx->dc_status); 2754 total_len = DC_RXBYTES(rxstat); 2755 } 2756 } 2757 2758 /* 2759 * If an error occurs, update stats, clear the 2760 * status word and leave the mbuf cluster in place: 2761 * it should simply get re-used next time this descriptor 2762 * comes up in the ring. However, don't report long 2763 * frames as errors since they could be vlans. 2764 */ 2765 if ((rxstat & DC_RXSTAT_RXERR)) { 2766 if (!(rxstat & DC_RXSTAT_GIANT) || 2767 (rxstat & (DC_RXSTAT_CRCERR | DC_RXSTAT_DRIBBLE | 2768 DC_RXSTAT_MIIERE | DC_RXSTAT_COLLSEEN | 2769 DC_RXSTAT_RUNT | DC_RXSTAT_DE))) { 2770 ifp->if_ierrors++; 2771 if (rxstat & DC_RXSTAT_COLLSEEN) 2772 ifp->if_collisions++; 2773 dc_newbuf(sc, i, 0); 2774 if (rxstat & DC_RXSTAT_CRCERR) { 2775 DC_INC(i, DC_RX_LIST_CNT); 2776 continue; 2777 } else { 2778 dc_init(sc); 2779 return; 2780 } 2781 } 2782 } 2783 2784 /* No errors; receive the packet. */ 2785 total_len -= ETHER_CRC_LEN; 2786 #ifdef __i386__ 2787 /* 2788 * On the x86 we do not have alignment problems, so try to 2789 * allocate a new buffer for the receive ring, and pass up 2790 * the one where the packet is already, saving the expensive 2791 * copy done in m_devget(). 2792 * If we are on an architecture with alignment problems, or 2793 * if the allocation fails, then use m_devget and leave the 2794 * existing buffer in the receive ring. 2795 */ 2796 if (dc_quick && dc_newbuf(sc, i, 1) == 0) { 2797 m->m_pkthdr.rcvif = ifp; 2798 m->m_pkthdr.len = m->m_len = total_len; 2799 DC_INC(i, DC_RX_LIST_CNT); 2800 } else 2801 #endif 2802 { 2803 struct mbuf *m0; 2804 2805 m0 = m_devget(mtod(m, char *), total_len, 2806 ETHER_ALIGN, ifp, NULL); 2807 dc_newbuf(sc, i, 0); 2808 DC_INC(i, DC_RX_LIST_CNT); 2809 if (m0 == NULL) { 2810 ifp->if_ierrors++; 2811 continue; 2812 } 2813 m = m0; 2814 } 2815 2816 ifp->if_ipackets++; 2817 (*ifp->if_input)(ifp, m); 2818 } 2819 2820 sc->dc_cdata.dc_rx_prod = i; 2821 } 2822 2823 /* 2824 * A frame was downloaded to the chip. It's safe for us to clean up 2825 * the list buffers. 2826 */ 2827 2828 static void 2829 dc_txeof(struct dc_softc *sc) 2830 { 2831 struct dc_desc *cur_tx = NULL; 2832 struct ifnet *ifp; 2833 int idx; 2834 u_int32_t ctl, txstat; 2835 2836 ifp = &sc->arpcom.ac_if; 2837 2838 /* 2839 * Go through our tx list and free mbufs for those 2840 * frames that have been transmitted. 2841 */ 2842 bus_dmamap_sync(sc->dc_ltag, sc->dc_lmap, BUS_DMASYNC_POSTREAD); 2843 idx = sc->dc_cdata.dc_tx_cons; 2844 while (idx != sc->dc_cdata.dc_tx_prod) { 2845 2846 cur_tx = &sc->dc_ldata->dc_tx_list[idx]; 2847 txstat = le32toh(cur_tx->dc_status); 2848 ctl = le32toh(cur_tx->dc_ctl); 2849 2850 if (txstat & DC_TXSTAT_OWN) 2851 break; 2852 2853 if (!(ctl & DC_TXCTL_FIRSTFRAG) || ctl & DC_TXCTL_SETUP) { 2854 if (ctl & DC_TXCTL_SETUP) { 2855 /* 2856 * Yes, the PNIC is so brain damaged 2857 * that it will sometimes generate a TX 2858 * underrun error while DMAing the RX 2859 * filter setup frame. If we detect this, 2860 * we have to send the setup frame again, 2861 * or else the filter won't be programmed 2862 * correctly. 2863 */ 2864 if (DC_IS_PNIC(sc)) { 2865 if (txstat & DC_TXSTAT_ERRSUM) 2866 dc_setfilt(sc); 2867 } 2868 sc->dc_cdata.dc_tx_chain[idx] = NULL; 2869 } 2870 sc->dc_cdata.dc_tx_cnt--; 2871 DC_INC(idx, DC_TX_LIST_CNT); 2872 continue; 2873 } 2874 2875 if (DC_IS_XIRCOM(sc) || DC_IS_CONEXANT(sc)) { 2876 /* 2877 * XXX: Why does my Xircom taunt me so? 2878 * For some reason it likes setting the CARRLOST flag 2879 * even when the carrier is there. wtf?!? 2880 * Who knows, but Conexant chips have the 2881 * same problem. Maybe they took lessons 2882 * from Xircom. 2883 */ 2884 if (/*sc->dc_type == DC_TYPE_21143 &&*/ 2885 sc->dc_pmode == DC_PMODE_MII && 2886 ((txstat & 0xFFFF) & ~(DC_TXSTAT_ERRSUM | 2887 DC_TXSTAT_NOCARRIER))) 2888 txstat &= ~DC_TXSTAT_ERRSUM; 2889 } else { 2890 if (/*sc->dc_type == DC_TYPE_21143 &&*/ 2891 sc->dc_pmode == DC_PMODE_MII && 2892 ((txstat & 0xFFFF) & ~(DC_TXSTAT_ERRSUM | 2893 DC_TXSTAT_NOCARRIER | DC_TXSTAT_CARRLOST))) 2894 txstat &= ~DC_TXSTAT_ERRSUM; 2895 } 2896 2897 if (txstat & DC_TXSTAT_ERRSUM) { 2898 ifp->if_oerrors++; 2899 if (txstat & DC_TXSTAT_EXCESSCOLL) 2900 ifp->if_collisions++; 2901 if (txstat & DC_TXSTAT_LATECOLL) 2902 ifp->if_collisions++; 2903 if (!(txstat & DC_TXSTAT_UNDERRUN)) { 2904 dc_init(sc); 2905 return; 2906 } 2907 } 2908 2909 ifp->if_collisions += (txstat & DC_TXSTAT_COLLCNT) >> 3; 2910 2911 ifp->if_opackets++; 2912 if (sc->dc_cdata.dc_tx_chain[idx] != NULL) { 2913 bus_dmamap_sync(sc->dc_mtag, 2914 sc->dc_cdata.dc_tx_map[idx], 2915 BUS_DMASYNC_POSTWRITE); 2916 bus_dmamap_unload(sc->dc_mtag, 2917 sc->dc_cdata.dc_tx_map[idx]); 2918 m_freem(sc->dc_cdata.dc_tx_chain[idx]); 2919 sc->dc_cdata.dc_tx_chain[idx] = NULL; 2920 } 2921 2922 sc->dc_cdata.dc_tx_cnt--; 2923 DC_INC(idx, DC_TX_LIST_CNT); 2924 } 2925 2926 if (idx != sc->dc_cdata.dc_tx_cons) { 2927 /* Some buffers have been freed. */ 2928 sc->dc_cdata.dc_tx_cons = idx; 2929 ifp->if_flags &= ~IFF_OACTIVE; 2930 } 2931 ifp->if_timer = (sc->dc_cdata.dc_tx_cnt == 0) ? 0 : 5; 2932 } 2933 2934 static void 2935 dc_tick(void *xsc) 2936 { 2937 struct dc_softc *sc; 2938 struct mii_data *mii; 2939 struct ifnet *ifp; 2940 u_int32_t r; 2941 2942 sc = xsc; 2943 DC_LOCK(sc); 2944 ifp = &sc->arpcom.ac_if; 2945 mii = device_get_softc(sc->dc_miibus); 2946 2947 if (sc->dc_flags & DC_REDUCED_MII_POLL) { 2948 if (sc->dc_flags & DC_21143_NWAY) { 2949 r = CSR_READ_4(sc, DC_10BTSTAT); 2950 if (IFM_SUBTYPE(mii->mii_media_active) == 2951 IFM_100_TX && (r & DC_TSTAT_LS100)) { 2952 sc->dc_link = 0; 2953 mii_mediachg(mii); 2954 } 2955 if (IFM_SUBTYPE(mii->mii_media_active) == 2956 IFM_10_T && (r & DC_TSTAT_LS10)) { 2957 sc->dc_link = 0; 2958 mii_mediachg(mii); 2959 } 2960 if (sc->dc_link == 0) 2961 mii_tick(mii); 2962 } else { 2963 r = CSR_READ_4(sc, DC_ISR); 2964 if ((r & DC_ISR_RX_STATE) == DC_RXSTATE_WAIT && 2965 sc->dc_cdata.dc_tx_cnt == 0) { 2966 mii_tick(mii); 2967 if (!(mii->mii_media_status & IFM_ACTIVE)) 2968 sc->dc_link = 0; 2969 } 2970 } 2971 } else 2972 mii_tick(mii); 2973 2974 /* 2975 * When the init routine completes, we expect to be able to send 2976 * packets right away, and in fact the network code will send a 2977 * gratuitous ARP the moment the init routine marks the interface 2978 * as running. However, even though the MAC may have been initialized, 2979 * there may be a delay of a few seconds before the PHY completes 2980 * autonegotiation and the link is brought up. Any transmissions 2981 * made during that delay will be lost. Dealing with this is tricky: 2982 * we can't just pause in the init routine while waiting for the 2983 * PHY to come ready since that would bring the whole system to 2984 * a screeching halt for several seconds. 2985 * 2986 * What we do here is prevent the TX start routine from sending 2987 * any packets until a link has been established. After the 2988 * interface has been initialized, the tick routine will poll 2989 * the state of the PHY until the IFM_ACTIVE flag is set. Until 2990 * that time, packets will stay in the send queue, and once the 2991 * link comes up, they will be flushed out to the wire. 2992 */ 2993 if (!sc->dc_link && mii->mii_media_status & IFM_ACTIVE && 2994 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) { 2995 sc->dc_link++; 2996 if (ifp->if_snd.ifq_head != NULL) 2997 dc_start(ifp); 2998 } 2999 3000 if (sc->dc_flags & DC_21143_NWAY && !sc->dc_link) 3001 callout_reset(&sc->dc_stat_ch, hz/10, dc_tick, sc); 3002 else 3003 callout_reset(&sc->dc_stat_ch, hz, dc_tick, sc); 3004 3005 DC_UNLOCK(sc); 3006 } 3007 3008 /* 3009 * A transmit underrun has occurred. Back off the transmit threshold, 3010 * or switch to store and forward mode if we have to. 3011 */ 3012 static void 3013 dc_tx_underrun(struct dc_softc *sc) 3014 { 3015 u_int32_t isr; 3016 int i; 3017 3018 if (DC_IS_DAVICOM(sc)) 3019 dc_init(sc); 3020 3021 if (DC_IS_INTEL(sc)) { 3022 /* 3023 * The real 21143 requires that the transmitter be idle 3024 * in order to change the transmit threshold or store 3025 * and forward state. 3026 */ 3027 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_TX_ON); 3028 3029 for (i = 0; i < DC_TIMEOUT; i++) { 3030 isr = CSR_READ_4(sc, DC_ISR); 3031 if (isr & DC_ISR_TX_IDLE) 3032 break; 3033 DELAY(10); 3034 } 3035 if (i == DC_TIMEOUT) { 3036 printf("dc%d: failed to force tx to idle state\n", 3037 sc->dc_unit); 3038 dc_init(sc); 3039 } 3040 } 3041 3042 printf("dc%d: TX underrun -- ", sc->dc_unit); 3043 sc->dc_txthresh += DC_TXTHRESH_INC; 3044 if (sc->dc_txthresh > DC_TXTHRESH_MAX) { 3045 printf("using store and forward mode\n"); 3046 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_STORENFWD); 3047 } else { 3048 printf("increasing TX threshold\n"); 3049 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_TX_THRESH); 3050 DC_SETBIT(sc, DC_NETCFG, sc->dc_txthresh); 3051 } 3052 3053 if (DC_IS_INTEL(sc)) 3054 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_TX_ON); 3055 } 3056 3057 #ifdef DEVICE_POLLING 3058 static poll_handler_t dc_poll; 3059 3060 static void 3061 dc_poll(struct ifnet *ifp, enum poll_cmd cmd, int count) 3062 { 3063 struct dc_softc *sc = ifp->if_softc; 3064 3065 if (cmd == POLL_DEREGISTER) { /* final call, enable interrupts */ 3066 /* Re-enable interrupts. */ 3067 CSR_WRITE_4(sc, DC_IMR, DC_INTRS); 3068 return; 3069 } 3070 sc->rxcycles = count; 3071 dc_rxeof(sc); 3072 dc_txeof(sc); 3073 if (ifp->if_snd.ifq_head != NULL && !(ifp->if_flags & IFF_OACTIVE)) 3074 dc_start(ifp); 3075 3076 if (cmd == POLL_AND_CHECK_STATUS) { /* also check status register */ 3077 u_int32_t status; 3078 3079 status = CSR_READ_4(sc, DC_ISR); 3080 status &= (DC_ISR_RX_WATDOGTIMEO | DC_ISR_RX_NOBUF | 3081 DC_ISR_TX_NOBUF | DC_ISR_TX_IDLE | DC_ISR_TX_UNDERRUN | 3082 DC_ISR_BUS_ERR); 3083 if (!status) 3084 return; 3085 /* ack what we have */ 3086 CSR_WRITE_4(sc, DC_ISR, status); 3087 3088 if (status & (DC_ISR_RX_WATDOGTIMEO | DC_ISR_RX_NOBUF)) { 3089 u_int32_t r = CSR_READ_4(sc, DC_FRAMESDISCARDED); 3090 ifp->if_ierrors += (r & 0xffff) + ((r >> 17) & 0x7ff); 3091 3092 if (dc_rx_resync(sc)) 3093 dc_rxeof(sc); 3094 } 3095 /* restart transmit unit if necessary */ 3096 if (status & DC_ISR_TX_IDLE && sc->dc_cdata.dc_tx_cnt) 3097 CSR_WRITE_4(sc, DC_TXSTART, 0xFFFFFFFF); 3098 3099 if (status & DC_ISR_TX_UNDERRUN) 3100 dc_tx_underrun(sc); 3101 3102 if (status & DC_ISR_BUS_ERR) { 3103 printf("dc_poll: dc%d bus error\n", sc->dc_unit); 3104 dc_reset(sc); 3105 dc_init(sc); 3106 } 3107 } 3108 } 3109 #endif /* DEVICE_POLLING */ 3110 3111 static void 3112 dc_intr(void *arg) 3113 { 3114 struct dc_softc *sc; 3115 struct ifnet *ifp; 3116 u_int32_t status; 3117 3118 sc = arg; 3119 3120 if (sc->suspended) 3121 return; 3122 3123 if ((CSR_READ_4(sc, DC_ISR) & DC_INTRS) == 0) 3124 return; 3125 3126 DC_LOCK(sc); 3127 ifp = &sc->arpcom.ac_if; 3128 #ifdef DEVICE_POLLING 3129 if (ifp->if_flags & IFF_POLLING) 3130 goto done; 3131 if (ether_poll_register(dc_poll, ifp)) { /* ok, disable interrupts */ 3132 CSR_WRITE_4(sc, DC_IMR, 0x00000000); 3133 goto done; 3134 } 3135 #endif 3136 3137 /* Suppress unwanted interrupts */ 3138 if (!(ifp->if_flags & IFF_UP)) { 3139 if (CSR_READ_4(sc, DC_ISR) & DC_INTRS) 3140 dc_stop(sc); 3141 DC_UNLOCK(sc); 3142 return; 3143 } 3144 3145 /* Disable interrupts. */ 3146 CSR_WRITE_4(sc, DC_IMR, 0x00000000); 3147 3148 while (((status = CSR_READ_4(sc, DC_ISR)) & DC_INTRS) 3149 && status != 0xFFFFFFFF) { 3150 3151 CSR_WRITE_4(sc, DC_ISR, status); 3152 3153 if (status & DC_ISR_RX_OK) { 3154 int curpkts; 3155 curpkts = ifp->if_ipackets; 3156 dc_rxeof(sc); 3157 if (curpkts == ifp->if_ipackets) { 3158 while (dc_rx_resync(sc)) 3159 dc_rxeof(sc); 3160 } 3161 } 3162 3163 if (status & (DC_ISR_TX_OK | DC_ISR_TX_NOBUF)) 3164 dc_txeof(sc); 3165 3166 if (status & DC_ISR_TX_IDLE) { 3167 dc_txeof(sc); 3168 if (sc->dc_cdata.dc_tx_cnt) { 3169 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_TX_ON); 3170 CSR_WRITE_4(sc, DC_TXSTART, 0xFFFFFFFF); 3171 } 3172 } 3173 3174 if (status & DC_ISR_TX_UNDERRUN) 3175 dc_tx_underrun(sc); 3176 3177 if ((status & DC_ISR_RX_WATDOGTIMEO) 3178 || (status & DC_ISR_RX_NOBUF)) { 3179 int curpkts; 3180 curpkts = ifp->if_ipackets; 3181 dc_rxeof(sc); 3182 if (curpkts == ifp->if_ipackets) { 3183 while (dc_rx_resync(sc)) 3184 dc_rxeof(sc); 3185 } 3186 } 3187 3188 if (status & DC_ISR_BUS_ERR) { 3189 dc_reset(sc); 3190 dc_init(sc); 3191 } 3192 } 3193 3194 /* Re-enable interrupts. */ 3195 CSR_WRITE_4(sc, DC_IMR, DC_INTRS); 3196 3197 if (ifp->if_snd.ifq_head != NULL) 3198 dc_start(ifp); 3199 3200 #ifdef DEVICE_POLLING 3201 done: 3202 #endif 3203 3204 DC_UNLOCK(sc); 3205 } 3206 3207 static void 3208 dc_dma_map_txbuf(arg, segs, nseg, mapsize, error) 3209 void *arg; 3210 bus_dma_segment_t *segs; 3211 int nseg; 3212 bus_size_t mapsize; 3213 int error; 3214 { 3215 struct dc_softc *sc; 3216 struct dc_desc *f; 3217 int cur, first, frag, i; 3218 3219 sc = arg; 3220 if (error) { 3221 sc->dc_cdata.dc_tx_err = error; 3222 return; 3223 } 3224 3225 first = cur = frag = sc->dc_cdata.dc_tx_prod; 3226 for (i = 0; i < nseg; i++) { 3227 if ((sc->dc_flags & DC_TX_ADMTEK_WAR) && 3228 (frag == (DC_TX_LIST_CNT - 1)) && 3229 (first != sc->dc_cdata.dc_tx_first)) { 3230 bus_dmamap_unload(sc->dc_mtag, 3231 sc->dc_cdata.dc_tx_map[first]); 3232 sc->dc_cdata.dc_tx_err = ENOBUFS; 3233 return; 3234 } 3235 3236 f = &sc->dc_ldata->dc_tx_list[frag]; 3237 f->dc_ctl = htole32(DC_TXCTL_TLINK | segs[i].ds_len); 3238 if (i == 0) { 3239 f->dc_status = 0; 3240 f->dc_ctl |= htole32(DC_TXCTL_FIRSTFRAG); 3241 } else 3242 f->dc_status = htole32(DC_TXSTAT_OWN); 3243 f->dc_data = htole32(segs[i].ds_addr); 3244 cur = frag; 3245 DC_INC(frag, DC_TX_LIST_CNT); 3246 } 3247 3248 sc->dc_cdata.dc_tx_err = 0; 3249 sc->dc_cdata.dc_tx_prod = frag; 3250 sc->dc_cdata.dc_tx_cnt += nseg; 3251 sc->dc_ldata->dc_tx_list[cur].dc_ctl |= htole32(DC_TXCTL_LASTFRAG); 3252 if (sc->dc_flags & DC_TX_INTR_FIRSTFRAG) 3253 sc->dc_ldata->dc_tx_list[first].dc_ctl |= 3254 htole32(DC_TXCTL_FINT); 3255 if (sc->dc_flags & DC_TX_INTR_ALWAYS) 3256 sc->dc_ldata->dc_tx_list[cur].dc_ctl |= htole32(DC_TXCTL_FINT); 3257 if (sc->dc_flags & DC_TX_USE_TX_INTR && sc->dc_cdata.dc_tx_cnt > 64) 3258 sc->dc_ldata->dc_tx_list[cur].dc_ctl |= htole32(DC_TXCTL_FINT); 3259 sc->dc_ldata->dc_tx_list[first].dc_status = htole32(DC_TXSTAT_OWN); 3260 } 3261 3262 /* 3263 * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data 3264 * pointers to the fragment pointers. 3265 */ 3266 static int 3267 dc_encap(struct dc_softc *sc, struct mbuf **m_head) 3268 { 3269 struct mbuf *m; 3270 int error, idx, chainlen = 0; 3271 3272 /* 3273 * If there's no way we can send any packets, return now. 3274 */ 3275 if (DC_TX_LIST_CNT - sc->dc_cdata.dc_tx_cnt < 6) 3276 return (ENOBUFS); 3277 3278 /* 3279 * Count the number of frags in this chain to see if 3280 * we need to m_defrag. Since the descriptor list is shared 3281 * by all packets, we'll m_defrag long chains so that they 3282 * do not use up the entire list, even if they would fit. 3283 */ 3284 for (m = *m_head; m != NULL; m = m->m_next) 3285 chainlen++; 3286 3287 if ((chainlen > DC_TX_LIST_CNT / 4) || 3288 ((DC_TX_LIST_CNT - (chainlen + sc->dc_cdata.dc_tx_cnt)) < 6)) { 3289 m = m_defrag(*m_head, M_DONTWAIT); 3290 if (m == NULL) 3291 return (ENOBUFS); 3292 *m_head = m; 3293 } 3294 3295 /* 3296 * Start packing the mbufs in this chain into 3297 * the fragment pointers. Stop when we run out 3298 * of fragments or hit the end of the mbuf chain. 3299 */ 3300 idx = sc->dc_cdata.dc_tx_prod; 3301 error = bus_dmamap_load_mbuf(sc->dc_mtag, sc->dc_cdata.dc_tx_map[idx], 3302 *m_head, dc_dma_map_txbuf, sc, 0); 3303 if (error) 3304 return (error); 3305 if (sc->dc_cdata.dc_tx_err != 0) 3306 return (sc->dc_cdata.dc_tx_err); 3307 sc->dc_cdata.dc_tx_chain[idx] = *m_head; 3308 bus_dmamap_sync(sc->dc_mtag, sc->dc_cdata.dc_tx_map[idx], 3309 BUS_DMASYNC_PREWRITE); 3310 bus_dmamap_sync(sc->dc_ltag, sc->dc_lmap, 3311 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3312 return (0); 3313 } 3314 3315 /* 3316 * Main transmit routine. To avoid having to do mbuf copies, we put pointers 3317 * to the mbuf data regions directly in the transmit lists. We also save a 3318 * copy of the pointers since the transmit list fragment pointers are 3319 * physical addresses. 3320 */ 3321 3322 static void 3323 dc_start(struct ifnet *ifp) 3324 { 3325 struct dc_softc *sc; 3326 struct mbuf *m_head = NULL, *m; 3327 int idx; 3328 3329 sc = ifp->if_softc; 3330 3331 DC_LOCK(sc); 3332 3333 if (!sc->dc_link && ifp->if_snd.ifq_len < 10) { 3334 DC_UNLOCK(sc); 3335 return; 3336 } 3337 3338 if (ifp->if_flags & IFF_OACTIVE) { 3339 DC_UNLOCK(sc); 3340 return; 3341 } 3342 3343 idx = sc->dc_cdata.dc_tx_first = sc->dc_cdata.dc_tx_prod; 3344 3345 while (sc->dc_cdata.dc_tx_chain[idx] == NULL) { 3346 IF_DEQUEUE(&ifp->if_snd, m_head); 3347 if (m_head == NULL) 3348 break; 3349 3350 if (sc->dc_flags & DC_TX_COALESCE && 3351 (m_head->m_next != NULL || 3352 sc->dc_flags & DC_TX_ALIGN)) { 3353 m = m_defrag(m_head, M_DONTWAIT); 3354 if (m == NULL) { 3355 IF_PREPEND(&ifp->if_snd, m_head); 3356 ifp->if_flags |= IFF_OACTIVE; 3357 break; 3358 } else { 3359 m_head = m; 3360 } 3361 } 3362 3363 if (dc_encap(sc, &m_head)) { 3364 IF_PREPEND(&ifp->if_snd, m_head); 3365 ifp->if_flags |= IFF_OACTIVE; 3366 break; 3367 } 3368 idx = sc->dc_cdata.dc_tx_prod; 3369 3370 /* 3371 * If there's a BPF listener, bounce a copy of this frame 3372 * to him. 3373 */ 3374 BPF_MTAP(ifp, m_head); 3375 3376 if (sc->dc_flags & DC_TX_ONE) { 3377 ifp->if_flags |= IFF_OACTIVE; 3378 break; 3379 } 3380 } 3381 3382 /* Transmit */ 3383 if (!(sc->dc_flags & DC_TX_POLL)) 3384 CSR_WRITE_4(sc, DC_TXSTART, 0xFFFFFFFF); 3385 3386 /* 3387 * Set a timeout in case the chip goes out to lunch. 3388 */ 3389 ifp->if_timer = 5; 3390 3391 DC_UNLOCK(sc); 3392 } 3393 3394 static void 3395 dc_init(void *xsc) 3396 { 3397 struct dc_softc *sc = xsc; 3398 struct ifnet *ifp = &sc->arpcom.ac_if; 3399 struct mii_data *mii; 3400 3401 DC_LOCK(sc); 3402 3403 mii = device_get_softc(sc->dc_miibus); 3404 3405 /* 3406 * Cancel pending I/O and free all RX/TX buffers. 3407 */ 3408 dc_stop(sc); 3409 dc_reset(sc); 3410 3411 /* 3412 * Set cache alignment and burst length. 3413 */ 3414 if (DC_IS_ASIX(sc) || DC_IS_DAVICOM(sc)) 3415 CSR_WRITE_4(sc, DC_BUSCTL, 0); 3416 else 3417 CSR_WRITE_4(sc, DC_BUSCTL, DC_BUSCTL_MRME | DC_BUSCTL_MRLE); 3418 /* 3419 * Evenly share the bus between receive and transmit process. 3420 */ 3421 if (DC_IS_INTEL(sc)) 3422 DC_SETBIT(sc, DC_BUSCTL, DC_BUSCTL_ARBITRATION); 3423 if (DC_IS_DAVICOM(sc) || DC_IS_INTEL(sc)) { 3424 DC_SETBIT(sc, DC_BUSCTL, DC_BURSTLEN_USECA); 3425 } else { 3426 DC_SETBIT(sc, DC_BUSCTL, DC_BURSTLEN_16LONG); 3427 } 3428 if (sc->dc_flags & DC_TX_POLL) 3429 DC_SETBIT(sc, DC_BUSCTL, DC_TXPOLL_1); 3430 switch(sc->dc_cachesize) { 3431 case 32: 3432 DC_SETBIT(sc, DC_BUSCTL, DC_CACHEALIGN_32LONG); 3433 break; 3434 case 16: 3435 DC_SETBIT(sc, DC_BUSCTL, DC_CACHEALIGN_16LONG); 3436 break; 3437 case 8: 3438 DC_SETBIT(sc, DC_BUSCTL, DC_CACHEALIGN_8LONG); 3439 break; 3440 case 0: 3441 default: 3442 DC_SETBIT(sc, DC_BUSCTL, DC_CACHEALIGN_NONE); 3443 break; 3444 } 3445 3446 if (sc->dc_flags & DC_TX_STORENFWD) 3447 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_STORENFWD); 3448 else { 3449 if (sc->dc_txthresh > DC_TXTHRESH_MAX) { 3450 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_STORENFWD); 3451 } else { 3452 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_STORENFWD); 3453 DC_SETBIT(sc, DC_NETCFG, sc->dc_txthresh); 3454 } 3455 } 3456 3457 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_NO_RXCRC); 3458 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_TX_BACKOFF); 3459 3460 if (DC_IS_MACRONIX(sc) || DC_IS_PNICII(sc)) { 3461 /* 3462 * The app notes for the 98713 and 98715A say that 3463 * in order to have the chips operate properly, a magic 3464 * number must be written to CSR16. Macronix does not 3465 * document the meaning of these bits so there's no way 3466 * to know exactly what they do. The 98713 has a magic 3467 * number all its own; the rest all use a different one. 3468 */ 3469 DC_CLRBIT(sc, DC_MX_MAGICPACKET, 0xFFFF0000); 3470 if (sc->dc_type == DC_TYPE_98713) 3471 DC_SETBIT(sc, DC_MX_MAGICPACKET, DC_MX_MAGIC_98713); 3472 else 3473 DC_SETBIT(sc, DC_MX_MAGICPACKET, DC_MX_MAGIC_98715); 3474 } 3475 3476 if (DC_IS_XIRCOM(sc)) { 3477 /* 3478 * setup General Purpose Port mode and data so the tulip 3479 * can talk to the MII. 3480 */ 3481 CSR_WRITE_4(sc, DC_SIAGP, DC_SIAGP_WRITE_EN | DC_SIAGP_INT1_EN | 3482 DC_SIAGP_MD_GP2_OUTPUT | DC_SIAGP_MD_GP0_OUTPUT); 3483 DELAY(10); 3484 CSR_WRITE_4(sc, DC_SIAGP, DC_SIAGP_INT1_EN | 3485 DC_SIAGP_MD_GP2_OUTPUT | DC_SIAGP_MD_GP0_OUTPUT); 3486 DELAY(10); 3487 } 3488 3489 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_TX_THRESH); 3490 DC_SETBIT(sc, DC_NETCFG, DC_TXTHRESH_MIN); 3491 3492 /* Init circular RX list. */ 3493 if (dc_list_rx_init(sc) == ENOBUFS) { 3494 printf("dc%d: initialization failed: no " 3495 "memory for rx buffers\n", sc->dc_unit); 3496 dc_stop(sc); 3497 DC_UNLOCK(sc); 3498 return; 3499 } 3500 3501 /* 3502 * Init TX descriptors. 3503 */ 3504 dc_list_tx_init(sc); 3505 3506 /* 3507 * Load the address of the RX list. 3508 */ 3509 CSR_WRITE_4(sc, DC_RXADDR, DC_RXDESC(sc, 0)); 3510 CSR_WRITE_4(sc, DC_TXADDR, DC_TXDESC(sc, 0)); 3511 3512 /* 3513 * Enable interrupts. 3514 */ 3515 #ifdef DEVICE_POLLING 3516 /* 3517 * ... but only if we are not polling, and make sure they are off in 3518 * the case of polling. Some cards (e.g. fxp) turn interrupts on 3519 * after a reset. 3520 */ 3521 if (ifp->if_flags & IFF_POLLING) 3522 CSR_WRITE_4(sc, DC_IMR, 0x00000000); 3523 else 3524 #endif 3525 CSR_WRITE_4(sc, DC_IMR, DC_INTRS); 3526 CSR_WRITE_4(sc, DC_ISR, 0xFFFFFFFF); 3527 3528 /* Enable transmitter. */ 3529 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_TX_ON); 3530 3531 /* 3532 * If this is an Intel 21143 and we're not using the 3533 * MII port, program the LED control pins so we get 3534 * link and activity indications. 3535 */ 3536 if (sc->dc_flags & DC_TULIP_LEDS) { 3537 CSR_WRITE_4(sc, DC_WATCHDOG, 3538 DC_WDOG_CTLWREN | DC_WDOG_LINK | DC_WDOG_ACTIVITY); 3539 CSR_WRITE_4(sc, DC_WATCHDOG, 0); 3540 } 3541 3542 /* 3543 * Load the RX/multicast filter. We do this sort of late 3544 * because the filter programming scheme on the 21143 and 3545 * some clones requires DMAing a setup frame via the TX 3546 * engine, and we need the transmitter enabled for that. 3547 */ 3548 dc_setfilt(sc); 3549 3550 /* Enable receiver. */ 3551 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_ON); 3552 CSR_WRITE_4(sc, DC_RXSTART, 0xFFFFFFFF); 3553 3554 mii_mediachg(mii); 3555 dc_setcfg(sc, sc->dc_if_media); 3556 3557 ifp->if_flags |= IFF_RUNNING; 3558 ifp->if_flags &= ~IFF_OACTIVE; 3559 3560 /* Don't start the ticker if this is a homePNA link. */ 3561 if (IFM_SUBTYPE(mii->mii_media.ifm_media) == IFM_HPNA_1) 3562 sc->dc_link = 1; 3563 else { 3564 if (sc->dc_flags & DC_21143_NWAY) 3565 callout_reset(&sc->dc_stat_ch, hz/10, dc_tick, sc); 3566 else 3567 callout_reset(&sc->dc_stat_ch, hz, dc_tick, sc); 3568 } 3569 3570 #ifdef SRM_MEDIA 3571 if(sc->dc_srm_media) { 3572 struct ifreq ifr; 3573 3574 ifr.ifr_media = sc->dc_srm_media; 3575 ifmedia_ioctl(ifp, &ifr, &mii->mii_media, SIOCSIFMEDIA); 3576 sc->dc_srm_media = 0; 3577 } 3578 #endif 3579 DC_UNLOCK(sc); 3580 } 3581 3582 /* 3583 * Set media options. 3584 */ 3585 static int 3586 dc_ifmedia_upd(struct ifnet *ifp) 3587 { 3588 struct dc_softc *sc; 3589 struct mii_data *mii; 3590 struct ifmedia *ifm; 3591 3592 sc = ifp->if_softc; 3593 mii = device_get_softc(sc->dc_miibus); 3594 mii_mediachg(mii); 3595 ifm = &mii->mii_media; 3596 3597 if (DC_IS_DAVICOM(sc) && 3598 IFM_SUBTYPE(ifm->ifm_media) == IFM_HPNA_1) 3599 dc_setcfg(sc, ifm->ifm_media); 3600 else 3601 sc->dc_link = 0; 3602 3603 return (0); 3604 } 3605 3606 /* 3607 * Report current media status. 3608 */ 3609 static void 3610 dc_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 3611 { 3612 struct dc_softc *sc; 3613 struct mii_data *mii; 3614 struct ifmedia *ifm; 3615 3616 sc = ifp->if_softc; 3617 mii = device_get_softc(sc->dc_miibus); 3618 mii_pollstat(mii); 3619 ifm = &mii->mii_media; 3620 if (DC_IS_DAVICOM(sc)) { 3621 if (IFM_SUBTYPE(ifm->ifm_media) == IFM_HPNA_1) { 3622 ifmr->ifm_active = ifm->ifm_media; 3623 ifmr->ifm_status = 0; 3624 return; 3625 } 3626 } 3627 ifmr->ifm_active = mii->mii_media_active; 3628 ifmr->ifm_status = mii->mii_media_status; 3629 } 3630 3631 static int 3632 dc_ioctl(struct ifnet *ifp, u_long command, caddr_t data) 3633 { 3634 struct dc_softc *sc = ifp->if_softc; 3635 struct ifreq *ifr = (struct ifreq *)data; 3636 struct mii_data *mii; 3637 int error = 0; 3638 3639 DC_LOCK(sc); 3640 3641 switch (command) { 3642 case SIOCSIFFLAGS: 3643 if (ifp->if_flags & IFF_UP) { 3644 int need_setfilt = (ifp->if_flags ^ sc->dc_if_flags) & 3645 (IFF_PROMISC | IFF_ALLMULTI); 3646 3647 if (ifp->if_flags & IFF_RUNNING) { 3648 if (need_setfilt) 3649 dc_setfilt(sc); 3650 } else { 3651 sc->dc_txthresh = 0; 3652 dc_init(sc); 3653 } 3654 } else { 3655 if (ifp->if_flags & IFF_RUNNING) 3656 dc_stop(sc); 3657 } 3658 sc->dc_if_flags = ifp->if_flags; 3659 error = 0; 3660 break; 3661 case SIOCADDMULTI: 3662 case SIOCDELMULTI: 3663 dc_setfilt(sc); 3664 error = 0; 3665 break; 3666 case SIOCGIFMEDIA: 3667 case SIOCSIFMEDIA: 3668 mii = device_get_softc(sc->dc_miibus); 3669 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 3670 #ifdef SRM_MEDIA 3671 if (sc->dc_srm_media) 3672 sc->dc_srm_media = 0; 3673 #endif 3674 break; 3675 default: 3676 error = ether_ioctl(ifp, command, data); 3677 break; 3678 } 3679 3680 DC_UNLOCK(sc); 3681 3682 return (error); 3683 } 3684 3685 static void 3686 dc_watchdog(struct ifnet *ifp) 3687 { 3688 struct dc_softc *sc; 3689 3690 sc = ifp->if_softc; 3691 3692 DC_LOCK(sc); 3693 3694 ifp->if_oerrors++; 3695 printf("dc%d: watchdog timeout\n", sc->dc_unit); 3696 3697 dc_stop(sc); 3698 dc_reset(sc); 3699 dc_init(sc); 3700 3701 if (ifp->if_snd.ifq_head != NULL) 3702 dc_start(ifp); 3703 3704 DC_UNLOCK(sc); 3705 } 3706 3707 /* 3708 * Stop the adapter and free any mbufs allocated to the 3709 * RX and TX lists. 3710 */ 3711 static void 3712 dc_stop(struct dc_softc *sc) 3713 { 3714 struct ifnet *ifp; 3715 struct dc_list_data *ld; 3716 struct dc_chain_data *cd; 3717 int i; 3718 u_int32_t ctl; 3719 3720 DC_LOCK(sc); 3721 3722 ifp = &sc->arpcom.ac_if; 3723 ifp->if_timer = 0; 3724 ld = sc->dc_ldata; 3725 cd = &sc->dc_cdata; 3726 3727 callout_stop(&sc->dc_stat_ch); 3728 3729 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 3730 #ifdef DEVICE_POLLING 3731 ether_poll_deregister(ifp); 3732 #endif 3733 3734 DC_CLRBIT(sc, DC_NETCFG, (DC_NETCFG_RX_ON | DC_NETCFG_TX_ON)); 3735 CSR_WRITE_4(sc, DC_IMR, 0x00000000); 3736 CSR_WRITE_4(sc, DC_TXADDR, 0x00000000); 3737 CSR_WRITE_4(sc, DC_RXADDR, 0x00000000); 3738 sc->dc_link = 0; 3739 3740 /* 3741 * Free data in the RX lists. 3742 */ 3743 for (i = 0; i < DC_RX_LIST_CNT; i++) { 3744 if (cd->dc_rx_chain[i] != NULL) { 3745 m_freem(cd->dc_rx_chain[i]); 3746 cd->dc_rx_chain[i] = NULL; 3747 } 3748 } 3749 bzero(&ld->dc_rx_list, sizeof(ld->dc_rx_list)); 3750 3751 /* 3752 * Free the TX list buffers. 3753 */ 3754 for (i = 0; i < DC_TX_LIST_CNT; i++) { 3755 if (cd->dc_tx_chain[i] != NULL) { 3756 ctl = le32toh(ld->dc_tx_list[i].dc_ctl); 3757 if ((ctl & DC_TXCTL_SETUP) || 3758 !(ctl & DC_TXCTL_FIRSTFRAG)) { 3759 cd->dc_tx_chain[i] = NULL; 3760 continue; 3761 } 3762 bus_dmamap_unload(sc->dc_mtag, cd->dc_tx_map[i]); 3763 m_freem(cd->dc_tx_chain[i]); 3764 cd->dc_tx_chain[i] = NULL; 3765 } 3766 } 3767 bzero(&ld->dc_tx_list, sizeof(ld->dc_tx_list)); 3768 3769 DC_UNLOCK(sc); 3770 } 3771 3772 /* 3773 * Device suspend routine. Stop the interface and save some PCI 3774 * settings in case the BIOS doesn't restore them properly on 3775 * resume. 3776 */ 3777 static int 3778 dc_suspend(device_t dev) 3779 { 3780 struct dc_softc *sc; 3781 int i, s; 3782 3783 s = splimp(); 3784 3785 sc = device_get_softc(dev); 3786 3787 dc_stop(sc); 3788 3789 for (i = 0; i < 5; i++) 3790 sc->saved_maps[i] = pci_read_config(dev, PCIR_BAR(i), 4); 3791 sc->saved_biosaddr = pci_read_config(dev, PCIR_BIOS, 4); 3792 sc->saved_intline = pci_read_config(dev, PCIR_INTLINE, 1); 3793 sc->saved_cachelnsz = pci_read_config(dev, PCIR_CACHELNSZ, 1); 3794 sc->saved_lattimer = pci_read_config(dev, PCIR_LATTIMER, 1); 3795 3796 sc->suspended = 1; 3797 3798 splx(s); 3799 return (0); 3800 } 3801 3802 /* 3803 * Device resume routine. Restore some PCI settings in case the BIOS 3804 * doesn't, re-enable busmastering, and restart the interface if 3805 * appropriate. 3806 */ 3807 static int 3808 dc_resume(device_t dev) 3809 { 3810 struct dc_softc *sc; 3811 struct ifnet *ifp; 3812 int i, s; 3813 3814 s = splimp(); 3815 3816 sc = device_get_softc(dev); 3817 ifp = &sc->arpcom.ac_if; 3818 #ifndef BURN_BRIDGES 3819 dc_acpi(dev); 3820 #endif 3821 /* better way to do this? */ 3822 for (i = 0; i < 5; i++) 3823 pci_write_config(dev, PCIR_BAR(i), sc->saved_maps[i], 4); 3824 pci_write_config(dev, PCIR_BIOS, sc->saved_biosaddr, 4); 3825 pci_write_config(dev, PCIR_INTLINE, sc->saved_intline, 1); 3826 pci_write_config(dev, PCIR_CACHELNSZ, sc->saved_cachelnsz, 1); 3827 pci_write_config(dev, PCIR_LATTIMER, sc->saved_lattimer, 1); 3828 3829 /* reenable busmastering */ 3830 pci_enable_busmaster(dev); 3831 pci_enable_io(dev, DC_RES); 3832 3833 /* reinitialize interface if necessary */ 3834 if (ifp->if_flags & IFF_UP) 3835 dc_init(sc); 3836 3837 sc->suspended = 0; 3838 3839 splx(s); 3840 return (0); 3841 } 3842 3843 /* 3844 * Stop all chip I/O so that the kernel's probe routines don't 3845 * get confused by errant DMAs when rebooting. 3846 */ 3847 static void 3848 dc_shutdown(device_t dev) 3849 { 3850 struct dc_softc *sc; 3851 3852 sc = device_get_softc(dev); 3853 3854 dc_stop(sc); 3855 } 3856