1 /* 2 * Copyright (c) 1997, 1998, 1999 3 * Bill Paul <wpaul@ee.columbia.edu>. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 3. All advertising materials mentioning features or use of this software 14 * must display the following acknowledgement: 15 * This product includes software developed by Bill Paul. 16 * 4. Neither the name of the author nor the names of any co-contributors 17 * may be used to endorse or promote products derived from this software 18 * without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30 * THE POSSIBILITY OF SUCH DAMAGE. 31 * 32 * $FreeBSD$ 33 */ 34 35 /* 36 * DEC "tulip" clone ethernet driver. Supports the DEC/Intel 21143 37 * series chips and several workalikes including the following: 38 * 39 * Macronix 98713/98715/98725/98727/98732 PMAC (www.macronix.com) 40 * Macronix/Lite-On 82c115 PNIC II (www.macronix.com) 41 * Lite-On 82c168/82c169 PNIC (www.litecom.com) 42 * ASIX Electronics AX88140A (www.asix.com.tw) 43 * ASIX Electronics AX88141 (www.asix.com.tw) 44 * ADMtek AL981 (www.admtek.com.tw) 45 * ADMtek AN985 (www.admtek.com.tw) 46 * Davicom DM9100, DM9102, DM9102A (www.davicom8.com) 47 * Accton EN1217 (www.accton.com) 48 * Xircom X3201 (www.xircom.com) 49 * Abocom FE2500 50 * Conexant LANfinity (www.conexant.com) 51 * 52 * Datasheets for the 21143 are available at developer.intel.com. 53 * Datasheets for the clone parts can be found at their respective sites. 54 * (Except for the PNIC; see www.freebsd.org/~wpaul/PNIC/pnic.ps.gz.) 55 * The PNIC II is essentially a Macronix 98715A chip; the only difference 56 * worth noting is that its multicast hash table is only 128 bits wide 57 * instead of 512. 58 * 59 * Written by Bill Paul <wpaul@ee.columbia.edu> 60 * Electrical Engineering Department 61 * Columbia University, New York City 62 */ 63 64 /* 65 * The Intel 21143 is the successor to the DEC 21140. It is basically 66 * the same as the 21140 but with a few new features. The 21143 supports 67 * three kinds of media attachments: 68 * 69 * o MII port, for 10Mbps and 100Mbps support and NWAY 70 * autonegotiation provided by an external PHY. 71 * o SYM port, for symbol mode 100Mbps support. 72 * o 10baseT port. 73 * o AUI/BNC port. 74 * 75 * The 100Mbps SYM port and 10baseT port can be used together in 76 * combination with the internal NWAY support to create a 10/100 77 * autosensing configuration. 78 * 79 * Note that not all tulip workalikes are handled in this driver: we only 80 * deal with those which are relatively well behaved. The Winbond is 81 * handled separately due to its different register offsets and the 82 * special handling needed for its various bugs. The PNIC is handled 83 * here, but I'm not thrilled about it. 84 * 85 * All of the workalike chips use some form of MII transceiver support 86 * with the exception of the Macronix chips, which also have a SYM port. 87 * The ASIX AX88140A is also documented to have a SYM port, but all 88 * the cards I've seen use an MII transceiver, probably because the 89 * AX88140A doesn't support internal NWAY. 90 */ 91 92 #include <sys/param.h> 93 #include <sys/systm.h> 94 #include <sys/sockio.h> 95 #include <sys/mbuf.h> 96 #include <sys/malloc.h> 97 #include <sys/kernel.h> 98 #include <sys/socket.h> 99 #include <sys/sysctl.h> 100 101 #include <net/if.h> 102 #include <net/if_arp.h> 103 #include <net/ethernet.h> 104 #include <net/if_dl.h> 105 #include <net/if_media.h> 106 #include <net/if_types.h> 107 #include <net/if_vlan_var.h> 108 109 #include <net/bpf.h> 110 111 #include <vm/vm.h> /* for vtophys */ 112 #include <vm/pmap.h> /* for vtophys */ 113 #include <machine/bus_pio.h> 114 #include <machine/bus_memio.h> 115 #include <machine/bus.h> 116 #include <machine/resource.h> 117 #include <sys/bus.h> 118 #include <sys/rman.h> 119 120 #include <dev/mii/mii.h> 121 #include <dev/mii/miivar.h> 122 123 #include <pci/pcireg.h> 124 #include <pci/pcivar.h> 125 126 #define DC_USEIOSPACE 127 #ifdef __alpha__ 128 #define SRM_MEDIA 129 #endif 130 131 #include <pci/if_dcreg.h> 132 133 MODULE_DEPEND(dc, miibus, 1, 1, 1); 134 135 /* "controller miibus0" required. See GENERIC if you get errors here. */ 136 #include "miibus_if.h" 137 138 #ifndef lint 139 static const char rcsid[] = 140 "$FreeBSD$"; 141 #endif 142 143 /* 144 * Various supported device vendors/types and their names. 145 */ 146 static struct dc_type dc_devs[] = { 147 { DC_VENDORID_DEC, DC_DEVICEID_21143, 148 "Intel 21143 10/100BaseTX" }, 149 { DC_VENDORID_DAVICOM, DC_DEVICEID_DM9009, 150 "Davicom DM9009 10/100BaseTX" }, 151 { DC_VENDORID_DAVICOM, DC_DEVICEID_DM9100, 152 "Davicom DM9100 10/100BaseTX" }, 153 { DC_VENDORID_DAVICOM, DC_DEVICEID_DM9102, 154 "Davicom DM9102 10/100BaseTX" }, 155 { DC_VENDORID_DAVICOM, DC_DEVICEID_DM9102, 156 "Davicom DM9102A 10/100BaseTX" }, 157 { DC_VENDORID_ADMTEK, DC_DEVICEID_AL981, 158 "ADMtek AL981 10/100BaseTX" }, 159 { DC_VENDORID_ADMTEK, DC_DEVICEID_AN985, 160 "ADMtek AN985 10/100BaseTX" }, 161 { DC_VENDORID_ASIX, DC_DEVICEID_AX88140A, 162 "ASIX AX88140A 10/100BaseTX" }, 163 { DC_VENDORID_ASIX, DC_DEVICEID_AX88140A, 164 "ASIX AX88141 10/100BaseTX" }, 165 { DC_VENDORID_MX, DC_DEVICEID_98713, 166 "Macronix 98713 10/100BaseTX" }, 167 { DC_VENDORID_MX, DC_DEVICEID_98713, 168 "Macronix 98713A 10/100BaseTX" }, 169 { DC_VENDORID_CP, DC_DEVICEID_98713_CP, 170 "Compex RL100-TX 10/100BaseTX" }, 171 { DC_VENDORID_CP, DC_DEVICEID_98713_CP, 172 "Compex RL100-TX 10/100BaseTX" }, 173 { DC_VENDORID_MX, DC_DEVICEID_987x5, 174 "Macronix 98715/98715A 10/100BaseTX" }, 175 { DC_VENDORID_MX, DC_DEVICEID_987x5, 176 "Macronix 98715AEC-C 10/100BaseTX" }, 177 { DC_VENDORID_MX, DC_DEVICEID_987x5, 178 "Macronix 98725 10/100BaseTX" }, 179 { DC_VENDORID_MX, DC_DEVICEID_98727, 180 "Macronix 98727/98732 10/100BaseTX" }, 181 { DC_VENDORID_LO, DC_DEVICEID_82C115, 182 "LC82C115 PNIC II 10/100BaseTX" }, 183 { DC_VENDORID_LO, DC_DEVICEID_82C168, 184 "82c168 PNIC 10/100BaseTX" }, 185 { DC_VENDORID_LO, DC_DEVICEID_82C168, 186 "82c169 PNIC 10/100BaseTX" }, 187 { DC_VENDORID_ACCTON, DC_DEVICEID_EN1217, 188 "Accton EN1217 10/100BaseTX" }, 189 { DC_VENDORID_ACCTON, DC_DEVICEID_EN2242, 190 "Accton EN2242 MiniPCI 10/100BaseTX" }, 191 { DC_VENDORID_XIRCOM, DC_DEVICEID_X3201, 192 "Xircom X3201 10/100BaseTX" }, 193 { DC_VENDORID_ABOCOM, DC_DEVICEID_FE2500, 194 "Abocom FE2500 10/100BaseTX" }, 195 { DC_VENDORID_CONEXANT, DC_DEVICEID_RS7112, 196 "Conexant LANfinity MiniPCI 10/100BaseTX" }, 197 { DC_VENDORID_HAWKING, DC_DEVICEID_HAWKING_PN672TX, 198 "Hawking CB102 CardBus 10/100" }, 199 { 0, 0, NULL } 200 }; 201 202 static int dc_probe (device_t); 203 static int dc_attach (device_t); 204 static int dc_detach (device_t); 205 static int dc_suspend (device_t); 206 static int dc_resume (device_t); 207 static void dc_acpi (device_t); 208 static struct dc_type *dc_devtype (device_t); 209 static int dc_newbuf (struct dc_softc *, int, struct mbuf *); 210 static int dc_encap (struct dc_softc *, struct mbuf *, u_int32_t *); 211 static int dc_coal (struct dc_softc *, struct mbuf **); 212 static void dc_pnic_rx_bug_war (struct dc_softc *, int); 213 static int dc_rx_resync (struct dc_softc *); 214 static void dc_rxeof (struct dc_softc *); 215 static void dc_txeof (struct dc_softc *); 216 static void dc_tick (void *); 217 static void dc_tx_underrun (struct dc_softc *); 218 static void dc_intr (void *); 219 static void dc_start (struct ifnet *); 220 static int dc_ioctl (struct ifnet *, u_long, caddr_t); 221 static void dc_init (void *); 222 static void dc_stop (struct dc_softc *); 223 static void dc_watchdog (struct ifnet *); 224 static void dc_shutdown (device_t); 225 static int dc_ifmedia_upd (struct ifnet *); 226 static void dc_ifmedia_sts (struct ifnet *, struct ifmediareq *); 227 228 static void dc_delay (struct dc_softc *); 229 static void dc_eeprom_idle (struct dc_softc *); 230 static void dc_eeprom_putbyte (struct dc_softc *, int); 231 static void dc_eeprom_getword (struct dc_softc *, int, u_int16_t *); 232 static void dc_eeprom_getword_pnic 233 (struct dc_softc *, int, u_int16_t *); 234 static void dc_eeprom_getword_xircom 235 (struct dc_softc *, int, u_int16_t *); 236 static void dc_eeprom_width (struct dc_softc *); 237 static void dc_read_eeprom (struct dc_softc *, caddr_t, int, int, int); 238 239 static void dc_mii_writebit (struct dc_softc *, int); 240 static int dc_mii_readbit (struct dc_softc *); 241 static void dc_mii_sync (struct dc_softc *); 242 static void dc_mii_send (struct dc_softc *, u_int32_t, int); 243 static int dc_mii_readreg (struct dc_softc *, struct dc_mii_frame *); 244 static int dc_mii_writereg (struct dc_softc *, struct dc_mii_frame *); 245 static int dc_miibus_readreg (device_t, int, int); 246 static int dc_miibus_writereg (device_t, int, int, int); 247 static void dc_miibus_statchg (device_t); 248 static void dc_miibus_mediainit (device_t); 249 250 static void dc_setcfg (struct dc_softc *, int); 251 static u_int32_t dc_crc_le (struct dc_softc *, caddr_t); 252 static u_int32_t dc_crc_be (caddr_t); 253 static void dc_setfilt_21143 (struct dc_softc *); 254 static void dc_setfilt_asix (struct dc_softc *); 255 static void dc_setfilt_admtek (struct dc_softc *); 256 static void dc_setfilt_xircom (struct dc_softc *); 257 258 static void dc_setfilt (struct dc_softc *); 259 260 static void dc_reset (struct dc_softc *); 261 static int dc_list_rx_init (struct dc_softc *); 262 static int dc_list_tx_init (struct dc_softc *); 263 264 static void dc_read_srom (struct dc_softc *, int); 265 static void dc_parse_21143_srom (struct dc_softc *); 266 static void dc_decode_leaf_sia (struct dc_softc *, struct dc_eblock_sia *); 267 static void dc_decode_leaf_mii (struct dc_softc *, struct dc_eblock_mii *); 268 static void dc_decode_leaf_sym (struct dc_softc *, struct dc_eblock_sym *); 269 static void dc_apply_fixup (struct dc_softc *, int); 270 271 #ifdef DC_USEIOSPACE 272 #define DC_RES SYS_RES_IOPORT 273 #define DC_RID DC_PCI_CFBIO 274 #else 275 #define DC_RES SYS_RES_MEMORY 276 #define DC_RID DC_PCI_CFBMA 277 #endif 278 279 static device_method_t dc_methods[] = { 280 /* Device interface */ 281 DEVMETHOD(device_probe, dc_probe), 282 DEVMETHOD(device_attach, dc_attach), 283 DEVMETHOD(device_detach, dc_detach), 284 DEVMETHOD(device_suspend, dc_suspend), 285 DEVMETHOD(device_resume, dc_resume), 286 DEVMETHOD(device_shutdown, dc_shutdown), 287 288 /* bus interface */ 289 DEVMETHOD(bus_print_child, bus_generic_print_child), 290 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 291 292 /* MII interface */ 293 DEVMETHOD(miibus_readreg, dc_miibus_readreg), 294 DEVMETHOD(miibus_writereg, dc_miibus_writereg), 295 DEVMETHOD(miibus_statchg, dc_miibus_statchg), 296 DEVMETHOD(miibus_mediainit, dc_miibus_mediainit), 297 298 { 0, 0 } 299 }; 300 301 static driver_t dc_driver = { 302 "dc", 303 dc_methods, 304 sizeof(struct dc_softc) 305 }; 306 307 static devclass_t dc_devclass; 308 #ifdef __i386__ 309 static int dc_quick=1; 310 SYSCTL_INT(_hw, OID_AUTO, dc_quick, CTLFLAG_RW, 311 &dc_quick,0,"do not mdevget in dc driver"); 312 #endif 313 314 DRIVER_MODULE(if_dc, cardbus, dc_driver, dc_devclass, 0, 0); 315 DRIVER_MODULE(if_dc, pci, dc_driver, dc_devclass, 0, 0); 316 DRIVER_MODULE(miibus, dc, miibus_driver, miibus_devclass, 0, 0); 317 318 #define DC_SETBIT(sc, reg, x) \ 319 CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) | (x)) 320 321 #define DC_CLRBIT(sc, reg, x) \ 322 CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) & ~(x)) 323 324 #define SIO_SET(x) DC_SETBIT(sc, DC_SIO, (x)) 325 #define SIO_CLR(x) DC_CLRBIT(sc, DC_SIO, (x)) 326 327 #define IS_MPSAFE 0 328 329 static void 330 dc_delay(sc) 331 struct dc_softc *sc; 332 { 333 int idx; 334 335 for (idx = (300 / 33) + 1; idx > 0; idx--) 336 CSR_READ_4(sc, DC_BUSCTL); 337 } 338 339 static void 340 dc_eeprom_width(sc) 341 struct dc_softc *sc; 342 { 343 int i; 344 345 /* Force EEPROM to idle state. */ 346 dc_eeprom_idle(sc); 347 348 /* Enter EEPROM access mode. */ 349 CSR_WRITE_4(sc, DC_SIO, DC_SIO_EESEL); 350 dc_delay(sc); 351 DC_SETBIT(sc, DC_SIO, DC_SIO_ROMCTL_READ); 352 dc_delay(sc); 353 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); 354 dc_delay(sc); 355 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CS); 356 dc_delay(sc); 357 358 for (i = 3; i--;) { 359 if (6 & (1 << i)) 360 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_DATAIN); 361 else 362 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_DATAIN); 363 dc_delay(sc); 364 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CLK); 365 dc_delay(sc); 366 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); 367 dc_delay(sc); 368 } 369 370 for (i = 1; i <= 12; i++) { 371 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CLK); 372 dc_delay(sc); 373 if (!(CSR_READ_4(sc, DC_SIO) & DC_SIO_EE_DATAOUT)) { 374 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); 375 dc_delay(sc); 376 break; 377 } 378 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); 379 dc_delay(sc); 380 } 381 382 /* Turn off EEPROM access mode. */ 383 dc_eeprom_idle(sc); 384 385 if (i < 4 || i > 12) 386 sc->dc_romwidth = 6; 387 else 388 sc->dc_romwidth = i; 389 390 /* Enter EEPROM access mode. */ 391 CSR_WRITE_4(sc, DC_SIO, DC_SIO_EESEL); 392 dc_delay(sc); 393 DC_SETBIT(sc, DC_SIO, DC_SIO_ROMCTL_READ); 394 dc_delay(sc); 395 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); 396 dc_delay(sc); 397 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CS); 398 dc_delay(sc); 399 400 /* Turn off EEPROM access mode. */ 401 dc_eeprom_idle(sc); 402 } 403 404 static void 405 dc_eeprom_idle(sc) 406 struct dc_softc *sc; 407 { 408 register int i; 409 410 CSR_WRITE_4(sc, DC_SIO, DC_SIO_EESEL); 411 dc_delay(sc); 412 DC_SETBIT(sc, DC_SIO, DC_SIO_ROMCTL_READ); 413 dc_delay(sc); 414 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); 415 dc_delay(sc); 416 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CS); 417 dc_delay(sc); 418 419 for (i = 0; i < 25; i++) { 420 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); 421 dc_delay(sc); 422 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CLK); 423 dc_delay(sc); 424 } 425 426 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); 427 dc_delay(sc); 428 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CS); 429 dc_delay(sc); 430 CSR_WRITE_4(sc, DC_SIO, 0x00000000); 431 432 return; 433 } 434 435 /* 436 * Send a read command and address to the EEPROM, check for ACK. 437 */ 438 static void 439 dc_eeprom_putbyte(sc, addr) 440 struct dc_softc *sc; 441 int addr; 442 { 443 register int d, i; 444 445 d = DC_EECMD_READ >> 6; 446 for (i = 3; i--; ) { 447 if (d & (1 << i)) 448 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_DATAIN); 449 else 450 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_DATAIN); 451 dc_delay(sc); 452 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CLK); 453 dc_delay(sc); 454 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); 455 dc_delay(sc); 456 } 457 458 /* 459 * Feed in each bit and strobe the clock. 460 */ 461 for (i = sc->dc_romwidth; i--;) { 462 if (addr & (1 << i)) { 463 SIO_SET(DC_SIO_EE_DATAIN); 464 } else { 465 SIO_CLR(DC_SIO_EE_DATAIN); 466 } 467 dc_delay(sc); 468 SIO_SET(DC_SIO_EE_CLK); 469 dc_delay(sc); 470 SIO_CLR(DC_SIO_EE_CLK); 471 dc_delay(sc); 472 } 473 474 return; 475 } 476 477 /* 478 * Read a word of data stored in the EEPROM at address 'addr.' 479 * The PNIC 82c168/82c169 has its own non-standard way to read 480 * the EEPROM. 481 */ 482 static void 483 dc_eeprom_getword_pnic(sc, addr, dest) 484 struct dc_softc *sc; 485 int addr; 486 u_int16_t *dest; 487 { 488 register int i; 489 u_int32_t r; 490 491 CSR_WRITE_4(sc, DC_PN_SIOCTL, DC_PN_EEOPCODE_READ|addr); 492 493 for (i = 0; i < DC_TIMEOUT; i++) { 494 DELAY(1); 495 r = CSR_READ_4(sc, DC_SIO); 496 if (!(r & DC_PN_SIOCTL_BUSY)) { 497 *dest = (u_int16_t)(r & 0xFFFF); 498 return; 499 } 500 } 501 502 return; 503 } 504 505 /* 506 * Read a word of data stored in the EEPROM at address 'addr.' 507 * The Xircom X3201 has its own non-standard way to read 508 * the EEPROM, too. 509 */ 510 static void 511 dc_eeprom_getword_xircom(sc, addr, dest) 512 struct dc_softc *sc; 513 int addr; 514 u_int16_t *dest; 515 { 516 SIO_SET(DC_SIO_ROMSEL | DC_SIO_ROMCTL_READ); 517 518 addr *= 2; 519 CSR_WRITE_4(sc, DC_ROM, addr | 0x160); 520 *dest = (u_int16_t)CSR_READ_4(sc, DC_SIO)&0xff; 521 addr += 1; 522 CSR_WRITE_4(sc, DC_ROM, addr | 0x160); 523 *dest |= ((u_int16_t)CSR_READ_4(sc, DC_SIO)&0xff) << 8; 524 525 SIO_CLR(DC_SIO_ROMSEL | DC_SIO_ROMCTL_READ); 526 return; 527 } 528 529 /* 530 * Read a word of data stored in the EEPROM at address 'addr.' 531 */ 532 static void 533 dc_eeprom_getword(sc, addr, dest) 534 struct dc_softc *sc; 535 int addr; 536 u_int16_t *dest; 537 { 538 register int i; 539 u_int16_t word = 0; 540 541 /* Force EEPROM to idle state. */ 542 dc_eeprom_idle(sc); 543 544 /* Enter EEPROM access mode. */ 545 CSR_WRITE_4(sc, DC_SIO, DC_SIO_EESEL); 546 dc_delay(sc); 547 DC_SETBIT(sc, DC_SIO, DC_SIO_ROMCTL_READ); 548 dc_delay(sc); 549 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); 550 dc_delay(sc); 551 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CS); 552 dc_delay(sc); 553 554 /* 555 * Send address of word we want to read. 556 */ 557 dc_eeprom_putbyte(sc, addr); 558 559 /* 560 * Start reading bits from EEPROM. 561 */ 562 for (i = 0x8000; i; i >>= 1) { 563 SIO_SET(DC_SIO_EE_CLK); 564 dc_delay(sc); 565 if (CSR_READ_4(sc, DC_SIO) & DC_SIO_EE_DATAOUT) 566 word |= i; 567 dc_delay(sc); 568 SIO_CLR(DC_SIO_EE_CLK); 569 dc_delay(sc); 570 } 571 572 /* Turn off EEPROM access mode. */ 573 dc_eeprom_idle(sc); 574 575 *dest = word; 576 577 return; 578 } 579 580 /* 581 * Read a sequence of words from the EEPROM. 582 */ 583 static void 584 dc_read_eeprom(sc, dest, off, cnt, swap) 585 struct dc_softc *sc; 586 caddr_t dest; 587 int off; 588 int cnt; 589 int swap; 590 { 591 int i; 592 u_int16_t word = 0, *ptr; 593 594 for (i = 0; i < cnt; i++) { 595 if (DC_IS_PNIC(sc)) 596 dc_eeprom_getword_pnic(sc, off + i, &word); 597 else if (DC_IS_XIRCOM(sc)) 598 dc_eeprom_getword_xircom(sc, off + i, &word); 599 else 600 dc_eeprom_getword(sc, off + i, &word); 601 ptr = (u_int16_t *)(dest + (i * 2)); 602 if (swap) 603 *ptr = ntohs(word); 604 else 605 *ptr = word; 606 } 607 608 return; 609 } 610 611 /* 612 * The following two routines are taken from the Macronix 98713 613 * Application Notes pp.19-21. 614 */ 615 /* 616 * Write a bit to the MII bus. 617 */ 618 static void 619 dc_mii_writebit(sc, bit) 620 struct dc_softc *sc; 621 int bit; 622 { 623 if (bit) 624 CSR_WRITE_4(sc, DC_SIO, 625 DC_SIO_ROMCTL_WRITE|DC_SIO_MII_DATAOUT); 626 else 627 CSR_WRITE_4(sc, DC_SIO, DC_SIO_ROMCTL_WRITE); 628 629 DC_SETBIT(sc, DC_SIO, DC_SIO_MII_CLK); 630 DC_CLRBIT(sc, DC_SIO, DC_SIO_MII_CLK); 631 632 return; 633 } 634 635 /* 636 * Read a bit from the MII bus. 637 */ 638 static int 639 dc_mii_readbit(sc) 640 struct dc_softc *sc; 641 { 642 CSR_WRITE_4(sc, DC_SIO, DC_SIO_ROMCTL_READ|DC_SIO_MII_DIR); 643 CSR_READ_4(sc, DC_SIO); 644 DC_SETBIT(sc, DC_SIO, DC_SIO_MII_CLK); 645 DC_CLRBIT(sc, DC_SIO, DC_SIO_MII_CLK); 646 if (CSR_READ_4(sc, DC_SIO) & DC_SIO_MII_DATAIN) 647 return(1); 648 649 return(0); 650 } 651 652 /* 653 * Sync the PHYs by setting data bit and strobing the clock 32 times. 654 */ 655 static void 656 dc_mii_sync(sc) 657 struct dc_softc *sc; 658 { 659 register int i; 660 661 CSR_WRITE_4(sc, DC_SIO, DC_SIO_ROMCTL_WRITE); 662 663 for (i = 0; i < 32; i++) 664 dc_mii_writebit(sc, 1); 665 666 return; 667 } 668 669 /* 670 * Clock a series of bits through the MII. 671 */ 672 static void 673 dc_mii_send(sc, bits, cnt) 674 struct dc_softc *sc; 675 u_int32_t bits; 676 int cnt; 677 { 678 int i; 679 680 for (i = (0x1 << (cnt - 1)); i; i >>= 1) 681 dc_mii_writebit(sc, bits & i); 682 } 683 684 /* 685 * Read an PHY register through the MII. 686 */ 687 static int 688 dc_mii_readreg(sc, frame) 689 struct dc_softc *sc; 690 struct dc_mii_frame *frame; 691 692 { 693 int i, ack; 694 695 DC_LOCK(sc); 696 697 /* 698 * Set up frame for RX. 699 */ 700 frame->mii_stdelim = DC_MII_STARTDELIM; 701 frame->mii_opcode = DC_MII_READOP; 702 frame->mii_turnaround = 0; 703 frame->mii_data = 0; 704 705 /* 706 * Sync the PHYs. 707 */ 708 dc_mii_sync(sc); 709 710 /* 711 * Send command/address info. 712 */ 713 dc_mii_send(sc, frame->mii_stdelim, 2); 714 dc_mii_send(sc, frame->mii_opcode, 2); 715 dc_mii_send(sc, frame->mii_phyaddr, 5); 716 dc_mii_send(sc, frame->mii_regaddr, 5); 717 718 #ifdef notdef 719 /* Idle bit */ 720 dc_mii_writebit(sc, 1); 721 dc_mii_writebit(sc, 0); 722 #endif 723 724 /* Check for ack */ 725 ack = dc_mii_readbit(sc); 726 727 /* 728 * Now try reading data bits. If the ack failed, we still 729 * need to clock through 16 cycles to keep the PHY(s) in sync. 730 */ 731 if (ack) { 732 for(i = 0; i < 16; i++) { 733 dc_mii_readbit(sc); 734 } 735 goto fail; 736 } 737 738 for (i = 0x8000; i; i >>= 1) { 739 if (!ack) { 740 if (dc_mii_readbit(sc)) 741 frame->mii_data |= i; 742 } 743 } 744 745 fail: 746 747 dc_mii_writebit(sc, 0); 748 dc_mii_writebit(sc, 0); 749 750 DC_UNLOCK(sc); 751 752 if (ack) 753 return(1); 754 return(0); 755 } 756 757 /* 758 * Write to a PHY register through the MII. 759 */ 760 static int 761 dc_mii_writereg(sc, frame) 762 struct dc_softc *sc; 763 struct dc_mii_frame *frame; 764 765 { 766 DC_LOCK(sc); 767 /* 768 * Set up frame for TX. 769 */ 770 771 frame->mii_stdelim = DC_MII_STARTDELIM; 772 frame->mii_opcode = DC_MII_WRITEOP; 773 frame->mii_turnaround = DC_MII_TURNAROUND; 774 775 /* 776 * Sync the PHYs. 777 */ 778 dc_mii_sync(sc); 779 780 dc_mii_send(sc, frame->mii_stdelim, 2); 781 dc_mii_send(sc, frame->mii_opcode, 2); 782 dc_mii_send(sc, frame->mii_phyaddr, 5); 783 dc_mii_send(sc, frame->mii_regaddr, 5); 784 dc_mii_send(sc, frame->mii_turnaround, 2); 785 dc_mii_send(sc, frame->mii_data, 16); 786 787 /* Idle bit. */ 788 dc_mii_writebit(sc, 0); 789 dc_mii_writebit(sc, 0); 790 791 DC_UNLOCK(sc); 792 793 return(0); 794 } 795 796 static int 797 dc_miibus_readreg(dev, phy, reg) 798 device_t dev; 799 int phy, reg; 800 { 801 struct dc_mii_frame frame; 802 struct dc_softc *sc; 803 int i, rval, phy_reg = 0; 804 805 sc = device_get_softc(dev); 806 bzero((char *)&frame, sizeof(frame)); 807 808 /* 809 * Note: both the AL981 and AN985 have internal PHYs, 810 * however the AL981 provides direct access to the PHY 811 * registers while the AN985 uses a serial MII interface. 812 * The AN985's MII interface is also buggy in that you 813 * can read from any MII address (0 to 31), but only address 1 814 * behaves normally. To deal with both cases, we pretend 815 * that the PHY is at MII address 1. 816 */ 817 if (DC_IS_ADMTEK(sc) && phy != DC_ADMTEK_PHYADDR) 818 return(0); 819 820 /* 821 * Note: the ukphy probes of the RS7112 report a PHY at 822 * MII address 0 (possibly HomePNA?) and 1 (ethernet) 823 * so we only respond to correct one. 824 */ 825 if (DC_IS_CONEXANT(sc) && phy != DC_CONEXANT_PHYADDR) 826 return(0); 827 828 if (sc->dc_pmode != DC_PMODE_MII) { 829 if (phy == (MII_NPHY - 1)) { 830 switch(reg) { 831 case MII_BMSR: 832 /* 833 * Fake something to make the probe 834 * code think there's a PHY here. 835 */ 836 return(BMSR_MEDIAMASK); 837 break; 838 case MII_PHYIDR1: 839 if (DC_IS_PNIC(sc)) 840 return(DC_VENDORID_LO); 841 return(DC_VENDORID_DEC); 842 break; 843 case MII_PHYIDR2: 844 if (DC_IS_PNIC(sc)) 845 return(DC_DEVICEID_82C168); 846 return(DC_DEVICEID_21143); 847 break; 848 default: 849 return(0); 850 break; 851 } 852 } else 853 return(0); 854 } 855 856 if (DC_IS_PNIC(sc)) { 857 CSR_WRITE_4(sc, DC_PN_MII, DC_PN_MIIOPCODE_READ | 858 (phy << 23) | (reg << 18)); 859 for (i = 0; i < DC_TIMEOUT; i++) { 860 DELAY(1); 861 rval = CSR_READ_4(sc, DC_PN_MII); 862 if (!(rval & DC_PN_MII_BUSY)) { 863 rval &= 0xFFFF; 864 return(rval == 0xFFFF ? 0 : rval); 865 } 866 } 867 return(0); 868 } 869 870 if (DC_IS_COMET(sc)) { 871 switch(reg) { 872 case MII_BMCR: 873 phy_reg = DC_AL_BMCR; 874 break; 875 case MII_BMSR: 876 phy_reg = DC_AL_BMSR; 877 break; 878 case MII_PHYIDR1: 879 phy_reg = DC_AL_VENID; 880 break; 881 case MII_PHYIDR2: 882 phy_reg = DC_AL_DEVID; 883 break; 884 case MII_ANAR: 885 phy_reg = DC_AL_ANAR; 886 break; 887 case MII_ANLPAR: 888 phy_reg = DC_AL_LPAR; 889 break; 890 case MII_ANER: 891 phy_reg = DC_AL_ANER; 892 break; 893 default: 894 printf("dc%d: phy_read: bad phy register %x\n", 895 sc->dc_unit, reg); 896 return(0); 897 break; 898 } 899 900 rval = CSR_READ_4(sc, phy_reg) & 0x0000FFFF; 901 902 if (rval == 0xFFFF) 903 return(0); 904 return(rval); 905 } 906 907 frame.mii_phyaddr = phy; 908 frame.mii_regaddr = reg; 909 if (sc->dc_type == DC_TYPE_98713) { 910 phy_reg = CSR_READ_4(sc, DC_NETCFG); 911 CSR_WRITE_4(sc, DC_NETCFG, phy_reg & ~DC_NETCFG_PORTSEL); 912 } 913 dc_mii_readreg(sc, &frame); 914 if (sc->dc_type == DC_TYPE_98713) 915 CSR_WRITE_4(sc, DC_NETCFG, phy_reg); 916 917 return(frame.mii_data); 918 } 919 920 static int 921 dc_miibus_writereg(dev, phy, reg, data) 922 device_t dev; 923 int phy, reg, data; 924 { 925 struct dc_softc *sc; 926 struct dc_mii_frame frame; 927 int i, phy_reg = 0; 928 929 sc = device_get_softc(dev); 930 bzero((char *)&frame, sizeof(frame)); 931 932 if (DC_IS_ADMTEK(sc) && phy != DC_ADMTEK_PHYADDR) 933 return(0); 934 935 if (DC_IS_CONEXANT(sc) && phy != DC_CONEXANT_PHYADDR) 936 return(0); 937 938 if (DC_IS_PNIC(sc)) { 939 CSR_WRITE_4(sc, DC_PN_MII, DC_PN_MIIOPCODE_WRITE | 940 (phy << 23) | (reg << 10) | data); 941 for (i = 0; i < DC_TIMEOUT; i++) { 942 if (!(CSR_READ_4(sc, DC_PN_MII) & DC_PN_MII_BUSY)) 943 break; 944 } 945 return(0); 946 } 947 948 if (DC_IS_COMET(sc)) { 949 switch(reg) { 950 case MII_BMCR: 951 phy_reg = DC_AL_BMCR; 952 break; 953 case MII_BMSR: 954 phy_reg = DC_AL_BMSR; 955 break; 956 case MII_PHYIDR1: 957 phy_reg = DC_AL_VENID; 958 break; 959 case MII_PHYIDR2: 960 phy_reg = DC_AL_DEVID; 961 break; 962 case MII_ANAR: 963 phy_reg = DC_AL_ANAR; 964 break; 965 case MII_ANLPAR: 966 phy_reg = DC_AL_LPAR; 967 break; 968 case MII_ANER: 969 phy_reg = DC_AL_ANER; 970 break; 971 default: 972 printf("dc%d: phy_write: bad phy register %x\n", 973 sc->dc_unit, reg); 974 return(0); 975 break; 976 } 977 978 CSR_WRITE_4(sc, phy_reg, data); 979 return(0); 980 } 981 982 frame.mii_phyaddr = phy; 983 frame.mii_regaddr = reg; 984 frame.mii_data = data; 985 986 if (sc->dc_type == DC_TYPE_98713) { 987 phy_reg = CSR_READ_4(sc, DC_NETCFG); 988 CSR_WRITE_4(sc, DC_NETCFG, phy_reg & ~DC_NETCFG_PORTSEL); 989 } 990 dc_mii_writereg(sc, &frame); 991 if (sc->dc_type == DC_TYPE_98713) 992 CSR_WRITE_4(sc, DC_NETCFG, phy_reg); 993 994 return(0); 995 } 996 997 static void 998 dc_miibus_statchg(dev) 999 device_t dev; 1000 { 1001 struct dc_softc *sc; 1002 struct mii_data *mii; 1003 struct ifmedia *ifm; 1004 1005 sc = device_get_softc(dev); 1006 if (DC_IS_ADMTEK(sc)) 1007 return; 1008 1009 mii = device_get_softc(sc->dc_miibus); 1010 ifm = &mii->mii_media; 1011 if (DC_IS_DAVICOM(sc) && 1012 IFM_SUBTYPE(ifm->ifm_media) == IFM_HPNA_1) { 1013 dc_setcfg(sc, ifm->ifm_media); 1014 sc->dc_if_media = ifm->ifm_media; 1015 } else { 1016 dc_setcfg(sc, mii->mii_media_active); 1017 sc->dc_if_media = mii->mii_media_active; 1018 } 1019 1020 return; 1021 } 1022 1023 /* 1024 * Special support for DM9102A cards with HomePNA PHYs. Note: 1025 * with the Davicom DM9102A/DM9801 eval board that I have, it seems 1026 * to be impossible to talk to the management interface of the DM9801 1027 * PHY (its MDIO pin is not connected to anything). Consequently, 1028 * the driver has to just 'know' about the additional mode and deal 1029 * with it itself. *sigh* 1030 */ 1031 static void 1032 dc_miibus_mediainit(dev) 1033 device_t dev; 1034 { 1035 struct dc_softc *sc; 1036 struct mii_data *mii; 1037 struct ifmedia *ifm; 1038 int rev; 1039 1040 rev = pci_read_config(dev, DC_PCI_CFRV, 4) & 0xFF; 1041 1042 sc = device_get_softc(dev); 1043 mii = device_get_softc(sc->dc_miibus); 1044 ifm = &mii->mii_media; 1045 1046 if (DC_IS_DAVICOM(sc) && rev >= DC_REVISION_DM9102A) 1047 ifmedia_add(ifm, IFM_ETHER|IFM_HPNA_1, 0, NULL); 1048 1049 return; 1050 } 1051 1052 #define DC_POLY 0xEDB88320 1053 #define DC_BITS_512 9 1054 #define DC_BITS_128 7 1055 #define DC_BITS_64 6 1056 1057 static u_int32_t 1058 dc_crc_le(sc, addr) 1059 struct dc_softc *sc; 1060 caddr_t addr; 1061 { 1062 u_int32_t idx, bit, data, crc; 1063 1064 /* Compute CRC for the address value. */ 1065 crc = 0xFFFFFFFF; /* initial value */ 1066 1067 for (idx = 0; idx < 6; idx++) { 1068 for (data = *addr++, bit = 0; bit < 8; bit++, data >>= 1) 1069 crc = (crc >> 1) ^ (((crc ^ data) & 1) ? DC_POLY : 0); 1070 } 1071 1072 /* 1073 * The hash table on the PNIC II and the MX98715AEC-C/D/E 1074 * chips is only 128 bits wide. 1075 */ 1076 if (sc->dc_flags & DC_128BIT_HASH) 1077 return (crc & ((1 << DC_BITS_128) - 1)); 1078 1079 /* The hash table on the MX98715BEC is only 64 bits wide. */ 1080 if (sc->dc_flags & DC_64BIT_HASH) 1081 return (crc & ((1 << DC_BITS_64) - 1)); 1082 1083 /* Xircom's hash filtering table is different (read: weird) */ 1084 /* Xircom uses the LEAST significant bits */ 1085 if (DC_IS_XIRCOM(sc)) { 1086 if ((crc & 0x180) == 0x180) 1087 return (crc & 0x0F) + (crc & 0x70)*3 + (14 << 4); 1088 else 1089 return (crc & 0x1F) + ((crc>>1) & 0xF0)*3 + (12 << 4); 1090 } 1091 1092 return (crc & ((1 << DC_BITS_512) - 1)); 1093 } 1094 1095 /* 1096 * Calculate CRC of a multicast group address, return the lower 6 bits. 1097 */ 1098 static u_int32_t 1099 dc_crc_be(addr) 1100 caddr_t addr; 1101 { 1102 u_int32_t crc, carry; 1103 int i, j; 1104 u_int8_t c; 1105 1106 /* Compute CRC for the address value. */ 1107 crc = 0xFFFFFFFF; /* initial value */ 1108 1109 for (i = 0; i < 6; i++) { 1110 c = *(addr + i); 1111 for (j = 0; j < 8; j++) { 1112 carry = ((crc & 0x80000000) ? 1 : 0) ^ (c & 0x01); 1113 crc <<= 1; 1114 c >>= 1; 1115 if (carry) 1116 crc = (crc ^ 0x04c11db6) | carry; 1117 } 1118 } 1119 1120 /* return the filter bit position */ 1121 return((crc >> 26) & 0x0000003F); 1122 } 1123 1124 /* 1125 * 21143-style RX filter setup routine. Filter programming is done by 1126 * downloading a special setup frame into the TX engine. 21143, Macronix, 1127 * PNIC, PNIC II and Davicom chips are programmed this way. 1128 * 1129 * We always program the chip using 'hash perfect' mode, i.e. one perfect 1130 * address (our node address) and a 512-bit hash filter for multicast 1131 * frames. We also sneak the broadcast address into the hash filter since 1132 * we need that too. 1133 */ 1134 static void 1135 dc_setfilt_21143(sc) 1136 struct dc_softc *sc; 1137 { 1138 struct dc_desc *sframe; 1139 u_int32_t h, *sp; 1140 struct ifmultiaddr *ifma; 1141 struct ifnet *ifp; 1142 int i; 1143 1144 ifp = &sc->arpcom.ac_if; 1145 1146 i = sc->dc_cdata.dc_tx_prod; 1147 DC_INC(sc->dc_cdata.dc_tx_prod, DC_TX_LIST_CNT); 1148 sc->dc_cdata.dc_tx_cnt++; 1149 sframe = &sc->dc_ldata->dc_tx_list[i]; 1150 sp = (u_int32_t *)&sc->dc_cdata.dc_sbuf; 1151 bzero((char *)sp, DC_SFRAME_LEN); 1152 1153 sframe->dc_data = vtophys(&sc->dc_cdata.dc_sbuf); 1154 sframe->dc_ctl = DC_SFRAME_LEN | DC_TXCTL_SETUP | DC_TXCTL_TLINK | 1155 DC_FILTER_HASHPERF | DC_TXCTL_FINT; 1156 1157 sc->dc_cdata.dc_tx_chain[i] = (struct mbuf *)&sc->dc_cdata.dc_sbuf; 1158 1159 /* If we want promiscuous mode, set the allframes bit. */ 1160 if (ifp->if_flags & IFF_PROMISC) 1161 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC); 1162 else 1163 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC); 1164 1165 if (ifp->if_flags & IFF_ALLMULTI) 1166 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI); 1167 else 1168 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI); 1169 1170 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 1171 if (ifma->ifma_addr->sa_family != AF_LINK) 1172 continue; 1173 h = dc_crc_le(sc, 1174 LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 1175 sp[h >> 4] |= 1 << (h & 0xF); 1176 } 1177 1178 if (ifp->if_flags & IFF_BROADCAST) { 1179 h = dc_crc_le(sc, (caddr_t)ifp->if_broadcastaddr); 1180 sp[h >> 4] |= 1 << (h & 0xF); 1181 } 1182 1183 /* Set our MAC address */ 1184 sp[39] = ((u_int16_t *)sc->arpcom.ac_enaddr)[0]; 1185 sp[40] = ((u_int16_t *)sc->arpcom.ac_enaddr)[1]; 1186 sp[41] = ((u_int16_t *)sc->arpcom.ac_enaddr)[2]; 1187 1188 sframe->dc_status = DC_TXSTAT_OWN; 1189 CSR_WRITE_4(sc, DC_TXSTART, 0xFFFFFFFF); 1190 1191 /* 1192 * The PNIC takes an exceedingly long time to process its 1193 * setup frame; wait 10ms after posting the setup frame 1194 * before proceeding, just so it has time to swallow its 1195 * medicine. 1196 */ 1197 DELAY(10000); 1198 1199 ifp->if_timer = 5; 1200 1201 return; 1202 } 1203 1204 static void 1205 dc_setfilt_admtek(sc) 1206 struct dc_softc *sc; 1207 { 1208 struct ifnet *ifp; 1209 int h = 0; 1210 u_int32_t hashes[2] = { 0, 0 }; 1211 struct ifmultiaddr *ifma; 1212 1213 ifp = &sc->arpcom.ac_if; 1214 1215 /* Init our MAC address */ 1216 CSR_WRITE_4(sc, DC_AL_PAR0, *(u_int32_t *)(&sc->arpcom.ac_enaddr[0])); 1217 CSR_WRITE_4(sc, DC_AL_PAR1, *(u_int32_t *)(&sc->arpcom.ac_enaddr[4])); 1218 1219 /* If we want promiscuous mode, set the allframes bit. */ 1220 if (ifp->if_flags & IFF_PROMISC) 1221 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC); 1222 else 1223 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC); 1224 1225 if (ifp->if_flags & IFF_ALLMULTI) 1226 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI); 1227 else 1228 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI); 1229 1230 /* first, zot all the existing hash bits */ 1231 CSR_WRITE_4(sc, DC_AL_MAR0, 0); 1232 CSR_WRITE_4(sc, DC_AL_MAR1, 0); 1233 1234 /* 1235 * If we're already in promisc or allmulti mode, we 1236 * don't have to bother programming the multicast filter. 1237 */ 1238 if (ifp->if_flags & (IFF_PROMISC|IFF_ALLMULTI)) 1239 return; 1240 1241 /* now program new ones */ 1242 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 1243 if (ifma->ifma_addr->sa_family != AF_LINK) 1244 continue; 1245 h = dc_crc_be(LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 1246 if (h < 32) 1247 hashes[0] |= (1 << h); 1248 else 1249 hashes[1] |= (1 << (h - 32)); 1250 } 1251 1252 CSR_WRITE_4(sc, DC_AL_MAR0, hashes[0]); 1253 CSR_WRITE_4(sc, DC_AL_MAR1, hashes[1]); 1254 1255 return; 1256 } 1257 1258 static void 1259 dc_setfilt_asix(sc) 1260 struct dc_softc *sc; 1261 { 1262 struct ifnet *ifp; 1263 int h = 0; 1264 u_int32_t hashes[2] = { 0, 0 }; 1265 struct ifmultiaddr *ifma; 1266 1267 ifp = &sc->arpcom.ac_if; 1268 1269 /* Init our MAC address */ 1270 CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_PAR0); 1271 CSR_WRITE_4(sc, DC_AX_FILTDATA, 1272 *(u_int32_t *)(&sc->arpcom.ac_enaddr[0])); 1273 CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_PAR1); 1274 CSR_WRITE_4(sc, DC_AX_FILTDATA, 1275 *(u_int32_t *)(&sc->arpcom.ac_enaddr[4])); 1276 1277 /* If we want promiscuous mode, set the allframes bit. */ 1278 if (ifp->if_flags & IFF_PROMISC) 1279 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC); 1280 else 1281 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC); 1282 1283 if (ifp->if_flags & IFF_ALLMULTI) 1284 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI); 1285 else 1286 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI); 1287 1288 /* 1289 * The ASIX chip has a special bit to enable reception 1290 * of broadcast frames. 1291 */ 1292 if (ifp->if_flags & IFF_BROADCAST) 1293 DC_SETBIT(sc, DC_NETCFG, DC_AX_NETCFG_RX_BROAD); 1294 else 1295 DC_CLRBIT(sc, DC_NETCFG, DC_AX_NETCFG_RX_BROAD); 1296 1297 /* first, zot all the existing hash bits */ 1298 CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_MAR0); 1299 CSR_WRITE_4(sc, DC_AX_FILTDATA, 0); 1300 CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_MAR1); 1301 CSR_WRITE_4(sc, DC_AX_FILTDATA, 0); 1302 1303 /* 1304 * If we're already in promisc or allmulti mode, we 1305 * don't have to bother programming the multicast filter. 1306 */ 1307 if (ifp->if_flags & (IFF_PROMISC|IFF_ALLMULTI)) 1308 return; 1309 1310 /* now program new ones */ 1311 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 1312 if (ifma->ifma_addr->sa_family != AF_LINK) 1313 continue; 1314 h = dc_crc_be(LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 1315 if (h < 32) 1316 hashes[0] |= (1 << h); 1317 else 1318 hashes[1] |= (1 << (h - 32)); 1319 } 1320 1321 CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_MAR0); 1322 CSR_WRITE_4(sc, DC_AX_FILTDATA, hashes[0]); 1323 CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_MAR1); 1324 CSR_WRITE_4(sc, DC_AX_FILTDATA, hashes[1]); 1325 1326 return; 1327 } 1328 1329 static void 1330 dc_setfilt_xircom(sc) 1331 struct dc_softc *sc; 1332 { 1333 struct dc_desc *sframe; 1334 u_int32_t h, *sp; 1335 struct ifmultiaddr *ifma; 1336 struct ifnet *ifp; 1337 int i; 1338 1339 ifp = &sc->arpcom.ac_if; 1340 DC_CLRBIT(sc, DC_NETCFG, (DC_NETCFG_TX_ON|DC_NETCFG_RX_ON)); 1341 1342 i = sc->dc_cdata.dc_tx_prod; 1343 DC_INC(sc->dc_cdata.dc_tx_prod, DC_TX_LIST_CNT); 1344 sc->dc_cdata.dc_tx_cnt++; 1345 sframe = &sc->dc_ldata->dc_tx_list[i]; 1346 sp = (u_int32_t *)&sc->dc_cdata.dc_sbuf; 1347 bzero((char *)sp, DC_SFRAME_LEN); 1348 1349 sframe->dc_data = vtophys(&sc->dc_cdata.dc_sbuf); 1350 sframe->dc_ctl = DC_SFRAME_LEN | DC_TXCTL_SETUP | DC_TXCTL_TLINK | 1351 DC_FILTER_HASHPERF | DC_TXCTL_FINT; 1352 1353 sc->dc_cdata.dc_tx_chain[i] = (struct mbuf *)&sc->dc_cdata.dc_sbuf; 1354 1355 /* If we want promiscuous mode, set the allframes bit. */ 1356 if (ifp->if_flags & IFF_PROMISC) 1357 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC); 1358 else 1359 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC); 1360 1361 if (ifp->if_flags & IFF_ALLMULTI) 1362 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI); 1363 else 1364 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI); 1365 1366 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 1367 if (ifma->ifma_addr->sa_family != AF_LINK) 1368 continue; 1369 h = dc_crc_le(sc, 1370 LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 1371 sp[h >> 4] |= 1 << (h & 0xF); 1372 } 1373 1374 if (ifp->if_flags & IFF_BROADCAST) { 1375 h = dc_crc_le(sc, (caddr_t)ifp->if_broadcastaddr); 1376 sp[h >> 4] |= 1 << (h & 0xF); 1377 } 1378 1379 /* Set our MAC address */ 1380 sp[0] = ((u_int16_t *)sc->arpcom.ac_enaddr)[0]; 1381 sp[1] = ((u_int16_t *)sc->arpcom.ac_enaddr)[1]; 1382 sp[2] = ((u_int16_t *)sc->arpcom.ac_enaddr)[2]; 1383 1384 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_TX_ON); 1385 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_ON); 1386 ifp->if_flags |= IFF_RUNNING; 1387 sframe->dc_status = DC_TXSTAT_OWN; 1388 CSR_WRITE_4(sc, DC_TXSTART, 0xFFFFFFFF); 1389 1390 /* 1391 * wait some time... 1392 */ 1393 DELAY(1000); 1394 1395 ifp->if_timer = 5; 1396 1397 return; 1398 } 1399 1400 static void 1401 dc_setfilt(sc) 1402 struct dc_softc *sc; 1403 { 1404 if (DC_IS_INTEL(sc) || DC_IS_MACRONIX(sc) || DC_IS_PNIC(sc) || 1405 DC_IS_PNICII(sc) || DC_IS_DAVICOM(sc) || DC_IS_CONEXANT(sc)) 1406 dc_setfilt_21143(sc); 1407 1408 if (DC_IS_ASIX(sc)) 1409 dc_setfilt_asix(sc); 1410 1411 if (DC_IS_ADMTEK(sc)) 1412 dc_setfilt_admtek(sc); 1413 1414 if (DC_IS_XIRCOM(sc)) 1415 dc_setfilt_xircom(sc); 1416 1417 return; 1418 } 1419 1420 /* 1421 * In order to fiddle with the 1422 * 'full-duplex' and '100Mbps' bits in the netconfig register, we 1423 * first have to put the transmit and/or receive logic in the idle state. 1424 */ 1425 static void 1426 dc_setcfg(sc, media) 1427 struct dc_softc *sc; 1428 int media; 1429 { 1430 int i, restart = 0; 1431 u_int32_t isr; 1432 1433 if (IFM_SUBTYPE(media) == IFM_NONE) 1434 return; 1435 1436 if (CSR_READ_4(sc, DC_NETCFG) & (DC_NETCFG_TX_ON|DC_NETCFG_RX_ON)) { 1437 restart = 1; 1438 DC_CLRBIT(sc, DC_NETCFG, (DC_NETCFG_TX_ON|DC_NETCFG_RX_ON)); 1439 1440 for (i = 0; i < DC_TIMEOUT; i++) { 1441 isr = CSR_READ_4(sc, DC_ISR); 1442 if (isr & DC_ISR_TX_IDLE && 1443 ((isr & DC_ISR_RX_STATE) == DC_RXSTATE_STOPPED || 1444 (isr & DC_ISR_RX_STATE) == DC_RXSTATE_WAIT)) 1445 break; 1446 DELAY(10); 1447 } 1448 1449 if (i == DC_TIMEOUT) 1450 printf("dc%d: failed to force tx and " 1451 "rx to idle state\n", sc->dc_unit); 1452 } 1453 1454 if (IFM_SUBTYPE(media) == IFM_100_TX) { 1455 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_SPEEDSEL); 1456 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_HEARTBEAT); 1457 if (sc->dc_pmode == DC_PMODE_MII) { 1458 int watchdogreg; 1459 1460 if (DC_IS_INTEL(sc)) { 1461 /* there's a write enable bit here that reads as 1 */ 1462 watchdogreg = CSR_READ_4(sc, DC_WATCHDOG); 1463 watchdogreg &= ~DC_WDOG_CTLWREN; 1464 watchdogreg |= DC_WDOG_JABBERDIS; 1465 CSR_WRITE_4(sc, DC_WATCHDOG, watchdogreg); 1466 } else { 1467 DC_SETBIT(sc, DC_WATCHDOG, DC_WDOG_JABBERDIS); 1468 } 1469 DC_CLRBIT(sc, DC_NETCFG, (DC_NETCFG_PCS| 1470 DC_NETCFG_PORTSEL|DC_NETCFG_SCRAMBLER)); 1471 if (sc->dc_type == DC_TYPE_98713) 1472 DC_SETBIT(sc, DC_NETCFG, (DC_NETCFG_PCS| 1473 DC_NETCFG_SCRAMBLER)); 1474 if (!DC_IS_DAVICOM(sc)) 1475 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL); 1476 DC_CLRBIT(sc, DC_10BTCTRL, 0xFFFF); 1477 if (DC_IS_INTEL(sc)) 1478 dc_apply_fixup(sc, IFM_AUTO); 1479 } else { 1480 if (DC_IS_PNIC(sc)) { 1481 DC_PN_GPIO_SETBIT(sc, DC_PN_GPIO_SPEEDSEL); 1482 DC_PN_GPIO_SETBIT(sc, DC_PN_GPIO_100TX_LOOP); 1483 DC_SETBIT(sc, DC_PN_NWAY, DC_PN_NWAY_SPEEDSEL); 1484 } 1485 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL); 1486 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PCS); 1487 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_SCRAMBLER); 1488 if (DC_IS_INTEL(sc)) 1489 dc_apply_fixup(sc, 1490 (media & IFM_GMASK) == IFM_FDX ? 1491 IFM_100_TX|IFM_FDX : IFM_100_TX); 1492 } 1493 } 1494 1495 if (IFM_SUBTYPE(media) == IFM_10_T) { 1496 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_SPEEDSEL); 1497 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_HEARTBEAT); 1498 if (sc->dc_pmode == DC_PMODE_MII) { 1499 int watchdogreg; 1500 1501 /* there's a write enable bit here that reads as 1 */ 1502 if (DC_IS_INTEL(sc)) { 1503 watchdogreg = CSR_READ_4(sc, DC_WATCHDOG); 1504 watchdogreg &= ~DC_WDOG_CTLWREN; 1505 watchdogreg |= DC_WDOG_JABBERDIS; 1506 CSR_WRITE_4(sc, DC_WATCHDOG, watchdogreg); 1507 } else { 1508 DC_SETBIT(sc, DC_WATCHDOG, DC_WDOG_JABBERDIS); 1509 } 1510 DC_CLRBIT(sc, DC_NETCFG, (DC_NETCFG_PCS| 1511 DC_NETCFG_PORTSEL|DC_NETCFG_SCRAMBLER)); 1512 if (sc->dc_type == DC_TYPE_98713) 1513 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PCS); 1514 if (!DC_IS_DAVICOM(sc)) 1515 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL); 1516 DC_CLRBIT(sc, DC_10BTCTRL, 0xFFFF); 1517 if (DC_IS_INTEL(sc)) 1518 dc_apply_fixup(sc, IFM_AUTO); 1519 } else { 1520 if (DC_IS_PNIC(sc)) { 1521 DC_PN_GPIO_CLRBIT(sc, DC_PN_GPIO_SPEEDSEL); 1522 DC_PN_GPIO_SETBIT(sc, DC_PN_GPIO_100TX_LOOP); 1523 DC_CLRBIT(sc, DC_PN_NWAY, DC_PN_NWAY_SPEEDSEL); 1524 } 1525 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL); 1526 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_PCS); 1527 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_SCRAMBLER); 1528 if (DC_IS_INTEL(sc)) { 1529 DC_CLRBIT(sc, DC_SIARESET, DC_SIA_RESET); 1530 DC_CLRBIT(sc, DC_10BTCTRL, 0xFFFF); 1531 if ((media & IFM_GMASK) == IFM_FDX) 1532 DC_SETBIT(sc, DC_10BTCTRL, 0x7F3D); 1533 else 1534 DC_SETBIT(sc, DC_10BTCTRL, 0x7F3F); 1535 DC_SETBIT(sc, DC_SIARESET, DC_SIA_RESET); 1536 DC_CLRBIT(sc, DC_10BTCTRL, 1537 DC_TCTL_AUTONEGENBL); 1538 dc_apply_fixup(sc, 1539 (media & IFM_GMASK) == IFM_FDX ? 1540 IFM_10_T|IFM_FDX : IFM_10_T); 1541 DELAY(20000); 1542 } 1543 } 1544 } 1545 1546 /* 1547 * If this is a Davicom DM9102A card with a DM9801 HomePNA 1548 * PHY and we want HomePNA mode, set the portsel bit to turn 1549 * on the external MII port. 1550 */ 1551 if (DC_IS_DAVICOM(sc)) { 1552 if (IFM_SUBTYPE(media) == IFM_HPNA_1) { 1553 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL); 1554 sc->dc_link = 1; 1555 } else { 1556 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL); 1557 } 1558 } 1559 1560 if ((media & IFM_GMASK) == IFM_FDX) { 1561 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_FULLDUPLEX); 1562 if (sc->dc_pmode == DC_PMODE_SYM && DC_IS_PNIC(sc)) 1563 DC_SETBIT(sc, DC_PN_NWAY, DC_PN_NWAY_DUPLEX); 1564 } else { 1565 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_FULLDUPLEX); 1566 if (sc->dc_pmode == DC_PMODE_SYM && DC_IS_PNIC(sc)) 1567 DC_CLRBIT(sc, DC_PN_NWAY, DC_PN_NWAY_DUPLEX); 1568 } 1569 1570 if (restart) 1571 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_TX_ON|DC_NETCFG_RX_ON); 1572 1573 return; 1574 } 1575 1576 static void 1577 dc_reset(sc) 1578 struct dc_softc *sc; 1579 { 1580 register int i; 1581 1582 DC_SETBIT(sc, DC_BUSCTL, DC_BUSCTL_RESET); 1583 1584 for (i = 0; i < DC_TIMEOUT; i++) { 1585 DELAY(10); 1586 if (!(CSR_READ_4(sc, DC_BUSCTL) & DC_BUSCTL_RESET)) 1587 break; 1588 } 1589 1590 if (DC_IS_ASIX(sc) || DC_IS_ADMTEK(sc) || DC_IS_CONEXANT(sc) || 1591 DC_IS_XIRCOM(sc) || DC_IS_INTEL(sc)) { 1592 DELAY(10000); 1593 DC_CLRBIT(sc, DC_BUSCTL, DC_BUSCTL_RESET); 1594 i = 0; 1595 } 1596 1597 if (i == DC_TIMEOUT) 1598 printf("dc%d: reset never completed!\n", sc->dc_unit); 1599 1600 /* Wait a little while for the chip to get its brains in order. */ 1601 DELAY(1000); 1602 1603 CSR_WRITE_4(sc, DC_IMR, 0x00000000); 1604 CSR_WRITE_4(sc, DC_BUSCTL, 0x00000000); 1605 CSR_WRITE_4(sc, DC_NETCFG, 0x00000000); 1606 1607 /* 1608 * Bring the SIA out of reset. In some cases, it looks 1609 * like failing to unreset the SIA soon enough gets it 1610 * into a state where it will never come out of reset 1611 * until we reset the whole chip again. 1612 */ 1613 if (DC_IS_INTEL(sc)) { 1614 DC_SETBIT(sc, DC_SIARESET, DC_SIA_RESET); 1615 CSR_WRITE_4(sc, DC_10BTCTRL, 0); 1616 CSR_WRITE_4(sc, DC_WATCHDOG, 0); 1617 } 1618 1619 return; 1620 } 1621 1622 static struct dc_type * 1623 dc_devtype(dev) 1624 device_t dev; 1625 { 1626 struct dc_type *t; 1627 u_int32_t rev; 1628 1629 t = dc_devs; 1630 1631 while(t->dc_name != NULL) { 1632 if ((pci_get_vendor(dev) == t->dc_vid) && 1633 (pci_get_device(dev) == t->dc_did)) { 1634 /* Check the PCI revision */ 1635 rev = pci_read_config(dev, DC_PCI_CFRV, 4) & 0xFF; 1636 if (t->dc_did == DC_DEVICEID_98713 && 1637 rev >= DC_REVISION_98713A) 1638 t++; 1639 if (t->dc_did == DC_DEVICEID_98713_CP && 1640 rev >= DC_REVISION_98713A) 1641 t++; 1642 if (t->dc_did == DC_DEVICEID_987x5 && 1643 rev >= DC_REVISION_98715AEC_C) 1644 t++; 1645 if (t->dc_did == DC_DEVICEID_987x5 && 1646 rev >= DC_REVISION_98725) 1647 t++; 1648 if (t->dc_did == DC_DEVICEID_AX88140A && 1649 rev >= DC_REVISION_88141) 1650 t++; 1651 if (t->dc_did == DC_DEVICEID_82C168 && 1652 rev >= DC_REVISION_82C169) 1653 t++; 1654 if (t->dc_did == DC_DEVICEID_DM9102 && 1655 rev >= DC_REVISION_DM9102A) 1656 t++; 1657 return(t); 1658 } 1659 t++; 1660 } 1661 1662 return(NULL); 1663 } 1664 1665 /* 1666 * Probe for a 21143 or clone chip. Check the PCI vendor and device 1667 * IDs against our list and return a device name if we find a match. 1668 * We do a little bit of extra work to identify the exact type of 1669 * chip. The MX98713 and MX98713A have the same PCI vendor/device ID, 1670 * but different revision IDs. The same is true for 98715/98715A 1671 * chips and the 98725, as well as the ASIX and ADMtek chips. In some 1672 * cases, the exact chip revision affects driver behavior. 1673 */ 1674 static int 1675 dc_probe(dev) 1676 device_t dev; 1677 { 1678 struct dc_type *t; 1679 1680 t = dc_devtype(dev); 1681 1682 if (t != NULL) { 1683 device_set_desc(dev, t->dc_name); 1684 return(0); 1685 } 1686 1687 return(ENXIO); 1688 } 1689 1690 static void 1691 dc_acpi(dev) 1692 device_t dev; 1693 { 1694 int unit; 1695 1696 unit = device_get_unit(dev); 1697 1698 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) { 1699 u_int32_t iobase, membase, irq; 1700 1701 /* Save important PCI config data. */ 1702 iobase = pci_read_config(dev, DC_PCI_CFBIO, 4); 1703 membase = pci_read_config(dev, DC_PCI_CFBMA, 4); 1704 irq = pci_read_config(dev, DC_PCI_CFIT, 4); 1705 1706 /* Reset the power state. */ 1707 printf("dc%d: chip is in D%d power mode " 1708 "-- setting to D0\n", unit, 1709 pci_get_powerstate(dev)); 1710 pci_set_powerstate(dev, PCI_POWERSTATE_D0); 1711 1712 /* Restore PCI config data. */ 1713 pci_write_config(dev, DC_PCI_CFBIO, iobase, 4); 1714 pci_write_config(dev, DC_PCI_CFBMA, membase, 4); 1715 pci_write_config(dev, DC_PCI_CFIT, irq, 4); 1716 } 1717 1718 return; 1719 } 1720 1721 static void 1722 dc_apply_fixup(sc, media) 1723 struct dc_softc *sc; 1724 int media; 1725 { 1726 struct dc_mediainfo *m; 1727 u_int8_t *p; 1728 int i; 1729 u_int32_t reg; 1730 1731 m = sc->dc_mi; 1732 1733 while (m != NULL) { 1734 if (m->dc_media == media) 1735 break; 1736 m = m->dc_next; 1737 } 1738 1739 if (m == NULL) 1740 return; 1741 1742 for (i = 0, p = m->dc_reset_ptr; i < m->dc_reset_len; i++, p += 2) { 1743 reg = (p[0] | (p[1] << 8)) << 16; 1744 CSR_WRITE_4(sc, DC_WATCHDOG, reg); 1745 } 1746 1747 for (i = 0, p = m->dc_gp_ptr; i < m->dc_gp_len; i++, p += 2) { 1748 reg = (p[0] | (p[1] << 8)) << 16; 1749 CSR_WRITE_4(sc, DC_WATCHDOG, reg); 1750 } 1751 1752 return; 1753 } 1754 1755 static void 1756 dc_decode_leaf_sia(sc, l) 1757 struct dc_softc *sc; 1758 struct dc_eblock_sia *l; 1759 { 1760 struct dc_mediainfo *m; 1761 1762 m = malloc(sizeof(struct dc_mediainfo), M_DEVBUF, M_NOWAIT); 1763 bzero(m, sizeof(struct dc_mediainfo)); 1764 if (l->dc_sia_code == DC_SIA_CODE_10BT) 1765 m->dc_media = IFM_10_T; 1766 1767 if (l->dc_sia_code == DC_SIA_CODE_10BT_FDX) 1768 m->dc_media = IFM_10_T|IFM_FDX; 1769 1770 if (l->dc_sia_code == DC_SIA_CODE_10B2) 1771 m->dc_media = IFM_10_2; 1772 1773 if (l->dc_sia_code == DC_SIA_CODE_10B5) 1774 m->dc_media = IFM_10_5; 1775 1776 m->dc_gp_len = 2; 1777 m->dc_gp_ptr = (u_int8_t *)&l->dc_sia_gpio_ctl; 1778 1779 m->dc_next = sc->dc_mi; 1780 sc->dc_mi = m; 1781 1782 sc->dc_pmode = DC_PMODE_SIA; 1783 1784 return; 1785 } 1786 1787 static void 1788 dc_decode_leaf_sym(sc, l) 1789 struct dc_softc *sc; 1790 struct dc_eblock_sym *l; 1791 { 1792 struct dc_mediainfo *m; 1793 1794 m = malloc(sizeof(struct dc_mediainfo), M_DEVBUF, M_NOWAIT); 1795 bzero(m, sizeof(struct dc_mediainfo)); 1796 if (l->dc_sym_code == DC_SYM_CODE_100BT) 1797 m->dc_media = IFM_100_TX; 1798 1799 if (l->dc_sym_code == DC_SYM_CODE_100BT_FDX) 1800 m->dc_media = IFM_100_TX|IFM_FDX; 1801 1802 m->dc_gp_len = 2; 1803 m->dc_gp_ptr = (u_int8_t *)&l->dc_sym_gpio_ctl; 1804 1805 m->dc_next = sc->dc_mi; 1806 sc->dc_mi = m; 1807 1808 sc->dc_pmode = DC_PMODE_SYM; 1809 1810 return; 1811 } 1812 1813 static void 1814 dc_decode_leaf_mii(sc, l) 1815 struct dc_softc *sc; 1816 struct dc_eblock_mii *l; 1817 { 1818 u_int8_t *p; 1819 struct dc_mediainfo *m; 1820 1821 m = malloc(sizeof(struct dc_mediainfo), M_DEVBUF, M_NOWAIT); 1822 bzero(m, sizeof(struct dc_mediainfo)); 1823 /* We abuse IFM_AUTO to represent MII. */ 1824 m->dc_media = IFM_AUTO; 1825 m->dc_gp_len = l->dc_gpr_len; 1826 1827 p = (u_int8_t *)l; 1828 p += sizeof(struct dc_eblock_mii); 1829 m->dc_gp_ptr = p; 1830 p += 2 * l->dc_gpr_len; 1831 m->dc_reset_len = *p; 1832 p++; 1833 m->dc_reset_ptr = p; 1834 1835 m->dc_next = sc->dc_mi; 1836 sc->dc_mi = m; 1837 1838 return; 1839 } 1840 1841 static void 1842 dc_read_srom(sc, bits) 1843 struct dc_softc *sc; 1844 int bits; 1845 { 1846 int size; 1847 1848 size = 2 << bits; 1849 sc->dc_srom = malloc(size, M_DEVBUF, M_NOWAIT); 1850 dc_read_eeprom(sc, (caddr_t)sc->dc_srom, 0, (size / 2), 0); 1851 } 1852 1853 static void 1854 dc_parse_21143_srom(sc) 1855 struct dc_softc *sc; 1856 { 1857 struct dc_leaf_hdr *lhdr; 1858 struct dc_eblock_hdr *hdr; 1859 int i, loff; 1860 char *ptr; 1861 1862 loff = sc->dc_srom[27]; 1863 lhdr = (struct dc_leaf_hdr *)&(sc->dc_srom[loff]); 1864 1865 ptr = (char *)lhdr; 1866 ptr += sizeof(struct dc_leaf_hdr) - 1; 1867 for (i = 0; i < lhdr->dc_mcnt; i++) { 1868 hdr = (struct dc_eblock_hdr *)ptr; 1869 switch(hdr->dc_type) { 1870 case DC_EBLOCK_MII: 1871 dc_decode_leaf_mii(sc, (struct dc_eblock_mii *)hdr); 1872 break; 1873 case DC_EBLOCK_SIA: 1874 dc_decode_leaf_sia(sc, (struct dc_eblock_sia *)hdr); 1875 break; 1876 case DC_EBLOCK_SYM: 1877 dc_decode_leaf_sym(sc, (struct dc_eblock_sym *)hdr); 1878 break; 1879 default: 1880 /* Don't care. Yet. */ 1881 break; 1882 } 1883 ptr += (hdr->dc_len & 0x7F); 1884 ptr++; 1885 } 1886 1887 return; 1888 } 1889 1890 /* 1891 * Attach the interface. Allocate softc structures, do ifmedia 1892 * setup and ethernet/BPF attach. 1893 */ 1894 static int 1895 dc_attach(dev) 1896 device_t dev; 1897 { 1898 int tmp = 0; 1899 u_char eaddr[ETHER_ADDR_LEN]; 1900 u_int32_t command; 1901 struct dc_softc *sc; 1902 struct ifnet *ifp; 1903 u_int32_t revision; 1904 int unit, error = 0, rid, mac_offset; 1905 u_int8_t *mac; 1906 1907 sc = device_get_softc(dev); 1908 unit = device_get_unit(dev); 1909 bzero(sc, sizeof(struct dc_softc)); 1910 1911 mtx_init(&sc->dc_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 1912 MTX_DEF | MTX_RECURSE); 1913 1914 /* 1915 * Handle power management nonsense. 1916 */ 1917 dc_acpi(dev); 1918 1919 /* 1920 * Map control/status registers. 1921 */ 1922 pci_enable_busmaster(dev); 1923 pci_enable_io(dev, SYS_RES_IOPORT); 1924 pci_enable_io(dev, SYS_RES_MEMORY); 1925 command = pci_read_config(dev, PCIR_COMMAND, 4); 1926 1927 #ifdef DC_USEIOSPACE 1928 if (!(command & PCIM_CMD_PORTEN)) { 1929 printf("dc%d: failed to enable I/O ports!\n", unit); 1930 error = ENXIO; 1931 goto fail; 1932 } 1933 #else 1934 if (!(command & PCIM_CMD_MEMEN)) { 1935 printf("dc%d: failed to enable memory mapping!\n", unit); 1936 error = ENXIO; 1937 goto fail; 1938 } 1939 #endif 1940 1941 rid = DC_RID; 1942 sc->dc_res = bus_alloc_resource(dev, DC_RES, &rid, 1943 0, ~0, 1, RF_ACTIVE); 1944 1945 if (sc->dc_res == NULL) { 1946 printf("dc%d: couldn't map ports/memory\n", unit); 1947 error = ENXIO; 1948 goto fail; 1949 } 1950 1951 sc->dc_btag = rman_get_bustag(sc->dc_res); 1952 sc->dc_bhandle = rman_get_bushandle(sc->dc_res); 1953 1954 /* Need this info to decide on a chip type. */ 1955 sc->dc_info = dc_devtype(dev); 1956 revision = pci_read_config(dev, DC_PCI_CFRV, 4) & 0x000000FF; 1957 1958 /* Get the eeprom width, but PNIC and XIRCOM have diff eeprom */ 1959 if (sc->dc_info->dc_did != DC_DEVICEID_82C168 && 1960 sc->dc_info->dc_did != DC_DEVICEID_X3201) 1961 dc_eeprom_width(sc); 1962 1963 switch(sc->dc_info->dc_did) { 1964 case DC_DEVICEID_21143: 1965 sc->dc_type = DC_TYPE_21143; 1966 sc->dc_flags |= DC_TX_POLL|DC_TX_USE_TX_INTR; 1967 sc->dc_flags |= DC_REDUCED_MII_POLL; 1968 /* Save EEPROM contents so we can parse them later. */ 1969 dc_read_srom(sc, sc->dc_romwidth); 1970 break; 1971 case DC_DEVICEID_DM9009: 1972 case DC_DEVICEID_DM9100: 1973 case DC_DEVICEID_DM9102: 1974 sc->dc_type = DC_TYPE_DM9102; 1975 sc->dc_flags |= DC_TX_COALESCE|DC_TX_INTR_ALWAYS; 1976 sc->dc_flags |= DC_REDUCED_MII_POLL|DC_TX_STORENFWD; 1977 sc->dc_pmode = DC_PMODE_MII; 1978 /* Increase the latency timer value. */ 1979 command = pci_read_config(dev, DC_PCI_CFLT, 4); 1980 command &= 0xFFFF00FF; 1981 command |= 0x00008000; 1982 pci_write_config(dev, DC_PCI_CFLT, command, 4); 1983 break; 1984 case DC_DEVICEID_AL981: 1985 sc->dc_type = DC_TYPE_AL981; 1986 sc->dc_flags |= DC_TX_USE_TX_INTR; 1987 sc->dc_flags |= DC_TX_ADMTEK_WAR; 1988 sc->dc_pmode = DC_PMODE_MII; 1989 dc_read_srom(sc, sc->dc_romwidth); 1990 break; 1991 case DC_DEVICEID_AN985: 1992 case DC_DEVICEID_FE2500: 1993 case DC_DEVICEID_EN2242: 1994 case DC_DEVICEID_HAWKING_PN672TX: 1995 sc->dc_type = DC_TYPE_AN985; 1996 sc->dc_flags |= DC_TX_USE_TX_INTR; 1997 sc->dc_flags |= DC_TX_ADMTEK_WAR; 1998 sc->dc_pmode = DC_PMODE_MII; 1999 dc_read_srom(sc, sc->dc_romwidth); 2000 break; 2001 case DC_DEVICEID_98713: 2002 case DC_DEVICEID_98713_CP: 2003 if (revision < DC_REVISION_98713A) { 2004 sc->dc_type = DC_TYPE_98713; 2005 } 2006 if (revision >= DC_REVISION_98713A) { 2007 sc->dc_type = DC_TYPE_98713A; 2008 sc->dc_flags |= DC_21143_NWAY; 2009 } 2010 sc->dc_flags |= DC_REDUCED_MII_POLL; 2011 sc->dc_flags |= DC_TX_POLL|DC_TX_USE_TX_INTR; 2012 break; 2013 case DC_DEVICEID_987x5: 2014 case DC_DEVICEID_EN1217: 2015 /* 2016 * Macronix MX98715AEC-C/D/E parts have only a 2017 * 128-bit hash table. We need to deal with these 2018 * in the same manner as the PNIC II so that we 2019 * get the right number of bits out of the 2020 * CRC routine. 2021 */ 2022 if (revision >= DC_REVISION_98715AEC_C && 2023 revision < DC_REVISION_98725) 2024 sc->dc_flags |= DC_128BIT_HASH; 2025 sc->dc_type = DC_TYPE_987x5; 2026 sc->dc_flags |= DC_TX_POLL|DC_TX_USE_TX_INTR; 2027 sc->dc_flags |= DC_REDUCED_MII_POLL|DC_21143_NWAY; 2028 break; 2029 case DC_DEVICEID_98727: 2030 sc->dc_type = DC_TYPE_987x5; 2031 sc->dc_flags |= DC_TX_POLL|DC_TX_USE_TX_INTR; 2032 sc->dc_flags |= DC_REDUCED_MII_POLL|DC_21143_NWAY; 2033 break; 2034 case DC_DEVICEID_82C115: 2035 sc->dc_type = DC_TYPE_PNICII; 2036 sc->dc_flags |= DC_TX_POLL|DC_TX_USE_TX_INTR|DC_128BIT_HASH; 2037 sc->dc_flags |= DC_REDUCED_MII_POLL|DC_21143_NWAY; 2038 break; 2039 case DC_DEVICEID_82C168: 2040 sc->dc_type = DC_TYPE_PNIC; 2041 sc->dc_flags |= DC_TX_STORENFWD|DC_TX_INTR_ALWAYS; 2042 sc->dc_flags |= DC_PNIC_RX_BUG_WAR; 2043 sc->dc_pnic_rx_buf = malloc(DC_RXLEN * 5, M_DEVBUF, M_NOWAIT); 2044 if (revision < DC_REVISION_82C169) 2045 sc->dc_pmode = DC_PMODE_SYM; 2046 break; 2047 case DC_DEVICEID_AX88140A: 2048 sc->dc_type = DC_TYPE_ASIX; 2049 sc->dc_flags |= DC_TX_USE_TX_INTR|DC_TX_INTR_FIRSTFRAG; 2050 sc->dc_flags |= DC_REDUCED_MII_POLL; 2051 sc->dc_pmode = DC_PMODE_MII; 2052 break; 2053 case DC_DEVICEID_X3201: 2054 sc->dc_type = DC_TYPE_XIRCOM; 2055 sc->dc_flags |= DC_TX_INTR_ALWAYS | DC_TX_COALESCE | 2056 DC_TX_ALIGN; 2057 /* 2058 * We don't actually need to coalesce, but we're doing 2059 * it to obtain a double word aligned buffer. 2060 * The DC_TX_COALESCE flag is required. 2061 */ 2062 sc->dc_pmode = DC_PMODE_MII; 2063 break; 2064 case DC_DEVICEID_RS7112: 2065 sc->dc_type = DC_TYPE_CONEXANT; 2066 sc->dc_flags |= DC_TX_INTR_ALWAYS; 2067 sc->dc_flags |= DC_REDUCED_MII_POLL; 2068 sc->dc_pmode = DC_PMODE_MII; 2069 dc_read_srom(sc, sc->dc_romwidth); 2070 break; 2071 default: 2072 printf("dc%d: unknown device: %x\n", sc->dc_unit, 2073 sc->dc_info->dc_did); 2074 break; 2075 } 2076 2077 /* Save the cache line size. */ 2078 if (DC_IS_DAVICOM(sc)) 2079 sc->dc_cachesize = 0; 2080 else 2081 sc->dc_cachesize = pci_read_config(dev, 2082 DC_PCI_CFLT, 4) & 0xFF; 2083 2084 /* Reset the adapter. */ 2085 dc_reset(sc); 2086 2087 /* Take 21143 out of snooze mode */ 2088 if (DC_IS_INTEL(sc) || DC_IS_XIRCOM(sc)) { 2089 command = pci_read_config(dev, DC_PCI_CFDD, 4); 2090 command &= ~(DC_CFDD_SNOOZE_MODE|DC_CFDD_SLEEP_MODE); 2091 pci_write_config(dev, DC_PCI_CFDD, command, 4); 2092 } 2093 2094 /* 2095 * Try to learn something about the supported media. 2096 * We know that ASIX and ADMtek and Davicom devices 2097 * will *always* be using MII media, so that's a no-brainer. 2098 * The tricky ones are the Macronix/PNIC II and the 2099 * Intel 21143. 2100 */ 2101 if (DC_IS_INTEL(sc)) 2102 dc_parse_21143_srom(sc); 2103 else if (DC_IS_MACRONIX(sc) || DC_IS_PNICII(sc)) { 2104 if (sc->dc_type == DC_TYPE_98713) 2105 sc->dc_pmode = DC_PMODE_MII; 2106 else 2107 sc->dc_pmode = DC_PMODE_SYM; 2108 } else if (!sc->dc_pmode) 2109 sc->dc_pmode = DC_PMODE_MII; 2110 2111 /* 2112 * Get station address from the EEPROM. 2113 */ 2114 switch(sc->dc_type) { 2115 case DC_TYPE_98713: 2116 case DC_TYPE_98713A: 2117 case DC_TYPE_987x5: 2118 case DC_TYPE_PNICII: 2119 dc_read_eeprom(sc, (caddr_t)&mac_offset, 2120 (DC_EE_NODEADDR_OFFSET / 2), 1, 0); 2121 dc_read_eeprom(sc, (caddr_t)&eaddr, (mac_offset / 2), 3, 0); 2122 break; 2123 case DC_TYPE_PNIC: 2124 dc_read_eeprom(sc, (caddr_t)&eaddr, 0, 3, 1); 2125 break; 2126 case DC_TYPE_DM9102: 2127 case DC_TYPE_21143: 2128 case DC_TYPE_ASIX: 2129 dc_read_eeprom(sc, (caddr_t)&eaddr, DC_EE_NODEADDR, 3, 0); 2130 break; 2131 case DC_TYPE_AL981: 2132 case DC_TYPE_AN985: 2133 bcopy(&sc->dc_srom[DC_AL_EE_NODEADDR], (caddr_t)&eaddr, 2134 ETHER_ADDR_LEN); 2135 dc_read_eeprom(sc, (caddr_t)&eaddr, DC_AL_EE_NODEADDR, 3, 0); 2136 break; 2137 case DC_TYPE_CONEXANT: 2138 bcopy(sc->dc_srom + DC_CONEXANT_EE_NODEADDR, &eaddr, 6); 2139 break; 2140 case DC_TYPE_XIRCOM: 2141 /* The MAC comes from the CIS */ 2142 mac = pci_get_ether(dev); 2143 if (!mac) { 2144 device_printf(dev, "No station address in CIS!\n"); 2145 bus_release_resource(dev, DC_RES, DC_RID, sc->dc_res); 2146 error = ENXIO; 2147 goto fail; 2148 } 2149 bcopy(mac, eaddr, ETHER_ADDR_LEN); 2150 break; 2151 default: 2152 dc_read_eeprom(sc, (caddr_t)&eaddr, DC_EE_NODEADDR, 3, 0); 2153 break; 2154 } 2155 2156 /* 2157 * A 21143 or clone chip was detected. Inform the world. 2158 */ 2159 printf("dc%d: Ethernet address: %6D\n", unit, eaddr, ":"); 2160 2161 sc->dc_unit = unit; 2162 bcopy(eaddr, (char *)&sc->arpcom.ac_enaddr, ETHER_ADDR_LEN); 2163 2164 sc->dc_ldata = contigmalloc(sizeof(struct dc_list_data), M_DEVBUF, 2165 M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0); 2166 2167 if (sc->dc_ldata == NULL) { 2168 printf("dc%d: no memory for list buffers!\n", unit); 2169 bus_release_resource(dev, DC_RES, DC_RID, sc->dc_res); 2170 error = ENXIO; 2171 goto fail; 2172 } 2173 2174 bzero(sc->dc_ldata, sizeof(struct dc_list_data)); 2175 2176 ifp = &sc->arpcom.ac_if; 2177 ifp->if_softc = sc; 2178 ifp->if_unit = unit; 2179 ifp->if_name = "dc"; 2180 /* XXX: bleah, MTU gets overwritten in ether_ifattach() */ 2181 ifp->if_mtu = ETHERMTU; 2182 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 2183 ifp->if_ioctl = dc_ioctl; 2184 ifp->if_output = ether_output; 2185 ifp->if_start = dc_start; 2186 ifp->if_watchdog = dc_watchdog; 2187 ifp->if_init = dc_init; 2188 ifp->if_baudrate = 10000000; 2189 ifp->if_snd.ifq_maxlen = DC_TX_LIST_CNT - 1; 2190 2191 /* 2192 * Do MII setup. If this is a 21143, check for a PHY on the 2193 * MII bus after applying any necessary fixups to twiddle the 2194 * GPIO bits. If we don't end up finding a PHY, restore the 2195 * old selection (SIA only or SIA/SYM) and attach the dcphy 2196 * driver instead. 2197 */ 2198 if (DC_IS_INTEL(sc)) { 2199 dc_apply_fixup(sc, IFM_AUTO); 2200 tmp = sc->dc_pmode; 2201 sc->dc_pmode = DC_PMODE_MII; 2202 } 2203 2204 error = mii_phy_probe(dev, &sc->dc_miibus, 2205 dc_ifmedia_upd, dc_ifmedia_sts); 2206 2207 if (error && DC_IS_INTEL(sc)) { 2208 sc->dc_pmode = tmp; 2209 if (sc->dc_pmode != DC_PMODE_SIA) 2210 sc->dc_pmode = DC_PMODE_SYM; 2211 sc->dc_flags |= DC_21143_NWAY; 2212 mii_phy_probe(dev, &sc->dc_miibus, 2213 dc_ifmedia_upd, dc_ifmedia_sts); 2214 /* 2215 * For non-MII cards, we need to have the 21143 2216 * drive the LEDs. Except there are some systems 2217 * like the NEC VersaPro NoteBook PC which have no 2218 * LEDs, and twiddling these bits has adverse effects 2219 * on them. (I.e. you suddenly can't get a link.) 2220 */ 2221 if (pci_read_config(dev, DC_PCI_CSID, 4) != 0x80281033) 2222 sc->dc_flags |= DC_TULIP_LEDS; 2223 error = 0; 2224 } 2225 2226 if (error) { 2227 printf("dc%d: MII without any PHY!\n", sc->dc_unit); 2228 bus_release_resource(dev, DC_RES, DC_RID, sc->dc_res); 2229 error = ENXIO; 2230 goto fail; 2231 } 2232 2233 if (DC_IS_XIRCOM(sc)) { 2234 /* 2235 * setup General Purpose Port mode and data so the tulip 2236 * can talk to the MII. 2237 */ 2238 CSR_WRITE_4(sc, DC_SIAGP, DC_SIAGP_WRITE_EN | DC_SIAGP_INT1_EN | 2239 DC_SIAGP_MD_GP2_OUTPUT | DC_SIAGP_MD_GP0_OUTPUT); 2240 DELAY(10); 2241 CSR_WRITE_4(sc, DC_SIAGP, DC_SIAGP_INT1_EN | 2242 DC_SIAGP_MD_GP2_OUTPUT | DC_SIAGP_MD_GP0_OUTPUT); 2243 DELAY(10); 2244 } 2245 2246 if (DC_IS_ADMTEK(sc)) { 2247 /* 2248 * Set automatic TX underrun recovery for the ADMtek chips 2249 */ 2250 DC_SETBIT(sc, DC_AL_CR, DC_AL_CR_ATUR); 2251 } 2252 2253 /* 2254 * Tell the upper layer(s) we support long frames. 2255 */ 2256 ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header); 2257 ifp->if_capabilities |= IFCAP_VLAN_MTU; 2258 2259 callout_init(&sc->dc_stat_ch, IS_MPSAFE); 2260 2261 #ifdef SRM_MEDIA 2262 sc->dc_srm_media = 0; 2263 2264 /* Remember the SRM console media setting */ 2265 if (DC_IS_INTEL(sc)) { 2266 command = pci_read_config(dev, DC_PCI_CFDD, 4); 2267 command &= ~(DC_CFDD_SNOOZE_MODE|DC_CFDD_SLEEP_MODE); 2268 switch ((command >> 8) & 0xff) { 2269 case 3: 2270 sc->dc_srm_media = IFM_10_T; 2271 break; 2272 case 4: 2273 sc->dc_srm_media = IFM_10_T | IFM_FDX; 2274 break; 2275 case 5: 2276 sc->dc_srm_media = IFM_100_TX; 2277 break; 2278 case 6: 2279 sc->dc_srm_media = IFM_100_TX | IFM_FDX; 2280 break; 2281 } 2282 if (sc->dc_srm_media) 2283 sc->dc_srm_media |= IFM_ACTIVE | IFM_ETHER; 2284 } 2285 #endif 2286 2287 /* 2288 * Call MI attach routine. 2289 */ 2290 ether_ifattach(ifp, eaddr); 2291 2292 /* Allocate interrupt */ 2293 rid = 0; 2294 sc->dc_irq = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, 0, ~0, 1, 2295 RF_SHAREABLE | RF_ACTIVE); 2296 2297 if (sc->dc_irq == NULL) { 2298 printf("dc%d: couldn't map interrupt\n", unit); 2299 bus_release_resource(dev, DC_RES, DC_RID, sc->dc_res); 2300 error = ENXIO; 2301 goto fail; 2302 } 2303 2304 error = bus_setup_intr(dev, sc->dc_irq, INTR_TYPE_NET | 2305 (IS_MPSAFE ? INTR_MPSAFE : 0), 2306 dc_intr, sc, &sc->dc_intrhand); 2307 2308 if (error) { 2309 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->dc_irq); 2310 bus_release_resource(dev, DC_RES, DC_RID, sc->dc_res); 2311 printf("dc%d: couldn't set up irq\n", unit); 2312 } 2313 2314 fail: 2315 if (error != 0) 2316 mtx_destroy(&sc->dc_mtx); 2317 return (error); 2318 } 2319 2320 static int 2321 dc_detach(dev) 2322 device_t dev; 2323 { 2324 struct dc_softc *sc; 2325 struct ifnet *ifp; 2326 struct dc_mediainfo *m; 2327 2328 sc = device_get_softc(dev); 2329 2330 DC_LOCK(sc); 2331 2332 ifp = &sc->arpcom.ac_if; 2333 2334 dc_stop(sc); 2335 ether_ifdetach(ifp); 2336 2337 bus_generic_detach(dev); 2338 device_delete_child(dev, sc->dc_miibus); 2339 2340 bus_teardown_intr(dev, sc->dc_irq, sc->dc_intrhand); 2341 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->dc_irq); 2342 bus_release_resource(dev, DC_RES, DC_RID, sc->dc_res); 2343 2344 contigfree(sc->dc_ldata, sizeof(struct dc_list_data), M_DEVBUF); 2345 if (sc->dc_pnic_rx_buf != NULL) 2346 free(sc->dc_pnic_rx_buf, M_DEVBUF); 2347 2348 while(sc->dc_mi != NULL) { 2349 m = sc->dc_mi->dc_next; 2350 free(sc->dc_mi, M_DEVBUF); 2351 sc->dc_mi = m; 2352 } 2353 free(sc->dc_srom, M_DEVBUF); 2354 2355 DC_UNLOCK(sc); 2356 mtx_destroy(&sc->dc_mtx); 2357 2358 return(0); 2359 } 2360 2361 /* 2362 * Initialize the transmit descriptors. 2363 */ 2364 static int 2365 dc_list_tx_init(sc) 2366 struct dc_softc *sc; 2367 { 2368 struct dc_chain_data *cd; 2369 struct dc_list_data *ld; 2370 int i, nexti; 2371 2372 cd = &sc->dc_cdata; 2373 ld = sc->dc_ldata; 2374 for (i = 0; i < DC_TX_LIST_CNT; i++) { 2375 nexti = (i == (DC_TX_LIST_CNT - 1)) ? 0 : i+1; 2376 ld->dc_tx_list[i].dc_next = vtophys(&ld->dc_tx_list[nexti]); 2377 cd->dc_tx_chain[i] = NULL; 2378 ld->dc_tx_list[i].dc_data = 0; 2379 ld->dc_tx_list[i].dc_ctl = 0; 2380 } 2381 2382 cd->dc_tx_prod = cd->dc_tx_cons = cd->dc_tx_cnt = 0; 2383 2384 return(0); 2385 } 2386 2387 2388 /* 2389 * Initialize the RX descriptors and allocate mbufs for them. Note that 2390 * we arrange the descriptors in a closed ring, so that the last descriptor 2391 * points back to the first. 2392 */ 2393 static int 2394 dc_list_rx_init(sc) 2395 struct dc_softc *sc; 2396 { 2397 struct dc_chain_data *cd; 2398 struct dc_list_data *ld; 2399 int i, nexti; 2400 2401 cd = &sc->dc_cdata; 2402 ld = sc->dc_ldata; 2403 2404 for (i = 0; i < DC_RX_LIST_CNT; i++) { 2405 if (dc_newbuf(sc, i, NULL) == ENOBUFS) 2406 return(ENOBUFS); 2407 nexti = (i == (DC_RX_LIST_CNT - 1)) ? 0 : i+1; 2408 ld->dc_rx_list[i].dc_next = vtophys(&ld->dc_rx_list[nexti]); 2409 } 2410 2411 cd->dc_rx_prod = 0; 2412 2413 return(0); 2414 } 2415 2416 /* 2417 * Initialize an RX descriptor and attach an MBUF cluster. 2418 */ 2419 static int 2420 dc_newbuf(sc, i, m) 2421 struct dc_softc *sc; 2422 int i; 2423 struct mbuf *m; 2424 { 2425 struct mbuf *m_new = NULL; 2426 struct dc_desc *c; 2427 2428 c = &sc->dc_ldata->dc_rx_list[i]; 2429 2430 if (m == NULL) { 2431 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 2432 if (m_new == NULL) 2433 return(ENOBUFS); 2434 2435 MCLGET(m_new, M_DONTWAIT); 2436 if (!(m_new->m_flags & M_EXT)) { 2437 m_freem(m_new); 2438 return(ENOBUFS); 2439 } 2440 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 2441 } else { 2442 m_new = m; 2443 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 2444 m_new->m_data = m_new->m_ext.ext_buf; 2445 } 2446 2447 m_adj(m_new, sizeof(u_int64_t)); 2448 2449 /* 2450 * If this is a PNIC chip, zero the buffer. This is part 2451 * of the workaround for the receive bug in the 82c168 and 2452 * 82c169 chips. 2453 */ 2454 if (sc->dc_flags & DC_PNIC_RX_BUG_WAR) 2455 bzero((char *)mtod(m_new, char *), m_new->m_len); 2456 2457 sc->dc_cdata.dc_rx_chain[i] = m_new; 2458 c->dc_data = vtophys(mtod(m_new, caddr_t)); 2459 c->dc_ctl = DC_RXCTL_RLINK | DC_RXLEN; 2460 c->dc_status = DC_RXSTAT_OWN; 2461 2462 return(0); 2463 } 2464 2465 /* 2466 * Grrrrr. 2467 * The PNIC chip has a terrible bug in it that manifests itself during 2468 * periods of heavy activity. The exact mode of failure if difficult to 2469 * pinpoint: sometimes it only happens in promiscuous mode, sometimes it 2470 * will happen on slow machines. The bug is that sometimes instead of 2471 * uploading one complete frame during reception, it uploads what looks 2472 * like the entire contents of its FIFO memory. The frame we want is at 2473 * the end of the whole mess, but we never know exactly how much data has 2474 * been uploaded, so salvaging the frame is hard. 2475 * 2476 * There is only one way to do it reliably, and it's disgusting. 2477 * Here's what we know: 2478 * 2479 * - We know there will always be somewhere between one and three extra 2480 * descriptors uploaded. 2481 * 2482 * - We know the desired received frame will always be at the end of the 2483 * total data upload. 2484 * 2485 * - We know the size of the desired received frame because it will be 2486 * provided in the length field of the status word in the last descriptor. 2487 * 2488 * Here's what we do: 2489 * 2490 * - When we allocate buffers for the receive ring, we bzero() them. 2491 * This means that we know that the buffer contents should be all 2492 * zeros, except for data uploaded by the chip. 2493 * 2494 * - We also force the PNIC chip to upload frames that include the 2495 * ethernet CRC at the end. 2496 * 2497 * - We gather all of the bogus frame data into a single buffer. 2498 * 2499 * - We then position a pointer at the end of this buffer and scan 2500 * backwards until we encounter the first non-zero byte of data. 2501 * This is the end of the received frame. We know we will encounter 2502 * some data at the end of the frame because the CRC will always be 2503 * there, so even if the sender transmits a packet of all zeros, 2504 * we won't be fooled. 2505 * 2506 * - We know the size of the actual received frame, so we subtract 2507 * that value from the current pointer location. This brings us 2508 * to the start of the actual received packet. 2509 * 2510 * - We copy this into an mbuf and pass it on, along with the actual 2511 * frame length. 2512 * 2513 * The performance hit is tremendous, but it beats dropping frames all 2514 * the time. 2515 */ 2516 2517 #define DC_WHOLEFRAME (DC_RXSTAT_FIRSTFRAG|DC_RXSTAT_LASTFRAG) 2518 static void 2519 dc_pnic_rx_bug_war(sc, idx) 2520 struct dc_softc *sc; 2521 int idx; 2522 { 2523 struct dc_desc *cur_rx; 2524 struct dc_desc *c = NULL; 2525 struct mbuf *m = NULL; 2526 unsigned char *ptr; 2527 int i, total_len; 2528 u_int32_t rxstat = 0; 2529 2530 i = sc->dc_pnic_rx_bug_save; 2531 cur_rx = &sc->dc_ldata->dc_rx_list[idx]; 2532 ptr = sc->dc_pnic_rx_buf; 2533 bzero(ptr, sizeof(DC_RXLEN * 5)); 2534 2535 /* Copy all the bytes from the bogus buffers. */ 2536 while (1) { 2537 c = &sc->dc_ldata->dc_rx_list[i]; 2538 rxstat = c->dc_status; 2539 m = sc->dc_cdata.dc_rx_chain[i]; 2540 bcopy(mtod(m, char *), ptr, DC_RXLEN); 2541 ptr += DC_RXLEN; 2542 /* If this is the last buffer, break out. */ 2543 if (i == idx || rxstat & DC_RXSTAT_LASTFRAG) 2544 break; 2545 dc_newbuf(sc, i, m); 2546 DC_INC(i, DC_RX_LIST_CNT); 2547 } 2548 2549 /* Find the length of the actual receive frame. */ 2550 total_len = DC_RXBYTES(rxstat); 2551 2552 /* Scan backwards until we hit a non-zero byte. */ 2553 while(*ptr == 0x00) 2554 ptr--; 2555 2556 /* Round off. */ 2557 if ((uintptr_t)(ptr) & 0x3) 2558 ptr -= 1; 2559 2560 /* Now find the start of the frame. */ 2561 ptr -= total_len; 2562 if (ptr < sc->dc_pnic_rx_buf) 2563 ptr = sc->dc_pnic_rx_buf; 2564 2565 /* 2566 * Now copy the salvaged frame to the last mbuf and fake up 2567 * the status word to make it look like a successful 2568 * frame reception. 2569 */ 2570 dc_newbuf(sc, i, m); 2571 bcopy(ptr, mtod(m, char *), total_len); 2572 cur_rx->dc_status = rxstat | DC_RXSTAT_FIRSTFRAG; 2573 2574 return; 2575 } 2576 2577 /* 2578 * This routine searches the RX ring for dirty descriptors in the 2579 * event that the rxeof routine falls out of sync with the chip's 2580 * current descriptor pointer. This may happen sometimes as a result 2581 * of a "no RX buffer available" condition that happens when the chip 2582 * consumes all of the RX buffers before the driver has a chance to 2583 * process the RX ring. This routine may need to be called more than 2584 * once to bring the driver back in sync with the chip, however we 2585 * should still be getting RX DONE interrupts to drive the search 2586 * for new packets in the RX ring, so we should catch up eventually. 2587 */ 2588 static int 2589 dc_rx_resync(sc) 2590 struct dc_softc *sc; 2591 { 2592 int i, pos; 2593 struct dc_desc *cur_rx; 2594 2595 pos = sc->dc_cdata.dc_rx_prod; 2596 2597 for (i = 0; i < DC_RX_LIST_CNT; i++) { 2598 cur_rx = &sc->dc_ldata->dc_rx_list[pos]; 2599 if (!(cur_rx->dc_status & DC_RXSTAT_OWN)) 2600 break; 2601 DC_INC(pos, DC_RX_LIST_CNT); 2602 } 2603 2604 /* If the ring really is empty, then just return. */ 2605 if (i == DC_RX_LIST_CNT) 2606 return(0); 2607 2608 /* We've fallen behing the chip: catch it. */ 2609 sc->dc_cdata.dc_rx_prod = pos; 2610 2611 return(EAGAIN); 2612 } 2613 2614 /* 2615 * A frame has been uploaded: pass the resulting mbuf chain up to 2616 * the higher level protocols. 2617 */ 2618 static void 2619 dc_rxeof(sc) 2620 struct dc_softc *sc; 2621 { 2622 struct mbuf *m; 2623 struct ifnet *ifp; 2624 struct dc_desc *cur_rx; 2625 int i, total_len = 0; 2626 u_int32_t rxstat; 2627 2628 ifp = &sc->arpcom.ac_if; 2629 i = sc->dc_cdata.dc_rx_prod; 2630 2631 while(!(sc->dc_ldata->dc_rx_list[i].dc_status & DC_RXSTAT_OWN)) { 2632 2633 #ifdef DEVICE_POLLING 2634 if (ifp->if_flags & IFF_POLLING) { 2635 if (sc->rxcycles <= 0) 2636 break; 2637 sc->rxcycles--; 2638 } 2639 #endif /* DEVICE_POLLING */ 2640 cur_rx = &sc->dc_ldata->dc_rx_list[i]; 2641 rxstat = cur_rx->dc_status; 2642 m = sc->dc_cdata.dc_rx_chain[i]; 2643 total_len = DC_RXBYTES(rxstat); 2644 2645 if (sc->dc_flags & DC_PNIC_RX_BUG_WAR) { 2646 if ((rxstat & DC_WHOLEFRAME) != DC_WHOLEFRAME) { 2647 if (rxstat & DC_RXSTAT_FIRSTFRAG) 2648 sc->dc_pnic_rx_bug_save = i; 2649 if ((rxstat & DC_RXSTAT_LASTFRAG) == 0) { 2650 DC_INC(i, DC_RX_LIST_CNT); 2651 continue; 2652 } 2653 dc_pnic_rx_bug_war(sc, i); 2654 rxstat = cur_rx->dc_status; 2655 total_len = DC_RXBYTES(rxstat); 2656 } 2657 } 2658 2659 sc->dc_cdata.dc_rx_chain[i] = NULL; 2660 2661 /* 2662 * If an error occurs, update stats, clear the 2663 * status word and leave the mbuf cluster in place: 2664 * it should simply get re-used next time this descriptor 2665 * comes up in the ring. However, don't report long 2666 * frames as errors since they could be vlans 2667 */ 2668 if ((rxstat & DC_RXSTAT_RXERR)){ 2669 if (!(rxstat & DC_RXSTAT_GIANT) || 2670 (rxstat & (DC_RXSTAT_CRCERR | DC_RXSTAT_DRIBBLE | 2671 DC_RXSTAT_MIIERE | DC_RXSTAT_COLLSEEN | 2672 DC_RXSTAT_RUNT | DC_RXSTAT_DE))) { 2673 ifp->if_ierrors++; 2674 if (rxstat & DC_RXSTAT_COLLSEEN) 2675 ifp->if_collisions++; 2676 dc_newbuf(sc, i, m); 2677 if (rxstat & DC_RXSTAT_CRCERR) { 2678 DC_INC(i, DC_RX_LIST_CNT); 2679 continue; 2680 } else { 2681 dc_init(sc); 2682 return; 2683 } 2684 } 2685 } 2686 2687 /* No errors; receive the packet. */ 2688 total_len -= ETHER_CRC_LEN; 2689 #ifdef __i386__ 2690 /* 2691 * On the x86 we do not have alignment problems, so try to 2692 * allocate a new buffer for the receive ring, and pass up 2693 * the one where the packet is already, saving the expensive 2694 * copy done in m_devget(). 2695 * If we are on an architecture with alignment problems, or 2696 * if the allocation fails, then use m_devget and leave the 2697 * existing buffer in the receive ring. 2698 */ 2699 if (dc_quick && dc_newbuf(sc, i, NULL) == 0) { 2700 m->m_pkthdr.rcvif = ifp; 2701 m->m_pkthdr.len = m->m_len = total_len; 2702 DC_INC(i, DC_RX_LIST_CNT); 2703 } else 2704 #endif 2705 { 2706 struct mbuf *m0; 2707 2708 m0 = m_devget(mtod(m, char *), total_len, 2709 ETHER_ALIGN, ifp, NULL); 2710 dc_newbuf(sc, i, m); 2711 DC_INC(i, DC_RX_LIST_CNT); 2712 if (m0 == NULL) { 2713 ifp->if_ierrors++; 2714 continue; 2715 } 2716 m = m0; 2717 } 2718 2719 ifp->if_ipackets++; 2720 (*ifp->if_input)(ifp, m); 2721 } 2722 2723 sc->dc_cdata.dc_rx_prod = i; 2724 } 2725 2726 /* 2727 * A frame was downloaded to the chip. It's safe for us to clean up 2728 * the list buffers. 2729 */ 2730 2731 static void 2732 dc_txeof(sc) 2733 struct dc_softc *sc; 2734 { 2735 struct dc_desc *cur_tx = NULL; 2736 struct ifnet *ifp; 2737 int idx; 2738 2739 ifp = &sc->arpcom.ac_if; 2740 2741 /* 2742 * Go through our tx list and free mbufs for those 2743 * frames that have been transmitted. 2744 */ 2745 idx = sc->dc_cdata.dc_tx_cons; 2746 while(idx != sc->dc_cdata.dc_tx_prod) { 2747 u_int32_t txstat; 2748 2749 cur_tx = &sc->dc_ldata->dc_tx_list[idx]; 2750 txstat = cur_tx->dc_status; 2751 2752 if (txstat & DC_TXSTAT_OWN) 2753 break; 2754 2755 if (!(cur_tx->dc_ctl & DC_TXCTL_LASTFRAG) || 2756 cur_tx->dc_ctl & DC_TXCTL_SETUP) { 2757 if (cur_tx->dc_ctl & DC_TXCTL_SETUP) { 2758 /* 2759 * Yes, the PNIC is so brain damaged 2760 * that it will sometimes generate a TX 2761 * underrun error while DMAing the RX 2762 * filter setup frame. If we detect this, 2763 * we have to send the setup frame again, 2764 * or else the filter won't be programmed 2765 * correctly. 2766 */ 2767 if (DC_IS_PNIC(sc)) { 2768 if (txstat & DC_TXSTAT_ERRSUM) 2769 dc_setfilt(sc); 2770 } 2771 sc->dc_cdata.dc_tx_chain[idx] = NULL; 2772 } 2773 sc->dc_cdata.dc_tx_cnt--; 2774 DC_INC(idx, DC_TX_LIST_CNT); 2775 continue; 2776 } 2777 2778 if (DC_IS_XIRCOM(sc) || DC_IS_CONEXANT(sc)) { 2779 /* 2780 * XXX: Why does my Xircom taunt me so? 2781 * For some reason it likes setting the CARRLOST flag 2782 * even when the carrier is there. wtf?!? 2783 * Who knows, but Conexant chips have the 2784 * same problem. Maybe they took lessons 2785 * from Xircom. 2786 */ 2787 if (/*sc->dc_type == DC_TYPE_21143 &&*/ 2788 sc->dc_pmode == DC_PMODE_MII && 2789 ((txstat & 0xFFFF) & ~(DC_TXSTAT_ERRSUM| 2790 DC_TXSTAT_NOCARRIER))) 2791 txstat &= ~DC_TXSTAT_ERRSUM; 2792 } else { 2793 if (/*sc->dc_type == DC_TYPE_21143 &&*/ 2794 sc->dc_pmode == DC_PMODE_MII && 2795 ((txstat & 0xFFFF) & ~(DC_TXSTAT_ERRSUM| 2796 DC_TXSTAT_NOCARRIER|DC_TXSTAT_CARRLOST))) 2797 txstat &= ~DC_TXSTAT_ERRSUM; 2798 } 2799 2800 if (txstat & DC_TXSTAT_ERRSUM) { 2801 ifp->if_oerrors++; 2802 if (txstat & DC_TXSTAT_EXCESSCOLL) 2803 ifp->if_collisions++; 2804 if (txstat & DC_TXSTAT_LATECOLL) 2805 ifp->if_collisions++; 2806 if (!(txstat & DC_TXSTAT_UNDERRUN)) { 2807 dc_init(sc); 2808 return; 2809 } 2810 } 2811 2812 ifp->if_collisions += (txstat & DC_TXSTAT_COLLCNT) >> 3; 2813 2814 ifp->if_opackets++; 2815 if (sc->dc_cdata.dc_tx_chain[idx] != NULL) { 2816 m_freem(sc->dc_cdata.dc_tx_chain[idx]); 2817 sc->dc_cdata.dc_tx_chain[idx] = NULL; 2818 } 2819 2820 sc->dc_cdata.dc_tx_cnt--; 2821 DC_INC(idx, DC_TX_LIST_CNT); 2822 } 2823 2824 if (idx != sc->dc_cdata.dc_tx_cons) { 2825 /* some buffers have been freed */ 2826 sc->dc_cdata.dc_tx_cons = idx; 2827 ifp->if_flags &= ~IFF_OACTIVE; 2828 } 2829 ifp->if_timer = (sc->dc_cdata.dc_tx_cnt == 0) ? 0 : 5; 2830 2831 return; 2832 } 2833 2834 static void 2835 dc_tick(xsc) 2836 void *xsc; 2837 { 2838 struct dc_softc *sc; 2839 struct mii_data *mii; 2840 struct ifnet *ifp; 2841 u_int32_t r; 2842 2843 sc = xsc; 2844 DC_LOCK(sc); 2845 ifp = &sc->arpcom.ac_if; 2846 mii = device_get_softc(sc->dc_miibus); 2847 2848 if (sc->dc_flags & DC_REDUCED_MII_POLL) { 2849 if (sc->dc_flags & DC_21143_NWAY) { 2850 r = CSR_READ_4(sc, DC_10BTSTAT); 2851 if (IFM_SUBTYPE(mii->mii_media_active) == 2852 IFM_100_TX && (r & DC_TSTAT_LS100)) { 2853 sc->dc_link = 0; 2854 mii_mediachg(mii); 2855 } 2856 if (IFM_SUBTYPE(mii->mii_media_active) == 2857 IFM_10_T && (r & DC_TSTAT_LS10)) { 2858 sc->dc_link = 0; 2859 mii_mediachg(mii); 2860 } 2861 if (sc->dc_link == 0) 2862 mii_tick(mii); 2863 } else { 2864 r = CSR_READ_4(sc, DC_ISR); 2865 if ((r & DC_ISR_RX_STATE) == DC_RXSTATE_WAIT && 2866 sc->dc_cdata.dc_tx_cnt == 0) { 2867 mii_tick(mii); 2868 if (!(mii->mii_media_status & IFM_ACTIVE)) 2869 sc->dc_link = 0; 2870 } 2871 } 2872 } else 2873 mii_tick(mii); 2874 2875 /* 2876 * When the init routine completes, we expect to be able to send 2877 * packets right away, and in fact the network code will send a 2878 * gratuitous ARP the moment the init routine marks the interface 2879 * as running. However, even though the MAC may have been initialized, 2880 * there may be a delay of a few seconds before the PHY completes 2881 * autonegotiation and the link is brought up. Any transmissions 2882 * made during that delay will be lost. Dealing with this is tricky: 2883 * we can't just pause in the init routine while waiting for the 2884 * PHY to come ready since that would bring the whole system to 2885 * a screeching halt for several seconds. 2886 * 2887 * What we do here is prevent the TX start routine from sending 2888 * any packets until a link has been established. After the 2889 * interface has been initialized, the tick routine will poll 2890 * the state of the PHY until the IFM_ACTIVE flag is set. Until 2891 * that time, packets will stay in the send queue, and once the 2892 * link comes up, they will be flushed out to the wire. 2893 */ 2894 if (!sc->dc_link && mii->mii_media_status & IFM_ACTIVE && 2895 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) { 2896 sc->dc_link++; 2897 if (ifp->if_snd.ifq_head != NULL) 2898 dc_start(ifp); 2899 } 2900 2901 if (sc->dc_flags & DC_21143_NWAY && !sc->dc_link) 2902 callout_reset(&sc->dc_stat_ch, hz/10, dc_tick, sc); 2903 else 2904 callout_reset(&sc->dc_stat_ch, hz, dc_tick, sc); 2905 2906 DC_UNLOCK(sc); 2907 2908 return; 2909 } 2910 2911 /* 2912 * A transmit underrun has occurred. Back off the transmit threshold, 2913 * or switch to store and forward mode if we have to. 2914 */ 2915 static void 2916 dc_tx_underrun(sc) 2917 struct dc_softc *sc; 2918 { 2919 u_int32_t isr; 2920 int i; 2921 2922 if (DC_IS_DAVICOM(sc)) 2923 dc_init(sc); 2924 2925 if (DC_IS_INTEL(sc)) { 2926 /* 2927 * The real 21143 requires that the transmitter be idle 2928 * in order to change the transmit threshold or store 2929 * and forward state. 2930 */ 2931 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_TX_ON); 2932 2933 for (i = 0; i < DC_TIMEOUT; i++) { 2934 isr = CSR_READ_4(sc, DC_ISR); 2935 if (isr & DC_ISR_TX_IDLE) 2936 break; 2937 DELAY(10); 2938 } 2939 if (i == DC_TIMEOUT) { 2940 printf("dc%d: failed to force tx to idle state\n", 2941 sc->dc_unit); 2942 dc_init(sc); 2943 } 2944 } 2945 2946 printf("dc%d: TX underrun -- ", sc->dc_unit); 2947 sc->dc_txthresh += DC_TXTHRESH_INC; 2948 if (sc->dc_txthresh > DC_TXTHRESH_MAX) { 2949 printf("using store and forward mode\n"); 2950 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_STORENFWD); 2951 } else { 2952 printf("increasing TX threshold\n"); 2953 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_TX_THRESH); 2954 DC_SETBIT(sc, DC_NETCFG, sc->dc_txthresh); 2955 } 2956 2957 if (DC_IS_INTEL(sc)) 2958 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_TX_ON); 2959 2960 return; 2961 } 2962 2963 #ifdef DEVICE_POLLING 2964 static poll_handler_t dc_poll; 2965 2966 static void 2967 dc_poll(struct ifnet *ifp, enum poll_cmd cmd, int count) 2968 { 2969 struct dc_softc *sc = ifp->if_softc; 2970 2971 if (cmd == POLL_DEREGISTER) { /* final call, enable interrupts */ 2972 /* Re-enable interrupts. */ 2973 CSR_WRITE_4(sc, DC_IMR, DC_INTRS); 2974 return; 2975 } 2976 sc->rxcycles = count; 2977 dc_rxeof(sc); 2978 dc_txeof(sc); 2979 if (ifp->if_snd.ifq_head != NULL && !(ifp->if_flags & IFF_OACTIVE)) 2980 dc_start(ifp); 2981 2982 if (cmd == POLL_AND_CHECK_STATUS) { /* also check status register */ 2983 u_int32_t status; 2984 2985 status = CSR_READ_4(sc, DC_ISR); 2986 status &= (DC_ISR_RX_WATDOGTIMEO|DC_ISR_RX_NOBUF| 2987 DC_ISR_TX_NOBUF|DC_ISR_TX_IDLE|DC_ISR_TX_UNDERRUN| 2988 DC_ISR_BUS_ERR); 2989 if (!status) 2990 return; 2991 /* ack what we have */ 2992 CSR_WRITE_4(sc, DC_ISR, status); 2993 2994 if (status & (DC_ISR_RX_WATDOGTIMEO|DC_ISR_RX_NOBUF)) { 2995 u_int32_t r = CSR_READ_4(sc, DC_FRAMESDISCARDED); 2996 ifp->if_ierrors += (r & 0xffff) + ((r >> 17) & 0x7ff); 2997 2998 if (dc_rx_resync(sc)) 2999 dc_rxeof(sc); 3000 } 3001 /* restart transmit unit if necessary */ 3002 if (status & DC_ISR_TX_IDLE && sc->dc_cdata.dc_tx_cnt) 3003 CSR_WRITE_4(sc, DC_TXSTART, 0xFFFFFFFF); 3004 3005 if (status & DC_ISR_TX_UNDERRUN) 3006 dc_tx_underrun(sc); 3007 3008 if (status & DC_ISR_BUS_ERR) { 3009 printf("dc_poll: dc%d bus error\n", sc->dc_unit); 3010 dc_reset(sc); 3011 dc_init(sc); 3012 } 3013 } 3014 } 3015 #endif /* DEVICE_POLLING */ 3016 3017 static void 3018 dc_intr(arg) 3019 void *arg; 3020 { 3021 struct dc_softc *sc; 3022 struct ifnet *ifp; 3023 u_int32_t status; 3024 3025 sc = arg; 3026 3027 if (sc->suspended) { 3028 return; 3029 } 3030 3031 if ((CSR_READ_4(sc, DC_ISR) & DC_INTRS) == 0) 3032 return; 3033 3034 DC_LOCK(sc); 3035 ifp = &sc->arpcom.ac_if; 3036 #ifdef DEVICE_POLLING 3037 if (ifp->if_flags & IFF_POLLING) 3038 goto done; 3039 if (ether_poll_register(dc_poll, ifp)) { /* ok, disable interrupts */ 3040 CSR_WRITE_4(sc, DC_IMR, 0x00000000); 3041 goto done; 3042 } 3043 #endif /* DEVICE_POLLING */ 3044 3045 /* Suppress unwanted interrupts */ 3046 if (!(ifp->if_flags & IFF_UP)) { 3047 if (CSR_READ_4(sc, DC_ISR) & DC_INTRS) 3048 dc_stop(sc); 3049 DC_UNLOCK(sc); 3050 return; 3051 } 3052 3053 /* Disable interrupts. */ 3054 CSR_WRITE_4(sc, DC_IMR, 0x00000000); 3055 3056 while(((status = CSR_READ_4(sc, DC_ISR)) & DC_INTRS) 3057 && status != 0xFFFFFFFF) { 3058 3059 CSR_WRITE_4(sc, DC_ISR, status); 3060 3061 if (status & DC_ISR_RX_OK) { 3062 int curpkts; 3063 curpkts = ifp->if_ipackets; 3064 dc_rxeof(sc); 3065 if (curpkts == ifp->if_ipackets) { 3066 while(dc_rx_resync(sc)) 3067 dc_rxeof(sc); 3068 } 3069 } 3070 3071 if (status & (DC_ISR_TX_OK|DC_ISR_TX_NOBUF)) 3072 dc_txeof(sc); 3073 3074 if (status & DC_ISR_TX_IDLE) { 3075 dc_txeof(sc); 3076 if (sc->dc_cdata.dc_tx_cnt) { 3077 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_TX_ON); 3078 CSR_WRITE_4(sc, DC_TXSTART, 0xFFFFFFFF); 3079 } 3080 } 3081 3082 if (status & DC_ISR_TX_UNDERRUN) 3083 dc_tx_underrun(sc); 3084 3085 if ((status & DC_ISR_RX_WATDOGTIMEO) 3086 || (status & DC_ISR_RX_NOBUF)) { 3087 int curpkts; 3088 curpkts = ifp->if_ipackets; 3089 dc_rxeof(sc); 3090 if (curpkts == ifp->if_ipackets) { 3091 while(dc_rx_resync(sc)) 3092 dc_rxeof(sc); 3093 } 3094 } 3095 3096 if (status & DC_ISR_BUS_ERR) { 3097 dc_reset(sc); 3098 dc_init(sc); 3099 } 3100 } 3101 3102 /* Re-enable interrupts. */ 3103 CSR_WRITE_4(sc, DC_IMR, DC_INTRS); 3104 3105 if (ifp->if_snd.ifq_head != NULL) 3106 dc_start(ifp); 3107 3108 #ifdef DEVICE_POLLING 3109 done: 3110 #endif /* DEVICE_POLLING */ 3111 3112 DC_UNLOCK(sc); 3113 3114 return; 3115 } 3116 3117 /* 3118 * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data 3119 * pointers to the fragment pointers. 3120 */ 3121 static int 3122 dc_encap(sc, m_head, txidx) 3123 struct dc_softc *sc; 3124 struct mbuf *m_head; 3125 u_int32_t *txidx; 3126 { 3127 struct dc_desc *f = NULL; 3128 struct mbuf *m; 3129 int frag, cur, cnt = 0; 3130 3131 /* 3132 * Start packing the mbufs in this chain into 3133 * the fragment pointers. Stop when we run out 3134 * of fragments or hit the end of the mbuf chain. 3135 */ 3136 m = m_head; 3137 cur = frag = *txidx; 3138 3139 for (m = m_head; m != NULL; m = m->m_next) { 3140 if (m->m_len != 0) { 3141 if (sc->dc_flags & DC_TX_ADMTEK_WAR) { 3142 if (*txidx != sc->dc_cdata.dc_tx_prod && 3143 frag == (DC_TX_LIST_CNT - 1)) 3144 return(ENOBUFS); 3145 } 3146 if ((DC_TX_LIST_CNT - 3147 (sc->dc_cdata.dc_tx_cnt + cnt)) < 5) 3148 return(ENOBUFS); 3149 3150 f = &sc->dc_ldata->dc_tx_list[frag]; 3151 f->dc_ctl = DC_TXCTL_TLINK | m->m_len; 3152 if (cnt == 0) { 3153 f->dc_status = 0; 3154 f->dc_ctl |= DC_TXCTL_FIRSTFRAG; 3155 } else 3156 f->dc_status = DC_TXSTAT_OWN; 3157 f->dc_data = vtophys(mtod(m, vm_offset_t)); 3158 cur = frag; 3159 DC_INC(frag, DC_TX_LIST_CNT); 3160 cnt++; 3161 } 3162 } 3163 3164 if (m != NULL) 3165 return(ENOBUFS); 3166 3167 sc->dc_cdata.dc_tx_cnt += cnt; 3168 sc->dc_cdata.dc_tx_chain[cur] = m_head; 3169 sc->dc_ldata->dc_tx_list[cur].dc_ctl |= DC_TXCTL_LASTFRAG; 3170 if (sc->dc_flags & DC_TX_INTR_FIRSTFRAG) 3171 sc->dc_ldata->dc_tx_list[*txidx].dc_ctl |= DC_TXCTL_FINT; 3172 if (sc->dc_flags & DC_TX_INTR_ALWAYS) 3173 sc->dc_ldata->dc_tx_list[cur].dc_ctl |= DC_TXCTL_FINT; 3174 if (sc->dc_flags & DC_TX_USE_TX_INTR && sc->dc_cdata.dc_tx_cnt > 64) 3175 sc->dc_ldata->dc_tx_list[cur].dc_ctl |= DC_TXCTL_FINT; 3176 sc->dc_ldata->dc_tx_list[*txidx].dc_status = DC_TXSTAT_OWN; 3177 *txidx = frag; 3178 3179 return(0); 3180 } 3181 3182 /* 3183 * Coalesce an mbuf chain into a single mbuf cluster buffer. 3184 * Needed for some really badly behaved chips that just can't 3185 * do scatter/gather correctly. 3186 */ 3187 static int 3188 dc_coal(sc, m_head) 3189 struct dc_softc *sc; 3190 struct mbuf **m_head; 3191 { 3192 struct mbuf *m_new, *m; 3193 3194 m = *m_head; 3195 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 3196 if (m_new == NULL) 3197 return(ENOBUFS); 3198 if (m->m_pkthdr.len > MHLEN) { 3199 MCLGET(m_new, M_DONTWAIT); 3200 if (!(m_new->m_flags & M_EXT)) { 3201 m_freem(m_new); 3202 return(ENOBUFS); 3203 } 3204 } 3205 m_copydata(m, 0, m->m_pkthdr.len, mtod(m_new, caddr_t)); 3206 m_new->m_pkthdr.len = m_new->m_len = m->m_pkthdr.len; 3207 m_freem(m); 3208 *m_head = m_new; 3209 3210 return(0); 3211 } 3212 3213 /* 3214 * Main transmit routine. To avoid having to do mbuf copies, we put pointers 3215 * to the mbuf data regions directly in the transmit lists. We also save a 3216 * copy of the pointers since the transmit list fragment pointers are 3217 * physical addresses. 3218 */ 3219 3220 static void 3221 dc_start(ifp) 3222 struct ifnet *ifp; 3223 { 3224 struct dc_softc *sc; 3225 struct mbuf *m_head = NULL; 3226 int idx; 3227 3228 sc = ifp->if_softc; 3229 3230 DC_LOCK(sc); 3231 3232 if (!sc->dc_link && ifp->if_snd.ifq_len < 10) { 3233 DC_UNLOCK(sc); 3234 return; 3235 } 3236 3237 if (ifp->if_flags & IFF_OACTIVE) { 3238 DC_UNLOCK(sc); 3239 return; 3240 } 3241 3242 idx = sc->dc_cdata.dc_tx_prod; 3243 3244 while(sc->dc_cdata.dc_tx_chain[idx] == NULL) { 3245 IF_DEQUEUE(&ifp->if_snd, m_head); 3246 if (m_head == NULL) 3247 break; 3248 3249 if (sc->dc_flags & DC_TX_COALESCE && 3250 (m_head->m_next != NULL || 3251 sc->dc_flags & DC_TX_ALIGN)) { 3252 if (dc_coal(sc, &m_head)) { 3253 IF_PREPEND(&ifp->if_snd, m_head); 3254 ifp->if_flags |= IFF_OACTIVE; 3255 break; 3256 } 3257 } 3258 3259 if (dc_encap(sc, m_head, &idx)) { 3260 IF_PREPEND(&ifp->if_snd, m_head); 3261 ifp->if_flags |= IFF_OACTIVE; 3262 break; 3263 } 3264 3265 /* 3266 * If there's a BPF listener, bounce a copy of this frame 3267 * to him. 3268 */ 3269 BPF_MTAP(ifp, m_head); 3270 3271 if (sc->dc_flags & DC_TX_ONE) { 3272 ifp->if_flags |= IFF_OACTIVE; 3273 break; 3274 } 3275 } 3276 3277 /* Transmit */ 3278 sc->dc_cdata.dc_tx_prod = idx; 3279 if (!(sc->dc_flags & DC_TX_POLL)) 3280 CSR_WRITE_4(sc, DC_TXSTART, 0xFFFFFFFF); 3281 3282 /* 3283 * Set a timeout in case the chip goes out to lunch. 3284 */ 3285 ifp->if_timer = 5; 3286 3287 DC_UNLOCK(sc); 3288 3289 return; 3290 } 3291 3292 static void 3293 dc_init(xsc) 3294 void *xsc; 3295 { 3296 struct dc_softc *sc = xsc; 3297 struct ifnet *ifp = &sc->arpcom.ac_if; 3298 struct mii_data *mii; 3299 3300 DC_LOCK(sc); 3301 3302 mii = device_get_softc(sc->dc_miibus); 3303 3304 /* 3305 * Cancel pending I/O and free all RX/TX buffers. 3306 */ 3307 dc_stop(sc); 3308 dc_reset(sc); 3309 3310 /* 3311 * Set cache alignment and burst length. 3312 */ 3313 if (DC_IS_ASIX(sc) || DC_IS_DAVICOM(sc)) 3314 CSR_WRITE_4(sc, DC_BUSCTL, 0); 3315 else 3316 CSR_WRITE_4(sc, DC_BUSCTL, DC_BUSCTL_MRME|DC_BUSCTL_MRLE); 3317 /* 3318 * Evenly share the bus between receive and transmit process. 3319 */ 3320 if (DC_IS_INTEL(sc)) 3321 DC_SETBIT(sc, DC_BUSCTL, DC_BUSCTL_ARBITRATION); 3322 if (DC_IS_DAVICOM(sc) || DC_IS_INTEL(sc)) { 3323 DC_SETBIT(sc, DC_BUSCTL, DC_BURSTLEN_USECA); 3324 } else { 3325 DC_SETBIT(sc, DC_BUSCTL, DC_BURSTLEN_16LONG); 3326 } 3327 if (sc->dc_flags & DC_TX_POLL) 3328 DC_SETBIT(sc, DC_BUSCTL, DC_TXPOLL_1); 3329 switch(sc->dc_cachesize) { 3330 case 32: 3331 DC_SETBIT(sc, DC_BUSCTL, DC_CACHEALIGN_32LONG); 3332 break; 3333 case 16: 3334 DC_SETBIT(sc, DC_BUSCTL, DC_CACHEALIGN_16LONG); 3335 break; 3336 case 8: 3337 DC_SETBIT(sc, DC_BUSCTL, DC_CACHEALIGN_8LONG); 3338 break; 3339 case 0: 3340 default: 3341 DC_SETBIT(sc, DC_BUSCTL, DC_CACHEALIGN_NONE); 3342 break; 3343 } 3344 3345 if (sc->dc_flags & DC_TX_STORENFWD) 3346 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_STORENFWD); 3347 else { 3348 if (sc->dc_txthresh > DC_TXTHRESH_MAX) { 3349 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_STORENFWD); 3350 } else { 3351 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_STORENFWD); 3352 DC_SETBIT(sc, DC_NETCFG, sc->dc_txthresh); 3353 } 3354 } 3355 3356 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_NO_RXCRC); 3357 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_TX_BACKOFF); 3358 3359 if (DC_IS_MACRONIX(sc) || DC_IS_PNICII(sc)) { 3360 /* 3361 * The app notes for the 98713 and 98715A say that 3362 * in order to have the chips operate properly, a magic 3363 * number must be written to CSR16. Macronix does not 3364 * document the meaning of these bits so there's no way 3365 * to know exactly what they do. The 98713 has a magic 3366 * number all its own; the rest all use a different one. 3367 */ 3368 DC_CLRBIT(sc, DC_MX_MAGICPACKET, 0xFFFF0000); 3369 if (sc->dc_type == DC_TYPE_98713) 3370 DC_SETBIT(sc, DC_MX_MAGICPACKET, DC_MX_MAGIC_98713); 3371 else 3372 DC_SETBIT(sc, DC_MX_MAGICPACKET, DC_MX_MAGIC_98715); 3373 } 3374 3375 if (DC_IS_XIRCOM(sc)) { 3376 /* 3377 * setup General Purpose Port mode and data so the tulip 3378 * can talk to the MII. 3379 */ 3380 CSR_WRITE_4(sc, DC_SIAGP, DC_SIAGP_WRITE_EN | DC_SIAGP_INT1_EN | 3381 DC_SIAGP_MD_GP2_OUTPUT | DC_SIAGP_MD_GP0_OUTPUT); 3382 DELAY(10); 3383 CSR_WRITE_4(sc, DC_SIAGP, DC_SIAGP_INT1_EN | 3384 DC_SIAGP_MD_GP2_OUTPUT | DC_SIAGP_MD_GP0_OUTPUT); 3385 DELAY(10); 3386 } 3387 3388 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_TX_THRESH); 3389 DC_SETBIT(sc, DC_NETCFG, DC_TXTHRESH_MIN); 3390 3391 /* Init circular RX list. */ 3392 if (dc_list_rx_init(sc) == ENOBUFS) { 3393 printf("dc%d: initialization failed: no " 3394 "memory for rx buffers\n", sc->dc_unit); 3395 dc_stop(sc); 3396 DC_UNLOCK(sc); 3397 return; 3398 } 3399 3400 /* 3401 * Init tx descriptors. 3402 */ 3403 dc_list_tx_init(sc); 3404 3405 /* 3406 * Load the address of the RX list. 3407 */ 3408 CSR_WRITE_4(sc, DC_RXADDR, vtophys(&sc->dc_ldata->dc_rx_list[0])); 3409 CSR_WRITE_4(sc, DC_TXADDR, vtophys(&sc->dc_ldata->dc_tx_list[0])); 3410 3411 /* 3412 * Enable interrupts. 3413 */ 3414 #ifdef DEVICE_POLLING 3415 /* 3416 * ... but only if we are not polling, and make sure they are off in 3417 * the case of polling. Some cards (e.g. fxp) turn interrupts on 3418 * after a reset. 3419 */ 3420 if (ifp->if_flags & IFF_POLLING) 3421 CSR_WRITE_4(sc, DC_IMR, 0x00000000); 3422 else 3423 #endif 3424 CSR_WRITE_4(sc, DC_IMR, DC_INTRS); 3425 CSR_WRITE_4(sc, DC_ISR, 0xFFFFFFFF); 3426 3427 /* Enable transmitter. */ 3428 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_TX_ON); 3429 3430 /* 3431 * If this is an Intel 21143 and we're not using the 3432 * MII port, program the LED control pins so we get 3433 * link and activity indications. 3434 */ 3435 if (sc->dc_flags & DC_TULIP_LEDS) { 3436 CSR_WRITE_4(sc, DC_WATCHDOG, 3437 DC_WDOG_CTLWREN|DC_WDOG_LINK|DC_WDOG_ACTIVITY); 3438 CSR_WRITE_4(sc, DC_WATCHDOG, 0); 3439 } 3440 3441 /* 3442 * Load the RX/multicast filter. We do this sort of late 3443 * because the filter programming scheme on the 21143 and 3444 * some clones requires DMAing a setup frame via the TX 3445 * engine, and we need the transmitter enabled for that. 3446 */ 3447 dc_setfilt(sc); 3448 3449 /* Enable receiver. */ 3450 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_ON); 3451 CSR_WRITE_4(sc, DC_RXSTART, 0xFFFFFFFF); 3452 3453 mii_mediachg(mii); 3454 dc_setcfg(sc, sc->dc_if_media); 3455 3456 ifp->if_flags |= IFF_RUNNING; 3457 ifp->if_flags &= ~IFF_OACTIVE; 3458 3459 /* Don't start the ticker if this is a homePNA link. */ 3460 if (IFM_SUBTYPE(mii->mii_media.ifm_media) == IFM_HPNA_1) 3461 sc->dc_link = 1; 3462 else { 3463 if (sc->dc_flags & DC_21143_NWAY) 3464 callout_reset(&sc->dc_stat_ch, hz/10, dc_tick, sc); 3465 else 3466 callout_reset(&sc->dc_stat_ch, hz, dc_tick, sc); 3467 } 3468 3469 #ifdef SRM_MEDIA 3470 if(sc->dc_srm_media) { 3471 struct ifreq ifr; 3472 3473 ifr.ifr_media = sc->dc_srm_media; 3474 ifmedia_ioctl(ifp, &ifr, &mii->mii_media, SIOCSIFMEDIA); 3475 sc->dc_srm_media = 0; 3476 } 3477 #endif 3478 DC_UNLOCK(sc); 3479 return; 3480 } 3481 3482 /* 3483 * Set media options. 3484 */ 3485 static int 3486 dc_ifmedia_upd(ifp) 3487 struct ifnet *ifp; 3488 { 3489 struct dc_softc *sc; 3490 struct mii_data *mii; 3491 struct ifmedia *ifm; 3492 3493 sc = ifp->if_softc; 3494 mii = device_get_softc(sc->dc_miibus); 3495 mii_mediachg(mii); 3496 ifm = &mii->mii_media; 3497 3498 if (DC_IS_DAVICOM(sc) && 3499 IFM_SUBTYPE(ifm->ifm_media) == IFM_HPNA_1) 3500 dc_setcfg(sc, ifm->ifm_media); 3501 else 3502 sc->dc_link = 0; 3503 3504 return(0); 3505 } 3506 3507 /* 3508 * Report current media status. 3509 */ 3510 static void 3511 dc_ifmedia_sts(ifp, ifmr) 3512 struct ifnet *ifp; 3513 struct ifmediareq *ifmr; 3514 { 3515 struct dc_softc *sc; 3516 struct mii_data *mii; 3517 struct ifmedia *ifm; 3518 3519 sc = ifp->if_softc; 3520 mii = device_get_softc(sc->dc_miibus); 3521 mii_pollstat(mii); 3522 ifm = &mii->mii_media; 3523 if (DC_IS_DAVICOM(sc)) { 3524 if (IFM_SUBTYPE(ifm->ifm_media) == IFM_HPNA_1) { 3525 ifmr->ifm_active = ifm->ifm_media; 3526 ifmr->ifm_status = 0; 3527 return; 3528 } 3529 } 3530 ifmr->ifm_active = mii->mii_media_active; 3531 ifmr->ifm_status = mii->mii_media_status; 3532 3533 return; 3534 } 3535 3536 static int 3537 dc_ioctl(ifp, command, data) 3538 struct ifnet *ifp; 3539 u_long command; 3540 caddr_t data; 3541 { 3542 struct dc_softc *sc = ifp->if_softc; 3543 struct ifreq *ifr = (struct ifreq *) data; 3544 struct mii_data *mii; 3545 int error = 0; 3546 3547 DC_LOCK(sc); 3548 3549 switch(command) { 3550 case SIOCSIFFLAGS: 3551 if (ifp->if_flags & IFF_UP) { 3552 int need_setfilt = (ifp->if_flags ^ sc->dc_if_flags) & 3553 (IFF_PROMISC | IFF_ALLMULTI); 3554 3555 if (ifp->if_flags & IFF_RUNNING) { 3556 if (need_setfilt) 3557 dc_setfilt(sc); 3558 } else { 3559 sc->dc_txthresh = 0; 3560 dc_init(sc); 3561 } 3562 } else { 3563 if (ifp->if_flags & IFF_RUNNING) 3564 dc_stop(sc); 3565 } 3566 sc->dc_if_flags = ifp->if_flags; 3567 error = 0; 3568 break; 3569 case SIOCADDMULTI: 3570 case SIOCDELMULTI: 3571 dc_setfilt(sc); 3572 error = 0; 3573 break; 3574 case SIOCGIFMEDIA: 3575 case SIOCSIFMEDIA: 3576 mii = device_get_softc(sc->dc_miibus); 3577 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 3578 #ifdef SRM_MEDIA 3579 if (sc->dc_srm_media) 3580 sc->dc_srm_media = 0; 3581 #endif 3582 break; 3583 default: 3584 error = ether_ioctl(ifp, command, data); 3585 break; 3586 } 3587 3588 DC_UNLOCK(sc); 3589 3590 return(error); 3591 } 3592 3593 static void 3594 dc_watchdog(ifp) 3595 struct ifnet *ifp; 3596 { 3597 struct dc_softc *sc; 3598 3599 sc = ifp->if_softc; 3600 3601 DC_LOCK(sc); 3602 3603 ifp->if_oerrors++; 3604 printf("dc%d: watchdog timeout\n", sc->dc_unit); 3605 3606 dc_stop(sc); 3607 dc_reset(sc); 3608 dc_init(sc); 3609 3610 if (ifp->if_snd.ifq_head != NULL) 3611 dc_start(ifp); 3612 3613 DC_UNLOCK(sc); 3614 3615 return; 3616 } 3617 3618 /* 3619 * Stop the adapter and free any mbufs allocated to the 3620 * RX and TX lists. 3621 */ 3622 static void 3623 dc_stop(sc) 3624 struct dc_softc *sc; 3625 { 3626 register int i; 3627 struct ifnet *ifp; 3628 3629 DC_LOCK(sc); 3630 3631 ifp = &sc->arpcom.ac_if; 3632 ifp->if_timer = 0; 3633 3634 callout_stop(&sc->dc_stat_ch); 3635 3636 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 3637 #ifdef DEVICE_POLLING 3638 ether_poll_deregister(ifp); 3639 #endif 3640 3641 DC_CLRBIT(sc, DC_NETCFG, (DC_NETCFG_RX_ON|DC_NETCFG_TX_ON)); 3642 CSR_WRITE_4(sc, DC_IMR, 0x00000000); 3643 CSR_WRITE_4(sc, DC_TXADDR, 0x00000000); 3644 CSR_WRITE_4(sc, DC_RXADDR, 0x00000000); 3645 sc->dc_link = 0; 3646 3647 /* 3648 * Free data in the RX lists. 3649 */ 3650 for (i = 0; i < DC_RX_LIST_CNT; i++) { 3651 if (sc->dc_cdata.dc_rx_chain[i] != NULL) { 3652 m_freem(sc->dc_cdata.dc_rx_chain[i]); 3653 sc->dc_cdata.dc_rx_chain[i] = NULL; 3654 } 3655 } 3656 bzero((char *)&sc->dc_ldata->dc_rx_list, 3657 sizeof(sc->dc_ldata->dc_rx_list)); 3658 3659 /* 3660 * Free the TX list buffers. 3661 */ 3662 for (i = 0; i < DC_TX_LIST_CNT; i++) { 3663 if (sc->dc_cdata.dc_tx_chain[i] != NULL) { 3664 if (sc->dc_ldata->dc_tx_list[i].dc_ctl & 3665 DC_TXCTL_SETUP) { 3666 sc->dc_cdata.dc_tx_chain[i] = NULL; 3667 continue; 3668 } 3669 m_freem(sc->dc_cdata.dc_tx_chain[i]); 3670 sc->dc_cdata.dc_tx_chain[i] = NULL; 3671 } 3672 } 3673 3674 bzero((char *)&sc->dc_ldata->dc_tx_list, 3675 sizeof(sc->dc_ldata->dc_tx_list)); 3676 3677 DC_UNLOCK(sc); 3678 3679 return; 3680 } 3681 3682 /* 3683 * Device suspend routine. Stop the interface and save some PCI 3684 * settings in case the BIOS doesn't restore them properly on 3685 * resume. 3686 */ 3687 static int 3688 dc_suspend(dev) 3689 device_t dev; 3690 { 3691 register int i; 3692 int s; 3693 struct dc_softc *sc; 3694 3695 s = splimp(); 3696 3697 sc = device_get_softc(dev); 3698 3699 dc_stop(sc); 3700 3701 for (i = 0; i < 5; i++) 3702 sc->saved_maps[i] = pci_read_config(dev, PCIR_MAPS + i * 4, 4); 3703 sc->saved_biosaddr = pci_read_config(dev, PCIR_BIOS, 4); 3704 sc->saved_intline = pci_read_config(dev, PCIR_INTLINE, 1); 3705 sc->saved_cachelnsz = pci_read_config(dev, PCIR_CACHELNSZ, 1); 3706 sc->saved_lattimer = pci_read_config(dev, PCIR_LATTIMER, 1); 3707 3708 sc->suspended = 1; 3709 3710 splx(s); 3711 return (0); 3712 } 3713 3714 /* 3715 * Device resume routine. Restore some PCI settings in case the BIOS 3716 * doesn't, re-enable busmastering, and restart the interface if 3717 * appropriate. 3718 */ 3719 static int 3720 dc_resume(dev) 3721 device_t dev; 3722 { 3723 register int i; 3724 int s; 3725 struct dc_softc *sc; 3726 struct ifnet *ifp; 3727 3728 s = splimp(); 3729 3730 sc = device_get_softc(dev); 3731 ifp = &sc->arpcom.ac_if; 3732 3733 dc_acpi(dev); 3734 3735 /* better way to do this? */ 3736 for (i = 0; i < 5; i++) 3737 pci_write_config(dev, PCIR_MAPS + i * 4, sc->saved_maps[i], 4); 3738 pci_write_config(dev, PCIR_BIOS, sc->saved_biosaddr, 4); 3739 pci_write_config(dev, PCIR_INTLINE, sc->saved_intline, 1); 3740 pci_write_config(dev, PCIR_CACHELNSZ, sc->saved_cachelnsz, 1); 3741 pci_write_config(dev, PCIR_LATTIMER, sc->saved_lattimer, 1); 3742 3743 /* reenable busmastering */ 3744 pci_enable_busmaster(dev); 3745 pci_enable_io(dev, DC_RES); 3746 3747 /* reinitialize interface if necessary */ 3748 if (ifp->if_flags & IFF_UP) 3749 dc_init(sc); 3750 3751 sc->suspended = 0; 3752 3753 splx(s); 3754 return (0); 3755 } 3756 3757 /* 3758 * Stop all chip I/O so that the kernel's probe routines don't 3759 * get confused by errant DMAs when rebooting. 3760 */ 3761 static void 3762 dc_shutdown(dev) 3763 device_t dev; 3764 { 3765 struct dc_softc *sc; 3766 3767 sc = device_get_softc(dev); 3768 3769 dc_stop(sc); 3770 3771 return; 3772 } 3773