1 /*- 2 * Copyright (c) 1997, 1998, 1999 3 * Bill Paul <wpaul@ee.columbia.edu>. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 3. All advertising materials mentioning features or use of this software 14 * must display the following acknowledgement: 15 * This product includes software developed by Bill Paul. 16 * 4. Neither the name of the author nor the names of any co-contributors 17 * may be used to endorse or promote products derived from this software 18 * without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30 * THE POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33 #include <sys/cdefs.h> 34 __FBSDID("$FreeBSD$"); 35 36 /* 37 * DEC "tulip" clone ethernet driver. Supports the DEC/Intel 21143 38 * series chips and several workalikes including the following: 39 * 40 * Macronix 98713/98715/98725/98727/98732 PMAC (www.macronix.com) 41 * Macronix/Lite-On 82c115 PNIC II (www.macronix.com) 42 * Lite-On 82c168/82c169 PNIC (www.litecom.com) 43 * ASIX Electronics AX88140A (www.asix.com.tw) 44 * ASIX Electronics AX88141 (www.asix.com.tw) 45 * ADMtek AL981 (www.admtek.com.tw) 46 * ADMtek AN985 (www.admtek.com.tw) 47 * Netgear FA511 (www.netgear.com) Appears to be rebadged ADMTek AN985 48 * Davicom DM9100, DM9102, DM9102A (www.davicom8.com) 49 * Accton EN1217 (www.accton.com) 50 * Xircom X3201 (www.xircom.com) 51 * Abocom FE2500 52 * Conexant LANfinity (www.conexant.com) 53 * 3Com OfficeConnect 10/100B 3CSOHO100B (www.3com.com) 54 * 55 * Datasheets for the 21143 are available at developer.intel.com. 56 * Datasheets for the clone parts can be found at their respective sites. 57 * (Except for the PNIC; see www.freebsd.org/~wpaul/PNIC/pnic.ps.gz.) 58 * The PNIC II is essentially a Macronix 98715A chip; the only difference 59 * worth noting is that its multicast hash table is only 128 bits wide 60 * instead of 512. 61 * 62 * Written by Bill Paul <wpaul@ee.columbia.edu> 63 * Electrical Engineering Department 64 * Columbia University, New York City 65 */ 66 /* 67 * The Intel 21143 is the successor to the DEC 21140. It is basically 68 * the same as the 21140 but with a few new features. The 21143 supports 69 * three kinds of media attachments: 70 * 71 * o MII port, for 10Mbps and 100Mbps support and NWAY 72 * autonegotiation provided by an external PHY. 73 * o SYM port, for symbol mode 100Mbps support. 74 * o 10baseT port. 75 * o AUI/BNC port. 76 * 77 * The 100Mbps SYM port and 10baseT port can be used together in 78 * combination with the internal NWAY support to create a 10/100 79 * autosensing configuration. 80 * 81 * Note that not all tulip workalikes are handled in this driver: we only 82 * deal with those which are relatively well behaved. The Winbond is 83 * handled separately due to its different register offsets and the 84 * special handling needed for its various bugs. The PNIC is handled 85 * here, but I'm not thrilled about it. 86 * 87 * All of the workalike chips use some form of MII transceiver support 88 * with the exception of the Macronix chips, which also have a SYM port. 89 * The ASIX AX88140A is also documented to have a SYM port, but all 90 * the cards I've seen use an MII transceiver, probably because the 91 * AX88140A doesn't support internal NWAY. 92 */ 93 94 #ifdef HAVE_KERNEL_OPTION_HEADERS 95 #include "opt_device_polling.h" 96 #endif 97 98 #include <sys/param.h> 99 #include <sys/endian.h> 100 #include <sys/systm.h> 101 #include <sys/sockio.h> 102 #include <sys/mbuf.h> 103 #include <sys/malloc.h> 104 #include <sys/kernel.h> 105 #include <sys/module.h> 106 #include <sys/socket.h> 107 108 #include <net/if.h> 109 #include <net/if_arp.h> 110 #include <net/ethernet.h> 111 #include <net/if_dl.h> 112 #include <net/if_media.h> 113 #include <net/if_types.h> 114 #include <net/if_vlan_var.h> 115 116 #include <net/bpf.h> 117 118 #include <machine/bus.h> 119 #include <machine/resource.h> 120 #include <sys/bus.h> 121 #include <sys/rman.h> 122 123 #include <dev/mii/mii.h> 124 #include <dev/mii/miivar.h> 125 126 #include <dev/pci/pcireg.h> 127 #include <dev/pci/pcivar.h> 128 129 #define DC_USEIOSPACE 130 131 #include <dev/dc/if_dcreg.h> 132 133 #ifdef __sparc64__ 134 #include <dev/ofw/openfirm.h> 135 #include <machine/ofw_machdep.h> 136 #endif 137 138 MODULE_DEPEND(dc, pci, 1, 1, 1); 139 MODULE_DEPEND(dc, ether, 1, 1, 1); 140 MODULE_DEPEND(dc, miibus, 1, 1, 1); 141 142 /* 143 * "device miibus" is required in kernel config. See GENERIC if you get 144 * errors here. 145 */ 146 #include "miibus_if.h" 147 148 /* 149 * Various supported device vendors/types and their names. 150 */ 151 static const struct dc_type dc_devs[] = { 152 { DC_DEVID(DC_VENDORID_DEC, DC_DEVICEID_21143), 0, 153 "Intel 21143 10/100BaseTX" }, 154 { DC_DEVID(DC_VENDORID_DAVICOM, DC_DEVICEID_DM9009), 0, 155 "Davicom DM9009 10/100BaseTX" }, 156 { DC_DEVID(DC_VENDORID_DAVICOM, DC_DEVICEID_DM9100), 0, 157 "Davicom DM9100 10/100BaseTX" }, 158 { DC_DEVID(DC_VENDORID_DAVICOM, DC_DEVICEID_DM9102), DC_REVISION_DM9102A, 159 "Davicom DM9102A 10/100BaseTX" }, 160 { DC_DEVID(DC_VENDORID_DAVICOM, DC_DEVICEID_DM9102), 0, 161 "Davicom DM9102 10/100BaseTX" }, 162 { DC_DEVID(DC_VENDORID_ADMTEK, DC_DEVICEID_AL981), 0, 163 "ADMtek AL981 10/100BaseTX" }, 164 { DC_DEVID(DC_VENDORID_ADMTEK, DC_DEVICEID_AN985), 0, 165 "ADMtek AN985 10/100BaseTX" }, 166 { DC_DEVID(DC_VENDORID_ADMTEK, DC_DEVICEID_ADM9511), 0, 167 "ADMtek ADM9511 10/100BaseTX" }, 168 { DC_DEVID(DC_VENDORID_ADMTEK, DC_DEVICEID_ADM9513), 0, 169 "ADMtek ADM9513 10/100BaseTX" }, 170 { DC_DEVID(DC_VENDORID_ADMTEK, DC_DEVICEID_FA511), 0, 171 "Netgear FA511 10/100BaseTX" }, 172 { DC_DEVID(DC_VENDORID_ASIX, DC_DEVICEID_AX88140A), DC_REVISION_88141, 173 "ASIX AX88141 10/100BaseTX" }, 174 { DC_DEVID(DC_VENDORID_ASIX, DC_DEVICEID_AX88140A), 0, 175 "ASIX AX88140A 10/100BaseTX" }, 176 { DC_DEVID(DC_VENDORID_MX, DC_DEVICEID_98713), DC_REVISION_98713A, 177 "Macronix 98713A 10/100BaseTX" }, 178 { DC_DEVID(DC_VENDORID_MX, DC_DEVICEID_98713), 0, 179 "Macronix 98713 10/100BaseTX" }, 180 { DC_DEVID(DC_VENDORID_CP, DC_DEVICEID_98713_CP), DC_REVISION_98713A, 181 "Compex RL100-TX 10/100BaseTX" }, 182 { DC_DEVID(DC_VENDORID_CP, DC_DEVICEID_98713_CP), 0, 183 "Compex RL100-TX 10/100BaseTX" }, 184 { DC_DEVID(DC_VENDORID_MX, DC_DEVICEID_987x5), DC_REVISION_98725, 185 "Macronix 98725 10/100BaseTX" }, 186 { DC_DEVID(DC_VENDORID_MX, DC_DEVICEID_987x5), DC_REVISION_98715AEC_C, 187 "Macronix 98715AEC-C 10/100BaseTX" }, 188 { DC_DEVID(DC_VENDORID_MX, DC_DEVICEID_987x5), 0, 189 "Macronix 98715/98715A 10/100BaseTX" }, 190 { DC_DEVID(DC_VENDORID_MX, DC_DEVICEID_98727), 0, 191 "Macronix 98727/98732 10/100BaseTX" }, 192 { DC_DEVID(DC_VENDORID_LO, DC_DEVICEID_82C115), 0, 193 "LC82C115 PNIC II 10/100BaseTX" }, 194 { DC_DEVID(DC_VENDORID_LO, DC_DEVICEID_82C168), DC_REVISION_82C169, 195 "82c169 PNIC 10/100BaseTX" }, 196 { DC_DEVID(DC_VENDORID_LO, DC_DEVICEID_82C168), 0, 197 "82c168 PNIC 10/100BaseTX" }, 198 { DC_DEVID(DC_VENDORID_ACCTON, DC_DEVICEID_EN1217), 0, 199 "Accton EN1217 10/100BaseTX" }, 200 { DC_DEVID(DC_VENDORID_ACCTON, DC_DEVICEID_EN2242), 0, 201 "Accton EN2242 MiniPCI 10/100BaseTX" }, 202 { DC_DEVID(DC_VENDORID_XIRCOM, DC_DEVICEID_X3201), 0, 203 "Xircom X3201 10/100BaseTX" }, 204 { DC_DEVID(DC_VENDORID_DLINK, DC_DEVICEID_DRP32TXD), 0, 205 "Neteasy DRP-32TXD Cardbus 10/100" }, 206 { DC_DEVID(DC_VENDORID_ABOCOM, DC_DEVICEID_FE2500), 0, 207 "Abocom FE2500 10/100BaseTX" }, 208 { DC_DEVID(DC_VENDORID_ABOCOM, DC_DEVICEID_FE2500MX), 0, 209 "Abocom FE2500MX 10/100BaseTX" }, 210 { DC_DEVID(DC_VENDORID_CONEXANT, DC_DEVICEID_RS7112), 0, 211 "Conexant LANfinity MiniPCI 10/100BaseTX" }, 212 { DC_DEVID(DC_VENDORID_HAWKING, DC_DEVICEID_HAWKING_PN672TX), 0, 213 "Hawking CB102 CardBus 10/100" }, 214 { DC_DEVID(DC_VENDORID_PLANEX, DC_DEVICEID_FNW3602T), 0, 215 "PlaneX FNW-3602-T CardBus 10/100" }, 216 { DC_DEVID(DC_VENDORID_3COM, DC_DEVICEID_3CSOHOB), 0, 217 "3Com OfficeConnect 10/100B" }, 218 { DC_DEVID(DC_VENDORID_MICROSOFT, DC_DEVICEID_MSMN120), 0, 219 "Microsoft MN-120 CardBus 10/100" }, 220 { DC_DEVID(DC_VENDORID_MICROSOFT, DC_DEVICEID_MSMN130), 0, 221 "Microsoft MN-130 10/100" }, 222 { DC_DEVID(DC_VENDORID_LINKSYS, DC_DEVICEID_PCMPC200_AB08), 0, 223 "Linksys PCMPC200 CardBus 10/100" }, 224 { DC_DEVID(DC_VENDORID_LINKSYS, DC_DEVICEID_PCMPC200_AB09), 0, 225 "Linksys PCMPC200 CardBus 10/100" }, 226 { 0, 0, NULL } 227 }; 228 229 static int dc_probe(device_t); 230 static int dc_attach(device_t); 231 static int dc_detach(device_t); 232 static int dc_suspend(device_t); 233 static int dc_resume(device_t); 234 static const struct dc_type *dc_devtype(device_t); 235 static int dc_newbuf(struct dc_softc *, int, int); 236 static int dc_encap(struct dc_softc *, struct mbuf **); 237 static void dc_pnic_rx_bug_war(struct dc_softc *, int); 238 static int dc_rx_resync(struct dc_softc *); 239 static void dc_rxeof(struct dc_softc *); 240 static void dc_txeof(struct dc_softc *); 241 static void dc_tick(void *); 242 static void dc_tx_underrun(struct dc_softc *); 243 static void dc_intr(void *); 244 static void dc_start(struct ifnet *); 245 static void dc_start_locked(struct ifnet *); 246 static int dc_ioctl(struct ifnet *, u_long, caddr_t); 247 static void dc_init(void *); 248 static void dc_init_locked(struct dc_softc *); 249 static void dc_stop(struct dc_softc *); 250 static void dc_watchdog(void *); 251 static int dc_shutdown(device_t); 252 static int dc_ifmedia_upd(struct ifnet *); 253 static void dc_ifmedia_sts(struct ifnet *, struct ifmediareq *); 254 255 static void dc_delay(struct dc_softc *); 256 static void dc_eeprom_idle(struct dc_softc *); 257 static void dc_eeprom_putbyte(struct dc_softc *, int); 258 static void dc_eeprom_getword(struct dc_softc *, int, u_int16_t *); 259 static void dc_eeprom_getword_pnic(struct dc_softc *, int, u_int16_t *); 260 static void dc_eeprom_getword_xircom(struct dc_softc *, int, u_int16_t *); 261 static void dc_eeprom_width(struct dc_softc *); 262 static void dc_read_eeprom(struct dc_softc *, caddr_t, int, int, int); 263 264 static void dc_mii_writebit(struct dc_softc *, int); 265 static int dc_mii_readbit(struct dc_softc *); 266 static void dc_mii_sync(struct dc_softc *); 267 static void dc_mii_send(struct dc_softc *, u_int32_t, int); 268 static int dc_mii_readreg(struct dc_softc *, struct dc_mii_frame *); 269 static int dc_mii_writereg(struct dc_softc *, struct dc_mii_frame *); 270 static int dc_miibus_readreg(device_t, int, int); 271 static int dc_miibus_writereg(device_t, int, int, int); 272 static void dc_miibus_statchg(device_t); 273 static void dc_miibus_mediainit(device_t); 274 275 static void dc_setcfg(struct dc_softc *, int); 276 static uint32_t dc_mchash_le(struct dc_softc *, const uint8_t *); 277 static uint32_t dc_mchash_be(const uint8_t *); 278 static void dc_setfilt_21143(struct dc_softc *); 279 static void dc_setfilt_asix(struct dc_softc *); 280 static void dc_setfilt_admtek(struct dc_softc *); 281 static void dc_setfilt_xircom(struct dc_softc *); 282 283 static void dc_setfilt(struct dc_softc *); 284 285 static void dc_reset(struct dc_softc *); 286 static int dc_list_rx_init(struct dc_softc *); 287 static int dc_list_tx_init(struct dc_softc *); 288 289 static void dc_read_srom(struct dc_softc *, int); 290 static void dc_parse_21143_srom(struct dc_softc *); 291 static void dc_decode_leaf_sia(struct dc_softc *, struct dc_eblock_sia *); 292 static void dc_decode_leaf_mii(struct dc_softc *, struct dc_eblock_mii *); 293 static void dc_decode_leaf_sym(struct dc_softc *, struct dc_eblock_sym *); 294 static void dc_apply_fixup(struct dc_softc *, int); 295 296 #ifdef DC_USEIOSPACE 297 #define DC_RES SYS_RES_IOPORT 298 #define DC_RID DC_PCI_CFBIO 299 #else 300 #define DC_RES SYS_RES_MEMORY 301 #define DC_RID DC_PCI_CFBMA 302 #endif 303 304 static device_method_t dc_methods[] = { 305 /* Device interface */ 306 DEVMETHOD(device_probe, dc_probe), 307 DEVMETHOD(device_attach, dc_attach), 308 DEVMETHOD(device_detach, dc_detach), 309 DEVMETHOD(device_suspend, dc_suspend), 310 DEVMETHOD(device_resume, dc_resume), 311 DEVMETHOD(device_shutdown, dc_shutdown), 312 313 /* bus interface */ 314 DEVMETHOD(bus_print_child, bus_generic_print_child), 315 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 316 317 /* MII interface */ 318 DEVMETHOD(miibus_readreg, dc_miibus_readreg), 319 DEVMETHOD(miibus_writereg, dc_miibus_writereg), 320 DEVMETHOD(miibus_statchg, dc_miibus_statchg), 321 DEVMETHOD(miibus_mediainit, dc_miibus_mediainit), 322 323 { 0, 0 } 324 }; 325 326 static driver_t dc_driver = { 327 "dc", 328 dc_methods, 329 sizeof(struct dc_softc) 330 }; 331 332 static devclass_t dc_devclass; 333 334 DRIVER_MODULE(dc, cardbus, dc_driver, dc_devclass, 0, 0); 335 DRIVER_MODULE(dc, pci, dc_driver, dc_devclass, 0, 0); 336 DRIVER_MODULE(miibus, dc, miibus_driver, miibus_devclass, 0, 0); 337 338 #define DC_SETBIT(sc, reg, x) \ 339 CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) | (x)) 340 341 #define DC_CLRBIT(sc, reg, x) \ 342 CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) & ~(x)) 343 344 #define SIO_SET(x) DC_SETBIT(sc, DC_SIO, (x)) 345 #define SIO_CLR(x) DC_CLRBIT(sc, DC_SIO, (x)) 346 347 static void 348 dc_delay(struct dc_softc *sc) 349 { 350 int idx; 351 352 for (idx = (300 / 33) + 1; idx > 0; idx--) 353 CSR_READ_4(sc, DC_BUSCTL); 354 } 355 356 static void 357 dc_eeprom_width(struct dc_softc *sc) 358 { 359 int i; 360 361 /* Force EEPROM to idle state. */ 362 dc_eeprom_idle(sc); 363 364 /* Enter EEPROM access mode. */ 365 CSR_WRITE_4(sc, DC_SIO, DC_SIO_EESEL); 366 dc_delay(sc); 367 DC_SETBIT(sc, DC_SIO, DC_SIO_ROMCTL_READ); 368 dc_delay(sc); 369 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); 370 dc_delay(sc); 371 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CS); 372 dc_delay(sc); 373 374 for (i = 3; i--;) { 375 if (6 & (1 << i)) 376 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_DATAIN); 377 else 378 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_DATAIN); 379 dc_delay(sc); 380 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CLK); 381 dc_delay(sc); 382 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); 383 dc_delay(sc); 384 } 385 386 for (i = 1; i <= 12; i++) { 387 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CLK); 388 dc_delay(sc); 389 if (!(CSR_READ_4(sc, DC_SIO) & DC_SIO_EE_DATAOUT)) { 390 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); 391 dc_delay(sc); 392 break; 393 } 394 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); 395 dc_delay(sc); 396 } 397 398 /* Turn off EEPROM access mode. */ 399 dc_eeprom_idle(sc); 400 401 if (i < 4 || i > 12) 402 sc->dc_romwidth = 6; 403 else 404 sc->dc_romwidth = i; 405 406 /* Enter EEPROM access mode. */ 407 CSR_WRITE_4(sc, DC_SIO, DC_SIO_EESEL); 408 dc_delay(sc); 409 DC_SETBIT(sc, DC_SIO, DC_SIO_ROMCTL_READ); 410 dc_delay(sc); 411 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); 412 dc_delay(sc); 413 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CS); 414 dc_delay(sc); 415 416 /* Turn off EEPROM access mode. */ 417 dc_eeprom_idle(sc); 418 } 419 420 static void 421 dc_eeprom_idle(struct dc_softc *sc) 422 { 423 int i; 424 425 CSR_WRITE_4(sc, DC_SIO, DC_SIO_EESEL); 426 dc_delay(sc); 427 DC_SETBIT(sc, DC_SIO, DC_SIO_ROMCTL_READ); 428 dc_delay(sc); 429 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); 430 dc_delay(sc); 431 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CS); 432 dc_delay(sc); 433 434 for (i = 0; i < 25; i++) { 435 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); 436 dc_delay(sc); 437 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CLK); 438 dc_delay(sc); 439 } 440 441 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); 442 dc_delay(sc); 443 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CS); 444 dc_delay(sc); 445 CSR_WRITE_4(sc, DC_SIO, 0x00000000); 446 } 447 448 /* 449 * Send a read command and address to the EEPROM, check for ACK. 450 */ 451 static void 452 dc_eeprom_putbyte(struct dc_softc *sc, int addr) 453 { 454 int d, i; 455 456 d = DC_EECMD_READ >> 6; 457 for (i = 3; i--; ) { 458 if (d & (1 << i)) 459 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_DATAIN); 460 else 461 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_DATAIN); 462 dc_delay(sc); 463 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CLK); 464 dc_delay(sc); 465 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); 466 dc_delay(sc); 467 } 468 469 /* 470 * Feed in each bit and strobe the clock. 471 */ 472 for (i = sc->dc_romwidth; i--;) { 473 if (addr & (1 << i)) { 474 SIO_SET(DC_SIO_EE_DATAIN); 475 } else { 476 SIO_CLR(DC_SIO_EE_DATAIN); 477 } 478 dc_delay(sc); 479 SIO_SET(DC_SIO_EE_CLK); 480 dc_delay(sc); 481 SIO_CLR(DC_SIO_EE_CLK); 482 dc_delay(sc); 483 } 484 } 485 486 /* 487 * Read a word of data stored in the EEPROM at address 'addr.' 488 * The PNIC 82c168/82c169 has its own non-standard way to read 489 * the EEPROM. 490 */ 491 static void 492 dc_eeprom_getword_pnic(struct dc_softc *sc, int addr, u_int16_t *dest) 493 { 494 int i; 495 u_int32_t r; 496 497 CSR_WRITE_4(sc, DC_PN_SIOCTL, DC_PN_EEOPCODE_READ | addr); 498 499 for (i = 0; i < DC_TIMEOUT; i++) { 500 DELAY(1); 501 r = CSR_READ_4(sc, DC_SIO); 502 if (!(r & DC_PN_SIOCTL_BUSY)) { 503 *dest = (u_int16_t)(r & 0xFFFF); 504 return; 505 } 506 } 507 } 508 509 /* 510 * Read a word of data stored in the EEPROM at address 'addr.' 511 * The Xircom X3201 has its own non-standard way to read 512 * the EEPROM, too. 513 */ 514 static void 515 dc_eeprom_getword_xircom(struct dc_softc *sc, int addr, u_int16_t *dest) 516 { 517 518 SIO_SET(DC_SIO_ROMSEL | DC_SIO_ROMCTL_READ); 519 520 addr *= 2; 521 CSR_WRITE_4(sc, DC_ROM, addr | 0x160); 522 *dest = (u_int16_t)CSR_READ_4(sc, DC_SIO) & 0xff; 523 addr += 1; 524 CSR_WRITE_4(sc, DC_ROM, addr | 0x160); 525 *dest |= ((u_int16_t)CSR_READ_4(sc, DC_SIO) & 0xff) << 8; 526 527 SIO_CLR(DC_SIO_ROMSEL | DC_SIO_ROMCTL_READ); 528 } 529 530 /* 531 * Read a word of data stored in the EEPROM at address 'addr.' 532 */ 533 static void 534 dc_eeprom_getword(struct dc_softc *sc, int addr, u_int16_t *dest) 535 { 536 int i; 537 u_int16_t word = 0; 538 539 /* Force EEPROM to idle state. */ 540 dc_eeprom_idle(sc); 541 542 /* Enter EEPROM access mode. */ 543 CSR_WRITE_4(sc, DC_SIO, DC_SIO_EESEL); 544 dc_delay(sc); 545 DC_SETBIT(sc, DC_SIO, DC_SIO_ROMCTL_READ); 546 dc_delay(sc); 547 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); 548 dc_delay(sc); 549 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CS); 550 dc_delay(sc); 551 552 /* 553 * Send address of word we want to read. 554 */ 555 dc_eeprom_putbyte(sc, addr); 556 557 /* 558 * Start reading bits from EEPROM. 559 */ 560 for (i = 0x8000; i; i >>= 1) { 561 SIO_SET(DC_SIO_EE_CLK); 562 dc_delay(sc); 563 if (CSR_READ_4(sc, DC_SIO) & DC_SIO_EE_DATAOUT) 564 word |= i; 565 dc_delay(sc); 566 SIO_CLR(DC_SIO_EE_CLK); 567 dc_delay(sc); 568 } 569 570 /* Turn off EEPROM access mode. */ 571 dc_eeprom_idle(sc); 572 573 *dest = word; 574 } 575 576 /* 577 * Read a sequence of words from the EEPROM. 578 */ 579 static void 580 dc_read_eeprom(struct dc_softc *sc, caddr_t dest, int off, int cnt, int be) 581 { 582 int i; 583 u_int16_t word = 0, *ptr; 584 585 for (i = 0; i < cnt; i++) { 586 if (DC_IS_PNIC(sc)) 587 dc_eeprom_getword_pnic(sc, off + i, &word); 588 else if (DC_IS_XIRCOM(sc)) 589 dc_eeprom_getword_xircom(sc, off + i, &word); 590 else 591 dc_eeprom_getword(sc, off + i, &word); 592 ptr = (u_int16_t *)(dest + (i * 2)); 593 if (be) 594 *ptr = be16toh(word); 595 else 596 *ptr = le16toh(word); 597 } 598 } 599 600 /* 601 * The following two routines are taken from the Macronix 98713 602 * Application Notes pp.19-21. 603 */ 604 /* 605 * Write a bit to the MII bus. 606 */ 607 static void 608 dc_mii_writebit(struct dc_softc *sc, int bit) 609 { 610 611 if (bit) 612 CSR_WRITE_4(sc, DC_SIO, 613 DC_SIO_ROMCTL_WRITE | DC_SIO_MII_DATAOUT); 614 else 615 CSR_WRITE_4(sc, DC_SIO, DC_SIO_ROMCTL_WRITE); 616 617 DC_SETBIT(sc, DC_SIO, DC_SIO_MII_CLK); 618 DC_CLRBIT(sc, DC_SIO, DC_SIO_MII_CLK); 619 } 620 621 /* 622 * Read a bit from the MII bus. 623 */ 624 static int 625 dc_mii_readbit(struct dc_softc *sc) 626 { 627 628 CSR_WRITE_4(sc, DC_SIO, DC_SIO_ROMCTL_READ | DC_SIO_MII_DIR); 629 CSR_READ_4(sc, DC_SIO); 630 DC_SETBIT(sc, DC_SIO, DC_SIO_MII_CLK); 631 DC_CLRBIT(sc, DC_SIO, DC_SIO_MII_CLK); 632 if (CSR_READ_4(sc, DC_SIO) & DC_SIO_MII_DATAIN) 633 return (1); 634 635 return (0); 636 } 637 638 /* 639 * Sync the PHYs by setting data bit and strobing the clock 32 times. 640 */ 641 static void 642 dc_mii_sync(struct dc_softc *sc) 643 { 644 int i; 645 646 CSR_WRITE_4(sc, DC_SIO, DC_SIO_ROMCTL_WRITE); 647 648 for (i = 0; i < 32; i++) 649 dc_mii_writebit(sc, 1); 650 } 651 652 /* 653 * Clock a series of bits through the MII. 654 */ 655 static void 656 dc_mii_send(struct dc_softc *sc, u_int32_t bits, int cnt) 657 { 658 int i; 659 660 for (i = (0x1 << (cnt - 1)); i; i >>= 1) 661 dc_mii_writebit(sc, bits & i); 662 } 663 664 /* 665 * Read an PHY register through the MII. 666 */ 667 static int 668 dc_mii_readreg(struct dc_softc *sc, struct dc_mii_frame *frame) 669 { 670 int i, ack; 671 672 /* 673 * Set up frame for RX. 674 */ 675 frame->mii_stdelim = DC_MII_STARTDELIM; 676 frame->mii_opcode = DC_MII_READOP; 677 frame->mii_turnaround = 0; 678 frame->mii_data = 0; 679 680 /* 681 * Sync the PHYs. 682 */ 683 dc_mii_sync(sc); 684 685 /* 686 * Send command/address info. 687 */ 688 dc_mii_send(sc, frame->mii_stdelim, 2); 689 dc_mii_send(sc, frame->mii_opcode, 2); 690 dc_mii_send(sc, frame->mii_phyaddr, 5); 691 dc_mii_send(sc, frame->mii_regaddr, 5); 692 693 #ifdef notdef 694 /* Idle bit */ 695 dc_mii_writebit(sc, 1); 696 dc_mii_writebit(sc, 0); 697 #endif 698 699 /* Check for ack. */ 700 ack = dc_mii_readbit(sc); 701 702 /* 703 * Now try reading data bits. If the ack failed, we still 704 * need to clock through 16 cycles to keep the PHY(s) in sync. 705 */ 706 if (ack) { 707 for (i = 0; i < 16; i++) 708 dc_mii_readbit(sc); 709 goto fail; 710 } 711 712 for (i = 0x8000; i; i >>= 1) { 713 if (!ack) { 714 if (dc_mii_readbit(sc)) 715 frame->mii_data |= i; 716 } 717 } 718 719 fail: 720 721 dc_mii_writebit(sc, 0); 722 dc_mii_writebit(sc, 0); 723 724 if (ack) 725 return (1); 726 return (0); 727 } 728 729 /* 730 * Write to a PHY register through the MII. 731 */ 732 static int 733 dc_mii_writereg(struct dc_softc *sc, struct dc_mii_frame *frame) 734 { 735 736 /* 737 * Set up frame for TX. 738 */ 739 740 frame->mii_stdelim = DC_MII_STARTDELIM; 741 frame->mii_opcode = DC_MII_WRITEOP; 742 frame->mii_turnaround = DC_MII_TURNAROUND; 743 744 /* 745 * Sync the PHYs. 746 */ 747 dc_mii_sync(sc); 748 749 dc_mii_send(sc, frame->mii_stdelim, 2); 750 dc_mii_send(sc, frame->mii_opcode, 2); 751 dc_mii_send(sc, frame->mii_phyaddr, 5); 752 dc_mii_send(sc, frame->mii_regaddr, 5); 753 dc_mii_send(sc, frame->mii_turnaround, 2); 754 dc_mii_send(sc, frame->mii_data, 16); 755 756 /* Idle bit. */ 757 dc_mii_writebit(sc, 0); 758 dc_mii_writebit(sc, 0); 759 760 return (0); 761 } 762 763 static int 764 dc_miibus_readreg(device_t dev, int phy, int reg) 765 { 766 struct dc_mii_frame frame; 767 struct dc_softc *sc; 768 int i, rval, phy_reg = 0; 769 770 sc = device_get_softc(dev); 771 bzero(&frame, sizeof(frame)); 772 773 /* 774 * Note: both the AL981 and AN985 have internal PHYs, 775 * however the AL981 provides direct access to the PHY 776 * registers while the AN985 uses a serial MII interface. 777 * The AN985's MII interface is also buggy in that you 778 * can read from any MII address (0 to 31), but only address 1 779 * behaves normally. To deal with both cases, we pretend 780 * that the PHY is at MII address 1. 781 */ 782 if (DC_IS_ADMTEK(sc) && phy != DC_ADMTEK_PHYADDR) 783 return (0); 784 785 /* 786 * Note: the ukphy probes of the RS7112 report a PHY at 787 * MII address 0 (possibly HomePNA?) and 1 (ethernet) 788 * so we only respond to correct one. 789 */ 790 if (DC_IS_CONEXANT(sc) && phy != DC_CONEXANT_PHYADDR) 791 return (0); 792 793 if (sc->dc_pmode != DC_PMODE_MII) { 794 if (phy == (MII_NPHY - 1)) { 795 switch (reg) { 796 case MII_BMSR: 797 /* 798 * Fake something to make the probe 799 * code think there's a PHY here. 800 */ 801 return (BMSR_MEDIAMASK); 802 break; 803 case MII_PHYIDR1: 804 if (DC_IS_PNIC(sc)) 805 return (DC_VENDORID_LO); 806 return (DC_VENDORID_DEC); 807 break; 808 case MII_PHYIDR2: 809 if (DC_IS_PNIC(sc)) 810 return (DC_DEVICEID_82C168); 811 return (DC_DEVICEID_21143); 812 break; 813 default: 814 return (0); 815 break; 816 } 817 } else 818 return (0); 819 } 820 821 if (DC_IS_PNIC(sc)) { 822 CSR_WRITE_4(sc, DC_PN_MII, DC_PN_MIIOPCODE_READ | 823 (phy << 23) | (reg << 18)); 824 for (i = 0; i < DC_TIMEOUT; i++) { 825 DELAY(1); 826 rval = CSR_READ_4(sc, DC_PN_MII); 827 if (!(rval & DC_PN_MII_BUSY)) { 828 rval &= 0xFFFF; 829 return (rval == 0xFFFF ? 0 : rval); 830 } 831 } 832 return (0); 833 } 834 835 if (DC_IS_COMET(sc)) { 836 switch (reg) { 837 case MII_BMCR: 838 phy_reg = DC_AL_BMCR; 839 break; 840 case MII_BMSR: 841 phy_reg = DC_AL_BMSR; 842 break; 843 case MII_PHYIDR1: 844 phy_reg = DC_AL_VENID; 845 break; 846 case MII_PHYIDR2: 847 phy_reg = DC_AL_DEVID; 848 break; 849 case MII_ANAR: 850 phy_reg = DC_AL_ANAR; 851 break; 852 case MII_ANLPAR: 853 phy_reg = DC_AL_LPAR; 854 break; 855 case MII_ANER: 856 phy_reg = DC_AL_ANER; 857 break; 858 default: 859 device_printf(dev, "phy_read: bad phy register %x\n", 860 reg); 861 return (0); 862 break; 863 } 864 865 rval = CSR_READ_4(sc, phy_reg) & 0x0000FFFF; 866 867 if (rval == 0xFFFF) 868 return (0); 869 return (rval); 870 } 871 872 frame.mii_phyaddr = phy; 873 frame.mii_regaddr = reg; 874 if (sc->dc_type == DC_TYPE_98713) { 875 phy_reg = CSR_READ_4(sc, DC_NETCFG); 876 CSR_WRITE_4(sc, DC_NETCFG, phy_reg & ~DC_NETCFG_PORTSEL); 877 } 878 dc_mii_readreg(sc, &frame); 879 if (sc->dc_type == DC_TYPE_98713) 880 CSR_WRITE_4(sc, DC_NETCFG, phy_reg); 881 882 return (frame.mii_data); 883 } 884 885 static int 886 dc_miibus_writereg(device_t dev, int phy, int reg, int data) 887 { 888 struct dc_softc *sc; 889 struct dc_mii_frame frame; 890 int i, phy_reg = 0; 891 892 sc = device_get_softc(dev); 893 bzero(&frame, sizeof(frame)); 894 895 if (DC_IS_ADMTEK(sc) && phy != DC_ADMTEK_PHYADDR) 896 return (0); 897 898 if (DC_IS_CONEXANT(sc) && phy != DC_CONEXANT_PHYADDR) 899 return (0); 900 901 if (DC_IS_PNIC(sc)) { 902 CSR_WRITE_4(sc, DC_PN_MII, DC_PN_MIIOPCODE_WRITE | 903 (phy << 23) | (reg << 10) | data); 904 for (i = 0; i < DC_TIMEOUT; i++) { 905 if (!(CSR_READ_4(sc, DC_PN_MII) & DC_PN_MII_BUSY)) 906 break; 907 } 908 return (0); 909 } 910 911 if (DC_IS_COMET(sc)) { 912 switch (reg) { 913 case MII_BMCR: 914 phy_reg = DC_AL_BMCR; 915 break; 916 case MII_BMSR: 917 phy_reg = DC_AL_BMSR; 918 break; 919 case MII_PHYIDR1: 920 phy_reg = DC_AL_VENID; 921 break; 922 case MII_PHYIDR2: 923 phy_reg = DC_AL_DEVID; 924 break; 925 case MII_ANAR: 926 phy_reg = DC_AL_ANAR; 927 break; 928 case MII_ANLPAR: 929 phy_reg = DC_AL_LPAR; 930 break; 931 case MII_ANER: 932 phy_reg = DC_AL_ANER; 933 break; 934 default: 935 device_printf(dev, "phy_write: bad phy register %x\n", 936 reg); 937 return (0); 938 break; 939 } 940 941 CSR_WRITE_4(sc, phy_reg, data); 942 return (0); 943 } 944 945 frame.mii_phyaddr = phy; 946 frame.mii_regaddr = reg; 947 frame.mii_data = data; 948 949 if (sc->dc_type == DC_TYPE_98713) { 950 phy_reg = CSR_READ_4(sc, DC_NETCFG); 951 CSR_WRITE_4(sc, DC_NETCFG, phy_reg & ~DC_NETCFG_PORTSEL); 952 } 953 dc_mii_writereg(sc, &frame); 954 if (sc->dc_type == DC_TYPE_98713) 955 CSR_WRITE_4(sc, DC_NETCFG, phy_reg); 956 957 return (0); 958 } 959 960 static void 961 dc_miibus_statchg(device_t dev) 962 { 963 struct dc_softc *sc; 964 struct mii_data *mii; 965 struct ifmedia *ifm; 966 967 sc = device_get_softc(dev); 968 if (DC_IS_ADMTEK(sc)) 969 return; 970 971 mii = device_get_softc(sc->dc_miibus); 972 ifm = &mii->mii_media; 973 if (DC_IS_DAVICOM(sc) && 974 IFM_SUBTYPE(ifm->ifm_media) == IFM_HPNA_1) { 975 dc_setcfg(sc, ifm->ifm_media); 976 sc->dc_if_media = ifm->ifm_media; 977 } else { 978 dc_setcfg(sc, mii->mii_media_active); 979 sc->dc_if_media = mii->mii_media_active; 980 } 981 } 982 983 /* 984 * Special support for DM9102A cards with HomePNA PHYs. Note: 985 * with the Davicom DM9102A/DM9801 eval board that I have, it seems 986 * to be impossible to talk to the management interface of the DM9801 987 * PHY (its MDIO pin is not connected to anything). Consequently, 988 * the driver has to just 'know' about the additional mode and deal 989 * with it itself. *sigh* 990 */ 991 static void 992 dc_miibus_mediainit(device_t dev) 993 { 994 struct dc_softc *sc; 995 struct mii_data *mii; 996 struct ifmedia *ifm; 997 int rev; 998 999 rev = pci_get_revid(dev); 1000 1001 sc = device_get_softc(dev); 1002 mii = device_get_softc(sc->dc_miibus); 1003 ifm = &mii->mii_media; 1004 1005 if (DC_IS_DAVICOM(sc) && rev >= DC_REVISION_DM9102A) 1006 ifmedia_add(ifm, IFM_ETHER | IFM_HPNA_1, 0, NULL); 1007 } 1008 1009 #define DC_BITS_512 9 1010 #define DC_BITS_128 7 1011 #define DC_BITS_64 6 1012 1013 static uint32_t 1014 dc_mchash_le(struct dc_softc *sc, const uint8_t *addr) 1015 { 1016 uint32_t crc; 1017 1018 /* Compute CRC for the address value. */ 1019 crc = ether_crc32_le(addr, ETHER_ADDR_LEN); 1020 1021 /* 1022 * The hash table on the PNIC II and the MX98715AEC-C/D/E 1023 * chips is only 128 bits wide. 1024 */ 1025 if (sc->dc_flags & DC_128BIT_HASH) 1026 return (crc & ((1 << DC_BITS_128) - 1)); 1027 1028 /* The hash table on the MX98715BEC is only 64 bits wide. */ 1029 if (sc->dc_flags & DC_64BIT_HASH) 1030 return (crc & ((1 << DC_BITS_64) - 1)); 1031 1032 /* Xircom's hash filtering table is different (read: weird) */ 1033 /* Xircom uses the LEAST significant bits */ 1034 if (DC_IS_XIRCOM(sc)) { 1035 if ((crc & 0x180) == 0x180) 1036 return ((crc & 0x0F) + (crc & 0x70) * 3 + (14 << 4)); 1037 else 1038 return ((crc & 0x1F) + ((crc >> 1) & 0xF0) * 3 + 1039 (12 << 4)); 1040 } 1041 1042 return (crc & ((1 << DC_BITS_512) - 1)); 1043 } 1044 1045 /* 1046 * Calculate CRC of a multicast group address, return the lower 6 bits. 1047 */ 1048 static uint32_t 1049 dc_mchash_be(const uint8_t *addr) 1050 { 1051 uint32_t crc; 1052 1053 /* Compute CRC for the address value. */ 1054 crc = ether_crc32_be(addr, ETHER_ADDR_LEN); 1055 1056 /* Return the filter bit position. */ 1057 return ((crc >> 26) & 0x0000003F); 1058 } 1059 1060 /* 1061 * 21143-style RX filter setup routine. Filter programming is done by 1062 * downloading a special setup frame into the TX engine. 21143, Macronix, 1063 * PNIC, PNIC II and Davicom chips are programmed this way. 1064 * 1065 * We always program the chip using 'hash perfect' mode, i.e. one perfect 1066 * address (our node address) and a 512-bit hash filter for multicast 1067 * frames. We also sneak the broadcast address into the hash filter since 1068 * we need that too. 1069 */ 1070 static void 1071 dc_setfilt_21143(struct dc_softc *sc) 1072 { 1073 uint16_t eaddr[(ETHER_ADDR_LEN+1)/2]; 1074 struct dc_desc *sframe; 1075 u_int32_t h, *sp; 1076 struct ifmultiaddr *ifma; 1077 struct ifnet *ifp; 1078 int i; 1079 1080 ifp = sc->dc_ifp; 1081 1082 i = sc->dc_cdata.dc_tx_prod; 1083 DC_INC(sc->dc_cdata.dc_tx_prod, DC_TX_LIST_CNT); 1084 sc->dc_cdata.dc_tx_cnt++; 1085 sframe = &sc->dc_ldata->dc_tx_list[i]; 1086 sp = sc->dc_cdata.dc_sbuf; 1087 bzero(sp, DC_SFRAME_LEN); 1088 1089 sframe->dc_data = htole32(sc->dc_saddr); 1090 sframe->dc_ctl = htole32(DC_SFRAME_LEN | DC_TXCTL_SETUP | 1091 DC_TXCTL_TLINK | DC_FILTER_HASHPERF | DC_TXCTL_FINT); 1092 1093 sc->dc_cdata.dc_tx_chain[i] = (struct mbuf *)sc->dc_cdata.dc_sbuf; 1094 1095 /* If we want promiscuous mode, set the allframes bit. */ 1096 if (ifp->if_flags & IFF_PROMISC) 1097 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC); 1098 else 1099 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC); 1100 1101 if (ifp->if_flags & IFF_ALLMULTI) 1102 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI); 1103 else 1104 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI); 1105 1106 IF_ADDR_LOCK(ifp); 1107 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 1108 if (ifma->ifma_addr->sa_family != AF_LINK) 1109 continue; 1110 h = dc_mchash_le(sc, 1111 LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 1112 sp[h >> 4] |= htole32(1 << (h & 0xF)); 1113 } 1114 IF_ADDR_UNLOCK(ifp); 1115 1116 if (ifp->if_flags & IFF_BROADCAST) { 1117 h = dc_mchash_le(sc, ifp->if_broadcastaddr); 1118 sp[h >> 4] |= htole32(1 << (h & 0xF)); 1119 } 1120 1121 /* Set our MAC address. */ 1122 bcopy(IF_LLADDR(sc->dc_ifp), eaddr, ETHER_ADDR_LEN); 1123 sp[39] = DC_SP_MAC(eaddr[0]); 1124 sp[40] = DC_SP_MAC(eaddr[1]); 1125 sp[41] = DC_SP_MAC(eaddr[2]); 1126 1127 sframe->dc_status = htole32(DC_TXSTAT_OWN); 1128 CSR_WRITE_4(sc, DC_TXSTART, 0xFFFFFFFF); 1129 1130 /* 1131 * The PNIC takes an exceedingly long time to process its 1132 * setup frame; wait 10ms after posting the setup frame 1133 * before proceeding, just so it has time to swallow its 1134 * medicine. 1135 */ 1136 DELAY(10000); 1137 1138 sc->dc_wdog_timer = 5; 1139 } 1140 1141 static void 1142 dc_setfilt_admtek(struct dc_softc *sc) 1143 { 1144 uint8_t eaddr[ETHER_ADDR_LEN]; 1145 struct ifnet *ifp; 1146 struct ifmultiaddr *ifma; 1147 int h = 0; 1148 u_int32_t hashes[2] = { 0, 0 }; 1149 1150 ifp = sc->dc_ifp; 1151 1152 /* Init our MAC address. */ 1153 bcopy(IF_LLADDR(sc->dc_ifp), eaddr, ETHER_ADDR_LEN); 1154 CSR_WRITE_4(sc, DC_AL_PAR0, eaddr[3] << 24 | eaddr[2] << 16 | 1155 eaddr[1] << 8 | eaddr[0]); 1156 CSR_WRITE_4(sc, DC_AL_PAR1, eaddr[5] << 8 | eaddr[4]); 1157 1158 /* If we want promiscuous mode, set the allframes bit. */ 1159 if (ifp->if_flags & IFF_PROMISC) 1160 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC); 1161 else 1162 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC); 1163 1164 if (ifp->if_flags & IFF_ALLMULTI) 1165 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI); 1166 else 1167 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI); 1168 1169 /* First, zot all the existing hash bits. */ 1170 CSR_WRITE_4(sc, DC_AL_MAR0, 0); 1171 CSR_WRITE_4(sc, DC_AL_MAR1, 0); 1172 1173 /* 1174 * If we're already in promisc or allmulti mode, we 1175 * don't have to bother programming the multicast filter. 1176 */ 1177 if (ifp->if_flags & (IFF_PROMISC | IFF_ALLMULTI)) 1178 return; 1179 1180 /* Now program new ones. */ 1181 IF_ADDR_LOCK(ifp); 1182 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 1183 if (ifma->ifma_addr->sa_family != AF_LINK) 1184 continue; 1185 if (DC_IS_CENTAUR(sc)) 1186 h = dc_mchash_le(sc, 1187 LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 1188 else 1189 h = dc_mchash_be( 1190 LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 1191 if (h < 32) 1192 hashes[0] |= (1 << h); 1193 else 1194 hashes[1] |= (1 << (h - 32)); 1195 } 1196 IF_ADDR_UNLOCK(ifp); 1197 1198 CSR_WRITE_4(sc, DC_AL_MAR0, hashes[0]); 1199 CSR_WRITE_4(sc, DC_AL_MAR1, hashes[1]); 1200 } 1201 1202 static void 1203 dc_setfilt_asix(struct dc_softc *sc) 1204 { 1205 uint32_t eaddr[(ETHER_ADDR_LEN+3)/4]; 1206 struct ifnet *ifp; 1207 struct ifmultiaddr *ifma; 1208 int h = 0; 1209 u_int32_t hashes[2] = { 0, 0 }; 1210 1211 ifp = sc->dc_ifp; 1212 1213 /* Init our MAC address. */ 1214 bcopy(IF_LLADDR(sc->dc_ifp), eaddr, ETHER_ADDR_LEN); 1215 CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_PAR0); 1216 CSR_WRITE_4(sc, DC_AX_FILTDATA, eaddr[0]); 1217 CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_PAR1); 1218 CSR_WRITE_4(sc, DC_AX_FILTDATA, eaddr[1]); 1219 1220 /* If we want promiscuous mode, set the allframes bit. */ 1221 if (ifp->if_flags & IFF_PROMISC) 1222 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC); 1223 else 1224 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC); 1225 1226 if (ifp->if_flags & IFF_ALLMULTI) 1227 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI); 1228 else 1229 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI); 1230 1231 /* 1232 * The ASIX chip has a special bit to enable reception 1233 * of broadcast frames. 1234 */ 1235 if (ifp->if_flags & IFF_BROADCAST) 1236 DC_SETBIT(sc, DC_NETCFG, DC_AX_NETCFG_RX_BROAD); 1237 else 1238 DC_CLRBIT(sc, DC_NETCFG, DC_AX_NETCFG_RX_BROAD); 1239 1240 /* first, zot all the existing hash bits */ 1241 CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_MAR0); 1242 CSR_WRITE_4(sc, DC_AX_FILTDATA, 0); 1243 CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_MAR1); 1244 CSR_WRITE_4(sc, DC_AX_FILTDATA, 0); 1245 1246 /* 1247 * If we're already in promisc or allmulti mode, we 1248 * don't have to bother programming the multicast filter. 1249 */ 1250 if (ifp->if_flags & (IFF_PROMISC | IFF_ALLMULTI)) 1251 return; 1252 1253 /* now program new ones */ 1254 IF_ADDR_LOCK(ifp); 1255 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 1256 if (ifma->ifma_addr->sa_family != AF_LINK) 1257 continue; 1258 h = dc_mchash_be(LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 1259 if (h < 32) 1260 hashes[0] |= (1 << h); 1261 else 1262 hashes[1] |= (1 << (h - 32)); 1263 } 1264 IF_ADDR_UNLOCK(ifp); 1265 1266 CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_MAR0); 1267 CSR_WRITE_4(sc, DC_AX_FILTDATA, hashes[0]); 1268 CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_MAR1); 1269 CSR_WRITE_4(sc, DC_AX_FILTDATA, hashes[1]); 1270 } 1271 1272 static void 1273 dc_setfilt_xircom(struct dc_softc *sc) 1274 { 1275 uint16_t eaddr[(ETHER_ADDR_LEN+1)/2]; 1276 struct ifnet *ifp; 1277 struct ifmultiaddr *ifma; 1278 struct dc_desc *sframe; 1279 u_int32_t h, *sp; 1280 int i; 1281 1282 ifp = sc->dc_ifp; 1283 DC_CLRBIT(sc, DC_NETCFG, (DC_NETCFG_TX_ON | DC_NETCFG_RX_ON)); 1284 1285 i = sc->dc_cdata.dc_tx_prod; 1286 DC_INC(sc->dc_cdata.dc_tx_prod, DC_TX_LIST_CNT); 1287 sc->dc_cdata.dc_tx_cnt++; 1288 sframe = &sc->dc_ldata->dc_tx_list[i]; 1289 sp = sc->dc_cdata.dc_sbuf; 1290 bzero(sp, DC_SFRAME_LEN); 1291 1292 sframe->dc_data = htole32(sc->dc_saddr); 1293 sframe->dc_ctl = htole32(DC_SFRAME_LEN | DC_TXCTL_SETUP | 1294 DC_TXCTL_TLINK | DC_FILTER_HASHPERF | DC_TXCTL_FINT); 1295 1296 sc->dc_cdata.dc_tx_chain[i] = (struct mbuf *)sc->dc_cdata.dc_sbuf; 1297 1298 /* If we want promiscuous mode, set the allframes bit. */ 1299 if (ifp->if_flags & IFF_PROMISC) 1300 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC); 1301 else 1302 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC); 1303 1304 if (ifp->if_flags & IFF_ALLMULTI) 1305 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI); 1306 else 1307 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI); 1308 1309 IF_ADDR_LOCK(ifp); 1310 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 1311 if (ifma->ifma_addr->sa_family != AF_LINK) 1312 continue; 1313 h = dc_mchash_le(sc, 1314 LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 1315 sp[h >> 4] |= htole32(1 << (h & 0xF)); 1316 } 1317 IF_ADDR_UNLOCK(ifp); 1318 1319 if (ifp->if_flags & IFF_BROADCAST) { 1320 h = dc_mchash_le(sc, ifp->if_broadcastaddr); 1321 sp[h >> 4] |= htole32(1 << (h & 0xF)); 1322 } 1323 1324 /* Set our MAC address. */ 1325 bcopy(IF_LLADDR(sc->dc_ifp), eaddr, ETHER_ADDR_LEN); 1326 sp[0] = DC_SP_MAC(eaddr[0]); 1327 sp[1] = DC_SP_MAC(eaddr[1]); 1328 sp[2] = DC_SP_MAC(eaddr[2]); 1329 1330 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_TX_ON); 1331 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_ON); 1332 ifp->if_drv_flags |= IFF_DRV_RUNNING; 1333 sframe->dc_status = htole32(DC_TXSTAT_OWN); 1334 CSR_WRITE_4(sc, DC_TXSTART, 0xFFFFFFFF); 1335 1336 /* 1337 * Wait some time... 1338 */ 1339 DELAY(1000); 1340 1341 sc->dc_wdog_timer = 5; 1342 } 1343 1344 static void 1345 dc_setfilt(struct dc_softc *sc) 1346 { 1347 1348 if (DC_IS_INTEL(sc) || DC_IS_MACRONIX(sc) || DC_IS_PNIC(sc) || 1349 DC_IS_PNICII(sc) || DC_IS_DAVICOM(sc) || DC_IS_CONEXANT(sc)) 1350 dc_setfilt_21143(sc); 1351 1352 if (DC_IS_ASIX(sc)) 1353 dc_setfilt_asix(sc); 1354 1355 if (DC_IS_ADMTEK(sc)) 1356 dc_setfilt_admtek(sc); 1357 1358 if (DC_IS_XIRCOM(sc)) 1359 dc_setfilt_xircom(sc); 1360 } 1361 1362 /* 1363 * In order to fiddle with the 'full-duplex' and '100Mbps' bits in 1364 * the netconfig register, we first have to put the transmit and/or 1365 * receive logic in the idle state. 1366 */ 1367 static void 1368 dc_setcfg(struct dc_softc *sc, int media) 1369 { 1370 int i, restart = 0, watchdogreg; 1371 u_int32_t isr; 1372 1373 if (IFM_SUBTYPE(media) == IFM_NONE) 1374 return; 1375 1376 if (CSR_READ_4(sc, DC_NETCFG) & (DC_NETCFG_TX_ON | DC_NETCFG_RX_ON)) { 1377 restart = 1; 1378 DC_CLRBIT(sc, DC_NETCFG, (DC_NETCFG_TX_ON | DC_NETCFG_RX_ON)); 1379 1380 for (i = 0; i < DC_TIMEOUT; i++) { 1381 isr = CSR_READ_4(sc, DC_ISR); 1382 if (isr & DC_ISR_TX_IDLE && 1383 ((isr & DC_ISR_RX_STATE) == DC_RXSTATE_STOPPED || 1384 (isr & DC_ISR_RX_STATE) == DC_RXSTATE_WAIT)) 1385 break; 1386 DELAY(10); 1387 } 1388 1389 if (i == DC_TIMEOUT) { 1390 if (!(isr & DC_ISR_TX_IDLE) && !DC_IS_ASIX(sc)) 1391 device_printf(sc->dc_dev, 1392 "%s: failed to force tx to idle state\n", 1393 __func__); 1394 if (!((isr & DC_ISR_RX_STATE) == DC_RXSTATE_STOPPED || 1395 (isr & DC_ISR_RX_STATE) == DC_RXSTATE_WAIT) && 1396 !(DC_IS_CENTAUR(sc) || DC_IS_CONEXANT(sc) || 1397 (DC_IS_DAVICOM(sc) && pci_get_revid(sc->dc_dev) >= 1398 DC_REVISION_DM9102A))) 1399 device_printf(sc->dc_dev, 1400 "%s: failed to force rx to idle state\n", 1401 __func__); 1402 } 1403 } 1404 1405 if (IFM_SUBTYPE(media) == IFM_100_TX) { 1406 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_SPEEDSEL); 1407 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_HEARTBEAT); 1408 if (sc->dc_pmode == DC_PMODE_MII) { 1409 if (DC_IS_INTEL(sc)) { 1410 /* There's a write enable bit here that reads as 1. */ 1411 watchdogreg = CSR_READ_4(sc, DC_WATCHDOG); 1412 watchdogreg &= ~DC_WDOG_CTLWREN; 1413 watchdogreg |= DC_WDOG_JABBERDIS; 1414 CSR_WRITE_4(sc, DC_WATCHDOG, watchdogreg); 1415 } else { 1416 DC_SETBIT(sc, DC_WATCHDOG, DC_WDOG_JABBERDIS); 1417 } 1418 DC_CLRBIT(sc, DC_NETCFG, (DC_NETCFG_PCS | 1419 DC_NETCFG_PORTSEL | DC_NETCFG_SCRAMBLER)); 1420 if (sc->dc_type == DC_TYPE_98713) 1421 DC_SETBIT(sc, DC_NETCFG, (DC_NETCFG_PCS | 1422 DC_NETCFG_SCRAMBLER)); 1423 if (!DC_IS_DAVICOM(sc)) 1424 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL); 1425 DC_CLRBIT(sc, DC_10BTCTRL, 0xFFFF); 1426 if (DC_IS_INTEL(sc)) 1427 dc_apply_fixup(sc, IFM_AUTO); 1428 } else { 1429 if (DC_IS_PNIC(sc)) { 1430 DC_PN_GPIO_SETBIT(sc, DC_PN_GPIO_SPEEDSEL); 1431 DC_PN_GPIO_SETBIT(sc, DC_PN_GPIO_100TX_LOOP); 1432 DC_SETBIT(sc, DC_PN_NWAY, DC_PN_NWAY_SPEEDSEL); 1433 } 1434 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL); 1435 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PCS); 1436 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_SCRAMBLER); 1437 if (DC_IS_INTEL(sc)) 1438 dc_apply_fixup(sc, 1439 (media & IFM_GMASK) == IFM_FDX ? 1440 IFM_100_TX | IFM_FDX : IFM_100_TX); 1441 } 1442 } 1443 1444 if (IFM_SUBTYPE(media) == IFM_10_T) { 1445 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_SPEEDSEL); 1446 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_HEARTBEAT); 1447 if (sc->dc_pmode == DC_PMODE_MII) { 1448 /* There's a write enable bit here that reads as 1. */ 1449 if (DC_IS_INTEL(sc)) { 1450 watchdogreg = CSR_READ_4(sc, DC_WATCHDOG); 1451 watchdogreg &= ~DC_WDOG_CTLWREN; 1452 watchdogreg |= DC_WDOG_JABBERDIS; 1453 CSR_WRITE_4(sc, DC_WATCHDOG, watchdogreg); 1454 } else { 1455 DC_SETBIT(sc, DC_WATCHDOG, DC_WDOG_JABBERDIS); 1456 } 1457 DC_CLRBIT(sc, DC_NETCFG, (DC_NETCFG_PCS | 1458 DC_NETCFG_PORTSEL | DC_NETCFG_SCRAMBLER)); 1459 if (sc->dc_type == DC_TYPE_98713) 1460 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PCS); 1461 if (!DC_IS_DAVICOM(sc)) 1462 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL); 1463 DC_CLRBIT(sc, DC_10BTCTRL, 0xFFFF); 1464 if (DC_IS_INTEL(sc)) 1465 dc_apply_fixup(sc, IFM_AUTO); 1466 } else { 1467 if (DC_IS_PNIC(sc)) { 1468 DC_PN_GPIO_CLRBIT(sc, DC_PN_GPIO_SPEEDSEL); 1469 DC_PN_GPIO_SETBIT(sc, DC_PN_GPIO_100TX_LOOP); 1470 DC_CLRBIT(sc, DC_PN_NWAY, DC_PN_NWAY_SPEEDSEL); 1471 } 1472 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL); 1473 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_PCS); 1474 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_SCRAMBLER); 1475 if (DC_IS_INTEL(sc)) { 1476 DC_CLRBIT(sc, DC_SIARESET, DC_SIA_RESET); 1477 DC_CLRBIT(sc, DC_10BTCTRL, 0xFFFF); 1478 if ((media & IFM_GMASK) == IFM_FDX) 1479 DC_SETBIT(sc, DC_10BTCTRL, 0x7F3D); 1480 else 1481 DC_SETBIT(sc, DC_10BTCTRL, 0x7F3F); 1482 DC_SETBIT(sc, DC_SIARESET, DC_SIA_RESET); 1483 DC_CLRBIT(sc, DC_10BTCTRL, 1484 DC_TCTL_AUTONEGENBL); 1485 dc_apply_fixup(sc, 1486 (media & IFM_GMASK) == IFM_FDX ? 1487 IFM_10_T | IFM_FDX : IFM_10_T); 1488 DELAY(20000); 1489 } 1490 } 1491 } 1492 1493 /* 1494 * If this is a Davicom DM9102A card with a DM9801 HomePNA 1495 * PHY and we want HomePNA mode, set the portsel bit to turn 1496 * on the external MII port. 1497 */ 1498 if (DC_IS_DAVICOM(sc)) { 1499 if (IFM_SUBTYPE(media) == IFM_HPNA_1) { 1500 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL); 1501 sc->dc_link = 1; 1502 } else { 1503 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL); 1504 } 1505 } 1506 1507 if ((media & IFM_GMASK) == IFM_FDX) { 1508 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_FULLDUPLEX); 1509 if (sc->dc_pmode == DC_PMODE_SYM && DC_IS_PNIC(sc)) 1510 DC_SETBIT(sc, DC_PN_NWAY, DC_PN_NWAY_DUPLEX); 1511 } else { 1512 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_FULLDUPLEX); 1513 if (sc->dc_pmode == DC_PMODE_SYM && DC_IS_PNIC(sc)) 1514 DC_CLRBIT(sc, DC_PN_NWAY, DC_PN_NWAY_DUPLEX); 1515 } 1516 1517 if (restart) 1518 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_TX_ON | DC_NETCFG_RX_ON); 1519 } 1520 1521 static void 1522 dc_reset(struct dc_softc *sc) 1523 { 1524 int i; 1525 1526 DC_SETBIT(sc, DC_BUSCTL, DC_BUSCTL_RESET); 1527 1528 for (i = 0; i < DC_TIMEOUT; i++) { 1529 DELAY(10); 1530 if (!(CSR_READ_4(sc, DC_BUSCTL) & DC_BUSCTL_RESET)) 1531 break; 1532 } 1533 1534 if (DC_IS_ASIX(sc) || DC_IS_ADMTEK(sc) || DC_IS_CONEXANT(sc) || 1535 DC_IS_XIRCOM(sc) || DC_IS_INTEL(sc)) { 1536 DELAY(10000); 1537 DC_CLRBIT(sc, DC_BUSCTL, DC_BUSCTL_RESET); 1538 i = 0; 1539 } 1540 1541 if (i == DC_TIMEOUT) 1542 device_printf(sc->dc_dev, "reset never completed!\n"); 1543 1544 /* Wait a little while for the chip to get its brains in order. */ 1545 DELAY(1000); 1546 1547 CSR_WRITE_4(sc, DC_IMR, 0x00000000); 1548 CSR_WRITE_4(sc, DC_BUSCTL, 0x00000000); 1549 CSR_WRITE_4(sc, DC_NETCFG, 0x00000000); 1550 1551 /* 1552 * Bring the SIA out of reset. In some cases, it looks 1553 * like failing to unreset the SIA soon enough gets it 1554 * into a state where it will never come out of reset 1555 * until we reset the whole chip again. 1556 */ 1557 if (DC_IS_INTEL(sc)) { 1558 DC_SETBIT(sc, DC_SIARESET, DC_SIA_RESET); 1559 CSR_WRITE_4(sc, DC_10BTCTRL, 0); 1560 CSR_WRITE_4(sc, DC_WATCHDOG, 0); 1561 } 1562 } 1563 1564 static const struct dc_type * 1565 dc_devtype(device_t dev) 1566 { 1567 const struct dc_type *t; 1568 u_int32_t devid; 1569 u_int8_t rev; 1570 1571 t = dc_devs; 1572 devid = pci_get_devid(dev); 1573 rev = pci_get_revid(dev); 1574 1575 while (t->dc_name != NULL) { 1576 if (devid == t->dc_devid && rev >= t->dc_minrev) 1577 return (t); 1578 t++; 1579 } 1580 1581 return (NULL); 1582 } 1583 1584 /* 1585 * Probe for a 21143 or clone chip. Check the PCI vendor and device 1586 * IDs against our list and return a device name if we find a match. 1587 * We do a little bit of extra work to identify the exact type of 1588 * chip. The MX98713 and MX98713A have the same PCI vendor/device ID, 1589 * but different revision IDs. The same is true for 98715/98715A 1590 * chips and the 98725, as well as the ASIX and ADMtek chips. In some 1591 * cases, the exact chip revision affects driver behavior. 1592 */ 1593 static int 1594 dc_probe(device_t dev) 1595 { 1596 const struct dc_type *t; 1597 1598 t = dc_devtype(dev); 1599 1600 if (t != NULL) { 1601 device_set_desc(dev, t->dc_name); 1602 return (BUS_PROBE_DEFAULT); 1603 } 1604 1605 return (ENXIO); 1606 } 1607 1608 static void 1609 dc_apply_fixup(struct dc_softc *sc, int media) 1610 { 1611 struct dc_mediainfo *m; 1612 u_int8_t *p; 1613 int i; 1614 u_int32_t reg; 1615 1616 m = sc->dc_mi; 1617 1618 while (m != NULL) { 1619 if (m->dc_media == media) 1620 break; 1621 m = m->dc_next; 1622 } 1623 1624 if (m == NULL) 1625 return; 1626 1627 for (i = 0, p = m->dc_reset_ptr; i < m->dc_reset_len; i++, p += 2) { 1628 reg = (p[0] | (p[1] << 8)) << 16; 1629 CSR_WRITE_4(sc, DC_WATCHDOG, reg); 1630 } 1631 1632 for (i = 0, p = m->dc_gp_ptr; i < m->dc_gp_len; i++, p += 2) { 1633 reg = (p[0] | (p[1] << 8)) << 16; 1634 CSR_WRITE_4(sc, DC_WATCHDOG, reg); 1635 } 1636 } 1637 1638 static void 1639 dc_decode_leaf_sia(struct dc_softc *sc, struct dc_eblock_sia *l) 1640 { 1641 struct dc_mediainfo *m; 1642 1643 m = malloc(sizeof(struct dc_mediainfo), M_DEVBUF, M_NOWAIT | M_ZERO); 1644 switch (l->dc_sia_code & ~DC_SIA_CODE_EXT) { 1645 case DC_SIA_CODE_10BT: 1646 m->dc_media = IFM_10_T; 1647 break; 1648 case DC_SIA_CODE_10BT_FDX: 1649 m->dc_media = IFM_10_T | IFM_FDX; 1650 break; 1651 case DC_SIA_CODE_10B2: 1652 m->dc_media = IFM_10_2; 1653 break; 1654 case DC_SIA_CODE_10B5: 1655 m->dc_media = IFM_10_5; 1656 break; 1657 default: 1658 break; 1659 } 1660 1661 /* 1662 * We need to ignore CSR13, CSR14, CSR15 for SIA mode. 1663 * Things apparently already work for cards that do 1664 * supply Media Specific Data. 1665 */ 1666 if (l->dc_sia_code & DC_SIA_CODE_EXT) { 1667 m->dc_gp_len = 2; 1668 m->dc_gp_ptr = 1669 (u_int8_t *)&l->dc_un.dc_sia_ext.dc_sia_gpio_ctl; 1670 } else { 1671 m->dc_gp_len = 2; 1672 m->dc_gp_ptr = 1673 (u_int8_t *)&l->dc_un.dc_sia_noext.dc_sia_gpio_ctl; 1674 } 1675 1676 m->dc_next = sc->dc_mi; 1677 sc->dc_mi = m; 1678 1679 sc->dc_pmode = DC_PMODE_SIA; 1680 } 1681 1682 static void 1683 dc_decode_leaf_sym(struct dc_softc *sc, struct dc_eblock_sym *l) 1684 { 1685 struct dc_mediainfo *m; 1686 1687 m = malloc(sizeof(struct dc_mediainfo), M_DEVBUF, M_NOWAIT | M_ZERO); 1688 if (l->dc_sym_code == DC_SYM_CODE_100BT) 1689 m->dc_media = IFM_100_TX; 1690 1691 if (l->dc_sym_code == DC_SYM_CODE_100BT_FDX) 1692 m->dc_media = IFM_100_TX | IFM_FDX; 1693 1694 m->dc_gp_len = 2; 1695 m->dc_gp_ptr = (u_int8_t *)&l->dc_sym_gpio_ctl; 1696 1697 m->dc_next = sc->dc_mi; 1698 sc->dc_mi = m; 1699 1700 sc->dc_pmode = DC_PMODE_SYM; 1701 } 1702 1703 static void 1704 dc_decode_leaf_mii(struct dc_softc *sc, struct dc_eblock_mii *l) 1705 { 1706 struct dc_mediainfo *m; 1707 u_int8_t *p; 1708 1709 m = malloc(sizeof(struct dc_mediainfo), M_DEVBUF, M_NOWAIT | M_ZERO); 1710 /* We abuse IFM_AUTO to represent MII. */ 1711 m->dc_media = IFM_AUTO; 1712 m->dc_gp_len = l->dc_gpr_len; 1713 1714 p = (u_int8_t *)l; 1715 p += sizeof(struct dc_eblock_mii); 1716 m->dc_gp_ptr = p; 1717 p += 2 * l->dc_gpr_len; 1718 m->dc_reset_len = *p; 1719 p++; 1720 m->dc_reset_ptr = p; 1721 1722 m->dc_next = sc->dc_mi; 1723 sc->dc_mi = m; 1724 } 1725 1726 static void 1727 dc_read_srom(struct dc_softc *sc, int bits) 1728 { 1729 int size; 1730 1731 size = 2 << bits; 1732 sc->dc_srom = malloc(size, M_DEVBUF, M_NOWAIT); 1733 dc_read_eeprom(sc, (caddr_t)sc->dc_srom, 0, (size / 2), 0); 1734 } 1735 1736 static void 1737 dc_parse_21143_srom(struct dc_softc *sc) 1738 { 1739 struct dc_leaf_hdr *lhdr; 1740 struct dc_eblock_hdr *hdr; 1741 int have_mii, i, loff; 1742 char *ptr; 1743 1744 have_mii = 0; 1745 loff = sc->dc_srom[27]; 1746 lhdr = (struct dc_leaf_hdr *)&(sc->dc_srom[loff]); 1747 1748 ptr = (char *)lhdr; 1749 ptr += sizeof(struct dc_leaf_hdr) - 1; 1750 /* 1751 * Look if we got a MII media block. 1752 */ 1753 for (i = 0; i < lhdr->dc_mcnt; i++) { 1754 hdr = (struct dc_eblock_hdr *)ptr; 1755 if (hdr->dc_type == DC_EBLOCK_MII) 1756 have_mii++; 1757 1758 ptr += (hdr->dc_len & 0x7F); 1759 ptr++; 1760 } 1761 1762 /* 1763 * Do the same thing again. Only use SIA and SYM media 1764 * blocks if no MII media block is available. 1765 */ 1766 ptr = (char *)lhdr; 1767 ptr += sizeof(struct dc_leaf_hdr) - 1; 1768 for (i = 0; i < lhdr->dc_mcnt; i++) { 1769 hdr = (struct dc_eblock_hdr *)ptr; 1770 switch (hdr->dc_type) { 1771 case DC_EBLOCK_MII: 1772 dc_decode_leaf_mii(sc, (struct dc_eblock_mii *)hdr); 1773 break; 1774 case DC_EBLOCK_SIA: 1775 if (! have_mii) 1776 dc_decode_leaf_sia(sc, 1777 (struct dc_eblock_sia *)hdr); 1778 break; 1779 case DC_EBLOCK_SYM: 1780 if (! have_mii) 1781 dc_decode_leaf_sym(sc, 1782 (struct dc_eblock_sym *)hdr); 1783 break; 1784 default: 1785 /* Don't care. Yet. */ 1786 break; 1787 } 1788 ptr += (hdr->dc_len & 0x7F); 1789 ptr++; 1790 } 1791 } 1792 1793 static void 1794 dc_dma_map_addr(void *arg, bus_dma_segment_t *segs, int nseg, int error) 1795 { 1796 u_int32_t *paddr; 1797 1798 KASSERT(nseg == 1, 1799 ("%s: wrong number of segments (%d)", __func__, nseg)); 1800 paddr = arg; 1801 *paddr = segs->ds_addr; 1802 } 1803 1804 /* 1805 * Attach the interface. Allocate softc structures, do ifmedia 1806 * setup and ethernet/BPF attach. 1807 */ 1808 static int 1809 dc_attach(device_t dev) 1810 { 1811 int tmp = 0; 1812 uint32_t eaddr[(ETHER_ADDR_LEN+3)/4]; 1813 u_int32_t command; 1814 struct dc_softc *sc; 1815 struct ifnet *ifp; 1816 u_int32_t reg, revision; 1817 int error = 0, rid, mac_offset; 1818 int i; 1819 u_int8_t *mac; 1820 1821 sc = device_get_softc(dev); 1822 sc->dc_dev = dev; 1823 1824 mtx_init(&sc->dc_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 1825 MTX_DEF); 1826 1827 /* 1828 * Map control/status registers. 1829 */ 1830 pci_enable_busmaster(dev); 1831 1832 rid = DC_RID; 1833 sc->dc_res = bus_alloc_resource_any(dev, DC_RES, &rid, RF_ACTIVE); 1834 1835 if (sc->dc_res == NULL) { 1836 device_printf(dev, "couldn't map ports/memory\n"); 1837 error = ENXIO; 1838 goto fail; 1839 } 1840 1841 sc->dc_btag = rman_get_bustag(sc->dc_res); 1842 sc->dc_bhandle = rman_get_bushandle(sc->dc_res); 1843 1844 /* Allocate interrupt. */ 1845 rid = 0; 1846 sc->dc_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 1847 RF_SHAREABLE | RF_ACTIVE); 1848 1849 if (sc->dc_irq == NULL) { 1850 device_printf(dev, "couldn't map interrupt\n"); 1851 error = ENXIO; 1852 goto fail; 1853 } 1854 1855 /* Need this info to decide on a chip type. */ 1856 sc->dc_info = dc_devtype(dev); 1857 revision = pci_get_revid(dev); 1858 1859 /* Get the eeprom width, but PNIC and XIRCOM have diff eeprom */ 1860 if (sc->dc_info->dc_devid != 1861 DC_DEVID(DC_VENDORID_LO, DC_DEVICEID_82C168) && 1862 sc->dc_info->dc_devid != 1863 DC_DEVID(DC_VENDORID_XIRCOM, DC_DEVICEID_X3201)) 1864 dc_eeprom_width(sc); 1865 1866 switch (sc->dc_info->dc_devid) { 1867 case DC_DEVID(DC_VENDORID_DEC, DC_DEVICEID_21143): 1868 sc->dc_type = DC_TYPE_21143; 1869 sc->dc_flags |= DC_TX_POLL | DC_TX_USE_TX_INTR; 1870 sc->dc_flags |= DC_REDUCED_MII_POLL; 1871 /* Save EEPROM contents so we can parse them later. */ 1872 dc_read_srom(sc, sc->dc_romwidth); 1873 break; 1874 case DC_DEVID(DC_VENDORID_DAVICOM, DC_DEVICEID_DM9009): 1875 case DC_DEVID(DC_VENDORID_DAVICOM, DC_DEVICEID_DM9100): 1876 case DC_DEVID(DC_VENDORID_DAVICOM, DC_DEVICEID_DM9102): 1877 sc->dc_type = DC_TYPE_DM9102; 1878 sc->dc_flags |= DC_TX_COALESCE | DC_TX_INTR_ALWAYS; 1879 sc->dc_flags |= DC_REDUCED_MII_POLL | DC_TX_STORENFWD; 1880 sc->dc_flags |= DC_TX_ALIGN; 1881 sc->dc_pmode = DC_PMODE_MII; 1882 1883 /* Increase the latency timer value. */ 1884 pci_write_config(dev, PCIR_LATTIMER, 0x80, 1); 1885 break; 1886 case DC_DEVID(DC_VENDORID_ADMTEK, DC_DEVICEID_AL981): 1887 sc->dc_type = DC_TYPE_AL981; 1888 sc->dc_flags |= DC_TX_USE_TX_INTR; 1889 sc->dc_flags |= DC_TX_ADMTEK_WAR; 1890 sc->dc_pmode = DC_PMODE_MII; 1891 dc_read_srom(sc, sc->dc_romwidth); 1892 break; 1893 case DC_DEVID(DC_VENDORID_ADMTEK, DC_DEVICEID_AN985): 1894 case DC_DEVID(DC_VENDORID_ADMTEK, DC_DEVICEID_ADM9511): 1895 case DC_DEVID(DC_VENDORID_ADMTEK, DC_DEVICEID_ADM9513): 1896 case DC_DEVID(DC_VENDORID_DLINK, DC_DEVICEID_DRP32TXD): 1897 case DC_DEVID(DC_VENDORID_ADMTEK, DC_DEVICEID_FA511): 1898 case DC_DEVID(DC_VENDORID_ABOCOM, DC_DEVICEID_FE2500): 1899 case DC_DEVID(DC_VENDORID_ABOCOM, DC_DEVICEID_FE2500MX): 1900 case DC_DEVID(DC_VENDORID_ACCTON, DC_DEVICEID_EN2242): 1901 case DC_DEVID(DC_VENDORID_HAWKING, DC_DEVICEID_HAWKING_PN672TX): 1902 case DC_DEVID(DC_VENDORID_PLANEX, DC_DEVICEID_FNW3602T): 1903 case DC_DEVID(DC_VENDORID_3COM, DC_DEVICEID_3CSOHOB): 1904 case DC_DEVID(DC_VENDORID_MICROSOFT, DC_DEVICEID_MSMN120): 1905 case DC_DEVID(DC_VENDORID_MICROSOFT, DC_DEVICEID_MSMN130): 1906 case DC_DEVID(DC_VENDORID_LINKSYS, DC_DEVICEID_PCMPC200_AB08): 1907 case DC_DEVID(DC_VENDORID_LINKSYS, DC_DEVICEID_PCMPC200_AB09): 1908 sc->dc_type = DC_TYPE_AN985; 1909 sc->dc_flags |= DC_64BIT_HASH; 1910 sc->dc_flags |= DC_TX_USE_TX_INTR; 1911 sc->dc_flags |= DC_TX_ADMTEK_WAR; 1912 sc->dc_pmode = DC_PMODE_MII; 1913 /* Don't read SROM for - auto-loaded on reset */ 1914 break; 1915 case DC_DEVID(DC_VENDORID_MX, DC_DEVICEID_98713): 1916 case DC_DEVID(DC_VENDORID_CP, DC_DEVICEID_98713_CP): 1917 if (revision < DC_REVISION_98713A) { 1918 sc->dc_type = DC_TYPE_98713; 1919 } 1920 if (revision >= DC_REVISION_98713A) { 1921 sc->dc_type = DC_TYPE_98713A; 1922 sc->dc_flags |= DC_21143_NWAY; 1923 } 1924 sc->dc_flags |= DC_REDUCED_MII_POLL; 1925 sc->dc_flags |= DC_TX_POLL | DC_TX_USE_TX_INTR; 1926 break; 1927 case DC_DEVID(DC_VENDORID_MX, DC_DEVICEID_987x5): 1928 case DC_DEVID(DC_VENDORID_ACCTON, DC_DEVICEID_EN1217): 1929 /* 1930 * Macronix MX98715AEC-C/D/E parts have only a 1931 * 128-bit hash table. We need to deal with these 1932 * in the same manner as the PNIC II so that we 1933 * get the right number of bits out of the 1934 * CRC routine. 1935 */ 1936 if (revision >= DC_REVISION_98715AEC_C && 1937 revision < DC_REVISION_98725) 1938 sc->dc_flags |= DC_128BIT_HASH; 1939 sc->dc_type = DC_TYPE_987x5; 1940 sc->dc_flags |= DC_TX_POLL | DC_TX_USE_TX_INTR; 1941 sc->dc_flags |= DC_REDUCED_MII_POLL | DC_21143_NWAY; 1942 break; 1943 case DC_DEVID(DC_VENDORID_MX, DC_DEVICEID_98727): 1944 sc->dc_type = DC_TYPE_987x5; 1945 sc->dc_flags |= DC_TX_POLL | DC_TX_USE_TX_INTR; 1946 sc->dc_flags |= DC_REDUCED_MII_POLL | DC_21143_NWAY; 1947 break; 1948 case DC_DEVID(DC_VENDORID_LO, DC_DEVICEID_82C115): 1949 sc->dc_type = DC_TYPE_PNICII; 1950 sc->dc_flags |= DC_TX_POLL | DC_TX_USE_TX_INTR | DC_128BIT_HASH; 1951 sc->dc_flags |= DC_REDUCED_MII_POLL | DC_21143_NWAY; 1952 break; 1953 case DC_DEVID(DC_VENDORID_LO, DC_DEVICEID_82C168): 1954 sc->dc_type = DC_TYPE_PNIC; 1955 sc->dc_flags |= DC_TX_STORENFWD | DC_TX_INTR_ALWAYS; 1956 sc->dc_flags |= DC_PNIC_RX_BUG_WAR; 1957 sc->dc_pnic_rx_buf = malloc(DC_RXLEN * 5, M_DEVBUF, M_NOWAIT); 1958 if (revision < DC_REVISION_82C169) 1959 sc->dc_pmode = DC_PMODE_SYM; 1960 break; 1961 case DC_DEVID(DC_VENDORID_ASIX, DC_DEVICEID_AX88140A): 1962 sc->dc_type = DC_TYPE_ASIX; 1963 sc->dc_flags |= DC_TX_USE_TX_INTR | DC_TX_INTR_FIRSTFRAG; 1964 sc->dc_flags |= DC_REDUCED_MII_POLL; 1965 sc->dc_pmode = DC_PMODE_MII; 1966 break; 1967 case DC_DEVID(DC_VENDORID_XIRCOM, DC_DEVICEID_X3201): 1968 sc->dc_type = DC_TYPE_XIRCOM; 1969 sc->dc_flags |= DC_TX_INTR_ALWAYS | DC_TX_COALESCE | 1970 DC_TX_ALIGN; 1971 /* 1972 * We don't actually need to coalesce, but we're doing 1973 * it to obtain a double word aligned buffer. 1974 * The DC_TX_COALESCE flag is required. 1975 */ 1976 sc->dc_pmode = DC_PMODE_MII; 1977 break; 1978 case DC_DEVID(DC_VENDORID_CONEXANT, DC_DEVICEID_RS7112): 1979 sc->dc_type = DC_TYPE_CONEXANT; 1980 sc->dc_flags |= DC_TX_INTR_ALWAYS; 1981 sc->dc_flags |= DC_REDUCED_MII_POLL; 1982 sc->dc_pmode = DC_PMODE_MII; 1983 dc_read_srom(sc, sc->dc_romwidth); 1984 break; 1985 default: 1986 device_printf(dev, "unknown device: %x\n", 1987 sc->dc_info->dc_devid); 1988 break; 1989 } 1990 1991 /* Save the cache line size. */ 1992 if (DC_IS_DAVICOM(sc)) 1993 sc->dc_cachesize = 0; 1994 else 1995 sc->dc_cachesize = pci_get_cachelnsz(dev); 1996 1997 /* Reset the adapter. */ 1998 dc_reset(sc); 1999 2000 /* Take 21143 out of snooze mode */ 2001 if (DC_IS_INTEL(sc) || DC_IS_XIRCOM(sc)) { 2002 command = pci_read_config(dev, DC_PCI_CFDD, 4); 2003 command &= ~(DC_CFDD_SNOOZE_MODE | DC_CFDD_SLEEP_MODE); 2004 pci_write_config(dev, DC_PCI_CFDD, command, 4); 2005 } 2006 2007 /* 2008 * Try to learn something about the supported media. 2009 * We know that ASIX and ADMtek and Davicom devices 2010 * will *always* be using MII media, so that's a no-brainer. 2011 * The tricky ones are the Macronix/PNIC II and the 2012 * Intel 21143. 2013 */ 2014 if (DC_IS_INTEL(sc)) 2015 dc_parse_21143_srom(sc); 2016 else if (DC_IS_MACRONIX(sc) || DC_IS_PNICII(sc)) { 2017 if (sc->dc_type == DC_TYPE_98713) 2018 sc->dc_pmode = DC_PMODE_MII; 2019 else 2020 sc->dc_pmode = DC_PMODE_SYM; 2021 } else if (!sc->dc_pmode) 2022 sc->dc_pmode = DC_PMODE_MII; 2023 2024 /* 2025 * Get station address from the EEPROM. 2026 */ 2027 switch(sc->dc_type) { 2028 case DC_TYPE_98713: 2029 case DC_TYPE_98713A: 2030 case DC_TYPE_987x5: 2031 case DC_TYPE_PNICII: 2032 dc_read_eeprom(sc, (caddr_t)&mac_offset, 2033 (DC_EE_NODEADDR_OFFSET / 2), 1, 0); 2034 dc_read_eeprom(sc, (caddr_t)&eaddr, (mac_offset / 2), 3, 0); 2035 break; 2036 case DC_TYPE_PNIC: 2037 dc_read_eeprom(sc, (caddr_t)&eaddr, 0, 3, 1); 2038 break; 2039 case DC_TYPE_DM9102: 2040 dc_read_eeprom(sc, (caddr_t)&eaddr, DC_EE_NODEADDR, 3, 0); 2041 #ifdef __sparc64__ 2042 /* 2043 * If this is an onboard dc(4) the station address read from 2044 * the EEPROM is all zero and we have to get it from the FCode. 2045 */ 2046 if (eaddr[0] == 0 && (eaddr[1] & ~0xffff) == 0) 2047 OF_getetheraddr(dev, (caddr_t)&eaddr); 2048 #endif 2049 break; 2050 case DC_TYPE_21143: 2051 case DC_TYPE_ASIX: 2052 dc_read_eeprom(sc, (caddr_t)&eaddr, DC_EE_NODEADDR, 3, 0); 2053 break; 2054 case DC_TYPE_AL981: 2055 case DC_TYPE_AN985: 2056 reg = CSR_READ_4(sc, DC_AL_PAR0); 2057 mac = (uint8_t *)&eaddr[0]; 2058 mac[0] = (reg >> 0) & 0xff; 2059 mac[1] = (reg >> 8) & 0xff; 2060 mac[2] = (reg >> 16) & 0xff; 2061 mac[3] = (reg >> 24) & 0xff; 2062 reg = CSR_READ_4(sc, DC_AL_PAR1); 2063 mac[4] = (reg >> 0) & 0xff; 2064 mac[5] = (reg >> 8) & 0xff; 2065 break; 2066 case DC_TYPE_CONEXANT: 2067 bcopy(sc->dc_srom + DC_CONEXANT_EE_NODEADDR, &eaddr, 2068 ETHER_ADDR_LEN); 2069 break; 2070 case DC_TYPE_XIRCOM: 2071 /* The MAC comes from the CIS. */ 2072 mac = pci_get_ether(dev); 2073 if (!mac) { 2074 device_printf(dev, "No station address in CIS!\n"); 2075 error = ENXIO; 2076 goto fail; 2077 } 2078 bcopy(mac, eaddr, ETHER_ADDR_LEN); 2079 break; 2080 default: 2081 dc_read_eeprom(sc, (caddr_t)&eaddr, DC_EE_NODEADDR, 3, 0); 2082 break; 2083 } 2084 2085 /* Allocate a busdma tag and DMA safe memory for TX/RX descriptors. */ 2086 error = bus_dma_tag_create(bus_get_dma_tag(dev), PAGE_SIZE, 0, 2087 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL, 2088 sizeof(struct dc_list_data), 1, sizeof(struct dc_list_data), 2089 0, NULL, NULL, &sc->dc_ltag); 2090 if (error) { 2091 device_printf(dev, "failed to allocate busdma tag\n"); 2092 error = ENXIO; 2093 goto fail; 2094 } 2095 error = bus_dmamem_alloc(sc->dc_ltag, (void **)&sc->dc_ldata, 2096 BUS_DMA_NOWAIT | BUS_DMA_ZERO, &sc->dc_lmap); 2097 if (error) { 2098 device_printf(dev, "failed to allocate DMA safe memory\n"); 2099 error = ENXIO; 2100 goto fail; 2101 } 2102 error = bus_dmamap_load(sc->dc_ltag, sc->dc_lmap, sc->dc_ldata, 2103 sizeof(struct dc_list_data), dc_dma_map_addr, &sc->dc_laddr, 2104 BUS_DMA_NOWAIT); 2105 if (error) { 2106 device_printf(dev, "cannot get address of the descriptors\n"); 2107 error = ENXIO; 2108 goto fail; 2109 } 2110 2111 /* 2112 * Allocate a busdma tag and DMA safe memory for the multicast 2113 * setup frame. 2114 */ 2115 error = bus_dma_tag_create(bus_get_dma_tag(dev), PAGE_SIZE, 0, 2116 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL, 2117 DC_SFRAME_LEN + DC_MIN_FRAMELEN, 1, DC_SFRAME_LEN + DC_MIN_FRAMELEN, 2118 0, NULL, NULL, &sc->dc_stag); 2119 if (error) { 2120 device_printf(dev, "failed to allocate busdma tag\n"); 2121 error = ENXIO; 2122 goto fail; 2123 } 2124 error = bus_dmamem_alloc(sc->dc_stag, (void **)&sc->dc_cdata.dc_sbuf, 2125 BUS_DMA_NOWAIT, &sc->dc_smap); 2126 if (error) { 2127 device_printf(dev, "failed to allocate DMA safe memory\n"); 2128 error = ENXIO; 2129 goto fail; 2130 } 2131 error = bus_dmamap_load(sc->dc_stag, sc->dc_smap, sc->dc_cdata.dc_sbuf, 2132 DC_SFRAME_LEN, dc_dma_map_addr, &sc->dc_saddr, BUS_DMA_NOWAIT); 2133 if (error) { 2134 device_printf(dev, "cannot get address of the descriptors\n"); 2135 error = ENXIO; 2136 goto fail; 2137 } 2138 2139 /* Allocate a busdma tag for mbufs. */ 2140 error = bus_dma_tag_create(bus_get_dma_tag(dev), 1, 0, 2141 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL, 2142 MCLBYTES * DC_MAXFRAGS, DC_MAXFRAGS, MCLBYTES, 2143 0, NULL, NULL, &sc->dc_mtag); 2144 if (error) { 2145 device_printf(dev, "failed to allocate busdma tag\n"); 2146 error = ENXIO; 2147 goto fail; 2148 } 2149 2150 /* Create the TX/RX busdma maps. */ 2151 for (i = 0; i < DC_TX_LIST_CNT; i++) { 2152 error = bus_dmamap_create(sc->dc_mtag, 0, 2153 &sc->dc_cdata.dc_tx_map[i]); 2154 if (error) { 2155 device_printf(dev, "failed to init TX ring\n"); 2156 error = ENXIO; 2157 goto fail; 2158 } 2159 } 2160 for (i = 0; i < DC_RX_LIST_CNT; i++) { 2161 error = bus_dmamap_create(sc->dc_mtag, 0, 2162 &sc->dc_cdata.dc_rx_map[i]); 2163 if (error) { 2164 device_printf(dev, "failed to init RX ring\n"); 2165 error = ENXIO; 2166 goto fail; 2167 } 2168 } 2169 error = bus_dmamap_create(sc->dc_mtag, 0, &sc->dc_sparemap); 2170 if (error) { 2171 device_printf(dev, "failed to init RX ring\n"); 2172 error = ENXIO; 2173 goto fail; 2174 } 2175 2176 ifp = sc->dc_ifp = if_alloc(IFT_ETHER); 2177 if (ifp == NULL) { 2178 device_printf(dev, "can not if_alloc()\n"); 2179 error = ENOSPC; 2180 goto fail; 2181 } 2182 ifp->if_softc = sc; 2183 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 2184 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 2185 ifp->if_ioctl = dc_ioctl; 2186 ifp->if_start = dc_start; 2187 ifp->if_init = dc_init; 2188 IFQ_SET_MAXLEN(&ifp->if_snd, DC_TX_LIST_CNT - 1); 2189 ifp->if_snd.ifq_drv_maxlen = DC_TX_LIST_CNT - 1; 2190 IFQ_SET_READY(&ifp->if_snd); 2191 2192 /* 2193 * Do MII setup. If this is a 21143, check for a PHY on the 2194 * MII bus after applying any necessary fixups to twiddle the 2195 * GPIO bits. If we don't end up finding a PHY, restore the 2196 * old selection (SIA only or SIA/SYM) and attach the dcphy 2197 * driver instead. 2198 */ 2199 if (DC_IS_INTEL(sc)) { 2200 dc_apply_fixup(sc, IFM_AUTO); 2201 tmp = sc->dc_pmode; 2202 sc->dc_pmode = DC_PMODE_MII; 2203 } 2204 2205 /* 2206 * Setup General Purpose port mode and data so the tulip can talk 2207 * to the MII. This needs to be done before mii_phy_probe so that 2208 * we can actually see them. 2209 */ 2210 if (DC_IS_XIRCOM(sc)) { 2211 CSR_WRITE_4(sc, DC_SIAGP, DC_SIAGP_WRITE_EN | DC_SIAGP_INT1_EN | 2212 DC_SIAGP_MD_GP2_OUTPUT | DC_SIAGP_MD_GP0_OUTPUT); 2213 DELAY(10); 2214 CSR_WRITE_4(sc, DC_SIAGP, DC_SIAGP_INT1_EN | 2215 DC_SIAGP_MD_GP2_OUTPUT | DC_SIAGP_MD_GP0_OUTPUT); 2216 DELAY(10); 2217 } 2218 2219 error = mii_phy_probe(dev, &sc->dc_miibus, 2220 dc_ifmedia_upd, dc_ifmedia_sts); 2221 2222 if (error && DC_IS_INTEL(sc)) { 2223 sc->dc_pmode = tmp; 2224 if (sc->dc_pmode != DC_PMODE_SIA) 2225 sc->dc_pmode = DC_PMODE_SYM; 2226 sc->dc_flags |= DC_21143_NWAY; 2227 mii_phy_probe(dev, &sc->dc_miibus, 2228 dc_ifmedia_upd, dc_ifmedia_sts); 2229 /* 2230 * For non-MII cards, we need to have the 21143 2231 * drive the LEDs. Except there are some systems 2232 * like the NEC VersaPro NoteBook PC which have no 2233 * LEDs, and twiddling these bits has adverse effects 2234 * on them. (I.e. you suddenly can't get a link.) 2235 */ 2236 if (!(pci_get_subvendor(dev) == 0x1033 && 2237 pci_get_subdevice(dev) == 0x8028)) 2238 sc->dc_flags |= DC_TULIP_LEDS; 2239 error = 0; 2240 } 2241 2242 if (error) { 2243 device_printf(dev, "MII without any PHY!\n"); 2244 goto fail; 2245 } 2246 2247 if (DC_IS_ADMTEK(sc)) { 2248 /* 2249 * Set automatic TX underrun recovery for the ADMtek chips 2250 */ 2251 DC_SETBIT(sc, DC_AL_CR, DC_AL_CR_ATUR); 2252 } 2253 2254 /* 2255 * Tell the upper layer(s) we support long frames. 2256 */ 2257 ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header); 2258 ifp->if_capabilities |= IFCAP_VLAN_MTU; 2259 ifp->if_capenable = ifp->if_capabilities; 2260 #ifdef DEVICE_POLLING 2261 ifp->if_capabilities |= IFCAP_POLLING; 2262 #endif 2263 2264 callout_init_mtx(&sc->dc_stat_ch, &sc->dc_mtx, 0); 2265 callout_init_mtx(&sc->dc_wdog_ch, &sc->dc_mtx, 0); 2266 2267 /* 2268 * Call MI attach routine. 2269 */ 2270 ether_ifattach(ifp, (caddr_t)eaddr); 2271 2272 /* Hook interrupt last to avoid having to lock softc */ 2273 error = bus_setup_intr(dev, sc->dc_irq, INTR_TYPE_NET | INTR_MPSAFE, 2274 NULL, dc_intr, sc, &sc->dc_intrhand); 2275 2276 if (error) { 2277 device_printf(dev, "couldn't set up irq\n"); 2278 ether_ifdetach(ifp); 2279 goto fail; 2280 } 2281 2282 fail: 2283 if (error) 2284 dc_detach(dev); 2285 return (error); 2286 } 2287 2288 /* 2289 * Shutdown hardware and free up resources. This can be called any 2290 * time after the mutex has been initialized. It is called in both 2291 * the error case in attach and the normal detach case so it needs 2292 * to be careful about only freeing resources that have actually been 2293 * allocated. 2294 */ 2295 static int 2296 dc_detach(device_t dev) 2297 { 2298 struct dc_softc *sc; 2299 struct ifnet *ifp; 2300 struct dc_mediainfo *m; 2301 int i; 2302 2303 sc = device_get_softc(dev); 2304 KASSERT(mtx_initialized(&sc->dc_mtx), ("dc mutex not initialized")); 2305 2306 ifp = sc->dc_ifp; 2307 2308 #ifdef DEVICE_POLLING 2309 if (ifp->if_capenable & IFCAP_POLLING) 2310 ether_poll_deregister(ifp); 2311 #endif 2312 2313 /* These should only be active if attach succeeded */ 2314 if (device_is_attached(dev)) { 2315 DC_LOCK(sc); 2316 dc_stop(sc); 2317 DC_UNLOCK(sc); 2318 callout_drain(&sc->dc_stat_ch); 2319 callout_drain(&sc->dc_wdog_ch); 2320 ether_ifdetach(ifp); 2321 } 2322 if (sc->dc_miibus) 2323 device_delete_child(dev, sc->dc_miibus); 2324 bus_generic_detach(dev); 2325 2326 if (sc->dc_intrhand) 2327 bus_teardown_intr(dev, sc->dc_irq, sc->dc_intrhand); 2328 if (sc->dc_irq) 2329 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->dc_irq); 2330 if (sc->dc_res) 2331 bus_release_resource(dev, DC_RES, DC_RID, sc->dc_res); 2332 2333 if (ifp) 2334 if_free(ifp); 2335 2336 if (sc->dc_cdata.dc_sbuf != NULL) 2337 bus_dmamem_free(sc->dc_stag, sc->dc_cdata.dc_sbuf, sc->dc_smap); 2338 if (sc->dc_ldata != NULL) 2339 bus_dmamem_free(sc->dc_ltag, sc->dc_ldata, sc->dc_lmap); 2340 if (sc->dc_mtag) { 2341 for (i = 0; i < DC_TX_LIST_CNT; i++) 2342 if (sc->dc_cdata.dc_tx_map[i] != NULL) 2343 bus_dmamap_destroy(sc->dc_mtag, 2344 sc->dc_cdata.dc_tx_map[i]); 2345 for (i = 0; i < DC_RX_LIST_CNT; i++) 2346 if (sc->dc_cdata.dc_rx_map[i] != NULL) 2347 bus_dmamap_destroy(sc->dc_mtag, 2348 sc->dc_cdata.dc_rx_map[i]); 2349 bus_dmamap_destroy(sc->dc_mtag, sc->dc_sparemap); 2350 } 2351 if (sc->dc_stag) 2352 bus_dma_tag_destroy(sc->dc_stag); 2353 if (sc->dc_mtag) 2354 bus_dma_tag_destroy(sc->dc_mtag); 2355 if (sc->dc_ltag) 2356 bus_dma_tag_destroy(sc->dc_ltag); 2357 2358 free(sc->dc_pnic_rx_buf, M_DEVBUF); 2359 2360 while (sc->dc_mi != NULL) { 2361 m = sc->dc_mi->dc_next; 2362 free(sc->dc_mi, M_DEVBUF); 2363 sc->dc_mi = m; 2364 } 2365 free(sc->dc_srom, M_DEVBUF); 2366 2367 mtx_destroy(&sc->dc_mtx); 2368 2369 return (0); 2370 } 2371 2372 /* 2373 * Initialize the transmit descriptors. 2374 */ 2375 static int 2376 dc_list_tx_init(struct dc_softc *sc) 2377 { 2378 struct dc_chain_data *cd; 2379 struct dc_list_data *ld; 2380 int i, nexti; 2381 2382 cd = &sc->dc_cdata; 2383 ld = sc->dc_ldata; 2384 for (i = 0; i < DC_TX_LIST_CNT; i++) { 2385 if (i == DC_TX_LIST_CNT - 1) 2386 nexti = 0; 2387 else 2388 nexti = i + 1; 2389 ld->dc_tx_list[i].dc_next = htole32(DC_TXDESC(sc, nexti)); 2390 cd->dc_tx_chain[i] = NULL; 2391 ld->dc_tx_list[i].dc_data = 0; 2392 ld->dc_tx_list[i].dc_ctl = 0; 2393 } 2394 2395 cd->dc_tx_prod = cd->dc_tx_cons = cd->dc_tx_cnt = 0; 2396 bus_dmamap_sync(sc->dc_ltag, sc->dc_lmap, 2397 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2398 return (0); 2399 } 2400 2401 2402 /* 2403 * Initialize the RX descriptors and allocate mbufs for them. Note that 2404 * we arrange the descriptors in a closed ring, so that the last descriptor 2405 * points back to the first. 2406 */ 2407 static int 2408 dc_list_rx_init(struct dc_softc *sc) 2409 { 2410 struct dc_chain_data *cd; 2411 struct dc_list_data *ld; 2412 int i, nexti; 2413 2414 cd = &sc->dc_cdata; 2415 ld = sc->dc_ldata; 2416 2417 for (i = 0; i < DC_RX_LIST_CNT; i++) { 2418 if (dc_newbuf(sc, i, 1) != 0) 2419 return (ENOBUFS); 2420 if (i == DC_RX_LIST_CNT - 1) 2421 nexti = 0; 2422 else 2423 nexti = i + 1; 2424 ld->dc_rx_list[i].dc_next = htole32(DC_RXDESC(sc, nexti)); 2425 } 2426 2427 cd->dc_rx_prod = 0; 2428 bus_dmamap_sync(sc->dc_ltag, sc->dc_lmap, 2429 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2430 return (0); 2431 } 2432 2433 /* 2434 * Initialize an RX descriptor and attach an MBUF cluster. 2435 */ 2436 static int 2437 dc_newbuf(struct dc_softc *sc, int i, int alloc) 2438 { 2439 struct mbuf *m_new; 2440 bus_dmamap_t tmp; 2441 bus_dma_segment_t segs[1]; 2442 int error, nseg; 2443 2444 if (alloc) { 2445 m_new = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR); 2446 if (m_new == NULL) 2447 return (ENOBUFS); 2448 } else { 2449 m_new = sc->dc_cdata.dc_rx_chain[i]; 2450 m_new->m_data = m_new->m_ext.ext_buf; 2451 } 2452 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 2453 m_adj(m_new, sizeof(u_int64_t)); 2454 2455 /* 2456 * If this is a PNIC chip, zero the buffer. This is part 2457 * of the workaround for the receive bug in the 82c168 and 2458 * 82c169 chips. 2459 */ 2460 if (sc->dc_flags & DC_PNIC_RX_BUG_WAR) 2461 bzero(mtod(m_new, char *), m_new->m_len); 2462 2463 /* No need to remap the mbuf if we're reusing it. */ 2464 if (alloc) { 2465 error = bus_dmamap_load_mbuf_sg(sc->dc_mtag, sc->dc_sparemap, 2466 m_new, segs, &nseg, 0); 2467 if (error) { 2468 m_freem(m_new); 2469 return (error); 2470 } 2471 KASSERT(nseg == 1, 2472 ("%s: wrong number of segments (%d)", __func__, nseg)); 2473 sc->dc_ldata->dc_rx_list[i].dc_data = htole32(segs->ds_addr); 2474 bus_dmamap_unload(sc->dc_mtag, sc->dc_cdata.dc_rx_map[i]); 2475 tmp = sc->dc_cdata.dc_rx_map[i]; 2476 sc->dc_cdata.dc_rx_map[i] = sc->dc_sparemap; 2477 sc->dc_sparemap = tmp; 2478 sc->dc_cdata.dc_rx_chain[i] = m_new; 2479 } 2480 2481 sc->dc_ldata->dc_rx_list[i].dc_ctl = htole32(DC_RXCTL_RLINK | DC_RXLEN); 2482 sc->dc_ldata->dc_rx_list[i].dc_status = htole32(DC_RXSTAT_OWN); 2483 bus_dmamap_sync(sc->dc_mtag, sc->dc_cdata.dc_rx_map[i], 2484 BUS_DMASYNC_PREREAD); 2485 bus_dmamap_sync(sc->dc_ltag, sc->dc_lmap, 2486 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2487 return (0); 2488 } 2489 2490 /* 2491 * Grrrrr. 2492 * The PNIC chip has a terrible bug in it that manifests itself during 2493 * periods of heavy activity. The exact mode of failure if difficult to 2494 * pinpoint: sometimes it only happens in promiscuous mode, sometimes it 2495 * will happen on slow machines. The bug is that sometimes instead of 2496 * uploading one complete frame during reception, it uploads what looks 2497 * like the entire contents of its FIFO memory. The frame we want is at 2498 * the end of the whole mess, but we never know exactly how much data has 2499 * been uploaded, so salvaging the frame is hard. 2500 * 2501 * There is only one way to do it reliably, and it's disgusting. 2502 * Here's what we know: 2503 * 2504 * - We know there will always be somewhere between one and three extra 2505 * descriptors uploaded. 2506 * 2507 * - We know the desired received frame will always be at the end of the 2508 * total data upload. 2509 * 2510 * - We know the size of the desired received frame because it will be 2511 * provided in the length field of the status word in the last descriptor. 2512 * 2513 * Here's what we do: 2514 * 2515 * - When we allocate buffers for the receive ring, we bzero() them. 2516 * This means that we know that the buffer contents should be all 2517 * zeros, except for data uploaded by the chip. 2518 * 2519 * - We also force the PNIC chip to upload frames that include the 2520 * ethernet CRC at the end. 2521 * 2522 * - We gather all of the bogus frame data into a single buffer. 2523 * 2524 * - We then position a pointer at the end of this buffer and scan 2525 * backwards until we encounter the first non-zero byte of data. 2526 * This is the end of the received frame. We know we will encounter 2527 * some data at the end of the frame because the CRC will always be 2528 * there, so even if the sender transmits a packet of all zeros, 2529 * we won't be fooled. 2530 * 2531 * - We know the size of the actual received frame, so we subtract 2532 * that value from the current pointer location. This brings us 2533 * to the start of the actual received packet. 2534 * 2535 * - We copy this into an mbuf and pass it on, along with the actual 2536 * frame length. 2537 * 2538 * The performance hit is tremendous, but it beats dropping frames all 2539 * the time. 2540 */ 2541 2542 #define DC_WHOLEFRAME (DC_RXSTAT_FIRSTFRAG | DC_RXSTAT_LASTFRAG) 2543 static void 2544 dc_pnic_rx_bug_war(struct dc_softc *sc, int idx) 2545 { 2546 struct dc_desc *cur_rx; 2547 struct dc_desc *c = NULL; 2548 struct mbuf *m = NULL; 2549 unsigned char *ptr; 2550 int i, total_len; 2551 u_int32_t rxstat = 0; 2552 2553 i = sc->dc_pnic_rx_bug_save; 2554 cur_rx = &sc->dc_ldata->dc_rx_list[idx]; 2555 ptr = sc->dc_pnic_rx_buf; 2556 bzero(ptr, DC_RXLEN * 5); 2557 2558 /* Copy all the bytes from the bogus buffers. */ 2559 while (1) { 2560 c = &sc->dc_ldata->dc_rx_list[i]; 2561 rxstat = le32toh(c->dc_status); 2562 m = sc->dc_cdata.dc_rx_chain[i]; 2563 bcopy(mtod(m, char *), ptr, DC_RXLEN); 2564 ptr += DC_RXLEN; 2565 /* If this is the last buffer, break out. */ 2566 if (i == idx || rxstat & DC_RXSTAT_LASTFRAG) 2567 break; 2568 dc_newbuf(sc, i, 0); 2569 DC_INC(i, DC_RX_LIST_CNT); 2570 } 2571 2572 /* Find the length of the actual receive frame. */ 2573 total_len = DC_RXBYTES(rxstat); 2574 2575 /* Scan backwards until we hit a non-zero byte. */ 2576 while (*ptr == 0x00) 2577 ptr--; 2578 2579 /* Round off. */ 2580 if ((uintptr_t)(ptr) & 0x3) 2581 ptr -= 1; 2582 2583 /* Now find the start of the frame. */ 2584 ptr -= total_len; 2585 if (ptr < sc->dc_pnic_rx_buf) 2586 ptr = sc->dc_pnic_rx_buf; 2587 2588 /* 2589 * Now copy the salvaged frame to the last mbuf and fake up 2590 * the status word to make it look like a successful 2591 * frame reception. 2592 */ 2593 dc_newbuf(sc, i, 0); 2594 bcopy(ptr, mtod(m, char *), total_len); 2595 cur_rx->dc_status = htole32(rxstat | DC_RXSTAT_FIRSTFRAG); 2596 } 2597 2598 /* 2599 * This routine searches the RX ring for dirty descriptors in the 2600 * event that the rxeof routine falls out of sync with the chip's 2601 * current descriptor pointer. This may happen sometimes as a result 2602 * of a "no RX buffer available" condition that happens when the chip 2603 * consumes all of the RX buffers before the driver has a chance to 2604 * process the RX ring. This routine may need to be called more than 2605 * once to bring the driver back in sync with the chip, however we 2606 * should still be getting RX DONE interrupts to drive the search 2607 * for new packets in the RX ring, so we should catch up eventually. 2608 */ 2609 static int 2610 dc_rx_resync(struct dc_softc *sc) 2611 { 2612 struct dc_desc *cur_rx; 2613 int i, pos; 2614 2615 pos = sc->dc_cdata.dc_rx_prod; 2616 2617 for (i = 0; i < DC_RX_LIST_CNT; i++) { 2618 cur_rx = &sc->dc_ldata->dc_rx_list[pos]; 2619 if (!(le32toh(cur_rx->dc_status) & DC_RXSTAT_OWN)) 2620 break; 2621 DC_INC(pos, DC_RX_LIST_CNT); 2622 } 2623 2624 /* If the ring really is empty, then just return. */ 2625 if (i == DC_RX_LIST_CNT) 2626 return (0); 2627 2628 /* We've fallen behing the chip: catch it. */ 2629 sc->dc_cdata.dc_rx_prod = pos; 2630 2631 return (EAGAIN); 2632 } 2633 2634 /* 2635 * A frame has been uploaded: pass the resulting mbuf chain up to 2636 * the higher level protocols. 2637 */ 2638 static void 2639 dc_rxeof(struct dc_softc *sc) 2640 { 2641 struct mbuf *m, *m0; 2642 struct ifnet *ifp; 2643 struct dc_desc *cur_rx; 2644 int i, total_len = 0; 2645 u_int32_t rxstat; 2646 2647 DC_LOCK_ASSERT(sc); 2648 2649 ifp = sc->dc_ifp; 2650 i = sc->dc_cdata.dc_rx_prod; 2651 2652 bus_dmamap_sync(sc->dc_ltag, sc->dc_lmap, BUS_DMASYNC_POSTREAD); 2653 while (!(le32toh(sc->dc_ldata->dc_rx_list[i].dc_status) & 2654 DC_RXSTAT_OWN)) { 2655 #ifdef DEVICE_POLLING 2656 if (ifp->if_capenable & IFCAP_POLLING) { 2657 if (sc->rxcycles <= 0) 2658 break; 2659 sc->rxcycles--; 2660 } 2661 #endif 2662 cur_rx = &sc->dc_ldata->dc_rx_list[i]; 2663 rxstat = le32toh(cur_rx->dc_status); 2664 m = sc->dc_cdata.dc_rx_chain[i]; 2665 bus_dmamap_sync(sc->dc_mtag, sc->dc_cdata.dc_rx_map[i], 2666 BUS_DMASYNC_POSTREAD); 2667 total_len = DC_RXBYTES(rxstat); 2668 2669 if (sc->dc_flags & DC_PNIC_RX_BUG_WAR) { 2670 if ((rxstat & DC_WHOLEFRAME) != DC_WHOLEFRAME) { 2671 if (rxstat & DC_RXSTAT_FIRSTFRAG) 2672 sc->dc_pnic_rx_bug_save = i; 2673 if ((rxstat & DC_RXSTAT_LASTFRAG) == 0) { 2674 DC_INC(i, DC_RX_LIST_CNT); 2675 continue; 2676 } 2677 dc_pnic_rx_bug_war(sc, i); 2678 rxstat = le32toh(cur_rx->dc_status); 2679 total_len = DC_RXBYTES(rxstat); 2680 } 2681 } 2682 2683 /* 2684 * If an error occurs, update stats, clear the 2685 * status word and leave the mbuf cluster in place: 2686 * it should simply get re-used next time this descriptor 2687 * comes up in the ring. However, don't report long 2688 * frames as errors since they could be vlans. 2689 */ 2690 if ((rxstat & DC_RXSTAT_RXERR)) { 2691 if (!(rxstat & DC_RXSTAT_GIANT) || 2692 (rxstat & (DC_RXSTAT_CRCERR | DC_RXSTAT_DRIBBLE | 2693 DC_RXSTAT_MIIERE | DC_RXSTAT_COLLSEEN | 2694 DC_RXSTAT_RUNT | DC_RXSTAT_DE))) { 2695 ifp->if_ierrors++; 2696 if (rxstat & DC_RXSTAT_COLLSEEN) 2697 ifp->if_collisions++; 2698 dc_newbuf(sc, i, 0); 2699 if (rxstat & DC_RXSTAT_CRCERR) { 2700 DC_INC(i, DC_RX_LIST_CNT); 2701 continue; 2702 } else { 2703 dc_init_locked(sc); 2704 return; 2705 } 2706 } 2707 } 2708 2709 /* No errors; receive the packet. */ 2710 total_len -= ETHER_CRC_LEN; 2711 #ifdef __NO_STRICT_ALIGNMENT 2712 /* 2713 * On architectures without alignment problems we try to 2714 * allocate a new buffer for the receive ring, and pass up 2715 * the one where the packet is already, saving the expensive 2716 * copy done in m_devget(). 2717 * If we are on an architecture with alignment problems, or 2718 * if the allocation fails, then use m_devget and leave the 2719 * existing buffer in the receive ring. 2720 */ 2721 if (dc_newbuf(sc, i, 1) == 0) { 2722 m->m_pkthdr.rcvif = ifp; 2723 m->m_pkthdr.len = m->m_len = total_len; 2724 DC_INC(i, DC_RX_LIST_CNT); 2725 } else 2726 #endif 2727 { 2728 m0 = m_devget(mtod(m, char *), total_len, 2729 ETHER_ALIGN, ifp, NULL); 2730 dc_newbuf(sc, i, 0); 2731 DC_INC(i, DC_RX_LIST_CNT); 2732 if (m0 == NULL) { 2733 ifp->if_ierrors++; 2734 continue; 2735 } 2736 m = m0; 2737 } 2738 2739 ifp->if_ipackets++; 2740 DC_UNLOCK(sc); 2741 (*ifp->if_input)(ifp, m); 2742 DC_LOCK(sc); 2743 } 2744 2745 sc->dc_cdata.dc_rx_prod = i; 2746 } 2747 2748 /* 2749 * A frame was downloaded to the chip. It's safe for us to clean up 2750 * the list buffers. 2751 */ 2752 static void 2753 dc_txeof(struct dc_softc *sc) 2754 { 2755 struct dc_desc *cur_tx = NULL; 2756 struct ifnet *ifp; 2757 int idx; 2758 u_int32_t ctl, txstat; 2759 2760 ifp = sc->dc_ifp; 2761 2762 /* 2763 * Go through our tx list and free mbufs for those 2764 * frames that have been transmitted. 2765 */ 2766 bus_dmamap_sync(sc->dc_ltag, sc->dc_lmap, BUS_DMASYNC_POSTREAD); 2767 idx = sc->dc_cdata.dc_tx_cons; 2768 while (idx != sc->dc_cdata.dc_tx_prod) { 2769 2770 cur_tx = &sc->dc_ldata->dc_tx_list[idx]; 2771 txstat = le32toh(cur_tx->dc_status); 2772 ctl = le32toh(cur_tx->dc_ctl); 2773 2774 if (txstat & DC_TXSTAT_OWN) 2775 break; 2776 2777 if (!(ctl & DC_TXCTL_LASTFRAG) || ctl & DC_TXCTL_SETUP) { 2778 if (ctl & DC_TXCTL_SETUP) { 2779 /* 2780 * Yes, the PNIC is so brain damaged 2781 * that it will sometimes generate a TX 2782 * underrun error while DMAing the RX 2783 * filter setup frame. If we detect this, 2784 * we have to send the setup frame again, 2785 * or else the filter won't be programmed 2786 * correctly. 2787 */ 2788 if (DC_IS_PNIC(sc)) { 2789 if (txstat & DC_TXSTAT_ERRSUM) 2790 dc_setfilt(sc); 2791 } 2792 sc->dc_cdata.dc_tx_chain[idx] = NULL; 2793 } 2794 sc->dc_cdata.dc_tx_cnt--; 2795 DC_INC(idx, DC_TX_LIST_CNT); 2796 continue; 2797 } 2798 2799 if (DC_IS_XIRCOM(sc) || DC_IS_CONEXANT(sc)) { 2800 /* 2801 * XXX: Why does my Xircom taunt me so? 2802 * For some reason it likes setting the CARRLOST flag 2803 * even when the carrier is there. wtf?!? 2804 * Who knows, but Conexant chips have the 2805 * same problem. Maybe they took lessons 2806 * from Xircom. 2807 */ 2808 if (/*sc->dc_type == DC_TYPE_21143 &&*/ 2809 sc->dc_pmode == DC_PMODE_MII && 2810 ((txstat & 0xFFFF) & ~(DC_TXSTAT_ERRSUM | 2811 DC_TXSTAT_NOCARRIER))) 2812 txstat &= ~DC_TXSTAT_ERRSUM; 2813 } else { 2814 if (/*sc->dc_type == DC_TYPE_21143 &&*/ 2815 sc->dc_pmode == DC_PMODE_MII && 2816 ((txstat & 0xFFFF) & ~(DC_TXSTAT_ERRSUM | 2817 DC_TXSTAT_NOCARRIER | DC_TXSTAT_CARRLOST))) 2818 txstat &= ~DC_TXSTAT_ERRSUM; 2819 } 2820 2821 if (txstat & DC_TXSTAT_ERRSUM) { 2822 ifp->if_oerrors++; 2823 if (txstat & DC_TXSTAT_EXCESSCOLL) 2824 ifp->if_collisions++; 2825 if (txstat & DC_TXSTAT_LATECOLL) 2826 ifp->if_collisions++; 2827 if (!(txstat & DC_TXSTAT_UNDERRUN)) { 2828 dc_init_locked(sc); 2829 return; 2830 } 2831 } 2832 2833 ifp->if_collisions += (txstat & DC_TXSTAT_COLLCNT) >> 3; 2834 2835 ifp->if_opackets++; 2836 if (sc->dc_cdata.dc_tx_chain[idx] != NULL) { 2837 bus_dmamap_sync(sc->dc_mtag, 2838 sc->dc_cdata.dc_tx_map[idx], 2839 BUS_DMASYNC_POSTWRITE); 2840 bus_dmamap_unload(sc->dc_mtag, 2841 sc->dc_cdata.dc_tx_map[idx]); 2842 m_freem(sc->dc_cdata.dc_tx_chain[idx]); 2843 sc->dc_cdata.dc_tx_chain[idx] = NULL; 2844 } 2845 2846 sc->dc_cdata.dc_tx_cnt--; 2847 DC_INC(idx, DC_TX_LIST_CNT); 2848 } 2849 sc->dc_cdata.dc_tx_cons = idx; 2850 2851 if (DC_TX_LIST_CNT - sc->dc_cdata.dc_tx_cnt > DC_TX_LIST_RSVD) 2852 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 2853 2854 if (sc->dc_cdata.dc_tx_cnt == 0) 2855 sc->dc_wdog_timer = 0; 2856 } 2857 2858 static void 2859 dc_tick(void *xsc) 2860 { 2861 struct dc_softc *sc; 2862 struct mii_data *mii; 2863 struct ifnet *ifp; 2864 u_int32_t r; 2865 2866 sc = xsc; 2867 DC_LOCK_ASSERT(sc); 2868 ifp = sc->dc_ifp; 2869 mii = device_get_softc(sc->dc_miibus); 2870 2871 if (sc->dc_flags & DC_REDUCED_MII_POLL) { 2872 if (sc->dc_flags & DC_21143_NWAY) { 2873 r = CSR_READ_4(sc, DC_10BTSTAT); 2874 if (IFM_SUBTYPE(mii->mii_media_active) == 2875 IFM_100_TX && (r & DC_TSTAT_LS100)) { 2876 sc->dc_link = 0; 2877 mii_mediachg(mii); 2878 } 2879 if (IFM_SUBTYPE(mii->mii_media_active) == 2880 IFM_10_T && (r & DC_TSTAT_LS10)) { 2881 sc->dc_link = 0; 2882 mii_mediachg(mii); 2883 } 2884 if (sc->dc_link == 0) 2885 mii_tick(mii); 2886 } else { 2887 r = CSR_READ_4(sc, DC_ISR); 2888 if ((r & DC_ISR_RX_STATE) == DC_RXSTATE_WAIT && 2889 sc->dc_cdata.dc_tx_cnt == 0) { 2890 mii_tick(mii); 2891 if (!(mii->mii_media_status & IFM_ACTIVE)) 2892 sc->dc_link = 0; 2893 } 2894 } 2895 } else 2896 mii_tick(mii); 2897 2898 /* 2899 * When the init routine completes, we expect to be able to send 2900 * packets right away, and in fact the network code will send a 2901 * gratuitous ARP the moment the init routine marks the interface 2902 * as running. However, even though the MAC may have been initialized, 2903 * there may be a delay of a few seconds before the PHY completes 2904 * autonegotiation and the link is brought up. Any transmissions 2905 * made during that delay will be lost. Dealing with this is tricky: 2906 * we can't just pause in the init routine while waiting for the 2907 * PHY to come ready since that would bring the whole system to 2908 * a screeching halt for several seconds. 2909 * 2910 * What we do here is prevent the TX start routine from sending 2911 * any packets until a link has been established. After the 2912 * interface has been initialized, the tick routine will poll 2913 * the state of the PHY until the IFM_ACTIVE flag is set. Until 2914 * that time, packets will stay in the send queue, and once the 2915 * link comes up, they will be flushed out to the wire. 2916 */ 2917 if (!sc->dc_link && mii->mii_media_status & IFM_ACTIVE && 2918 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) { 2919 sc->dc_link++; 2920 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 2921 dc_start_locked(ifp); 2922 } 2923 2924 if (sc->dc_flags & DC_21143_NWAY && !sc->dc_link) 2925 callout_reset(&sc->dc_stat_ch, hz/10, dc_tick, sc); 2926 else 2927 callout_reset(&sc->dc_stat_ch, hz, dc_tick, sc); 2928 } 2929 2930 /* 2931 * A transmit underrun has occurred. Back off the transmit threshold, 2932 * or switch to store and forward mode if we have to. 2933 */ 2934 static void 2935 dc_tx_underrun(struct dc_softc *sc) 2936 { 2937 u_int32_t isr; 2938 int i; 2939 2940 if (DC_IS_DAVICOM(sc)) 2941 dc_init_locked(sc); 2942 2943 if (DC_IS_INTEL(sc)) { 2944 /* 2945 * The real 21143 requires that the transmitter be idle 2946 * in order to change the transmit threshold or store 2947 * and forward state. 2948 */ 2949 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_TX_ON); 2950 2951 for (i = 0; i < DC_TIMEOUT; i++) { 2952 isr = CSR_READ_4(sc, DC_ISR); 2953 if (isr & DC_ISR_TX_IDLE) 2954 break; 2955 DELAY(10); 2956 } 2957 if (i == DC_TIMEOUT) { 2958 device_printf(sc->dc_dev, 2959 "%s: failed to force tx to idle state\n", 2960 __func__); 2961 dc_init_locked(sc); 2962 } 2963 } 2964 2965 device_printf(sc->dc_dev, "TX underrun -- "); 2966 sc->dc_txthresh += DC_TXTHRESH_INC; 2967 if (sc->dc_txthresh > DC_TXTHRESH_MAX) { 2968 printf("using store and forward mode\n"); 2969 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_STORENFWD); 2970 } else { 2971 printf("increasing TX threshold\n"); 2972 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_TX_THRESH); 2973 DC_SETBIT(sc, DC_NETCFG, sc->dc_txthresh); 2974 } 2975 2976 if (DC_IS_INTEL(sc)) 2977 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_TX_ON); 2978 } 2979 2980 #ifdef DEVICE_POLLING 2981 static poll_handler_t dc_poll; 2982 2983 static void 2984 dc_poll(struct ifnet *ifp, enum poll_cmd cmd, int count) 2985 { 2986 struct dc_softc *sc = ifp->if_softc; 2987 2988 DC_LOCK(sc); 2989 2990 if (!(ifp->if_drv_flags & IFF_DRV_RUNNING)) { 2991 DC_UNLOCK(sc); 2992 return; 2993 } 2994 2995 sc->rxcycles = count; 2996 dc_rxeof(sc); 2997 dc_txeof(sc); 2998 if (!IFQ_IS_EMPTY(&ifp->if_snd) && 2999 !(ifp->if_drv_flags & IFF_DRV_OACTIVE)) 3000 dc_start_locked(ifp); 3001 3002 if (cmd == POLL_AND_CHECK_STATUS) { /* also check status register */ 3003 u_int32_t status; 3004 3005 status = CSR_READ_4(sc, DC_ISR); 3006 status &= (DC_ISR_RX_WATDOGTIMEO | DC_ISR_RX_NOBUF | 3007 DC_ISR_TX_NOBUF | DC_ISR_TX_IDLE | DC_ISR_TX_UNDERRUN | 3008 DC_ISR_BUS_ERR); 3009 if (!status) { 3010 DC_UNLOCK(sc); 3011 return; 3012 } 3013 /* ack what we have */ 3014 CSR_WRITE_4(sc, DC_ISR, status); 3015 3016 if (status & (DC_ISR_RX_WATDOGTIMEO | DC_ISR_RX_NOBUF)) { 3017 u_int32_t r = CSR_READ_4(sc, DC_FRAMESDISCARDED); 3018 ifp->if_ierrors += (r & 0xffff) + ((r >> 17) & 0x7ff); 3019 3020 if (dc_rx_resync(sc)) 3021 dc_rxeof(sc); 3022 } 3023 /* restart transmit unit if necessary */ 3024 if (status & DC_ISR_TX_IDLE && sc->dc_cdata.dc_tx_cnt) 3025 CSR_WRITE_4(sc, DC_TXSTART, 0xFFFFFFFF); 3026 3027 if (status & DC_ISR_TX_UNDERRUN) 3028 dc_tx_underrun(sc); 3029 3030 if (status & DC_ISR_BUS_ERR) { 3031 if_printf(ifp, "%s: bus error\n", __func__); 3032 dc_reset(sc); 3033 dc_init_locked(sc); 3034 } 3035 } 3036 DC_UNLOCK(sc); 3037 } 3038 #endif /* DEVICE_POLLING */ 3039 3040 static void 3041 dc_intr(void *arg) 3042 { 3043 struct dc_softc *sc; 3044 struct ifnet *ifp; 3045 u_int32_t status; 3046 3047 sc = arg; 3048 3049 if (sc->suspended) 3050 return; 3051 3052 if ((CSR_READ_4(sc, DC_ISR) & DC_INTRS) == 0) 3053 return; 3054 3055 DC_LOCK(sc); 3056 ifp = sc->dc_ifp; 3057 #ifdef DEVICE_POLLING 3058 if (ifp->if_capenable & IFCAP_POLLING) { 3059 DC_UNLOCK(sc); 3060 return; 3061 } 3062 #endif 3063 3064 /* Suppress unwanted interrupts */ 3065 if (!(ifp->if_flags & IFF_UP)) { 3066 if (CSR_READ_4(sc, DC_ISR) & DC_INTRS) 3067 dc_stop(sc); 3068 DC_UNLOCK(sc); 3069 return; 3070 } 3071 3072 /* Disable interrupts. */ 3073 CSR_WRITE_4(sc, DC_IMR, 0x00000000); 3074 3075 while (((status = CSR_READ_4(sc, DC_ISR)) & DC_INTRS) && 3076 status != 0xFFFFFFFF && 3077 (ifp->if_drv_flags & IFF_DRV_RUNNING)) { 3078 3079 CSR_WRITE_4(sc, DC_ISR, status); 3080 3081 if (status & DC_ISR_RX_OK) { 3082 int curpkts; 3083 curpkts = ifp->if_ipackets; 3084 dc_rxeof(sc); 3085 if (curpkts == ifp->if_ipackets) { 3086 while (dc_rx_resync(sc)) 3087 dc_rxeof(sc); 3088 } 3089 } 3090 3091 if (status & (DC_ISR_TX_OK | DC_ISR_TX_NOBUF)) 3092 dc_txeof(sc); 3093 3094 if (status & DC_ISR_TX_IDLE) { 3095 dc_txeof(sc); 3096 if (sc->dc_cdata.dc_tx_cnt) { 3097 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_TX_ON); 3098 CSR_WRITE_4(sc, DC_TXSTART, 0xFFFFFFFF); 3099 } 3100 } 3101 3102 if (status & DC_ISR_TX_UNDERRUN) 3103 dc_tx_underrun(sc); 3104 3105 if ((status & DC_ISR_RX_WATDOGTIMEO) 3106 || (status & DC_ISR_RX_NOBUF)) { 3107 int curpkts; 3108 curpkts = ifp->if_ipackets; 3109 dc_rxeof(sc); 3110 if (curpkts == ifp->if_ipackets) { 3111 while (dc_rx_resync(sc)) 3112 dc_rxeof(sc); 3113 } 3114 } 3115 3116 if (status & DC_ISR_BUS_ERR) { 3117 dc_reset(sc); 3118 dc_init_locked(sc); 3119 } 3120 } 3121 3122 /* Re-enable interrupts. */ 3123 CSR_WRITE_4(sc, DC_IMR, DC_INTRS); 3124 3125 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 3126 dc_start_locked(ifp); 3127 3128 DC_UNLOCK(sc); 3129 } 3130 3131 /* 3132 * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data 3133 * pointers to the fragment pointers. 3134 */ 3135 static int 3136 dc_encap(struct dc_softc *sc, struct mbuf **m_head) 3137 { 3138 bus_dma_segment_t segs[DC_MAXFRAGS]; 3139 struct dc_desc *f; 3140 struct mbuf *m; 3141 int chainlen, cur, error, first, frag, i, idx, nseg; 3142 3143 /* 3144 * If there's no way we can send any packets, return now. 3145 */ 3146 if (DC_TX_LIST_CNT - sc->dc_cdata.dc_tx_cnt <= DC_TX_LIST_RSVD) 3147 return (ENOBUFS); 3148 3149 /* 3150 * Count the number of frags in this chain to see if 3151 * we need to m_defrag. Since the descriptor list is shared 3152 * by all packets, we'll m_defrag long chains so that they 3153 * do not use up the entire list, even if they would fit. 3154 */ 3155 chainlen = 0; 3156 for (m = *m_head; m != NULL; m = m->m_next) 3157 chainlen++; 3158 3159 m = NULL; 3160 if ((sc->dc_flags & DC_TX_COALESCE && ((*m_head)->m_next != NULL || 3161 sc->dc_flags & DC_TX_ALIGN)) || (chainlen > DC_TX_LIST_CNT / 4) || 3162 (DC_TX_LIST_CNT - (chainlen + sc->dc_cdata.dc_tx_cnt) <= 3163 DC_TX_LIST_RSVD)) { 3164 m = m_defrag(*m_head, M_DONTWAIT); 3165 if (m == NULL) { 3166 m_freem(*m_head); 3167 *m_head = NULL; 3168 return (ENOBUFS); 3169 } 3170 *m_head = m; 3171 } 3172 idx = sc->dc_cdata.dc_tx_prod; 3173 error = bus_dmamap_load_mbuf_sg(sc->dc_mtag, 3174 sc->dc_cdata.dc_tx_map[idx], *m_head, segs, &nseg, 0); 3175 if (error == EFBIG) { 3176 m = m_defrag(*m_head, M_DONTWAIT); 3177 if (m == NULL) { 3178 m_freem(*m_head); 3179 *m_head = NULL; 3180 return (ENOBUFS); 3181 } 3182 *m_head = m; 3183 error = bus_dmamap_load_mbuf_sg(sc->dc_mtag, 3184 sc->dc_cdata.dc_tx_map[idx], *m_head, segs, &nseg, 0); 3185 if (error != 0) { 3186 m_freem(*m_head); 3187 *m_head = NULL; 3188 return (error); 3189 } 3190 } else if (error != 0) 3191 return (error); 3192 KASSERT(nseg <= DC_MAXFRAGS, 3193 ("%s: wrong number of segments (%d)", __func__, nseg)); 3194 if (nseg == 0) { 3195 m_freem(*m_head); 3196 *m_head = NULL; 3197 return (EIO); 3198 } 3199 3200 first = cur = frag = sc->dc_cdata.dc_tx_prod; 3201 for (i = 0; i < nseg; i++) { 3202 if ((sc->dc_flags & DC_TX_ADMTEK_WAR) && 3203 (frag == (DC_TX_LIST_CNT - 1)) && 3204 (first != sc->dc_cdata.dc_tx_first)) { 3205 bus_dmamap_unload(sc->dc_mtag, 3206 sc->dc_cdata.dc_tx_map[first]); 3207 m_freem(*m_head); 3208 *m_head = NULL; 3209 return (ENOBUFS); 3210 } 3211 3212 f = &sc->dc_ldata->dc_tx_list[frag]; 3213 f->dc_ctl = htole32(DC_TXCTL_TLINK | segs[i].ds_len); 3214 if (i == 0) { 3215 f->dc_status = 0; 3216 f->dc_ctl |= htole32(DC_TXCTL_FIRSTFRAG); 3217 } else 3218 f->dc_status = htole32(DC_TXSTAT_OWN); 3219 f->dc_data = htole32(segs[i].ds_addr); 3220 cur = frag; 3221 DC_INC(frag, DC_TX_LIST_CNT); 3222 } 3223 3224 sc->dc_cdata.dc_tx_prod = frag; 3225 sc->dc_cdata.dc_tx_cnt += nseg; 3226 sc->dc_cdata.dc_tx_chain[cur] = *m_head; 3227 sc->dc_ldata->dc_tx_list[cur].dc_ctl |= htole32(DC_TXCTL_LASTFRAG); 3228 if (sc->dc_flags & DC_TX_INTR_FIRSTFRAG) 3229 sc->dc_ldata->dc_tx_list[first].dc_ctl |= 3230 htole32(DC_TXCTL_FINT); 3231 if (sc->dc_flags & DC_TX_INTR_ALWAYS) 3232 sc->dc_ldata->dc_tx_list[cur].dc_ctl |= htole32(DC_TXCTL_FINT); 3233 if (sc->dc_flags & DC_TX_USE_TX_INTR && sc->dc_cdata.dc_tx_cnt > 64) 3234 sc->dc_ldata->dc_tx_list[cur].dc_ctl |= htole32(DC_TXCTL_FINT); 3235 sc->dc_ldata->dc_tx_list[first].dc_status = htole32(DC_TXSTAT_OWN); 3236 3237 bus_dmamap_sync(sc->dc_mtag, sc->dc_cdata.dc_tx_map[idx], 3238 BUS_DMASYNC_PREWRITE); 3239 bus_dmamap_sync(sc->dc_ltag, sc->dc_lmap, 3240 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3241 return (0); 3242 } 3243 3244 static void 3245 dc_start(struct ifnet *ifp) 3246 { 3247 struct dc_softc *sc; 3248 3249 sc = ifp->if_softc; 3250 DC_LOCK(sc); 3251 dc_start_locked(ifp); 3252 DC_UNLOCK(sc); 3253 } 3254 3255 /* 3256 * Main transmit routine 3257 * To avoid having to do mbuf copies, we put pointers to the mbuf data 3258 * regions directly in the transmit lists. We also save a copy of the 3259 * pointers since the transmit list fragment pointers are physical 3260 * addresses. 3261 */ 3262 static void 3263 dc_start_locked(struct ifnet *ifp) 3264 { 3265 struct dc_softc *sc; 3266 struct mbuf *m_head = NULL; 3267 unsigned int queued = 0; 3268 int idx; 3269 3270 sc = ifp->if_softc; 3271 3272 DC_LOCK_ASSERT(sc); 3273 3274 if (!sc->dc_link && ifp->if_snd.ifq_len < 10) 3275 return; 3276 3277 if (ifp->if_drv_flags & IFF_DRV_OACTIVE) 3278 return; 3279 3280 idx = sc->dc_cdata.dc_tx_first = sc->dc_cdata.dc_tx_prod; 3281 3282 while (sc->dc_cdata.dc_tx_chain[idx] == NULL) { 3283 IFQ_DRV_DEQUEUE(&ifp->if_snd, m_head); 3284 if (m_head == NULL) 3285 break; 3286 3287 if (dc_encap(sc, &m_head)) { 3288 if (m_head == NULL) 3289 break; 3290 IFQ_DRV_PREPEND(&ifp->if_snd, m_head); 3291 ifp->if_drv_flags |= IFF_DRV_OACTIVE; 3292 break; 3293 } 3294 idx = sc->dc_cdata.dc_tx_prod; 3295 3296 queued++; 3297 /* 3298 * If there's a BPF listener, bounce a copy of this frame 3299 * to him. 3300 */ 3301 BPF_MTAP(ifp, m_head); 3302 3303 if (sc->dc_flags & DC_TX_ONE) { 3304 ifp->if_drv_flags |= IFF_DRV_OACTIVE; 3305 break; 3306 } 3307 } 3308 3309 if (queued > 0) { 3310 /* Transmit */ 3311 if (!(sc->dc_flags & DC_TX_POLL)) 3312 CSR_WRITE_4(sc, DC_TXSTART, 0xFFFFFFFF); 3313 3314 /* 3315 * Set a timeout in case the chip goes out to lunch. 3316 */ 3317 sc->dc_wdog_timer = 5; 3318 } 3319 } 3320 3321 static void 3322 dc_init(void *xsc) 3323 { 3324 struct dc_softc *sc = xsc; 3325 3326 DC_LOCK(sc); 3327 dc_init_locked(sc); 3328 DC_UNLOCK(sc); 3329 } 3330 3331 static void 3332 dc_init_locked(struct dc_softc *sc) 3333 { 3334 struct ifnet *ifp = sc->dc_ifp; 3335 struct mii_data *mii; 3336 3337 DC_LOCK_ASSERT(sc); 3338 3339 mii = device_get_softc(sc->dc_miibus); 3340 3341 /* 3342 * Cancel pending I/O and free all RX/TX buffers. 3343 */ 3344 dc_stop(sc); 3345 dc_reset(sc); 3346 3347 /* 3348 * Set cache alignment and burst length. 3349 */ 3350 if (DC_IS_ASIX(sc) || DC_IS_DAVICOM(sc)) 3351 CSR_WRITE_4(sc, DC_BUSCTL, 0); 3352 else 3353 CSR_WRITE_4(sc, DC_BUSCTL, DC_BUSCTL_MRME | DC_BUSCTL_MRLE); 3354 /* 3355 * Evenly share the bus between receive and transmit process. 3356 */ 3357 if (DC_IS_INTEL(sc)) 3358 DC_SETBIT(sc, DC_BUSCTL, DC_BUSCTL_ARBITRATION); 3359 if (DC_IS_DAVICOM(sc) || DC_IS_INTEL(sc)) { 3360 DC_SETBIT(sc, DC_BUSCTL, DC_BURSTLEN_USECA); 3361 } else { 3362 DC_SETBIT(sc, DC_BUSCTL, DC_BURSTLEN_16LONG); 3363 } 3364 if (sc->dc_flags & DC_TX_POLL) 3365 DC_SETBIT(sc, DC_BUSCTL, DC_TXPOLL_1); 3366 switch(sc->dc_cachesize) { 3367 case 32: 3368 DC_SETBIT(sc, DC_BUSCTL, DC_CACHEALIGN_32LONG); 3369 break; 3370 case 16: 3371 DC_SETBIT(sc, DC_BUSCTL, DC_CACHEALIGN_16LONG); 3372 break; 3373 case 8: 3374 DC_SETBIT(sc, DC_BUSCTL, DC_CACHEALIGN_8LONG); 3375 break; 3376 case 0: 3377 default: 3378 DC_SETBIT(sc, DC_BUSCTL, DC_CACHEALIGN_NONE); 3379 break; 3380 } 3381 3382 if (sc->dc_flags & DC_TX_STORENFWD) 3383 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_STORENFWD); 3384 else { 3385 if (sc->dc_txthresh > DC_TXTHRESH_MAX) { 3386 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_STORENFWD); 3387 } else { 3388 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_STORENFWD); 3389 DC_SETBIT(sc, DC_NETCFG, sc->dc_txthresh); 3390 } 3391 } 3392 3393 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_NO_RXCRC); 3394 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_TX_BACKOFF); 3395 3396 if (DC_IS_MACRONIX(sc) || DC_IS_PNICII(sc)) { 3397 /* 3398 * The app notes for the 98713 and 98715A say that 3399 * in order to have the chips operate properly, a magic 3400 * number must be written to CSR16. Macronix does not 3401 * document the meaning of these bits so there's no way 3402 * to know exactly what they do. The 98713 has a magic 3403 * number all its own; the rest all use a different one. 3404 */ 3405 DC_CLRBIT(sc, DC_MX_MAGICPACKET, 0xFFFF0000); 3406 if (sc->dc_type == DC_TYPE_98713) 3407 DC_SETBIT(sc, DC_MX_MAGICPACKET, DC_MX_MAGIC_98713); 3408 else 3409 DC_SETBIT(sc, DC_MX_MAGICPACKET, DC_MX_MAGIC_98715); 3410 } 3411 3412 if (DC_IS_XIRCOM(sc)) { 3413 /* 3414 * setup General Purpose Port mode and data so the tulip 3415 * can talk to the MII. 3416 */ 3417 CSR_WRITE_4(sc, DC_SIAGP, DC_SIAGP_WRITE_EN | DC_SIAGP_INT1_EN | 3418 DC_SIAGP_MD_GP2_OUTPUT | DC_SIAGP_MD_GP0_OUTPUT); 3419 DELAY(10); 3420 CSR_WRITE_4(sc, DC_SIAGP, DC_SIAGP_INT1_EN | 3421 DC_SIAGP_MD_GP2_OUTPUT | DC_SIAGP_MD_GP0_OUTPUT); 3422 DELAY(10); 3423 } 3424 3425 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_TX_THRESH); 3426 DC_SETBIT(sc, DC_NETCFG, DC_TXTHRESH_MIN); 3427 3428 /* Init circular RX list. */ 3429 if (dc_list_rx_init(sc) == ENOBUFS) { 3430 device_printf(sc->dc_dev, 3431 "initialization failed: no memory for rx buffers\n"); 3432 dc_stop(sc); 3433 return; 3434 } 3435 3436 /* 3437 * Init TX descriptors. 3438 */ 3439 dc_list_tx_init(sc); 3440 3441 /* 3442 * Load the address of the RX list. 3443 */ 3444 CSR_WRITE_4(sc, DC_RXADDR, DC_RXDESC(sc, 0)); 3445 CSR_WRITE_4(sc, DC_TXADDR, DC_TXDESC(sc, 0)); 3446 3447 /* 3448 * Enable interrupts. 3449 */ 3450 #ifdef DEVICE_POLLING 3451 /* 3452 * ... but only if we are not polling, and make sure they are off in 3453 * the case of polling. Some cards (e.g. fxp) turn interrupts on 3454 * after a reset. 3455 */ 3456 if (ifp->if_capenable & IFCAP_POLLING) 3457 CSR_WRITE_4(sc, DC_IMR, 0x00000000); 3458 else 3459 #endif 3460 CSR_WRITE_4(sc, DC_IMR, DC_INTRS); 3461 CSR_WRITE_4(sc, DC_ISR, 0xFFFFFFFF); 3462 3463 /* Enable transmitter. */ 3464 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_TX_ON); 3465 3466 /* 3467 * If this is an Intel 21143 and we're not using the 3468 * MII port, program the LED control pins so we get 3469 * link and activity indications. 3470 */ 3471 if (sc->dc_flags & DC_TULIP_LEDS) { 3472 CSR_WRITE_4(sc, DC_WATCHDOG, 3473 DC_WDOG_CTLWREN | DC_WDOG_LINK | DC_WDOG_ACTIVITY); 3474 CSR_WRITE_4(sc, DC_WATCHDOG, 0); 3475 } 3476 3477 /* 3478 * Load the RX/multicast filter. We do this sort of late 3479 * because the filter programming scheme on the 21143 and 3480 * some clones requires DMAing a setup frame via the TX 3481 * engine, and we need the transmitter enabled for that. 3482 */ 3483 dc_setfilt(sc); 3484 3485 /* Enable receiver. */ 3486 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_ON); 3487 CSR_WRITE_4(sc, DC_RXSTART, 0xFFFFFFFF); 3488 3489 mii_mediachg(mii); 3490 dc_setcfg(sc, sc->dc_if_media); 3491 3492 ifp->if_drv_flags |= IFF_DRV_RUNNING; 3493 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 3494 3495 /* Don't start the ticker if this is a homePNA link. */ 3496 if (IFM_SUBTYPE(mii->mii_media.ifm_media) == IFM_HPNA_1) 3497 sc->dc_link = 1; 3498 else { 3499 if (sc->dc_flags & DC_21143_NWAY) 3500 callout_reset(&sc->dc_stat_ch, hz/10, dc_tick, sc); 3501 else 3502 callout_reset(&sc->dc_stat_ch, hz, dc_tick, sc); 3503 } 3504 3505 sc->dc_wdog_timer = 0; 3506 callout_reset(&sc->dc_wdog_ch, hz, dc_watchdog, sc); 3507 } 3508 3509 /* 3510 * Set media options. 3511 */ 3512 static int 3513 dc_ifmedia_upd(struct ifnet *ifp) 3514 { 3515 struct dc_softc *sc; 3516 struct mii_data *mii; 3517 struct ifmedia *ifm; 3518 3519 sc = ifp->if_softc; 3520 mii = device_get_softc(sc->dc_miibus); 3521 DC_LOCK(sc); 3522 mii_mediachg(mii); 3523 ifm = &mii->mii_media; 3524 3525 if (DC_IS_DAVICOM(sc) && 3526 IFM_SUBTYPE(ifm->ifm_media) == IFM_HPNA_1) 3527 dc_setcfg(sc, ifm->ifm_media); 3528 else 3529 sc->dc_link = 0; 3530 DC_UNLOCK(sc); 3531 3532 return (0); 3533 } 3534 3535 /* 3536 * Report current media status. 3537 */ 3538 static void 3539 dc_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 3540 { 3541 struct dc_softc *sc; 3542 struct mii_data *mii; 3543 struct ifmedia *ifm; 3544 3545 sc = ifp->if_softc; 3546 mii = device_get_softc(sc->dc_miibus); 3547 DC_LOCK(sc); 3548 mii_pollstat(mii); 3549 ifm = &mii->mii_media; 3550 if (DC_IS_DAVICOM(sc)) { 3551 if (IFM_SUBTYPE(ifm->ifm_media) == IFM_HPNA_1) { 3552 ifmr->ifm_active = ifm->ifm_media; 3553 ifmr->ifm_status = 0; 3554 DC_UNLOCK(sc); 3555 return; 3556 } 3557 } 3558 ifmr->ifm_active = mii->mii_media_active; 3559 ifmr->ifm_status = mii->mii_media_status; 3560 DC_UNLOCK(sc); 3561 } 3562 3563 static int 3564 dc_ioctl(struct ifnet *ifp, u_long command, caddr_t data) 3565 { 3566 struct dc_softc *sc = ifp->if_softc; 3567 struct ifreq *ifr = (struct ifreq *)data; 3568 struct mii_data *mii; 3569 int error = 0; 3570 3571 switch (command) { 3572 case SIOCSIFFLAGS: 3573 DC_LOCK(sc); 3574 if (ifp->if_flags & IFF_UP) { 3575 int need_setfilt = (ifp->if_flags ^ sc->dc_if_flags) & 3576 (IFF_PROMISC | IFF_ALLMULTI); 3577 3578 if (ifp->if_drv_flags & IFF_DRV_RUNNING) { 3579 if (need_setfilt) 3580 dc_setfilt(sc); 3581 } else { 3582 sc->dc_txthresh = 0; 3583 dc_init_locked(sc); 3584 } 3585 } else { 3586 if (ifp->if_drv_flags & IFF_DRV_RUNNING) 3587 dc_stop(sc); 3588 } 3589 sc->dc_if_flags = ifp->if_flags; 3590 DC_UNLOCK(sc); 3591 error = 0; 3592 break; 3593 case SIOCADDMULTI: 3594 case SIOCDELMULTI: 3595 DC_LOCK(sc); 3596 dc_setfilt(sc); 3597 DC_UNLOCK(sc); 3598 error = 0; 3599 break; 3600 case SIOCGIFMEDIA: 3601 case SIOCSIFMEDIA: 3602 mii = device_get_softc(sc->dc_miibus); 3603 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 3604 break; 3605 case SIOCSIFCAP: 3606 #ifdef DEVICE_POLLING 3607 if (ifr->ifr_reqcap & IFCAP_POLLING && 3608 !(ifp->if_capenable & IFCAP_POLLING)) { 3609 error = ether_poll_register(dc_poll, ifp); 3610 if (error) 3611 return(error); 3612 DC_LOCK(sc); 3613 /* Disable interrupts */ 3614 CSR_WRITE_4(sc, DC_IMR, 0x00000000); 3615 ifp->if_capenable |= IFCAP_POLLING; 3616 DC_UNLOCK(sc); 3617 return (error); 3618 } 3619 if (!(ifr->ifr_reqcap & IFCAP_POLLING) && 3620 ifp->if_capenable & IFCAP_POLLING) { 3621 error = ether_poll_deregister(ifp); 3622 /* Enable interrupts. */ 3623 DC_LOCK(sc); 3624 CSR_WRITE_4(sc, DC_IMR, DC_INTRS); 3625 ifp->if_capenable &= ~IFCAP_POLLING; 3626 DC_UNLOCK(sc); 3627 return (error); 3628 } 3629 #endif /* DEVICE_POLLING */ 3630 break; 3631 default: 3632 error = ether_ioctl(ifp, command, data); 3633 break; 3634 } 3635 3636 return (error); 3637 } 3638 3639 static void 3640 dc_watchdog(void *xsc) 3641 { 3642 struct dc_softc *sc = xsc; 3643 struct ifnet *ifp; 3644 3645 DC_LOCK_ASSERT(sc); 3646 3647 if (sc->dc_wdog_timer == 0 || --sc->dc_wdog_timer != 0) { 3648 callout_reset(&sc->dc_wdog_ch, hz, dc_watchdog, sc); 3649 return; 3650 } 3651 3652 ifp = sc->dc_ifp; 3653 ifp->if_oerrors++; 3654 device_printf(sc->dc_dev, "watchdog timeout\n"); 3655 3656 dc_stop(sc); 3657 dc_reset(sc); 3658 dc_init_locked(sc); 3659 3660 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 3661 dc_start_locked(ifp); 3662 } 3663 3664 /* 3665 * Stop the adapter and free any mbufs allocated to the 3666 * RX and TX lists. 3667 */ 3668 static void 3669 dc_stop(struct dc_softc *sc) 3670 { 3671 struct ifnet *ifp; 3672 struct dc_list_data *ld; 3673 struct dc_chain_data *cd; 3674 int i; 3675 u_int32_t ctl; 3676 3677 DC_LOCK_ASSERT(sc); 3678 3679 ifp = sc->dc_ifp; 3680 ld = sc->dc_ldata; 3681 cd = &sc->dc_cdata; 3682 3683 callout_stop(&sc->dc_stat_ch); 3684 callout_stop(&sc->dc_wdog_ch); 3685 sc->dc_wdog_timer = 0; 3686 3687 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE); 3688 3689 DC_CLRBIT(sc, DC_NETCFG, (DC_NETCFG_RX_ON | DC_NETCFG_TX_ON)); 3690 CSR_WRITE_4(sc, DC_IMR, 0x00000000); 3691 CSR_WRITE_4(sc, DC_TXADDR, 0x00000000); 3692 CSR_WRITE_4(sc, DC_RXADDR, 0x00000000); 3693 sc->dc_link = 0; 3694 3695 /* 3696 * Free data in the RX lists. 3697 */ 3698 for (i = 0; i < DC_RX_LIST_CNT; i++) { 3699 if (cd->dc_rx_chain[i] != NULL) { 3700 m_freem(cd->dc_rx_chain[i]); 3701 cd->dc_rx_chain[i] = NULL; 3702 } 3703 } 3704 bzero(&ld->dc_rx_list, sizeof(ld->dc_rx_list)); 3705 3706 /* 3707 * Free the TX list buffers. 3708 */ 3709 for (i = 0; i < DC_TX_LIST_CNT; i++) { 3710 if (cd->dc_tx_chain[i] != NULL) { 3711 ctl = le32toh(ld->dc_tx_list[i].dc_ctl); 3712 if ((ctl & DC_TXCTL_SETUP) || 3713 !(ctl & DC_TXCTL_LASTFRAG)) { 3714 cd->dc_tx_chain[i] = NULL; 3715 continue; 3716 } 3717 bus_dmamap_unload(sc->dc_mtag, cd->dc_tx_map[i]); 3718 m_freem(cd->dc_tx_chain[i]); 3719 cd->dc_tx_chain[i] = NULL; 3720 } 3721 } 3722 bzero(&ld->dc_tx_list, sizeof(ld->dc_tx_list)); 3723 } 3724 3725 /* 3726 * Device suspend routine. Stop the interface and save some PCI 3727 * settings in case the BIOS doesn't restore them properly on 3728 * resume. 3729 */ 3730 static int 3731 dc_suspend(device_t dev) 3732 { 3733 struct dc_softc *sc; 3734 3735 sc = device_get_softc(dev); 3736 DC_LOCK(sc); 3737 dc_stop(sc); 3738 sc->suspended = 1; 3739 DC_UNLOCK(sc); 3740 3741 return (0); 3742 } 3743 3744 /* 3745 * Device resume routine. Restore some PCI settings in case the BIOS 3746 * doesn't, re-enable busmastering, and restart the interface if 3747 * appropriate. 3748 */ 3749 static int 3750 dc_resume(device_t dev) 3751 { 3752 struct dc_softc *sc; 3753 struct ifnet *ifp; 3754 3755 sc = device_get_softc(dev); 3756 ifp = sc->dc_ifp; 3757 3758 /* reinitialize interface if necessary */ 3759 DC_LOCK(sc); 3760 if (ifp->if_flags & IFF_UP) 3761 dc_init_locked(sc); 3762 3763 sc->suspended = 0; 3764 DC_UNLOCK(sc); 3765 3766 return (0); 3767 } 3768 3769 /* 3770 * Stop all chip I/O so that the kernel's probe routines don't 3771 * get confused by errant DMAs when rebooting. 3772 */ 3773 static int 3774 dc_shutdown(device_t dev) 3775 { 3776 struct dc_softc *sc; 3777 3778 sc = device_get_softc(dev); 3779 3780 DC_LOCK(sc); 3781 dc_stop(sc); 3782 DC_UNLOCK(sc); 3783 3784 return (0); 3785 } 3786