1 /* 2 * Copyright (c) 1997, 1998, 1999 3 * Bill Paul <wpaul@ee.columbia.edu>. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 3. All advertising materials mentioning features or use of this software 14 * must display the following acknowledgement: 15 * This product includes software developed by Bill Paul. 16 * 4. Neither the name of the author nor the names of any co-contributors 17 * may be used to endorse or promote products derived from this software 18 * without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30 * THE POSSIBILITY OF SUCH DAMAGE. 31 * 32 * $FreeBSD$ 33 */ 34 35 /* 36 * DEC "tulip" clone ethernet driver. Supports the DEC/Intel 21143 37 * series chips and several workalikes including the following: 38 * 39 * Macronix 98713/98715/98725/98727/98732 PMAC (www.macronix.com) 40 * Macronix/Lite-On 82c115 PNIC II (www.macronix.com) 41 * Lite-On 82c168/82c169 PNIC (www.litecom.com) 42 * ASIX Electronics AX88140A (www.asix.com.tw) 43 * ASIX Electronics AX88141 (www.asix.com.tw) 44 * ADMtek AL981 (www.admtek.com.tw) 45 * ADMtek AN985 (www.admtek.com.tw) 46 * Davicom DM9100, DM9102, DM9102A (www.davicom8.com) 47 * Accton EN1217 (www.accton.com) 48 * Xircom X3201 (www.xircom.com) 49 * Abocom FE2500 50 * Conexant LANfinity (www.conexant.com) 51 * 52 * Datasheets for the 21143 are available at developer.intel.com. 53 * Datasheets for the clone parts can be found at their respective sites. 54 * (Except for the PNIC; see www.freebsd.org/~wpaul/PNIC/pnic.ps.gz.) 55 * The PNIC II is essentially a Macronix 98715A chip; the only difference 56 * worth noting is that its multicast hash table is only 128 bits wide 57 * instead of 512. 58 * 59 * Written by Bill Paul <wpaul@ee.columbia.edu> 60 * Electrical Engineering Department 61 * Columbia University, New York City 62 */ 63 64 /* 65 * The Intel 21143 is the successor to the DEC 21140. It is basically 66 * the same as the 21140 but with a few new features. The 21143 supports 67 * three kinds of media attachments: 68 * 69 * o MII port, for 10Mbps and 100Mbps support and NWAY 70 * autonegotiation provided by an external PHY. 71 * o SYM port, for symbol mode 100Mbps support. 72 * o 10baseT port. 73 * o AUI/BNC port. 74 * 75 * The 100Mbps SYM port and 10baseT port can be used together in 76 * combination with the internal NWAY support to create a 10/100 77 * autosensing configuration. 78 * 79 * Note that not all tulip workalikes are handled in this driver: we only 80 * deal with those which are relatively well behaved. The Winbond is 81 * handled separately due to its different register offsets and the 82 * special handling needed for its various bugs. The PNIC is handled 83 * here, but I'm not thrilled about it. 84 * 85 * All of the workalike chips use some form of MII transceiver support 86 * with the exception of the Macronix chips, which also have a SYM port. 87 * The ASIX AX88140A is also documented to have a SYM port, but all 88 * the cards I've seen use an MII transceiver, probably because the 89 * AX88140A doesn't support internal NWAY. 90 */ 91 92 #include <sys/param.h> 93 #include <sys/systm.h> 94 #include <sys/sockio.h> 95 #include <sys/mbuf.h> 96 #include <sys/malloc.h> 97 #include <sys/kernel.h> 98 #include <sys/socket.h> 99 100 #include <net/if.h> 101 #include <net/if_arp.h> 102 #include <net/ethernet.h> 103 #include <net/if_dl.h> 104 #include <net/if_media.h> 105 106 #include <net/bpf.h> 107 108 #include <vm/vm.h> /* for vtophys */ 109 #include <vm/pmap.h> /* for vtophys */ 110 #include <machine/bus_pio.h> 111 #include <machine/bus_memio.h> 112 #include <machine/bus.h> 113 #include <machine/resource.h> 114 #include <sys/bus.h> 115 #include <sys/rman.h> 116 117 #include <dev/mii/mii.h> 118 #include <dev/mii/miivar.h> 119 120 #include <pci/pcireg.h> 121 #include <pci/pcivar.h> 122 123 #define DC_USEIOSPACE 124 #ifdef __alpha__ 125 #define SRM_MEDIA 126 #endif 127 128 #include <pci/if_dcreg.h> 129 130 MODULE_DEPEND(dc, miibus, 1, 1, 1); 131 132 /* "controller miibus0" required. See GENERIC if you get errors here. */ 133 #include "miibus_if.h" 134 135 #ifndef lint 136 static const char rcsid[] = 137 "$FreeBSD$"; 138 #endif 139 140 /* 141 * Various supported device vendors/types and their names. 142 */ 143 static struct dc_type dc_devs[] = { 144 { DC_VENDORID_DEC, DC_DEVICEID_21143, 145 "Intel 21143 10/100BaseTX" }, 146 { DC_VENDORID_DAVICOM, DC_DEVICEID_DM9100, 147 "Davicom DM9100 10/100BaseTX" }, 148 { DC_VENDORID_DAVICOM, DC_DEVICEID_DM9102, 149 "Davicom DM9102 10/100BaseTX" }, 150 { DC_VENDORID_DAVICOM, DC_DEVICEID_DM9102, 151 "Davicom DM9102A 10/100BaseTX" }, 152 { DC_VENDORID_ADMTEK, DC_DEVICEID_AL981, 153 "ADMtek AL981 10/100BaseTX" }, 154 { DC_VENDORID_ADMTEK, DC_DEVICEID_AN985, 155 "ADMtek AN985 10/100BaseTX" }, 156 { DC_VENDORID_ASIX, DC_DEVICEID_AX88140A, 157 "ASIX AX88140A 10/100BaseTX" }, 158 { DC_VENDORID_ASIX, DC_DEVICEID_AX88140A, 159 "ASIX AX88141 10/100BaseTX" }, 160 { DC_VENDORID_MX, DC_DEVICEID_98713, 161 "Macronix 98713 10/100BaseTX" }, 162 { DC_VENDORID_MX, DC_DEVICEID_98713, 163 "Macronix 98713A 10/100BaseTX" }, 164 { DC_VENDORID_CP, DC_DEVICEID_98713_CP, 165 "Compex RL100-TX 10/100BaseTX" }, 166 { DC_VENDORID_CP, DC_DEVICEID_98713_CP, 167 "Compex RL100-TX 10/100BaseTX" }, 168 { DC_VENDORID_MX, DC_DEVICEID_987x5, 169 "Macronix 98715/98715A 10/100BaseTX" }, 170 { DC_VENDORID_MX, DC_DEVICEID_987x5, 171 "Macronix 98715AEC-C 10/100BaseTX" }, 172 { DC_VENDORID_MX, DC_DEVICEID_987x5, 173 "Macronix 98725 10/100BaseTX" }, 174 { DC_VENDORID_MX, DC_DEVICEID_98727, 175 "Macronix 98727/98732 10/100BaseTX" }, 176 { DC_VENDORID_LO, DC_DEVICEID_82C115, 177 "LC82C115 PNIC II 10/100BaseTX" }, 178 { DC_VENDORID_LO, DC_DEVICEID_82C168, 179 "82c168 PNIC 10/100BaseTX" }, 180 { DC_VENDORID_LO, DC_DEVICEID_82C168, 181 "82c169 PNIC 10/100BaseTX" }, 182 { DC_VENDORID_ACCTON, DC_DEVICEID_EN1217, 183 "Accton EN1217 10/100BaseTX" }, 184 { DC_VENDORID_ACCTON, DC_DEVICEID_EN2242, 185 "Accton EN2242 MiniPCI 10/100BaseTX" }, 186 { DC_VENDORID_XIRCOM, DC_DEVICEID_X3201, 187 "Xircom X3201 10/100BaseTX" }, 188 { DC_VENDORID_ABOCOM, DC_DEVICEID_FE2500, 189 "Abocom FE2500 10/100BaseTX" }, 190 { DC_VENDORID_CONEXANT, DC_DEVICEID_RS7112, 191 "Conexant LANfinity MiniPCI 10/100BaseTX" }, 192 { 0, 0, NULL } 193 }; 194 195 static int dc_probe __P((device_t)); 196 static int dc_attach __P((device_t)); 197 static int dc_detach __P((device_t)); 198 static void dc_acpi __P((device_t)); 199 static struct dc_type *dc_devtype __P((device_t)); 200 static int dc_newbuf __P((struct dc_softc *, int, struct mbuf *)); 201 static int dc_encap __P((struct dc_softc *, struct mbuf *, 202 u_int32_t *)); 203 static int dc_coal __P((struct dc_softc *, struct mbuf **)); 204 static void dc_pnic_rx_bug_war __P((struct dc_softc *, int)); 205 static int dc_rx_resync __P((struct dc_softc *)); 206 static void dc_rxeof __P((struct dc_softc *)); 207 static void dc_txeof __P((struct dc_softc *)); 208 static void dc_tick __P((void *)); 209 static void dc_tx_underrun __P((struct dc_softc *)); 210 static void dc_intr __P((void *)); 211 static void dc_start __P((struct ifnet *)); 212 static int dc_ioctl __P((struct ifnet *, u_long, caddr_t)); 213 static void dc_init __P((void *)); 214 static void dc_stop __P((struct dc_softc *)); 215 static void dc_watchdog __P((struct ifnet *)); 216 static void dc_shutdown __P((device_t)); 217 static int dc_ifmedia_upd __P((struct ifnet *)); 218 static void dc_ifmedia_sts __P((struct ifnet *, struct ifmediareq *)); 219 220 static void dc_delay __P((struct dc_softc *)); 221 static void dc_eeprom_idle __P((struct dc_softc *)); 222 static void dc_eeprom_putbyte __P((struct dc_softc *, int)); 223 static void dc_eeprom_getword __P((struct dc_softc *, int, u_int16_t *)); 224 static void dc_eeprom_getword_pnic 225 __P((struct dc_softc *, int, u_int16_t *)); 226 static void dc_eeprom_getword_xircom 227 __P((struct dc_softc *, int, u_int16_t *)); 228 static void dc_read_eeprom __P((struct dc_softc *, caddr_t, int, 229 int, int)); 230 231 static void dc_mii_writebit __P((struct dc_softc *, int)); 232 static int dc_mii_readbit __P((struct dc_softc *)); 233 static void dc_mii_sync __P((struct dc_softc *)); 234 static void dc_mii_send __P((struct dc_softc *, u_int32_t, int)); 235 static int dc_mii_readreg __P((struct dc_softc *, struct dc_mii_frame *)); 236 static int dc_mii_writereg __P((struct dc_softc *, struct dc_mii_frame *)); 237 static int dc_miibus_readreg __P((device_t, int, int)); 238 static int dc_miibus_writereg __P((device_t, int, int, int)); 239 static void dc_miibus_statchg __P((device_t)); 240 static void dc_miibus_mediainit __P((device_t)); 241 242 static void dc_setcfg __P((struct dc_softc *, int)); 243 static u_int32_t dc_crc_le __P((struct dc_softc *, caddr_t)); 244 static u_int32_t dc_crc_be __P((caddr_t)); 245 static void dc_setfilt_21143 __P((struct dc_softc *)); 246 static void dc_setfilt_asix __P((struct dc_softc *)); 247 static void dc_setfilt_admtek __P((struct dc_softc *)); 248 static void dc_setfilt_xircom __P((struct dc_softc *)); 249 250 static void dc_setfilt __P((struct dc_softc *)); 251 252 static void dc_reset __P((struct dc_softc *)); 253 static int dc_list_rx_init __P((struct dc_softc *)); 254 static int dc_list_tx_init __P((struct dc_softc *)); 255 256 static void dc_parse_21143_srom __P((struct dc_softc *)); 257 static void dc_decode_leaf_sia __P((struct dc_softc *, 258 struct dc_eblock_sia *)); 259 static void dc_decode_leaf_mii __P((struct dc_softc *, 260 struct dc_eblock_mii *)); 261 static void dc_decode_leaf_sym __P((struct dc_softc *, 262 struct dc_eblock_sym *)); 263 static void dc_apply_fixup __P((struct dc_softc *, int)); 264 265 #ifdef DC_USEIOSPACE 266 #define DC_RES SYS_RES_IOPORT 267 #define DC_RID DC_PCI_CFBIO 268 #else 269 #define DC_RES SYS_RES_MEMORY 270 #define DC_RID DC_PCI_CFBMA 271 #endif 272 273 static device_method_t dc_methods[] = { 274 /* Device interface */ 275 DEVMETHOD(device_probe, dc_probe), 276 DEVMETHOD(device_attach, dc_attach), 277 DEVMETHOD(device_detach, dc_detach), 278 DEVMETHOD(device_shutdown, dc_shutdown), 279 280 /* bus interface */ 281 DEVMETHOD(bus_print_child, bus_generic_print_child), 282 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 283 284 /* MII interface */ 285 DEVMETHOD(miibus_readreg, dc_miibus_readreg), 286 DEVMETHOD(miibus_writereg, dc_miibus_writereg), 287 DEVMETHOD(miibus_statchg, dc_miibus_statchg), 288 DEVMETHOD(miibus_mediainit, dc_miibus_mediainit), 289 290 { 0, 0 } 291 }; 292 293 static driver_t dc_driver = { 294 "dc", 295 dc_methods, 296 sizeof(struct dc_softc) 297 }; 298 299 static devclass_t dc_devclass; 300 301 DRIVER_MODULE(if_dc, cardbus, dc_driver, dc_devclass, 0, 0); 302 DRIVER_MODULE(if_dc, pci, dc_driver, dc_devclass, 0, 0); 303 DRIVER_MODULE(miibus, dc, miibus_driver, miibus_devclass, 0, 0); 304 305 #define DC_SETBIT(sc, reg, x) \ 306 CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) | (x)) 307 308 #define DC_CLRBIT(sc, reg, x) \ 309 CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) & ~(x)) 310 311 #define SIO_SET(x) DC_SETBIT(sc, DC_SIO, (x)) 312 #define SIO_CLR(x) DC_CLRBIT(sc, DC_SIO, (x)) 313 314 #define IS_MPSAFE 0 315 316 static void dc_delay(sc) 317 struct dc_softc *sc; 318 { 319 int idx; 320 321 for (idx = (300 / 33) + 1; idx > 0; idx--) 322 CSR_READ_4(sc, DC_BUSCTL); 323 } 324 325 static void dc_eeprom_idle(sc) 326 struct dc_softc *sc; 327 { 328 register int i; 329 330 CSR_WRITE_4(sc, DC_SIO, DC_SIO_EESEL); 331 dc_delay(sc); 332 DC_SETBIT(sc, DC_SIO, DC_SIO_ROMCTL_READ); 333 dc_delay(sc); 334 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); 335 dc_delay(sc); 336 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CS); 337 dc_delay(sc); 338 339 for (i = 0; i < 25; i++) { 340 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); 341 dc_delay(sc); 342 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CLK); 343 dc_delay(sc); 344 } 345 346 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); 347 dc_delay(sc); 348 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CS); 349 dc_delay(sc); 350 CSR_WRITE_4(sc, DC_SIO, 0x00000000); 351 352 return; 353 } 354 355 /* 356 * Send a read command and address to the EEPROM, check for ACK. 357 */ 358 static void dc_eeprom_putbyte(sc, addr) 359 struct dc_softc *sc; 360 int addr; 361 { 362 register int d, i; 363 364 /* 365 * The AN985 has a 93C66 EEPROM on it instead of 366 * a 93C46. It uses a different bit sequence for 367 * specifying the "read" opcode. 368 */ 369 if (DC_IS_CENTAUR(sc) || DC_IS_CONEXANT(sc)) 370 d = addr | (DC_EECMD_READ << 2); 371 else 372 d = addr | DC_EECMD_READ; 373 374 /* 375 * Feed in each bit and strobe the clock. 376 */ 377 for (i = 0x400; i; i >>= 1) { 378 if (d & i) { 379 SIO_SET(DC_SIO_EE_DATAIN); 380 } else { 381 SIO_CLR(DC_SIO_EE_DATAIN); 382 } 383 dc_delay(sc); 384 SIO_SET(DC_SIO_EE_CLK); 385 dc_delay(sc); 386 SIO_CLR(DC_SIO_EE_CLK); 387 dc_delay(sc); 388 } 389 390 return; 391 } 392 393 /* 394 * Read a word of data stored in the EEPROM at address 'addr.' 395 * The PNIC 82c168/82c169 has its own non-standard way to read 396 * the EEPROM. 397 */ 398 static void dc_eeprom_getword_pnic(sc, addr, dest) 399 struct dc_softc *sc; 400 int addr; 401 u_int16_t *dest; 402 { 403 register int i; 404 u_int32_t r; 405 406 CSR_WRITE_4(sc, DC_PN_SIOCTL, DC_PN_EEOPCODE_READ|addr); 407 408 for (i = 0; i < DC_TIMEOUT; i++) { 409 DELAY(1); 410 r = CSR_READ_4(sc, DC_SIO); 411 if (!(r & DC_PN_SIOCTL_BUSY)) { 412 *dest = (u_int16_t)(r & 0xFFFF); 413 return; 414 } 415 } 416 417 return; 418 } 419 420 /* 421 * Read a word of data stored in the EEPROM at address 'addr.' 422 * The Xircom X3201 has its own non-standard way to read 423 * the EEPROM, too. 424 */ 425 static void dc_eeprom_getword_xircom(sc, addr, dest) 426 struct dc_softc *sc; 427 int addr; 428 u_int16_t *dest; 429 { 430 SIO_SET(DC_SIO_ROMSEL | DC_SIO_ROMCTL_READ); 431 432 addr *= 2; 433 CSR_WRITE_4(sc, DC_ROM, addr | 0x160); 434 *dest = (u_int16_t)CSR_READ_4(sc, DC_SIO)&0xff; 435 addr += 1; 436 CSR_WRITE_4(sc, DC_ROM, addr | 0x160); 437 *dest |= ((u_int16_t)CSR_READ_4(sc, DC_SIO)&0xff) << 8; 438 439 SIO_CLR(DC_SIO_ROMSEL | DC_SIO_ROMCTL_READ); 440 return; 441 } 442 443 /* 444 * Read a word of data stored in the EEPROM at address 'addr.' 445 */ 446 static void dc_eeprom_getword(sc, addr, dest) 447 struct dc_softc *sc; 448 int addr; 449 u_int16_t *dest; 450 { 451 register int i; 452 u_int16_t word = 0; 453 454 /* Force EEPROM to idle state. */ 455 dc_eeprom_idle(sc); 456 457 /* Enter EEPROM access mode. */ 458 CSR_WRITE_4(sc, DC_SIO, DC_SIO_EESEL); 459 dc_delay(sc); 460 DC_SETBIT(sc, DC_SIO, DC_SIO_ROMCTL_READ); 461 dc_delay(sc); 462 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); 463 dc_delay(sc); 464 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CS); 465 dc_delay(sc); 466 467 /* 468 * Send address of word we want to read. 469 */ 470 dc_eeprom_putbyte(sc, addr); 471 472 /* 473 * Start reading bits from EEPROM. 474 */ 475 for (i = 0x8000; i; i >>= 1) { 476 SIO_SET(DC_SIO_EE_CLK); 477 dc_delay(sc); 478 if (CSR_READ_4(sc, DC_SIO) & DC_SIO_EE_DATAOUT) 479 word |= i; 480 dc_delay(sc); 481 SIO_CLR(DC_SIO_EE_CLK); 482 dc_delay(sc); 483 } 484 485 /* Turn off EEPROM access mode. */ 486 dc_eeprom_idle(sc); 487 488 *dest = word; 489 490 return; 491 } 492 493 /* 494 * Read a sequence of words from the EEPROM. 495 */ 496 static void dc_read_eeprom(sc, dest, off, cnt, swap) 497 struct dc_softc *sc; 498 caddr_t dest; 499 int off; 500 int cnt; 501 int swap; 502 { 503 int i; 504 u_int16_t word = 0, *ptr; 505 506 for (i = 0; i < cnt; i++) { 507 if (DC_IS_PNIC(sc)) 508 dc_eeprom_getword_pnic(sc, off + i, &word); 509 else if (DC_IS_XIRCOM(sc)) 510 dc_eeprom_getword_xircom(sc, off + i, &word); 511 else 512 dc_eeprom_getword(sc, off + i, &word); 513 ptr = (u_int16_t *)(dest + (i * 2)); 514 if (swap) 515 *ptr = ntohs(word); 516 else 517 *ptr = word; 518 } 519 520 return; 521 } 522 523 /* 524 * The following two routines are taken from the Macronix 98713 525 * Application Notes pp.19-21. 526 */ 527 /* 528 * Write a bit to the MII bus. 529 */ 530 static void dc_mii_writebit(sc, bit) 531 struct dc_softc *sc; 532 int bit; 533 { 534 if (bit) 535 CSR_WRITE_4(sc, DC_SIO, 536 DC_SIO_ROMCTL_WRITE|DC_SIO_MII_DATAOUT); 537 else 538 CSR_WRITE_4(sc, DC_SIO, DC_SIO_ROMCTL_WRITE); 539 540 DC_SETBIT(sc, DC_SIO, DC_SIO_MII_CLK); 541 DC_CLRBIT(sc, DC_SIO, DC_SIO_MII_CLK); 542 543 return; 544 } 545 546 /* 547 * Read a bit from the MII bus. 548 */ 549 static int dc_mii_readbit(sc) 550 struct dc_softc *sc; 551 { 552 CSR_WRITE_4(sc, DC_SIO, DC_SIO_ROMCTL_READ|DC_SIO_MII_DIR); 553 CSR_READ_4(sc, DC_SIO); 554 DC_SETBIT(sc, DC_SIO, DC_SIO_MII_CLK); 555 DC_CLRBIT(sc, DC_SIO, DC_SIO_MII_CLK); 556 if (CSR_READ_4(sc, DC_SIO) & DC_SIO_MII_DATAIN) 557 return(1); 558 559 return(0); 560 } 561 562 /* 563 * Sync the PHYs by setting data bit and strobing the clock 32 times. 564 */ 565 static void dc_mii_sync(sc) 566 struct dc_softc *sc; 567 { 568 register int i; 569 570 CSR_WRITE_4(sc, DC_SIO, DC_SIO_ROMCTL_WRITE); 571 572 for (i = 0; i < 32; i++) 573 dc_mii_writebit(sc, 1); 574 575 return; 576 } 577 578 /* 579 * Clock a series of bits through the MII. 580 */ 581 static void dc_mii_send(sc, bits, cnt) 582 struct dc_softc *sc; 583 u_int32_t bits; 584 int cnt; 585 { 586 int i; 587 588 for (i = (0x1 << (cnt - 1)); i; i >>= 1) 589 dc_mii_writebit(sc, bits & i); 590 } 591 592 /* 593 * Read an PHY register through the MII. 594 */ 595 static int dc_mii_readreg(sc, frame) 596 struct dc_softc *sc; 597 struct dc_mii_frame *frame; 598 599 { 600 int i, ack; 601 602 DC_LOCK(sc); 603 604 /* 605 * Set up frame for RX. 606 */ 607 frame->mii_stdelim = DC_MII_STARTDELIM; 608 frame->mii_opcode = DC_MII_READOP; 609 frame->mii_turnaround = 0; 610 frame->mii_data = 0; 611 612 /* 613 * Sync the PHYs. 614 */ 615 dc_mii_sync(sc); 616 617 /* 618 * Send command/address info. 619 */ 620 dc_mii_send(sc, frame->mii_stdelim, 2); 621 dc_mii_send(sc, frame->mii_opcode, 2); 622 dc_mii_send(sc, frame->mii_phyaddr, 5); 623 dc_mii_send(sc, frame->mii_regaddr, 5); 624 625 #ifdef notdef 626 /* Idle bit */ 627 dc_mii_writebit(sc, 1); 628 dc_mii_writebit(sc, 0); 629 #endif 630 631 /* Check for ack */ 632 ack = dc_mii_readbit(sc); 633 634 /* 635 * Now try reading data bits. If the ack failed, we still 636 * need to clock through 16 cycles to keep the PHY(s) in sync. 637 */ 638 if (ack) { 639 for(i = 0; i < 16; i++) { 640 dc_mii_readbit(sc); 641 } 642 goto fail; 643 } 644 645 for (i = 0x8000; i; i >>= 1) { 646 if (!ack) { 647 if (dc_mii_readbit(sc)) 648 frame->mii_data |= i; 649 } 650 } 651 652 fail: 653 654 dc_mii_writebit(sc, 0); 655 dc_mii_writebit(sc, 0); 656 657 DC_UNLOCK(sc); 658 659 if (ack) 660 return(1); 661 return(0); 662 } 663 664 /* 665 * Write to a PHY register through the MII. 666 */ 667 static int dc_mii_writereg(sc, frame) 668 struct dc_softc *sc; 669 struct dc_mii_frame *frame; 670 671 { 672 DC_LOCK(sc); 673 /* 674 * Set up frame for TX. 675 */ 676 677 frame->mii_stdelim = DC_MII_STARTDELIM; 678 frame->mii_opcode = DC_MII_WRITEOP; 679 frame->mii_turnaround = DC_MII_TURNAROUND; 680 681 /* 682 * Sync the PHYs. 683 */ 684 dc_mii_sync(sc); 685 686 dc_mii_send(sc, frame->mii_stdelim, 2); 687 dc_mii_send(sc, frame->mii_opcode, 2); 688 dc_mii_send(sc, frame->mii_phyaddr, 5); 689 dc_mii_send(sc, frame->mii_regaddr, 5); 690 dc_mii_send(sc, frame->mii_turnaround, 2); 691 dc_mii_send(sc, frame->mii_data, 16); 692 693 /* Idle bit. */ 694 dc_mii_writebit(sc, 0); 695 dc_mii_writebit(sc, 0); 696 697 DC_UNLOCK(sc); 698 699 return(0); 700 } 701 702 static int dc_miibus_readreg(dev, phy, reg) 703 device_t dev; 704 int phy, reg; 705 { 706 struct dc_mii_frame frame; 707 struct dc_softc *sc; 708 int i, rval, phy_reg = 0; 709 710 sc = device_get_softc(dev); 711 bzero((char *)&frame, sizeof(frame)); 712 713 /* 714 * Note: both the AL981 and AN985 have internal PHYs, 715 * however the AL981 provides direct access to the PHY 716 * registers while the AN985 uses a serial MII interface. 717 * The AN985's MII interface is also buggy in that you 718 * can read from any MII address (0 to 31), but only address 1 719 * behaves normally. To deal with both cases, we pretend 720 * that the PHY is at MII address 1. 721 */ 722 if (DC_IS_ADMTEK(sc) && phy != DC_ADMTEK_PHYADDR) 723 return(0); 724 725 /* 726 * Note: the ukphy probes of the RS7112 report a PHY at 727 * MII address 0 (possibly HomePNA?) and 1 (ethernet) 728 * so we only respond to correct one. 729 */ 730 if (DC_IS_CONEXANT(sc) && phy != DC_CONEXANT_PHYADDR) 731 return(0); 732 733 if (sc->dc_pmode != DC_PMODE_MII) { 734 if (phy == (MII_NPHY - 1)) { 735 switch(reg) { 736 case MII_BMSR: 737 /* 738 * Fake something to make the probe 739 * code think there's a PHY here. 740 */ 741 return(BMSR_MEDIAMASK); 742 break; 743 case MII_PHYIDR1: 744 if (DC_IS_PNIC(sc)) 745 return(DC_VENDORID_LO); 746 return(DC_VENDORID_DEC); 747 break; 748 case MII_PHYIDR2: 749 if (DC_IS_PNIC(sc)) 750 return(DC_DEVICEID_82C168); 751 return(DC_DEVICEID_21143); 752 break; 753 default: 754 return(0); 755 break; 756 } 757 } else 758 return(0); 759 } 760 761 if (DC_IS_PNIC(sc)) { 762 CSR_WRITE_4(sc, DC_PN_MII, DC_PN_MIIOPCODE_READ | 763 (phy << 23) | (reg << 18)); 764 for (i = 0; i < DC_TIMEOUT; i++) { 765 DELAY(1); 766 rval = CSR_READ_4(sc, DC_PN_MII); 767 if (!(rval & DC_PN_MII_BUSY)) { 768 rval &= 0xFFFF; 769 return(rval == 0xFFFF ? 0 : rval); 770 } 771 } 772 return(0); 773 } 774 775 if (DC_IS_COMET(sc)) { 776 switch(reg) { 777 case MII_BMCR: 778 phy_reg = DC_AL_BMCR; 779 break; 780 case MII_BMSR: 781 phy_reg = DC_AL_BMSR; 782 break; 783 case MII_PHYIDR1: 784 phy_reg = DC_AL_VENID; 785 break; 786 case MII_PHYIDR2: 787 phy_reg = DC_AL_DEVID; 788 break; 789 case MII_ANAR: 790 phy_reg = DC_AL_ANAR; 791 break; 792 case MII_ANLPAR: 793 phy_reg = DC_AL_LPAR; 794 break; 795 case MII_ANER: 796 phy_reg = DC_AL_ANER; 797 break; 798 default: 799 printf("dc%d: phy_read: bad phy register %x\n", 800 sc->dc_unit, reg); 801 return(0); 802 break; 803 } 804 805 rval = CSR_READ_4(sc, phy_reg) & 0x0000FFFF; 806 807 if (rval == 0xFFFF) 808 return(0); 809 return(rval); 810 } 811 812 frame.mii_phyaddr = phy; 813 frame.mii_regaddr = reg; 814 if (sc->dc_type == DC_TYPE_98713) { 815 phy_reg = CSR_READ_4(sc, DC_NETCFG); 816 CSR_WRITE_4(sc, DC_NETCFG, phy_reg & ~DC_NETCFG_PORTSEL); 817 } 818 dc_mii_readreg(sc, &frame); 819 if (sc->dc_type == DC_TYPE_98713) 820 CSR_WRITE_4(sc, DC_NETCFG, phy_reg); 821 822 return(frame.mii_data); 823 } 824 825 static int dc_miibus_writereg(dev, phy, reg, data) 826 device_t dev; 827 int phy, reg, data; 828 { 829 struct dc_softc *sc; 830 struct dc_mii_frame frame; 831 int i, phy_reg = 0; 832 833 sc = device_get_softc(dev); 834 bzero((char *)&frame, sizeof(frame)); 835 836 if (DC_IS_ADMTEK(sc) && phy != DC_ADMTEK_PHYADDR) 837 return(0); 838 839 if (DC_IS_CONEXANT(sc) && phy != DC_CONEXANT_PHYADDR) 840 return(0); 841 842 if (DC_IS_PNIC(sc)) { 843 CSR_WRITE_4(sc, DC_PN_MII, DC_PN_MIIOPCODE_WRITE | 844 (phy << 23) | (reg << 10) | data); 845 for (i = 0; i < DC_TIMEOUT; i++) { 846 if (!(CSR_READ_4(sc, DC_PN_MII) & DC_PN_MII_BUSY)) 847 break; 848 } 849 return(0); 850 } 851 852 if (DC_IS_COMET(sc)) { 853 switch(reg) { 854 case MII_BMCR: 855 phy_reg = DC_AL_BMCR; 856 break; 857 case MII_BMSR: 858 phy_reg = DC_AL_BMSR; 859 break; 860 case MII_PHYIDR1: 861 phy_reg = DC_AL_VENID; 862 break; 863 case MII_PHYIDR2: 864 phy_reg = DC_AL_DEVID; 865 break; 866 case MII_ANAR: 867 phy_reg = DC_AL_ANAR; 868 break; 869 case MII_ANLPAR: 870 phy_reg = DC_AL_LPAR; 871 break; 872 case MII_ANER: 873 phy_reg = DC_AL_ANER; 874 break; 875 default: 876 printf("dc%d: phy_write: bad phy register %x\n", 877 sc->dc_unit, reg); 878 return(0); 879 break; 880 } 881 882 CSR_WRITE_4(sc, phy_reg, data); 883 return(0); 884 } 885 886 frame.mii_phyaddr = phy; 887 frame.mii_regaddr = reg; 888 frame.mii_data = data; 889 890 if (sc->dc_type == DC_TYPE_98713) { 891 phy_reg = CSR_READ_4(sc, DC_NETCFG); 892 CSR_WRITE_4(sc, DC_NETCFG, phy_reg & ~DC_NETCFG_PORTSEL); 893 } 894 dc_mii_writereg(sc, &frame); 895 if (sc->dc_type == DC_TYPE_98713) 896 CSR_WRITE_4(sc, DC_NETCFG, phy_reg); 897 898 return(0); 899 } 900 901 static void dc_miibus_statchg(dev) 902 device_t dev; 903 { 904 struct dc_softc *sc; 905 struct mii_data *mii; 906 struct ifmedia *ifm; 907 908 sc = device_get_softc(dev); 909 if (DC_IS_ADMTEK(sc)) 910 return; 911 912 mii = device_get_softc(sc->dc_miibus); 913 ifm = &mii->mii_media; 914 if (DC_IS_DAVICOM(sc) && 915 IFM_SUBTYPE(ifm->ifm_media) == IFM_homePNA) { 916 dc_setcfg(sc, ifm->ifm_media); 917 sc->dc_if_media = ifm->ifm_media; 918 } else { 919 dc_setcfg(sc, mii->mii_media_active); 920 sc->dc_if_media = mii->mii_media_active; 921 } 922 923 return; 924 } 925 926 /* 927 * Special support for DM9102A cards with HomePNA PHYs. Note: 928 * with the Davicom DM9102A/DM9801 eval board that I have, it seems 929 * to be impossible to talk to the management interface of the DM9801 930 * PHY (its MDIO pin is not connected to anything). Consequently, 931 * the driver has to just 'know' about the additional mode and deal 932 * with it itself. *sigh* 933 */ 934 static void dc_miibus_mediainit(dev) 935 device_t dev; 936 { 937 struct dc_softc *sc; 938 struct mii_data *mii; 939 struct ifmedia *ifm; 940 int rev; 941 942 rev = pci_read_config(dev, DC_PCI_CFRV, 4) & 0xFF; 943 944 sc = device_get_softc(dev); 945 mii = device_get_softc(sc->dc_miibus); 946 ifm = &mii->mii_media; 947 948 if (DC_IS_DAVICOM(sc) && rev >= DC_REVISION_DM9102A) 949 ifmedia_add(ifm, IFM_ETHER|IFM_homePNA, 0, NULL); 950 951 return; 952 } 953 954 #define DC_POLY 0xEDB88320 955 #define DC_BITS_512 9 956 #define DC_BITS_128 7 957 #define DC_BITS_64 6 958 959 static u_int32_t dc_crc_le(sc, addr) 960 struct dc_softc *sc; 961 caddr_t addr; 962 { 963 u_int32_t idx, bit, data, crc; 964 965 /* Compute CRC for the address value. */ 966 crc = 0xFFFFFFFF; /* initial value */ 967 968 for (idx = 0; idx < 6; idx++) { 969 for (data = *addr++, bit = 0; bit < 8; bit++, data >>= 1) 970 crc = (crc >> 1) ^ (((crc ^ data) & 1) ? DC_POLY : 0); 971 } 972 973 /* 974 * The hash table on the PNIC II and the MX98715AEC-C/D/E 975 * chips is only 128 bits wide. 976 */ 977 if (sc->dc_flags & DC_128BIT_HASH) 978 return (crc & ((1 << DC_BITS_128) - 1)); 979 980 /* The hash table on the MX98715BEC is only 64 bits wide. */ 981 if (sc->dc_flags & DC_64BIT_HASH) 982 return (crc & ((1 << DC_BITS_64) - 1)); 983 984 /* Xircom's hash filtering table is different (read: weird) */ 985 /* Xircom uses the LEAST significant bits */ 986 if (DC_IS_XIRCOM(sc)) { 987 if ((crc & 0x180) == 0x180) 988 return (crc & 0x0F) + (crc & 0x70)*3 + (14 << 4); 989 else 990 return (crc & 0x1F) + ((crc>>1) & 0xF0)*3 + (12 << 4); 991 } 992 993 return (crc & ((1 << DC_BITS_512) - 1)); 994 } 995 996 /* 997 * Calculate CRC of a multicast group address, return the lower 6 bits. 998 */ 999 static u_int32_t dc_crc_be(addr) 1000 caddr_t addr; 1001 { 1002 u_int32_t crc, carry; 1003 int i, j; 1004 u_int8_t c; 1005 1006 /* Compute CRC for the address value. */ 1007 crc = 0xFFFFFFFF; /* initial value */ 1008 1009 for (i = 0; i < 6; i++) { 1010 c = *(addr + i); 1011 for (j = 0; j < 8; j++) { 1012 carry = ((crc & 0x80000000) ? 1 : 0) ^ (c & 0x01); 1013 crc <<= 1; 1014 c >>= 1; 1015 if (carry) 1016 crc = (crc ^ 0x04c11db6) | carry; 1017 } 1018 } 1019 1020 /* return the filter bit position */ 1021 return((crc >> 26) & 0x0000003F); 1022 } 1023 1024 /* 1025 * 21143-style RX filter setup routine. Filter programming is done by 1026 * downloading a special setup frame into the TX engine. 21143, Macronix, 1027 * PNIC, PNIC II and Davicom chips are programmed this way. 1028 * 1029 * We always program the chip using 'hash perfect' mode, i.e. one perfect 1030 * address (our node address) and a 512-bit hash filter for multicast 1031 * frames. We also sneak the broadcast address into the hash filter since 1032 * we need that too. 1033 */ 1034 void dc_setfilt_21143(sc) 1035 struct dc_softc *sc; 1036 { 1037 struct dc_desc *sframe; 1038 u_int32_t h, *sp; 1039 struct ifmultiaddr *ifma; 1040 struct ifnet *ifp; 1041 int i; 1042 1043 ifp = &sc->arpcom.ac_if; 1044 1045 i = sc->dc_cdata.dc_tx_prod; 1046 DC_INC(sc->dc_cdata.dc_tx_prod, DC_TX_LIST_CNT); 1047 sc->dc_cdata.dc_tx_cnt++; 1048 sframe = &sc->dc_ldata->dc_tx_list[i]; 1049 sp = (u_int32_t *)&sc->dc_cdata.dc_sbuf; 1050 bzero((char *)sp, DC_SFRAME_LEN); 1051 1052 sframe->dc_data = vtophys(&sc->dc_cdata.dc_sbuf); 1053 sframe->dc_ctl = DC_SFRAME_LEN | DC_TXCTL_SETUP | DC_TXCTL_TLINK | 1054 DC_FILTER_HASHPERF | DC_TXCTL_FINT; 1055 1056 sc->dc_cdata.dc_tx_chain[i] = (struct mbuf *)&sc->dc_cdata.dc_sbuf; 1057 1058 /* If we want promiscuous mode, set the allframes bit. */ 1059 if (ifp->if_flags & IFF_PROMISC) 1060 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC); 1061 else 1062 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC); 1063 1064 if (ifp->if_flags & IFF_ALLMULTI) 1065 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI); 1066 else 1067 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI); 1068 1069 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 1070 if (ifma->ifma_addr->sa_family != AF_LINK) 1071 continue; 1072 h = dc_crc_le(sc, 1073 LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 1074 sp[h >> 4] |= 1 << (h & 0xF); 1075 } 1076 1077 if (ifp->if_flags & IFF_BROADCAST) { 1078 h = dc_crc_le(sc, (caddr_t)ðerbroadcastaddr); 1079 sp[h >> 4] |= 1 << (h & 0xF); 1080 } 1081 1082 /* Set our MAC address */ 1083 sp[39] = ((u_int16_t *)sc->arpcom.ac_enaddr)[0]; 1084 sp[40] = ((u_int16_t *)sc->arpcom.ac_enaddr)[1]; 1085 sp[41] = ((u_int16_t *)sc->arpcom.ac_enaddr)[2]; 1086 1087 sframe->dc_status = DC_TXSTAT_OWN; 1088 CSR_WRITE_4(sc, DC_TXSTART, 0xFFFFFFFF); 1089 1090 /* 1091 * The PNIC takes an exceedingly long time to process its 1092 * setup frame; wait 10ms after posting the setup frame 1093 * before proceeding, just so it has time to swallow its 1094 * medicine. 1095 */ 1096 DELAY(10000); 1097 1098 ifp->if_timer = 5; 1099 1100 return; 1101 } 1102 1103 void dc_setfilt_admtek(sc) 1104 struct dc_softc *sc; 1105 { 1106 struct ifnet *ifp; 1107 int h = 0; 1108 u_int32_t hashes[2] = { 0, 0 }; 1109 struct ifmultiaddr *ifma; 1110 1111 ifp = &sc->arpcom.ac_if; 1112 1113 /* Init our MAC address */ 1114 CSR_WRITE_4(sc, DC_AL_PAR0, *(u_int32_t *)(&sc->arpcom.ac_enaddr[0])); 1115 CSR_WRITE_4(sc, DC_AL_PAR1, *(u_int32_t *)(&sc->arpcom.ac_enaddr[4])); 1116 1117 /* If we want promiscuous mode, set the allframes bit. */ 1118 if (ifp->if_flags & IFF_PROMISC) 1119 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC); 1120 else 1121 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC); 1122 1123 if (ifp->if_flags & IFF_ALLMULTI) 1124 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI); 1125 else 1126 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI); 1127 1128 /* first, zot all the existing hash bits */ 1129 CSR_WRITE_4(sc, DC_AL_MAR0, 0); 1130 CSR_WRITE_4(sc, DC_AL_MAR1, 0); 1131 1132 /* 1133 * If we're already in promisc or allmulti mode, we 1134 * don't have to bother programming the multicast filter. 1135 */ 1136 if (ifp->if_flags & (IFF_PROMISC|IFF_ALLMULTI)) 1137 return; 1138 1139 /* now program new ones */ 1140 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 1141 if (ifma->ifma_addr->sa_family != AF_LINK) 1142 continue; 1143 h = dc_crc_be(LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 1144 if (h < 32) 1145 hashes[0] |= (1 << h); 1146 else 1147 hashes[1] |= (1 << (h - 32)); 1148 } 1149 1150 CSR_WRITE_4(sc, DC_AL_MAR0, hashes[0]); 1151 CSR_WRITE_4(sc, DC_AL_MAR1, hashes[1]); 1152 1153 return; 1154 } 1155 1156 void dc_setfilt_asix(sc) 1157 struct dc_softc *sc; 1158 { 1159 struct ifnet *ifp; 1160 int h = 0; 1161 u_int32_t hashes[2] = { 0, 0 }; 1162 struct ifmultiaddr *ifma; 1163 1164 ifp = &sc->arpcom.ac_if; 1165 1166 /* Init our MAC address */ 1167 CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_PAR0); 1168 CSR_WRITE_4(sc, DC_AX_FILTDATA, 1169 *(u_int32_t *)(&sc->arpcom.ac_enaddr[0])); 1170 CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_PAR1); 1171 CSR_WRITE_4(sc, DC_AX_FILTDATA, 1172 *(u_int32_t *)(&sc->arpcom.ac_enaddr[4])); 1173 1174 /* If we want promiscuous mode, set the allframes bit. */ 1175 if (ifp->if_flags & IFF_PROMISC) 1176 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC); 1177 else 1178 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC); 1179 1180 if (ifp->if_flags & IFF_ALLMULTI) 1181 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI); 1182 else 1183 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI); 1184 1185 /* 1186 * The ASIX chip has a special bit to enable reception 1187 * of broadcast frames. 1188 */ 1189 if (ifp->if_flags & IFF_BROADCAST) 1190 DC_SETBIT(sc, DC_NETCFG, DC_AX_NETCFG_RX_BROAD); 1191 else 1192 DC_CLRBIT(sc, DC_NETCFG, DC_AX_NETCFG_RX_BROAD); 1193 1194 /* first, zot all the existing hash bits */ 1195 CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_MAR0); 1196 CSR_WRITE_4(sc, DC_AX_FILTDATA, 0); 1197 CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_MAR1); 1198 CSR_WRITE_4(sc, DC_AX_FILTDATA, 0); 1199 1200 /* 1201 * If we're already in promisc or allmulti mode, we 1202 * don't have to bother programming the multicast filter. 1203 */ 1204 if (ifp->if_flags & (IFF_PROMISC|IFF_ALLMULTI)) 1205 return; 1206 1207 /* now program new ones */ 1208 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 1209 if (ifma->ifma_addr->sa_family != AF_LINK) 1210 continue; 1211 h = dc_crc_be(LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 1212 if (h < 32) 1213 hashes[0] |= (1 << h); 1214 else 1215 hashes[1] |= (1 << (h - 32)); 1216 } 1217 1218 CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_MAR0); 1219 CSR_WRITE_4(sc, DC_AX_FILTDATA, hashes[0]); 1220 CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_MAR1); 1221 CSR_WRITE_4(sc, DC_AX_FILTDATA, hashes[1]); 1222 1223 return; 1224 } 1225 1226 void dc_setfilt_xircom(sc) 1227 struct dc_softc *sc; 1228 { 1229 struct dc_desc *sframe; 1230 u_int32_t h, *sp; 1231 struct ifmultiaddr *ifma; 1232 struct ifnet *ifp; 1233 int i; 1234 1235 ifp = &sc->arpcom.ac_if; 1236 DC_CLRBIT(sc, DC_NETCFG, (DC_NETCFG_TX_ON|DC_NETCFG_RX_ON)); 1237 1238 i = sc->dc_cdata.dc_tx_prod; 1239 DC_INC(sc->dc_cdata.dc_tx_prod, DC_TX_LIST_CNT); 1240 sc->dc_cdata.dc_tx_cnt++; 1241 sframe = &sc->dc_ldata->dc_tx_list[i]; 1242 sp = (u_int32_t *)&sc->dc_cdata.dc_sbuf; 1243 bzero((char *)sp, DC_SFRAME_LEN); 1244 1245 sframe->dc_data = vtophys(&sc->dc_cdata.dc_sbuf); 1246 sframe->dc_ctl = DC_SFRAME_LEN | DC_TXCTL_SETUP | DC_TXCTL_TLINK | 1247 DC_FILTER_HASHPERF | DC_TXCTL_FINT; 1248 1249 sc->dc_cdata.dc_tx_chain[i] = (struct mbuf *)&sc->dc_cdata.dc_sbuf; 1250 1251 /* If we want promiscuous mode, set the allframes bit. */ 1252 if (ifp->if_flags & IFF_PROMISC) 1253 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC); 1254 else 1255 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC); 1256 1257 if (ifp->if_flags & IFF_ALLMULTI) 1258 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI); 1259 else 1260 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI); 1261 1262 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 1263 if (ifma->ifma_addr->sa_family != AF_LINK) 1264 continue; 1265 h = dc_crc_le(sc, 1266 LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 1267 sp[h >> 4] |= 1 << (h & 0xF); 1268 } 1269 1270 if (ifp->if_flags & IFF_BROADCAST) { 1271 h = dc_crc_le(sc, (caddr_t)ðerbroadcastaddr); 1272 sp[h >> 4] |= 1 << (h & 0xF); 1273 } 1274 1275 /* Set our MAC address */ 1276 sp[0] = ((u_int16_t *)sc->arpcom.ac_enaddr)[0]; 1277 sp[1] = ((u_int16_t *)sc->arpcom.ac_enaddr)[1]; 1278 sp[2] = ((u_int16_t *)sc->arpcom.ac_enaddr)[2]; 1279 1280 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_TX_ON); 1281 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_ON); 1282 ifp->if_flags |= IFF_RUNNING; 1283 sframe->dc_status = DC_TXSTAT_OWN; 1284 CSR_WRITE_4(sc, DC_TXSTART, 0xFFFFFFFF); 1285 1286 /* 1287 * wait some time... 1288 */ 1289 DELAY(1000); 1290 1291 ifp->if_timer = 5; 1292 1293 return; 1294 } 1295 1296 static void dc_setfilt(sc) 1297 struct dc_softc *sc; 1298 { 1299 if (DC_IS_INTEL(sc) || DC_IS_MACRONIX(sc) || DC_IS_PNIC(sc) || 1300 DC_IS_PNICII(sc) || DC_IS_DAVICOM(sc) || DC_IS_CONEXANT(sc)) 1301 dc_setfilt_21143(sc); 1302 1303 if (DC_IS_ASIX(sc)) 1304 dc_setfilt_asix(sc); 1305 1306 if (DC_IS_ADMTEK(sc)) 1307 dc_setfilt_admtek(sc); 1308 1309 if (DC_IS_XIRCOM(sc)) 1310 dc_setfilt_xircom(sc); 1311 1312 return; 1313 } 1314 1315 /* 1316 * In order to fiddle with the 1317 * 'full-duplex' and '100Mbps' bits in the netconfig register, we 1318 * first have to put the transmit and/or receive logic in the idle state. 1319 */ 1320 static void dc_setcfg(sc, media) 1321 struct dc_softc *sc; 1322 int media; 1323 { 1324 int i, restart = 0; 1325 u_int32_t isr; 1326 1327 if (IFM_SUBTYPE(media) == IFM_NONE) 1328 return; 1329 1330 if (CSR_READ_4(sc, DC_NETCFG) & (DC_NETCFG_TX_ON|DC_NETCFG_RX_ON)) { 1331 restart = 1; 1332 DC_CLRBIT(sc, DC_NETCFG, (DC_NETCFG_TX_ON|DC_NETCFG_RX_ON)); 1333 1334 for (i = 0; i < DC_TIMEOUT; i++) { 1335 isr = CSR_READ_4(sc, DC_ISR); 1336 if (isr & DC_ISR_TX_IDLE && 1337 (isr & DC_ISR_RX_STATE) == DC_RXSTATE_STOPPED) 1338 break; 1339 DELAY(10); 1340 } 1341 1342 if (i == DC_TIMEOUT) 1343 printf("dc%d: failed to force tx and " 1344 "rx to idle state\n", sc->dc_unit); 1345 } 1346 1347 if (IFM_SUBTYPE(media) == IFM_100_TX) { 1348 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_SPEEDSEL); 1349 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_HEARTBEAT); 1350 if (sc->dc_pmode == DC_PMODE_MII) { 1351 int watchdogreg; 1352 1353 if (DC_IS_INTEL(sc)) { 1354 /* there's a write enable bit here that reads as 1 */ 1355 watchdogreg = CSR_READ_4(sc, DC_WATCHDOG); 1356 watchdogreg &= ~DC_WDOG_CTLWREN; 1357 watchdogreg |= DC_WDOG_JABBERDIS; 1358 CSR_WRITE_4(sc, DC_WATCHDOG, watchdogreg); 1359 } else { 1360 DC_SETBIT(sc, DC_WATCHDOG, DC_WDOG_JABBERDIS); 1361 } 1362 DC_CLRBIT(sc, DC_NETCFG, (DC_NETCFG_PCS| 1363 DC_NETCFG_PORTSEL|DC_NETCFG_SCRAMBLER)); 1364 if (sc->dc_type == DC_TYPE_98713) 1365 DC_SETBIT(sc, DC_NETCFG, (DC_NETCFG_PCS| 1366 DC_NETCFG_SCRAMBLER)); 1367 if (!DC_IS_DAVICOM(sc)) 1368 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL); 1369 DC_CLRBIT(sc, DC_10BTCTRL, 0xFFFF); 1370 if (DC_IS_INTEL(sc)) 1371 dc_apply_fixup(sc, IFM_AUTO); 1372 } else { 1373 if (DC_IS_PNIC(sc)) { 1374 DC_PN_GPIO_SETBIT(sc, DC_PN_GPIO_SPEEDSEL); 1375 DC_PN_GPIO_SETBIT(sc, DC_PN_GPIO_100TX_LOOP); 1376 DC_SETBIT(sc, DC_PN_NWAY, DC_PN_NWAY_SPEEDSEL); 1377 } 1378 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL); 1379 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PCS); 1380 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_SCRAMBLER); 1381 if (DC_IS_INTEL(sc)) 1382 dc_apply_fixup(sc, 1383 (media & IFM_GMASK) == IFM_FDX ? 1384 IFM_100_TX|IFM_FDX : IFM_100_TX); 1385 } 1386 } 1387 1388 if (IFM_SUBTYPE(media) == IFM_10_T) { 1389 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_SPEEDSEL); 1390 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_HEARTBEAT); 1391 if (sc->dc_pmode == DC_PMODE_MII) { 1392 int watchdogreg; 1393 1394 /* there's a write enable bit here that reads as 1 */ 1395 if (DC_IS_INTEL(sc)) { 1396 watchdogreg = CSR_READ_4(sc, DC_WATCHDOG); 1397 watchdogreg &= ~DC_WDOG_CTLWREN; 1398 watchdogreg |= DC_WDOG_JABBERDIS; 1399 CSR_WRITE_4(sc, DC_WATCHDOG, watchdogreg); 1400 } else { 1401 DC_SETBIT(sc, DC_WATCHDOG, DC_WDOG_JABBERDIS); 1402 } 1403 DC_CLRBIT(sc, DC_NETCFG, (DC_NETCFG_PCS| 1404 DC_NETCFG_PORTSEL|DC_NETCFG_SCRAMBLER)); 1405 if (sc->dc_type == DC_TYPE_98713) 1406 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PCS); 1407 if (!DC_IS_DAVICOM(sc)) 1408 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL); 1409 DC_CLRBIT(sc, DC_10BTCTRL, 0xFFFF); 1410 if (DC_IS_INTEL(sc)) 1411 dc_apply_fixup(sc, IFM_AUTO); 1412 } else { 1413 if (DC_IS_PNIC(sc)) { 1414 DC_PN_GPIO_CLRBIT(sc, DC_PN_GPIO_SPEEDSEL); 1415 DC_PN_GPIO_SETBIT(sc, DC_PN_GPIO_100TX_LOOP); 1416 DC_CLRBIT(sc, DC_PN_NWAY, DC_PN_NWAY_SPEEDSEL); 1417 } 1418 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL); 1419 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_PCS); 1420 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_SCRAMBLER); 1421 if (DC_IS_INTEL(sc)) { 1422 DC_CLRBIT(sc, DC_SIARESET, DC_SIA_RESET); 1423 DC_CLRBIT(sc, DC_10BTCTRL, 0xFFFF); 1424 if ((media & IFM_GMASK) == IFM_FDX) 1425 DC_SETBIT(sc, DC_10BTCTRL, 0x7F3D); 1426 else 1427 DC_SETBIT(sc, DC_10BTCTRL, 0x7F3F); 1428 DC_SETBIT(sc, DC_SIARESET, DC_SIA_RESET); 1429 DC_CLRBIT(sc, DC_10BTCTRL, 1430 DC_TCTL_AUTONEGENBL); 1431 dc_apply_fixup(sc, 1432 (media & IFM_GMASK) == IFM_FDX ? 1433 IFM_10_T|IFM_FDX : IFM_10_T); 1434 DELAY(20000); 1435 } 1436 } 1437 } 1438 1439 /* 1440 * If this is a Davicom DM9102A card with a DM9801 HomePNA 1441 * PHY and we want HomePNA mode, set the portsel bit to turn 1442 * on the external MII port. 1443 */ 1444 if (DC_IS_DAVICOM(sc)) { 1445 if (IFM_SUBTYPE(media) == IFM_homePNA) { 1446 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL); 1447 sc->dc_link = 1; 1448 } else { 1449 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL); 1450 } 1451 } 1452 1453 if ((media & IFM_GMASK) == IFM_FDX) { 1454 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_FULLDUPLEX); 1455 if (sc->dc_pmode == DC_PMODE_SYM && DC_IS_PNIC(sc)) 1456 DC_SETBIT(sc, DC_PN_NWAY, DC_PN_NWAY_DUPLEX); 1457 } else { 1458 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_FULLDUPLEX); 1459 if (sc->dc_pmode == DC_PMODE_SYM && DC_IS_PNIC(sc)) 1460 DC_CLRBIT(sc, DC_PN_NWAY, DC_PN_NWAY_DUPLEX); 1461 } 1462 1463 if (restart) 1464 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_TX_ON|DC_NETCFG_RX_ON); 1465 1466 return; 1467 } 1468 1469 static void dc_reset(sc) 1470 struct dc_softc *sc; 1471 { 1472 register int i; 1473 1474 DC_SETBIT(sc, DC_BUSCTL, DC_BUSCTL_RESET); 1475 1476 for (i = 0; i < DC_TIMEOUT; i++) { 1477 DELAY(10); 1478 if (!(CSR_READ_4(sc, DC_BUSCTL) & DC_BUSCTL_RESET)) 1479 break; 1480 } 1481 1482 if (DC_IS_ASIX(sc) || DC_IS_ADMTEK(sc) || DC_IS_CONEXANT(sc) || 1483 DC_IS_XIRCOM(sc) || DC_IS_INTEL(sc)) { 1484 DELAY(10000); 1485 DC_CLRBIT(sc, DC_BUSCTL, DC_BUSCTL_RESET); 1486 i = 0; 1487 } 1488 1489 if (i == DC_TIMEOUT) 1490 printf("dc%d: reset never completed!\n", sc->dc_unit); 1491 1492 /* Wait a little while for the chip to get its brains in order. */ 1493 DELAY(1000); 1494 1495 CSR_WRITE_4(sc, DC_IMR, 0x00000000); 1496 CSR_WRITE_4(sc, DC_BUSCTL, 0x00000000); 1497 CSR_WRITE_4(sc, DC_NETCFG, 0x00000000); 1498 1499 /* 1500 * Bring the SIA out of reset. In some cases, it looks 1501 * like failing to unreset the SIA soon enough gets it 1502 * into a state where it will never come out of reset 1503 * until we reset the whole chip again. 1504 */ 1505 if (DC_IS_INTEL(sc)) { 1506 DC_SETBIT(sc, DC_SIARESET, DC_SIA_RESET); 1507 CSR_WRITE_4(sc, DC_10BTCTRL, 0); 1508 CSR_WRITE_4(sc, DC_WATCHDOG, 0); 1509 } 1510 1511 return; 1512 } 1513 1514 static struct dc_type *dc_devtype(dev) 1515 device_t dev; 1516 { 1517 struct dc_type *t; 1518 u_int32_t rev; 1519 1520 t = dc_devs; 1521 1522 while(t->dc_name != NULL) { 1523 if ((pci_get_vendor(dev) == t->dc_vid) && 1524 (pci_get_device(dev) == t->dc_did)) { 1525 /* Check the PCI revision */ 1526 rev = pci_read_config(dev, DC_PCI_CFRV, 4) & 0xFF; 1527 if (t->dc_did == DC_DEVICEID_98713 && 1528 rev >= DC_REVISION_98713A) 1529 t++; 1530 if (t->dc_did == DC_DEVICEID_98713_CP && 1531 rev >= DC_REVISION_98713A) 1532 t++; 1533 if (t->dc_did == DC_DEVICEID_987x5 && 1534 rev >= DC_REVISION_98715AEC_C) 1535 t++; 1536 if (t->dc_did == DC_DEVICEID_987x5 && 1537 rev >= DC_REVISION_98725) 1538 t++; 1539 if (t->dc_did == DC_DEVICEID_AX88140A && 1540 rev >= DC_REVISION_88141) 1541 t++; 1542 if (t->dc_did == DC_DEVICEID_82C168 && 1543 rev >= DC_REVISION_82C169) 1544 t++; 1545 if (t->dc_did == DC_DEVICEID_DM9102 && 1546 rev >= DC_REVISION_DM9102A) 1547 t++; 1548 return(t); 1549 } 1550 t++; 1551 } 1552 1553 return(NULL); 1554 } 1555 1556 /* 1557 * Probe for a 21143 or clone chip. Check the PCI vendor and device 1558 * IDs against our list and return a device name if we find a match. 1559 * We do a little bit of extra work to identify the exact type of 1560 * chip. The MX98713 and MX98713A have the same PCI vendor/device ID, 1561 * but different revision IDs. The same is true for 98715/98715A 1562 * chips and the 98725, as well as the ASIX and ADMtek chips. In some 1563 * cases, the exact chip revision affects driver behavior. 1564 */ 1565 static int dc_probe(dev) 1566 device_t dev; 1567 { 1568 struct dc_type *t; 1569 1570 t = dc_devtype(dev); 1571 1572 if (t != NULL) { 1573 device_set_desc(dev, t->dc_name); 1574 return(0); 1575 } 1576 1577 return(ENXIO); 1578 } 1579 1580 static void dc_acpi(dev) 1581 device_t dev; 1582 { 1583 int unit; 1584 1585 unit = device_get_unit(dev); 1586 1587 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) { 1588 u_int32_t iobase, membase, irq; 1589 1590 /* Save important PCI config data. */ 1591 iobase = pci_read_config(dev, DC_PCI_CFBIO, 4); 1592 membase = pci_read_config(dev, DC_PCI_CFBMA, 4); 1593 irq = pci_read_config(dev, DC_PCI_CFIT, 4); 1594 1595 /* Reset the power state. */ 1596 printf("dc%d: chip is in D%d power mode " 1597 "-- setting to D0\n", unit, 1598 pci_get_powerstate(dev)); 1599 pci_set_powerstate(dev, PCI_POWERSTATE_D0); 1600 1601 /* Restore PCI config data. */ 1602 pci_write_config(dev, DC_PCI_CFBIO, iobase, 4); 1603 pci_write_config(dev, DC_PCI_CFBMA, membase, 4); 1604 pci_write_config(dev, DC_PCI_CFIT, irq, 4); 1605 } 1606 1607 return; 1608 } 1609 1610 static void dc_apply_fixup(sc, media) 1611 struct dc_softc *sc; 1612 int media; 1613 { 1614 struct dc_mediainfo *m; 1615 u_int8_t *p; 1616 int i; 1617 u_int32_t reg; 1618 1619 m = sc->dc_mi; 1620 1621 while (m != NULL) { 1622 if (m->dc_media == media) 1623 break; 1624 m = m->dc_next; 1625 } 1626 1627 if (m == NULL) 1628 return; 1629 1630 for (i = 0, p = m->dc_reset_ptr; i < m->dc_reset_len; i++, p += 2) { 1631 reg = (p[0] | (p[1] << 8)) << 16; 1632 CSR_WRITE_4(sc, DC_WATCHDOG, reg); 1633 } 1634 1635 for (i = 0, p = m->dc_gp_ptr; i < m->dc_gp_len; i++, p += 2) { 1636 reg = (p[0] | (p[1] << 8)) << 16; 1637 CSR_WRITE_4(sc, DC_WATCHDOG, reg); 1638 } 1639 1640 return; 1641 } 1642 1643 static void dc_decode_leaf_sia(sc, l) 1644 struct dc_softc *sc; 1645 struct dc_eblock_sia *l; 1646 { 1647 struct dc_mediainfo *m; 1648 1649 m = malloc(sizeof(struct dc_mediainfo), M_DEVBUF, M_NOWAIT); 1650 bzero(m, sizeof(struct dc_mediainfo)); 1651 if (l->dc_sia_code == DC_SIA_CODE_10BT) 1652 m->dc_media = IFM_10_T; 1653 1654 if (l->dc_sia_code == DC_SIA_CODE_10BT_FDX) 1655 m->dc_media = IFM_10_T|IFM_FDX; 1656 1657 if (l->dc_sia_code == DC_SIA_CODE_10B2) 1658 m->dc_media = IFM_10_2; 1659 1660 if (l->dc_sia_code == DC_SIA_CODE_10B5) 1661 m->dc_media = IFM_10_5; 1662 1663 m->dc_gp_len = 2; 1664 m->dc_gp_ptr = (u_int8_t *)&l->dc_sia_gpio_ctl; 1665 1666 m->dc_next = sc->dc_mi; 1667 sc->dc_mi = m; 1668 1669 sc->dc_pmode = DC_PMODE_SIA; 1670 1671 return; 1672 } 1673 1674 static void dc_decode_leaf_sym(sc, l) 1675 struct dc_softc *sc; 1676 struct dc_eblock_sym *l; 1677 { 1678 struct dc_mediainfo *m; 1679 1680 m = malloc(sizeof(struct dc_mediainfo), M_DEVBUF, M_NOWAIT); 1681 bzero(m, sizeof(struct dc_mediainfo)); 1682 if (l->dc_sym_code == DC_SYM_CODE_100BT) 1683 m->dc_media = IFM_100_TX; 1684 1685 if (l->dc_sym_code == DC_SYM_CODE_100BT_FDX) 1686 m->dc_media = IFM_100_TX|IFM_FDX; 1687 1688 m->dc_gp_len = 2; 1689 m->dc_gp_ptr = (u_int8_t *)&l->dc_sym_gpio_ctl; 1690 1691 m->dc_next = sc->dc_mi; 1692 sc->dc_mi = m; 1693 1694 sc->dc_pmode = DC_PMODE_SYM; 1695 1696 return; 1697 } 1698 1699 static void dc_decode_leaf_mii(sc, l) 1700 struct dc_softc *sc; 1701 struct dc_eblock_mii *l; 1702 { 1703 u_int8_t *p; 1704 struct dc_mediainfo *m; 1705 1706 m = malloc(sizeof(struct dc_mediainfo), M_DEVBUF, M_NOWAIT); 1707 bzero(m, sizeof(struct dc_mediainfo)); 1708 /* We abuse IFM_AUTO to represent MII. */ 1709 m->dc_media = IFM_AUTO; 1710 m->dc_gp_len = l->dc_gpr_len; 1711 1712 p = (u_int8_t *)l; 1713 p += sizeof(struct dc_eblock_mii); 1714 m->dc_gp_ptr = p; 1715 p += 2 * l->dc_gpr_len; 1716 m->dc_reset_len = *p; 1717 p++; 1718 m->dc_reset_ptr = p; 1719 1720 m->dc_next = sc->dc_mi; 1721 sc->dc_mi = m; 1722 1723 return; 1724 } 1725 1726 static void dc_parse_21143_srom(sc) 1727 struct dc_softc *sc; 1728 { 1729 struct dc_leaf_hdr *lhdr; 1730 struct dc_eblock_hdr *hdr; 1731 int i, loff; 1732 char *ptr; 1733 1734 loff = sc->dc_srom[27]; 1735 lhdr = (struct dc_leaf_hdr *)&(sc->dc_srom[loff]); 1736 1737 ptr = (char *)lhdr; 1738 ptr += sizeof(struct dc_leaf_hdr) - 1; 1739 for (i = 0; i < lhdr->dc_mcnt; i++) { 1740 hdr = (struct dc_eblock_hdr *)ptr; 1741 switch(hdr->dc_type) { 1742 case DC_EBLOCK_MII: 1743 dc_decode_leaf_mii(sc, (struct dc_eblock_mii *)hdr); 1744 break; 1745 case DC_EBLOCK_SIA: 1746 dc_decode_leaf_sia(sc, (struct dc_eblock_sia *)hdr); 1747 break; 1748 case DC_EBLOCK_SYM: 1749 dc_decode_leaf_sym(sc, (struct dc_eblock_sym *)hdr); 1750 break; 1751 default: 1752 /* Don't care. Yet. */ 1753 break; 1754 } 1755 ptr += (hdr->dc_len & 0x7F); 1756 ptr++; 1757 } 1758 1759 return; 1760 } 1761 1762 /* 1763 * Attach the interface. Allocate softc structures, do ifmedia 1764 * setup and ethernet/BPF attach. 1765 */ 1766 static int dc_attach(dev) 1767 device_t dev; 1768 { 1769 int tmp = 0; 1770 u_char eaddr[ETHER_ADDR_LEN]; 1771 u_int32_t command; 1772 struct dc_softc *sc; 1773 struct ifnet *ifp; 1774 u_int32_t revision; 1775 int unit, error = 0, rid, mac_offset; 1776 1777 sc = device_get_softc(dev); 1778 unit = device_get_unit(dev); 1779 bzero(sc, sizeof(struct dc_softc)); 1780 1781 mtx_init(&sc->dc_mtx, device_get_nameunit(dev), MTX_DEF | MTX_RECURSE); 1782 DC_LOCK(sc); 1783 1784 /* 1785 * Handle power management nonsense. 1786 */ 1787 dc_acpi(dev); 1788 1789 /* 1790 * Map control/status registers. 1791 */ 1792 pci_enable_busmaster(dev); 1793 pci_enable_io(dev, SYS_RES_IOPORT); 1794 pci_enable_io(dev, SYS_RES_MEMORY); 1795 command = pci_read_config(dev, PCIR_COMMAND, 4); 1796 1797 #ifdef DC_USEIOSPACE 1798 if (!(command & PCIM_CMD_PORTEN)) { 1799 printf("dc%d: failed to enable I/O ports!\n", unit); 1800 error = ENXIO; 1801 goto fail; 1802 } 1803 #else 1804 if (!(command & PCIM_CMD_MEMEN)) { 1805 printf("dc%d: failed to enable memory mapping!\n", unit); 1806 error = ENXIO; 1807 goto fail; 1808 } 1809 #endif 1810 1811 rid = DC_RID; 1812 sc->dc_res = bus_alloc_resource(dev, DC_RES, &rid, 1813 0, ~0, 1, RF_ACTIVE); 1814 1815 if (sc->dc_res == NULL) { 1816 printf("dc%d: couldn't map ports/memory\n", unit); 1817 error = ENXIO; 1818 goto fail; 1819 } 1820 1821 sc->dc_btag = rman_get_bustag(sc->dc_res); 1822 sc->dc_bhandle = rman_get_bushandle(sc->dc_res); 1823 1824 /* Allocate interrupt */ 1825 rid = 0; 1826 sc->dc_irq = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, 0, ~0, 1, 1827 RF_SHAREABLE | RF_ACTIVE); 1828 1829 if (sc->dc_irq == NULL) { 1830 printf("dc%d: couldn't map interrupt\n", unit); 1831 bus_release_resource(dev, DC_RES, DC_RID, sc->dc_res); 1832 error = ENXIO; 1833 goto fail; 1834 } 1835 1836 error = bus_setup_intr(dev, sc->dc_irq, INTR_TYPE_NET | 1837 (IS_MPSAFE ? INTR_MPSAFE : 0), 1838 dc_intr, sc, &sc->dc_intrhand); 1839 1840 if (error) { 1841 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->dc_irq); 1842 bus_release_resource(dev, DC_RES, DC_RID, sc->dc_res); 1843 printf("dc%d: couldn't set up irq\n", unit); 1844 goto fail; 1845 } 1846 1847 /* Need this info to decide on a chip type. */ 1848 sc->dc_info = dc_devtype(dev); 1849 revision = pci_read_config(dev, DC_PCI_CFRV, 4) & 0x000000FF; 1850 1851 switch(sc->dc_info->dc_did) { 1852 case DC_DEVICEID_21143: 1853 sc->dc_type = DC_TYPE_21143; 1854 sc->dc_flags |= DC_TX_POLL|DC_TX_USE_TX_INTR; 1855 sc->dc_flags |= DC_REDUCED_MII_POLL; 1856 /* Save EEPROM contents so we can parse them later. */ 1857 dc_read_eeprom(sc, (caddr_t)&sc->dc_srom, 0, 512, 0); 1858 break; 1859 case DC_DEVICEID_DM9100: 1860 case DC_DEVICEID_DM9102: 1861 sc->dc_type = DC_TYPE_DM9102; 1862 sc->dc_flags |= DC_TX_COALESCE|DC_TX_INTR_ALWAYS; 1863 sc->dc_flags |= DC_REDUCED_MII_POLL|DC_TX_STORENFWD; 1864 sc->dc_pmode = DC_PMODE_MII; 1865 /* Increase the latency timer value. */ 1866 command = pci_read_config(dev, DC_PCI_CFLT, 4); 1867 command &= 0xFFFF00FF; 1868 command |= 0x00008000; 1869 pci_write_config(dev, DC_PCI_CFLT, command, 4); 1870 break; 1871 case DC_DEVICEID_AL981: 1872 sc->dc_type = DC_TYPE_AL981; 1873 sc->dc_flags |= DC_TX_USE_TX_INTR; 1874 sc->dc_flags |= DC_TX_ADMTEK_WAR; 1875 sc->dc_pmode = DC_PMODE_MII; 1876 break; 1877 case DC_DEVICEID_AN985: 1878 case DC_DEVICEID_FE2500: 1879 case DC_DEVICEID_EN2242: 1880 sc->dc_type = DC_TYPE_AN985; 1881 sc->dc_flags |= DC_TX_USE_TX_INTR; 1882 sc->dc_flags |= DC_TX_ADMTEK_WAR; 1883 sc->dc_pmode = DC_PMODE_MII; 1884 break; 1885 case DC_DEVICEID_98713: 1886 case DC_DEVICEID_98713_CP: 1887 if (revision < DC_REVISION_98713A) { 1888 sc->dc_type = DC_TYPE_98713; 1889 } 1890 if (revision >= DC_REVISION_98713A) { 1891 sc->dc_type = DC_TYPE_98713A; 1892 sc->dc_flags |= DC_21143_NWAY; 1893 } 1894 sc->dc_flags |= DC_REDUCED_MII_POLL; 1895 sc->dc_flags |= DC_TX_POLL|DC_TX_USE_TX_INTR; 1896 break; 1897 case DC_DEVICEID_987x5: 1898 case DC_DEVICEID_EN1217: 1899 /* 1900 * Macronix MX98715AEC-C/D/E parts have only a 1901 * 128-bit hash table. We need to deal with these 1902 * in the same manner as the PNIC II so that we 1903 * get the right number of bits out of the 1904 * CRC routine. 1905 */ 1906 if (revision >= DC_REVISION_98715AEC_C && 1907 revision < DC_REVISION_98725) 1908 sc->dc_flags |= DC_128BIT_HASH; 1909 sc->dc_type = DC_TYPE_987x5; 1910 sc->dc_flags |= DC_TX_POLL|DC_TX_USE_TX_INTR; 1911 sc->dc_flags |= DC_REDUCED_MII_POLL|DC_21143_NWAY; 1912 break; 1913 case DC_DEVICEID_98727: 1914 sc->dc_type = DC_TYPE_987x5; 1915 sc->dc_flags |= DC_TX_POLL|DC_TX_USE_TX_INTR; 1916 sc->dc_flags |= DC_REDUCED_MII_POLL|DC_21143_NWAY; 1917 break; 1918 case DC_DEVICEID_82C115: 1919 sc->dc_type = DC_TYPE_PNICII; 1920 sc->dc_flags |= DC_TX_POLL|DC_TX_USE_TX_INTR|DC_128BIT_HASH; 1921 sc->dc_flags |= DC_REDUCED_MII_POLL|DC_21143_NWAY; 1922 break; 1923 case DC_DEVICEID_82C168: 1924 sc->dc_type = DC_TYPE_PNIC; 1925 sc->dc_flags |= DC_TX_STORENFWD|DC_TX_INTR_ALWAYS; 1926 sc->dc_flags |= DC_PNIC_RX_BUG_WAR; 1927 sc->dc_pnic_rx_buf = malloc(DC_RXLEN * 5, M_DEVBUF, M_NOWAIT); 1928 if (revision < DC_REVISION_82C169) 1929 sc->dc_pmode = DC_PMODE_SYM; 1930 break; 1931 case DC_DEVICEID_AX88140A: 1932 sc->dc_type = DC_TYPE_ASIX; 1933 sc->dc_flags |= DC_TX_USE_TX_INTR|DC_TX_INTR_FIRSTFRAG; 1934 sc->dc_flags |= DC_REDUCED_MII_POLL; 1935 sc->dc_pmode = DC_PMODE_MII; 1936 break; 1937 case DC_DEVICEID_X3201: 1938 sc->dc_type = DC_TYPE_XIRCOM; 1939 sc->dc_flags |= DC_TX_INTR_ALWAYS | DC_TX_COALESCE; 1940 /* 1941 * We don't actually need to coalesce, but we're doing 1942 * it to obtain a double word aligned buffer. 1943 */ 1944 break; 1945 case DC_DEVICEID_RS7112: 1946 sc->dc_type = DC_TYPE_CONEXANT; 1947 sc->dc_flags |= DC_TX_INTR_ALWAYS; 1948 sc->dc_flags |= DC_REDUCED_MII_POLL; 1949 sc->dc_pmode = DC_PMODE_MII; 1950 dc_read_eeprom(sc, (caddr_t)&sc->dc_srom, 0, 256, 0); 1951 break; 1952 default: 1953 printf("dc%d: unknown device: %x\n", sc->dc_unit, 1954 sc->dc_info->dc_did); 1955 break; 1956 } 1957 1958 /* Save the cache line size. */ 1959 if (DC_IS_DAVICOM(sc)) 1960 sc->dc_cachesize = 0; 1961 else 1962 sc->dc_cachesize = pci_read_config(dev, 1963 DC_PCI_CFLT, 4) & 0xFF; 1964 1965 /* Reset the adapter. */ 1966 dc_reset(sc); 1967 1968 /* Take 21143 out of snooze mode */ 1969 if (DC_IS_INTEL(sc) || DC_IS_XIRCOM(sc)) { 1970 command = pci_read_config(dev, DC_PCI_CFDD, 4); 1971 command &= ~(DC_CFDD_SNOOZE_MODE|DC_CFDD_SLEEP_MODE); 1972 pci_write_config(dev, DC_PCI_CFDD, command, 4); 1973 } 1974 1975 /* 1976 * Try to learn something about the supported media. 1977 * We know that ASIX and ADMtek and Davicom devices 1978 * will *always* be using MII media, so that's a no-brainer. 1979 * The tricky ones are the Macronix/PNIC II and the 1980 * Intel 21143. 1981 */ 1982 if (DC_IS_INTEL(sc)) 1983 dc_parse_21143_srom(sc); 1984 else if (DC_IS_MACRONIX(sc) || DC_IS_PNICII(sc)) { 1985 if (sc->dc_type == DC_TYPE_98713) 1986 sc->dc_pmode = DC_PMODE_MII; 1987 else 1988 sc->dc_pmode = DC_PMODE_SYM; 1989 } else if (!sc->dc_pmode) 1990 sc->dc_pmode = DC_PMODE_MII; 1991 1992 /* 1993 * Get station address from the EEPROM. 1994 */ 1995 switch(sc->dc_type) { 1996 case DC_TYPE_98713: 1997 case DC_TYPE_98713A: 1998 case DC_TYPE_987x5: 1999 case DC_TYPE_PNICII: 2000 dc_read_eeprom(sc, (caddr_t)&mac_offset, 2001 (DC_EE_NODEADDR_OFFSET / 2), 1, 0); 2002 dc_read_eeprom(sc, (caddr_t)&eaddr, (mac_offset / 2), 3, 0); 2003 break; 2004 case DC_TYPE_PNIC: 2005 dc_read_eeprom(sc, (caddr_t)&eaddr, 0, 3, 1); 2006 break; 2007 case DC_TYPE_DM9102: 2008 case DC_TYPE_21143: 2009 case DC_TYPE_ASIX: 2010 dc_read_eeprom(sc, (caddr_t)&eaddr, DC_EE_NODEADDR, 3, 0); 2011 break; 2012 case DC_TYPE_AL981: 2013 case DC_TYPE_AN985: 2014 dc_read_eeprom(sc, (caddr_t)&eaddr, DC_AL_EE_NODEADDR, 3, 0); 2015 break; 2016 case DC_TYPE_CONEXANT: 2017 bcopy(sc->dc_srom + DC_CONEXANT_EE_NODEADDR, &eaddr, 6); 2018 break; 2019 case DC_TYPE_XIRCOM: 2020 dc_read_eeprom(sc, (caddr_t)&eaddr, 3, 3, 0); 2021 break; 2022 default: 2023 dc_read_eeprom(sc, (caddr_t)&eaddr, DC_EE_NODEADDR, 3, 0); 2024 break; 2025 } 2026 2027 /* 2028 * A 21143 or clone chip was detected. Inform the world. 2029 */ 2030 printf("dc%d: Ethernet address: %6D\n", unit, eaddr, ":"); 2031 2032 sc->dc_unit = unit; 2033 bcopy(eaddr, (char *)&sc->arpcom.ac_enaddr, ETHER_ADDR_LEN); 2034 2035 sc->dc_ldata = contigmalloc(sizeof(struct dc_list_data), M_DEVBUF, 2036 M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0); 2037 2038 if (sc->dc_ldata == NULL) { 2039 printf("dc%d: no memory for list buffers!\n", unit); 2040 bus_teardown_intr(dev, sc->dc_irq, sc->dc_intrhand); 2041 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->dc_irq); 2042 bus_release_resource(dev, DC_RES, DC_RID, sc->dc_res); 2043 error = ENXIO; 2044 goto fail; 2045 } 2046 2047 bzero(sc->dc_ldata, sizeof(struct dc_list_data)); 2048 2049 ifp = &sc->arpcom.ac_if; 2050 ifp->if_softc = sc; 2051 ifp->if_unit = unit; 2052 ifp->if_name = "dc"; 2053 /* XXX: bleah, MTU gets overwritten in ether_ifattach() */ 2054 ifp->if_mtu = ETHERMTU; 2055 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 2056 ifp->if_ioctl = dc_ioctl; 2057 ifp->if_output = ether_output; 2058 ifp->if_start = dc_start; 2059 ifp->if_watchdog = dc_watchdog; 2060 ifp->if_init = dc_init; 2061 ifp->if_baudrate = 10000000; 2062 ifp->if_snd.ifq_maxlen = DC_TX_LIST_CNT - 1; 2063 ifp->if_mpsafe = IS_MPSAFE; 2064 2065 /* 2066 * Do MII setup. If this is a 21143, check for a PHY on the 2067 * MII bus after applying any necessary fixups to twiddle the 2068 * GPIO bits. If we don't end up finding a PHY, restore the 2069 * old selection (SIA only or SIA/SYM) and attach the dcphy 2070 * driver instead. 2071 */ 2072 if (DC_IS_INTEL(sc)) { 2073 dc_apply_fixup(sc, IFM_AUTO); 2074 tmp = sc->dc_pmode; 2075 sc->dc_pmode = DC_PMODE_MII; 2076 } 2077 2078 error = mii_phy_probe(dev, &sc->dc_miibus, 2079 dc_ifmedia_upd, dc_ifmedia_sts); 2080 2081 if (error && DC_IS_INTEL(sc)) { 2082 sc->dc_pmode = tmp; 2083 if (sc->dc_pmode != DC_PMODE_SIA) 2084 sc->dc_pmode = DC_PMODE_SYM; 2085 sc->dc_flags |= DC_21143_NWAY; 2086 mii_phy_probe(dev, &sc->dc_miibus, 2087 dc_ifmedia_upd, dc_ifmedia_sts); 2088 /* 2089 * For non-MII cards, we need to have the 21143 2090 * drive the LEDs. Except there are some systems 2091 * like the NEC VersaPro NoteBook PC which have no 2092 * LEDs, and twiddling these bits has adverse effects 2093 * on them. (I.e. you suddenly can't get a link.) 2094 */ 2095 if (pci_read_config(dev, DC_PCI_CSID, 4) != 0x80281033) 2096 sc->dc_flags |= DC_TULIP_LEDS; 2097 error = 0; 2098 } 2099 2100 if (error) { 2101 printf("dc%d: MII without any PHY!\n", sc->dc_unit); 2102 bus_teardown_intr(dev, sc->dc_irq, sc->dc_intrhand); 2103 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->dc_irq); 2104 bus_release_resource(dev, DC_RES, DC_RID, sc->dc_res); 2105 error = ENXIO; 2106 goto fail; 2107 } 2108 2109 if (DC_IS_XIRCOM(sc)) { 2110 /* 2111 * setup General Purpose Port mode and data so the tulip 2112 * can talk to the MII. 2113 */ 2114 CSR_WRITE_4(sc, DC_SIAGP, DC_SIAGP_WRITE_EN | DC_SIAGP_INT1_EN | 2115 DC_SIAGP_MD_GP2_OUTPUT | DC_SIAGP_MD_GP0_OUTPUT); 2116 DELAY(10); 2117 CSR_WRITE_4(sc, DC_SIAGP, DC_SIAGP_INT1_EN | 2118 DC_SIAGP_MD_GP2_OUTPUT | DC_SIAGP_MD_GP0_OUTPUT); 2119 DELAY(10); 2120 } 2121 2122 /* 2123 * Call MI attach routine. 2124 */ 2125 ether_ifattach(ifp, ETHER_BPF_SUPPORTED); 2126 callout_init(&sc->dc_stat_ch, IS_MPSAFE); 2127 2128 #ifdef SRM_MEDIA 2129 sc->dc_srm_media = 0; 2130 2131 /* Remember the SRM console media setting */ 2132 if (DC_IS_INTEL(sc)) { 2133 command = pci_read_config(dev, DC_PCI_CFDD, 4); 2134 command &= ~(DC_CFDD_SNOOZE_MODE|DC_CFDD_SLEEP_MODE); 2135 switch ((command >> 8) & 0xff) { 2136 case 3: 2137 sc->dc_srm_media = IFM_10_T; 2138 break; 2139 case 4: 2140 sc->dc_srm_media = IFM_10_T | IFM_FDX; 2141 break; 2142 case 5: 2143 sc->dc_srm_media = IFM_100_TX; 2144 break; 2145 case 6: 2146 sc->dc_srm_media = IFM_100_TX | IFM_FDX; 2147 break; 2148 } 2149 if (sc->dc_srm_media) 2150 sc->dc_srm_media |= IFM_ACTIVE | IFM_ETHER; 2151 } 2152 #endif 2153 2154 DC_UNLOCK(sc); 2155 return(0); 2156 2157 fail: 2158 DC_UNLOCK(sc); 2159 mtx_destroy(&sc->dc_mtx); 2160 return(error); 2161 } 2162 2163 static int dc_detach(dev) 2164 device_t dev; 2165 { 2166 struct dc_softc *sc; 2167 struct ifnet *ifp; 2168 struct dc_mediainfo *m; 2169 2170 sc = device_get_softc(dev); 2171 2172 DC_LOCK(sc); 2173 2174 ifp = &sc->arpcom.ac_if; 2175 2176 dc_stop(sc); 2177 ether_ifdetach(ifp, ETHER_BPF_SUPPORTED); 2178 2179 bus_generic_detach(dev); 2180 device_delete_child(dev, sc->dc_miibus); 2181 2182 bus_teardown_intr(dev, sc->dc_irq, sc->dc_intrhand); 2183 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->dc_irq); 2184 bus_release_resource(dev, DC_RES, DC_RID, sc->dc_res); 2185 2186 contigfree(sc->dc_ldata, sizeof(struct dc_list_data), M_DEVBUF); 2187 if (sc->dc_pnic_rx_buf != NULL) 2188 free(sc->dc_pnic_rx_buf, M_DEVBUF); 2189 2190 while(sc->dc_mi != NULL) { 2191 m = sc->dc_mi->dc_next; 2192 free(sc->dc_mi, M_DEVBUF); 2193 sc->dc_mi = m; 2194 } 2195 2196 DC_UNLOCK(sc); 2197 mtx_destroy(&sc->dc_mtx); 2198 2199 return(0); 2200 } 2201 2202 /* 2203 * Initialize the transmit descriptors. 2204 */ 2205 static int dc_list_tx_init(sc) 2206 struct dc_softc *sc; 2207 { 2208 struct dc_chain_data *cd; 2209 struct dc_list_data *ld; 2210 int i; 2211 2212 cd = &sc->dc_cdata; 2213 ld = sc->dc_ldata; 2214 for (i = 0; i < DC_TX_LIST_CNT; i++) { 2215 if (i == (DC_TX_LIST_CNT - 1)) { 2216 ld->dc_tx_list[i].dc_next = 2217 vtophys(&ld->dc_tx_list[0]); 2218 } else { 2219 ld->dc_tx_list[i].dc_next = 2220 vtophys(&ld->dc_tx_list[i + 1]); 2221 } 2222 cd->dc_tx_chain[i] = NULL; 2223 ld->dc_tx_list[i].dc_data = 0; 2224 ld->dc_tx_list[i].dc_ctl = 0; 2225 } 2226 2227 cd->dc_tx_prod = cd->dc_tx_cons = cd->dc_tx_cnt = 0; 2228 2229 return(0); 2230 } 2231 2232 2233 /* 2234 * Initialize the RX descriptors and allocate mbufs for them. Note that 2235 * we arrange the descriptors in a closed ring, so that the last descriptor 2236 * points back to the first. 2237 */ 2238 static int dc_list_rx_init(sc) 2239 struct dc_softc *sc; 2240 { 2241 struct dc_chain_data *cd; 2242 struct dc_list_data *ld; 2243 int i; 2244 2245 cd = &sc->dc_cdata; 2246 ld = sc->dc_ldata; 2247 2248 for (i = 0; i < DC_RX_LIST_CNT; i++) { 2249 if (dc_newbuf(sc, i, NULL) == ENOBUFS) 2250 return(ENOBUFS); 2251 if (i == (DC_RX_LIST_CNT - 1)) { 2252 ld->dc_rx_list[i].dc_next = 2253 vtophys(&ld->dc_rx_list[0]); 2254 } else { 2255 ld->dc_rx_list[i].dc_next = 2256 vtophys(&ld->dc_rx_list[i + 1]); 2257 } 2258 } 2259 2260 cd->dc_rx_prod = 0; 2261 2262 return(0); 2263 } 2264 2265 /* 2266 * Initialize an RX descriptor and attach an MBUF cluster. 2267 */ 2268 static int dc_newbuf(sc, i, m) 2269 struct dc_softc *sc; 2270 int i; 2271 struct mbuf *m; 2272 { 2273 struct mbuf *m_new = NULL; 2274 struct dc_desc *c; 2275 2276 c = &sc->dc_ldata->dc_rx_list[i]; 2277 2278 if (m == NULL) { 2279 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 2280 if (m_new == NULL) { 2281 printf("dc%d: no memory for rx list " 2282 "-- packet dropped!\n", sc->dc_unit); 2283 return(ENOBUFS); 2284 } 2285 2286 MCLGET(m_new, M_DONTWAIT); 2287 if (!(m_new->m_flags & M_EXT)) { 2288 printf("dc%d: no memory for rx list " 2289 "-- packet dropped!\n", sc->dc_unit); 2290 m_freem(m_new); 2291 return(ENOBUFS); 2292 } 2293 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 2294 } else { 2295 m_new = m; 2296 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 2297 m_new->m_data = m_new->m_ext.ext_buf; 2298 } 2299 2300 m_adj(m_new, sizeof(u_int64_t)); 2301 2302 /* 2303 * If this is a PNIC chip, zero the buffer. This is part 2304 * of the workaround for the receive bug in the 82c168 and 2305 * 82c169 chips. 2306 */ 2307 if (sc->dc_flags & DC_PNIC_RX_BUG_WAR) 2308 bzero((char *)mtod(m_new, char *), m_new->m_len); 2309 2310 sc->dc_cdata.dc_rx_chain[i] = m_new; 2311 c->dc_data = vtophys(mtod(m_new, caddr_t)); 2312 c->dc_ctl = DC_RXCTL_RLINK | DC_RXLEN; 2313 c->dc_status = DC_RXSTAT_OWN; 2314 2315 return(0); 2316 } 2317 2318 /* 2319 * Grrrrr. 2320 * The PNIC chip has a terrible bug in it that manifests itself during 2321 * periods of heavy activity. The exact mode of failure if difficult to 2322 * pinpoint: sometimes it only happens in promiscuous mode, sometimes it 2323 * will happen on slow machines. The bug is that sometimes instead of 2324 * uploading one complete frame during reception, it uploads what looks 2325 * like the entire contents of its FIFO memory. The frame we want is at 2326 * the end of the whole mess, but we never know exactly how much data has 2327 * been uploaded, so salvaging the frame is hard. 2328 * 2329 * There is only one way to do it reliably, and it's disgusting. 2330 * Here's what we know: 2331 * 2332 * - We know there will always be somewhere between one and three extra 2333 * descriptors uploaded. 2334 * 2335 * - We know the desired received frame will always be at the end of the 2336 * total data upload. 2337 * 2338 * - We know the size of the desired received frame because it will be 2339 * provided in the length field of the status word in the last descriptor. 2340 * 2341 * Here's what we do: 2342 * 2343 * - When we allocate buffers for the receive ring, we bzero() them. 2344 * This means that we know that the buffer contents should be all 2345 * zeros, except for data uploaded by the chip. 2346 * 2347 * - We also force the PNIC chip to upload frames that include the 2348 * ethernet CRC at the end. 2349 * 2350 * - We gather all of the bogus frame data into a single buffer. 2351 * 2352 * - We then position a pointer at the end of this buffer and scan 2353 * backwards until we encounter the first non-zero byte of data. 2354 * This is the end of the received frame. We know we will encounter 2355 * some data at the end of the frame because the CRC will always be 2356 * there, so even if the sender transmits a packet of all zeros, 2357 * we won't be fooled. 2358 * 2359 * - We know the size of the actual received frame, so we subtract 2360 * that value from the current pointer location. This brings us 2361 * to the start of the actual received packet. 2362 * 2363 * - We copy this into an mbuf and pass it on, along with the actual 2364 * frame length. 2365 * 2366 * The performance hit is tremendous, but it beats dropping frames all 2367 * the time. 2368 */ 2369 2370 #define DC_WHOLEFRAME (DC_RXSTAT_FIRSTFRAG|DC_RXSTAT_LASTFRAG) 2371 static void dc_pnic_rx_bug_war(sc, idx) 2372 struct dc_softc *sc; 2373 int idx; 2374 { 2375 struct dc_desc *cur_rx; 2376 struct dc_desc *c = NULL; 2377 struct mbuf *m = NULL; 2378 unsigned char *ptr; 2379 int i, total_len; 2380 u_int32_t rxstat = 0; 2381 2382 i = sc->dc_pnic_rx_bug_save; 2383 cur_rx = &sc->dc_ldata->dc_rx_list[idx]; 2384 ptr = sc->dc_pnic_rx_buf; 2385 bzero(ptr, sizeof(DC_RXLEN * 5)); 2386 2387 /* Copy all the bytes from the bogus buffers. */ 2388 while (1) { 2389 c = &sc->dc_ldata->dc_rx_list[i]; 2390 rxstat = c->dc_status; 2391 m = sc->dc_cdata.dc_rx_chain[i]; 2392 bcopy(mtod(m, char *), ptr, DC_RXLEN); 2393 ptr += DC_RXLEN; 2394 /* If this is the last buffer, break out. */ 2395 if (i == idx || rxstat & DC_RXSTAT_LASTFRAG) 2396 break; 2397 dc_newbuf(sc, i, m); 2398 DC_INC(i, DC_RX_LIST_CNT); 2399 } 2400 2401 /* Find the length of the actual receive frame. */ 2402 total_len = DC_RXBYTES(rxstat); 2403 2404 /* Scan backwards until we hit a non-zero byte. */ 2405 while(*ptr == 0x00) 2406 ptr--; 2407 2408 /* Round off. */ 2409 if ((uintptr_t)(ptr) & 0x3) 2410 ptr -= 1; 2411 2412 /* Now find the start of the frame. */ 2413 ptr -= total_len; 2414 if (ptr < sc->dc_pnic_rx_buf) 2415 ptr = sc->dc_pnic_rx_buf; 2416 2417 /* 2418 * Now copy the salvaged frame to the last mbuf and fake up 2419 * the status word to make it look like a successful 2420 * frame reception. 2421 */ 2422 dc_newbuf(sc, i, m); 2423 bcopy(ptr, mtod(m, char *), total_len); 2424 cur_rx->dc_status = rxstat | DC_RXSTAT_FIRSTFRAG; 2425 2426 return; 2427 } 2428 2429 /* 2430 * This routine searches the RX ring for dirty descriptors in the 2431 * event that the rxeof routine falls out of sync with the chip's 2432 * current descriptor pointer. This may happen sometimes as a result 2433 * of a "no RX buffer available" condition that happens when the chip 2434 * consumes all of the RX buffers before the driver has a chance to 2435 * process the RX ring. This routine may need to be called more than 2436 * once to bring the driver back in sync with the chip, however we 2437 * should still be getting RX DONE interrupts to drive the search 2438 * for new packets in the RX ring, so we should catch up eventually. 2439 */ 2440 static int dc_rx_resync(sc) 2441 struct dc_softc *sc; 2442 { 2443 int i, pos; 2444 struct dc_desc *cur_rx; 2445 2446 pos = sc->dc_cdata.dc_rx_prod; 2447 2448 for (i = 0; i < DC_RX_LIST_CNT; i++) { 2449 cur_rx = &sc->dc_ldata->dc_rx_list[pos]; 2450 if (!(cur_rx->dc_status & DC_RXSTAT_OWN)) 2451 break; 2452 DC_INC(pos, DC_RX_LIST_CNT); 2453 } 2454 2455 /* If the ring really is empty, then just return. */ 2456 if (i == DC_RX_LIST_CNT) 2457 return(0); 2458 2459 /* We've fallen behing the chip: catch it. */ 2460 sc->dc_cdata.dc_rx_prod = pos; 2461 2462 return(EAGAIN); 2463 } 2464 2465 /* 2466 * A frame has been uploaded: pass the resulting mbuf chain up to 2467 * the higher level protocols. 2468 */ 2469 static void dc_rxeof(sc) 2470 struct dc_softc *sc; 2471 { 2472 struct ether_header *eh; 2473 struct mbuf *m; 2474 struct ifnet *ifp; 2475 struct dc_desc *cur_rx; 2476 int i, total_len = 0; 2477 u_int32_t rxstat; 2478 2479 ifp = &sc->arpcom.ac_if; 2480 i = sc->dc_cdata.dc_rx_prod; 2481 2482 while(!(sc->dc_ldata->dc_rx_list[i].dc_status & DC_RXSTAT_OWN)) { 2483 struct mbuf *m0 = NULL; 2484 2485 cur_rx = &sc->dc_ldata->dc_rx_list[i]; 2486 rxstat = cur_rx->dc_status; 2487 m = sc->dc_cdata.dc_rx_chain[i]; 2488 total_len = DC_RXBYTES(rxstat); 2489 2490 if (sc->dc_flags & DC_PNIC_RX_BUG_WAR) { 2491 if ((rxstat & DC_WHOLEFRAME) != DC_WHOLEFRAME) { 2492 if (rxstat & DC_RXSTAT_FIRSTFRAG) 2493 sc->dc_pnic_rx_bug_save = i; 2494 if ((rxstat & DC_RXSTAT_LASTFRAG) == 0) { 2495 DC_INC(i, DC_RX_LIST_CNT); 2496 continue; 2497 } 2498 dc_pnic_rx_bug_war(sc, i); 2499 rxstat = cur_rx->dc_status; 2500 total_len = DC_RXBYTES(rxstat); 2501 } 2502 } 2503 2504 sc->dc_cdata.dc_rx_chain[i] = NULL; 2505 2506 /* 2507 * If an error occurs, update stats, clear the 2508 * status word and leave the mbuf cluster in place: 2509 * it should simply get re-used next time this descriptor 2510 * comes up in the ring. 2511 */ 2512 if (rxstat & DC_RXSTAT_RXERR) { 2513 ifp->if_ierrors++; 2514 if (rxstat & DC_RXSTAT_COLLSEEN) 2515 ifp->if_collisions++; 2516 dc_newbuf(sc, i, m); 2517 if (rxstat & DC_RXSTAT_CRCERR) { 2518 DC_INC(i, DC_RX_LIST_CNT); 2519 continue; 2520 } else { 2521 dc_init(sc); 2522 return; 2523 } 2524 } 2525 2526 /* No errors; receive the packet. */ 2527 total_len -= ETHER_CRC_LEN; 2528 2529 m0 = m_devget(mtod(m, char *), total_len, ETHER_ALIGN, ifp, 2530 NULL); 2531 dc_newbuf(sc, i, m); 2532 DC_INC(i, DC_RX_LIST_CNT); 2533 if (m0 == NULL) { 2534 ifp->if_ierrors++; 2535 continue; 2536 } 2537 m = m0; 2538 2539 ifp->if_ipackets++; 2540 eh = mtod(m, struct ether_header *); 2541 2542 /* Remove header from mbuf and pass it on. */ 2543 m_adj(m, sizeof(struct ether_header)); 2544 ether_input(ifp, eh, m); 2545 } 2546 2547 sc->dc_cdata.dc_rx_prod = i; 2548 } 2549 2550 /* 2551 * A frame was downloaded to the chip. It's safe for us to clean up 2552 * the list buffers. 2553 */ 2554 2555 static void dc_txeof(sc) 2556 struct dc_softc *sc; 2557 { 2558 struct dc_desc *cur_tx = NULL; 2559 struct ifnet *ifp; 2560 int idx; 2561 2562 ifp = &sc->arpcom.ac_if; 2563 2564 /* Clear the timeout timer. */ 2565 ifp->if_timer = 0; 2566 2567 /* 2568 * Go through our tx list and free mbufs for those 2569 * frames that have been transmitted. 2570 */ 2571 idx = sc->dc_cdata.dc_tx_cons; 2572 while(idx != sc->dc_cdata.dc_tx_prod) { 2573 u_int32_t txstat; 2574 2575 cur_tx = &sc->dc_ldata->dc_tx_list[idx]; 2576 txstat = cur_tx->dc_status; 2577 2578 if (txstat & DC_TXSTAT_OWN) 2579 break; 2580 2581 if (!(cur_tx->dc_ctl & DC_TXCTL_LASTFRAG) || 2582 cur_tx->dc_ctl & DC_TXCTL_SETUP) { 2583 sc->dc_cdata.dc_tx_cnt--; 2584 if (cur_tx->dc_ctl & DC_TXCTL_SETUP) { 2585 /* 2586 * Yes, the PNIC is so brain damaged 2587 * that it will sometimes generate a TX 2588 * underrun error while DMAing the RX 2589 * filter setup frame. If we detect this, 2590 * we have to send the setup frame again, 2591 * or else the filter won't be programmed 2592 * correctly. 2593 */ 2594 if (DC_IS_PNIC(sc)) { 2595 if (txstat & DC_TXSTAT_ERRSUM) 2596 dc_setfilt(sc); 2597 } 2598 sc->dc_cdata.dc_tx_chain[idx] = NULL; 2599 } 2600 DC_INC(idx, DC_TX_LIST_CNT); 2601 continue; 2602 } 2603 2604 if (DC_IS_XIRCOM(sc)) { 2605 /* 2606 * XXX: Why does my Xircom taunt me so? 2607 * For some reason it likes setting the CARRLOST flag 2608 * even when the carrier is there. wtf?!? */ 2609 if (/*sc->dc_type == DC_TYPE_21143 &&*/ 2610 sc->dc_pmode == DC_PMODE_MII && 2611 ((txstat & 0xFFFF) & ~(DC_TXSTAT_ERRSUM| 2612 DC_TXSTAT_NOCARRIER))) 2613 txstat &= ~DC_TXSTAT_ERRSUM; 2614 } else { 2615 if (/*sc->dc_type == DC_TYPE_21143 &&*/ 2616 sc->dc_pmode == DC_PMODE_MII && 2617 ((txstat & 0xFFFF) & ~(DC_TXSTAT_ERRSUM| 2618 DC_TXSTAT_NOCARRIER|DC_TXSTAT_CARRLOST))) 2619 txstat &= ~DC_TXSTAT_ERRSUM; 2620 } 2621 2622 if (txstat & DC_TXSTAT_ERRSUM) { 2623 ifp->if_oerrors++; 2624 if (txstat & DC_TXSTAT_EXCESSCOLL) 2625 ifp->if_collisions++; 2626 if (txstat & DC_TXSTAT_LATECOLL) 2627 ifp->if_collisions++; 2628 if (!(txstat & DC_TXSTAT_UNDERRUN)) { 2629 dc_init(sc); 2630 return; 2631 } 2632 } 2633 2634 ifp->if_collisions += (txstat & DC_TXSTAT_COLLCNT) >> 3; 2635 2636 ifp->if_opackets++; 2637 if (sc->dc_cdata.dc_tx_chain[idx] != NULL) { 2638 m_freem(sc->dc_cdata.dc_tx_chain[idx]); 2639 sc->dc_cdata.dc_tx_chain[idx] = NULL; 2640 } 2641 2642 sc->dc_cdata.dc_tx_cnt--; 2643 DC_INC(idx, DC_TX_LIST_CNT); 2644 } 2645 2646 sc->dc_cdata.dc_tx_cons = idx; 2647 if (cur_tx != NULL) 2648 ifp->if_flags &= ~IFF_OACTIVE; 2649 2650 return; 2651 } 2652 2653 static void dc_tick(xsc) 2654 void *xsc; 2655 { 2656 struct dc_softc *sc; 2657 struct mii_data *mii; 2658 struct ifnet *ifp; 2659 u_int32_t r; 2660 2661 sc = xsc; 2662 DC_LOCK(sc); 2663 ifp = &sc->arpcom.ac_if; 2664 mii = device_get_softc(sc->dc_miibus); 2665 2666 if (sc->dc_flags & DC_REDUCED_MII_POLL) { 2667 if (sc->dc_flags & DC_21143_NWAY) { 2668 r = CSR_READ_4(sc, DC_10BTSTAT); 2669 if (IFM_SUBTYPE(mii->mii_media_active) == 2670 IFM_100_TX && (r & DC_TSTAT_LS100)) { 2671 sc->dc_link = 0; 2672 mii_mediachg(mii); 2673 } 2674 if (IFM_SUBTYPE(mii->mii_media_active) == 2675 IFM_10_T && (r & DC_TSTAT_LS10)) { 2676 sc->dc_link = 0; 2677 mii_mediachg(mii); 2678 } 2679 if (sc->dc_link == 0) 2680 mii_tick(mii); 2681 } else { 2682 r = CSR_READ_4(sc, DC_ISR); 2683 if ((r & DC_ISR_RX_STATE) == DC_RXSTATE_WAIT && 2684 sc->dc_cdata.dc_tx_cnt == 0) 2685 mii_tick(mii); 2686 if (!(mii->mii_media_status & IFM_ACTIVE)) 2687 sc->dc_link = 0; 2688 } 2689 } else 2690 mii_tick(mii); 2691 2692 /* 2693 * When the init routine completes, we expect to be able to send 2694 * packets right away, and in fact the network code will send a 2695 * gratuitous ARP the moment the init routine marks the interface 2696 * as running. However, even though the MAC may have been initialized, 2697 * there may be a delay of a few seconds before the PHY completes 2698 * autonegotiation and the link is brought up. Any transmissions 2699 * made during that delay will be lost. Dealing with this is tricky: 2700 * we can't just pause in the init routine while waiting for the 2701 * PHY to come ready since that would bring the whole system to 2702 * a screeching halt for several seconds. 2703 * 2704 * What we do here is prevent the TX start routine from sending 2705 * any packets until a link has been established. After the 2706 * interface has been initialized, the tick routine will poll 2707 * the state of the PHY until the IFM_ACTIVE flag is set. Until 2708 * that time, packets will stay in the send queue, and once the 2709 * link comes up, they will be flushed out to the wire. 2710 */ 2711 if (!sc->dc_link) { 2712 mii_pollstat(mii); 2713 if (mii->mii_media_status & IFM_ACTIVE && 2714 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) { 2715 sc->dc_link++; 2716 if (ifp->if_snd.ifq_head != NULL) 2717 dc_start(ifp); 2718 } 2719 } 2720 2721 if (sc->dc_flags & DC_21143_NWAY && !sc->dc_link) 2722 callout_reset(&sc->dc_stat_ch, hz/10, dc_tick, sc); 2723 else 2724 callout_reset(&sc->dc_stat_ch, hz, dc_tick, sc); 2725 2726 DC_UNLOCK(sc); 2727 2728 return; 2729 } 2730 2731 /* 2732 * A transmit underrun has occurred. Back off the transmit threshold, 2733 * or switch to store and forward mode if we have to. 2734 */ 2735 static void dc_tx_underrun(sc) 2736 struct dc_softc *sc; 2737 { 2738 u_int32_t isr; 2739 int i; 2740 2741 if (DC_IS_DAVICOM(sc)) 2742 dc_init(sc); 2743 2744 if (DC_IS_INTEL(sc)) { 2745 /* 2746 * The real 21143 requires that the transmitter be idle 2747 * in order to change the transmit threshold or store 2748 * and forward state. 2749 */ 2750 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_TX_ON); 2751 2752 for (i = 0; i < DC_TIMEOUT; i++) { 2753 isr = CSR_READ_4(sc, DC_ISR); 2754 if (isr & DC_ISR_TX_IDLE) 2755 break; 2756 DELAY(10); 2757 } 2758 if (i == DC_TIMEOUT) { 2759 printf("dc%d: failed to force tx to idle state\n", 2760 sc->dc_unit); 2761 dc_init(sc); 2762 } 2763 } 2764 2765 printf("dc%d: TX underrun -- ", sc->dc_unit); 2766 sc->dc_txthresh += DC_TXTHRESH_INC; 2767 if (sc->dc_txthresh > DC_TXTHRESH_MAX) { 2768 printf("using store and forward mode\n"); 2769 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_STORENFWD); 2770 } else { 2771 printf("increasing TX threshold\n"); 2772 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_TX_THRESH); 2773 DC_SETBIT(sc, DC_NETCFG, sc->dc_txthresh); 2774 } 2775 2776 if (DC_IS_INTEL(sc)) 2777 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_TX_ON); 2778 2779 return; 2780 } 2781 2782 static void dc_intr(arg) 2783 void *arg; 2784 { 2785 struct dc_softc *sc; 2786 struct ifnet *ifp; 2787 u_int32_t status; 2788 2789 sc = arg; 2790 2791 if ( (CSR_READ_4(sc, DC_ISR) & DC_INTRS) == 0) 2792 return ; 2793 2794 DC_LOCK(sc); 2795 ifp = &sc->arpcom.ac_if; 2796 2797 /* Suppress unwanted interrupts */ 2798 if (!(ifp->if_flags & IFF_UP)) { 2799 if (CSR_READ_4(sc, DC_ISR) & DC_INTRS) 2800 dc_stop(sc); 2801 DC_UNLOCK(sc); 2802 return; 2803 } 2804 2805 /* Disable interrupts. */ 2806 CSR_WRITE_4(sc, DC_IMR, 0x00000000); 2807 2808 while(((status = CSR_READ_4(sc, DC_ISR)) & DC_INTRS) 2809 && status != 0xFFFFFFFF) { 2810 2811 CSR_WRITE_4(sc, DC_ISR, status); 2812 2813 if (status & DC_ISR_RX_OK) { 2814 int curpkts; 2815 curpkts = ifp->if_ipackets; 2816 dc_rxeof(sc); 2817 if (curpkts == ifp->if_ipackets) { 2818 while(dc_rx_resync(sc)) 2819 dc_rxeof(sc); 2820 } 2821 } 2822 2823 if (status & (DC_ISR_TX_OK|DC_ISR_TX_NOBUF)) 2824 dc_txeof(sc); 2825 2826 if (status & DC_ISR_TX_IDLE) { 2827 dc_txeof(sc); 2828 if (sc->dc_cdata.dc_tx_cnt) { 2829 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_TX_ON); 2830 CSR_WRITE_4(sc, DC_TXSTART, 0xFFFFFFFF); 2831 } 2832 } 2833 2834 if (status & DC_ISR_TX_UNDERRUN) 2835 dc_tx_underrun(sc); 2836 2837 if ((status & DC_ISR_RX_WATDOGTIMEO) 2838 || (status & DC_ISR_RX_NOBUF)) { 2839 int curpkts; 2840 curpkts = ifp->if_ipackets; 2841 dc_rxeof(sc); 2842 if (curpkts == ifp->if_ipackets) { 2843 while(dc_rx_resync(sc)) 2844 dc_rxeof(sc); 2845 } 2846 } 2847 2848 if (status & DC_ISR_BUS_ERR) { 2849 dc_reset(sc); 2850 dc_init(sc); 2851 } 2852 } 2853 2854 /* Re-enable interrupts. */ 2855 CSR_WRITE_4(sc, DC_IMR, DC_INTRS); 2856 2857 if (ifp->if_snd.ifq_head != NULL) 2858 dc_start(ifp); 2859 2860 DC_UNLOCK(sc); 2861 2862 return; 2863 } 2864 2865 /* 2866 * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data 2867 * pointers to the fragment pointers. 2868 */ 2869 static int dc_encap(sc, m_head, txidx) 2870 struct dc_softc *sc; 2871 struct mbuf *m_head; 2872 u_int32_t *txidx; 2873 { 2874 struct dc_desc *f = NULL; 2875 struct mbuf *m; 2876 int frag, cur, cnt = 0; 2877 2878 /* 2879 * Start packing the mbufs in this chain into 2880 * the fragment pointers. Stop when we run out 2881 * of fragments or hit the end of the mbuf chain. 2882 */ 2883 m = m_head; 2884 cur = frag = *txidx; 2885 2886 for (m = m_head; m != NULL; m = m->m_next) { 2887 if (m->m_len != 0) { 2888 if (sc->dc_flags & DC_TX_ADMTEK_WAR) { 2889 if (*txidx != sc->dc_cdata.dc_tx_prod && 2890 frag == (DC_TX_LIST_CNT - 1)) 2891 return(ENOBUFS); 2892 } 2893 if ((DC_TX_LIST_CNT - 2894 (sc->dc_cdata.dc_tx_cnt + cnt)) < 5) 2895 return(ENOBUFS); 2896 2897 f = &sc->dc_ldata->dc_tx_list[frag]; 2898 f->dc_ctl = DC_TXCTL_TLINK | m->m_len; 2899 if (cnt == 0) { 2900 f->dc_status = 0; 2901 f->dc_ctl |= DC_TXCTL_FIRSTFRAG; 2902 } else 2903 f->dc_status = DC_TXSTAT_OWN; 2904 f->dc_data = vtophys(mtod(m, vm_offset_t)); 2905 cur = frag; 2906 DC_INC(frag, DC_TX_LIST_CNT); 2907 cnt++; 2908 } 2909 } 2910 2911 if (m != NULL) 2912 return(ENOBUFS); 2913 2914 sc->dc_cdata.dc_tx_cnt += cnt; 2915 sc->dc_cdata.dc_tx_chain[cur] = m_head; 2916 sc->dc_ldata->dc_tx_list[cur].dc_ctl |= DC_TXCTL_LASTFRAG; 2917 if (sc->dc_flags & DC_TX_INTR_FIRSTFRAG) 2918 sc->dc_ldata->dc_tx_list[*txidx].dc_ctl |= DC_TXCTL_FINT; 2919 if (sc->dc_flags & DC_TX_INTR_ALWAYS) 2920 sc->dc_ldata->dc_tx_list[cur].dc_ctl |= DC_TXCTL_FINT; 2921 if (sc->dc_flags & DC_TX_USE_TX_INTR && sc->dc_cdata.dc_tx_cnt > 64) 2922 sc->dc_ldata->dc_tx_list[cur].dc_ctl |= DC_TXCTL_FINT; 2923 sc->dc_ldata->dc_tx_list[*txidx].dc_status = DC_TXSTAT_OWN; 2924 *txidx = frag; 2925 2926 return(0); 2927 } 2928 2929 /* 2930 * Coalesce an mbuf chain into a single mbuf cluster buffer. 2931 * Needed for some really badly behaved chips that just can't 2932 * do scatter/gather correctly. 2933 */ 2934 static int dc_coal(sc, m_head) 2935 struct dc_softc *sc; 2936 struct mbuf **m_head; 2937 { 2938 struct mbuf *m_new, *m; 2939 2940 m = *m_head; 2941 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 2942 if (m_new == NULL) { 2943 printf("dc%d: no memory for tx list", sc->dc_unit); 2944 return(ENOBUFS); 2945 } 2946 if (m->m_pkthdr.len > MHLEN) { 2947 MCLGET(m_new, M_DONTWAIT); 2948 if (!(m_new->m_flags & M_EXT)) { 2949 m_freem(m_new); 2950 printf("dc%d: no memory for tx list", sc->dc_unit); 2951 return(ENOBUFS); 2952 } 2953 } 2954 m_copydata(m, 0, m->m_pkthdr.len, mtod(m_new, caddr_t)); 2955 m_new->m_pkthdr.len = m_new->m_len = m->m_pkthdr.len; 2956 m_freem(m); 2957 *m_head = m_new; 2958 2959 return(0); 2960 } 2961 2962 /* 2963 * Main transmit routine. To avoid having to do mbuf copies, we put pointers 2964 * to the mbuf data regions directly in the transmit lists. We also save a 2965 * copy of the pointers since the transmit list fragment pointers are 2966 * physical addresses. 2967 */ 2968 2969 static void dc_start(ifp) 2970 struct ifnet *ifp; 2971 { 2972 struct dc_softc *sc; 2973 struct mbuf *m_head = NULL; 2974 int idx; 2975 2976 sc = ifp->if_softc; 2977 2978 DC_LOCK(sc); 2979 2980 if (!sc->dc_link && ifp->if_snd.ifq_len < 10) { 2981 DC_UNLOCK(sc); 2982 return; 2983 } 2984 2985 if (ifp->if_flags & IFF_OACTIVE) { 2986 DC_UNLOCK(sc); 2987 return; 2988 } 2989 2990 idx = sc->dc_cdata.dc_tx_prod; 2991 2992 while(sc->dc_cdata.dc_tx_chain[idx] == NULL) { 2993 IF_DEQUEUE(&ifp->if_snd, m_head); 2994 if (m_head == NULL) 2995 break; 2996 2997 if (sc->dc_flags & DC_TX_COALESCE) { 2998 if (dc_coal(sc, &m_head)) { 2999 IF_PREPEND(&ifp->if_snd, m_head); 3000 ifp->if_flags |= IFF_OACTIVE; 3001 break; 3002 } 3003 } 3004 3005 if (dc_encap(sc, m_head, &idx)) { 3006 IF_PREPEND(&ifp->if_snd, m_head); 3007 ifp->if_flags |= IFF_OACTIVE; 3008 break; 3009 } 3010 3011 /* 3012 * If there's a BPF listener, bounce a copy of this frame 3013 * to him. 3014 */ 3015 if (ifp->if_bpf) 3016 bpf_mtap(ifp, m_head); 3017 3018 if (sc->dc_flags & DC_TX_ONE) { 3019 ifp->if_flags |= IFF_OACTIVE; 3020 break; 3021 } 3022 } 3023 3024 /* Transmit */ 3025 sc->dc_cdata.dc_tx_prod = idx; 3026 if (!(sc->dc_flags & DC_TX_POLL)) 3027 CSR_WRITE_4(sc, DC_TXSTART, 0xFFFFFFFF); 3028 3029 /* 3030 * Set a timeout in case the chip goes out to lunch. 3031 */ 3032 ifp->if_timer = 5; 3033 3034 DC_UNLOCK(sc); 3035 3036 return; 3037 } 3038 3039 static void dc_init(xsc) 3040 void *xsc; 3041 { 3042 struct dc_softc *sc = xsc; 3043 struct ifnet *ifp = &sc->arpcom.ac_if; 3044 struct mii_data *mii; 3045 3046 DC_LOCK(sc); 3047 3048 mii = device_get_softc(sc->dc_miibus); 3049 3050 /* 3051 * Cancel pending I/O and free all RX/TX buffers. 3052 */ 3053 dc_stop(sc); 3054 dc_reset(sc); 3055 3056 /* 3057 * Set cache alignment and burst length. 3058 */ 3059 if (DC_IS_ASIX(sc) || DC_IS_DAVICOM(sc)) 3060 CSR_WRITE_4(sc, DC_BUSCTL, 0); 3061 else 3062 CSR_WRITE_4(sc, DC_BUSCTL, DC_BUSCTL_MRME|DC_BUSCTL_MRLE); 3063 if (DC_IS_DAVICOM(sc) || DC_IS_INTEL(sc)) { 3064 DC_SETBIT(sc, DC_BUSCTL, DC_BURSTLEN_USECA); 3065 } else { 3066 DC_SETBIT(sc, DC_BUSCTL, DC_BURSTLEN_16LONG); 3067 } 3068 if (sc->dc_flags & DC_TX_POLL) 3069 DC_SETBIT(sc, DC_BUSCTL, DC_TXPOLL_1); 3070 switch(sc->dc_cachesize) { 3071 case 32: 3072 DC_SETBIT(sc, DC_BUSCTL, DC_CACHEALIGN_32LONG); 3073 break; 3074 case 16: 3075 DC_SETBIT(sc, DC_BUSCTL, DC_CACHEALIGN_16LONG); 3076 break; 3077 case 8: 3078 DC_SETBIT(sc, DC_BUSCTL, DC_CACHEALIGN_8LONG); 3079 break; 3080 case 0: 3081 default: 3082 DC_SETBIT(sc, DC_BUSCTL, DC_CACHEALIGN_NONE); 3083 break; 3084 } 3085 3086 if (sc->dc_flags & DC_TX_STORENFWD) 3087 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_STORENFWD); 3088 else { 3089 if (sc->dc_txthresh > DC_TXTHRESH_MAX) { 3090 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_STORENFWD); 3091 } else { 3092 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_STORENFWD); 3093 DC_SETBIT(sc, DC_NETCFG, sc->dc_txthresh); 3094 } 3095 } 3096 3097 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_NO_RXCRC); 3098 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_TX_BACKOFF); 3099 3100 if (DC_IS_MACRONIX(sc) || DC_IS_PNICII(sc)) { 3101 /* 3102 * The app notes for the 98713 and 98715A say that 3103 * in order to have the chips operate properly, a magic 3104 * number must be written to CSR16. Macronix does not 3105 * document the meaning of these bits so there's no way 3106 * to know exactly what they do. The 98713 has a magic 3107 * number all its own; the rest all use a different one. 3108 */ 3109 DC_CLRBIT(sc, DC_MX_MAGICPACKET, 0xFFFF0000); 3110 if (sc->dc_type == DC_TYPE_98713) 3111 DC_SETBIT(sc, DC_MX_MAGICPACKET, DC_MX_MAGIC_98713); 3112 else 3113 DC_SETBIT(sc, DC_MX_MAGICPACKET, DC_MX_MAGIC_98715); 3114 } 3115 3116 if (DC_IS_XIRCOM(sc)) { 3117 /* 3118 * setup General Purpose Port mode and data so the tulip 3119 * can talk to the MII. 3120 */ 3121 CSR_WRITE_4(sc, DC_SIAGP, DC_SIAGP_WRITE_EN | DC_SIAGP_INT1_EN | 3122 DC_SIAGP_MD_GP2_OUTPUT | DC_SIAGP_MD_GP0_OUTPUT); 3123 DELAY(10); 3124 CSR_WRITE_4(sc, DC_SIAGP, DC_SIAGP_INT1_EN | 3125 DC_SIAGP_MD_GP2_OUTPUT | DC_SIAGP_MD_GP0_OUTPUT); 3126 DELAY(10); 3127 } 3128 3129 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_TX_THRESH); 3130 DC_SETBIT(sc, DC_NETCFG, DC_TXTHRESH_MIN); 3131 3132 /* Init circular RX list. */ 3133 if (dc_list_rx_init(sc) == ENOBUFS) { 3134 printf("dc%d: initialization failed: no " 3135 "memory for rx buffers\n", sc->dc_unit); 3136 dc_stop(sc); 3137 DC_UNLOCK(sc); 3138 return; 3139 } 3140 3141 /* 3142 * Init tx descriptors. 3143 */ 3144 dc_list_tx_init(sc); 3145 3146 /* 3147 * Load the address of the RX list. 3148 */ 3149 CSR_WRITE_4(sc, DC_RXADDR, vtophys(&sc->dc_ldata->dc_rx_list[0])); 3150 CSR_WRITE_4(sc, DC_TXADDR, vtophys(&sc->dc_ldata->dc_tx_list[0])); 3151 3152 /* 3153 * Enable interrupts. 3154 */ 3155 CSR_WRITE_4(sc, DC_IMR, DC_INTRS); 3156 CSR_WRITE_4(sc, DC_ISR, 0xFFFFFFFF); 3157 3158 /* Enable transmitter. */ 3159 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_TX_ON); 3160 3161 /* 3162 * If this is an Intel 21143 and we're not using the 3163 * MII port, program the LED control pins so we get 3164 * link and activity indications. 3165 */ 3166 if (sc->dc_flags & DC_TULIP_LEDS) { 3167 CSR_WRITE_4(sc, DC_WATCHDOG, 3168 DC_WDOG_CTLWREN|DC_WDOG_LINK|DC_WDOG_ACTIVITY); 3169 CSR_WRITE_4(sc, DC_WATCHDOG, 0); 3170 } 3171 3172 /* 3173 * Load the RX/multicast filter. We do this sort of late 3174 * because the filter programming scheme on the 21143 and 3175 * some clones requires DMAing a setup frame via the TX 3176 * engine, and we need the transmitter enabled for that. 3177 */ 3178 dc_setfilt(sc); 3179 3180 /* Enable receiver. */ 3181 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_ON); 3182 CSR_WRITE_4(sc, DC_RXSTART, 0xFFFFFFFF); 3183 3184 mii_mediachg(mii); 3185 dc_setcfg(sc, sc->dc_if_media); 3186 3187 ifp->if_flags |= IFF_RUNNING; 3188 ifp->if_flags &= ~IFF_OACTIVE; 3189 3190 /* Don't start the ticker if this is a homePNA link. */ 3191 if (IFM_SUBTYPE(mii->mii_media.ifm_media) == IFM_homePNA) 3192 sc->dc_link = 1; 3193 else { 3194 if (sc->dc_flags & DC_21143_NWAY) 3195 callout_reset(&sc->dc_stat_ch, hz/10, dc_tick, sc); 3196 else 3197 callout_reset(&sc->dc_stat_ch, hz, dc_tick, sc); 3198 } 3199 3200 #ifdef SRM_MEDIA 3201 if(sc->dc_srm_media) { 3202 struct ifreq ifr; 3203 3204 ifr.ifr_media = sc->dc_srm_media; 3205 ifmedia_ioctl(ifp, &ifr, &mii->mii_media, SIOCSIFMEDIA); 3206 sc->dc_srm_media = 0; 3207 } 3208 #endif 3209 DC_UNLOCK(sc); 3210 return; 3211 } 3212 3213 /* 3214 * Set media options. 3215 */ 3216 static int dc_ifmedia_upd(ifp) 3217 struct ifnet *ifp; 3218 { 3219 struct dc_softc *sc; 3220 struct mii_data *mii; 3221 struct ifmedia *ifm; 3222 3223 sc = ifp->if_softc; 3224 mii = device_get_softc(sc->dc_miibus); 3225 mii_mediachg(mii); 3226 ifm = &mii->mii_media; 3227 3228 if (DC_IS_DAVICOM(sc) && 3229 IFM_SUBTYPE(ifm->ifm_media) == IFM_homePNA) 3230 dc_setcfg(sc, ifm->ifm_media); 3231 else 3232 sc->dc_link = 0; 3233 3234 return(0); 3235 } 3236 3237 /* 3238 * Report current media status. 3239 */ 3240 static void dc_ifmedia_sts(ifp, ifmr) 3241 struct ifnet *ifp; 3242 struct ifmediareq *ifmr; 3243 { 3244 struct dc_softc *sc; 3245 struct mii_data *mii; 3246 struct ifmedia *ifm; 3247 3248 sc = ifp->if_softc; 3249 mii = device_get_softc(sc->dc_miibus); 3250 mii_pollstat(mii); 3251 ifm = &mii->mii_media; 3252 if (DC_IS_DAVICOM(sc)) { 3253 if (IFM_SUBTYPE(ifm->ifm_media) == IFM_homePNA) { 3254 ifmr->ifm_active = ifm->ifm_media; 3255 ifmr->ifm_status = 0; 3256 return; 3257 } 3258 } 3259 ifmr->ifm_active = mii->mii_media_active; 3260 ifmr->ifm_status = mii->mii_media_status; 3261 3262 return; 3263 } 3264 3265 static int dc_ioctl(ifp, command, data) 3266 struct ifnet *ifp; 3267 u_long command; 3268 caddr_t data; 3269 { 3270 struct dc_softc *sc = ifp->if_softc; 3271 struct ifreq *ifr = (struct ifreq *) data; 3272 struct mii_data *mii; 3273 int error = 0; 3274 3275 DC_LOCK(sc); 3276 3277 switch(command) { 3278 case SIOCSIFADDR: 3279 case SIOCGIFADDR: 3280 case SIOCSIFMTU: 3281 error = ether_ioctl(ifp, command, data); 3282 break; 3283 case SIOCSIFFLAGS: 3284 if (ifp->if_flags & IFF_UP) { 3285 if (ifp->if_flags & IFF_RUNNING && 3286 ifp->if_flags & IFF_PROMISC && 3287 !(sc->dc_if_flags & IFF_PROMISC)) { 3288 dc_setfilt(sc); 3289 } else if (ifp->if_flags & IFF_RUNNING && 3290 !(ifp->if_flags & IFF_PROMISC) && 3291 sc->dc_if_flags & IFF_PROMISC) { 3292 dc_setfilt(sc); 3293 } else if (!(ifp->if_flags & IFF_RUNNING)) { 3294 sc->dc_txthresh = 0; 3295 dc_init(sc); 3296 } 3297 } else { 3298 if (ifp->if_flags & IFF_RUNNING) 3299 dc_stop(sc); 3300 } 3301 sc->dc_if_flags = ifp->if_flags; 3302 error = 0; 3303 break; 3304 case SIOCADDMULTI: 3305 case SIOCDELMULTI: 3306 dc_setfilt(sc); 3307 error = 0; 3308 break; 3309 case SIOCGIFMEDIA: 3310 case SIOCSIFMEDIA: 3311 mii = device_get_softc(sc->dc_miibus); 3312 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 3313 #ifdef SRM_MEDIA 3314 if (sc->dc_srm_media) 3315 sc->dc_srm_media = 0; 3316 #endif 3317 break; 3318 default: 3319 error = EINVAL; 3320 break; 3321 } 3322 3323 DC_UNLOCK(sc); 3324 3325 return(error); 3326 } 3327 3328 static void dc_watchdog(ifp) 3329 struct ifnet *ifp; 3330 { 3331 struct dc_softc *sc; 3332 3333 sc = ifp->if_softc; 3334 3335 DC_LOCK(sc); 3336 3337 ifp->if_oerrors++; 3338 printf("dc%d: watchdog timeout\n", sc->dc_unit); 3339 3340 dc_stop(sc); 3341 dc_reset(sc); 3342 dc_init(sc); 3343 3344 if (ifp->if_snd.ifq_head != NULL) 3345 dc_start(ifp); 3346 3347 DC_UNLOCK(sc); 3348 3349 return; 3350 } 3351 3352 /* 3353 * Stop the adapter and free any mbufs allocated to the 3354 * RX and TX lists. 3355 */ 3356 static void dc_stop(sc) 3357 struct dc_softc *sc; 3358 { 3359 register int i; 3360 struct ifnet *ifp; 3361 3362 DC_LOCK(sc); 3363 3364 ifp = &sc->arpcom.ac_if; 3365 ifp->if_timer = 0; 3366 3367 callout_stop(&sc->dc_stat_ch); 3368 3369 DC_CLRBIT(sc, DC_NETCFG, (DC_NETCFG_RX_ON|DC_NETCFG_TX_ON)); 3370 CSR_WRITE_4(sc, DC_IMR, 0x00000000); 3371 CSR_WRITE_4(sc, DC_TXADDR, 0x00000000); 3372 CSR_WRITE_4(sc, DC_RXADDR, 0x00000000); 3373 sc->dc_link = 0; 3374 3375 /* 3376 * Free data in the RX lists. 3377 */ 3378 for (i = 0; i < DC_RX_LIST_CNT; i++) { 3379 if (sc->dc_cdata.dc_rx_chain[i] != NULL) { 3380 m_freem(sc->dc_cdata.dc_rx_chain[i]); 3381 sc->dc_cdata.dc_rx_chain[i] = NULL; 3382 } 3383 } 3384 bzero((char *)&sc->dc_ldata->dc_rx_list, 3385 sizeof(sc->dc_ldata->dc_rx_list)); 3386 3387 /* 3388 * Free the TX list buffers. 3389 */ 3390 for (i = 0; i < DC_TX_LIST_CNT; i++) { 3391 if (sc->dc_cdata.dc_tx_chain[i] != NULL) { 3392 if (sc->dc_ldata->dc_tx_list[i].dc_ctl & 3393 DC_TXCTL_SETUP) { 3394 sc->dc_cdata.dc_tx_chain[i] = NULL; 3395 continue; 3396 } 3397 m_freem(sc->dc_cdata.dc_tx_chain[i]); 3398 sc->dc_cdata.dc_tx_chain[i] = NULL; 3399 } 3400 } 3401 3402 bzero((char *)&sc->dc_ldata->dc_tx_list, 3403 sizeof(sc->dc_ldata->dc_tx_list)); 3404 3405 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 3406 3407 DC_UNLOCK(sc); 3408 3409 return; 3410 } 3411 3412 /* 3413 * Stop all chip I/O so that the kernel's probe routines don't 3414 * get confused by errant DMAs when rebooting. 3415 */ 3416 static void dc_shutdown(dev) 3417 device_t dev; 3418 { 3419 struct dc_softc *sc; 3420 3421 sc = device_get_softc(dev); 3422 3423 dc_stop(sc); 3424 3425 return; 3426 } 3427