1 /*- 2 * Copyright (c) 1997, 1998, 1999 3 * Bill Paul <wpaul@ee.columbia.edu>. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 3. All advertising materials mentioning features or use of this software 14 * must display the following acknowledgement: 15 * This product includes software developed by Bill Paul. 16 * 4. Neither the name of the author nor the names of any co-contributors 17 * may be used to endorse or promote products derived from this software 18 * without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30 * THE POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33 #include <sys/cdefs.h> 34 __FBSDID("$FreeBSD$"); 35 36 /* 37 * DEC "tulip" clone ethernet driver. Supports the DEC/Intel 21143 38 * series chips and several workalikes including the following: 39 * 40 * Macronix 98713/98715/98725/98727/98732 PMAC (www.macronix.com) 41 * Macronix/Lite-On 82c115 PNIC II (www.macronix.com) 42 * Lite-On 82c168/82c169 PNIC (www.litecom.com) 43 * ASIX Electronics AX88140A (www.asix.com.tw) 44 * ASIX Electronics AX88141 (www.asix.com.tw) 45 * ADMtek AL981 (www.admtek.com.tw) 46 * ADMtek AN983 (www.admtek.com.tw) 47 * ADMtek CardBus AN985 (www.admtek.com.tw) 48 * Netgear FA511 (www.netgear.com) Appears to be rebadged ADMTek CardBus AN985 49 * Davicom DM9100, DM9102, DM9102A (www.davicom8.com) 50 * Accton EN1217 (www.accton.com) 51 * Xircom X3201 (www.xircom.com) 52 * Abocom FE2500 53 * Conexant LANfinity (www.conexant.com) 54 * 3Com OfficeConnect 10/100B 3CSOHO100B (www.3com.com) 55 * 56 * Datasheets for the 21143 are available at developer.intel.com. 57 * Datasheets for the clone parts can be found at their respective sites. 58 * (Except for the PNIC; see www.freebsd.org/~wpaul/PNIC/pnic.ps.gz.) 59 * The PNIC II is essentially a Macronix 98715A chip; the only difference 60 * worth noting is that its multicast hash table is only 128 bits wide 61 * instead of 512. 62 * 63 * Written by Bill Paul <wpaul@ee.columbia.edu> 64 * Electrical Engineering Department 65 * Columbia University, New York City 66 */ 67 /* 68 * The Intel 21143 is the successor to the DEC 21140. It is basically 69 * the same as the 21140 but with a few new features. The 21143 supports 70 * three kinds of media attachments: 71 * 72 * o MII port, for 10Mbps and 100Mbps support and NWAY 73 * autonegotiation provided by an external PHY. 74 * o SYM port, for symbol mode 100Mbps support. 75 * o 10baseT port. 76 * o AUI/BNC port. 77 * 78 * The 100Mbps SYM port and 10baseT port can be used together in 79 * combination with the internal NWAY support to create a 10/100 80 * autosensing configuration. 81 * 82 * Note that not all tulip workalikes are handled in this driver: we only 83 * deal with those which are relatively well behaved. The Winbond is 84 * handled separately due to its different register offsets and the 85 * special handling needed for its various bugs. The PNIC is handled 86 * here, but I'm not thrilled about it. 87 * 88 * All of the workalike chips use some form of MII transceiver support 89 * with the exception of the Macronix chips, which also have a SYM port. 90 * The ASIX AX88140A is also documented to have a SYM port, but all 91 * the cards I've seen use an MII transceiver, probably because the 92 * AX88140A doesn't support internal NWAY. 93 */ 94 95 #ifdef HAVE_KERNEL_OPTION_HEADERS 96 #include "opt_device_polling.h" 97 #endif 98 99 #include <sys/param.h> 100 #include <sys/endian.h> 101 #include <sys/systm.h> 102 #include <sys/sockio.h> 103 #include <sys/mbuf.h> 104 #include <sys/malloc.h> 105 #include <sys/kernel.h> 106 #include <sys/module.h> 107 #include <sys/socket.h> 108 109 #include <net/if.h> 110 #include <net/if_arp.h> 111 #include <net/ethernet.h> 112 #include <net/if_dl.h> 113 #include <net/if_media.h> 114 #include <net/if_types.h> 115 #include <net/if_vlan_var.h> 116 117 #include <net/bpf.h> 118 119 #include <machine/bus.h> 120 #include <machine/resource.h> 121 #include <sys/bus.h> 122 #include <sys/rman.h> 123 124 #include <dev/mii/mii.h> 125 #include <dev/mii/mii_bitbang.h> 126 #include <dev/mii/miivar.h> 127 128 #include <dev/pci/pcireg.h> 129 #include <dev/pci/pcivar.h> 130 131 #define DC_USEIOSPACE 132 133 #include <dev/dc/if_dcreg.h> 134 135 #ifdef __sparc64__ 136 #include <dev/ofw/openfirm.h> 137 #include <machine/ofw_machdep.h> 138 #endif 139 140 MODULE_DEPEND(dc, pci, 1, 1, 1); 141 MODULE_DEPEND(dc, ether, 1, 1, 1); 142 MODULE_DEPEND(dc, miibus, 1, 1, 1); 143 144 /* 145 * "device miibus" is required in kernel config. See GENERIC if you get 146 * errors here. 147 */ 148 #include "miibus_if.h" 149 150 /* 151 * Various supported device vendors/types and their names. 152 */ 153 static const struct dc_type const dc_devs[] = { 154 { DC_DEVID(DC_VENDORID_DEC, DC_DEVICEID_21143), 0, 155 "Intel 21143 10/100BaseTX" }, 156 { DC_DEVID(DC_VENDORID_DAVICOM, DC_DEVICEID_DM9009), 0, 157 "Davicom DM9009 10/100BaseTX" }, 158 { DC_DEVID(DC_VENDORID_DAVICOM, DC_DEVICEID_DM9100), 0, 159 "Davicom DM9100 10/100BaseTX" }, 160 { DC_DEVID(DC_VENDORID_DAVICOM, DC_DEVICEID_DM9102), DC_REVISION_DM9102A, 161 "Davicom DM9102A 10/100BaseTX" }, 162 { DC_DEVID(DC_VENDORID_DAVICOM, DC_DEVICEID_DM9102), 0, 163 "Davicom DM9102 10/100BaseTX" }, 164 { DC_DEVID(DC_VENDORID_ADMTEK, DC_DEVICEID_AL981), 0, 165 "ADMtek AL981 10/100BaseTX" }, 166 { DC_DEVID(DC_VENDORID_ADMTEK, DC_DEVICEID_AN983), 0, 167 "ADMtek AN983 10/100BaseTX" }, 168 { DC_DEVID(DC_VENDORID_ADMTEK, DC_DEVICEID_AN985), 0, 169 "ADMtek AN985 CardBus 10/100BaseTX or clone" }, 170 { DC_DEVID(DC_VENDORID_ADMTEK, DC_DEVICEID_ADM9511), 0, 171 "ADMtek ADM9511 10/100BaseTX" }, 172 { DC_DEVID(DC_VENDORID_ADMTEK, DC_DEVICEID_ADM9513), 0, 173 "ADMtek ADM9513 10/100BaseTX" }, 174 { DC_DEVID(DC_VENDORID_ASIX, DC_DEVICEID_AX88140A), DC_REVISION_88141, 175 "ASIX AX88141 10/100BaseTX" }, 176 { DC_DEVID(DC_VENDORID_ASIX, DC_DEVICEID_AX88140A), 0, 177 "ASIX AX88140A 10/100BaseTX" }, 178 { DC_DEVID(DC_VENDORID_MX, DC_DEVICEID_98713), DC_REVISION_98713A, 179 "Macronix 98713A 10/100BaseTX" }, 180 { DC_DEVID(DC_VENDORID_MX, DC_DEVICEID_98713), 0, 181 "Macronix 98713 10/100BaseTX" }, 182 { DC_DEVID(DC_VENDORID_CP, DC_DEVICEID_98713_CP), DC_REVISION_98713A, 183 "Compex RL100-TX 10/100BaseTX" }, 184 { DC_DEVID(DC_VENDORID_CP, DC_DEVICEID_98713_CP), 0, 185 "Compex RL100-TX 10/100BaseTX" }, 186 { DC_DEVID(DC_VENDORID_MX, DC_DEVICEID_987x5), DC_REVISION_98725, 187 "Macronix 98725 10/100BaseTX" }, 188 { DC_DEVID(DC_VENDORID_MX, DC_DEVICEID_987x5), DC_REVISION_98715AEC_C, 189 "Macronix 98715AEC-C 10/100BaseTX" }, 190 { DC_DEVID(DC_VENDORID_MX, DC_DEVICEID_987x5), 0, 191 "Macronix 98715/98715A 10/100BaseTX" }, 192 { DC_DEVID(DC_VENDORID_MX, DC_DEVICEID_98727), 0, 193 "Macronix 98727/98732 10/100BaseTX" }, 194 { DC_DEVID(DC_VENDORID_LO, DC_DEVICEID_82C115), 0, 195 "LC82C115 PNIC II 10/100BaseTX" }, 196 { DC_DEVID(DC_VENDORID_LO, DC_DEVICEID_82C168), DC_REVISION_82C169, 197 "82c169 PNIC 10/100BaseTX" }, 198 { DC_DEVID(DC_VENDORID_LO, DC_DEVICEID_82C168), 0, 199 "82c168 PNIC 10/100BaseTX" }, 200 { DC_DEVID(DC_VENDORID_ACCTON, DC_DEVICEID_EN1217), 0, 201 "Accton EN1217 10/100BaseTX" }, 202 { DC_DEVID(DC_VENDORID_ACCTON, DC_DEVICEID_EN2242), 0, 203 "Accton EN2242 MiniPCI 10/100BaseTX" }, 204 { DC_DEVID(DC_VENDORID_XIRCOM, DC_DEVICEID_X3201), 0, 205 "Xircom X3201 10/100BaseTX" }, 206 { DC_DEVID(DC_VENDORID_DLINK, DC_DEVICEID_DRP32TXD), 0, 207 "Neteasy DRP-32TXD Cardbus 10/100" }, 208 { DC_DEVID(DC_VENDORID_ABOCOM, DC_DEVICEID_FE2500), 0, 209 "Abocom FE2500 10/100BaseTX" }, 210 { DC_DEVID(DC_VENDORID_ABOCOM, DC_DEVICEID_FE2500MX), 0, 211 "Abocom FE2500MX 10/100BaseTX" }, 212 { DC_DEVID(DC_VENDORID_CONEXANT, DC_DEVICEID_RS7112), 0, 213 "Conexant LANfinity MiniPCI 10/100BaseTX" }, 214 { DC_DEVID(DC_VENDORID_HAWKING, DC_DEVICEID_HAWKING_PN672TX), 0, 215 "Hawking CB102 CardBus 10/100" }, 216 { DC_DEVID(DC_VENDORID_PLANEX, DC_DEVICEID_FNW3602T), 0, 217 "PlaneX FNW-3602-T CardBus 10/100" }, 218 { DC_DEVID(DC_VENDORID_3COM, DC_DEVICEID_3CSOHOB), 0, 219 "3Com OfficeConnect 10/100B" }, 220 { DC_DEVID(DC_VENDORID_MICROSOFT, DC_DEVICEID_MSMN120), 0, 221 "Microsoft MN-120 CardBus 10/100" }, 222 { DC_DEVID(DC_VENDORID_MICROSOFT, DC_DEVICEID_MSMN130), 0, 223 "Microsoft MN-130 10/100" }, 224 { DC_DEVID(DC_VENDORID_LINKSYS, DC_DEVICEID_PCMPC200_AB08), 0, 225 "Linksys PCMPC200 CardBus 10/100" }, 226 { DC_DEVID(DC_VENDORID_LINKSYS, DC_DEVICEID_PCMPC200_AB09), 0, 227 "Linksys PCMPC200 CardBus 10/100" }, 228 { DC_DEVID(DC_VENDORID_ULI, DC_DEVICEID_M5261), 0, 229 "ULi M5261 FastEthernet" }, 230 { DC_DEVID(DC_VENDORID_ULI, DC_DEVICEID_M5263), 0, 231 "ULi M5263 FastEthernet" }, 232 { 0, 0, NULL } 233 }; 234 235 static int dc_probe(device_t); 236 static int dc_attach(device_t); 237 static int dc_detach(device_t); 238 static int dc_suspend(device_t); 239 static int dc_resume(device_t); 240 static const struct dc_type *dc_devtype(device_t); 241 static void dc_discard_rxbuf(struct dc_softc *, int); 242 static int dc_newbuf(struct dc_softc *, int); 243 static int dc_encap(struct dc_softc *, struct mbuf **); 244 static void dc_pnic_rx_bug_war(struct dc_softc *, int); 245 static int dc_rx_resync(struct dc_softc *); 246 static int dc_rxeof(struct dc_softc *); 247 static void dc_txeof(struct dc_softc *); 248 static void dc_tick(void *); 249 static void dc_tx_underrun(struct dc_softc *); 250 static void dc_intr(void *); 251 static void dc_start(struct ifnet *); 252 static void dc_start_locked(struct ifnet *); 253 static int dc_ioctl(struct ifnet *, u_long, caddr_t); 254 static void dc_init(void *); 255 static void dc_init_locked(struct dc_softc *); 256 static void dc_stop(struct dc_softc *); 257 static void dc_watchdog(void *); 258 static int dc_shutdown(device_t); 259 static int dc_ifmedia_upd(struct ifnet *); 260 static int dc_ifmedia_upd_locked(struct dc_softc *); 261 static void dc_ifmedia_sts(struct ifnet *, struct ifmediareq *); 262 263 static int dc_dma_alloc(struct dc_softc *); 264 static void dc_dma_free(struct dc_softc *); 265 static void dc_dma_map_addr(void *, bus_dma_segment_t *, int, int); 266 267 static void dc_delay(struct dc_softc *); 268 static void dc_eeprom_idle(struct dc_softc *); 269 static void dc_eeprom_putbyte(struct dc_softc *, int); 270 static void dc_eeprom_getword(struct dc_softc *, int, uint16_t *); 271 static void dc_eeprom_getword_pnic(struct dc_softc *, int, uint16_t *); 272 static void dc_eeprom_getword_xircom(struct dc_softc *, int, uint16_t *); 273 static void dc_eeprom_width(struct dc_softc *); 274 static void dc_read_eeprom(struct dc_softc *, caddr_t, int, int, int); 275 276 static int dc_miibus_readreg(device_t, int, int); 277 static int dc_miibus_writereg(device_t, int, int, int); 278 static void dc_miibus_statchg(device_t); 279 static void dc_miibus_mediainit(device_t); 280 281 static void dc_setcfg(struct dc_softc *, int); 282 static void dc_netcfg_wait(struct dc_softc *); 283 static uint32_t dc_mchash_le(struct dc_softc *, const uint8_t *); 284 static uint32_t dc_mchash_be(const uint8_t *); 285 static void dc_setfilt_21143(struct dc_softc *); 286 static void dc_setfilt_asix(struct dc_softc *); 287 static void dc_setfilt_admtek(struct dc_softc *); 288 static void dc_setfilt_uli(struct dc_softc *); 289 static void dc_setfilt_xircom(struct dc_softc *); 290 291 static void dc_setfilt(struct dc_softc *); 292 293 static void dc_reset(struct dc_softc *); 294 static int dc_list_rx_init(struct dc_softc *); 295 static int dc_list_tx_init(struct dc_softc *); 296 297 static int dc_read_srom(struct dc_softc *, int); 298 static int dc_parse_21143_srom(struct dc_softc *); 299 static int dc_decode_leaf_sia(struct dc_softc *, struct dc_eblock_sia *); 300 static int dc_decode_leaf_mii(struct dc_softc *, struct dc_eblock_mii *); 301 static int dc_decode_leaf_sym(struct dc_softc *, struct dc_eblock_sym *); 302 static void dc_apply_fixup(struct dc_softc *, int); 303 static int dc_check_multiport(struct dc_softc *); 304 305 /* 306 * MII bit-bang glue 307 */ 308 static uint32_t dc_mii_bitbang_read(device_t); 309 static void dc_mii_bitbang_write(device_t, uint32_t); 310 311 static const struct mii_bitbang_ops dc_mii_bitbang_ops = { 312 dc_mii_bitbang_read, 313 dc_mii_bitbang_write, 314 { 315 DC_SIO_MII_DATAOUT, /* MII_BIT_MDO */ 316 DC_SIO_MII_DATAIN, /* MII_BIT_MDI */ 317 DC_SIO_MII_CLK, /* MII_BIT_MDC */ 318 0, /* MII_BIT_DIR_HOST_PHY */ 319 DC_SIO_MII_DIR, /* MII_BIT_DIR_PHY_HOST */ 320 } 321 }; 322 323 #ifdef DC_USEIOSPACE 324 #define DC_RES SYS_RES_IOPORT 325 #define DC_RID DC_PCI_CFBIO 326 #else 327 #define DC_RES SYS_RES_MEMORY 328 #define DC_RID DC_PCI_CFBMA 329 #endif 330 331 static device_method_t dc_methods[] = { 332 /* Device interface */ 333 DEVMETHOD(device_probe, dc_probe), 334 DEVMETHOD(device_attach, dc_attach), 335 DEVMETHOD(device_detach, dc_detach), 336 DEVMETHOD(device_suspend, dc_suspend), 337 DEVMETHOD(device_resume, dc_resume), 338 DEVMETHOD(device_shutdown, dc_shutdown), 339 340 /* MII interface */ 341 DEVMETHOD(miibus_readreg, dc_miibus_readreg), 342 DEVMETHOD(miibus_writereg, dc_miibus_writereg), 343 DEVMETHOD(miibus_statchg, dc_miibus_statchg), 344 DEVMETHOD(miibus_mediainit, dc_miibus_mediainit), 345 346 DEVMETHOD_END 347 }; 348 349 static driver_t dc_driver = { 350 "dc", 351 dc_methods, 352 sizeof(struct dc_softc) 353 }; 354 355 static devclass_t dc_devclass; 356 357 DRIVER_MODULE(dc, pci, dc_driver, dc_devclass, 0, 0); 358 DRIVER_MODULE(miibus, dc, miibus_driver, miibus_devclass, 0, 0); 359 360 #define DC_SETBIT(sc, reg, x) \ 361 CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) | (x)) 362 363 #define DC_CLRBIT(sc, reg, x) \ 364 CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) & ~(x)) 365 366 #define SIO_SET(x) DC_SETBIT(sc, DC_SIO, (x)) 367 #define SIO_CLR(x) DC_CLRBIT(sc, DC_SIO, (x)) 368 369 static void 370 dc_delay(struct dc_softc *sc) 371 { 372 int idx; 373 374 for (idx = (300 / 33) + 1; idx > 0; idx--) 375 CSR_READ_4(sc, DC_BUSCTL); 376 } 377 378 static void 379 dc_eeprom_width(struct dc_softc *sc) 380 { 381 int i; 382 383 /* Force EEPROM to idle state. */ 384 dc_eeprom_idle(sc); 385 386 /* Enter EEPROM access mode. */ 387 CSR_WRITE_4(sc, DC_SIO, DC_SIO_EESEL); 388 dc_delay(sc); 389 DC_SETBIT(sc, DC_SIO, DC_SIO_ROMCTL_READ); 390 dc_delay(sc); 391 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); 392 dc_delay(sc); 393 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CS); 394 dc_delay(sc); 395 396 for (i = 3; i--;) { 397 if (6 & (1 << i)) 398 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_DATAIN); 399 else 400 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_DATAIN); 401 dc_delay(sc); 402 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CLK); 403 dc_delay(sc); 404 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); 405 dc_delay(sc); 406 } 407 408 for (i = 1; i <= 12; i++) { 409 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CLK); 410 dc_delay(sc); 411 if (!(CSR_READ_4(sc, DC_SIO) & DC_SIO_EE_DATAOUT)) { 412 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); 413 dc_delay(sc); 414 break; 415 } 416 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); 417 dc_delay(sc); 418 } 419 420 /* Turn off EEPROM access mode. */ 421 dc_eeprom_idle(sc); 422 423 if (i < 4 || i > 12) 424 sc->dc_romwidth = 6; 425 else 426 sc->dc_romwidth = i; 427 428 /* Enter EEPROM access mode. */ 429 CSR_WRITE_4(sc, DC_SIO, DC_SIO_EESEL); 430 dc_delay(sc); 431 DC_SETBIT(sc, DC_SIO, DC_SIO_ROMCTL_READ); 432 dc_delay(sc); 433 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); 434 dc_delay(sc); 435 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CS); 436 dc_delay(sc); 437 438 /* Turn off EEPROM access mode. */ 439 dc_eeprom_idle(sc); 440 } 441 442 static void 443 dc_eeprom_idle(struct dc_softc *sc) 444 { 445 int i; 446 447 CSR_WRITE_4(sc, DC_SIO, DC_SIO_EESEL); 448 dc_delay(sc); 449 DC_SETBIT(sc, DC_SIO, DC_SIO_ROMCTL_READ); 450 dc_delay(sc); 451 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); 452 dc_delay(sc); 453 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CS); 454 dc_delay(sc); 455 456 for (i = 0; i < 25; i++) { 457 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); 458 dc_delay(sc); 459 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CLK); 460 dc_delay(sc); 461 } 462 463 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); 464 dc_delay(sc); 465 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CS); 466 dc_delay(sc); 467 CSR_WRITE_4(sc, DC_SIO, 0x00000000); 468 } 469 470 /* 471 * Send a read command and address to the EEPROM, check for ACK. 472 */ 473 static void 474 dc_eeprom_putbyte(struct dc_softc *sc, int addr) 475 { 476 int d, i; 477 478 d = DC_EECMD_READ >> 6; 479 for (i = 3; i--; ) { 480 if (d & (1 << i)) 481 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_DATAIN); 482 else 483 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_DATAIN); 484 dc_delay(sc); 485 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CLK); 486 dc_delay(sc); 487 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); 488 dc_delay(sc); 489 } 490 491 /* 492 * Feed in each bit and strobe the clock. 493 */ 494 for (i = sc->dc_romwidth; i--;) { 495 if (addr & (1 << i)) { 496 SIO_SET(DC_SIO_EE_DATAIN); 497 } else { 498 SIO_CLR(DC_SIO_EE_DATAIN); 499 } 500 dc_delay(sc); 501 SIO_SET(DC_SIO_EE_CLK); 502 dc_delay(sc); 503 SIO_CLR(DC_SIO_EE_CLK); 504 dc_delay(sc); 505 } 506 } 507 508 /* 509 * Read a word of data stored in the EEPROM at address 'addr.' 510 * The PNIC 82c168/82c169 has its own non-standard way to read 511 * the EEPROM. 512 */ 513 static void 514 dc_eeprom_getword_pnic(struct dc_softc *sc, int addr, uint16_t *dest) 515 { 516 int i; 517 uint32_t r; 518 519 CSR_WRITE_4(sc, DC_PN_SIOCTL, DC_PN_EEOPCODE_READ | addr); 520 521 for (i = 0; i < DC_TIMEOUT; i++) { 522 DELAY(1); 523 r = CSR_READ_4(sc, DC_SIO); 524 if (!(r & DC_PN_SIOCTL_BUSY)) { 525 *dest = (uint16_t)(r & 0xFFFF); 526 return; 527 } 528 } 529 } 530 531 /* 532 * Read a word of data stored in the EEPROM at address 'addr.' 533 * The Xircom X3201 has its own non-standard way to read 534 * the EEPROM, too. 535 */ 536 static void 537 dc_eeprom_getword_xircom(struct dc_softc *sc, int addr, uint16_t *dest) 538 { 539 540 SIO_SET(DC_SIO_ROMSEL | DC_SIO_ROMCTL_READ); 541 542 addr *= 2; 543 CSR_WRITE_4(sc, DC_ROM, addr | 0x160); 544 *dest = (uint16_t)CSR_READ_4(sc, DC_SIO) & 0xff; 545 addr += 1; 546 CSR_WRITE_4(sc, DC_ROM, addr | 0x160); 547 *dest |= ((uint16_t)CSR_READ_4(sc, DC_SIO) & 0xff) << 8; 548 549 SIO_CLR(DC_SIO_ROMSEL | DC_SIO_ROMCTL_READ); 550 } 551 552 /* 553 * Read a word of data stored in the EEPROM at address 'addr.' 554 */ 555 static void 556 dc_eeprom_getword(struct dc_softc *sc, int addr, uint16_t *dest) 557 { 558 int i; 559 uint16_t word = 0; 560 561 /* Force EEPROM to idle state. */ 562 dc_eeprom_idle(sc); 563 564 /* Enter EEPROM access mode. */ 565 CSR_WRITE_4(sc, DC_SIO, DC_SIO_EESEL); 566 dc_delay(sc); 567 DC_SETBIT(sc, DC_SIO, DC_SIO_ROMCTL_READ); 568 dc_delay(sc); 569 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); 570 dc_delay(sc); 571 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CS); 572 dc_delay(sc); 573 574 /* 575 * Send address of word we want to read. 576 */ 577 dc_eeprom_putbyte(sc, addr); 578 579 /* 580 * Start reading bits from EEPROM. 581 */ 582 for (i = 0x8000; i; i >>= 1) { 583 SIO_SET(DC_SIO_EE_CLK); 584 dc_delay(sc); 585 if (CSR_READ_4(sc, DC_SIO) & DC_SIO_EE_DATAOUT) 586 word |= i; 587 dc_delay(sc); 588 SIO_CLR(DC_SIO_EE_CLK); 589 dc_delay(sc); 590 } 591 592 /* Turn off EEPROM access mode. */ 593 dc_eeprom_idle(sc); 594 595 *dest = word; 596 } 597 598 /* 599 * Read a sequence of words from the EEPROM. 600 */ 601 static void 602 dc_read_eeprom(struct dc_softc *sc, caddr_t dest, int off, int cnt, int be) 603 { 604 int i; 605 uint16_t word = 0, *ptr; 606 607 for (i = 0; i < cnt; i++) { 608 if (DC_IS_PNIC(sc)) 609 dc_eeprom_getword_pnic(sc, off + i, &word); 610 else if (DC_IS_XIRCOM(sc)) 611 dc_eeprom_getword_xircom(sc, off + i, &word); 612 else 613 dc_eeprom_getword(sc, off + i, &word); 614 ptr = (uint16_t *)(dest + (i * 2)); 615 if (be) 616 *ptr = be16toh(word); 617 else 618 *ptr = le16toh(word); 619 } 620 } 621 622 /* 623 * Write the MII serial port for the MII bit-bang module. 624 */ 625 static void 626 dc_mii_bitbang_write(device_t dev, uint32_t val) 627 { 628 struct dc_softc *sc; 629 630 sc = device_get_softc(dev); 631 632 CSR_WRITE_4(sc, DC_SIO, val); 633 CSR_BARRIER_4(sc, DC_SIO, 634 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 635 } 636 637 /* 638 * Read the MII serial port for the MII bit-bang module. 639 */ 640 static uint32_t 641 dc_mii_bitbang_read(device_t dev) 642 { 643 struct dc_softc *sc; 644 uint32_t val; 645 646 sc = device_get_softc(dev); 647 648 val = CSR_READ_4(sc, DC_SIO); 649 CSR_BARRIER_4(sc, DC_SIO, 650 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 651 652 return (val); 653 } 654 655 static int 656 dc_miibus_readreg(device_t dev, int phy, int reg) 657 { 658 struct dc_softc *sc; 659 int i, rval, phy_reg = 0; 660 661 sc = device_get_softc(dev); 662 663 if (sc->dc_pmode != DC_PMODE_MII) { 664 if (phy == (MII_NPHY - 1)) { 665 switch (reg) { 666 case MII_BMSR: 667 /* 668 * Fake something to make the probe 669 * code think there's a PHY here. 670 */ 671 return (BMSR_MEDIAMASK); 672 break; 673 case MII_PHYIDR1: 674 if (DC_IS_PNIC(sc)) 675 return (DC_VENDORID_LO); 676 return (DC_VENDORID_DEC); 677 break; 678 case MII_PHYIDR2: 679 if (DC_IS_PNIC(sc)) 680 return (DC_DEVICEID_82C168); 681 return (DC_DEVICEID_21143); 682 break; 683 default: 684 return (0); 685 break; 686 } 687 } else 688 return (0); 689 } 690 691 if (DC_IS_PNIC(sc)) { 692 CSR_WRITE_4(sc, DC_PN_MII, DC_PN_MIIOPCODE_READ | 693 (phy << 23) | (reg << 18)); 694 for (i = 0; i < DC_TIMEOUT; i++) { 695 DELAY(1); 696 rval = CSR_READ_4(sc, DC_PN_MII); 697 if (!(rval & DC_PN_MII_BUSY)) { 698 rval &= 0xFFFF; 699 return (rval == 0xFFFF ? 0 : rval); 700 } 701 } 702 return (0); 703 } 704 705 if (sc->dc_type == DC_TYPE_ULI_M5263) { 706 CSR_WRITE_4(sc, DC_ROM, 707 ((phy << DC_ULI_PHY_ADDR_SHIFT) & DC_ULI_PHY_ADDR_MASK) | 708 ((reg << DC_ULI_PHY_REG_SHIFT) & DC_ULI_PHY_REG_MASK) | 709 DC_ULI_PHY_OP_READ); 710 for (i = 0; i < DC_TIMEOUT; i++) { 711 DELAY(1); 712 rval = CSR_READ_4(sc, DC_ROM); 713 if ((rval & DC_ULI_PHY_OP_DONE) != 0) { 714 return (rval & DC_ULI_PHY_DATA_MASK); 715 } 716 } 717 if (i == DC_TIMEOUT) 718 device_printf(dev, "phy read timed out\n"); 719 return (0); 720 } 721 722 if (DC_IS_COMET(sc)) { 723 switch (reg) { 724 case MII_BMCR: 725 phy_reg = DC_AL_BMCR; 726 break; 727 case MII_BMSR: 728 phy_reg = DC_AL_BMSR; 729 break; 730 case MII_PHYIDR1: 731 phy_reg = DC_AL_VENID; 732 break; 733 case MII_PHYIDR2: 734 phy_reg = DC_AL_DEVID; 735 break; 736 case MII_ANAR: 737 phy_reg = DC_AL_ANAR; 738 break; 739 case MII_ANLPAR: 740 phy_reg = DC_AL_LPAR; 741 break; 742 case MII_ANER: 743 phy_reg = DC_AL_ANER; 744 break; 745 default: 746 device_printf(dev, "phy_read: bad phy register %x\n", 747 reg); 748 return (0); 749 break; 750 } 751 752 rval = CSR_READ_4(sc, phy_reg) & 0x0000FFFF; 753 if (rval == 0xFFFF) 754 return (0); 755 return (rval); 756 } 757 758 if (sc->dc_type == DC_TYPE_98713) { 759 phy_reg = CSR_READ_4(sc, DC_NETCFG); 760 CSR_WRITE_4(sc, DC_NETCFG, phy_reg & ~DC_NETCFG_PORTSEL); 761 } 762 rval = mii_bitbang_readreg(dev, &dc_mii_bitbang_ops, phy, reg); 763 if (sc->dc_type == DC_TYPE_98713) 764 CSR_WRITE_4(sc, DC_NETCFG, phy_reg); 765 766 return (rval); 767 } 768 769 static int 770 dc_miibus_writereg(device_t dev, int phy, int reg, int data) 771 { 772 struct dc_softc *sc; 773 int i, phy_reg = 0; 774 775 sc = device_get_softc(dev); 776 777 if (DC_IS_PNIC(sc)) { 778 CSR_WRITE_4(sc, DC_PN_MII, DC_PN_MIIOPCODE_WRITE | 779 (phy << 23) | (reg << 10) | data); 780 for (i = 0; i < DC_TIMEOUT; i++) { 781 if (!(CSR_READ_4(sc, DC_PN_MII) & DC_PN_MII_BUSY)) 782 break; 783 } 784 return (0); 785 } 786 787 if (sc->dc_type == DC_TYPE_ULI_M5263) { 788 CSR_WRITE_4(sc, DC_ROM, 789 ((phy << DC_ULI_PHY_ADDR_SHIFT) & DC_ULI_PHY_ADDR_MASK) | 790 ((reg << DC_ULI_PHY_REG_SHIFT) & DC_ULI_PHY_REG_MASK) | 791 ((data << DC_ULI_PHY_DATA_SHIFT) & DC_ULI_PHY_DATA_MASK) | 792 DC_ULI_PHY_OP_WRITE); 793 DELAY(1); 794 return (0); 795 } 796 797 if (DC_IS_COMET(sc)) { 798 switch (reg) { 799 case MII_BMCR: 800 phy_reg = DC_AL_BMCR; 801 break; 802 case MII_BMSR: 803 phy_reg = DC_AL_BMSR; 804 break; 805 case MII_PHYIDR1: 806 phy_reg = DC_AL_VENID; 807 break; 808 case MII_PHYIDR2: 809 phy_reg = DC_AL_DEVID; 810 break; 811 case MII_ANAR: 812 phy_reg = DC_AL_ANAR; 813 break; 814 case MII_ANLPAR: 815 phy_reg = DC_AL_LPAR; 816 break; 817 case MII_ANER: 818 phy_reg = DC_AL_ANER; 819 break; 820 default: 821 device_printf(dev, "phy_write: bad phy register %x\n", 822 reg); 823 return (0); 824 break; 825 } 826 827 CSR_WRITE_4(sc, phy_reg, data); 828 return (0); 829 } 830 831 if (sc->dc_type == DC_TYPE_98713) { 832 phy_reg = CSR_READ_4(sc, DC_NETCFG); 833 CSR_WRITE_4(sc, DC_NETCFG, phy_reg & ~DC_NETCFG_PORTSEL); 834 } 835 mii_bitbang_writereg(dev, &dc_mii_bitbang_ops, phy, reg, data); 836 if (sc->dc_type == DC_TYPE_98713) 837 CSR_WRITE_4(sc, DC_NETCFG, phy_reg); 838 839 return (0); 840 } 841 842 static void 843 dc_miibus_statchg(device_t dev) 844 { 845 struct dc_softc *sc; 846 struct ifnet *ifp; 847 struct mii_data *mii; 848 struct ifmedia *ifm; 849 850 sc = device_get_softc(dev); 851 852 mii = device_get_softc(sc->dc_miibus); 853 ifp = sc->dc_ifp; 854 if (mii == NULL || ifp == NULL || 855 (ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) 856 return; 857 858 ifm = &mii->mii_media; 859 if (DC_IS_DAVICOM(sc) && IFM_SUBTYPE(ifm->ifm_media) == IFM_HPNA_1) { 860 dc_setcfg(sc, ifm->ifm_media); 861 return; 862 } else if (!DC_IS_ADMTEK(sc)) 863 dc_setcfg(sc, mii->mii_media_active); 864 865 sc->dc_link = 0; 866 if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) == 867 (IFM_ACTIVE | IFM_AVALID)) { 868 switch (IFM_SUBTYPE(mii->mii_media_active)) { 869 case IFM_10_T: 870 case IFM_100_TX: 871 sc->dc_link = 1; 872 break; 873 } 874 } 875 } 876 877 /* 878 * Special support for DM9102A cards with HomePNA PHYs. Note: 879 * with the Davicom DM9102A/DM9801 eval board that I have, it seems 880 * to be impossible to talk to the management interface of the DM9801 881 * PHY (its MDIO pin is not connected to anything). Consequently, 882 * the driver has to just 'know' about the additional mode and deal 883 * with it itself. *sigh* 884 */ 885 static void 886 dc_miibus_mediainit(device_t dev) 887 { 888 struct dc_softc *sc; 889 struct mii_data *mii; 890 struct ifmedia *ifm; 891 int rev; 892 893 rev = pci_get_revid(dev); 894 895 sc = device_get_softc(dev); 896 mii = device_get_softc(sc->dc_miibus); 897 ifm = &mii->mii_media; 898 899 if (DC_IS_DAVICOM(sc) && rev >= DC_REVISION_DM9102A) 900 ifmedia_add(ifm, IFM_ETHER | IFM_HPNA_1, 0, NULL); 901 } 902 903 #define DC_BITS_512 9 904 #define DC_BITS_128 7 905 #define DC_BITS_64 6 906 907 static uint32_t 908 dc_mchash_le(struct dc_softc *sc, const uint8_t *addr) 909 { 910 uint32_t crc; 911 912 /* Compute CRC for the address value. */ 913 crc = ether_crc32_le(addr, ETHER_ADDR_LEN); 914 915 /* 916 * The hash table on the PNIC II and the MX98715AEC-C/D/E 917 * chips is only 128 bits wide. 918 */ 919 if (sc->dc_flags & DC_128BIT_HASH) 920 return (crc & ((1 << DC_BITS_128) - 1)); 921 922 /* The hash table on the MX98715BEC is only 64 bits wide. */ 923 if (sc->dc_flags & DC_64BIT_HASH) 924 return (crc & ((1 << DC_BITS_64) - 1)); 925 926 /* Xircom's hash filtering table is different (read: weird) */ 927 /* Xircom uses the LEAST significant bits */ 928 if (DC_IS_XIRCOM(sc)) { 929 if ((crc & 0x180) == 0x180) 930 return ((crc & 0x0F) + (crc & 0x70) * 3 + (14 << 4)); 931 else 932 return ((crc & 0x1F) + ((crc >> 1) & 0xF0) * 3 + 933 (12 << 4)); 934 } 935 936 return (crc & ((1 << DC_BITS_512) - 1)); 937 } 938 939 /* 940 * Calculate CRC of a multicast group address, return the lower 6 bits. 941 */ 942 static uint32_t 943 dc_mchash_be(const uint8_t *addr) 944 { 945 uint32_t crc; 946 947 /* Compute CRC for the address value. */ 948 crc = ether_crc32_be(addr, ETHER_ADDR_LEN); 949 950 /* Return the filter bit position. */ 951 return ((crc >> 26) & 0x0000003F); 952 } 953 954 /* 955 * 21143-style RX filter setup routine. Filter programming is done by 956 * downloading a special setup frame into the TX engine. 21143, Macronix, 957 * PNIC, PNIC II and Davicom chips are programmed this way. 958 * 959 * We always program the chip using 'hash perfect' mode, i.e. one perfect 960 * address (our node address) and a 512-bit hash filter for multicast 961 * frames. We also sneak the broadcast address into the hash filter since 962 * we need that too. 963 */ 964 static void 965 dc_setfilt_21143(struct dc_softc *sc) 966 { 967 uint16_t eaddr[(ETHER_ADDR_LEN+1)/2]; 968 struct dc_desc *sframe; 969 uint32_t h, *sp; 970 struct ifmultiaddr *ifma; 971 struct ifnet *ifp; 972 int i; 973 974 ifp = sc->dc_ifp; 975 976 i = sc->dc_cdata.dc_tx_prod; 977 DC_INC(sc->dc_cdata.dc_tx_prod, DC_TX_LIST_CNT); 978 sc->dc_cdata.dc_tx_cnt++; 979 sframe = &sc->dc_ldata.dc_tx_list[i]; 980 sp = sc->dc_cdata.dc_sbuf; 981 bzero(sp, DC_SFRAME_LEN); 982 983 sframe->dc_data = htole32(DC_ADDR_LO(sc->dc_saddr)); 984 sframe->dc_ctl = htole32(DC_SFRAME_LEN | DC_TXCTL_SETUP | 985 DC_TXCTL_TLINK | DC_FILTER_HASHPERF | DC_TXCTL_FINT); 986 987 sc->dc_cdata.dc_tx_chain[i] = (struct mbuf *)sc->dc_cdata.dc_sbuf; 988 989 /* If we want promiscuous mode, set the allframes bit. */ 990 if (ifp->if_flags & IFF_PROMISC) 991 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC); 992 else 993 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC); 994 995 if (ifp->if_flags & IFF_ALLMULTI) 996 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI); 997 else 998 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI); 999 1000 if_maddr_rlock(ifp); 1001 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 1002 if (ifma->ifma_addr->sa_family != AF_LINK) 1003 continue; 1004 h = dc_mchash_le(sc, 1005 LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 1006 sp[h >> 4] |= htole32(1 << (h & 0xF)); 1007 } 1008 if_maddr_runlock(ifp); 1009 1010 if (ifp->if_flags & IFF_BROADCAST) { 1011 h = dc_mchash_le(sc, ifp->if_broadcastaddr); 1012 sp[h >> 4] |= htole32(1 << (h & 0xF)); 1013 } 1014 1015 /* Set our MAC address. */ 1016 bcopy(IF_LLADDR(sc->dc_ifp), eaddr, ETHER_ADDR_LEN); 1017 sp[39] = DC_SP_MAC(eaddr[0]); 1018 sp[40] = DC_SP_MAC(eaddr[1]); 1019 sp[41] = DC_SP_MAC(eaddr[2]); 1020 1021 sframe->dc_status = htole32(DC_TXSTAT_OWN); 1022 bus_dmamap_sync(sc->dc_tx_ltag, sc->dc_tx_lmap, BUS_DMASYNC_PREREAD | 1023 BUS_DMASYNC_PREWRITE); 1024 bus_dmamap_sync(sc->dc_stag, sc->dc_smap, BUS_DMASYNC_PREWRITE); 1025 CSR_WRITE_4(sc, DC_TXSTART, 0xFFFFFFFF); 1026 1027 /* 1028 * The PNIC takes an exceedingly long time to process its 1029 * setup frame; wait 10ms after posting the setup frame 1030 * before proceeding, just so it has time to swallow its 1031 * medicine. 1032 */ 1033 DELAY(10000); 1034 1035 sc->dc_wdog_timer = 5; 1036 } 1037 1038 static void 1039 dc_setfilt_admtek(struct dc_softc *sc) 1040 { 1041 uint8_t eaddr[ETHER_ADDR_LEN]; 1042 struct ifnet *ifp; 1043 struct ifmultiaddr *ifma; 1044 int h = 0; 1045 uint32_t hashes[2] = { 0, 0 }; 1046 1047 ifp = sc->dc_ifp; 1048 1049 /* Init our MAC address. */ 1050 bcopy(IF_LLADDR(sc->dc_ifp), eaddr, ETHER_ADDR_LEN); 1051 CSR_WRITE_4(sc, DC_AL_PAR0, eaddr[3] << 24 | eaddr[2] << 16 | 1052 eaddr[1] << 8 | eaddr[0]); 1053 CSR_WRITE_4(sc, DC_AL_PAR1, eaddr[5] << 8 | eaddr[4]); 1054 1055 /* If we want promiscuous mode, set the allframes bit. */ 1056 if (ifp->if_flags & IFF_PROMISC) 1057 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC); 1058 else 1059 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC); 1060 1061 if (ifp->if_flags & IFF_ALLMULTI) 1062 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI); 1063 else 1064 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI); 1065 1066 /* First, zot all the existing hash bits. */ 1067 CSR_WRITE_4(sc, DC_AL_MAR0, 0); 1068 CSR_WRITE_4(sc, DC_AL_MAR1, 0); 1069 1070 /* 1071 * If we're already in promisc or allmulti mode, we 1072 * don't have to bother programming the multicast filter. 1073 */ 1074 if (ifp->if_flags & (IFF_PROMISC | IFF_ALLMULTI)) 1075 return; 1076 1077 /* Now program new ones. */ 1078 if_maddr_rlock(ifp); 1079 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 1080 if (ifma->ifma_addr->sa_family != AF_LINK) 1081 continue; 1082 if (DC_IS_CENTAUR(sc)) 1083 h = dc_mchash_le(sc, 1084 LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 1085 else 1086 h = dc_mchash_be( 1087 LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 1088 if (h < 32) 1089 hashes[0] |= (1 << h); 1090 else 1091 hashes[1] |= (1 << (h - 32)); 1092 } 1093 if_maddr_runlock(ifp); 1094 1095 CSR_WRITE_4(sc, DC_AL_MAR0, hashes[0]); 1096 CSR_WRITE_4(sc, DC_AL_MAR1, hashes[1]); 1097 } 1098 1099 static void 1100 dc_setfilt_asix(struct dc_softc *sc) 1101 { 1102 uint32_t eaddr[(ETHER_ADDR_LEN+3)/4]; 1103 struct ifnet *ifp; 1104 struct ifmultiaddr *ifma; 1105 int h = 0; 1106 uint32_t hashes[2] = { 0, 0 }; 1107 1108 ifp = sc->dc_ifp; 1109 1110 /* Init our MAC address. */ 1111 bcopy(IF_LLADDR(sc->dc_ifp), eaddr, ETHER_ADDR_LEN); 1112 CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_PAR0); 1113 CSR_WRITE_4(sc, DC_AX_FILTDATA, eaddr[0]); 1114 CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_PAR1); 1115 CSR_WRITE_4(sc, DC_AX_FILTDATA, eaddr[1]); 1116 1117 /* If we want promiscuous mode, set the allframes bit. */ 1118 if (ifp->if_flags & IFF_PROMISC) 1119 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC); 1120 else 1121 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC); 1122 1123 if (ifp->if_flags & IFF_ALLMULTI) 1124 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI); 1125 else 1126 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI); 1127 1128 /* 1129 * The ASIX chip has a special bit to enable reception 1130 * of broadcast frames. 1131 */ 1132 if (ifp->if_flags & IFF_BROADCAST) 1133 DC_SETBIT(sc, DC_NETCFG, DC_AX_NETCFG_RX_BROAD); 1134 else 1135 DC_CLRBIT(sc, DC_NETCFG, DC_AX_NETCFG_RX_BROAD); 1136 1137 /* first, zot all the existing hash bits */ 1138 CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_MAR0); 1139 CSR_WRITE_4(sc, DC_AX_FILTDATA, 0); 1140 CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_MAR1); 1141 CSR_WRITE_4(sc, DC_AX_FILTDATA, 0); 1142 1143 /* 1144 * If we're already in promisc or allmulti mode, we 1145 * don't have to bother programming the multicast filter. 1146 */ 1147 if (ifp->if_flags & (IFF_PROMISC | IFF_ALLMULTI)) 1148 return; 1149 1150 /* now program new ones */ 1151 if_maddr_rlock(ifp); 1152 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 1153 if (ifma->ifma_addr->sa_family != AF_LINK) 1154 continue; 1155 h = dc_mchash_be(LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 1156 if (h < 32) 1157 hashes[0] |= (1 << h); 1158 else 1159 hashes[1] |= (1 << (h - 32)); 1160 } 1161 if_maddr_runlock(ifp); 1162 1163 CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_MAR0); 1164 CSR_WRITE_4(sc, DC_AX_FILTDATA, hashes[0]); 1165 CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_MAR1); 1166 CSR_WRITE_4(sc, DC_AX_FILTDATA, hashes[1]); 1167 } 1168 1169 static void 1170 dc_setfilt_uli(struct dc_softc *sc) 1171 { 1172 uint8_t eaddr[ETHER_ADDR_LEN]; 1173 struct ifnet *ifp; 1174 struct ifmultiaddr *ifma; 1175 struct dc_desc *sframe; 1176 uint32_t filter, *sp; 1177 uint8_t *ma; 1178 int i, mcnt; 1179 1180 ifp = sc->dc_ifp; 1181 1182 i = sc->dc_cdata.dc_tx_prod; 1183 DC_INC(sc->dc_cdata.dc_tx_prod, DC_TX_LIST_CNT); 1184 sc->dc_cdata.dc_tx_cnt++; 1185 sframe = &sc->dc_ldata.dc_tx_list[i]; 1186 sp = sc->dc_cdata.dc_sbuf; 1187 bzero(sp, DC_SFRAME_LEN); 1188 1189 sframe->dc_data = htole32(DC_ADDR_LO(sc->dc_saddr)); 1190 sframe->dc_ctl = htole32(DC_SFRAME_LEN | DC_TXCTL_SETUP | 1191 DC_TXCTL_TLINK | DC_FILTER_PERFECT | DC_TXCTL_FINT); 1192 1193 sc->dc_cdata.dc_tx_chain[i] = (struct mbuf *)sc->dc_cdata.dc_sbuf; 1194 1195 /* Set station address. */ 1196 bcopy(IF_LLADDR(sc->dc_ifp), eaddr, ETHER_ADDR_LEN); 1197 *sp++ = DC_SP_MAC(eaddr[1] << 8 | eaddr[0]); 1198 *sp++ = DC_SP_MAC(eaddr[3] << 8 | eaddr[2]); 1199 *sp++ = DC_SP_MAC(eaddr[5] << 8 | eaddr[4]); 1200 1201 /* Set broadcast address. */ 1202 *sp++ = DC_SP_MAC(0xFFFF); 1203 *sp++ = DC_SP_MAC(0xFFFF); 1204 *sp++ = DC_SP_MAC(0xFFFF); 1205 1206 /* Extract current filter configuration. */ 1207 filter = CSR_READ_4(sc, DC_NETCFG); 1208 filter &= ~(DC_NETCFG_RX_PROMISC | DC_NETCFG_RX_ALLMULTI); 1209 1210 /* Now build perfect filters. */ 1211 mcnt = 0; 1212 if_maddr_rlock(ifp); 1213 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 1214 if (ifma->ifma_addr->sa_family != AF_LINK) 1215 continue; 1216 if (mcnt >= DC_ULI_FILTER_NPERF) { 1217 filter |= DC_NETCFG_RX_ALLMULTI; 1218 break; 1219 } 1220 ma = LLADDR((struct sockaddr_dl *)ifma->ifma_addr); 1221 *sp++ = DC_SP_MAC(ma[1] << 8 | ma[0]); 1222 *sp++ = DC_SP_MAC(ma[3] << 8 | ma[2]); 1223 *sp++ = DC_SP_MAC(ma[5] << 8 | ma[4]); 1224 mcnt++; 1225 } 1226 if_maddr_runlock(ifp); 1227 1228 for (; mcnt < DC_ULI_FILTER_NPERF; mcnt++) { 1229 *sp++ = DC_SP_MAC(0xFFFF); 1230 *sp++ = DC_SP_MAC(0xFFFF); 1231 *sp++ = DC_SP_MAC(0xFFFF); 1232 } 1233 1234 if (filter & (DC_NETCFG_TX_ON | DC_NETCFG_RX_ON)) 1235 CSR_WRITE_4(sc, DC_NETCFG, 1236 filter & ~(DC_NETCFG_TX_ON | DC_NETCFG_RX_ON)); 1237 if (ifp->if_flags & IFF_PROMISC) 1238 filter |= DC_NETCFG_RX_PROMISC | DC_NETCFG_RX_ALLMULTI; 1239 if (ifp->if_flags & IFF_ALLMULTI) 1240 filter |= DC_NETCFG_RX_ALLMULTI; 1241 CSR_WRITE_4(sc, DC_NETCFG, 1242 filter & ~(DC_NETCFG_TX_ON | DC_NETCFG_RX_ON)); 1243 if (filter & (DC_NETCFG_TX_ON | DC_NETCFG_RX_ON)) 1244 CSR_WRITE_4(sc, DC_NETCFG, filter); 1245 1246 sframe->dc_status = htole32(DC_TXSTAT_OWN); 1247 bus_dmamap_sync(sc->dc_tx_ltag, sc->dc_tx_lmap, BUS_DMASYNC_PREREAD | 1248 BUS_DMASYNC_PREWRITE); 1249 bus_dmamap_sync(sc->dc_stag, sc->dc_smap, BUS_DMASYNC_PREWRITE); 1250 CSR_WRITE_4(sc, DC_TXSTART, 0xFFFFFFFF); 1251 1252 /* 1253 * Wait some time... 1254 */ 1255 DELAY(1000); 1256 1257 sc->dc_wdog_timer = 5; 1258 } 1259 1260 static void 1261 dc_setfilt_xircom(struct dc_softc *sc) 1262 { 1263 uint16_t eaddr[(ETHER_ADDR_LEN+1)/2]; 1264 struct ifnet *ifp; 1265 struct ifmultiaddr *ifma; 1266 struct dc_desc *sframe; 1267 uint32_t h, *sp; 1268 int i; 1269 1270 ifp = sc->dc_ifp; 1271 DC_CLRBIT(sc, DC_NETCFG, (DC_NETCFG_TX_ON | DC_NETCFG_RX_ON)); 1272 1273 i = sc->dc_cdata.dc_tx_prod; 1274 DC_INC(sc->dc_cdata.dc_tx_prod, DC_TX_LIST_CNT); 1275 sc->dc_cdata.dc_tx_cnt++; 1276 sframe = &sc->dc_ldata.dc_tx_list[i]; 1277 sp = sc->dc_cdata.dc_sbuf; 1278 bzero(sp, DC_SFRAME_LEN); 1279 1280 sframe->dc_data = htole32(DC_ADDR_LO(sc->dc_saddr)); 1281 sframe->dc_ctl = htole32(DC_SFRAME_LEN | DC_TXCTL_SETUP | 1282 DC_TXCTL_TLINK | DC_FILTER_HASHPERF | DC_TXCTL_FINT); 1283 1284 sc->dc_cdata.dc_tx_chain[i] = (struct mbuf *)sc->dc_cdata.dc_sbuf; 1285 1286 /* If we want promiscuous mode, set the allframes bit. */ 1287 if (ifp->if_flags & IFF_PROMISC) 1288 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC); 1289 else 1290 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC); 1291 1292 if (ifp->if_flags & IFF_ALLMULTI) 1293 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI); 1294 else 1295 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI); 1296 1297 if_maddr_rlock(ifp); 1298 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 1299 if (ifma->ifma_addr->sa_family != AF_LINK) 1300 continue; 1301 h = dc_mchash_le(sc, 1302 LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 1303 sp[h >> 4] |= htole32(1 << (h & 0xF)); 1304 } 1305 if_maddr_runlock(ifp); 1306 1307 if (ifp->if_flags & IFF_BROADCAST) { 1308 h = dc_mchash_le(sc, ifp->if_broadcastaddr); 1309 sp[h >> 4] |= htole32(1 << (h & 0xF)); 1310 } 1311 1312 /* Set our MAC address. */ 1313 bcopy(IF_LLADDR(sc->dc_ifp), eaddr, ETHER_ADDR_LEN); 1314 sp[0] = DC_SP_MAC(eaddr[0]); 1315 sp[1] = DC_SP_MAC(eaddr[1]); 1316 sp[2] = DC_SP_MAC(eaddr[2]); 1317 1318 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_TX_ON); 1319 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_ON); 1320 sframe->dc_status = htole32(DC_TXSTAT_OWN); 1321 bus_dmamap_sync(sc->dc_tx_ltag, sc->dc_tx_lmap, BUS_DMASYNC_PREREAD | 1322 BUS_DMASYNC_PREWRITE); 1323 bus_dmamap_sync(sc->dc_stag, sc->dc_smap, BUS_DMASYNC_PREWRITE); 1324 CSR_WRITE_4(sc, DC_TXSTART, 0xFFFFFFFF); 1325 1326 /* 1327 * Wait some time... 1328 */ 1329 DELAY(1000); 1330 1331 sc->dc_wdog_timer = 5; 1332 } 1333 1334 static void 1335 dc_setfilt(struct dc_softc *sc) 1336 { 1337 1338 if (DC_IS_INTEL(sc) || DC_IS_MACRONIX(sc) || DC_IS_PNIC(sc) || 1339 DC_IS_PNICII(sc) || DC_IS_DAVICOM(sc) || DC_IS_CONEXANT(sc)) 1340 dc_setfilt_21143(sc); 1341 1342 if (DC_IS_ASIX(sc)) 1343 dc_setfilt_asix(sc); 1344 1345 if (DC_IS_ADMTEK(sc)) 1346 dc_setfilt_admtek(sc); 1347 1348 if (DC_IS_ULI(sc)) 1349 dc_setfilt_uli(sc); 1350 1351 if (DC_IS_XIRCOM(sc)) 1352 dc_setfilt_xircom(sc); 1353 } 1354 1355 static void 1356 dc_netcfg_wait(struct dc_softc *sc) 1357 { 1358 uint32_t isr; 1359 int i; 1360 1361 for (i = 0; i < DC_TIMEOUT; i++) { 1362 isr = CSR_READ_4(sc, DC_ISR); 1363 if (isr & DC_ISR_TX_IDLE && 1364 ((isr & DC_ISR_RX_STATE) == DC_RXSTATE_STOPPED || 1365 (isr & DC_ISR_RX_STATE) == DC_RXSTATE_WAIT)) 1366 break; 1367 DELAY(10); 1368 } 1369 if (i == DC_TIMEOUT && bus_child_present(sc->dc_dev)) { 1370 if (!(isr & DC_ISR_TX_IDLE) && !DC_IS_ASIX(sc)) 1371 device_printf(sc->dc_dev, 1372 "%s: failed to force tx to idle state\n", __func__); 1373 if (!((isr & DC_ISR_RX_STATE) == DC_RXSTATE_STOPPED || 1374 (isr & DC_ISR_RX_STATE) == DC_RXSTATE_WAIT) && 1375 !DC_HAS_BROKEN_RXSTATE(sc)) 1376 device_printf(sc->dc_dev, 1377 "%s: failed to force rx to idle state\n", __func__); 1378 } 1379 } 1380 1381 /* 1382 * In order to fiddle with the 'full-duplex' and '100Mbps' bits in 1383 * the netconfig register, we first have to put the transmit and/or 1384 * receive logic in the idle state. 1385 */ 1386 static void 1387 dc_setcfg(struct dc_softc *sc, int media) 1388 { 1389 int restart = 0, watchdogreg; 1390 1391 if (IFM_SUBTYPE(media) == IFM_NONE) 1392 return; 1393 1394 if (CSR_READ_4(sc, DC_NETCFG) & (DC_NETCFG_TX_ON | DC_NETCFG_RX_ON)) { 1395 restart = 1; 1396 DC_CLRBIT(sc, DC_NETCFG, (DC_NETCFG_TX_ON | DC_NETCFG_RX_ON)); 1397 dc_netcfg_wait(sc); 1398 } 1399 1400 if (IFM_SUBTYPE(media) == IFM_100_TX) { 1401 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_SPEEDSEL); 1402 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_HEARTBEAT); 1403 if (sc->dc_pmode == DC_PMODE_MII) { 1404 if (DC_IS_INTEL(sc)) { 1405 /* There's a write enable bit here that reads as 1. */ 1406 watchdogreg = CSR_READ_4(sc, DC_WATCHDOG); 1407 watchdogreg &= ~DC_WDOG_CTLWREN; 1408 watchdogreg |= DC_WDOG_JABBERDIS; 1409 CSR_WRITE_4(sc, DC_WATCHDOG, watchdogreg); 1410 } else { 1411 DC_SETBIT(sc, DC_WATCHDOG, DC_WDOG_JABBERDIS); 1412 } 1413 DC_CLRBIT(sc, DC_NETCFG, (DC_NETCFG_PCS | 1414 DC_NETCFG_PORTSEL | DC_NETCFG_SCRAMBLER)); 1415 if (sc->dc_type == DC_TYPE_98713) 1416 DC_SETBIT(sc, DC_NETCFG, (DC_NETCFG_PCS | 1417 DC_NETCFG_SCRAMBLER)); 1418 if (!DC_IS_DAVICOM(sc)) 1419 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL); 1420 DC_CLRBIT(sc, DC_10BTCTRL, 0xFFFF); 1421 } else { 1422 if (DC_IS_PNIC(sc)) { 1423 DC_PN_GPIO_SETBIT(sc, DC_PN_GPIO_SPEEDSEL); 1424 DC_PN_GPIO_SETBIT(sc, DC_PN_GPIO_100TX_LOOP); 1425 DC_SETBIT(sc, DC_PN_NWAY, DC_PN_NWAY_SPEEDSEL); 1426 } 1427 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL); 1428 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PCS); 1429 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_SCRAMBLER); 1430 } 1431 } 1432 1433 if (IFM_SUBTYPE(media) == IFM_10_T) { 1434 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_SPEEDSEL); 1435 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_HEARTBEAT); 1436 if (sc->dc_pmode == DC_PMODE_MII) { 1437 /* There's a write enable bit here that reads as 1. */ 1438 if (DC_IS_INTEL(sc)) { 1439 watchdogreg = CSR_READ_4(sc, DC_WATCHDOG); 1440 watchdogreg &= ~DC_WDOG_CTLWREN; 1441 watchdogreg |= DC_WDOG_JABBERDIS; 1442 CSR_WRITE_4(sc, DC_WATCHDOG, watchdogreg); 1443 } else { 1444 DC_SETBIT(sc, DC_WATCHDOG, DC_WDOG_JABBERDIS); 1445 } 1446 DC_CLRBIT(sc, DC_NETCFG, (DC_NETCFG_PCS | 1447 DC_NETCFG_PORTSEL | DC_NETCFG_SCRAMBLER)); 1448 if (sc->dc_type == DC_TYPE_98713) 1449 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PCS); 1450 if (!DC_IS_DAVICOM(sc)) 1451 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL); 1452 DC_CLRBIT(sc, DC_10BTCTRL, 0xFFFF); 1453 } else { 1454 if (DC_IS_PNIC(sc)) { 1455 DC_PN_GPIO_CLRBIT(sc, DC_PN_GPIO_SPEEDSEL); 1456 DC_PN_GPIO_SETBIT(sc, DC_PN_GPIO_100TX_LOOP); 1457 DC_CLRBIT(sc, DC_PN_NWAY, DC_PN_NWAY_SPEEDSEL); 1458 } 1459 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL); 1460 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_PCS); 1461 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_SCRAMBLER); 1462 if (DC_IS_INTEL(sc)) { 1463 DC_CLRBIT(sc, DC_SIARESET, DC_SIA_RESET); 1464 DC_CLRBIT(sc, DC_10BTCTRL, 0xFFFF); 1465 if ((media & IFM_GMASK) == IFM_FDX) 1466 DC_SETBIT(sc, DC_10BTCTRL, 0x7F3D); 1467 else 1468 DC_SETBIT(sc, DC_10BTCTRL, 0x7F3F); 1469 DC_SETBIT(sc, DC_SIARESET, DC_SIA_RESET); 1470 DC_CLRBIT(sc, DC_10BTCTRL, 1471 DC_TCTL_AUTONEGENBL); 1472 DELAY(20000); 1473 } 1474 } 1475 } 1476 1477 /* 1478 * If this is a Davicom DM9102A card with a DM9801 HomePNA 1479 * PHY and we want HomePNA mode, set the portsel bit to turn 1480 * on the external MII port. 1481 */ 1482 if (DC_IS_DAVICOM(sc)) { 1483 if (IFM_SUBTYPE(media) == IFM_HPNA_1) { 1484 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL); 1485 sc->dc_link = 1; 1486 } else { 1487 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL); 1488 } 1489 } 1490 1491 if ((media & IFM_GMASK) == IFM_FDX) { 1492 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_FULLDUPLEX); 1493 if (sc->dc_pmode == DC_PMODE_SYM && DC_IS_PNIC(sc)) 1494 DC_SETBIT(sc, DC_PN_NWAY, DC_PN_NWAY_DUPLEX); 1495 } else { 1496 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_FULLDUPLEX); 1497 if (sc->dc_pmode == DC_PMODE_SYM && DC_IS_PNIC(sc)) 1498 DC_CLRBIT(sc, DC_PN_NWAY, DC_PN_NWAY_DUPLEX); 1499 } 1500 1501 if (restart) 1502 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_TX_ON | DC_NETCFG_RX_ON); 1503 } 1504 1505 static void 1506 dc_reset(struct dc_softc *sc) 1507 { 1508 int i; 1509 1510 DC_SETBIT(sc, DC_BUSCTL, DC_BUSCTL_RESET); 1511 1512 for (i = 0; i < DC_TIMEOUT; i++) { 1513 DELAY(10); 1514 if (!(CSR_READ_4(sc, DC_BUSCTL) & DC_BUSCTL_RESET)) 1515 break; 1516 } 1517 1518 if (DC_IS_ASIX(sc) || DC_IS_ADMTEK(sc) || DC_IS_CONEXANT(sc) || 1519 DC_IS_XIRCOM(sc) || DC_IS_INTEL(sc) || DC_IS_ULI(sc)) { 1520 DELAY(10000); 1521 DC_CLRBIT(sc, DC_BUSCTL, DC_BUSCTL_RESET); 1522 i = 0; 1523 } 1524 1525 if (i == DC_TIMEOUT) 1526 device_printf(sc->dc_dev, "reset never completed!\n"); 1527 1528 /* Wait a little while for the chip to get its brains in order. */ 1529 DELAY(1000); 1530 1531 CSR_WRITE_4(sc, DC_IMR, 0x00000000); 1532 CSR_WRITE_4(sc, DC_BUSCTL, 0x00000000); 1533 CSR_WRITE_4(sc, DC_NETCFG, 0x00000000); 1534 1535 /* 1536 * Bring the SIA out of reset. In some cases, it looks 1537 * like failing to unreset the SIA soon enough gets it 1538 * into a state where it will never come out of reset 1539 * until we reset the whole chip again. 1540 */ 1541 if (DC_IS_INTEL(sc)) { 1542 DC_SETBIT(sc, DC_SIARESET, DC_SIA_RESET); 1543 CSR_WRITE_4(sc, DC_10BTCTRL, 0xFFFFFFFF); 1544 CSR_WRITE_4(sc, DC_WATCHDOG, 0); 1545 } 1546 } 1547 1548 static const struct dc_type * 1549 dc_devtype(device_t dev) 1550 { 1551 const struct dc_type *t; 1552 uint32_t devid; 1553 uint8_t rev; 1554 1555 t = dc_devs; 1556 devid = pci_get_devid(dev); 1557 rev = pci_get_revid(dev); 1558 1559 while (t->dc_name != NULL) { 1560 if (devid == t->dc_devid && rev >= t->dc_minrev) 1561 return (t); 1562 t++; 1563 } 1564 1565 return (NULL); 1566 } 1567 1568 /* 1569 * Probe for a 21143 or clone chip. Check the PCI vendor and device 1570 * IDs against our list and return a device name if we find a match. 1571 * We do a little bit of extra work to identify the exact type of 1572 * chip. The MX98713 and MX98713A have the same PCI vendor/device ID, 1573 * but different revision IDs. The same is true for 98715/98715A 1574 * chips and the 98725, as well as the ASIX and ADMtek chips. In some 1575 * cases, the exact chip revision affects driver behavior. 1576 */ 1577 static int 1578 dc_probe(device_t dev) 1579 { 1580 const struct dc_type *t; 1581 1582 t = dc_devtype(dev); 1583 1584 if (t != NULL) { 1585 device_set_desc(dev, t->dc_name); 1586 return (BUS_PROBE_DEFAULT); 1587 } 1588 1589 return (ENXIO); 1590 } 1591 1592 static void 1593 dc_apply_fixup(struct dc_softc *sc, int media) 1594 { 1595 struct dc_mediainfo *m; 1596 uint8_t *p; 1597 int i; 1598 uint32_t reg; 1599 1600 m = sc->dc_mi; 1601 1602 while (m != NULL) { 1603 if (m->dc_media == media) 1604 break; 1605 m = m->dc_next; 1606 } 1607 1608 if (m == NULL) 1609 return; 1610 1611 for (i = 0, p = m->dc_reset_ptr; i < m->dc_reset_len; i++, p += 2) { 1612 reg = (p[0] | (p[1] << 8)) << 16; 1613 CSR_WRITE_4(sc, DC_WATCHDOG, reg); 1614 } 1615 1616 for (i = 0, p = m->dc_gp_ptr; i < m->dc_gp_len; i++, p += 2) { 1617 reg = (p[0] | (p[1] << 8)) << 16; 1618 CSR_WRITE_4(sc, DC_WATCHDOG, reg); 1619 } 1620 } 1621 1622 static int 1623 dc_decode_leaf_sia(struct dc_softc *sc, struct dc_eblock_sia *l) 1624 { 1625 struct dc_mediainfo *m; 1626 1627 m = malloc(sizeof(struct dc_mediainfo), M_DEVBUF, M_NOWAIT | M_ZERO); 1628 if (m == NULL) { 1629 device_printf(sc->dc_dev, "Could not allocate mediainfo\n"); 1630 return (ENOMEM); 1631 } 1632 switch (l->dc_sia_code & ~DC_SIA_CODE_EXT) { 1633 case DC_SIA_CODE_10BT: 1634 m->dc_media = IFM_10_T; 1635 break; 1636 case DC_SIA_CODE_10BT_FDX: 1637 m->dc_media = IFM_10_T | IFM_FDX; 1638 break; 1639 case DC_SIA_CODE_10B2: 1640 m->dc_media = IFM_10_2; 1641 break; 1642 case DC_SIA_CODE_10B5: 1643 m->dc_media = IFM_10_5; 1644 break; 1645 default: 1646 break; 1647 } 1648 1649 /* 1650 * We need to ignore CSR13, CSR14, CSR15 for SIA mode. 1651 * Things apparently already work for cards that do 1652 * supply Media Specific Data. 1653 */ 1654 if (l->dc_sia_code & DC_SIA_CODE_EXT) { 1655 m->dc_gp_len = 2; 1656 m->dc_gp_ptr = 1657 (uint8_t *)&l->dc_un.dc_sia_ext.dc_sia_gpio_ctl; 1658 } else { 1659 m->dc_gp_len = 2; 1660 m->dc_gp_ptr = 1661 (uint8_t *)&l->dc_un.dc_sia_noext.dc_sia_gpio_ctl; 1662 } 1663 1664 m->dc_next = sc->dc_mi; 1665 sc->dc_mi = m; 1666 1667 sc->dc_pmode = DC_PMODE_SIA; 1668 return (0); 1669 } 1670 1671 static int 1672 dc_decode_leaf_sym(struct dc_softc *sc, struct dc_eblock_sym *l) 1673 { 1674 struct dc_mediainfo *m; 1675 1676 m = malloc(sizeof(struct dc_mediainfo), M_DEVBUF, M_NOWAIT | M_ZERO); 1677 if (m == NULL) { 1678 device_printf(sc->dc_dev, "Could not allocate mediainfo\n"); 1679 return (ENOMEM); 1680 } 1681 if (l->dc_sym_code == DC_SYM_CODE_100BT) 1682 m->dc_media = IFM_100_TX; 1683 1684 if (l->dc_sym_code == DC_SYM_CODE_100BT_FDX) 1685 m->dc_media = IFM_100_TX | IFM_FDX; 1686 1687 m->dc_gp_len = 2; 1688 m->dc_gp_ptr = (uint8_t *)&l->dc_sym_gpio_ctl; 1689 1690 m->dc_next = sc->dc_mi; 1691 sc->dc_mi = m; 1692 1693 sc->dc_pmode = DC_PMODE_SYM; 1694 return (0); 1695 } 1696 1697 static int 1698 dc_decode_leaf_mii(struct dc_softc *sc, struct dc_eblock_mii *l) 1699 { 1700 struct dc_mediainfo *m; 1701 uint8_t *p; 1702 1703 m = malloc(sizeof(struct dc_mediainfo), M_DEVBUF, M_NOWAIT | M_ZERO); 1704 if (m == NULL) { 1705 device_printf(sc->dc_dev, "Could not allocate mediainfo\n"); 1706 return (ENOMEM); 1707 } 1708 /* We abuse IFM_AUTO to represent MII. */ 1709 m->dc_media = IFM_AUTO; 1710 m->dc_gp_len = l->dc_gpr_len; 1711 1712 p = (uint8_t *)l; 1713 p += sizeof(struct dc_eblock_mii); 1714 m->dc_gp_ptr = p; 1715 p += 2 * l->dc_gpr_len; 1716 m->dc_reset_len = *p; 1717 p++; 1718 m->dc_reset_ptr = p; 1719 1720 m->dc_next = sc->dc_mi; 1721 sc->dc_mi = m; 1722 return (0); 1723 } 1724 1725 static int 1726 dc_read_srom(struct dc_softc *sc, int bits) 1727 { 1728 int size; 1729 1730 size = DC_ROM_SIZE(bits); 1731 sc->dc_srom = malloc(size, M_DEVBUF, M_NOWAIT | M_ZERO); 1732 if (sc->dc_srom == NULL) { 1733 device_printf(sc->dc_dev, "Could not allocate SROM buffer\n"); 1734 return (ENOMEM); 1735 } 1736 dc_read_eeprom(sc, (caddr_t)sc->dc_srom, 0, (size / 2), 0); 1737 return (0); 1738 } 1739 1740 static int 1741 dc_parse_21143_srom(struct dc_softc *sc) 1742 { 1743 struct dc_leaf_hdr *lhdr; 1744 struct dc_eblock_hdr *hdr; 1745 int error, have_mii, i, loff; 1746 char *ptr; 1747 1748 have_mii = 0; 1749 loff = sc->dc_srom[27]; 1750 lhdr = (struct dc_leaf_hdr *)&(sc->dc_srom[loff]); 1751 1752 ptr = (char *)lhdr; 1753 ptr += sizeof(struct dc_leaf_hdr) - 1; 1754 /* 1755 * Look if we got a MII media block. 1756 */ 1757 for (i = 0; i < lhdr->dc_mcnt; i++) { 1758 hdr = (struct dc_eblock_hdr *)ptr; 1759 if (hdr->dc_type == DC_EBLOCK_MII) 1760 have_mii++; 1761 1762 ptr += (hdr->dc_len & 0x7F); 1763 ptr++; 1764 } 1765 1766 /* 1767 * Do the same thing again. Only use SIA and SYM media 1768 * blocks if no MII media block is available. 1769 */ 1770 ptr = (char *)lhdr; 1771 ptr += sizeof(struct dc_leaf_hdr) - 1; 1772 error = 0; 1773 for (i = 0; i < lhdr->dc_mcnt; i++) { 1774 hdr = (struct dc_eblock_hdr *)ptr; 1775 switch (hdr->dc_type) { 1776 case DC_EBLOCK_MII: 1777 error = dc_decode_leaf_mii(sc, (struct dc_eblock_mii *)hdr); 1778 break; 1779 case DC_EBLOCK_SIA: 1780 if (! have_mii) 1781 error = dc_decode_leaf_sia(sc, 1782 (struct dc_eblock_sia *)hdr); 1783 break; 1784 case DC_EBLOCK_SYM: 1785 if (! have_mii) 1786 error = dc_decode_leaf_sym(sc, 1787 (struct dc_eblock_sym *)hdr); 1788 break; 1789 default: 1790 /* Don't care. Yet. */ 1791 break; 1792 } 1793 ptr += (hdr->dc_len & 0x7F); 1794 ptr++; 1795 } 1796 return (error); 1797 } 1798 1799 static void 1800 dc_dma_map_addr(void *arg, bus_dma_segment_t *segs, int nseg, int error) 1801 { 1802 bus_addr_t *paddr; 1803 1804 KASSERT(nseg == 1, 1805 ("%s: wrong number of segments (%d)", __func__, nseg)); 1806 paddr = arg; 1807 *paddr = segs->ds_addr; 1808 } 1809 1810 static int 1811 dc_dma_alloc(struct dc_softc *sc) 1812 { 1813 int error, i; 1814 1815 error = bus_dma_tag_create(bus_get_dma_tag(sc->dc_dev), 1, 0, 1816 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL, 1817 BUS_SPACE_MAXSIZE_32BIT, 0, BUS_SPACE_MAXSIZE_32BIT, 0, 1818 NULL, NULL, &sc->dc_ptag); 1819 if (error) { 1820 device_printf(sc->dc_dev, 1821 "failed to allocate parent DMA tag\n"); 1822 goto fail; 1823 } 1824 1825 /* Allocate a busdma tag and DMA safe memory for TX/RX descriptors. */ 1826 error = bus_dma_tag_create(sc->dc_ptag, DC_LIST_ALIGN, 0, 1827 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL, DC_RX_LIST_SZ, 1, 1828 DC_RX_LIST_SZ, 0, NULL, NULL, &sc->dc_rx_ltag); 1829 if (error) { 1830 device_printf(sc->dc_dev, "failed to create RX list DMA tag\n"); 1831 goto fail; 1832 } 1833 1834 error = bus_dma_tag_create(sc->dc_ptag, DC_LIST_ALIGN, 0, 1835 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL, DC_TX_LIST_SZ, 1, 1836 DC_TX_LIST_SZ, 0, NULL, NULL, &sc->dc_tx_ltag); 1837 if (error) { 1838 device_printf(sc->dc_dev, "failed to create TX list DMA tag\n"); 1839 goto fail; 1840 } 1841 1842 /* RX descriptor list. */ 1843 error = bus_dmamem_alloc(sc->dc_rx_ltag, 1844 (void **)&sc->dc_ldata.dc_rx_list, BUS_DMA_NOWAIT | 1845 BUS_DMA_ZERO | BUS_DMA_COHERENT, &sc->dc_rx_lmap); 1846 if (error) { 1847 device_printf(sc->dc_dev, 1848 "failed to allocate DMA'able memory for RX list\n"); 1849 goto fail; 1850 } 1851 error = bus_dmamap_load(sc->dc_rx_ltag, sc->dc_rx_lmap, 1852 sc->dc_ldata.dc_rx_list, DC_RX_LIST_SZ, dc_dma_map_addr, 1853 &sc->dc_ldata.dc_rx_list_paddr, BUS_DMA_NOWAIT); 1854 if (error) { 1855 device_printf(sc->dc_dev, 1856 "failed to load DMA'able memory for RX list\n"); 1857 goto fail; 1858 } 1859 /* TX descriptor list. */ 1860 error = bus_dmamem_alloc(sc->dc_tx_ltag, 1861 (void **)&sc->dc_ldata.dc_tx_list, BUS_DMA_NOWAIT | 1862 BUS_DMA_ZERO | BUS_DMA_COHERENT, &sc->dc_tx_lmap); 1863 if (error) { 1864 device_printf(sc->dc_dev, 1865 "failed to allocate DMA'able memory for TX list\n"); 1866 goto fail; 1867 } 1868 error = bus_dmamap_load(sc->dc_tx_ltag, sc->dc_tx_lmap, 1869 sc->dc_ldata.dc_tx_list, DC_TX_LIST_SZ, dc_dma_map_addr, 1870 &sc->dc_ldata.dc_tx_list_paddr, BUS_DMA_NOWAIT); 1871 if (error) { 1872 device_printf(sc->dc_dev, 1873 "cannot load DMA'able memory for TX list\n"); 1874 goto fail; 1875 } 1876 1877 /* 1878 * Allocate a busdma tag and DMA safe memory for the multicast 1879 * setup frame. 1880 */ 1881 error = bus_dma_tag_create(sc->dc_ptag, DC_LIST_ALIGN, 0, 1882 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL, 1883 DC_SFRAME_LEN + DC_MIN_FRAMELEN, 1, DC_SFRAME_LEN + DC_MIN_FRAMELEN, 1884 0, NULL, NULL, &sc->dc_stag); 1885 if (error) { 1886 device_printf(sc->dc_dev, 1887 "failed to create DMA tag for setup frame\n"); 1888 goto fail; 1889 } 1890 error = bus_dmamem_alloc(sc->dc_stag, (void **)&sc->dc_cdata.dc_sbuf, 1891 BUS_DMA_NOWAIT, &sc->dc_smap); 1892 if (error) { 1893 device_printf(sc->dc_dev, 1894 "failed to allocate DMA'able memory for setup frame\n"); 1895 goto fail; 1896 } 1897 error = bus_dmamap_load(sc->dc_stag, sc->dc_smap, sc->dc_cdata.dc_sbuf, 1898 DC_SFRAME_LEN, dc_dma_map_addr, &sc->dc_saddr, BUS_DMA_NOWAIT); 1899 if (error) { 1900 device_printf(sc->dc_dev, 1901 "cannot load DMA'able memory for setup frame\n"); 1902 goto fail; 1903 } 1904 1905 /* Allocate a busdma tag for RX mbufs. */ 1906 error = bus_dma_tag_create(sc->dc_ptag, DC_RXBUF_ALIGN, 0, 1907 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL, 1908 MCLBYTES, 1, MCLBYTES, 0, NULL, NULL, &sc->dc_rx_mtag); 1909 if (error) { 1910 device_printf(sc->dc_dev, "failed to create RX mbuf tag\n"); 1911 goto fail; 1912 } 1913 1914 /* Allocate a busdma tag for TX mbufs. */ 1915 error = bus_dma_tag_create(sc->dc_ptag, 1, 0, 1916 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL, 1917 MCLBYTES * DC_MAXFRAGS, DC_MAXFRAGS, MCLBYTES, 1918 0, NULL, NULL, &sc->dc_tx_mtag); 1919 if (error) { 1920 device_printf(sc->dc_dev, "failed to create TX mbuf tag\n"); 1921 goto fail; 1922 } 1923 1924 /* Create the TX/RX busdma maps. */ 1925 for (i = 0; i < DC_TX_LIST_CNT; i++) { 1926 error = bus_dmamap_create(sc->dc_tx_mtag, 0, 1927 &sc->dc_cdata.dc_tx_map[i]); 1928 if (error) { 1929 device_printf(sc->dc_dev, 1930 "failed to create TX mbuf dmamap\n"); 1931 goto fail; 1932 } 1933 } 1934 for (i = 0; i < DC_RX_LIST_CNT; i++) { 1935 error = bus_dmamap_create(sc->dc_rx_mtag, 0, 1936 &sc->dc_cdata.dc_rx_map[i]); 1937 if (error) { 1938 device_printf(sc->dc_dev, 1939 "failed to create RX mbuf dmamap\n"); 1940 goto fail; 1941 } 1942 } 1943 error = bus_dmamap_create(sc->dc_rx_mtag, 0, &sc->dc_sparemap); 1944 if (error) { 1945 device_printf(sc->dc_dev, 1946 "failed to create spare RX mbuf dmamap\n"); 1947 goto fail; 1948 } 1949 1950 fail: 1951 return (error); 1952 } 1953 1954 static void 1955 dc_dma_free(struct dc_softc *sc) 1956 { 1957 int i; 1958 1959 /* RX buffers. */ 1960 if (sc->dc_rx_mtag != NULL) { 1961 for (i = 0; i < DC_RX_LIST_CNT; i++) { 1962 if (sc->dc_cdata.dc_rx_map[i] != NULL) 1963 bus_dmamap_destroy(sc->dc_rx_mtag, 1964 sc->dc_cdata.dc_rx_map[i]); 1965 } 1966 if (sc->dc_sparemap != NULL) 1967 bus_dmamap_destroy(sc->dc_rx_mtag, sc->dc_sparemap); 1968 bus_dma_tag_destroy(sc->dc_rx_mtag); 1969 } 1970 1971 /* TX buffers. */ 1972 if (sc->dc_rx_mtag != NULL) { 1973 for (i = 0; i < DC_TX_LIST_CNT; i++) { 1974 if (sc->dc_cdata.dc_tx_map[i] != NULL) 1975 bus_dmamap_destroy(sc->dc_tx_mtag, 1976 sc->dc_cdata.dc_tx_map[i]); 1977 } 1978 bus_dma_tag_destroy(sc->dc_tx_mtag); 1979 } 1980 1981 /* RX descriptor list. */ 1982 if (sc->dc_rx_ltag) { 1983 if (sc->dc_rx_lmap != NULL) 1984 bus_dmamap_unload(sc->dc_rx_ltag, sc->dc_rx_lmap); 1985 if (sc->dc_rx_lmap != NULL && sc->dc_ldata.dc_rx_list != NULL) 1986 bus_dmamem_free(sc->dc_rx_ltag, sc->dc_ldata.dc_rx_list, 1987 sc->dc_rx_lmap); 1988 bus_dma_tag_destroy(sc->dc_rx_ltag); 1989 } 1990 1991 /* TX descriptor list. */ 1992 if (sc->dc_tx_ltag) { 1993 if (sc->dc_tx_lmap != NULL) 1994 bus_dmamap_unload(sc->dc_tx_ltag, sc->dc_tx_lmap); 1995 if (sc->dc_tx_lmap != NULL && sc->dc_ldata.dc_tx_list != NULL) 1996 bus_dmamem_free(sc->dc_tx_ltag, sc->dc_ldata.dc_tx_list, 1997 sc->dc_tx_lmap); 1998 bus_dma_tag_destroy(sc->dc_tx_ltag); 1999 } 2000 2001 /* multicast setup frame. */ 2002 if (sc->dc_stag) { 2003 if (sc->dc_smap != NULL) 2004 bus_dmamap_unload(sc->dc_stag, sc->dc_smap); 2005 if (sc->dc_smap != NULL && sc->dc_cdata.dc_sbuf != NULL) 2006 bus_dmamem_free(sc->dc_stag, sc->dc_cdata.dc_sbuf, 2007 sc->dc_smap); 2008 bus_dma_tag_destroy(sc->dc_stag); 2009 } 2010 } 2011 2012 /* 2013 * Attach the interface. Allocate softc structures, do ifmedia 2014 * setup and ethernet/BPF attach. 2015 */ 2016 static int 2017 dc_attach(device_t dev) 2018 { 2019 uint32_t eaddr[(ETHER_ADDR_LEN+3)/4]; 2020 uint32_t command; 2021 struct dc_softc *sc; 2022 struct ifnet *ifp; 2023 struct dc_mediainfo *m; 2024 uint32_t reg, revision; 2025 uint16_t *srom; 2026 int error, mac_offset, n, phy, rid, tmp; 2027 uint8_t *mac; 2028 2029 sc = device_get_softc(dev); 2030 sc->dc_dev = dev; 2031 2032 mtx_init(&sc->dc_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 2033 MTX_DEF); 2034 2035 /* 2036 * Map control/status registers. 2037 */ 2038 pci_enable_busmaster(dev); 2039 2040 rid = DC_RID; 2041 sc->dc_res = bus_alloc_resource_any(dev, DC_RES, &rid, RF_ACTIVE); 2042 2043 if (sc->dc_res == NULL) { 2044 device_printf(dev, "couldn't map ports/memory\n"); 2045 error = ENXIO; 2046 goto fail; 2047 } 2048 2049 sc->dc_btag = rman_get_bustag(sc->dc_res); 2050 sc->dc_bhandle = rman_get_bushandle(sc->dc_res); 2051 2052 /* Allocate interrupt. */ 2053 rid = 0; 2054 sc->dc_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 2055 RF_SHAREABLE | RF_ACTIVE); 2056 2057 if (sc->dc_irq == NULL) { 2058 device_printf(dev, "couldn't map interrupt\n"); 2059 error = ENXIO; 2060 goto fail; 2061 } 2062 2063 /* Need this info to decide on a chip type. */ 2064 sc->dc_info = dc_devtype(dev); 2065 revision = pci_get_revid(dev); 2066 2067 error = 0; 2068 /* Get the eeprom width, but PNIC and XIRCOM have diff eeprom */ 2069 if (sc->dc_info->dc_devid != 2070 DC_DEVID(DC_VENDORID_LO, DC_DEVICEID_82C168) && 2071 sc->dc_info->dc_devid != 2072 DC_DEVID(DC_VENDORID_XIRCOM, DC_DEVICEID_X3201)) 2073 dc_eeprom_width(sc); 2074 2075 switch (sc->dc_info->dc_devid) { 2076 case DC_DEVID(DC_VENDORID_DEC, DC_DEVICEID_21143): 2077 sc->dc_type = DC_TYPE_21143; 2078 sc->dc_flags |= DC_TX_POLL | DC_TX_USE_TX_INTR; 2079 sc->dc_flags |= DC_REDUCED_MII_POLL; 2080 /* Save EEPROM contents so we can parse them later. */ 2081 error = dc_read_srom(sc, sc->dc_romwidth); 2082 if (error != 0) 2083 goto fail; 2084 break; 2085 case DC_DEVID(DC_VENDORID_DAVICOM, DC_DEVICEID_DM9009): 2086 case DC_DEVID(DC_VENDORID_DAVICOM, DC_DEVICEID_DM9100): 2087 case DC_DEVID(DC_VENDORID_DAVICOM, DC_DEVICEID_DM9102): 2088 sc->dc_type = DC_TYPE_DM9102; 2089 sc->dc_flags |= DC_TX_COALESCE | DC_TX_INTR_ALWAYS; 2090 sc->dc_flags |= DC_REDUCED_MII_POLL | DC_TX_STORENFWD; 2091 sc->dc_flags |= DC_TX_ALIGN; 2092 sc->dc_pmode = DC_PMODE_MII; 2093 2094 /* Increase the latency timer value. */ 2095 pci_write_config(dev, PCIR_LATTIMER, 0x80, 1); 2096 break; 2097 case DC_DEVID(DC_VENDORID_ADMTEK, DC_DEVICEID_AL981): 2098 sc->dc_type = DC_TYPE_AL981; 2099 sc->dc_flags |= DC_TX_USE_TX_INTR; 2100 sc->dc_flags |= DC_TX_ADMTEK_WAR; 2101 sc->dc_pmode = DC_PMODE_MII; 2102 error = dc_read_srom(sc, sc->dc_romwidth); 2103 if (error != 0) 2104 goto fail; 2105 break; 2106 case DC_DEVID(DC_VENDORID_ADMTEK, DC_DEVICEID_AN983): 2107 case DC_DEVID(DC_VENDORID_ADMTEK, DC_DEVICEID_AN985): 2108 case DC_DEVID(DC_VENDORID_ADMTEK, DC_DEVICEID_ADM9511): 2109 case DC_DEVID(DC_VENDORID_ADMTEK, DC_DEVICEID_ADM9513): 2110 case DC_DEVID(DC_VENDORID_DLINK, DC_DEVICEID_DRP32TXD): 2111 case DC_DEVID(DC_VENDORID_ABOCOM, DC_DEVICEID_FE2500): 2112 case DC_DEVID(DC_VENDORID_ABOCOM, DC_DEVICEID_FE2500MX): 2113 case DC_DEVID(DC_VENDORID_ACCTON, DC_DEVICEID_EN2242): 2114 case DC_DEVID(DC_VENDORID_HAWKING, DC_DEVICEID_HAWKING_PN672TX): 2115 case DC_DEVID(DC_VENDORID_PLANEX, DC_DEVICEID_FNW3602T): 2116 case DC_DEVID(DC_VENDORID_3COM, DC_DEVICEID_3CSOHOB): 2117 case DC_DEVID(DC_VENDORID_MICROSOFT, DC_DEVICEID_MSMN120): 2118 case DC_DEVID(DC_VENDORID_MICROSOFT, DC_DEVICEID_MSMN130): 2119 case DC_DEVID(DC_VENDORID_LINKSYS, DC_DEVICEID_PCMPC200_AB08): 2120 case DC_DEVID(DC_VENDORID_LINKSYS, DC_DEVICEID_PCMPC200_AB09): 2121 sc->dc_type = DC_TYPE_AN983; 2122 sc->dc_flags |= DC_64BIT_HASH; 2123 sc->dc_flags |= DC_TX_USE_TX_INTR; 2124 sc->dc_flags |= DC_TX_ADMTEK_WAR; 2125 sc->dc_pmode = DC_PMODE_MII; 2126 /* Don't read SROM for - auto-loaded on reset */ 2127 break; 2128 case DC_DEVID(DC_VENDORID_MX, DC_DEVICEID_98713): 2129 case DC_DEVID(DC_VENDORID_CP, DC_DEVICEID_98713_CP): 2130 if (revision < DC_REVISION_98713A) { 2131 sc->dc_type = DC_TYPE_98713; 2132 } 2133 if (revision >= DC_REVISION_98713A) { 2134 sc->dc_type = DC_TYPE_98713A; 2135 sc->dc_flags |= DC_21143_NWAY; 2136 } 2137 sc->dc_flags |= DC_REDUCED_MII_POLL; 2138 sc->dc_flags |= DC_TX_POLL | DC_TX_USE_TX_INTR; 2139 break; 2140 case DC_DEVID(DC_VENDORID_MX, DC_DEVICEID_987x5): 2141 case DC_DEVID(DC_VENDORID_ACCTON, DC_DEVICEID_EN1217): 2142 /* 2143 * Macronix MX98715AEC-C/D/E parts have only a 2144 * 128-bit hash table. We need to deal with these 2145 * in the same manner as the PNIC II so that we 2146 * get the right number of bits out of the 2147 * CRC routine. 2148 */ 2149 if (revision >= DC_REVISION_98715AEC_C && 2150 revision < DC_REVISION_98725) 2151 sc->dc_flags |= DC_128BIT_HASH; 2152 sc->dc_type = DC_TYPE_987x5; 2153 sc->dc_flags |= DC_TX_POLL | DC_TX_USE_TX_INTR; 2154 sc->dc_flags |= DC_REDUCED_MII_POLL | DC_21143_NWAY; 2155 break; 2156 case DC_DEVID(DC_VENDORID_MX, DC_DEVICEID_98727): 2157 sc->dc_type = DC_TYPE_987x5; 2158 sc->dc_flags |= DC_TX_POLL | DC_TX_USE_TX_INTR; 2159 sc->dc_flags |= DC_REDUCED_MII_POLL | DC_21143_NWAY; 2160 break; 2161 case DC_DEVID(DC_VENDORID_LO, DC_DEVICEID_82C115): 2162 sc->dc_type = DC_TYPE_PNICII; 2163 sc->dc_flags |= DC_TX_POLL | DC_TX_USE_TX_INTR | DC_128BIT_HASH; 2164 sc->dc_flags |= DC_REDUCED_MII_POLL | DC_21143_NWAY; 2165 break; 2166 case DC_DEVID(DC_VENDORID_LO, DC_DEVICEID_82C168): 2167 sc->dc_type = DC_TYPE_PNIC; 2168 sc->dc_flags |= DC_TX_STORENFWD | DC_TX_INTR_ALWAYS; 2169 sc->dc_flags |= DC_PNIC_RX_BUG_WAR; 2170 sc->dc_pnic_rx_buf = malloc(DC_RXLEN * 5, M_DEVBUF, M_NOWAIT); 2171 if (sc->dc_pnic_rx_buf == NULL) { 2172 device_printf(sc->dc_dev, 2173 "Could not allocate PNIC RX buffer\n"); 2174 error = ENOMEM; 2175 goto fail; 2176 } 2177 if (revision < DC_REVISION_82C169) 2178 sc->dc_pmode = DC_PMODE_SYM; 2179 break; 2180 case DC_DEVID(DC_VENDORID_ASIX, DC_DEVICEID_AX88140A): 2181 sc->dc_type = DC_TYPE_ASIX; 2182 sc->dc_flags |= DC_TX_USE_TX_INTR | DC_TX_INTR_FIRSTFRAG; 2183 sc->dc_flags |= DC_REDUCED_MII_POLL; 2184 sc->dc_pmode = DC_PMODE_MII; 2185 break; 2186 case DC_DEVID(DC_VENDORID_XIRCOM, DC_DEVICEID_X3201): 2187 sc->dc_type = DC_TYPE_XIRCOM; 2188 sc->dc_flags |= DC_TX_INTR_ALWAYS | DC_TX_COALESCE | 2189 DC_TX_ALIGN; 2190 /* 2191 * We don't actually need to coalesce, but we're doing 2192 * it to obtain a double word aligned buffer. 2193 * The DC_TX_COALESCE flag is required. 2194 */ 2195 sc->dc_pmode = DC_PMODE_MII; 2196 break; 2197 case DC_DEVID(DC_VENDORID_CONEXANT, DC_DEVICEID_RS7112): 2198 sc->dc_type = DC_TYPE_CONEXANT; 2199 sc->dc_flags |= DC_TX_INTR_ALWAYS; 2200 sc->dc_flags |= DC_REDUCED_MII_POLL; 2201 sc->dc_pmode = DC_PMODE_MII; 2202 error = dc_read_srom(sc, sc->dc_romwidth); 2203 if (error != 0) 2204 goto fail; 2205 break; 2206 case DC_DEVID(DC_VENDORID_ULI, DC_DEVICEID_M5261): 2207 case DC_DEVID(DC_VENDORID_ULI, DC_DEVICEID_M5263): 2208 if (sc->dc_info->dc_devid == 2209 DC_DEVID(DC_VENDORID_ULI, DC_DEVICEID_M5261)) 2210 sc->dc_type = DC_TYPE_ULI_M5261; 2211 else 2212 sc->dc_type = DC_TYPE_ULI_M5263; 2213 /* TX buffers should be aligned on 4 byte boundary. */ 2214 sc->dc_flags |= DC_TX_INTR_ALWAYS | DC_TX_COALESCE | 2215 DC_TX_ALIGN; 2216 sc->dc_pmode = DC_PMODE_MII; 2217 error = dc_read_srom(sc, sc->dc_romwidth); 2218 if (error != 0) 2219 goto fail; 2220 break; 2221 default: 2222 device_printf(dev, "unknown device: %x\n", 2223 sc->dc_info->dc_devid); 2224 break; 2225 } 2226 2227 /* Save the cache line size. */ 2228 if (DC_IS_DAVICOM(sc)) 2229 sc->dc_cachesize = 0; 2230 else 2231 sc->dc_cachesize = pci_get_cachelnsz(dev); 2232 2233 /* Reset the adapter. */ 2234 dc_reset(sc); 2235 2236 /* Take 21143 out of snooze mode */ 2237 if (DC_IS_INTEL(sc) || DC_IS_XIRCOM(sc)) { 2238 command = pci_read_config(dev, DC_PCI_CFDD, 4); 2239 command &= ~(DC_CFDD_SNOOZE_MODE | DC_CFDD_SLEEP_MODE); 2240 pci_write_config(dev, DC_PCI_CFDD, command, 4); 2241 } 2242 2243 /* 2244 * Try to learn something about the supported media. 2245 * We know that ASIX and ADMtek and Davicom devices 2246 * will *always* be using MII media, so that's a no-brainer. 2247 * The tricky ones are the Macronix/PNIC II and the 2248 * Intel 21143. 2249 */ 2250 if (DC_IS_INTEL(sc)) { 2251 error = dc_parse_21143_srom(sc); 2252 if (error != 0) 2253 goto fail; 2254 } else if (DC_IS_MACRONIX(sc) || DC_IS_PNICII(sc)) { 2255 if (sc->dc_type == DC_TYPE_98713) 2256 sc->dc_pmode = DC_PMODE_MII; 2257 else 2258 sc->dc_pmode = DC_PMODE_SYM; 2259 } else if (!sc->dc_pmode) 2260 sc->dc_pmode = DC_PMODE_MII; 2261 2262 /* 2263 * Get station address from the EEPROM. 2264 */ 2265 switch(sc->dc_type) { 2266 case DC_TYPE_98713: 2267 case DC_TYPE_98713A: 2268 case DC_TYPE_987x5: 2269 case DC_TYPE_PNICII: 2270 dc_read_eeprom(sc, (caddr_t)&mac_offset, 2271 (DC_EE_NODEADDR_OFFSET / 2), 1, 0); 2272 dc_read_eeprom(sc, (caddr_t)&eaddr, (mac_offset / 2), 3, 0); 2273 break; 2274 case DC_TYPE_PNIC: 2275 dc_read_eeprom(sc, (caddr_t)&eaddr, 0, 3, 1); 2276 break; 2277 case DC_TYPE_DM9102: 2278 dc_read_eeprom(sc, (caddr_t)&eaddr, DC_EE_NODEADDR, 3, 0); 2279 #ifdef __sparc64__ 2280 /* 2281 * If this is an onboard dc(4) the station address read from 2282 * the EEPROM is all zero and we have to get it from the FCode. 2283 */ 2284 if (eaddr[0] == 0 && (eaddr[1] & ~0xffff) == 0) 2285 OF_getetheraddr(dev, (caddr_t)&eaddr); 2286 #endif 2287 break; 2288 case DC_TYPE_21143: 2289 case DC_TYPE_ASIX: 2290 dc_read_eeprom(sc, (caddr_t)&eaddr, DC_EE_NODEADDR, 3, 0); 2291 break; 2292 case DC_TYPE_AL981: 2293 case DC_TYPE_AN983: 2294 reg = CSR_READ_4(sc, DC_AL_PAR0); 2295 mac = (uint8_t *)&eaddr[0]; 2296 mac[0] = (reg >> 0) & 0xff; 2297 mac[1] = (reg >> 8) & 0xff; 2298 mac[2] = (reg >> 16) & 0xff; 2299 mac[3] = (reg >> 24) & 0xff; 2300 reg = CSR_READ_4(sc, DC_AL_PAR1); 2301 mac[4] = (reg >> 0) & 0xff; 2302 mac[5] = (reg >> 8) & 0xff; 2303 break; 2304 case DC_TYPE_CONEXANT: 2305 bcopy(sc->dc_srom + DC_CONEXANT_EE_NODEADDR, &eaddr, 2306 ETHER_ADDR_LEN); 2307 break; 2308 case DC_TYPE_XIRCOM: 2309 /* The MAC comes from the CIS. */ 2310 mac = pci_get_ether(dev); 2311 if (!mac) { 2312 device_printf(dev, "No station address in CIS!\n"); 2313 error = ENXIO; 2314 goto fail; 2315 } 2316 bcopy(mac, eaddr, ETHER_ADDR_LEN); 2317 break; 2318 case DC_TYPE_ULI_M5261: 2319 case DC_TYPE_ULI_M5263: 2320 srom = (uint16_t *)sc->dc_srom; 2321 if (srom == NULL || *srom == 0xFFFF || *srom == 0) { 2322 /* 2323 * No valid SROM present, read station address 2324 * from ID Table. 2325 */ 2326 device_printf(dev, 2327 "Reading station address from ID Table.\n"); 2328 CSR_WRITE_4(sc, DC_BUSCTL, 0x10000); 2329 CSR_WRITE_4(sc, DC_SIARESET, 0x01C0); 2330 CSR_WRITE_4(sc, DC_10BTCTRL, 0x0000); 2331 CSR_WRITE_4(sc, DC_10BTCTRL, 0x0010); 2332 CSR_WRITE_4(sc, DC_10BTCTRL, 0x0000); 2333 CSR_WRITE_4(sc, DC_SIARESET, 0x0000); 2334 CSR_WRITE_4(sc, DC_SIARESET, 0x01B0); 2335 mac = (uint8_t *)eaddr; 2336 for (n = 0; n < ETHER_ADDR_LEN; n++) 2337 mac[n] = (uint8_t)CSR_READ_4(sc, DC_10BTCTRL); 2338 CSR_WRITE_4(sc, DC_SIARESET, 0x0000); 2339 CSR_WRITE_4(sc, DC_BUSCTL, 0x0000); 2340 DELAY(10); 2341 } else 2342 dc_read_eeprom(sc, (caddr_t)&eaddr, DC_EE_NODEADDR, 3, 2343 0); 2344 break; 2345 default: 2346 dc_read_eeprom(sc, (caddr_t)&eaddr, DC_EE_NODEADDR, 3, 0); 2347 break; 2348 } 2349 2350 bcopy(eaddr, sc->dc_eaddr, sizeof(eaddr)); 2351 /* 2352 * If we still have invalid station address, see whether we can 2353 * find station address for chip 0. Some multi-port controllers 2354 * just store station address for chip 0 if they have a shared 2355 * SROM. 2356 */ 2357 if ((sc->dc_eaddr[0] == 0 && (sc->dc_eaddr[1] & ~0xffff) == 0) || 2358 (sc->dc_eaddr[0] == 0xffffffff && 2359 (sc->dc_eaddr[1] & 0xffff) == 0xffff)) { 2360 error = dc_check_multiport(sc); 2361 if (error == 0) { 2362 bcopy(sc->dc_eaddr, eaddr, sizeof(eaddr)); 2363 /* Extract media information. */ 2364 if (DC_IS_INTEL(sc) && sc->dc_srom != NULL) { 2365 while (sc->dc_mi != NULL) { 2366 m = sc->dc_mi->dc_next; 2367 free(sc->dc_mi, M_DEVBUF); 2368 sc->dc_mi = m; 2369 } 2370 error = dc_parse_21143_srom(sc); 2371 if (error != 0) 2372 goto fail; 2373 } 2374 } else if (error == ENOMEM) 2375 goto fail; 2376 else 2377 error = 0; 2378 } 2379 2380 if ((error = dc_dma_alloc(sc)) != 0) 2381 goto fail; 2382 2383 ifp = sc->dc_ifp = if_alloc(IFT_ETHER); 2384 if (ifp == NULL) { 2385 device_printf(dev, "can not if_alloc()\n"); 2386 error = ENOSPC; 2387 goto fail; 2388 } 2389 ifp->if_softc = sc; 2390 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 2391 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 2392 ifp->if_ioctl = dc_ioctl; 2393 ifp->if_start = dc_start; 2394 ifp->if_init = dc_init; 2395 IFQ_SET_MAXLEN(&ifp->if_snd, DC_TX_LIST_CNT - 1); 2396 ifp->if_snd.ifq_drv_maxlen = DC_TX_LIST_CNT - 1; 2397 IFQ_SET_READY(&ifp->if_snd); 2398 2399 /* 2400 * Do MII setup. If this is a 21143, check for a PHY on the 2401 * MII bus after applying any necessary fixups to twiddle the 2402 * GPIO bits. If we don't end up finding a PHY, restore the 2403 * old selection (SIA only or SIA/SYM) and attach the dcphy 2404 * driver instead. 2405 */ 2406 tmp = 0; 2407 if (DC_IS_INTEL(sc)) { 2408 dc_apply_fixup(sc, IFM_AUTO); 2409 tmp = sc->dc_pmode; 2410 sc->dc_pmode = DC_PMODE_MII; 2411 } 2412 2413 /* 2414 * Setup General Purpose port mode and data so the tulip can talk 2415 * to the MII. This needs to be done before mii_attach so that 2416 * we can actually see them. 2417 */ 2418 if (DC_IS_XIRCOM(sc)) { 2419 CSR_WRITE_4(sc, DC_SIAGP, DC_SIAGP_WRITE_EN | DC_SIAGP_INT1_EN | 2420 DC_SIAGP_MD_GP2_OUTPUT | DC_SIAGP_MD_GP0_OUTPUT); 2421 DELAY(10); 2422 CSR_WRITE_4(sc, DC_SIAGP, DC_SIAGP_INT1_EN | 2423 DC_SIAGP_MD_GP2_OUTPUT | DC_SIAGP_MD_GP0_OUTPUT); 2424 DELAY(10); 2425 } 2426 2427 phy = MII_PHY_ANY; 2428 /* 2429 * Note: both the AL981 and AN983 have internal PHYs, however the 2430 * AL981 provides direct access to the PHY registers while the AN983 2431 * uses a serial MII interface. The AN983's MII interface is also 2432 * buggy in that you can read from any MII address (0 to 31), but 2433 * only address 1 behaves normally. To deal with both cases, we 2434 * pretend that the PHY is at MII address 1. 2435 */ 2436 if (DC_IS_ADMTEK(sc)) 2437 phy = DC_ADMTEK_PHYADDR; 2438 2439 /* 2440 * Note: the ukphy probes of the RS7112 report a PHY at MII address 2441 * 0 (possibly HomePNA?) and 1 (ethernet) so we only respond to the 2442 * correct one. 2443 */ 2444 if (DC_IS_CONEXANT(sc)) 2445 phy = DC_CONEXANT_PHYADDR; 2446 2447 error = mii_attach(dev, &sc->dc_miibus, ifp, dc_ifmedia_upd, 2448 dc_ifmedia_sts, BMSR_DEFCAPMASK, phy, MII_OFFSET_ANY, 0); 2449 2450 if (error && DC_IS_INTEL(sc)) { 2451 sc->dc_pmode = tmp; 2452 if (sc->dc_pmode != DC_PMODE_SIA) 2453 sc->dc_pmode = DC_PMODE_SYM; 2454 sc->dc_flags |= DC_21143_NWAY; 2455 /* 2456 * For non-MII cards, we need to have the 21143 2457 * drive the LEDs. Except there are some systems 2458 * like the NEC VersaPro NoteBook PC which have no 2459 * LEDs, and twiddling these bits has adverse effects 2460 * on them. (I.e. you suddenly can't get a link.) 2461 */ 2462 if (!(pci_get_subvendor(dev) == 0x1033 && 2463 pci_get_subdevice(dev) == 0x8028)) 2464 sc->dc_flags |= DC_TULIP_LEDS; 2465 error = mii_attach(dev, &sc->dc_miibus, ifp, dc_ifmedia_upd, 2466 dc_ifmedia_sts, BMSR_DEFCAPMASK, MII_PHY_ANY, 2467 MII_OFFSET_ANY, 0); 2468 } 2469 2470 if (error) { 2471 device_printf(dev, "attaching PHYs failed\n"); 2472 goto fail; 2473 } 2474 2475 if (DC_IS_ADMTEK(sc)) { 2476 /* 2477 * Set automatic TX underrun recovery for the ADMtek chips 2478 */ 2479 DC_SETBIT(sc, DC_AL_CR, DC_AL_CR_ATUR); 2480 } 2481 2482 /* 2483 * Tell the upper layer(s) we support long frames. 2484 */ 2485 ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header); 2486 ifp->if_capabilities |= IFCAP_VLAN_MTU; 2487 ifp->if_capenable = ifp->if_capabilities; 2488 #ifdef DEVICE_POLLING 2489 ifp->if_capabilities |= IFCAP_POLLING; 2490 #endif 2491 2492 callout_init_mtx(&sc->dc_stat_ch, &sc->dc_mtx, 0); 2493 callout_init_mtx(&sc->dc_wdog_ch, &sc->dc_mtx, 0); 2494 2495 /* 2496 * Call MI attach routine. 2497 */ 2498 ether_ifattach(ifp, (caddr_t)eaddr); 2499 2500 /* Hook interrupt last to avoid having to lock softc */ 2501 error = bus_setup_intr(dev, sc->dc_irq, INTR_TYPE_NET | INTR_MPSAFE, 2502 NULL, dc_intr, sc, &sc->dc_intrhand); 2503 2504 if (error) { 2505 device_printf(dev, "couldn't set up irq\n"); 2506 ether_ifdetach(ifp); 2507 goto fail; 2508 } 2509 2510 fail: 2511 if (error) 2512 dc_detach(dev); 2513 return (error); 2514 } 2515 2516 /* 2517 * Shutdown hardware and free up resources. This can be called any 2518 * time after the mutex has been initialized. It is called in both 2519 * the error case in attach and the normal detach case so it needs 2520 * to be careful about only freeing resources that have actually been 2521 * allocated. 2522 */ 2523 static int 2524 dc_detach(device_t dev) 2525 { 2526 struct dc_softc *sc; 2527 struct ifnet *ifp; 2528 struct dc_mediainfo *m; 2529 2530 sc = device_get_softc(dev); 2531 KASSERT(mtx_initialized(&sc->dc_mtx), ("dc mutex not initialized")); 2532 2533 ifp = sc->dc_ifp; 2534 2535 #ifdef DEVICE_POLLING 2536 if (ifp != NULL && ifp->if_capenable & IFCAP_POLLING) 2537 ether_poll_deregister(ifp); 2538 #endif 2539 2540 /* These should only be active if attach succeeded */ 2541 if (device_is_attached(dev)) { 2542 DC_LOCK(sc); 2543 dc_stop(sc); 2544 DC_UNLOCK(sc); 2545 callout_drain(&sc->dc_stat_ch); 2546 callout_drain(&sc->dc_wdog_ch); 2547 ether_ifdetach(ifp); 2548 } 2549 if (sc->dc_miibus) 2550 device_delete_child(dev, sc->dc_miibus); 2551 bus_generic_detach(dev); 2552 2553 if (sc->dc_intrhand) 2554 bus_teardown_intr(dev, sc->dc_irq, sc->dc_intrhand); 2555 if (sc->dc_irq) 2556 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->dc_irq); 2557 if (sc->dc_res) 2558 bus_release_resource(dev, DC_RES, DC_RID, sc->dc_res); 2559 2560 if (ifp != NULL) 2561 if_free(ifp); 2562 2563 dc_dma_free(sc); 2564 2565 free(sc->dc_pnic_rx_buf, M_DEVBUF); 2566 2567 while (sc->dc_mi != NULL) { 2568 m = sc->dc_mi->dc_next; 2569 free(sc->dc_mi, M_DEVBUF); 2570 sc->dc_mi = m; 2571 } 2572 free(sc->dc_srom, M_DEVBUF); 2573 2574 mtx_destroy(&sc->dc_mtx); 2575 2576 return (0); 2577 } 2578 2579 /* 2580 * Initialize the transmit descriptors. 2581 */ 2582 static int 2583 dc_list_tx_init(struct dc_softc *sc) 2584 { 2585 struct dc_chain_data *cd; 2586 struct dc_list_data *ld; 2587 int i, nexti; 2588 2589 cd = &sc->dc_cdata; 2590 ld = &sc->dc_ldata; 2591 for (i = 0; i < DC_TX_LIST_CNT; i++) { 2592 if (i == DC_TX_LIST_CNT - 1) 2593 nexti = 0; 2594 else 2595 nexti = i + 1; 2596 ld->dc_tx_list[i].dc_status = 0; 2597 ld->dc_tx_list[i].dc_ctl = 0; 2598 ld->dc_tx_list[i].dc_data = 0; 2599 ld->dc_tx_list[i].dc_next = htole32(DC_TXDESC(sc, nexti)); 2600 cd->dc_tx_chain[i] = NULL; 2601 } 2602 2603 cd->dc_tx_prod = cd->dc_tx_cons = cd->dc_tx_cnt = 0; 2604 cd->dc_tx_pkts = 0; 2605 bus_dmamap_sync(sc->dc_tx_ltag, sc->dc_tx_lmap, 2606 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2607 return (0); 2608 } 2609 2610 /* 2611 * Initialize the RX descriptors and allocate mbufs for them. Note that 2612 * we arrange the descriptors in a closed ring, so that the last descriptor 2613 * points back to the first. 2614 */ 2615 static int 2616 dc_list_rx_init(struct dc_softc *sc) 2617 { 2618 struct dc_chain_data *cd; 2619 struct dc_list_data *ld; 2620 int i, nexti; 2621 2622 cd = &sc->dc_cdata; 2623 ld = &sc->dc_ldata; 2624 2625 for (i = 0; i < DC_RX_LIST_CNT; i++) { 2626 if (dc_newbuf(sc, i) != 0) 2627 return (ENOBUFS); 2628 if (i == DC_RX_LIST_CNT - 1) 2629 nexti = 0; 2630 else 2631 nexti = i + 1; 2632 ld->dc_rx_list[i].dc_next = htole32(DC_RXDESC(sc, nexti)); 2633 } 2634 2635 cd->dc_rx_prod = 0; 2636 bus_dmamap_sync(sc->dc_rx_ltag, sc->dc_rx_lmap, 2637 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2638 return (0); 2639 } 2640 2641 /* 2642 * Initialize an RX descriptor and attach an MBUF cluster. 2643 */ 2644 static int 2645 dc_newbuf(struct dc_softc *sc, int i) 2646 { 2647 struct mbuf *m; 2648 bus_dmamap_t map; 2649 bus_dma_segment_t segs[1]; 2650 int error, nseg; 2651 2652 m = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR); 2653 if (m == NULL) 2654 return (ENOBUFS); 2655 m->m_len = m->m_pkthdr.len = MCLBYTES; 2656 m_adj(m, sizeof(u_int64_t)); 2657 2658 /* 2659 * If this is a PNIC chip, zero the buffer. This is part 2660 * of the workaround for the receive bug in the 82c168 and 2661 * 82c169 chips. 2662 */ 2663 if (sc->dc_flags & DC_PNIC_RX_BUG_WAR) 2664 bzero(mtod(m, char *), m->m_len); 2665 2666 error = bus_dmamap_load_mbuf_sg(sc->dc_rx_mtag, sc->dc_sparemap, 2667 m, segs, &nseg, 0); 2668 if (error) { 2669 m_freem(m); 2670 return (error); 2671 } 2672 KASSERT(nseg == 1, ("%s: wrong number of segments (%d)", __func__, 2673 nseg)); 2674 if (sc->dc_cdata.dc_rx_chain[i] != NULL) 2675 bus_dmamap_unload(sc->dc_rx_mtag, sc->dc_cdata.dc_rx_map[i]); 2676 2677 map = sc->dc_cdata.dc_rx_map[i]; 2678 sc->dc_cdata.dc_rx_map[i] = sc->dc_sparemap; 2679 sc->dc_sparemap = map; 2680 sc->dc_cdata.dc_rx_chain[i] = m; 2681 bus_dmamap_sync(sc->dc_rx_mtag, sc->dc_cdata.dc_rx_map[i], 2682 BUS_DMASYNC_PREREAD); 2683 2684 sc->dc_ldata.dc_rx_list[i].dc_ctl = htole32(DC_RXCTL_RLINK | DC_RXLEN); 2685 sc->dc_ldata.dc_rx_list[i].dc_data = 2686 htole32(DC_ADDR_LO(segs[0].ds_addr)); 2687 sc->dc_ldata.dc_rx_list[i].dc_status = htole32(DC_RXSTAT_OWN); 2688 bus_dmamap_sync(sc->dc_rx_ltag, sc->dc_rx_lmap, 2689 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2690 return (0); 2691 } 2692 2693 /* 2694 * Grrrrr. 2695 * The PNIC chip has a terrible bug in it that manifests itself during 2696 * periods of heavy activity. The exact mode of failure if difficult to 2697 * pinpoint: sometimes it only happens in promiscuous mode, sometimes it 2698 * will happen on slow machines. The bug is that sometimes instead of 2699 * uploading one complete frame during reception, it uploads what looks 2700 * like the entire contents of its FIFO memory. The frame we want is at 2701 * the end of the whole mess, but we never know exactly how much data has 2702 * been uploaded, so salvaging the frame is hard. 2703 * 2704 * There is only one way to do it reliably, and it's disgusting. 2705 * Here's what we know: 2706 * 2707 * - We know there will always be somewhere between one and three extra 2708 * descriptors uploaded. 2709 * 2710 * - We know the desired received frame will always be at the end of the 2711 * total data upload. 2712 * 2713 * - We know the size of the desired received frame because it will be 2714 * provided in the length field of the status word in the last descriptor. 2715 * 2716 * Here's what we do: 2717 * 2718 * - When we allocate buffers for the receive ring, we bzero() them. 2719 * This means that we know that the buffer contents should be all 2720 * zeros, except for data uploaded by the chip. 2721 * 2722 * - We also force the PNIC chip to upload frames that include the 2723 * ethernet CRC at the end. 2724 * 2725 * - We gather all of the bogus frame data into a single buffer. 2726 * 2727 * - We then position a pointer at the end of this buffer and scan 2728 * backwards until we encounter the first non-zero byte of data. 2729 * This is the end of the received frame. We know we will encounter 2730 * some data at the end of the frame because the CRC will always be 2731 * there, so even if the sender transmits a packet of all zeros, 2732 * we won't be fooled. 2733 * 2734 * - We know the size of the actual received frame, so we subtract 2735 * that value from the current pointer location. This brings us 2736 * to the start of the actual received packet. 2737 * 2738 * - We copy this into an mbuf and pass it on, along with the actual 2739 * frame length. 2740 * 2741 * The performance hit is tremendous, but it beats dropping frames all 2742 * the time. 2743 */ 2744 2745 #define DC_WHOLEFRAME (DC_RXSTAT_FIRSTFRAG | DC_RXSTAT_LASTFRAG) 2746 static void 2747 dc_pnic_rx_bug_war(struct dc_softc *sc, int idx) 2748 { 2749 struct dc_desc *cur_rx; 2750 struct dc_desc *c = NULL; 2751 struct mbuf *m = NULL; 2752 unsigned char *ptr; 2753 int i, total_len; 2754 uint32_t rxstat = 0; 2755 2756 i = sc->dc_pnic_rx_bug_save; 2757 cur_rx = &sc->dc_ldata.dc_rx_list[idx]; 2758 ptr = sc->dc_pnic_rx_buf; 2759 bzero(ptr, DC_RXLEN * 5); 2760 2761 /* Copy all the bytes from the bogus buffers. */ 2762 while (1) { 2763 c = &sc->dc_ldata.dc_rx_list[i]; 2764 rxstat = le32toh(c->dc_status); 2765 m = sc->dc_cdata.dc_rx_chain[i]; 2766 bcopy(mtod(m, char *), ptr, DC_RXLEN); 2767 ptr += DC_RXLEN; 2768 /* If this is the last buffer, break out. */ 2769 if (i == idx || rxstat & DC_RXSTAT_LASTFRAG) 2770 break; 2771 dc_discard_rxbuf(sc, i); 2772 DC_INC(i, DC_RX_LIST_CNT); 2773 } 2774 2775 /* Find the length of the actual receive frame. */ 2776 total_len = DC_RXBYTES(rxstat); 2777 2778 /* Scan backwards until we hit a non-zero byte. */ 2779 while (*ptr == 0x00) 2780 ptr--; 2781 2782 /* Round off. */ 2783 if ((uintptr_t)(ptr) & 0x3) 2784 ptr -= 1; 2785 2786 /* Now find the start of the frame. */ 2787 ptr -= total_len; 2788 if (ptr < sc->dc_pnic_rx_buf) 2789 ptr = sc->dc_pnic_rx_buf; 2790 2791 /* 2792 * Now copy the salvaged frame to the last mbuf and fake up 2793 * the status word to make it look like a successful 2794 * frame reception. 2795 */ 2796 bcopy(ptr, mtod(m, char *), total_len); 2797 cur_rx->dc_status = htole32(rxstat | DC_RXSTAT_FIRSTFRAG); 2798 } 2799 2800 /* 2801 * This routine searches the RX ring for dirty descriptors in the 2802 * event that the rxeof routine falls out of sync with the chip's 2803 * current descriptor pointer. This may happen sometimes as a result 2804 * of a "no RX buffer available" condition that happens when the chip 2805 * consumes all of the RX buffers before the driver has a chance to 2806 * process the RX ring. This routine may need to be called more than 2807 * once to bring the driver back in sync with the chip, however we 2808 * should still be getting RX DONE interrupts to drive the search 2809 * for new packets in the RX ring, so we should catch up eventually. 2810 */ 2811 static int 2812 dc_rx_resync(struct dc_softc *sc) 2813 { 2814 struct dc_desc *cur_rx; 2815 int i, pos; 2816 2817 pos = sc->dc_cdata.dc_rx_prod; 2818 2819 for (i = 0; i < DC_RX_LIST_CNT; i++) { 2820 cur_rx = &sc->dc_ldata.dc_rx_list[pos]; 2821 if (!(le32toh(cur_rx->dc_status) & DC_RXSTAT_OWN)) 2822 break; 2823 DC_INC(pos, DC_RX_LIST_CNT); 2824 } 2825 2826 /* If the ring really is empty, then just return. */ 2827 if (i == DC_RX_LIST_CNT) 2828 return (0); 2829 2830 /* We've fallen behing the chip: catch it. */ 2831 sc->dc_cdata.dc_rx_prod = pos; 2832 2833 return (EAGAIN); 2834 } 2835 2836 static void 2837 dc_discard_rxbuf(struct dc_softc *sc, int i) 2838 { 2839 struct mbuf *m; 2840 2841 if (sc->dc_flags & DC_PNIC_RX_BUG_WAR) { 2842 m = sc->dc_cdata.dc_rx_chain[i]; 2843 bzero(mtod(m, char *), m->m_len); 2844 } 2845 2846 sc->dc_ldata.dc_rx_list[i].dc_ctl = htole32(DC_RXCTL_RLINK | DC_RXLEN); 2847 sc->dc_ldata.dc_rx_list[i].dc_status = htole32(DC_RXSTAT_OWN); 2848 bus_dmamap_sync(sc->dc_rx_ltag, sc->dc_rx_lmap, BUS_DMASYNC_PREREAD | 2849 BUS_DMASYNC_PREWRITE); 2850 } 2851 2852 /* 2853 * A frame has been uploaded: pass the resulting mbuf chain up to 2854 * the higher level protocols. 2855 */ 2856 static int 2857 dc_rxeof(struct dc_softc *sc) 2858 { 2859 struct mbuf *m; 2860 struct ifnet *ifp; 2861 struct dc_desc *cur_rx; 2862 int i, total_len, rx_npkts; 2863 uint32_t rxstat; 2864 2865 DC_LOCK_ASSERT(sc); 2866 2867 ifp = sc->dc_ifp; 2868 rx_npkts = 0; 2869 2870 bus_dmamap_sync(sc->dc_rx_ltag, sc->dc_rx_lmap, BUS_DMASYNC_POSTREAD | 2871 BUS_DMASYNC_POSTWRITE); 2872 for (i = sc->dc_cdata.dc_rx_prod; 2873 (ifp->if_drv_flags & IFF_DRV_RUNNING) != 0; 2874 DC_INC(i, DC_RX_LIST_CNT)) { 2875 #ifdef DEVICE_POLLING 2876 if (ifp->if_capenable & IFCAP_POLLING) { 2877 if (sc->rxcycles <= 0) 2878 break; 2879 sc->rxcycles--; 2880 } 2881 #endif 2882 cur_rx = &sc->dc_ldata.dc_rx_list[i]; 2883 rxstat = le32toh(cur_rx->dc_status); 2884 if ((rxstat & DC_RXSTAT_OWN) != 0) 2885 break; 2886 m = sc->dc_cdata.dc_rx_chain[i]; 2887 bus_dmamap_sync(sc->dc_rx_mtag, sc->dc_cdata.dc_rx_map[i], 2888 BUS_DMASYNC_POSTREAD); 2889 total_len = DC_RXBYTES(rxstat); 2890 rx_npkts++; 2891 2892 if (sc->dc_flags & DC_PNIC_RX_BUG_WAR) { 2893 if ((rxstat & DC_WHOLEFRAME) != DC_WHOLEFRAME) { 2894 if (rxstat & DC_RXSTAT_FIRSTFRAG) 2895 sc->dc_pnic_rx_bug_save = i; 2896 if ((rxstat & DC_RXSTAT_LASTFRAG) == 0) 2897 continue; 2898 dc_pnic_rx_bug_war(sc, i); 2899 rxstat = le32toh(cur_rx->dc_status); 2900 total_len = DC_RXBYTES(rxstat); 2901 } 2902 } 2903 2904 /* 2905 * If an error occurs, update stats, clear the 2906 * status word and leave the mbuf cluster in place: 2907 * it should simply get re-used next time this descriptor 2908 * comes up in the ring. However, don't report long 2909 * frames as errors since they could be vlans. 2910 */ 2911 if ((rxstat & DC_RXSTAT_RXERR)) { 2912 if (!(rxstat & DC_RXSTAT_GIANT) || 2913 (rxstat & (DC_RXSTAT_CRCERR | DC_RXSTAT_DRIBBLE | 2914 DC_RXSTAT_MIIERE | DC_RXSTAT_COLLSEEN | 2915 DC_RXSTAT_RUNT | DC_RXSTAT_DE))) { 2916 ifp->if_ierrors++; 2917 if (rxstat & DC_RXSTAT_COLLSEEN) 2918 ifp->if_collisions++; 2919 dc_discard_rxbuf(sc, i); 2920 if (rxstat & DC_RXSTAT_CRCERR) 2921 continue; 2922 else { 2923 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 2924 dc_init_locked(sc); 2925 return (rx_npkts); 2926 } 2927 } 2928 } 2929 2930 /* No errors; receive the packet. */ 2931 total_len -= ETHER_CRC_LEN; 2932 #ifdef __NO_STRICT_ALIGNMENT 2933 /* 2934 * On architectures without alignment problems we try to 2935 * allocate a new buffer for the receive ring, and pass up 2936 * the one where the packet is already, saving the expensive 2937 * copy done in m_devget(). 2938 * If we are on an architecture with alignment problems, or 2939 * if the allocation fails, then use m_devget and leave the 2940 * existing buffer in the receive ring. 2941 */ 2942 if (dc_newbuf(sc, i) != 0) { 2943 dc_discard_rxbuf(sc, i); 2944 ifp->if_iqdrops++; 2945 continue; 2946 } 2947 m->m_pkthdr.rcvif = ifp; 2948 m->m_pkthdr.len = m->m_len = total_len; 2949 #else 2950 { 2951 struct mbuf *m0; 2952 2953 m0 = m_devget(mtod(m, char *), total_len, 2954 ETHER_ALIGN, ifp, NULL); 2955 dc_discard_rxbuf(sc, i); 2956 if (m0 == NULL) { 2957 ifp->if_iqdrops++; 2958 continue; 2959 } 2960 m = m0; 2961 } 2962 #endif 2963 2964 ifp->if_ipackets++; 2965 DC_UNLOCK(sc); 2966 (*ifp->if_input)(ifp, m); 2967 DC_LOCK(sc); 2968 } 2969 2970 sc->dc_cdata.dc_rx_prod = i; 2971 return (rx_npkts); 2972 } 2973 2974 /* 2975 * A frame was downloaded to the chip. It's safe for us to clean up 2976 * the list buffers. 2977 */ 2978 static void 2979 dc_txeof(struct dc_softc *sc) 2980 { 2981 struct dc_desc *cur_tx; 2982 struct ifnet *ifp; 2983 int idx, setup; 2984 uint32_t ctl, txstat; 2985 2986 if (sc->dc_cdata.dc_tx_cnt == 0) 2987 return; 2988 2989 ifp = sc->dc_ifp; 2990 2991 /* 2992 * Go through our tx list and free mbufs for those 2993 * frames that have been transmitted. 2994 */ 2995 bus_dmamap_sync(sc->dc_tx_ltag, sc->dc_tx_lmap, BUS_DMASYNC_POSTREAD | 2996 BUS_DMASYNC_POSTWRITE); 2997 setup = 0; 2998 for (idx = sc->dc_cdata.dc_tx_cons; idx != sc->dc_cdata.dc_tx_prod; 2999 DC_INC(idx, DC_TX_LIST_CNT), sc->dc_cdata.dc_tx_cnt--) { 3000 cur_tx = &sc->dc_ldata.dc_tx_list[idx]; 3001 txstat = le32toh(cur_tx->dc_status); 3002 ctl = le32toh(cur_tx->dc_ctl); 3003 3004 if (txstat & DC_TXSTAT_OWN) 3005 break; 3006 3007 if (sc->dc_cdata.dc_tx_chain[idx] == NULL) 3008 continue; 3009 3010 if (ctl & DC_TXCTL_SETUP) { 3011 cur_tx->dc_ctl = htole32(ctl & ~DC_TXCTL_SETUP); 3012 setup++; 3013 bus_dmamap_sync(sc->dc_stag, sc->dc_smap, 3014 BUS_DMASYNC_POSTWRITE); 3015 /* 3016 * Yes, the PNIC is so brain damaged 3017 * that it will sometimes generate a TX 3018 * underrun error while DMAing the RX 3019 * filter setup frame. If we detect this, 3020 * we have to send the setup frame again, 3021 * or else the filter won't be programmed 3022 * correctly. 3023 */ 3024 if (DC_IS_PNIC(sc)) { 3025 if (txstat & DC_TXSTAT_ERRSUM) 3026 dc_setfilt(sc); 3027 } 3028 sc->dc_cdata.dc_tx_chain[idx] = NULL; 3029 continue; 3030 } 3031 3032 if (DC_IS_XIRCOM(sc) || DC_IS_CONEXANT(sc)) { 3033 /* 3034 * XXX: Why does my Xircom taunt me so? 3035 * For some reason it likes setting the CARRLOST flag 3036 * even when the carrier is there. wtf?!? 3037 * Who knows, but Conexant chips have the 3038 * same problem. Maybe they took lessons 3039 * from Xircom. 3040 */ 3041 if (/*sc->dc_type == DC_TYPE_21143 &&*/ 3042 sc->dc_pmode == DC_PMODE_MII && 3043 ((txstat & 0xFFFF) & ~(DC_TXSTAT_ERRSUM | 3044 DC_TXSTAT_NOCARRIER))) 3045 txstat &= ~DC_TXSTAT_ERRSUM; 3046 } else { 3047 if (/*sc->dc_type == DC_TYPE_21143 &&*/ 3048 sc->dc_pmode == DC_PMODE_MII && 3049 ((txstat & 0xFFFF) & ~(DC_TXSTAT_ERRSUM | 3050 DC_TXSTAT_NOCARRIER | DC_TXSTAT_CARRLOST))) 3051 txstat &= ~DC_TXSTAT_ERRSUM; 3052 } 3053 3054 if (txstat & DC_TXSTAT_ERRSUM) { 3055 ifp->if_oerrors++; 3056 if (txstat & DC_TXSTAT_EXCESSCOLL) 3057 ifp->if_collisions++; 3058 if (txstat & DC_TXSTAT_LATECOLL) 3059 ifp->if_collisions++; 3060 if (!(txstat & DC_TXSTAT_UNDERRUN)) { 3061 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 3062 dc_init_locked(sc); 3063 return; 3064 } 3065 } else 3066 ifp->if_opackets++; 3067 ifp->if_collisions += (txstat & DC_TXSTAT_COLLCNT) >> 3; 3068 3069 bus_dmamap_sync(sc->dc_tx_mtag, sc->dc_cdata.dc_tx_map[idx], 3070 BUS_DMASYNC_POSTWRITE); 3071 bus_dmamap_unload(sc->dc_tx_mtag, sc->dc_cdata.dc_tx_map[idx]); 3072 m_freem(sc->dc_cdata.dc_tx_chain[idx]); 3073 sc->dc_cdata.dc_tx_chain[idx] = NULL; 3074 } 3075 sc->dc_cdata.dc_tx_cons = idx; 3076 3077 if (sc->dc_cdata.dc_tx_cnt <= DC_TX_LIST_CNT - DC_TX_LIST_RSVD) { 3078 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 3079 if (sc->dc_cdata.dc_tx_cnt == 0) 3080 sc->dc_wdog_timer = 0; 3081 } 3082 if (setup > 0) 3083 bus_dmamap_sync(sc->dc_tx_ltag, sc->dc_tx_lmap, 3084 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 3085 } 3086 3087 static void 3088 dc_tick(void *xsc) 3089 { 3090 struct dc_softc *sc; 3091 struct mii_data *mii; 3092 struct ifnet *ifp; 3093 uint32_t r; 3094 3095 sc = xsc; 3096 DC_LOCK_ASSERT(sc); 3097 ifp = sc->dc_ifp; 3098 mii = device_get_softc(sc->dc_miibus); 3099 3100 /* 3101 * Reclaim transmitted frames for controllers that do 3102 * not generate TX completion interrupt for every frame. 3103 */ 3104 if (sc->dc_flags & DC_TX_USE_TX_INTR) 3105 dc_txeof(sc); 3106 3107 if (sc->dc_flags & DC_REDUCED_MII_POLL) { 3108 if (sc->dc_flags & DC_21143_NWAY) { 3109 r = CSR_READ_4(sc, DC_10BTSTAT); 3110 if (IFM_SUBTYPE(mii->mii_media_active) == 3111 IFM_100_TX && (r & DC_TSTAT_LS100)) { 3112 sc->dc_link = 0; 3113 mii_mediachg(mii); 3114 } 3115 if (IFM_SUBTYPE(mii->mii_media_active) == 3116 IFM_10_T && (r & DC_TSTAT_LS10)) { 3117 sc->dc_link = 0; 3118 mii_mediachg(mii); 3119 } 3120 if (sc->dc_link == 0) 3121 mii_tick(mii); 3122 } else { 3123 /* 3124 * For NICs which never report DC_RXSTATE_WAIT, we 3125 * have to bite the bullet... 3126 */ 3127 if ((DC_HAS_BROKEN_RXSTATE(sc) || (CSR_READ_4(sc, 3128 DC_ISR) & DC_ISR_RX_STATE) == DC_RXSTATE_WAIT) && 3129 sc->dc_cdata.dc_tx_cnt == 0) 3130 mii_tick(mii); 3131 } 3132 } else 3133 mii_tick(mii); 3134 3135 /* 3136 * When the init routine completes, we expect to be able to send 3137 * packets right away, and in fact the network code will send a 3138 * gratuitous ARP the moment the init routine marks the interface 3139 * as running. However, even though the MAC may have been initialized, 3140 * there may be a delay of a few seconds before the PHY completes 3141 * autonegotiation and the link is brought up. Any transmissions 3142 * made during that delay will be lost. Dealing with this is tricky: 3143 * we can't just pause in the init routine while waiting for the 3144 * PHY to come ready since that would bring the whole system to 3145 * a screeching halt for several seconds. 3146 * 3147 * What we do here is prevent the TX start routine from sending 3148 * any packets until a link has been established. After the 3149 * interface has been initialized, the tick routine will poll 3150 * the state of the PHY until the IFM_ACTIVE flag is set. Until 3151 * that time, packets will stay in the send queue, and once the 3152 * link comes up, they will be flushed out to the wire. 3153 */ 3154 if (sc->dc_link != 0 && !IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 3155 dc_start_locked(ifp); 3156 3157 if (sc->dc_flags & DC_21143_NWAY && !sc->dc_link) 3158 callout_reset(&sc->dc_stat_ch, hz/10, dc_tick, sc); 3159 else 3160 callout_reset(&sc->dc_stat_ch, hz, dc_tick, sc); 3161 } 3162 3163 /* 3164 * A transmit underrun has occurred. Back off the transmit threshold, 3165 * or switch to store and forward mode if we have to. 3166 */ 3167 static void 3168 dc_tx_underrun(struct dc_softc *sc) 3169 { 3170 uint32_t netcfg, isr; 3171 int i, reinit; 3172 3173 reinit = 0; 3174 netcfg = CSR_READ_4(sc, DC_NETCFG); 3175 device_printf(sc->dc_dev, "TX underrun -- "); 3176 if ((sc->dc_flags & DC_TX_STORENFWD) == 0) { 3177 if (sc->dc_txthresh + DC_TXTHRESH_INC > DC_TXTHRESH_MAX) { 3178 printf("using store and forward mode\n"); 3179 netcfg |= DC_NETCFG_STORENFWD; 3180 } else { 3181 printf("increasing TX threshold\n"); 3182 sc->dc_txthresh += DC_TXTHRESH_INC; 3183 netcfg &= ~DC_NETCFG_TX_THRESH; 3184 netcfg |= sc->dc_txthresh; 3185 } 3186 3187 if (DC_IS_INTEL(sc)) { 3188 /* 3189 * The real 21143 requires that the transmitter be idle 3190 * in order to change the transmit threshold or store 3191 * and forward state. 3192 */ 3193 CSR_WRITE_4(sc, DC_NETCFG, netcfg & ~DC_NETCFG_TX_ON); 3194 3195 for (i = 0; i < DC_TIMEOUT; i++) { 3196 isr = CSR_READ_4(sc, DC_ISR); 3197 if (isr & DC_ISR_TX_IDLE) 3198 break; 3199 DELAY(10); 3200 } 3201 if (i == DC_TIMEOUT) { 3202 device_printf(sc->dc_dev, 3203 "%s: failed to force tx to idle state\n", 3204 __func__); 3205 reinit++; 3206 } 3207 } 3208 } else { 3209 printf("resetting\n"); 3210 reinit++; 3211 } 3212 3213 if (reinit == 0) { 3214 CSR_WRITE_4(sc, DC_NETCFG, netcfg); 3215 if (DC_IS_INTEL(sc)) 3216 CSR_WRITE_4(sc, DC_NETCFG, netcfg | DC_NETCFG_TX_ON); 3217 } else { 3218 sc->dc_ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 3219 dc_init_locked(sc); 3220 } 3221 } 3222 3223 #ifdef DEVICE_POLLING 3224 static poll_handler_t dc_poll; 3225 3226 static int 3227 dc_poll(struct ifnet *ifp, enum poll_cmd cmd, int count) 3228 { 3229 struct dc_softc *sc = ifp->if_softc; 3230 int rx_npkts = 0; 3231 3232 DC_LOCK(sc); 3233 3234 if (!(ifp->if_drv_flags & IFF_DRV_RUNNING)) { 3235 DC_UNLOCK(sc); 3236 return (rx_npkts); 3237 } 3238 3239 sc->rxcycles = count; 3240 rx_npkts = dc_rxeof(sc); 3241 dc_txeof(sc); 3242 if (!IFQ_IS_EMPTY(&ifp->if_snd) && 3243 !(ifp->if_drv_flags & IFF_DRV_OACTIVE)) 3244 dc_start_locked(ifp); 3245 3246 if (cmd == POLL_AND_CHECK_STATUS) { /* also check status register */ 3247 uint32_t status; 3248 3249 status = CSR_READ_4(sc, DC_ISR); 3250 status &= (DC_ISR_RX_WATDOGTIMEO | DC_ISR_RX_NOBUF | 3251 DC_ISR_TX_NOBUF | DC_ISR_TX_IDLE | DC_ISR_TX_UNDERRUN | 3252 DC_ISR_BUS_ERR); 3253 if (!status) { 3254 DC_UNLOCK(sc); 3255 return (rx_npkts); 3256 } 3257 /* ack what we have */ 3258 CSR_WRITE_4(sc, DC_ISR, status); 3259 3260 if (status & (DC_ISR_RX_WATDOGTIMEO | DC_ISR_RX_NOBUF)) { 3261 uint32_t r = CSR_READ_4(sc, DC_FRAMESDISCARDED); 3262 ifp->if_ierrors += (r & 0xffff) + ((r >> 17) & 0x7ff); 3263 3264 if (dc_rx_resync(sc)) 3265 dc_rxeof(sc); 3266 } 3267 /* restart transmit unit if necessary */ 3268 if (status & DC_ISR_TX_IDLE && sc->dc_cdata.dc_tx_cnt) 3269 CSR_WRITE_4(sc, DC_TXSTART, 0xFFFFFFFF); 3270 3271 if (status & DC_ISR_TX_UNDERRUN) 3272 dc_tx_underrun(sc); 3273 3274 if (status & DC_ISR_BUS_ERR) { 3275 if_printf(ifp, "%s: bus error\n", __func__); 3276 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 3277 dc_init_locked(sc); 3278 } 3279 } 3280 DC_UNLOCK(sc); 3281 return (rx_npkts); 3282 } 3283 #endif /* DEVICE_POLLING */ 3284 3285 static void 3286 dc_intr(void *arg) 3287 { 3288 struct dc_softc *sc; 3289 struct ifnet *ifp; 3290 uint32_t r, status; 3291 int n; 3292 3293 sc = arg; 3294 3295 if (sc->suspended) 3296 return; 3297 3298 DC_LOCK(sc); 3299 status = CSR_READ_4(sc, DC_ISR); 3300 if (status == 0xFFFFFFFF || (status & DC_INTRS) == 0) { 3301 DC_UNLOCK(sc); 3302 return; 3303 } 3304 ifp = sc->dc_ifp; 3305 #ifdef DEVICE_POLLING 3306 if (ifp->if_capenable & IFCAP_POLLING) { 3307 DC_UNLOCK(sc); 3308 return; 3309 } 3310 #endif 3311 /* Disable interrupts. */ 3312 CSR_WRITE_4(sc, DC_IMR, 0x00000000); 3313 3314 for (n = 16; n > 0; n--) { 3315 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) 3316 break; 3317 /* Ack interrupts. */ 3318 CSR_WRITE_4(sc, DC_ISR, status); 3319 3320 if (status & DC_ISR_RX_OK) { 3321 if (dc_rxeof(sc) == 0) { 3322 while (dc_rx_resync(sc)) 3323 dc_rxeof(sc); 3324 } 3325 } 3326 3327 if (status & (DC_ISR_TX_OK | DC_ISR_TX_NOBUF)) 3328 dc_txeof(sc); 3329 3330 if (status & DC_ISR_TX_IDLE) { 3331 dc_txeof(sc); 3332 if (sc->dc_cdata.dc_tx_cnt) { 3333 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_TX_ON); 3334 CSR_WRITE_4(sc, DC_TXSTART, 0xFFFFFFFF); 3335 } 3336 } 3337 3338 if (status & DC_ISR_TX_UNDERRUN) 3339 dc_tx_underrun(sc); 3340 3341 if ((status & DC_ISR_RX_WATDOGTIMEO) 3342 || (status & DC_ISR_RX_NOBUF)) { 3343 r = CSR_READ_4(sc, DC_FRAMESDISCARDED); 3344 ifp->if_ierrors += (r & 0xffff) + ((r >> 17) & 0x7ff); 3345 if (dc_rxeof(sc) == 0) { 3346 while (dc_rx_resync(sc)) 3347 dc_rxeof(sc); 3348 } 3349 } 3350 3351 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 3352 dc_start_locked(ifp); 3353 3354 if (status & DC_ISR_BUS_ERR) { 3355 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 3356 dc_init_locked(sc); 3357 DC_UNLOCK(sc); 3358 return; 3359 } 3360 status = CSR_READ_4(sc, DC_ISR); 3361 if (status == 0xFFFFFFFF || (status & DC_INTRS) == 0) 3362 break; 3363 } 3364 3365 /* Re-enable interrupts. */ 3366 if (ifp->if_drv_flags & IFF_DRV_RUNNING) 3367 CSR_WRITE_4(sc, DC_IMR, DC_INTRS); 3368 3369 DC_UNLOCK(sc); 3370 } 3371 3372 /* 3373 * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data 3374 * pointers to the fragment pointers. 3375 */ 3376 static int 3377 dc_encap(struct dc_softc *sc, struct mbuf **m_head) 3378 { 3379 bus_dma_segment_t segs[DC_MAXFRAGS]; 3380 bus_dmamap_t map; 3381 struct dc_desc *f; 3382 struct mbuf *m; 3383 int cur, defragged, error, first, frag, i, idx, nseg; 3384 3385 m = NULL; 3386 defragged = 0; 3387 if (sc->dc_flags & DC_TX_COALESCE && 3388 ((*m_head)->m_next != NULL || sc->dc_flags & DC_TX_ALIGN)) { 3389 m = m_defrag(*m_head, M_DONTWAIT); 3390 defragged = 1; 3391 } else { 3392 /* 3393 * Count the number of frags in this chain to see if we 3394 * need to m_collapse. Since the descriptor list is shared 3395 * by all packets, we'll m_collapse long chains so that they 3396 * do not use up the entire list, even if they would fit. 3397 */ 3398 i = 0; 3399 for (m = *m_head; m != NULL; m = m->m_next) 3400 i++; 3401 if (i > DC_TX_LIST_CNT / 4 || 3402 DC_TX_LIST_CNT - i + sc->dc_cdata.dc_tx_cnt <= 3403 DC_TX_LIST_RSVD) { 3404 m = m_collapse(*m_head, M_DONTWAIT, DC_MAXFRAGS); 3405 defragged = 1; 3406 } 3407 } 3408 if (defragged != 0) { 3409 if (m == NULL) { 3410 m_freem(*m_head); 3411 *m_head = NULL; 3412 return (ENOBUFS); 3413 } 3414 *m_head = m; 3415 } 3416 3417 idx = sc->dc_cdata.dc_tx_prod; 3418 error = bus_dmamap_load_mbuf_sg(sc->dc_tx_mtag, 3419 sc->dc_cdata.dc_tx_map[idx], *m_head, segs, &nseg, 0); 3420 if (error == EFBIG) { 3421 if (defragged != 0 || (m = m_collapse(*m_head, M_DONTWAIT, 3422 DC_MAXFRAGS)) == NULL) { 3423 m_freem(*m_head); 3424 *m_head = NULL; 3425 return (defragged != 0 ? error : ENOBUFS); 3426 } 3427 *m_head = m; 3428 error = bus_dmamap_load_mbuf_sg(sc->dc_tx_mtag, 3429 sc->dc_cdata.dc_tx_map[idx], *m_head, segs, &nseg, 0); 3430 if (error != 0) { 3431 m_freem(*m_head); 3432 *m_head = NULL; 3433 return (error); 3434 } 3435 } else if (error != 0) 3436 return (error); 3437 KASSERT(nseg <= DC_MAXFRAGS, 3438 ("%s: wrong number of segments (%d)", __func__, nseg)); 3439 if (nseg == 0) { 3440 m_freem(*m_head); 3441 *m_head = NULL; 3442 return (EIO); 3443 } 3444 3445 /* Check descriptor overruns. */ 3446 if (sc->dc_cdata.dc_tx_cnt + nseg > DC_TX_LIST_CNT - DC_TX_LIST_RSVD) { 3447 bus_dmamap_unload(sc->dc_tx_mtag, sc->dc_cdata.dc_tx_map[idx]); 3448 return (ENOBUFS); 3449 } 3450 bus_dmamap_sync(sc->dc_tx_mtag, sc->dc_cdata.dc_tx_map[idx], 3451 BUS_DMASYNC_PREWRITE); 3452 3453 first = cur = frag = sc->dc_cdata.dc_tx_prod; 3454 for (i = 0; i < nseg; i++) { 3455 if ((sc->dc_flags & DC_TX_ADMTEK_WAR) && 3456 (frag == (DC_TX_LIST_CNT - 1)) && 3457 (first != sc->dc_cdata.dc_tx_first)) { 3458 bus_dmamap_unload(sc->dc_tx_mtag, 3459 sc->dc_cdata.dc_tx_map[first]); 3460 m_freem(*m_head); 3461 *m_head = NULL; 3462 return (ENOBUFS); 3463 } 3464 3465 f = &sc->dc_ldata.dc_tx_list[frag]; 3466 f->dc_ctl = htole32(DC_TXCTL_TLINK | segs[i].ds_len); 3467 if (i == 0) { 3468 f->dc_status = 0; 3469 f->dc_ctl |= htole32(DC_TXCTL_FIRSTFRAG); 3470 } else 3471 f->dc_status = htole32(DC_TXSTAT_OWN); 3472 f->dc_data = htole32(DC_ADDR_LO(segs[i].ds_addr)); 3473 cur = frag; 3474 DC_INC(frag, DC_TX_LIST_CNT); 3475 } 3476 3477 sc->dc_cdata.dc_tx_prod = frag; 3478 sc->dc_cdata.dc_tx_cnt += nseg; 3479 sc->dc_cdata.dc_tx_chain[cur] = *m_head; 3480 sc->dc_ldata.dc_tx_list[cur].dc_ctl |= htole32(DC_TXCTL_LASTFRAG); 3481 if (sc->dc_flags & DC_TX_INTR_FIRSTFRAG) 3482 sc->dc_ldata.dc_tx_list[first].dc_ctl |= 3483 htole32(DC_TXCTL_FINT); 3484 if (sc->dc_flags & DC_TX_INTR_ALWAYS) 3485 sc->dc_ldata.dc_tx_list[cur].dc_ctl |= htole32(DC_TXCTL_FINT); 3486 if (sc->dc_flags & DC_TX_USE_TX_INTR && 3487 ++sc->dc_cdata.dc_tx_pkts >= 8) { 3488 sc->dc_cdata.dc_tx_pkts = 0; 3489 sc->dc_ldata.dc_tx_list[cur].dc_ctl |= htole32(DC_TXCTL_FINT); 3490 } 3491 sc->dc_ldata.dc_tx_list[first].dc_status = htole32(DC_TXSTAT_OWN); 3492 3493 bus_dmamap_sync(sc->dc_tx_ltag, sc->dc_tx_lmap, 3494 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 3495 3496 /* 3497 * Swap the last and the first dmamaps to ensure the map for 3498 * this transmission is placed at the last descriptor. 3499 */ 3500 map = sc->dc_cdata.dc_tx_map[cur]; 3501 sc->dc_cdata.dc_tx_map[cur] = sc->dc_cdata.dc_tx_map[first]; 3502 sc->dc_cdata.dc_tx_map[first] = map; 3503 3504 return (0); 3505 } 3506 3507 static void 3508 dc_start(struct ifnet *ifp) 3509 { 3510 struct dc_softc *sc; 3511 3512 sc = ifp->if_softc; 3513 DC_LOCK(sc); 3514 dc_start_locked(ifp); 3515 DC_UNLOCK(sc); 3516 } 3517 3518 /* 3519 * Main transmit routine 3520 * To avoid having to do mbuf copies, we put pointers to the mbuf data 3521 * regions directly in the transmit lists. We also save a copy of the 3522 * pointers since the transmit list fragment pointers are physical 3523 * addresses. 3524 */ 3525 static void 3526 dc_start_locked(struct ifnet *ifp) 3527 { 3528 struct dc_softc *sc; 3529 struct mbuf *m_head; 3530 int queued; 3531 3532 sc = ifp->if_softc; 3533 3534 DC_LOCK_ASSERT(sc); 3535 3536 if ((ifp->if_drv_flags & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) != 3537 IFF_DRV_RUNNING || sc->dc_link == 0) 3538 return; 3539 3540 sc->dc_cdata.dc_tx_first = sc->dc_cdata.dc_tx_prod; 3541 3542 for (queued = 0; !IFQ_DRV_IS_EMPTY(&ifp->if_snd); ) { 3543 /* 3544 * If there's no way we can send any packets, return now. 3545 */ 3546 if (sc->dc_cdata.dc_tx_cnt > DC_TX_LIST_CNT - DC_TX_LIST_RSVD) { 3547 ifp->if_drv_flags |= IFF_DRV_OACTIVE; 3548 break; 3549 } 3550 IFQ_DRV_DEQUEUE(&ifp->if_snd, m_head); 3551 if (m_head == NULL) 3552 break; 3553 3554 if (dc_encap(sc, &m_head)) { 3555 if (m_head == NULL) 3556 break; 3557 IFQ_DRV_PREPEND(&ifp->if_snd, m_head); 3558 ifp->if_drv_flags |= IFF_DRV_OACTIVE; 3559 break; 3560 } 3561 3562 queued++; 3563 /* 3564 * If there's a BPF listener, bounce a copy of this frame 3565 * to him. 3566 */ 3567 BPF_MTAP(ifp, m_head); 3568 } 3569 3570 if (queued > 0) { 3571 /* Transmit */ 3572 if (!(sc->dc_flags & DC_TX_POLL)) 3573 CSR_WRITE_4(sc, DC_TXSTART, 0xFFFFFFFF); 3574 3575 /* 3576 * Set a timeout in case the chip goes out to lunch. 3577 */ 3578 sc->dc_wdog_timer = 5; 3579 } 3580 } 3581 3582 static void 3583 dc_init(void *xsc) 3584 { 3585 struct dc_softc *sc = xsc; 3586 3587 DC_LOCK(sc); 3588 dc_init_locked(sc); 3589 DC_UNLOCK(sc); 3590 } 3591 3592 static void 3593 dc_init_locked(struct dc_softc *sc) 3594 { 3595 struct ifnet *ifp = sc->dc_ifp; 3596 struct mii_data *mii; 3597 struct ifmedia *ifm; 3598 3599 DC_LOCK_ASSERT(sc); 3600 3601 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) 3602 return; 3603 3604 mii = device_get_softc(sc->dc_miibus); 3605 3606 /* 3607 * Cancel pending I/O and free all RX/TX buffers. 3608 */ 3609 dc_stop(sc); 3610 dc_reset(sc); 3611 if (DC_IS_INTEL(sc)) { 3612 ifm = &mii->mii_media; 3613 dc_apply_fixup(sc, ifm->ifm_media); 3614 } 3615 3616 /* 3617 * Set cache alignment and burst length. 3618 */ 3619 if (DC_IS_ASIX(sc) || DC_IS_DAVICOM(sc) || DC_IS_ULI(sc)) 3620 CSR_WRITE_4(sc, DC_BUSCTL, 0); 3621 else 3622 CSR_WRITE_4(sc, DC_BUSCTL, DC_BUSCTL_MRME | DC_BUSCTL_MRLE); 3623 /* 3624 * Evenly share the bus between receive and transmit process. 3625 */ 3626 if (DC_IS_INTEL(sc)) 3627 DC_SETBIT(sc, DC_BUSCTL, DC_BUSCTL_ARBITRATION); 3628 if (DC_IS_DAVICOM(sc) || DC_IS_INTEL(sc)) { 3629 DC_SETBIT(sc, DC_BUSCTL, DC_BURSTLEN_USECA); 3630 } else { 3631 DC_SETBIT(sc, DC_BUSCTL, DC_BURSTLEN_16LONG); 3632 } 3633 if (sc->dc_flags & DC_TX_POLL) 3634 DC_SETBIT(sc, DC_BUSCTL, DC_TXPOLL_1); 3635 switch(sc->dc_cachesize) { 3636 case 32: 3637 DC_SETBIT(sc, DC_BUSCTL, DC_CACHEALIGN_32LONG); 3638 break; 3639 case 16: 3640 DC_SETBIT(sc, DC_BUSCTL, DC_CACHEALIGN_16LONG); 3641 break; 3642 case 8: 3643 DC_SETBIT(sc, DC_BUSCTL, DC_CACHEALIGN_8LONG); 3644 break; 3645 case 0: 3646 default: 3647 DC_SETBIT(sc, DC_BUSCTL, DC_CACHEALIGN_NONE); 3648 break; 3649 } 3650 3651 if (sc->dc_flags & DC_TX_STORENFWD) 3652 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_STORENFWD); 3653 else { 3654 if (sc->dc_txthresh > DC_TXTHRESH_MAX) { 3655 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_STORENFWD); 3656 } else { 3657 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_STORENFWD); 3658 DC_SETBIT(sc, DC_NETCFG, sc->dc_txthresh); 3659 } 3660 } 3661 3662 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_NO_RXCRC); 3663 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_TX_BACKOFF); 3664 3665 if (DC_IS_MACRONIX(sc) || DC_IS_PNICII(sc)) { 3666 /* 3667 * The app notes for the 98713 and 98715A say that 3668 * in order to have the chips operate properly, a magic 3669 * number must be written to CSR16. Macronix does not 3670 * document the meaning of these bits so there's no way 3671 * to know exactly what they do. The 98713 has a magic 3672 * number all its own; the rest all use a different one. 3673 */ 3674 DC_CLRBIT(sc, DC_MX_MAGICPACKET, 0xFFFF0000); 3675 if (sc->dc_type == DC_TYPE_98713) 3676 DC_SETBIT(sc, DC_MX_MAGICPACKET, DC_MX_MAGIC_98713); 3677 else 3678 DC_SETBIT(sc, DC_MX_MAGICPACKET, DC_MX_MAGIC_98715); 3679 } 3680 3681 if (DC_IS_XIRCOM(sc)) { 3682 /* 3683 * setup General Purpose Port mode and data so the tulip 3684 * can talk to the MII. 3685 */ 3686 CSR_WRITE_4(sc, DC_SIAGP, DC_SIAGP_WRITE_EN | DC_SIAGP_INT1_EN | 3687 DC_SIAGP_MD_GP2_OUTPUT | DC_SIAGP_MD_GP0_OUTPUT); 3688 DELAY(10); 3689 CSR_WRITE_4(sc, DC_SIAGP, DC_SIAGP_INT1_EN | 3690 DC_SIAGP_MD_GP2_OUTPUT | DC_SIAGP_MD_GP0_OUTPUT); 3691 DELAY(10); 3692 } 3693 3694 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_TX_THRESH); 3695 DC_SETBIT(sc, DC_NETCFG, DC_TXTHRESH_MIN); 3696 3697 /* Init circular RX list. */ 3698 if (dc_list_rx_init(sc) == ENOBUFS) { 3699 device_printf(sc->dc_dev, 3700 "initialization failed: no memory for rx buffers\n"); 3701 dc_stop(sc); 3702 return; 3703 } 3704 3705 /* 3706 * Init TX descriptors. 3707 */ 3708 dc_list_tx_init(sc); 3709 3710 /* 3711 * Load the address of the RX list. 3712 */ 3713 CSR_WRITE_4(sc, DC_RXADDR, DC_RXDESC(sc, 0)); 3714 CSR_WRITE_4(sc, DC_TXADDR, DC_TXDESC(sc, 0)); 3715 3716 /* 3717 * Enable interrupts. 3718 */ 3719 #ifdef DEVICE_POLLING 3720 /* 3721 * ... but only if we are not polling, and make sure they are off in 3722 * the case of polling. Some cards (e.g. fxp) turn interrupts on 3723 * after a reset. 3724 */ 3725 if (ifp->if_capenable & IFCAP_POLLING) 3726 CSR_WRITE_4(sc, DC_IMR, 0x00000000); 3727 else 3728 #endif 3729 CSR_WRITE_4(sc, DC_IMR, DC_INTRS); 3730 CSR_WRITE_4(sc, DC_ISR, 0xFFFFFFFF); 3731 3732 /* Initialize TX jabber and RX watchdog timer. */ 3733 if (DC_IS_ULI(sc)) 3734 CSR_WRITE_4(sc, DC_WATCHDOG, DC_WDOG_JABBERCLK | 3735 DC_WDOG_HOSTUNJAB); 3736 3737 /* Enable transmitter. */ 3738 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_TX_ON); 3739 3740 /* 3741 * If this is an Intel 21143 and we're not using the 3742 * MII port, program the LED control pins so we get 3743 * link and activity indications. 3744 */ 3745 if (sc->dc_flags & DC_TULIP_LEDS) { 3746 CSR_WRITE_4(sc, DC_WATCHDOG, 3747 DC_WDOG_CTLWREN | DC_WDOG_LINK | DC_WDOG_ACTIVITY); 3748 CSR_WRITE_4(sc, DC_WATCHDOG, 0); 3749 } 3750 3751 /* 3752 * Load the RX/multicast filter. We do this sort of late 3753 * because the filter programming scheme on the 21143 and 3754 * some clones requires DMAing a setup frame via the TX 3755 * engine, and we need the transmitter enabled for that. 3756 */ 3757 dc_setfilt(sc); 3758 3759 /* Enable receiver. */ 3760 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_ON); 3761 CSR_WRITE_4(sc, DC_RXSTART, 0xFFFFFFFF); 3762 3763 ifp->if_drv_flags |= IFF_DRV_RUNNING; 3764 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 3765 3766 dc_ifmedia_upd_locked(sc); 3767 3768 /* Clear missed frames and overflow counter. */ 3769 CSR_READ_4(sc, DC_FRAMESDISCARDED); 3770 3771 /* Don't start the ticker if this is a homePNA link. */ 3772 if (IFM_SUBTYPE(mii->mii_media.ifm_media) == IFM_HPNA_1) 3773 sc->dc_link = 1; 3774 else { 3775 if (sc->dc_flags & DC_21143_NWAY) 3776 callout_reset(&sc->dc_stat_ch, hz/10, dc_tick, sc); 3777 else 3778 callout_reset(&sc->dc_stat_ch, hz, dc_tick, sc); 3779 } 3780 3781 sc->dc_wdog_timer = 0; 3782 callout_reset(&sc->dc_wdog_ch, hz, dc_watchdog, sc); 3783 } 3784 3785 /* 3786 * Set media options. 3787 */ 3788 static int 3789 dc_ifmedia_upd(struct ifnet *ifp) 3790 { 3791 struct dc_softc *sc; 3792 int error; 3793 3794 sc = ifp->if_softc; 3795 DC_LOCK(sc); 3796 error = dc_ifmedia_upd_locked(sc); 3797 DC_UNLOCK(sc); 3798 return (error); 3799 } 3800 3801 static int 3802 dc_ifmedia_upd_locked(struct dc_softc *sc) 3803 { 3804 struct mii_data *mii; 3805 struct ifmedia *ifm; 3806 int error; 3807 3808 DC_LOCK_ASSERT(sc); 3809 3810 sc->dc_link = 0; 3811 mii = device_get_softc(sc->dc_miibus); 3812 error = mii_mediachg(mii); 3813 if (error == 0) { 3814 ifm = &mii->mii_media; 3815 if (DC_IS_INTEL(sc)) 3816 dc_setcfg(sc, ifm->ifm_media); 3817 else if (DC_IS_DAVICOM(sc) && 3818 IFM_SUBTYPE(ifm->ifm_media) == IFM_HPNA_1) 3819 dc_setcfg(sc, ifm->ifm_media); 3820 } 3821 3822 return (error); 3823 } 3824 3825 /* 3826 * Report current media status. 3827 */ 3828 static void 3829 dc_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 3830 { 3831 struct dc_softc *sc; 3832 struct mii_data *mii; 3833 struct ifmedia *ifm; 3834 3835 sc = ifp->if_softc; 3836 mii = device_get_softc(sc->dc_miibus); 3837 DC_LOCK(sc); 3838 mii_pollstat(mii); 3839 ifm = &mii->mii_media; 3840 if (DC_IS_DAVICOM(sc)) { 3841 if (IFM_SUBTYPE(ifm->ifm_media) == IFM_HPNA_1) { 3842 ifmr->ifm_active = ifm->ifm_media; 3843 ifmr->ifm_status = 0; 3844 DC_UNLOCK(sc); 3845 return; 3846 } 3847 } 3848 ifmr->ifm_active = mii->mii_media_active; 3849 ifmr->ifm_status = mii->mii_media_status; 3850 DC_UNLOCK(sc); 3851 } 3852 3853 static int 3854 dc_ioctl(struct ifnet *ifp, u_long command, caddr_t data) 3855 { 3856 struct dc_softc *sc = ifp->if_softc; 3857 struct ifreq *ifr = (struct ifreq *)data; 3858 struct mii_data *mii; 3859 int error = 0; 3860 3861 switch (command) { 3862 case SIOCSIFFLAGS: 3863 DC_LOCK(sc); 3864 if (ifp->if_flags & IFF_UP) { 3865 int need_setfilt = (ifp->if_flags ^ sc->dc_if_flags) & 3866 (IFF_PROMISC | IFF_ALLMULTI); 3867 3868 if (ifp->if_drv_flags & IFF_DRV_RUNNING) { 3869 if (need_setfilt) 3870 dc_setfilt(sc); 3871 } else { 3872 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 3873 dc_init_locked(sc); 3874 } 3875 } else { 3876 if (ifp->if_drv_flags & IFF_DRV_RUNNING) 3877 dc_stop(sc); 3878 } 3879 sc->dc_if_flags = ifp->if_flags; 3880 DC_UNLOCK(sc); 3881 break; 3882 case SIOCADDMULTI: 3883 case SIOCDELMULTI: 3884 DC_LOCK(sc); 3885 if (ifp->if_drv_flags & IFF_DRV_RUNNING) 3886 dc_setfilt(sc); 3887 DC_UNLOCK(sc); 3888 break; 3889 case SIOCGIFMEDIA: 3890 case SIOCSIFMEDIA: 3891 mii = device_get_softc(sc->dc_miibus); 3892 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 3893 break; 3894 case SIOCSIFCAP: 3895 #ifdef DEVICE_POLLING 3896 if (ifr->ifr_reqcap & IFCAP_POLLING && 3897 !(ifp->if_capenable & IFCAP_POLLING)) { 3898 error = ether_poll_register(dc_poll, ifp); 3899 if (error) 3900 return(error); 3901 DC_LOCK(sc); 3902 /* Disable interrupts */ 3903 CSR_WRITE_4(sc, DC_IMR, 0x00000000); 3904 ifp->if_capenable |= IFCAP_POLLING; 3905 DC_UNLOCK(sc); 3906 return (error); 3907 } 3908 if (!(ifr->ifr_reqcap & IFCAP_POLLING) && 3909 ifp->if_capenable & IFCAP_POLLING) { 3910 error = ether_poll_deregister(ifp); 3911 /* Enable interrupts. */ 3912 DC_LOCK(sc); 3913 CSR_WRITE_4(sc, DC_IMR, DC_INTRS); 3914 ifp->if_capenable &= ~IFCAP_POLLING; 3915 DC_UNLOCK(sc); 3916 return (error); 3917 } 3918 #endif /* DEVICE_POLLING */ 3919 break; 3920 default: 3921 error = ether_ioctl(ifp, command, data); 3922 break; 3923 } 3924 3925 return (error); 3926 } 3927 3928 static void 3929 dc_watchdog(void *xsc) 3930 { 3931 struct dc_softc *sc = xsc; 3932 struct ifnet *ifp; 3933 3934 DC_LOCK_ASSERT(sc); 3935 3936 if (sc->dc_wdog_timer == 0 || --sc->dc_wdog_timer != 0) { 3937 callout_reset(&sc->dc_wdog_ch, hz, dc_watchdog, sc); 3938 return; 3939 } 3940 3941 ifp = sc->dc_ifp; 3942 ifp->if_oerrors++; 3943 device_printf(sc->dc_dev, "watchdog timeout\n"); 3944 3945 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 3946 dc_init_locked(sc); 3947 3948 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 3949 dc_start_locked(ifp); 3950 } 3951 3952 /* 3953 * Stop the adapter and free any mbufs allocated to the 3954 * RX and TX lists. 3955 */ 3956 static void 3957 dc_stop(struct dc_softc *sc) 3958 { 3959 struct ifnet *ifp; 3960 struct dc_list_data *ld; 3961 struct dc_chain_data *cd; 3962 int i; 3963 uint32_t ctl, netcfg; 3964 3965 DC_LOCK_ASSERT(sc); 3966 3967 ifp = sc->dc_ifp; 3968 ld = &sc->dc_ldata; 3969 cd = &sc->dc_cdata; 3970 3971 callout_stop(&sc->dc_stat_ch); 3972 callout_stop(&sc->dc_wdog_ch); 3973 sc->dc_wdog_timer = 0; 3974 sc->dc_link = 0; 3975 3976 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE); 3977 3978 netcfg = CSR_READ_4(sc, DC_NETCFG); 3979 if (netcfg & (DC_NETCFG_RX_ON | DC_NETCFG_TX_ON)) 3980 CSR_WRITE_4(sc, DC_NETCFG, 3981 netcfg & ~(DC_NETCFG_RX_ON | DC_NETCFG_TX_ON)); 3982 CSR_WRITE_4(sc, DC_IMR, 0x00000000); 3983 /* Wait the completion of TX/RX SM. */ 3984 if (netcfg & (DC_NETCFG_RX_ON | DC_NETCFG_TX_ON)) 3985 dc_netcfg_wait(sc); 3986 3987 CSR_WRITE_4(sc, DC_TXADDR, 0x00000000); 3988 CSR_WRITE_4(sc, DC_RXADDR, 0x00000000); 3989 3990 /* 3991 * Free data in the RX lists. 3992 */ 3993 for (i = 0; i < DC_RX_LIST_CNT; i++) { 3994 if (cd->dc_rx_chain[i] != NULL) { 3995 bus_dmamap_sync(sc->dc_rx_mtag, 3996 cd->dc_rx_map[i], BUS_DMASYNC_POSTREAD); 3997 bus_dmamap_unload(sc->dc_rx_mtag, 3998 cd->dc_rx_map[i]); 3999 m_freem(cd->dc_rx_chain[i]); 4000 cd->dc_rx_chain[i] = NULL; 4001 } 4002 } 4003 bzero(ld->dc_rx_list, DC_RX_LIST_SZ); 4004 bus_dmamap_sync(sc->dc_rx_ltag, sc->dc_rx_lmap, 4005 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 4006 4007 /* 4008 * Free the TX list buffers. 4009 */ 4010 for (i = 0; i < DC_TX_LIST_CNT; i++) { 4011 if (cd->dc_tx_chain[i] != NULL) { 4012 ctl = le32toh(ld->dc_tx_list[i].dc_ctl); 4013 if (ctl & DC_TXCTL_SETUP) { 4014 bus_dmamap_sync(sc->dc_stag, sc->dc_smap, 4015 BUS_DMASYNC_POSTWRITE); 4016 } else { 4017 bus_dmamap_sync(sc->dc_tx_mtag, 4018 cd->dc_tx_map[i], BUS_DMASYNC_POSTWRITE); 4019 bus_dmamap_unload(sc->dc_tx_mtag, 4020 cd->dc_tx_map[i]); 4021 m_freem(cd->dc_tx_chain[i]); 4022 } 4023 cd->dc_tx_chain[i] = NULL; 4024 } 4025 } 4026 bzero(ld->dc_tx_list, DC_TX_LIST_SZ); 4027 bus_dmamap_sync(sc->dc_tx_ltag, sc->dc_tx_lmap, 4028 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 4029 } 4030 4031 /* 4032 * Device suspend routine. Stop the interface and save some PCI 4033 * settings in case the BIOS doesn't restore them properly on 4034 * resume. 4035 */ 4036 static int 4037 dc_suspend(device_t dev) 4038 { 4039 struct dc_softc *sc; 4040 4041 sc = device_get_softc(dev); 4042 DC_LOCK(sc); 4043 dc_stop(sc); 4044 sc->suspended = 1; 4045 DC_UNLOCK(sc); 4046 4047 return (0); 4048 } 4049 4050 /* 4051 * Device resume routine. Restore some PCI settings in case the BIOS 4052 * doesn't, re-enable busmastering, and restart the interface if 4053 * appropriate. 4054 */ 4055 static int 4056 dc_resume(device_t dev) 4057 { 4058 struct dc_softc *sc; 4059 struct ifnet *ifp; 4060 4061 sc = device_get_softc(dev); 4062 ifp = sc->dc_ifp; 4063 4064 /* reinitialize interface if necessary */ 4065 DC_LOCK(sc); 4066 if (ifp->if_flags & IFF_UP) 4067 dc_init_locked(sc); 4068 4069 sc->suspended = 0; 4070 DC_UNLOCK(sc); 4071 4072 return (0); 4073 } 4074 4075 /* 4076 * Stop all chip I/O so that the kernel's probe routines don't 4077 * get confused by errant DMAs when rebooting. 4078 */ 4079 static int 4080 dc_shutdown(device_t dev) 4081 { 4082 struct dc_softc *sc; 4083 4084 sc = device_get_softc(dev); 4085 4086 DC_LOCK(sc); 4087 dc_stop(sc); 4088 DC_UNLOCK(sc); 4089 4090 return (0); 4091 } 4092 4093 static int 4094 dc_check_multiport(struct dc_softc *sc) 4095 { 4096 struct dc_softc *dsc; 4097 devclass_t dc; 4098 device_t child; 4099 uint8_t *eaddr; 4100 int unit; 4101 4102 dc = devclass_find("dc"); 4103 for (unit = 0; unit < devclass_get_maxunit(dc); unit++) { 4104 child = devclass_get_device(dc, unit); 4105 if (child == NULL) 4106 continue; 4107 if (child == sc->dc_dev) 4108 continue; 4109 if (device_get_parent(child) != device_get_parent(sc->dc_dev)) 4110 continue; 4111 if (unit > device_get_unit(sc->dc_dev)) 4112 continue; 4113 if (device_is_attached(child) == 0) 4114 continue; 4115 dsc = device_get_softc(child); 4116 device_printf(sc->dc_dev, 4117 "Using station address of %s as base\n", 4118 device_get_nameunit(child)); 4119 bcopy(dsc->dc_eaddr, sc->dc_eaddr, ETHER_ADDR_LEN); 4120 eaddr = (uint8_t *)sc->dc_eaddr; 4121 eaddr[5]++; 4122 /* Prepare SROM to parse again. */ 4123 if (DC_IS_INTEL(sc) && dsc->dc_srom != NULL && 4124 sc->dc_romwidth != 0) { 4125 free(sc->dc_srom, M_DEVBUF); 4126 sc->dc_romwidth = dsc->dc_romwidth; 4127 sc->dc_srom = malloc(DC_ROM_SIZE(sc->dc_romwidth), 4128 M_DEVBUF, M_NOWAIT); 4129 if (sc->dc_srom == NULL) { 4130 device_printf(sc->dc_dev, 4131 "Could not allocate SROM buffer\n"); 4132 return (ENOMEM); 4133 } 4134 bcopy(dsc->dc_srom, sc->dc_srom, 4135 DC_ROM_SIZE(sc->dc_romwidth)); 4136 } 4137 return (0); 4138 } 4139 return (ENOENT); 4140 } 4141