1 /*- 2 * Copyright (c) 1997, 1998, 1999 3 * Bill Paul <wpaul@ee.columbia.edu>. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 3. All advertising materials mentioning features or use of this software 14 * must display the following acknowledgement: 15 * This product includes software developed by Bill Paul. 16 * 4. Neither the name of the author nor the names of any co-contributors 17 * may be used to endorse or promote products derived from this software 18 * without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30 * THE POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33 #include <sys/cdefs.h> 34 __FBSDID("$FreeBSD$"); 35 36 /* 37 * DEC "tulip" clone ethernet driver. Supports the DEC/Intel 21143 38 * series chips and several workalikes including the following: 39 * 40 * Macronix 98713/98715/98725/98727/98732 PMAC (www.macronix.com) 41 * Macronix/Lite-On 82c115 PNIC II (www.macronix.com) 42 * Lite-On 82c168/82c169 PNIC (www.litecom.com) 43 * ASIX Electronics AX88140A (www.asix.com.tw) 44 * ASIX Electronics AX88141 (www.asix.com.tw) 45 * ADMtek AL981 (www.admtek.com.tw) 46 * ADMtek AN985 (www.admtek.com.tw) 47 * Netgear FA511 (www.netgear.com) Appears to be rebadged ADMTek AN985 48 * Davicom DM9100, DM9102, DM9102A (www.davicom8.com) 49 * Accton EN1217 (www.accton.com) 50 * Xircom X3201 (www.xircom.com) 51 * Abocom FE2500 52 * Conexant LANfinity (www.conexant.com) 53 * 3Com OfficeConnect 10/100B 3CSOHO100B (www.3com.com) 54 * 55 * Datasheets for the 21143 are available at developer.intel.com. 56 * Datasheets for the clone parts can be found at their respective sites. 57 * (Except for the PNIC; see www.freebsd.org/~wpaul/PNIC/pnic.ps.gz.) 58 * The PNIC II is essentially a Macronix 98715A chip; the only difference 59 * worth noting is that its multicast hash table is only 128 bits wide 60 * instead of 512. 61 * 62 * Written by Bill Paul <wpaul@ee.columbia.edu> 63 * Electrical Engineering Department 64 * Columbia University, New York City 65 */ 66 /* 67 * The Intel 21143 is the successor to the DEC 21140. It is basically 68 * the same as the 21140 but with a few new features. The 21143 supports 69 * three kinds of media attachments: 70 * 71 * o MII port, for 10Mbps and 100Mbps support and NWAY 72 * autonegotiation provided by an external PHY. 73 * o SYM port, for symbol mode 100Mbps support. 74 * o 10baseT port. 75 * o AUI/BNC port. 76 * 77 * The 100Mbps SYM port and 10baseT port can be used together in 78 * combination with the internal NWAY support to create a 10/100 79 * autosensing configuration. 80 * 81 * Note that not all tulip workalikes are handled in this driver: we only 82 * deal with those which are relatively well behaved. The Winbond is 83 * handled separately due to its different register offsets and the 84 * special handling needed for its various bugs. The PNIC is handled 85 * here, but I'm not thrilled about it. 86 * 87 * All of the workalike chips use some form of MII transceiver support 88 * with the exception of the Macronix chips, which also have a SYM port. 89 * The ASIX AX88140A is also documented to have a SYM port, but all 90 * the cards I've seen use an MII transceiver, probably because the 91 * AX88140A doesn't support internal NWAY. 92 */ 93 94 #ifdef HAVE_KERNEL_OPTION_HEADERS 95 #include "opt_device_polling.h" 96 #endif 97 98 #include <sys/param.h> 99 #include <sys/endian.h> 100 #include <sys/systm.h> 101 #include <sys/sockio.h> 102 #include <sys/mbuf.h> 103 #include <sys/malloc.h> 104 #include <sys/kernel.h> 105 #include <sys/module.h> 106 #include <sys/socket.h> 107 #include <sys/sysctl.h> 108 109 #include <net/if.h> 110 #include <net/if_arp.h> 111 #include <net/ethernet.h> 112 #include <net/if_dl.h> 113 #include <net/if_media.h> 114 #include <net/if_types.h> 115 #include <net/if_vlan_var.h> 116 117 #include <net/bpf.h> 118 119 #include <machine/bus.h> 120 #include <machine/resource.h> 121 #include <sys/bus.h> 122 #include <sys/rman.h> 123 124 #include <dev/mii/mii.h> 125 #include <dev/mii/miivar.h> 126 127 #include <dev/pci/pcireg.h> 128 #include <dev/pci/pcivar.h> 129 130 #define DC_USEIOSPACE 131 132 #include <dev/dc/if_dcreg.h> 133 134 #ifdef __sparc64__ 135 #include <dev/ofw/openfirm.h> 136 #include <machine/ofw_machdep.h> 137 #endif 138 139 MODULE_DEPEND(dc, pci, 1, 1, 1); 140 MODULE_DEPEND(dc, ether, 1, 1, 1); 141 MODULE_DEPEND(dc, miibus, 1, 1, 1); 142 143 /* 144 * "device miibus" is required in kernel config. See GENERIC if you get 145 * errors here. 146 */ 147 #include "miibus_if.h" 148 149 /* 150 * Various supported device vendors/types and their names. 151 */ 152 static struct dc_type dc_devs[] = { 153 { DC_VENDORID_DEC, DC_DEVICEID_21143, 154 "Intel 21143 10/100BaseTX" }, 155 { DC_VENDORID_DAVICOM, DC_DEVICEID_DM9009, 156 "Davicom DM9009 10/100BaseTX" }, 157 { DC_VENDORID_DAVICOM, DC_DEVICEID_DM9100, 158 "Davicom DM9100 10/100BaseTX" }, 159 { DC_VENDORID_DAVICOM, DC_DEVICEID_DM9102, 160 "Davicom DM9102 10/100BaseTX" }, 161 { DC_VENDORID_DAVICOM, DC_DEVICEID_DM9102, 162 "Davicom DM9102A 10/100BaseTX" }, 163 { DC_VENDORID_ADMTEK, DC_DEVICEID_AL981, 164 "ADMtek AL981 10/100BaseTX" }, 165 { DC_VENDORID_ADMTEK, DC_DEVICEID_AN985, 166 "ADMtek AN985 10/100BaseTX" }, 167 { DC_VENDORID_ADMTEK, DC_DEVICEID_ADM9511, 168 "ADMtek ADM9511 10/100BaseTX" }, 169 { DC_VENDORID_ADMTEK, DC_DEVICEID_ADM9513, 170 "ADMtek ADM9513 10/100BaseTX" }, 171 { DC_VENDORID_ADMTEK, DC_DEVICEID_FA511, 172 "Netgear FA511 10/100BaseTX" }, 173 { DC_VENDORID_ASIX, DC_DEVICEID_AX88140A, 174 "ASIX AX88140A 10/100BaseTX" }, 175 { DC_VENDORID_ASIX, DC_DEVICEID_AX88140A, 176 "ASIX AX88141 10/100BaseTX" }, 177 { DC_VENDORID_MX, DC_DEVICEID_98713, 178 "Macronix 98713 10/100BaseTX" }, 179 { DC_VENDORID_MX, DC_DEVICEID_98713, 180 "Macronix 98713A 10/100BaseTX" }, 181 { DC_VENDORID_CP, DC_DEVICEID_98713_CP, 182 "Compex RL100-TX 10/100BaseTX" }, 183 { DC_VENDORID_CP, DC_DEVICEID_98713_CP, 184 "Compex RL100-TX 10/100BaseTX" }, 185 { DC_VENDORID_MX, DC_DEVICEID_987x5, 186 "Macronix 98715/98715A 10/100BaseTX" }, 187 { DC_VENDORID_MX, DC_DEVICEID_987x5, 188 "Macronix 98715AEC-C 10/100BaseTX" }, 189 { DC_VENDORID_MX, DC_DEVICEID_987x5, 190 "Macronix 98725 10/100BaseTX" }, 191 { DC_VENDORID_MX, DC_DEVICEID_98727, 192 "Macronix 98727/98732 10/100BaseTX" }, 193 { DC_VENDORID_LO, DC_DEVICEID_82C115, 194 "LC82C115 PNIC II 10/100BaseTX" }, 195 { DC_VENDORID_LO, DC_DEVICEID_82C168, 196 "82c168 PNIC 10/100BaseTX" }, 197 { DC_VENDORID_LO, DC_DEVICEID_82C168, 198 "82c169 PNIC 10/100BaseTX" }, 199 { DC_VENDORID_ACCTON, DC_DEVICEID_EN1217, 200 "Accton EN1217 10/100BaseTX" }, 201 { DC_VENDORID_ACCTON, DC_DEVICEID_EN2242, 202 "Accton EN2242 MiniPCI 10/100BaseTX" }, 203 { DC_VENDORID_XIRCOM, DC_DEVICEID_X3201, 204 "Xircom X3201 10/100BaseTX" }, 205 { DC_VENDORID_DLINK, DC_DEVICEID_DRP32TXD, 206 "Neteasy DRP-32TXD Cardbus 10/100" }, 207 { DC_VENDORID_ABOCOM, DC_DEVICEID_FE2500, 208 "Abocom FE2500 10/100BaseTX" }, 209 { DC_VENDORID_ABOCOM, DC_DEVICEID_FE2500MX, 210 "Abocom FE2500MX 10/100BaseTX" }, 211 { DC_VENDORID_CONEXANT, DC_DEVICEID_RS7112, 212 "Conexant LANfinity MiniPCI 10/100BaseTX" }, 213 { DC_VENDORID_HAWKING, DC_DEVICEID_HAWKING_PN672TX, 214 "Hawking CB102 CardBus 10/100" }, 215 { DC_VENDORID_PLANEX, DC_DEVICEID_FNW3602T, 216 "PlaneX FNW-3602-T CardBus 10/100" }, 217 { DC_VENDORID_3COM, DC_DEVICEID_3CSOHOB, 218 "3Com OfficeConnect 10/100B" }, 219 { DC_VENDORID_MICROSOFT, DC_DEVICEID_MSMN120, 220 "Microsoft MN-120 CardBus 10/100" }, 221 { DC_VENDORID_MICROSOFT, DC_DEVICEID_MSMN130, 222 "Microsoft MN-130 10/100" }, 223 { DC_VENDORID_MICROSOFT, DC_DEVICEID_MSMN130_FAKE, 224 "Microsoft MN-130 10/100" }, 225 { 0, 0, NULL } 226 }; 227 228 static int dc_probe(device_t); 229 static int dc_attach(device_t); 230 static int dc_detach(device_t); 231 static int dc_suspend(device_t); 232 static int dc_resume(device_t); 233 static struct dc_type *dc_devtype(device_t); 234 static int dc_newbuf(struct dc_softc *, int, int); 235 static int dc_encap(struct dc_softc *, struct mbuf **); 236 static void dc_pnic_rx_bug_war(struct dc_softc *, int); 237 static int dc_rx_resync(struct dc_softc *); 238 static void dc_rxeof(struct dc_softc *); 239 static void dc_txeof(struct dc_softc *); 240 static void dc_tick(void *); 241 static void dc_tx_underrun(struct dc_softc *); 242 static void dc_intr(void *); 243 static void dc_start(struct ifnet *); 244 static void dc_start_locked(struct ifnet *); 245 static int dc_ioctl(struct ifnet *, u_long, caddr_t); 246 static void dc_init(void *); 247 static void dc_init_locked(struct dc_softc *); 248 static void dc_stop(struct dc_softc *); 249 static void dc_watchdog(struct ifnet *); 250 static void dc_shutdown(device_t); 251 static int dc_ifmedia_upd(struct ifnet *); 252 static void dc_ifmedia_sts(struct ifnet *, struct ifmediareq *); 253 254 static void dc_delay(struct dc_softc *); 255 static void dc_eeprom_idle(struct dc_softc *); 256 static void dc_eeprom_putbyte(struct dc_softc *, int); 257 static void dc_eeprom_getword(struct dc_softc *, int, u_int16_t *); 258 static void dc_eeprom_getword_pnic(struct dc_softc *, int, u_int16_t *); 259 static void dc_eeprom_getword_xircom(struct dc_softc *, int, u_int16_t *); 260 static void dc_eeprom_width(struct dc_softc *); 261 static void dc_read_eeprom(struct dc_softc *, caddr_t, int, int, int); 262 263 static void dc_mii_writebit(struct dc_softc *, int); 264 static int dc_mii_readbit(struct dc_softc *); 265 static void dc_mii_sync(struct dc_softc *); 266 static void dc_mii_send(struct dc_softc *, u_int32_t, int); 267 static int dc_mii_readreg(struct dc_softc *, struct dc_mii_frame *); 268 static int dc_mii_writereg(struct dc_softc *, struct dc_mii_frame *); 269 static int dc_miibus_readreg(device_t, int, int); 270 static int dc_miibus_writereg(device_t, int, int, int); 271 static void dc_miibus_statchg(device_t); 272 static void dc_miibus_mediainit(device_t); 273 274 static void dc_setcfg(struct dc_softc *, int); 275 static uint32_t dc_mchash_le(struct dc_softc *, const uint8_t *); 276 static uint32_t dc_mchash_be(const uint8_t *); 277 static void dc_setfilt_21143(struct dc_softc *); 278 static void dc_setfilt_asix(struct dc_softc *); 279 static void dc_setfilt_admtek(struct dc_softc *); 280 static void dc_setfilt_xircom(struct dc_softc *); 281 282 static void dc_setfilt(struct dc_softc *); 283 284 static void dc_reset(struct dc_softc *); 285 static int dc_list_rx_init(struct dc_softc *); 286 static int dc_list_tx_init(struct dc_softc *); 287 288 static void dc_read_srom(struct dc_softc *, int); 289 static void dc_parse_21143_srom(struct dc_softc *); 290 static void dc_decode_leaf_sia(struct dc_softc *, struct dc_eblock_sia *); 291 static void dc_decode_leaf_mii(struct dc_softc *, struct dc_eblock_mii *); 292 static void dc_decode_leaf_sym(struct dc_softc *, struct dc_eblock_sym *); 293 static void dc_apply_fixup(struct dc_softc *, int); 294 295 static void dc_dma_map_txbuf(void *, bus_dma_segment_t *, int, bus_size_t, int); 296 static void dc_dma_map_rxbuf(void *, bus_dma_segment_t *, int, bus_size_t, int); 297 298 #ifdef DC_USEIOSPACE 299 #define DC_RES SYS_RES_IOPORT 300 #define DC_RID DC_PCI_CFBIO 301 #else 302 #define DC_RES SYS_RES_MEMORY 303 #define DC_RID DC_PCI_CFBMA 304 #endif 305 306 static device_method_t dc_methods[] = { 307 /* Device interface */ 308 DEVMETHOD(device_probe, dc_probe), 309 DEVMETHOD(device_attach, dc_attach), 310 DEVMETHOD(device_detach, dc_detach), 311 DEVMETHOD(device_suspend, dc_suspend), 312 DEVMETHOD(device_resume, dc_resume), 313 DEVMETHOD(device_shutdown, dc_shutdown), 314 315 /* bus interface */ 316 DEVMETHOD(bus_print_child, bus_generic_print_child), 317 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 318 319 /* MII interface */ 320 DEVMETHOD(miibus_readreg, dc_miibus_readreg), 321 DEVMETHOD(miibus_writereg, dc_miibus_writereg), 322 DEVMETHOD(miibus_statchg, dc_miibus_statchg), 323 DEVMETHOD(miibus_mediainit, dc_miibus_mediainit), 324 325 { 0, 0 } 326 }; 327 328 static driver_t dc_driver = { 329 "dc", 330 dc_methods, 331 sizeof(struct dc_softc) 332 }; 333 334 static devclass_t dc_devclass; 335 #ifdef __i386__ 336 static int dc_quick = 1; 337 SYSCTL_INT(_hw, OID_AUTO, dc_quick, CTLFLAG_RW, &dc_quick, 0, 338 "do not m_devget() in dc driver"); 339 #endif 340 341 DRIVER_MODULE(dc, cardbus, dc_driver, dc_devclass, 0, 0); 342 DRIVER_MODULE(dc, pci, dc_driver, dc_devclass, 0, 0); 343 DRIVER_MODULE(miibus, dc, miibus_driver, miibus_devclass, 0, 0); 344 345 #define DC_SETBIT(sc, reg, x) \ 346 CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) | (x)) 347 348 #define DC_CLRBIT(sc, reg, x) \ 349 CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) & ~(x)) 350 351 #define SIO_SET(x) DC_SETBIT(sc, DC_SIO, (x)) 352 #define SIO_CLR(x) DC_CLRBIT(sc, DC_SIO, (x)) 353 354 static void 355 dc_delay(struct dc_softc *sc) 356 { 357 int idx; 358 359 for (idx = (300 / 33) + 1; idx > 0; idx--) 360 CSR_READ_4(sc, DC_BUSCTL); 361 } 362 363 static void 364 dc_eeprom_width(struct dc_softc *sc) 365 { 366 int i; 367 368 /* Force EEPROM to idle state. */ 369 dc_eeprom_idle(sc); 370 371 /* Enter EEPROM access mode. */ 372 CSR_WRITE_4(sc, DC_SIO, DC_SIO_EESEL); 373 dc_delay(sc); 374 DC_SETBIT(sc, DC_SIO, DC_SIO_ROMCTL_READ); 375 dc_delay(sc); 376 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); 377 dc_delay(sc); 378 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CS); 379 dc_delay(sc); 380 381 for (i = 3; i--;) { 382 if (6 & (1 << i)) 383 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_DATAIN); 384 else 385 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_DATAIN); 386 dc_delay(sc); 387 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CLK); 388 dc_delay(sc); 389 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); 390 dc_delay(sc); 391 } 392 393 for (i = 1; i <= 12; i++) { 394 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CLK); 395 dc_delay(sc); 396 if (!(CSR_READ_4(sc, DC_SIO) & DC_SIO_EE_DATAOUT)) { 397 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); 398 dc_delay(sc); 399 break; 400 } 401 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); 402 dc_delay(sc); 403 } 404 405 /* Turn off EEPROM access mode. */ 406 dc_eeprom_idle(sc); 407 408 if (i < 4 || i > 12) 409 sc->dc_romwidth = 6; 410 else 411 sc->dc_romwidth = i; 412 413 /* Enter EEPROM access mode. */ 414 CSR_WRITE_4(sc, DC_SIO, DC_SIO_EESEL); 415 dc_delay(sc); 416 DC_SETBIT(sc, DC_SIO, DC_SIO_ROMCTL_READ); 417 dc_delay(sc); 418 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); 419 dc_delay(sc); 420 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CS); 421 dc_delay(sc); 422 423 /* Turn off EEPROM access mode. */ 424 dc_eeprom_idle(sc); 425 } 426 427 static void 428 dc_eeprom_idle(struct dc_softc *sc) 429 { 430 int i; 431 432 CSR_WRITE_4(sc, DC_SIO, DC_SIO_EESEL); 433 dc_delay(sc); 434 DC_SETBIT(sc, DC_SIO, DC_SIO_ROMCTL_READ); 435 dc_delay(sc); 436 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); 437 dc_delay(sc); 438 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CS); 439 dc_delay(sc); 440 441 for (i = 0; i < 25; i++) { 442 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); 443 dc_delay(sc); 444 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CLK); 445 dc_delay(sc); 446 } 447 448 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); 449 dc_delay(sc); 450 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CS); 451 dc_delay(sc); 452 CSR_WRITE_4(sc, DC_SIO, 0x00000000); 453 } 454 455 /* 456 * Send a read command and address to the EEPROM, check for ACK. 457 */ 458 static void 459 dc_eeprom_putbyte(struct dc_softc *sc, int addr) 460 { 461 int d, i; 462 463 d = DC_EECMD_READ >> 6; 464 for (i = 3; i--; ) { 465 if (d & (1 << i)) 466 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_DATAIN); 467 else 468 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_DATAIN); 469 dc_delay(sc); 470 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CLK); 471 dc_delay(sc); 472 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); 473 dc_delay(sc); 474 } 475 476 /* 477 * Feed in each bit and strobe the clock. 478 */ 479 for (i = sc->dc_romwidth; i--;) { 480 if (addr & (1 << i)) { 481 SIO_SET(DC_SIO_EE_DATAIN); 482 } else { 483 SIO_CLR(DC_SIO_EE_DATAIN); 484 } 485 dc_delay(sc); 486 SIO_SET(DC_SIO_EE_CLK); 487 dc_delay(sc); 488 SIO_CLR(DC_SIO_EE_CLK); 489 dc_delay(sc); 490 } 491 } 492 493 /* 494 * Read a word of data stored in the EEPROM at address 'addr.' 495 * The PNIC 82c168/82c169 has its own non-standard way to read 496 * the EEPROM. 497 */ 498 static void 499 dc_eeprom_getword_pnic(struct dc_softc *sc, int addr, u_int16_t *dest) 500 { 501 int i; 502 u_int32_t r; 503 504 CSR_WRITE_4(sc, DC_PN_SIOCTL, DC_PN_EEOPCODE_READ | addr); 505 506 for (i = 0; i < DC_TIMEOUT; i++) { 507 DELAY(1); 508 r = CSR_READ_4(sc, DC_SIO); 509 if (!(r & DC_PN_SIOCTL_BUSY)) { 510 *dest = (u_int16_t)(r & 0xFFFF); 511 return; 512 } 513 } 514 } 515 516 /* 517 * Read a word of data stored in the EEPROM at address 'addr.' 518 * The Xircom X3201 has its own non-standard way to read 519 * the EEPROM, too. 520 */ 521 static void 522 dc_eeprom_getword_xircom(struct dc_softc *sc, int addr, u_int16_t *dest) 523 { 524 525 SIO_SET(DC_SIO_ROMSEL | DC_SIO_ROMCTL_READ); 526 527 addr *= 2; 528 CSR_WRITE_4(sc, DC_ROM, addr | 0x160); 529 *dest = (u_int16_t)CSR_READ_4(sc, DC_SIO) & 0xff; 530 addr += 1; 531 CSR_WRITE_4(sc, DC_ROM, addr | 0x160); 532 *dest |= ((u_int16_t)CSR_READ_4(sc, DC_SIO) & 0xff) << 8; 533 534 SIO_CLR(DC_SIO_ROMSEL | DC_SIO_ROMCTL_READ); 535 } 536 537 /* 538 * Read a word of data stored in the EEPROM at address 'addr.' 539 */ 540 static void 541 dc_eeprom_getword(struct dc_softc *sc, int addr, u_int16_t *dest) 542 { 543 int i; 544 u_int16_t word = 0; 545 546 /* Force EEPROM to idle state. */ 547 dc_eeprom_idle(sc); 548 549 /* Enter EEPROM access mode. */ 550 CSR_WRITE_4(sc, DC_SIO, DC_SIO_EESEL); 551 dc_delay(sc); 552 DC_SETBIT(sc, DC_SIO, DC_SIO_ROMCTL_READ); 553 dc_delay(sc); 554 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); 555 dc_delay(sc); 556 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CS); 557 dc_delay(sc); 558 559 /* 560 * Send address of word we want to read. 561 */ 562 dc_eeprom_putbyte(sc, addr); 563 564 /* 565 * Start reading bits from EEPROM. 566 */ 567 for (i = 0x8000; i; i >>= 1) { 568 SIO_SET(DC_SIO_EE_CLK); 569 dc_delay(sc); 570 if (CSR_READ_4(sc, DC_SIO) & DC_SIO_EE_DATAOUT) 571 word |= i; 572 dc_delay(sc); 573 SIO_CLR(DC_SIO_EE_CLK); 574 dc_delay(sc); 575 } 576 577 /* Turn off EEPROM access mode. */ 578 dc_eeprom_idle(sc); 579 580 *dest = word; 581 } 582 583 /* 584 * Read a sequence of words from the EEPROM. 585 */ 586 static void 587 dc_read_eeprom(struct dc_softc *sc, caddr_t dest, int off, int cnt, int be) 588 { 589 int i; 590 u_int16_t word = 0, *ptr; 591 592 for (i = 0; i < cnt; i++) { 593 if (DC_IS_PNIC(sc)) 594 dc_eeprom_getword_pnic(sc, off + i, &word); 595 else if (DC_IS_XIRCOM(sc)) 596 dc_eeprom_getword_xircom(sc, off + i, &word); 597 else 598 dc_eeprom_getword(sc, off + i, &word); 599 ptr = (u_int16_t *)(dest + (i * 2)); 600 if (be) 601 *ptr = be16toh(word); 602 else 603 *ptr = le16toh(word); 604 } 605 } 606 607 /* 608 * The following two routines are taken from the Macronix 98713 609 * Application Notes pp.19-21. 610 */ 611 /* 612 * Write a bit to the MII bus. 613 */ 614 static void 615 dc_mii_writebit(struct dc_softc *sc, int bit) 616 { 617 618 if (bit) 619 CSR_WRITE_4(sc, DC_SIO, 620 DC_SIO_ROMCTL_WRITE | DC_SIO_MII_DATAOUT); 621 else 622 CSR_WRITE_4(sc, DC_SIO, DC_SIO_ROMCTL_WRITE); 623 624 DC_SETBIT(sc, DC_SIO, DC_SIO_MII_CLK); 625 DC_CLRBIT(sc, DC_SIO, DC_SIO_MII_CLK); 626 } 627 628 /* 629 * Read a bit from the MII bus. 630 */ 631 static int 632 dc_mii_readbit(struct dc_softc *sc) 633 { 634 635 CSR_WRITE_4(sc, DC_SIO, DC_SIO_ROMCTL_READ | DC_SIO_MII_DIR); 636 CSR_READ_4(sc, DC_SIO); 637 DC_SETBIT(sc, DC_SIO, DC_SIO_MII_CLK); 638 DC_CLRBIT(sc, DC_SIO, DC_SIO_MII_CLK); 639 if (CSR_READ_4(sc, DC_SIO) & DC_SIO_MII_DATAIN) 640 return (1); 641 642 return (0); 643 } 644 645 /* 646 * Sync the PHYs by setting data bit and strobing the clock 32 times. 647 */ 648 static void 649 dc_mii_sync(struct dc_softc *sc) 650 { 651 int i; 652 653 CSR_WRITE_4(sc, DC_SIO, DC_SIO_ROMCTL_WRITE); 654 655 for (i = 0; i < 32; i++) 656 dc_mii_writebit(sc, 1); 657 } 658 659 /* 660 * Clock a series of bits through the MII. 661 */ 662 static void 663 dc_mii_send(struct dc_softc *sc, u_int32_t bits, int cnt) 664 { 665 int i; 666 667 for (i = (0x1 << (cnt - 1)); i; i >>= 1) 668 dc_mii_writebit(sc, bits & i); 669 } 670 671 /* 672 * Read an PHY register through the MII. 673 */ 674 static int 675 dc_mii_readreg(struct dc_softc *sc, struct dc_mii_frame *frame) 676 { 677 int i, ack; 678 679 /* 680 * Set up frame for RX. 681 */ 682 frame->mii_stdelim = DC_MII_STARTDELIM; 683 frame->mii_opcode = DC_MII_READOP; 684 frame->mii_turnaround = 0; 685 frame->mii_data = 0; 686 687 /* 688 * Sync the PHYs. 689 */ 690 dc_mii_sync(sc); 691 692 /* 693 * Send command/address info. 694 */ 695 dc_mii_send(sc, frame->mii_stdelim, 2); 696 dc_mii_send(sc, frame->mii_opcode, 2); 697 dc_mii_send(sc, frame->mii_phyaddr, 5); 698 dc_mii_send(sc, frame->mii_regaddr, 5); 699 700 #ifdef notdef 701 /* Idle bit */ 702 dc_mii_writebit(sc, 1); 703 dc_mii_writebit(sc, 0); 704 #endif 705 706 /* Check for ack. */ 707 ack = dc_mii_readbit(sc); 708 709 /* 710 * Now try reading data bits. If the ack failed, we still 711 * need to clock through 16 cycles to keep the PHY(s) in sync. 712 */ 713 if (ack) { 714 for (i = 0; i < 16; i++) 715 dc_mii_readbit(sc); 716 goto fail; 717 } 718 719 for (i = 0x8000; i; i >>= 1) { 720 if (!ack) { 721 if (dc_mii_readbit(sc)) 722 frame->mii_data |= i; 723 } 724 } 725 726 fail: 727 728 dc_mii_writebit(sc, 0); 729 dc_mii_writebit(sc, 0); 730 731 if (ack) 732 return (1); 733 return (0); 734 } 735 736 /* 737 * Write to a PHY register through the MII. 738 */ 739 static int 740 dc_mii_writereg(struct dc_softc *sc, struct dc_mii_frame *frame) 741 { 742 743 /* 744 * Set up frame for TX. 745 */ 746 747 frame->mii_stdelim = DC_MII_STARTDELIM; 748 frame->mii_opcode = DC_MII_WRITEOP; 749 frame->mii_turnaround = DC_MII_TURNAROUND; 750 751 /* 752 * Sync the PHYs. 753 */ 754 dc_mii_sync(sc); 755 756 dc_mii_send(sc, frame->mii_stdelim, 2); 757 dc_mii_send(sc, frame->mii_opcode, 2); 758 dc_mii_send(sc, frame->mii_phyaddr, 5); 759 dc_mii_send(sc, frame->mii_regaddr, 5); 760 dc_mii_send(sc, frame->mii_turnaround, 2); 761 dc_mii_send(sc, frame->mii_data, 16); 762 763 /* Idle bit. */ 764 dc_mii_writebit(sc, 0); 765 dc_mii_writebit(sc, 0); 766 767 return (0); 768 } 769 770 static int 771 dc_miibus_readreg(device_t dev, int phy, int reg) 772 { 773 struct dc_mii_frame frame; 774 struct dc_softc *sc; 775 int i, rval, phy_reg = 0; 776 777 sc = device_get_softc(dev); 778 bzero(&frame, sizeof(frame)); 779 780 /* 781 * Note: both the AL981 and AN985 have internal PHYs, 782 * however the AL981 provides direct access to the PHY 783 * registers while the AN985 uses a serial MII interface. 784 * The AN985's MII interface is also buggy in that you 785 * can read from any MII address (0 to 31), but only address 1 786 * behaves normally. To deal with both cases, we pretend 787 * that the PHY is at MII address 1. 788 */ 789 if (DC_IS_ADMTEK(sc) && phy != DC_ADMTEK_PHYADDR) 790 return (0); 791 792 /* 793 * Note: the ukphy probes of the RS7112 report a PHY at 794 * MII address 0 (possibly HomePNA?) and 1 (ethernet) 795 * so we only respond to correct one. 796 */ 797 if (DC_IS_CONEXANT(sc) && phy != DC_CONEXANT_PHYADDR) 798 return (0); 799 800 if (sc->dc_pmode != DC_PMODE_MII) { 801 if (phy == (MII_NPHY - 1)) { 802 switch (reg) { 803 case MII_BMSR: 804 /* 805 * Fake something to make the probe 806 * code think there's a PHY here. 807 */ 808 return (BMSR_MEDIAMASK); 809 break; 810 case MII_PHYIDR1: 811 if (DC_IS_PNIC(sc)) 812 return (DC_VENDORID_LO); 813 return (DC_VENDORID_DEC); 814 break; 815 case MII_PHYIDR2: 816 if (DC_IS_PNIC(sc)) 817 return (DC_DEVICEID_82C168); 818 return (DC_DEVICEID_21143); 819 break; 820 default: 821 return (0); 822 break; 823 } 824 } else 825 return (0); 826 } 827 828 if (DC_IS_PNIC(sc)) { 829 CSR_WRITE_4(sc, DC_PN_MII, DC_PN_MIIOPCODE_READ | 830 (phy << 23) | (reg << 18)); 831 for (i = 0; i < DC_TIMEOUT; i++) { 832 DELAY(1); 833 rval = CSR_READ_4(sc, DC_PN_MII); 834 if (!(rval & DC_PN_MII_BUSY)) { 835 rval &= 0xFFFF; 836 return (rval == 0xFFFF ? 0 : rval); 837 } 838 } 839 return (0); 840 } 841 842 if (DC_IS_COMET(sc)) { 843 switch (reg) { 844 case MII_BMCR: 845 phy_reg = DC_AL_BMCR; 846 break; 847 case MII_BMSR: 848 phy_reg = DC_AL_BMSR; 849 break; 850 case MII_PHYIDR1: 851 phy_reg = DC_AL_VENID; 852 break; 853 case MII_PHYIDR2: 854 phy_reg = DC_AL_DEVID; 855 break; 856 case MII_ANAR: 857 phy_reg = DC_AL_ANAR; 858 break; 859 case MII_ANLPAR: 860 phy_reg = DC_AL_LPAR; 861 break; 862 case MII_ANER: 863 phy_reg = DC_AL_ANER; 864 break; 865 default: 866 device_printf(dev, "phy_read: bad phy register %x\n", 867 reg); 868 return (0); 869 break; 870 } 871 872 rval = CSR_READ_4(sc, phy_reg) & 0x0000FFFF; 873 874 if (rval == 0xFFFF) 875 return (0); 876 return (rval); 877 } 878 879 frame.mii_phyaddr = phy; 880 frame.mii_regaddr = reg; 881 if (sc->dc_type == DC_TYPE_98713) { 882 phy_reg = CSR_READ_4(sc, DC_NETCFG); 883 CSR_WRITE_4(sc, DC_NETCFG, phy_reg & ~DC_NETCFG_PORTSEL); 884 } 885 dc_mii_readreg(sc, &frame); 886 if (sc->dc_type == DC_TYPE_98713) 887 CSR_WRITE_4(sc, DC_NETCFG, phy_reg); 888 889 return (frame.mii_data); 890 } 891 892 static int 893 dc_miibus_writereg(device_t dev, int phy, int reg, int data) 894 { 895 struct dc_softc *sc; 896 struct dc_mii_frame frame; 897 int i, phy_reg = 0; 898 899 sc = device_get_softc(dev); 900 bzero(&frame, sizeof(frame)); 901 902 if (DC_IS_ADMTEK(sc) && phy != DC_ADMTEK_PHYADDR) 903 return (0); 904 905 if (DC_IS_CONEXANT(sc) && phy != DC_CONEXANT_PHYADDR) 906 return (0); 907 908 if (DC_IS_PNIC(sc)) { 909 CSR_WRITE_4(sc, DC_PN_MII, DC_PN_MIIOPCODE_WRITE | 910 (phy << 23) | (reg << 10) | data); 911 for (i = 0; i < DC_TIMEOUT; i++) { 912 if (!(CSR_READ_4(sc, DC_PN_MII) & DC_PN_MII_BUSY)) 913 break; 914 } 915 return (0); 916 } 917 918 if (DC_IS_COMET(sc)) { 919 switch (reg) { 920 case MII_BMCR: 921 phy_reg = DC_AL_BMCR; 922 break; 923 case MII_BMSR: 924 phy_reg = DC_AL_BMSR; 925 break; 926 case MII_PHYIDR1: 927 phy_reg = DC_AL_VENID; 928 break; 929 case MII_PHYIDR2: 930 phy_reg = DC_AL_DEVID; 931 break; 932 case MII_ANAR: 933 phy_reg = DC_AL_ANAR; 934 break; 935 case MII_ANLPAR: 936 phy_reg = DC_AL_LPAR; 937 break; 938 case MII_ANER: 939 phy_reg = DC_AL_ANER; 940 break; 941 default: 942 device_printf(dev, "phy_write: bad phy register %x\n", 943 reg); 944 return (0); 945 break; 946 } 947 948 CSR_WRITE_4(sc, phy_reg, data); 949 return (0); 950 } 951 952 frame.mii_phyaddr = phy; 953 frame.mii_regaddr = reg; 954 frame.mii_data = data; 955 956 if (sc->dc_type == DC_TYPE_98713) { 957 phy_reg = CSR_READ_4(sc, DC_NETCFG); 958 CSR_WRITE_4(sc, DC_NETCFG, phy_reg & ~DC_NETCFG_PORTSEL); 959 } 960 dc_mii_writereg(sc, &frame); 961 if (sc->dc_type == DC_TYPE_98713) 962 CSR_WRITE_4(sc, DC_NETCFG, phy_reg); 963 964 return (0); 965 } 966 967 static void 968 dc_miibus_statchg(device_t dev) 969 { 970 struct dc_softc *sc; 971 struct mii_data *mii; 972 struct ifmedia *ifm; 973 974 sc = device_get_softc(dev); 975 if (DC_IS_ADMTEK(sc)) 976 return; 977 978 mii = device_get_softc(sc->dc_miibus); 979 ifm = &mii->mii_media; 980 if (DC_IS_DAVICOM(sc) && 981 IFM_SUBTYPE(ifm->ifm_media) == IFM_HPNA_1) { 982 dc_setcfg(sc, ifm->ifm_media); 983 sc->dc_if_media = ifm->ifm_media; 984 } else { 985 dc_setcfg(sc, mii->mii_media_active); 986 sc->dc_if_media = mii->mii_media_active; 987 } 988 } 989 990 /* 991 * Special support for DM9102A cards with HomePNA PHYs. Note: 992 * with the Davicom DM9102A/DM9801 eval board that I have, it seems 993 * to be impossible to talk to the management interface of the DM9801 994 * PHY (its MDIO pin is not connected to anything). Consequently, 995 * the driver has to just 'know' about the additional mode and deal 996 * with it itself. *sigh* 997 */ 998 static void 999 dc_miibus_mediainit(device_t dev) 1000 { 1001 struct dc_softc *sc; 1002 struct mii_data *mii; 1003 struct ifmedia *ifm; 1004 int rev; 1005 1006 rev = pci_read_config(dev, DC_PCI_CFRV, 4) & 0xFF; 1007 1008 sc = device_get_softc(dev); 1009 mii = device_get_softc(sc->dc_miibus); 1010 ifm = &mii->mii_media; 1011 1012 if (DC_IS_DAVICOM(sc) && rev >= DC_REVISION_DM9102A) 1013 ifmedia_add(ifm, IFM_ETHER | IFM_HPNA_1, 0, NULL); 1014 } 1015 1016 #define DC_BITS_512 9 1017 #define DC_BITS_128 7 1018 #define DC_BITS_64 6 1019 1020 static uint32_t 1021 dc_mchash_le(struct dc_softc *sc, const uint8_t *addr) 1022 { 1023 uint32_t crc; 1024 1025 /* Compute CRC for the address value. */ 1026 crc = ether_crc32_le(addr, ETHER_ADDR_LEN); 1027 1028 /* 1029 * The hash table on the PNIC II and the MX98715AEC-C/D/E 1030 * chips is only 128 bits wide. 1031 */ 1032 if (sc->dc_flags & DC_128BIT_HASH) 1033 return (crc & ((1 << DC_BITS_128) - 1)); 1034 1035 /* The hash table on the MX98715BEC is only 64 bits wide. */ 1036 if (sc->dc_flags & DC_64BIT_HASH) 1037 return (crc & ((1 << DC_BITS_64) - 1)); 1038 1039 /* Xircom's hash filtering table is different (read: weird) */ 1040 /* Xircom uses the LEAST significant bits */ 1041 if (DC_IS_XIRCOM(sc)) { 1042 if ((crc & 0x180) == 0x180) 1043 return ((crc & 0x0F) + (crc & 0x70) * 3 + (14 << 4)); 1044 else 1045 return ((crc & 0x1F) + ((crc >> 1) & 0xF0) * 3 + 1046 (12 << 4)); 1047 } 1048 1049 return (crc & ((1 << DC_BITS_512) - 1)); 1050 } 1051 1052 /* 1053 * Calculate CRC of a multicast group address, return the lower 6 bits. 1054 */ 1055 static uint32_t 1056 dc_mchash_be(const uint8_t *addr) 1057 { 1058 uint32_t crc; 1059 1060 /* Compute CRC for the address value. */ 1061 crc = ether_crc32_be(addr, ETHER_ADDR_LEN); 1062 1063 /* Return the filter bit position. */ 1064 return ((crc >> 26) & 0x0000003F); 1065 } 1066 1067 /* 1068 * 21143-style RX filter setup routine. Filter programming is done by 1069 * downloading a special setup frame into the TX engine. 21143, Macronix, 1070 * PNIC, PNIC II and Davicom chips are programmed this way. 1071 * 1072 * We always program the chip using 'hash perfect' mode, i.e. one perfect 1073 * address (our node address) and a 512-bit hash filter for multicast 1074 * frames. We also sneak the broadcast address into the hash filter since 1075 * we need that too. 1076 */ 1077 static void 1078 dc_setfilt_21143(struct dc_softc *sc) 1079 { 1080 uint16_t eaddr[(ETHER_ADDR_LEN+1)/2]; 1081 struct dc_desc *sframe; 1082 u_int32_t h, *sp; 1083 struct ifmultiaddr *ifma; 1084 struct ifnet *ifp; 1085 int i; 1086 1087 ifp = sc->dc_ifp; 1088 1089 i = sc->dc_cdata.dc_tx_prod; 1090 DC_INC(sc->dc_cdata.dc_tx_prod, DC_TX_LIST_CNT); 1091 sc->dc_cdata.dc_tx_cnt++; 1092 sframe = &sc->dc_ldata->dc_tx_list[i]; 1093 sp = sc->dc_cdata.dc_sbuf; 1094 bzero(sp, DC_SFRAME_LEN); 1095 1096 sframe->dc_data = htole32(sc->dc_saddr); 1097 sframe->dc_ctl = htole32(DC_SFRAME_LEN | DC_TXCTL_SETUP | 1098 DC_TXCTL_TLINK | DC_FILTER_HASHPERF | DC_TXCTL_FINT); 1099 1100 sc->dc_cdata.dc_tx_chain[i] = (struct mbuf *)sc->dc_cdata.dc_sbuf; 1101 1102 /* If we want promiscuous mode, set the allframes bit. */ 1103 if (ifp->if_flags & IFF_PROMISC) 1104 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC); 1105 else 1106 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC); 1107 1108 if (ifp->if_flags & IFF_ALLMULTI) 1109 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI); 1110 else 1111 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI); 1112 1113 IF_ADDR_LOCK(ifp); 1114 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 1115 if (ifma->ifma_addr->sa_family != AF_LINK) 1116 continue; 1117 h = dc_mchash_le(sc, 1118 LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 1119 sp[h >> 4] |= htole32(1 << (h & 0xF)); 1120 } 1121 IF_ADDR_UNLOCK(ifp); 1122 1123 if (ifp->if_flags & IFF_BROADCAST) { 1124 h = dc_mchash_le(sc, ifp->if_broadcastaddr); 1125 sp[h >> 4] |= htole32(1 << (h & 0xF)); 1126 } 1127 1128 /* Set our MAC address. */ 1129 bcopy(IF_LLADDR(sc->dc_ifp), eaddr, ETHER_ADDR_LEN); 1130 sp[39] = DC_SP_MAC(eaddr[0]); 1131 sp[40] = DC_SP_MAC(eaddr[1]); 1132 sp[41] = DC_SP_MAC(eaddr[2]); 1133 1134 sframe->dc_status = htole32(DC_TXSTAT_OWN); 1135 CSR_WRITE_4(sc, DC_TXSTART, 0xFFFFFFFF); 1136 1137 /* 1138 * The PNIC takes an exceedingly long time to process its 1139 * setup frame; wait 10ms after posting the setup frame 1140 * before proceeding, just so it has time to swallow its 1141 * medicine. 1142 */ 1143 DELAY(10000); 1144 1145 ifp->if_timer = 5; 1146 } 1147 1148 static void 1149 dc_setfilt_admtek(struct dc_softc *sc) 1150 { 1151 uint32_t eaddr[(ETHER_ADDR_LEN+3)/4]; 1152 struct ifnet *ifp; 1153 struct ifmultiaddr *ifma; 1154 int h = 0; 1155 u_int32_t hashes[2] = { 0, 0 }; 1156 1157 ifp = sc->dc_ifp; 1158 1159 /* Init our MAC address. */ 1160 bcopy(IF_LLADDR(sc->dc_ifp), eaddr, ETHER_ADDR_LEN); 1161 CSR_WRITE_4(sc, DC_AL_PAR0, eaddr[0]); 1162 CSR_WRITE_4(sc, DC_AL_PAR1, eaddr[1]); 1163 1164 /* If we want promiscuous mode, set the allframes bit. */ 1165 if (ifp->if_flags & IFF_PROMISC) 1166 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC); 1167 else 1168 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC); 1169 1170 if (ifp->if_flags & IFF_ALLMULTI) 1171 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI); 1172 else 1173 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI); 1174 1175 /* First, zot all the existing hash bits. */ 1176 CSR_WRITE_4(sc, DC_AL_MAR0, 0); 1177 CSR_WRITE_4(sc, DC_AL_MAR1, 0); 1178 1179 /* 1180 * If we're already in promisc or allmulti mode, we 1181 * don't have to bother programming the multicast filter. 1182 */ 1183 if (ifp->if_flags & (IFF_PROMISC | IFF_ALLMULTI)) 1184 return; 1185 1186 /* Now program new ones. */ 1187 IF_ADDR_LOCK(ifp); 1188 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 1189 if (ifma->ifma_addr->sa_family != AF_LINK) 1190 continue; 1191 if (DC_IS_CENTAUR(sc)) 1192 h = dc_mchash_le(sc, 1193 LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 1194 else 1195 h = dc_mchash_be( 1196 LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 1197 if (h < 32) 1198 hashes[0] |= (1 << h); 1199 else 1200 hashes[1] |= (1 << (h - 32)); 1201 } 1202 IF_ADDR_UNLOCK(ifp); 1203 1204 CSR_WRITE_4(sc, DC_AL_MAR0, hashes[0]); 1205 CSR_WRITE_4(sc, DC_AL_MAR1, hashes[1]); 1206 } 1207 1208 static void 1209 dc_setfilt_asix(struct dc_softc *sc) 1210 { 1211 uint32_t eaddr[(ETHER_ADDR_LEN+3)/4]; 1212 struct ifnet *ifp; 1213 struct ifmultiaddr *ifma; 1214 int h = 0; 1215 u_int32_t hashes[2] = { 0, 0 }; 1216 1217 ifp = sc->dc_ifp; 1218 1219 /* Init our MAC address. */ 1220 bcopy(IF_LLADDR(sc->dc_ifp), eaddr, ETHER_ADDR_LEN); 1221 CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_PAR0); 1222 CSR_WRITE_4(sc, DC_AX_FILTDATA, eaddr[0]); 1223 CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_PAR1); 1224 CSR_WRITE_4(sc, DC_AX_FILTDATA, eaddr[1]); 1225 1226 /* If we want promiscuous mode, set the allframes bit. */ 1227 if (ifp->if_flags & IFF_PROMISC) 1228 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC); 1229 else 1230 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC); 1231 1232 if (ifp->if_flags & IFF_ALLMULTI) 1233 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI); 1234 else 1235 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI); 1236 1237 /* 1238 * The ASIX chip has a special bit to enable reception 1239 * of broadcast frames. 1240 */ 1241 if (ifp->if_flags & IFF_BROADCAST) 1242 DC_SETBIT(sc, DC_NETCFG, DC_AX_NETCFG_RX_BROAD); 1243 else 1244 DC_CLRBIT(sc, DC_NETCFG, DC_AX_NETCFG_RX_BROAD); 1245 1246 /* first, zot all the existing hash bits */ 1247 CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_MAR0); 1248 CSR_WRITE_4(sc, DC_AX_FILTDATA, 0); 1249 CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_MAR1); 1250 CSR_WRITE_4(sc, DC_AX_FILTDATA, 0); 1251 1252 /* 1253 * If we're already in promisc or allmulti mode, we 1254 * don't have to bother programming the multicast filter. 1255 */ 1256 if (ifp->if_flags & (IFF_PROMISC | IFF_ALLMULTI)) 1257 return; 1258 1259 /* now program new ones */ 1260 IF_ADDR_LOCK(ifp); 1261 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 1262 if (ifma->ifma_addr->sa_family != AF_LINK) 1263 continue; 1264 h = dc_mchash_be(LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 1265 if (h < 32) 1266 hashes[0] |= (1 << h); 1267 else 1268 hashes[1] |= (1 << (h - 32)); 1269 } 1270 IF_ADDR_UNLOCK(ifp); 1271 1272 CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_MAR0); 1273 CSR_WRITE_4(sc, DC_AX_FILTDATA, hashes[0]); 1274 CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_MAR1); 1275 CSR_WRITE_4(sc, DC_AX_FILTDATA, hashes[1]); 1276 } 1277 1278 static void 1279 dc_setfilt_xircom(struct dc_softc *sc) 1280 { 1281 uint16_t eaddr[(ETHER_ADDR_LEN+1)/2]; 1282 struct ifnet *ifp; 1283 struct ifmultiaddr *ifma; 1284 struct dc_desc *sframe; 1285 u_int32_t h, *sp; 1286 int i; 1287 1288 ifp = sc->dc_ifp; 1289 DC_CLRBIT(sc, DC_NETCFG, (DC_NETCFG_TX_ON | DC_NETCFG_RX_ON)); 1290 1291 i = sc->dc_cdata.dc_tx_prod; 1292 DC_INC(sc->dc_cdata.dc_tx_prod, DC_TX_LIST_CNT); 1293 sc->dc_cdata.dc_tx_cnt++; 1294 sframe = &sc->dc_ldata->dc_tx_list[i]; 1295 sp = sc->dc_cdata.dc_sbuf; 1296 bzero(sp, DC_SFRAME_LEN); 1297 1298 sframe->dc_data = htole32(sc->dc_saddr); 1299 sframe->dc_ctl = htole32(DC_SFRAME_LEN | DC_TXCTL_SETUP | 1300 DC_TXCTL_TLINK | DC_FILTER_HASHPERF | DC_TXCTL_FINT); 1301 1302 sc->dc_cdata.dc_tx_chain[i] = (struct mbuf *)sc->dc_cdata.dc_sbuf; 1303 1304 /* If we want promiscuous mode, set the allframes bit. */ 1305 if (ifp->if_flags & IFF_PROMISC) 1306 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC); 1307 else 1308 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC); 1309 1310 if (ifp->if_flags & IFF_ALLMULTI) 1311 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI); 1312 else 1313 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI); 1314 1315 IF_ADDR_LOCK(ifp); 1316 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 1317 if (ifma->ifma_addr->sa_family != AF_LINK) 1318 continue; 1319 h = dc_mchash_le(sc, 1320 LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 1321 sp[h >> 4] |= htole32(1 << (h & 0xF)); 1322 } 1323 IF_ADDR_UNLOCK(ifp); 1324 1325 if (ifp->if_flags & IFF_BROADCAST) { 1326 h = dc_mchash_le(sc, ifp->if_broadcastaddr); 1327 sp[h >> 4] |= htole32(1 << (h & 0xF)); 1328 } 1329 1330 /* Set our MAC address. */ 1331 bcopy(IF_LLADDR(sc->dc_ifp), eaddr, ETHER_ADDR_LEN); 1332 sp[0] = DC_SP_MAC(eaddr[0]); 1333 sp[1] = DC_SP_MAC(eaddr[1]); 1334 sp[2] = DC_SP_MAC(eaddr[2]); 1335 1336 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_TX_ON); 1337 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_ON); 1338 ifp->if_drv_flags |= IFF_DRV_RUNNING; 1339 sframe->dc_status = htole32(DC_TXSTAT_OWN); 1340 CSR_WRITE_4(sc, DC_TXSTART, 0xFFFFFFFF); 1341 1342 /* 1343 * Wait some time... 1344 */ 1345 DELAY(1000); 1346 1347 ifp->if_timer = 5; 1348 } 1349 1350 static void 1351 dc_setfilt(struct dc_softc *sc) 1352 { 1353 1354 if (DC_IS_INTEL(sc) || DC_IS_MACRONIX(sc) || DC_IS_PNIC(sc) || 1355 DC_IS_PNICII(sc) || DC_IS_DAVICOM(sc) || DC_IS_CONEXANT(sc)) 1356 dc_setfilt_21143(sc); 1357 1358 if (DC_IS_ASIX(sc)) 1359 dc_setfilt_asix(sc); 1360 1361 if (DC_IS_ADMTEK(sc)) 1362 dc_setfilt_admtek(sc); 1363 1364 if (DC_IS_XIRCOM(sc)) 1365 dc_setfilt_xircom(sc); 1366 } 1367 1368 /* 1369 * In order to fiddle with the 'full-duplex' and '100Mbps' bits in 1370 * the netconfig register, we first have to put the transmit and/or 1371 * receive logic in the idle state. 1372 */ 1373 static void 1374 dc_setcfg(struct dc_softc *sc, int media) 1375 { 1376 int i, restart = 0, watchdogreg; 1377 u_int32_t isr; 1378 1379 if (IFM_SUBTYPE(media) == IFM_NONE) 1380 return; 1381 1382 if (CSR_READ_4(sc, DC_NETCFG) & (DC_NETCFG_TX_ON | DC_NETCFG_RX_ON)) { 1383 restart = 1; 1384 DC_CLRBIT(sc, DC_NETCFG, (DC_NETCFG_TX_ON | DC_NETCFG_RX_ON)); 1385 1386 for (i = 0; i < DC_TIMEOUT; i++) { 1387 isr = CSR_READ_4(sc, DC_ISR); 1388 if (isr & DC_ISR_TX_IDLE && 1389 ((isr & DC_ISR_RX_STATE) == DC_RXSTATE_STOPPED || 1390 (isr & DC_ISR_RX_STATE) == DC_RXSTATE_WAIT)) 1391 break; 1392 DELAY(10); 1393 } 1394 1395 if (i == DC_TIMEOUT) 1396 if_printf(sc->dc_ifp, 1397 "failed to force tx and rx to idle state\n"); 1398 } 1399 1400 if (IFM_SUBTYPE(media) == IFM_100_TX) { 1401 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_SPEEDSEL); 1402 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_HEARTBEAT); 1403 if (sc->dc_pmode == DC_PMODE_MII) { 1404 if (DC_IS_INTEL(sc)) { 1405 /* There's a write enable bit here that reads as 1. */ 1406 watchdogreg = CSR_READ_4(sc, DC_WATCHDOG); 1407 watchdogreg &= ~DC_WDOG_CTLWREN; 1408 watchdogreg |= DC_WDOG_JABBERDIS; 1409 CSR_WRITE_4(sc, DC_WATCHDOG, watchdogreg); 1410 } else { 1411 DC_SETBIT(sc, DC_WATCHDOG, DC_WDOG_JABBERDIS); 1412 } 1413 DC_CLRBIT(sc, DC_NETCFG, (DC_NETCFG_PCS | 1414 DC_NETCFG_PORTSEL | DC_NETCFG_SCRAMBLER)); 1415 if (sc->dc_type == DC_TYPE_98713) 1416 DC_SETBIT(sc, DC_NETCFG, (DC_NETCFG_PCS | 1417 DC_NETCFG_SCRAMBLER)); 1418 if (!DC_IS_DAVICOM(sc)) 1419 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL); 1420 DC_CLRBIT(sc, DC_10BTCTRL, 0xFFFF); 1421 if (DC_IS_INTEL(sc)) 1422 dc_apply_fixup(sc, IFM_AUTO); 1423 } else { 1424 if (DC_IS_PNIC(sc)) { 1425 DC_PN_GPIO_SETBIT(sc, DC_PN_GPIO_SPEEDSEL); 1426 DC_PN_GPIO_SETBIT(sc, DC_PN_GPIO_100TX_LOOP); 1427 DC_SETBIT(sc, DC_PN_NWAY, DC_PN_NWAY_SPEEDSEL); 1428 } 1429 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL); 1430 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PCS); 1431 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_SCRAMBLER); 1432 if (DC_IS_INTEL(sc)) 1433 dc_apply_fixup(sc, 1434 (media & IFM_GMASK) == IFM_FDX ? 1435 IFM_100_TX | IFM_FDX : IFM_100_TX); 1436 } 1437 } 1438 1439 if (IFM_SUBTYPE(media) == IFM_10_T) { 1440 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_SPEEDSEL); 1441 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_HEARTBEAT); 1442 if (sc->dc_pmode == DC_PMODE_MII) { 1443 /* There's a write enable bit here that reads as 1. */ 1444 if (DC_IS_INTEL(sc)) { 1445 watchdogreg = CSR_READ_4(sc, DC_WATCHDOG); 1446 watchdogreg &= ~DC_WDOG_CTLWREN; 1447 watchdogreg |= DC_WDOG_JABBERDIS; 1448 CSR_WRITE_4(sc, DC_WATCHDOG, watchdogreg); 1449 } else { 1450 DC_SETBIT(sc, DC_WATCHDOG, DC_WDOG_JABBERDIS); 1451 } 1452 DC_CLRBIT(sc, DC_NETCFG, (DC_NETCFG_PCS | 1453 DC_NETCFG_PORTSEL | DC_NETCFG_SCRAMBLER)); 1454 if (sc->dc_type == DC_TYPE_98713) 1455 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PCS); 1456 if (!DC_IS_DAVICOM(sc)) 1457 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL); 1458 DC_CLRBIT(sc, DC_10BTCTRL, 0xFFFF); 1459 if (DC_IS_INTEL(sc)) 1460 dc_apply_fixup(sc, IFM_AUTO); 1461 } else { 1462 if (DC_IS_PNIC(sc)) { 1463 DC_PN_GPIO_CLRBIT(sc, DC_PN_GPIO_SPEEDSEL); 1464 DC_PN_GPIO_SETBIT(sc, DC_PN_GPIO_100TX_LOOP); 1465 DC_CLRBIT(sc, DC_PN_NWAY, DC_PN_NWAY_SPEEDSEL); 1466 } 1467 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL); 1468 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_PCS); 1469 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_SCRAMBLER); 1470 if (DC_IS_INTEL(sc)) { 1471 DC_CLRBIT(sc, DC_SIARESET, DC_SIA_RESET); 1472 DC_CLRBIT(sc, DC_10BTCTRL, 0xFFFF); 1473 if ((media & IFM_GMASK) == IFM_FDX) 1474 DC_SETBIT(sc, DC_10BTCTRL, 0x7F3D); 1475 else 1476 DC_SETBIT(sc, DC_10BTCTRL, 0x7F3F); 1477 DC_SETBIT(sc, DC_SIARESET, DC_SIA_RESET); 1478 DC_CLRBIT(sc, DC_10BTCTRL, 1479 DC_TCTL_AUTONEGENBL); 1480 dc_apply_fixup(sc, 1481 (media & IFM_GMASK) == IFM_FDX ? 1482 IFM_10_T | IFM_FDX : IFM_10_T); 1483 DELAY(20000); 1484 } 1485 } 1486 } 1487 1488 /* 1489 * If this is a Davicom DM9102A card with a DM9801 HomePNA 1490 * PHY and we want HomePNA mode, set the portsel bit to turn 1491 * on the external MII port. 1492 */ 1493 if (DC_IS_DAVICOM(sc)) { 1494 if (IFM_SUBTYPE(media) == IFM_HPNA_1) { 1495 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL); 1496 sc->dc_link = 1; 1497 } else { 1498 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL); 1499 } 1500 } 1501 1502 if ((media & IFM_GMASK) == IFM_FDX) { 1503 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_FULLDUPLEX); 1504 if (sc->dc_pmode == DC_PMODE_SYM && DC_IS_PNIC(sc)) 1505 DC_SETBIT(sc, DC_PN_NWAY, DC_PN_NWAY_DUPLEX); 1506 } else { 1507 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_FULLDUPLEX); 1508 if (sc->dc_pmode == DC_PMODE_SYM && DC_IS_PNIC(sc)) 1509 DC_CLRBIT(sc, DC_PN_NWAY, DC_PN_NWAY_DUPLEX); 1510 } 1511 1512 if (restart) 1513 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_TX_ON | DC_NETCFG_RX_ON); 1514 } 1515 1516 static void 1517 dc_reset(struct dc_softc *sc) 1518 { 1519 int i; 1520 1521 DC_SETBIT(sc, DC_BUSCTL, DC_BUSCTL_RESET); 1522 1523 for (i = 0; i < DC_TIMEOUT; i++) { 1524 DELAY(10); 1525 if (!(CSR_READ_4(sc, DC_BUSCTL) & DC_BUSCTL_RESET)) 1526 break; 1527 } 1528 1529 if (DC_IS_ASIX(sc) || DC_IS_ADMTEK(sc) || DC_IS_CONEXANT(sc) || 1530 DC_IS_XIRCOM(sc) || DC_IS_INTEL(sc)) { 1531 DELAY(10000); 1532 DC_CLRBIT(sc, DC_BUSCTL, DC_BUSCTL_RESET); 1533 i = 0; 1534 } 1535 1536 if (i == DC_TIMEOUT) 1537 if_printf(sc->dc_ifp, "reset never completed!\n"); 1538 1539 /* Wait a little while for the chip to get its brains in order. */ 1540 DELAY(1000); 1541 1542 CSR_WRITE_4(sc, DC_IMR, 0x00000000); 1543 CSR_WRITE_4(sc, DC_BUSCTL, 0x00000000); 1544 CSR_WRITE_4(sc, DC_NETCFG, 0x00000000); 1545 1546 /* 1547 * Bring the SIA out of reset. In some cases, it looks 1548 * like failing to unreset the SIA soon enough gets it 1549 * into a state where it will never come out of reset 1550 * until we reset the whole chip again. 1551 */ 1552 if (DC_IS_INTEL(sc)) { 1553 DC_SETBIT(sc, DC_SIARESET, DC_SIA_RESET); 1554 CSR_WRITE_4(sc, DC_10BTCTRL, 0); 1555 CSR_WRITE_4(sc, DC_WATCHDOG, 0); 1556 } 1557 } 1558 1559 static struct dc_type * 1560 dc_devtype(device_t dev) 1561 { 1562 struct dc_type *t; 1563 u_int32_t rev; 1564 1565 t = dc_devs; 1566 1567 while (t->dc_name != NULL) { 1568 if ((pci_get_vendor(dev) == t->dc_vid) && 1569 (pci_get_device(dev) == t->dc_did)) { 1570 /* Check the PCI revision */ 1571 rev = pci_read_config(dev, DC_PCI_CFRV, 4) & 0xFF; 1572 if (t->dc_did == DC_DEVICEID_98713 && 1573 rev >= DC_REVISION_98713A) 1574 t++; 1575 if (t->dc_did == DC_DEVICEID_98713_CP && 1576 rev >= DC_REVISION_98713A) 1577 t++; 1578 if (t->dc_did == DC_DEVICEID_987x5 && 1579 rev >= DC_REVISION_98715AEC_C) 1580 t++; 1581 if (t->dc_did == DC_DEVICEID_987x5 && 1582 rev >= DC_REVISION_98725) 1583 t++; 1584 if (t->dc_did == DC_DEVICEID_AX88140A && 1585 rev >= DC_REVISION_88141) 1586 t++; 1587 if (t->dc_did == DC_DEVICEID_82C168 && 1588 rev >= DC_REVISION_82C169) 1589 t++; 1590 if (t->dc_did == DC_DEVICEID_DM9102 && 1591 rev >= DC_REVISION_DM9102A) 1592 t++; 1593 /* 1594 * The Microsoft MN-130 has a device ID of 0x0002, 1595 * which happens to be the same as the PNIC 82c168. 1596 * To keep dc_attach() from getting confused, we 1597 * pretend its ID is something different. 1598 * XXX: ideally, dc_attach() should be checking 1599 * vendorid+deviceid together to avoid such 1600 * collisions. 1601 */ 1602 if (t->dc_vid == DC_VENDORID_MICROSOFT && 1603 t->dc_did == DC_DEVICEID_MSMN130) 1604 t++; 1605 return (t); 1606 } 1607 t++; 1608 } 1609 1610 return (NULL); 1611 } 1612 1613 /* 1614 * Probe for a 21143 or clone chip. Check the PCI vendor and device 1615 * IDs against our list and return a device name if we find a match. 1616 * We do a little bit of extra work to identify the exact type of 1617 * chip. The MX98713 and MX98713A have the same PCI vendor/device ID, 1618 * but different revision IDs. The same is true for 98715/98715A 1619 * chips and the 98725, as well as the ASIX and ADMtek chips. In some 1620 * cases, the exact chip revision affects driver behavior. 1621 */ 1622 static int 1623 dc_probe(device_t dev) 1624 { 1625 struct dc_type *t; 1626 1627 t = dc_devtype(dev); 1628 1629 if (t != NULL) { 1630 device_set_desc(dev, t->dc_name); 1631 return (BUS_PROBE_DEFAULT); 1632 } 1633 1634 return (ENXIO); 1635 } 1636 1637 static void 1638 dc_apply_fixup(struct dc_softc *sc, int media) 1639 { 1640 struct dc_mediainfo *m; 1641 u_int8_t *p; 1642 int i; 1643 u_int32_t reg; 1644 1645 m = sc->dc_mi; 1646 1647 while (m != NULL) { 1648 if (m->dc_media == media) 1649 break; 1650 m = m->dc_next; 1651 } 1652 1653 if (m == NULL) 1654 return; 1655 1656 for (i = 0, p = m->dc_reset_ptr; i < m->dc_reset_len; i++, p += 2) { 1657 reg = (p[0] | (p[1] << 8)) << 16; 1658 CSR_WRITE_4(sc, DC_WATCHDOG, reg); 1659 } 1660 1661 for (i = 0, p = m->dc_gp_ptr; i < m->dc_gp_len; i++, p += 2) { 1662 reg = (p[0] | (p[1] << 8)) << 16; 1663 CSR_WRITE_4(sc, DC_WATCHDOG, reg); 1664 } 1665 } 1666 1667 static void 1668 dc_decode_leaf_sia(struct dc_softc *sc, struct dc_eblock_sia *l) 1669 { 1670 struct dc_mediainfo *m; 1671 1672 m = malloc(sizeof(struct dc_mediainfo), M_DEVBUF, M_NOWAIT | M_ZERO); 1673 switch (l->dc_sia_code & ~DC_SIA_CODE_EXT) { 1674 case DC_SIA_CODE_10BT: 1675 m->dc_media = IFM_10_T; 1676 break; 1677 case DC_SIA_CODE_10BT_FDX: 1678 m->dc_media = IFM_10_T | IFM_FDX; 1679 break; 1680 case DC_SIA_CODE_10B2: 1681 m->dc_media = IFM_10_2; 1682 break; 1683 case DC_SIA_CODE_10B5: 1684 m->dc_media = IFM_10_5; 1685 break; 1686 default: 1687 break; 1688 } 1689 1690 /* 1691 * We need to ignore CSR13, CSR14, CSR15 for SIA mode. 1692 * Things apparently already work for cards that do 1693 * supply Media Specific Data. 1694 */ 1695 if (l->dc_sia_code & DC_SIA_CODE_EXT) { 1696 m->dc_gp_len = 2; 1697 m->dc_gp_ptr = 1698 (u_int8_t *)&l->dc_un.dc_sia_ext.dc_sia_gpio_ctl; 1699 } else { 1700 m->dc_gp_len = 2; 1701 m->dc_gp_ptr = 1702 (u_int8_t *)&l->dc_un.dc_sia_noext.dc_sia_gpio_ctl; 1703 } 1704 1705 m->dc_next = sc->dc_mi; 1706 sc->dc_mi = m; 1707 1708 sc->dc_pmode = DC_PMODE_SIA; 1709 } 1710 1711 static void 1712 dc_decode_leaf_sym(struct dc_softc *sc, struct dc_eblock_sym *l) 1713 { 1714 struct dc_mediainfo *m; 1715 1716 m = malloc(sizeof(struct dc_mediainfo), M_DEVBUF, M_NOWAIT | M_ZERO); 1717 if (l->dc_sym_code == DC_SYM_CODE_100BT) 1718 m->dc_media = IFM_100_TX; 1719 1720 if (l->dc_sym_code == DC_SYM_CODE_100BT_FDX) 1721 m->dc_media = IFM_100_TX | IFM_FDX; 1722 1723 m->dc_gp_len = 2; 1724 m->dc_gp_ptr = (u_int8_t *)&l->dc_sym_gpio_ctl; 1725 1726 m->dc_next = sc->dc_mi; 1727 sc->dc_mi = m; 1728 1729 sc->dc_pmode = DC_PMODE_SYM; 1730 } 1731 1732 static void 1733 dc_decode_leaf_mii(struct dc_softc *sc, struct dc_eblock_mii *l) 1734 { 1735 struct dc_mediainfo *m; 1736 u_int8_t *p; 1737 1738 m = malloc(sizeof(struct dc_mediainfo), M_DEVBUF, M_NOWAIT | M_ZERO); 1739 /* We abuse IFM_AUTO to represent MII. */ 1740 m->dc_media = IFM_AUTO; 1741 m->dc_gp_len = l->dc_gpr_len; 1742 1743 p = (u_int8_t *)l; 1744 p += sizeof(struct dc_eblock_mii); 1745 m->dc_gp_ptr = p; 1746 p += 2 * l->dc_gpr_len; 1747 m->dc_reset_len = *p; 1748 p++; 1749 m->dc_reset_ptr = p; 1750 1751 m->dc_next = sc->dc_mi; 1752 sc->dc_mi = m; 1753 } 1754 1755 static void 1756 dc_read_srom(struct dc_softc *sc, int bits) 1757 { 1758 int size; 1759 1760 size = 2 << bits; 1761 sc->dc_srom = malloc(size, M_DEVBUF, M_NOWAIT); 1762 dc_read_eeprom(sc, (caddr_t)sc->dc_srom, 0, (size / 2), 0); 1763 } 1764 1765 static void 1766 dc_parse_21143_srom(struct dc_softc *sc) 1767 { 1768 struct dc_leaf_hdr *lhdr; 1769 struct dc_eblock_hdr *hdr; 1770 int have_mii, i, loff; 1771 char *ptr; 1772 1773 have_mii = 0; 1774 loff = sc->dc_srom[27]; 1775 lhdr = (struct dc_leaf_hdr *)&(sc->dc_srom[loff]); 1776 1777 ptr = (char *)lhdr; 1778 ptr += sizeof(struct dc_leaf_hdr) - 1; 1779 /* 1780 * Look if we got a MII media block. 1781 */ 1782 for (i = 0; i < lhdr->dc_mcnt; i++) { 1783 hdr = (struct dc_eblock_hdr *)ptr; 1784 if (hdr->dc_type == DC_EBLOCK_MII) 1785 have_mii++; 1786 1787 ptr += (hdr->dc_len & 0x7F); 1788 ptr++; 1789 } 1790 1791 /* 1792 * Do the same thing again. Only use SIA and SYM media 1793 * blocks if no MII media block is available. 1794 */ 1795 ptr = (char *)lhdr; 1796 ptr += sizeof(struct dc_leaf_hdr) - 1; 1797 for (i = 0; i < lhdr->dc_mcnt; i++) { 1798 hdr = (struct dc_eblock_hdr *)ptr; 1799 switch (hdr->dc_type) { 1800 case DC_EBLOCK_MII: 1801 dc_decode_leaf_mii(sc, (struct dc_eblock_mii *)hdr); 1802 break; 1803 case DC_EBLOCK_SIA: 1804 if (! have_mii) 1805 dc_decode_leaf_sia(sc, 1806 (struct dc_eblock_sia *)hdr); 1807 break; 1808 case DC_EBLOCK_SYM: 1809 if (! have_mii) 1810 dc_decode_leaf_sym(sc, 1811 (struct dc_eblock_sym *)hdr); 1812 break; 1813 default: 1814 /* Don't care. Yet. */ 1815 break; 1816 } 1817 ptr += (hdr->dc_len & 0x7F); 1818 ptr++; 1819 } 1820 } 1821 1822 static void 1823 dc_dma_map_addr(void *arg, bus_dma_segment_t *segs, int nseg, int error) 1824 { 1825 u_int32_t *paddr; 1826 1827 KASSERT(nseg == 1, ("wrong number of segments, should be 1")); 1828 paddr = arg; 1829 *paddr = segs->ds_addr; 1830 } 1831 1832 /* 1833 * Attach the interface. Allocate softc structures, do ifmedia 1834 * setup and ethernet/BPF attach. 1835 */ 1836 static int 1837 dc_attach(device_t dev) 1838 { 1839 int tmp = 0; 1840 uint32_t eaddr[(ETHER_ADDR_LEN+3)/4]; 1841 u_int32_t command; 1842 struct dc_softc *sc; 1843 struct ifnet *ifp; 1844 u_int32_t revision; 1845 int error = 0, rid, mac_offset; 1846 int i; 1847 u_int8_t *mac; 1848 1849 sc = device_get_softc(dev); 1850 1851 mtx_init(&sc->dc_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 1852 MTX_DEF); 1853 1854 /* 1855 * Map control/status registers. 1856 */ 1857 pci_enable_busmaster(dev); 1858 1859 rid = DC_RID; 1860 sc->dc_res = bus_alloc_resource_any(dev, DC_RES, &rid, RF_ACTIVE); 1861 1862 if (sc->dc_res == NULL) { 1863 device_printf(dev, "couldn't map ports/memory\n"); 1864 error = ENXIO; 1865 goto fail; 1866 } 1867 1868 sc->dc_btag = rman_get_bustag(sc->dc_res); 1869 sc->dc_bhandle = rman_get_bushandle(sc->dc_res); 1870 1871 /* Allocate interrupt. */ 1872 rid = 0; 1873 sc->dc_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 1874 RF_SHAREABLE | RF_ACTIVE); 1875 1876 if (sc->dc_irq == NULL) { 1877 device_printf(dev, "couldn't map interrupt\n"); 1878 error = ENXIO; 1879 goto fail; 1880 } 1881 1882 /* Need this info to decide on a chip type. */ 1883 sc->dc_info = dc_devtype(dev); 1884 revision = pci_read_config(dev, DC_PCI_CFRV, 4) & 0x000000FF; 1885 1886 /* Get the eeprom width, but PNIC and XIRCOM have diff eeprom */ 1887 if (sc->dc_info->dc_did != DC_DEVICEID_82C168 && 1888 sc->dc_info->dc_did != DC_DEVICEID_X3201) 1889 dc_eeprom_width(sc); 1890 1891 switch (sc->dc_info->dc_did) { 1892 case DC_DEVICEID_21143: 1893 sc->dc_type = DC_TYPE_21143; 1894 sc->dc_flags |= DC_TX_POLL | DC_TX_USE_TX_INTR; 1895 sc->dc_flags |= DC_REDUCED_MII_POLL; 1896 /* Save EEPROM contents so we can parse them later. */ 1897 dc_read_srom(sc, sc->dc_romwidth); 1898 break; 1899 case DC_DEVICEID_DM9009: 1900 case DC_DEVICEID_DM9100: 1901 case DC_DEVICEID_DM9102: 1902 sc->dc_type = DC_TYPE_DM9102; 1903 sc->dc_flags |= DC_TX_COALESCE | DC_TX_INTR_ALWAYS; 1904 sc->dc_flags |= DC_REDUCED_MII_POLL | DC_TX_STORENFWD; 1905 sc->dc_flags |= DC_TX_ALIGN; 1906 sc->dc_pmode = DC_PMODE_MII; 1907 /* Increase the latency timer value. */ 1908 command = pci_read_config(dev, DC_PCI_CFLT, 4); 1909 command &= 0xFFFF00FF; 1910 command |= 0x00008000; 1911 pci_write_config(dev, DC_PCI_CFLT, command, 4); 1912 break; 1913 case DC_DEVICEID_AL981: 1914 sc->dc_type = DC_TYPE_AL981; 1915 sc->dc_flags |= DC_TX_USE_TX_INTR; 1916 sc->dc_flags |= DC_TX_ADMTEK_WAR; 1917 sc->dc_pmode = DC_PMODE_MII; 1918 dc_read_srom(sc, sc->dc_romwidth); 1919 break; 1920 case DC_DEVICEID_AN985: 1921 case DC_DEVICEID_ADM9511: 1922 case DC_DEVICEID_ADM9513: 1923 case DC_DEVICEID_DRP32TXD: 1924 case DC_DEVICEID_FA511: 1925 case DC_DEVICEID_FE2500: 1926 case DC_DEVICEID_EN2242: 1927 case DC_DEVICEID_HAWKING_PN672TX: 1928 case DC_DEVICEID_3CSOHOB: 1929 case DC_DEVICEID_MSMN120: 1930 case DC_DEVICEID_MSMN130_FAKE: /* XXX avoid collision with PNIC*/ 1931 sc->dc_type = DC_TYPE_AN985; 1932 sc->dc_flags |= DC_64BIT_HASH; 1933 sc->dc_flags |= DC_TX_USE_TX_INTR; 1934 sc->dc_flags |= DC_TX_ADMTEK_WAR; 1935 sc->dc_pmode = DC_PMODE_MII; 1936 /* Don't read SROM for - auto-loaded on reset */ 1937 break; 1938 case DC_DEVICEID_98713: 1939 case DC_DEVICEID_98713_CP: 1940 if (revision < DC_REVISION_98713A) { 1941 sc->dc_type = DC_TYPE_98713; 1942 } 1943 if (revision >= DC_REVISION_98713A) { 1944 sc->dc_type = DC_TYPE_98713A; 1945 sc->dc_flags |= DC_21143_NWAY; 1946 } 1947 sc->dc_flags |= DC_REDUCED_MII_POLL; 1948 sc->dc_flags |= DC_TX_POLL | DC_TX_USE_TX_INTR; 1949 break; 1950 case DC_DEVICEID_987x5: 1951 case DC_DEVICEID_EN1217: 1952 /* 1953 * Macronix MX98715AEC-C/D/E parts have only a 1954 * 128-bit hash table. We need to deal with these 1955 * in the same manner as the PNIC II so that we 1956 * get the right number of bits out of the 1957 * CRC routine. 1958 */ 1959 if (revision >= DC_REVISION_98715AEC_C && 1960 revision < DC_REVISION_98725) 1961 sc->dc_flags |= DC_128BIT_HASH; 1962 sc->dc_type = DC_TYPE_987x5; 1963 sc->dc_flags |= DC_TX_POLL | DC_TX_USE_TX_INTR; 1964 sc->dc_flags |= DC_REDUCED_MII_POLL | DC_21143_NWAY; 1965 break; 1966 case DC_DEVICEID_98727: 1967 sc->dc_type = DC_TYPE_987x5; 1968 sc->dc_flags |= DC_TX_POLL | DC_TX_USE_TX_INTR; 1969 sc->dc_flags |= DC_REDUCED_MII_POLL | DC_21143_NWAY; 1970 break; 1971 case DC_DEVICEID_82C115: 1972 sc->dc_type = DC_TYPE_PNICII; 1973 sc->dc_flags |= DC_TX_POLL | DC_TX_USE_TX_INTR | DC_128BIT_HASH; 1974 sc->dc_flags |= DC_REDUCED_MII_POLL | DC_21143_NWAY; 1975 break; 1976 case DC_DEVICEID_82C168: 1977 sc->dc_type = DC_TYPE_PNIC; 1978 sc->dc_flags |= DC_TX_STORENFWD | DC_TX_INTR_ALWAYS; 1979 sc->dc_flags |= DC_PNIC_RX_BUG_WAR; 1980 sc->dc_pnic_rx_buf = malloc(DC_RXLEN * 5, M_DEVBUF, M_NOWAIT); 1981 if (revision < DC_REVISION_82C169) 1982 sc->dc_pmode = DC_PMODE_SYM; 1983 break; 1984 case DC_DEVICEID_AX88140A: 1985 sc->dc_type = DC_TYPE_ASIX; 1986 sc->dc_flags |= DC_TX_USE_TX_INTR | DC_TX_INTR_FIRSTFRAG; 1987 sc->dc_flags |= DC_REDUCED_MII_POLL; 1988 sc->dc_pmode = DC_PMODE_MII; 1989 break; 1990 case DC_DEVICEID_X3201: 1991 sc->dc_type = DC_TYPE_XIRCOM; 1992 sc->dc_flags |= DC_TX_INTR_ALWAYS | DC_TX_COALESCE | 1993 DC_TX_ALIGN; 1994 /* 1995 * We don't actually need to coalesce, but we're doing 1996 * it to obtain a double word aligned buffer. 1997 * The DC_TX_COALESCE flag is required. 1998 */ 1999 sc->dc_pmode = DC_PMODE_MII; 2000 break; 2001 case DC_DEVICEID_RS7112: 2002 sc->dc_type = DC_TYPE_CONEXANT; 2003 sc->dc_flags |= DC_TX_INTR_ALWAYS; 2004 sc->dc_flags |= DC_REDUCED_MII_POLL; 2005 sc->dc_pmode = DC_PMODE_MII; 2006 dc_read_srom(sc, sc->dc_romwidth); 2007 break; 2008 default: 2009 device_printf(dev, "unknown device: %x\n", sc->dc_info->dc_did); 2010 break; 2011 } 2012 2013 /* Save the cache line size. */ 2014 if (DC_IS_DAVICOM(sc)) 2015 sc->dc_cachesize = 0; 2016 else 2017 sc->dc_cachesize = pci_read_config(dev, 2018 DC_PCI_CFLT, 4) & 0xFF; 2019 2020 /* Reset the adapter. */ 2021 dc_reset(sc); 2022 2023 /* Take 21143 out of snooze mode */ 2024 if (DC_IS_INTEL(sc) || DC_IS_XIRCOM(sc)) { 2025 command = pci_read_config(dev, DC_PCI_CFDD, 4); 2026 command &= ~(DC_CFDD_SNOOZE_MODE | DC_CFDD_SLEEP_MODE); 2027 pci_write_config(dev, DC_PCI_CFDD, command, 4); 2028 } 2029 2030 /* 2031 * Try to learn something about the supported media. 2032 * We know that ASIX and ADMtek and Davicom devices 2033 * will *always* be using MII media, so that's a no-brainer. 2034 * The tricky ones are the Macronix/PNIC II and the 2035 * Intel 21143. 2036 */ 2037 if (DC_IS_INTEL(sc)) 2038 dc_parse_21143_srom(sc); 2039 else if (DC_IS_MACRONIX(sc) || DC_IS_PNICII(sc)) { 2040 if (sc->dc_type == DC_TYPE_98713) 2041 sc->dc_pmode = DC_PMODE_MII; 2042 else 2043 sc->dc_pmode = DC_PMODE_SYM; 2044 } else if (!sc->dc_pmode) 2045 sc->dc_pmode = DC_PMODE_MII; 2046 2047 /* 2048 * Get station address from the EEPROM. 2049 */ 2050 switch(sc->dc_type) { 2051 case DC_TYPE_98713: 2052 case DC_TYPE_98713A: 2053 case DC_TYPE_987x5: 2054 case DC_TYPE_PNICII: 2055 dc_read_eeprom(sc, (caddr_t)&mac_offset, 2056 (DC_EE_NODEADDR_OFFSET / 2), 1, 0); 2057 dc_read_eeprom(sc, (caddr_t)&eaddr, (mac_offset / 2), 3, 0); 2058 break; 2059 case DC_TYPE_PNIC: 2060 dc_read_eeprom(sc, (caddr_t)&eaddr, 0, 3, 1); 2061 break; 2062 case DC_TYPE_DM9102: 2063 dc_read_eeprom(sc, (caddr_t)&eaddr, DC_EE_NODEADDR, 3, 0); 2064 #ifdef __sparc64__ 2065 /* 2066 * If this is an onboard dc(4) the station address read from 2067 * the EEPROM is all zero and we have to get it from the FCode. 2068 */ 2069 if (eaddr[0] == 0 && (eaddr[1] & ~0xffff) == 0) 2070 OF_getetheraddr(dev, (caddr_t)&eaddr); 2071 #endif 2072 break; 2073 case DC_TYPE_21143: 2074 case DC_TYPE_ASIX: 2075 dc_read_eeprom(sc, (caddr_t)&eaddr, DC_EE_NODEADDR, 3, 0); 2076 break; 2077 case DC_TYPE_AL981: 2078 case DC_TYPE_AN985: 2079 eaddr[0] = CSR_READ_4(sc, DC_AL_PAR0); 2080 eaddr[1] = CSR_READ_4(sc, DC_AL_PAR1); 2081 break; 2082 case DC_TYPE_CONEXANT: 2083 bcopy(sc->dc_srom + DC_CONEXANT_EE_NODEADDR, &eaddr, 2084 ETHER_ADDR_LEN); 2085 break; 2086 case DC_TYPE_XIRCOM: 2087 /* The MAC comes from the CIS. */ 2088 mac = pci_get_ether(dev); 2089 if (!mac) { 2090 device_printf(dev, "No station address in CIS!\n"); 2091 error = ENXIO; 2092 goto fail; 2093 } 2094 bcopy(mac, eaddr, ETHER_ADDR_LEN); 2095 break; 2096 default: 2097 dc_read_eeprom(sc, (caddr_t)&eaddr, DC_EE_NODEADDR, 3, 0); 2098 break; 2099 } 2100 2101 /* Allocate a busdma tag and DMA safe memory for TX/RX descriptors. */ 2102 error = bus_dma_tag_create(NULL, PAGE_SIZE, 0, BUS_SPACE_MAXADDR_32BIT, 2103 BUS_SPACE_MAXADDR, NULL, NULL, sizeof(struct dc_list_data), 1, 2104 sizeof(struct dc_list_data), 0, NULL, NULL, &sc->dc_ltag); 2105 if (error) { 2106 device_printf(dev, "failed to allocate busdma tag\n"); 2107 error = ENXIO; 2108 goto fail; 2109 } 2110 error = bus_dmamem_alloc(sc->dc_ltag, (void **)&sc->dc_ldata, 2111 BUS_DMA_NOWAIT | BUS_DMA_ZERO, &sc->dc_lmap); 2112 if (error) { 2113 device_printf(dev, "failed to allocate DMA safe memory\n"); 2114 error = ENXIO; 2115 goto fail; 2116 } 2117 error = bus_dmamap_load(sc->dc_ltag, sc->dc_lmap, sc->dc_ldata, 2118 sizeof(struct dc_list_data), dc_dma_map_addr, &sc->dc_laddr, 2119 BUS_DMA_NOWAIT); 2120 if (error) { 2121 device_printf(dev, "cannot get address of the descriptors\n"); 2122 error = ENXIO; 2123 goto fail; 2124 } 2125 2126 /* 2127 * Allocate a busdma tag and DMA safe memory for the multicast 2128 * setup frame. 2129 */ 2130 error = bus_dma_tag_create(NULL, PAGE_SIZE, 0, BUS_SPACE_MAXADDR_32BIT, 2131 BUS_SPACE_MAXADDR, NULL, NULL, DC_SFRAME_LEN + DC_MIN_FRAMELEN, 1, 2132 DC_SFRAME_LEN + DC_MIN_FRAMELEN, 0, NULL, NULL, &sc->dc_stag); 2133 if (error) { 2134 device_printf(dev, "failed to allocate busdma tag\n"); 2135 error = ENXIO; 2136 goto fail; 2137 } 2138 error = bus_dmamem_alloc(sc->dc_stag, (void **)&sc->dc_cdata.dc_sbuf, 2139 BUS_DMA_NOWAIT, &sc->dc_smap); 2140 if (error) { 2141 device_printf(dev, "failed to allocate DMA safe memory\n"); 2142 error = ENXIO; 2143 goto fail; 2144 } 2145 error = bus_dmamap_load(sc->dc_stag, sc->dc_smap, sc->dc_cdata.dc_sbuf, 2146 DC_SFRAME_LEN, dc_dma_map_addr, &sc->dc_saddr, BUS_DMA_NOWAIT); 2147 if (error) { 2148 device_printf(dev, "cannot get address of the descriptors\n"); 2149 error = ENXIO; 2150 goto fail; 2151 } 2152 2153 /* Allocate a busdma tag for mbufs. */ 2154 error = bus_dma_tag_create(NULL, 1, 0, BUS_SPACE_MAXADDR_32BIT, 2155 BUS_SPACE_MAXADDR, NULL, NULL, MCLBYTES, DC_TX_LIST_CNT, MCLBYTES, 2156 0, NULL, NULL, &sc->dc_mtag); 2157 if (error) { 2158 device_printf(dev, "failed to allocate busdma tag\n"); 2159 error = ENXIO; 2160 goto fail; 2161 } 2162 2163 /* Create the TX/RX busdma maps. */ 2164 for (i = 0; i < DC_TX_LIST_CNT; i++) { 2165 error = bus_dmamap_create(sc->dc_mtag, 0, 2166 &sc->dc_cdata.dc_tx_map[i]); 2167 if (error) { 2168 device_printf(dev, "failed to init TX ring\n"); 2169 error = ENXIO; 2170 goto fail; 2171 } 2172 } 2173 for (i = 0; i < DC_RX_LIST_CNT; i++) { 2174 error = bus_dmamap_create(sc->dc_mtag, 0, 2175 &sc->dc_cdata.dc_rx_map[i]); 2176 if (error) { 2177 device_printf(dev, "failed to init RX ring\n"); 2178 error = ENXIO; 2179 goto fail; 2180 } 2181 } 2182 error = bus_dmamap_create(sc->dc_mtag, 0, &sc->dc_sparemap); 2183 if (error) { 2184 device_printf(dev, "failed to init RX ring\n"); 2185 error = ENXIO; 2186 goto fail; 2187 } 2188 2189 ifp = sc->dc_ifp = if_alloc(IFT_ETHER); 2190 if (ifp == NULL) { 2191 device_printf(dev, "can not if_alloc()\n"); 2192 error = ENOSPC; 2193 goto fail; 2194 } 2195 ifp->if_softc = sc; 2196 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 2197 /* XXX: bleah, MTU gets overwritten in ether_ifattach() */ 2198 ifp->if_mtu = ETHERMTU; 2199 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 2200 ifp->if_ioctl = dc_ioctl; 2201 ifp->if_start = dc_start; 2202 ifp->if_watchdog = dc_watchdog; 2203 ifp->if_init = dc_init; 2204 IFQ_SET_MAXLEN(&ifp->if_snd, DC_TX_LIST_CNT - 1); 2205 ifp->if_snd.ifq_drv_maxlen = DC_TX_LIST_CNT - 1; 2206 IFQ_SET_READY(&ifp->if_snd); 2207 2208 /* 2209 * Do MII setup. If this is a 21143, check for a PHY on the 2210 * MII bus after applying any necessary fixups to twiddle the 2211 * GPIO bits. If we don't end up finding a PHY, restore the 2212 * old selection (SIA only or SIA/SYM) and attach the dcphy 2213 * driver instead. 2214 */ 2215 if (DC_IS_INTEL(sc)) { 2216 dc_apply_fixup(sc, IFM_AUTO); 2217 tmp = sc->dc_pmode; 2218 sc->dc_pmode = DC_PMODE_MII; 2219 } 2220 2221 /* 2222 * Setup General Purpose port mode and data so the tulip can talk 2223 * to the MII. This needs to be done before mii_phy_probe so that 2224 * we can actually see them. 2225 */ 2226 if (DC_IS_XIRCOM(sc)) { 2227 CSR_WRITE_4(sc, DC_SIAGP, DC_SIAGP_WRITE_EN | DC_SIAGP_INT1_EN | 2228 DC_SIAGP_MD_GP2_OUTPUT | DC_SIAGP_MD_GP0_OUTPUT); 2229 DELAY(10); 2230 CSR_WRITE_4(sc, DC_SIAGP, DC_SIAGP_INT1_EN | 2231 DC_SIAGP_MD_GP2_OUTPUT | DC_SIAGP_MD_GP0_OUTPUT); 2232 DELAY(10); 2233 } 2234 2235 error = mii_phy_probe(dev, &sc->dc_miibus, 2236 dc_ifmedia_upd, dc_ifmedia_sts); 2237 2238 if (error && DC_IS_INTEL(sc)) { 2239 sc->dc_pmode = tmp; 2240 if (sc->dc_pmode != DC_PMODE_SIA) 2241 sc->dc_pmode = DC_PMODE_SYM; 2242 sc->dc_flags |= DC_21143_NWAY; 2243 mii_phy_probe(dev, &sc->dc_miibus, 2244 dc_ifmedia_upd, dc_ifmedia_sts); 2245 /* 2246 * For non-MII cards, we need to have the 21143 2247 * drive the LEDs. Except there are some systems 2248 * like the NEC VersaPro NoteBook PC which have no 2249 * LEDs, and twiddling these bits has adverse effects 2250 * on them. (I.e. you suddenly can't get a link.) 2251 */ 2252 if (pci_read_config(dev, DC_PCI_CSID, 4) != 0x80281033) 2253 sc->dc_flags |= DC_TULIP_LEDS; 2254 error = 0; 2255 } 2256 2257 if (error) { 2258 device_printf(dev, "MII without any PHY!\n"); 2259 goto fail; 2260 } 2261 2262 if (DC_IS_ADMTEK(sc)) { 2263 /* 2264 * Set automatic TX underrun recovery for the ADMtek chips 2265 */ 2266 DC_SETBIT(sc, DC_AL_CR, DC_AL_CR_ATUR); 2267 } 2268 2269 /* 2270 * Tell the upper layer(s) we support long frames. 2271 */ 2272 ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header); 2273 ifp->if_capabilities |= IFCAP_VLAN_MTU; 2274 ifp->if_capenable = ifp->if_capabilities; 2275 #ifdef DEVICE_POLLING 2276 ifp->if_capabilities |= IFCAP_POLLING; 2277 #endif 2278 2279 callout_init_mtx(&sc->dc_stat_ch, &sc->dc_mtx, 0); 2280 2281 /* 2282 * Call MI attach routine. 2283 */ 2284 ether_ifattach(ifp, (caddr_t)eaddr); 2285 2286 /* Hook interrupt last to avoid having to lock softc */ 2287 error = bus_setup_intr(dev, sc->dc_irq, INTR_TYPE_NET | INTR_MPSAFE, 2288 dc_intr, sc, &sc->dc_intrhand); 2289 2290 if (error) { 2291 device_printf(dev, "couldn't set up irq\n"); 2292 ether_ifdetach(ifp); 2293 goto fail; 2294 } 2295 2296 fail: 2297 if (error) 2298 dc_detach(dev); 2299 return (error); 2300 } 2301 2302 /* 2303 * Shutdown hardware and free up resources. This can be called any 2304 * time after the mutex has been initialized. It is called in both 2305 * the error case in attach and the normal detach case so it needs 2306 * to be careful about only freeing resources that have actually been 2307 * allocated. 2308 */ 2309 static int 2310 dc_detach(device_t dev) 2311 { 2312 struct dc_softc *sc; 2313 struct ifnet *ifp; 2314 struct dc_mediainfo *m; 2315 int i; 2316 2317 sc = device_get_softc(dev); 2318 KASSERT(mtx_initialized(&sc->dc_mtx), ("dc mutex not initialized")); 2319 2320 ifp = sc->dc_ifp; 2321 2322 #ifdef DEVICE_POLLING 2323 if (ifp->if_capenable & IFCAP_POLLING) 2324 ether_poll_deregister(ifp); 2325 #endif 2326 2327 /* These should only be active if attach succeeded */ 2328 if (device_is_attached(dev)) { 2329 DC_LOCK(sc); 2330 dc_stop(sc); 2331 DC_UNLOCK(sc); 2332 callout_drain(&sc->dc_stat_ch); 2333 ether_ifdetach(ifp); 2334 } 2335 if (sc->dc_miibus) 2336 device_delete_child(dev, sc->dc_miibus); 2337 bus_generic_detach(dev); 2338 2339 if (sc->dc_intrhand) 2340 bus_teardown_intr(dev, sc->dc_irq, sc->dc_intrhand); 2341 if (sc->dc_irq) 2342 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->dc_irq); 2343 if (sc->dc_res) 2344 bus_release_resource(dev, DC_RES, DC_RID, sc->dc_res); 2345 2346 if (ifp) 2347 if_free(ifp); 2348 2349 if (sc->dc_cdata.dc_sbuf != NULL) 2350 bus_dmamem_free(sc->dc_stag, sc->dc_cdata.dc_sbuf, sc->dc_smap); 2351 if (sc->dc_ldata != NULL) 2352 bus_dmamem_free(sc->dc_ltag, sc->dc_ldata, sc->dc_lmap); 2353 if (sc->dc_mtag) { 2354 for (i = 0; i < DC_TX_LIST_CNT; i++) 2355 if (sc->dc_cdata.dc_tx_map[i] != NULL) 2356 bus_dmamap_destroy(sc->dc_mtag, 2357 sc->dc_cdata.dc_tx_map[i]); 2358 for (i = 0; i < DC_RX_LIST_CNT; i++) 2359 if (sc->dc_cdata.dc_rx_map[i] != NULL) 2360 bus_dmamap_destroy(sc->dc_mtag, 2361 sc->dc_cdata.dc_rx_map[i]); 2362 bus_dmamap_destroy(sc->dc_mtag, sc->dc_sparemap); 2363 } 2364 if (sc->dc_stag) 2365 bus_dma_tag_destroy(sc->dc_stag); 2366 if (sc->dc_mtag) 2367 bus_dma_tag_destroy(sc->dc_mtag); 2368 if (sc->dc_ltag) 2369 bus_dma_tag_destroy(sc->dc_ltag); 2370 2371 free(sc->dc_pnic_rx_buf, M_DEVBUF); 2372 2373 while (sc->dc_mi != NULL) { 2374 m = sc->dc_mi->dc_next; 2375 free(sc->dc_mi, M_DEVBUF); 2376 sc->dc_mi = m; 2377 } 2378 free(sc->dc_srom, M_DEVBUF); 2379 2380 mtx_destroy(&sc->dc_mtx); 2381 2382 return (0); 2383 } 2384 2385 /* 2386 * Initialize the transmit descriptors. 2387 */ 2388 static int 2389 dc_list_tx_init(struct dc_softc *sc) 2390 { 2391 struct dc_chain_data *cd; 2392 struct dc_list_data *ld; 2393 int i, nexti; 2394 2395 cd = &sc->dc_cdata; 2396 ld = sc->dc_ldata; 2397 for (i = 0; i < DC_TX_LIST_CNT; i++) { 2398 if (i == DC_TX_LIST_CNT - 1) 2399 nexti = 0; 2400 else 2401 nexti = i + 1; 2402 ld->dc_tx_list[i].dc_next = htole32(DC_TXDESC(sc, nexti)); 2403 cd->dc_tx_chain[i] = NULL; 2404 ld->dc_tx_list[i].dc_data = 0; 2405 ld->dc_tx_list[i].dc_ctl = 0; 2406 } 2407 2408 cd->dc_tx_prod = cd->dc_tx_cons = cd->dc_tx_cnt = 0; 2409 bus_dmamap_sync(sc->dc_ltag, sc->dc_lmap, 2410 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2411 return (0); 2412 } 2413 2414 2415 /* 2416 * Initialize the RX descriptors and allocate mbufs for them. Note that 2417 * we arrange the descriptors in a closed ring, so that the last descriptor 2418 * points back to the first. 2419 */ 2420 static int 2421 dc_list_rx_init(struct dc_softc *sc) 2422 { 2423 struct dc_chain_data *cd; 2424 struct dc_list_data *ld; 2425 int i, nexti; 2426 2427 cd = &sc->dc_cdata; 2428 ld = sc->dc_ldata; 2429 2430 for (i = 0; i < DC_RX_LIST_CNT; i++) { 2431 if (dc_newbuf(sc, i, 1) != 0) 2432 return (ENOBUFS); 2433 if (i == DC_RX_LIST_CNT - 1) 2434 nexti = 0; 2435 else 2436 nexti = i + 1; 2437 ld->dc_rx_list[i].dc_next = htole32(DC_RXDESC(sc, nexti)); 2438 } 2439 2440 cd->dc_rx_prod = 0; 2441 bus_dmamap_sync(sc->dc_ltag, sc->dc_lmap, 2442 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2443 return (0); 2444 } 2445 2446 static void 2447 dc_dma_map_rxbuf(arg, segs, nseg, mapsize, error) 2448 void *arg; 2449 bus_dma_segment_t *segs; 2450 int nseg; 2451 bus_size_t mapsize; 2452 int error; 2453 { 2454 struct dc_softc *sc; 2455 struct dc_desc *c; 2456 2457 sc = arg; 2458 c = &sc->dc_ldata->dc_rx_list[sc->dc_cdata.dc_rx_cur]; 2459 if (error) { 2460 sc->dc_cdata.dc_rx_err = error; 2461 return; 2462 } 2463 2464 KASSERT(nseg == 1, ("wrong number of segments, should be 1")); 2465 sc->dc_cdata.dc_rx_err = 0; 2466 c->dc_data = htole32(segs->ds_addr); 2467 } 2468 2469 /* 2470 * Initialize an RX descriptor and attach an MBUF cluster. 2471 */ 2472 static int 2473 dc_newbuf(struct dc_softc *sc, int i, int alloc) 2474 { 2475 struct mbuf *m_new; 2476 bus_dmamap_t tmp; 2477 int error; 2478 2479 if (alloc) { 2480 m_new = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR); 2481 if (m_new == NULL) 2482 return (ENOBUFS); 2483 } else { 2484 m_new = sc->dc_cdata.dc_rx_chain[i]; 2485 m_new->m_data = m_new->m_ext.ext_buf; 2486 } 2487 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 2488 m_adj(m_new, sizeof(u_int64_t)); 2489 2490 /* 2491 * If this is a PNIC chip, zero the buffer. This is part 2492 * of the workaround for the receive bug in the 82c168 and 2493 * 82c169 chips. 2494 */ 2495 if (sc->dc_flags & DC_PNIC_RX_BUG_WAR) 2496 bzero(mtod(m_new, char *), m_new->m_len); 2497 2498 /* No need to remap the mbuf if we're reusing it. */ 2499 if (alloc) { 2500 sc->dc_cdata.dc_rx_cur = i; 2501 error = bus_dmamap_load_mbuf(sc->dc_mtag, sc->dc_sparemap, 2502 m_new, dc_dma_map_rxbuf, sc, 0); 2503 if (error) { 2504 m_freem(m_new); 2505 return (error); 2506 } 2507 if (sc->dc_cdata.dc_rx_err != 0) { 2508 m_freem(m_new); 2509 return (sc->dc_cdata.dc_rx_err); 2510 } 2511 bus_dmamap_unload(sc->dc_mtag, sc->dc_cdata.dc_rx_map[i]); 2512 tmp = sc->dc_cdata.dc_rx_map[i]; 2513 sc->dc_cdata.dc_rx_map[i] = sc->dc_sparemap; 2514 sc->dc_sparemap = tmp; 2515 sc->dc_cdata.dc_rx_chain[i] = m_new; 2516 } 2517 2518 sc->dc_ldata->dc_rx_list[i].dc_ctl = htole32(DC_RXCTL_RLINK | DC_RXLEN); 2519 sc->dc_ldata->dc_rx_list[i].dc_status = htole32(DC_RXSTAT_OWN); 2520 bus_dmamap_sync(sc->dc_mtag, sc->dc_cdata.dc_rx_map[i], 2521 BUS_DMASYNC_PREREAD); 2522 bus_dmamap_sync(sc->dc_ltag, sc->dc_lmap, 2523 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2524 return (0); 2525 } 2526 2527 /* 2528 * Grrrrr. 2529 * The PNIC chip has a terrible bug in it that manifests itself during 2530 * periods of heavy activity. The exact mode of failure if difficult to 2531 * pinpoint: sometimes it only happens in promiscuous mode, sometimes it 2532 * will happen on slow machines. The bug is that sometimes instead of 2533 * uploading one complete frame during reception, it uploads what looks 2534 * like the entire contents of its FIFO memory. The frame we want is at 2535 * the end of the whole mess, but we never know exactly how much data has 2536 * been uploaded, so salvaging the frame is hard. 2537 * 2538 * There is only one way to do it reliably, and it's disgusting. 2539 * Here's what we know: 2540 * 2541 * - We know there will always be somewhere between one and three extra 2542 * descriptors uploaded. 2543 * 2544 * - We know the desired received frame will always be at the end of the 2545 * total data upload. 2546 * 2547 * - We know the size of the desired received frame because it will be 2548 * provided in the length field of the status word in the last descriptor. 2549 * 2550 * Here's what we do: 2551 * 2552 * - When we allocate buffers for the receive ring, we bzero() them. 2553 * This means that we know that the buffer contents should be all 2554 * zeros, except for data uploaded by the chip. 2555 * 2556 * - We also force the PNIC chip to upload frames that include the 2557 * ethernet CRC at the end. 2558 * 2559 * - We gather all of the bogus frame data into a single buffer. 2560 * 2561 * - We then position a pointer at the end of this buffer and scan 2562 * backwards until we encounter the first non-zero byte of data. 2563 * This is the end of the received frame. We know we will encounter 2564 * some data at the end of the frame because the CRC will always be 2565 * there, so even if the sender transmits a packet of all zeros, 2566 * we won't be fooled. 2567 * 2568 * - We know the size of the actual received frame, so we subtract 2569 * that value from the current pointer location. This brings us 2570 * to the start of the actual received packet. 2571 * 2572 * - We copy this into an mbuf and pass it on, along with the actual 2573 * frame length. 2574 * 2575 * The performance hit is tremendous, but it beats dropping frames all 2576 * the time. 2577 */ 2578 2579 #define DC_WHOLEFRAME (DC_RXSTAT_FIRSTFRAG | DC_RXSTAT_LASTFRAG) 2580 static void 2581 dc_pnic_rx_bug_war(struct dc_softc *sc, int idx) 2582 { 2583 struct dc_desc *cur_rx; 2584 struct dc_desc *c = NULL; 2585 struct mbuf *m = NULL; 2586 unsigned char *ptr; 2587 int i, total_len; 2588 u_int32_t rxstat = 0; 2589 2590 i = sc->dc_pnic_rx_bug_save; 2591 cur_rx = &sc->dc_ldata->dc_rx_list[idx]; 2592 ptr = sc->dc_pnic_rx_buf; 2593 bzero(ptr, DC_RXLEN * 5); 2594 2595 /* Copy all the bytes from the bogus buffers. */ 2596 while (1) { 2597 c = &sc->dc_ldata->dc_rx_list[i]; 2598 rxstat = le32toh(c->dc_status); 2599 m = sc->dc_cdata.dc_rx_chain[i]; 2600 bcopy(mtod(m, char *), ptr, DC_RXLEN); 2601 ptr += DC_RXLEN; 2602 /* If this is the last buffer, break out. */ 2603 if (i == idx || rxstat & DC_RXSTAT_LASTFRAG) 2604 break; 2605 dc_newbuf(sc, i, 0); 2606 DC_INC(i, DC_RX_LIST_CNT); 2607 } 2608 2609 /* Find the length of the actual receive frame. */ 2610 total_len = DC_RXBYTES(rxstat); 2611 2612 /* Scan backwards until we hit a non-zero byte. */ 2613 while (*ptr == 0x00) 2614 ptr--; 2615 2616 /* Round off. */ 2617 if ((uintptr_t)(ptr) & 0x3) 2618 ptr -= 1; 2619 2620 /* Now find the start of the frame. */ 2621 ptr -= total_len; 2622 if (ptr < sc->dc_pnic_rx_buf) 2623 ptr = sc->dc_pnic_rx_buf; 2624 2625 /* 2626 * Now copy the salvaged frame to the last mbuf and fake up 2627 * the status word to make it look like a successful 2628 * frame reception. 2629 */ 2630 dc_newbuf(sc, i, 0); 2631 bcopy(ptr, mtod(m, char *), total_len); 2632 cur_rx->dc_status = htole32(rxstat | DC_RXSTAT_FIRSTFRAG); 2633 } 2634 2635 /* 2636 * This routine searches the RX ring for dirty descriptors in the 2637 * event that the rxeof routine falls out of sync with the chip's 2638 * current descriptor pointer. This may happen sometimes as a result 2639 * of a "no RX buffer available" condition that happens when the chip 2640 * consumes all of the RX buffers before the driver has a chance to 2641 * process the RX ring. This routine may need to be called more than 2642 * once to bring the driver back in sync with the chip, however we 2643 * should still be getting RX DONE interrupts to drive the search 2644 * for new packets in the RX ring, so we should catch up eventually. 2645 */ 2646 static int 2647 dc_rx_resync(struct dc_softc *sc) 2648 { 2649 struct dc_desc *cur_rx; 2650 int i, pos; 2651 2652 pos = sc->dc_cdata.dc_rx_prod; 2653 2654 for (i = 0; i < DC_RX_LIST_CNT; i++) { 2655 cur_rx = &sc->dc_ldata->dc_rx_list[pos]; 2656 if (!(le32toh(cur_rx->dc_status) & DC_RXSTAT_OWN)) 2657 break; 2658 DC_INC(pos, DC_RX_LIST_CNT); 2659 } 2660 2661 /* If the ring really is empty, then just return. */ 2662 if (i == DC_RX_LIST_CNT) 2663 return (0); 2664 2665 /* We've fallen behing the chip: catch it. */ 2666 sc->dc_cdata.dc_rx_prod = pos; 2667 2668 return (EAGAIN); 2669 } 2670 2671 /* 2672 * A frame has been uploaded: pass the resulting mbuf chain up to 2673 * the higher level protocols. 2674 */ 2675 static void 2676 dc_rxeof(struct dc_softc *sc) 2677 { 2678 struct mbuf *m; 2679 struct ifnet *ifp; 2680 struct dc_desc *cur_rx; 2681 int i, total_len = 0; 2682 u_int32_t rxstat; 2683 2684 DC_LOCK_ASSERT(sc); 2685 2686 ifp = sc->dc_ifp; 2687 i = sc->dc_cdata.dc_rx_prod; 2688 2689 bus_dmamap_sync(sc->dc_ltag, sc->dc_lmap, BUS_DMASYNC_POSTREAD); 2690 while (!(le32toh(sc->dc_ldata->dc_rx_list[i].dc_status) & 2691 DC_RXSTAT_OWN)) { 2692 #ifdef DEVICE_POLLING 2693 if (ifp->if_capenable & IFCAP_POLLING) { 2694 if (sc->rxcycles <= 0) 2695 break; 2696 sc->rxcycles--; 2697 } 2698 #endif 2699 cur_rx = &sc->dc_ldata->dc_rx_list[i]; 2700 rxstat = le32toh(cur_rx->dc_status); 2701 m = sc->dc_cdata.dc_rx_chain[i]; 2702 bus_dmamap_sync(sc->dc_mtag, sc->dc_cdata.dc_rx_map[i], 2703 BUS_DMASYNC_POSTREAD); 2704 total_len = DC_RXBYTES(rxstat); 2705 2706 if (sc->dc_flags & DC_PNIC_RX_BUG_WAR) { 2707 if ((rxstat & DC_WHOLEFRAME) != DC_WHOLEFRAME) { 2708 if (rxstat & DC_RXSTAT_FIRSTFRAG) 2709 sc->dc_pnic_rx_bug_save = i; 2710 if ((rxstat & DC_RXSTAT_LASTFRAG) == 0) { 2711 DC_INC(i, DC_RX_LIST_CNT); 2712 continue; 2713 } 2714 dc_pnic_rx_bug_war(sc, i); 2715 rxstat = le32toh(cur_rx->dc_status); 2716 total_len = DC_RXBYTES(rxstat); 2717 } 2718 } 2719 2720 /* 2721 * If an error occurs, update stats, clear the 2722 * status word and leave the mbuf cluster in place: 2723 * it should simply get re-used next time this descriptor 2724 * comes up in the ring. However, don't report long 2725 * frames as errors since they could be vlans. 2726 */ 2727 if ((rxstat & DC_RXSTAT_RXERR)) { 2728 if (!(rxstat & DC_RXSTAT_GIANT) || 2729 (rxstat & (DC_RXSTAT_CRCERR | DC_RXSTAT_DRIBBLE | 2730 DC_RXSTAT_MIIERE | DC_RXSTAT_COLLSEEN | 2731 DC_RXSTAT_RUNT | DC_RXSTAT_DE))) { 2732 ifp->if_ierrors++; 2733 if (rxstat & DC_RXSTAT_COLLSEEN) 2734 ifp->if_collisions++; 2735 dc_newbuf(sc, i, 0); 2736 if (rxstat & DC_RXSTAT_CRCERR) { 2737 DC_INC(i, DC_RX_LIST_CNT); 2738 continue; 2739 } else { 2740 dc_init_locked(sc); 2741 return; 2742 } 2743 } 2744 } 2745 2746 /* No errors; receive the packet. */ 2747 total_len -= ETHER_CRC_LEN; 2748 #ifdef __i386__ 2749 /* 2750 * On the x86 we do not have alignment problems, so try to 2751 * allocate a new buffer for the receive ring, and pass up 2752 * the one where the packet is already, saving the expensive 2753 * copy done in m_devget(). 2754 * If we are on an architecture with alignment problems, or 2755 * if the allocation fails, then use m_devget and leave the 2756 * existing buffer in the receive ring. 2757 */ 2758 if (dc_quick && dc_newbuf(sc, i, 1) == 0) { 2759 m->m_pkthdr.rcvif = ifp; 2760 m->m_pkthdr.len = m->m_len = total_len; 2761 DC_INC(i, DC_RX_LIST_CNT); 2762 } else 2763 #endif 2764 { 2765 struct mbuf *m0; 2766 2767 m0 = m_devget(mtod(m, char *), total_len, 2768 ETHER_ALIGN, ifp, NULL); 2769 dc_newbuf(sc, i, 0); 2770 DC_INC(i, DC_RX_LIST_CNT); 2771 if (m0 == NULL) { 2772 ifp->if_ierrors++; 2773 continue; 2774 } 2775 m = m0; 2776 } 2777 2778 ifp->if_ipackets++; 2779 DC_UNLOCK(sc); 2780 (*ifp->if_input)(ifp, m); 2781 DC_LOCK(sc); 2782 } 2783 2784 sc->dc_cdata.dc_rx_prod = i; 2785 } 2786 2787 /* 2788 * A frame was downloaded to the chip. It's safe for us to clean up 2789 * the list buffers. 2790 */ 2791 2792 static void 2793 dc_txeof(struct dc_softc *sc) 2794 { 2795 struct dc_desc *cur_tx = NULL; 2796 struct ifnet *ifp; 2797 int idx; 2798 u_int32_t ctl, txstat; 2799 2800 ifp = sc->dc_ifp; 2801 2802 /* 2803 * Go through our tx list and free mbufs for those 2804 * frames that have been transmitted. 2805 */ 2806 bus_dmamap_sync(sc->dc_ltag, sc->dc_lmap, BUS_DMASYNC_POSTREAD); 2807 idx = sc->dc_cdata.dc_tx_cons; 2808 while (idx != sc->dc_cdata.dc_tx_prod) { 2809 2810 cur_tx = &sc->dc_ldata->dc_tx_list[idx]; 2811 txstat = le32toh(cur_tx->dc_status); 2812 ctl = le32toh(cur_tx->dc_ctl); 2813 2814 if (txstat & DC_TXSTAT_OWN) 2815 break; 2816 2817 if (!(ctl & DC_TXCTL_LASTFRAG) || ctl & DC_TXCTL_SETUP) { 2818 if (ctl & DC_TXCTL_SETUP) { 2819 /* 2820 * Yes, the PNIC is so brain damaged 2821 * that it will sometimes generate a TX 2822 * underrun error while DMAing the RX 2823 * filter setup frame. If we detect this, 2824 * we have to send the setup frame again, 2825 * or else the filter won't be programmed 2826 * correctly. 2827 */ 2828 if (DC_IS_PNIC(sc)) { 2829 if (txstat & DC_TXSTAT_ERRSUM) 2830 dc_setfilt(sc); 2831 } 2832 sc->dc_cdata.dc_tx_chain[idx] = NULL; 2833 } 2834 sc->dc_cdata.dc_tx_cnt--; 2835 DC_INC(idx, DC_TX_LIST_CNT); 2836 continue; 2837 } 2838 2839 if (DC_IS_XIRCOM(sc) || DC_IS_CONEXANT(sc)) { 2840 /* 2841 * XXX: Why does my Xircom taunt me so? 2842 * For some reason it likes setting the CARRLOST flag 2843 * even when the carrier is there. wtf?!? 2844 * Who knows, but Conexant chips have the 2845 * same problem. Maybe they took lessons 2846 * from Xircom. 2847 */ 2848 if (/*sc->dc_type == DC_TYPE_21143 &&*/ 2849 sc->dc_pmode == DC_PMODE_MII && 2850 ((txstat & 0xFFFF) & ~(DC_TXSTAT_ERRSUM | 2851 DC_TXSTAT_NOCARRIER))) 2852 txstat &= ~DC_TXSTAT_ERRSUM; 2853 } else { 2854 if (/*sc->dc_type == DC_TYPE_21143 &&*/ 2855 sc->dc_pmode == DC_PMODE_MII && 2856 ((txstat & 0xFFFF) & ~(DC_TXSTAT_ERRSUM | 2857 DC_TXSTAT_NOCARRIER | DC_TXSTAT_CARRLOST))) 2858 txstat &= ~DC_TXSTAT_ERRSUM; 2859 } 2860 2861 if (txstat & DC_TXSTAT_ERRSUM) { 2862 ifp->if_oerrors++; 2863 if (txstat & DC_TXSTAT_EXCESSCOLL) 2864 ifp->if_collisions++; 2865 if (txstat & DC_TXSTAT_LATECOLL) 2866 ifp->if_collisions++; 2867 if (!(txstat & DC_TXSTAT_UNDERRUN)) { 2868 dc_init_locked(sc); 2869 return; 2870 } 2871 } 2872 2873 ifp->if_collisions += (txstat & DC_TXSTAT_COLLCNT) >> 3; 2874 2875 ifp->if_opackets++; 2876 if (sc->dc_cdata.dc_tx_chain[idx] != NULL) { 2877 bus_dmamap_sync(sc->dc_mtag, 2878 sc->dc_cdata.dc_tx_map[idx], 2879 BUS_DMASYNC_POSTWRITE); 2880 bus_dmamap_unload(sc->dc_mtag, 2881 sc->dc_cdata.dc_tx_map[idx]); 2882 m_freem(sc->dc_cdata.dc_tx_chain[idx]); 2883 sc->dc_cdata.dc_tx_chain[idx] = NULL; 2884 } 2885 2886 sc->dc_cdata.dc_tx_cnt--; 2887 DC_INC(idx, DC_TX_LIST_CNT); 2888 } 2889 2890 if (idx != sc->dc_cdata.dc_tx_cons) { 2891 /* Some buffers have been freed. */ 2892 sc->dc_cdata.dc_tx_cons = idx; 2893 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 2894 } 2895 ifp->if_timer = (sc->dc_cdata.dc_tx_cnt == 0) ? 0 : 5; 2896 } 2897 2898 static void 2899 dc_tick(void *xsc) 2900 { 2901 struct dc_softc *sc; 2902 struct mii_data *mii; 2903 struct ifnet *ifp; 2904 u_int32_t r; 2905 2906 sc = xsc; 2907 DC_LOCK_ASSERT(sc); 2908 ifp = sc->dc_ifp; 2909 mii = device_get_softc(sc->dc_miibus); 2910 2911 if (sc->dc_flags & DC_REDUCED_MII_POLL) { 2912 if (sc->dc_flags & DC_21143_NWAY) { 2913 r = CSR_READ_4(sc, DC_10BTSTAT); 2914 if (IFM_SUBTYPE(mii->mii_media_active) == 2915 IFM_100_TX && (r & DC_TSTAT_LS100)) { 2916 sc->dc_link = 0; 2917 mii_mediachg(mii); 2918 } 2919 if (IFM_SUBTYPE(mii->mii_media_active) == 2920 IFM_10_T && (r & DC_TSTAT_LS10)) { 2921 sc->dc_link = 0; 2922 mii_mediachg(mii); 2923 } 2924 if (sc->dc_link == 0) 2925 mii_tick(mii); 2926 } else { 2927 r = CSR_READ_4(sc, DC_ISR); 2928 if ((r & DC_ISR_RX_STATE) == DC_RXSTATE_WAIT && 2929 sc->dc_cdata.dc_tx_cnt == 0) { 2930 mii_tick(mii); 2931 if (!(mii->mii_media_status & IFM_ACTIVE)) 2932 sc->dc_link = 0; 2933 } 2934 } 2935 } else 2936 mii_tick(mii); 2937 2938 /* 2939 * When the init routine completes, we expect to be able to send 2940 * packets right away, and in fact the network code will send a 2941 * gratuitous ARP the moment the init routine marks the interface 2942 * as running. However, even though the MAC may have been initialized, 2943 * there may be a delay of a few seconds before the PHY completes 2944 * autonegotiation and the link is brought up. Any transmissions 2945 * made during that delay will be lost. Dealing with this is tricky: 2946 * we can't just pause in the init routine while waiting for the 2947 * PHY to come ready since that would bring the whole system to 2948 * a screeching halt for several seconds. 2949 * 2950 * What we do here is prevent the TX start routine from sending 2951 * any packets until a link has been established. After the 2952 * interface has been initialized, the tick routine will poll 2953 * the state of the PHY until the IFM_ACTIVE flag is set. Until 2954 * that time, packets will stay in the send queue, and once the 2955 * link comes up, they will be flushed out to the wire. 2956 */ 2957 if (!sc->dc_link && mii->mii_media_status & IFM_ACTIVE && 2958 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) { 2959 sc->dc_link++; 2960 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 2961 dc_start_locked(ifp); 2962 } 2963 2964 if (sc->dc_flags & DC_21143_NWAY && !sc->dc_link) 2965 callout_reset(&sc->dc_stat_ch, hz/10, dc_tick, sc); 2966 else 2967 callout_reset(&sc->dc_stat_ch, hz, dc_tick, sc); 2968 } 2969 2970 /* 2971 * A transmit underrun has occurred. Back off the transmit threshold, 2972 * or switch to store and forward mode if we have to. 2973 */ 2974 static void 2975 dc_tx_underrun(struct dc_softc *sc) 2976 { 2977 u_int32_t isr; 2978 int i; 2979 2980 if (DC_IS_DAVICOM(sc)) 2981 dc_init_locked(sc); 2982 2983 if (DC_IS_INTEL(sc)) { 2984 /* 2985 * The real 21143 requires that the transmitter be idle 2986 * in order to change the transmit threshold or store 2987 * and forward state. 2988 */ 2989 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_TX_ON); 2990 2991 for (i = 0; i < DC_TIMEOUT; i++) { 2992 isr = CSR_READ_4(sc, DC_ISR); 2993 if (isr & DC_ISR_TX_IDLE) 2994 break; 2995 DELAY(10); 2996 } 2997 if (i == DC_TIMEOUT) { 2998 if_printf(sc->dc_ifp, 2999 "failed to force tx to idle state\n"); 3000 dc_init_locked(sc); 3001 } 3002 } 3003 3004 if_printf(sc->dc_ifp, "TX underrun -- "); 3005 sc->dc_txthresh += DC_TXTHRESH_INC; 3006 if (sc->dc_txthresh > DC_TXTHRESH_MAX) { 3007 printf("using store and forward mode\n"); 3008 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_STORENFWD); 3009 } else { 3010 printf("increasing TX threshold\n"); 3011 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_TX_THRESH); 3012 DC_SETBIT(sc, DC_NETCFG, sc->dc_txthresh); 3013 } 3014 3015 if (DC_IS_INTEL(sc)) 3016 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_TX_ON); 3017 } 3018 3019 #ifdef DEVICE_POLLING 3020 static poll_handler_t dc_poll; 3021 3022 static void 3023 dc_poll(struct ifnet *ifp, enum poll_cmd cmd, int count) 3024 { 3025 struct dc_softc *sc = ifp->if_softc; 3026 3027 DC_LOCK(sc); 3028 3029 if (!(ifp->if_drv_flags & IFF_DRV_RUNNING)) { 3030 DC_UNLOCK(sc); 3031 return; 3032 } 3033 3034 sc->rxcycles = count; 3035 dc_rxeof(sc); 3036 dc_txeof(sc); 3037 if (!IFQ_IS_EMPTY(&ifp->if_snd) && 3038 !(ifp->if_drv_flags & IFF_DRV_OACTIVE)) 3039 dc_start_locked(ifp); 3040 3041 if (cmd == POLL_AND_CHECK_STATUS) { /* also check status register */ 3042 u_int32_t status; 3043 3044 status = CSR_READ_4(sc, DC_ISR); 3045 status &= (DC_ISR_RX_WATDOGTIMEO | DC_ISR_RX_NOBUF | 3046 DC_ISR_TX_NOBUF | DC_ISR_TX_IDLE | DC_ISR_TX_UNDERRUN | 3047 DC_ISR_BUS_ERR); 3048 if (!status) { 3049 DC_UNLOCK(sc); 3050 return; 3051 } 3052 /* ack what we have */ 3053 CSR_WRITE_4(sc, DC_ISR, status); 3054 3055 if (status & (DC_ISR_RX_WATDOGTIMEO | DC_ISR_RX_NOBUF)) { 3056 u_int32_t r = CSR_READ_4(sc, DC_FRAMESDISCARDED); 3057 ifp->if_ierrors += (r & 0xffff) + ((r >> 17) & 0x7ff); 3058 3059 if (dc_rx_resync(sc)) 3060 dc_rxeof(sc); 3061 } 3062 /* restart transmit unit if necessary */ 3063 if (status & DC_ISR_TX_IDLE && sc->dc_cdata.dc_tx_cnt) 3064 CSR_WRITE_4(sc, DC_TXSTART, 0xFFFFFFFF); 3065 3066 if (status & DC_ISR_TX_UNDERRUN) 3067 dc_tx_underrun(sc); 3068 3069 if (status & DC_ISR_BUS_ERR) { 3070 if_printf(ifp, "dc_poll: bus error\n"); 3071 dc_reset(sc); 3072 dc_init_locked(sc); 3073 } 3074 } 3075 DC_UNLOCK(sc); 3076 } 3077 #endif /* DEVICE_POLLING */ 3078 3079 static void 3080 dc_intr(void *arg) 3081 { 3082 struct dc_softc *sc; 3083 struct ifnet *ifp; 3084 u_int32_t status; 3085 3086 sc = arg; 3087 3088 if (sc->suspended) 3089 return; 3090 3091 if ((CSR_READ_4(sc, DC_ISR) & DC_INTRS) == 0) 3092 return; 3093 3094 DC_LOCK(sc); 3095 ifp = sc->dc_ifp; 3096 #ifdef DEVICE_POLLING 3097 if (ifp->if_capenable & IFCAP_POLLING) { 3098 DC_UNLOCK(sc); 3099 return; 3100 } 3101 #endif 3102 3103 /* Suppress unwanted interrupts */ 3104 if (!(ifp->if_flags & IFF_UP)) { 3105 if (CSR_READ_4(sc, DC_ISR) & DC_INTRS) 3106 dc_stop(sc); 3107 DC_UNLOCK(sc); 3108 return; 3109 } 3110 3111 /* Disable interrupts. */ 3112 CSR_WRITE_4(sc, DC_IMR, 0x00000000); 3113 3114 while (((status = CSR_READ_4(sc, DC_ISR)) & DC_INTRS) && 3115 status != 0xFFFFFFFF && 3116 (ifp->if_drv_flags & IFF_DRV_RUNNING)) { 3117 3118 CSR_WRITE_4(sc, DC_ISR, status); 3119 3120 if (status & DC_ISR_RX_OK) { 3121 int curpkts; 3122 curpkts = ifp->if_ipackets; 3123 dc_rxeof(sc); 3124 if (curpkts == ifp->if_ipackets) { 3125 while (dc_rx_resync(sc)) 3126 dc_rxeof(sc); 3127 } 3128 } 3129 3130 if (status & (DC_ISR_TX_OK | DC_ISR_TX_NOBUF)) 3131 dc_txeof(sc); 3132 3133 if (status & DC_ISR_TX_IDLE) { 3134 dc_txeof(sc); 3135 if (sc->dc_cdata.dc_tx_cnt) { 3136 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_TX_ON); 3137 CSR_WRITE_4(sc, DC_TXSTART, 0xFFFFFFFF); 3138 } 3139 } 3140 3141 if (status & DC_ISR_TX_UNDERRUN) 3142 dc_tx_underrun(sc); 3143 3144 if ((status & DC_ISR_RX_WATDOGTIMEO) 3145 || (status & DC_ISR_RX_NOBUF)) { 3146 int curpkts; 3147 curpkts = ifp->if_ipackets; 3148 dc_rxeof(sc); 3149 if (curpkts == ifp->if_ipackets) { 3150 while (dc_rx_resync(sc)) 3151 dc_rxeof(sc); 3152 } 3153 } 3154 3155 if (status & DC_ISR_BUS_ERR) { 3156 dc_reset(sc); 3157 dc_init_locked(sc); 3158 } 3159 } 3160 3161 /* Re-enable interrupts. */ 3162 CSR_WRITE_4(sc, DC_IMR, DC_INTRS); 3163 3164 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 3165 dc_start_locked(ifp); 3166 3167 DC_UNLOCK(sc); 3168 } 3169 3170 static void 3171 dc_dma_map_txbuf(arg, segs, nseg, mapsize, error) 3172 void *arg; 3173 bus_dma_segment_t *segs; 3174 int nseg; 3175 bus_size_t mapsize; 3176 int error; 3177 { 3178 struct dc_softc *sc; 3179 struct dc_desc *f; 3180 int cur, first, frag, i; 3181 3182 sc = arg; 3183 if (error) { 3184 sc->dc_cdata.dc_tx_err = error; 3185 return; 3186 } 3187 3188 first = cur = frag = sc->dc_cdata.dc_tx_prod; 3189 for (i = 0; i < nseg; i++) { 3190 if ((sc->dc_flags & DC_TX_ADMTEK_WAR) && 3191 (frag == (DC_TX_LIST_CNT - 1)) && 3192 (first != sc->dc_cdata.dc_tx_first)) { 3193 bus_dmamap_unload(sc->dc_mtag, 3194 sc->dc_cdata.dc_tx_map[first]); 3195 sc->dc_cdata.dc_tx_err = ENOBUFS; 3196 return; 3197 } 3198 3199 f = &sc->dc_ldata->dc_tx_list[frag]; 3200 f->dc_ctl = htole32(DC_TXCTL_TLINK | segs[i].ds_len); 3201 if (i == 0) { 3202 f->dc_status = 0; 3203 f->dc_ctl |= htole32(DC_TXCTL_FIRSTFRAG); 3204 } else 3205 f->dc_status = htole32(DC_TXSTAT_OWN); 3206 f->dc_data = htole32(segs[i].ds_addr); 3207 cur = frag; 3208 DC_INC(frag, DC_TX_LIST_CNT); 3209 } 3210 3211 sc->dc_cdata.dc_tx_err = 0; 3212 sc->dc_cdata.dc_tx_prod = frag; 3213 sc->dc_cdata.dc_tx_cnt += nseg; 3214 sc->dc_ldata->dc_tx_list[cur].dc_ctl |= htole32(DC_TXCTL_LASTFRAG); 3215 sc->dc_cdata.dc_tx_chain[cur] = sc->dc_cdata.dc_tx_mapping; 3216 if (sc->dc_flags & DC_TX_INTR_FIRSTFRAG) 3217 sc->dc_ldata->dc_tx_list[first].dc_ctl |= 3218 htole32(DC_TXCTL_FINT); 3219 if (sc->dc_flags & DC_TX_INTR_ALWAYS) 3220 sc->dc_ldata->dc_tx_list[cur].dc_ctl |= htole32(DC_TXCTL_FINT); 3221 if (sc->dc_flags & DC_TX_USE_TX_INTR && sc->dc_cdata.dc_tx_cnt > 64) 3222 sc->dc_ldata->dc_tx_list[cur].dc_ctl |= htole32(DC_TXCTL_FINT); 3223 sc->dc_ldata->dc_tx_list[first].dc_status = htole32(DC_TXSTAT_OWN); 3224 } 3225 3226 /* 3227 * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data 3228 * pointers to the fragment pointers. 3229 */ 3230 static int 3231 dc_encap(struct dc_softc *sc, struct mbuf **m_head) 3232 { 3233 struct mbuf *m; 3234 int error, idx, chainlen = 0; 3235 3236 /* 3237 * If there's no way we can send any packets, return now. 3238 */ 3239 if (DC_TX_LIST_CNT - sc->dc_cdata.dc_tx_cnt < 6) 3240 return (ENOBUFS); 3241 3242 /* 3243 * Count the number of frags in this chain to see if 3244 * we need to m_defrag. Since the descriptor list is shared 3245 * by all packets, we'll m_defrag long chains so that they 3246 * do not use up the entire list, even if they would fit. 3247 */ 3248 for (m = *m_head; m != NULL; m = m->m_next) 3249 chainlen++; 3250 3251 if ((chainlen > DC_TX_LIST_CNT / 4) || 3252 ((DC_TX_LIST_CNT - (chainlen + sc->dc_cdata.dc_tx_cnt)) < 6)) { 3253 m = m_defrag(*m_head, M_DONTWAIT); 3254 if (m == NULL) 3255 return (ENOBUFS); 3256 *m_head = m; 3257 } 3258 3259 /* 3260 * Start packing the mbufs in this chain into 3261 * the fragment pointers. Stop when we run out 3262 * of fragments or hit the end of the mbuf chain. 3263 */ 3264 idx = sc->dc_cdata.dc_tx_prod; 3265 sc->dc_cdata.dc_tx_mapping = *m_head; 3266 error = bus_dmamap_load_mbuf(sc->dc_mtag, sc->dc_cdata.dc_tx_map[idx], 3267 *m_head, dc_dma_map_txbuf, sc, 0); 3268 if (error) 3269 return (error); 3270 if (sc->dc_cdata.dc_tx_err != 0) 3271 return (sc->dc_cdata.dc_tx_err); 3272 bus_dmamap_sync(sc->dc_mtag, sc->dc_cdata.dc_tx_map[idx], 3273 BUS_DMASYNC_PREWRITE); 3274 bus_dmamap_sync(sc->dc_ltag, sc->dc_lmap, 3275 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3276 return (0); 3277 } 3278 3279 /* 3280 * Main transmit routine. To avoid having to do mbuf copies, we put pointers 3281 * to the mbuf data regions directly in the transmit lists. We also save a 3282 * copy of the pointers since the transmit list fragment pointers are 3283 * physical addresses. 3284 */ 3285 3286 static void 3287 dc_start(struct ifnet *ifp) 3288 { 3289 struct dc_softc *sc; 3290 3291 sc = ifp->if_softc; 3292 DC_LOCK(sc); 3293 dc_start_locked(ifp); 3294 DC_UNLOCK(sc); 3295 } 3296 3297 static void 3298 dc_start_locked(struct ifnet *ifp) 3299 { 3300 struct dc_softc *sc; 3301 struct mbuf *m_head = NULL, *m; 3302 unsigned int queued = 0; 3303 int idx; 3304 3305 sc = ifp->if_softc; 3306 3307 DC_LOCK_ASSERT(sc); 3308 3309 if (!sc->dc_link && ifp->if_snd.ifq_len < 10) 3310 return; 3311 3312 if (ifp->if_drv_flags & IFF_DRV_OACTIVE) 3313 return; 3314 3315 idx = sc->dc_cdata.dc_tx_first = sc->dc_cdata.dc_tx_prod; 3316 3317 while (sc->dc_cdata.dc_tx_chain[idx] == NULL) { 3318 IFQ_DRV_DEQUEUE(&ifp->if_snd, m_head); 3319 if (m_head == NULL) 3320 break; 3321 3322 if (sc->dc_flags & DC_TX_COALESCE && 3323 (m_head->m_next != NULL || 3324 sc->dc_flags & DC_TX_ALIGN)) { 3325 m = m_defrag(m_head, M_DONTWAIT); 3326 if (m == NULL) { 3327 IFQ_DRV_PREPEND(&ifp->if_snd, m_head); 3328 ifp->if_drv_flags |= IFF_DRV_OACTIVE; 3329 break; 3330 } else { 3331 m_head = m; 3332 } 3333 } 3334 3335 if (dc_encap(sc, &m_head)) { 3336 IFQ_DRV_PREPEND(&ifp->if_snd, m_head); 3337 ifp->if_drv_flags |= IFF_DRV_OACTIVE; 3338 break; 3339 } 3340 idx = sc->dc_cdata.dc_tx_prod; 3341 3342 queued++; 3343 /* 3344 * If there's a BPF listener, bounce a copy of this frame 3345 * to him. 3346 */ 3347 BPF_MTAP(ifp, m_head); 3348 3349 if (sc->dc_flags & DC_TX_ONE) { 3350 ifp->if_drv_flags |= IFF_DRV_OACTIVE; 3351 break; 3352 } 3353 } 3354 3355 if (queued > 0) { 3356 /* Transmit */ 3357 if (!(sc->dc_flags & DC_TX_POLL)) 3358 CSR_WRITE_4(sc, DC_TXSTART, 0xFFFFFFFF); 3359 3360 /* 3361 * Set a timeout in case the chip goes out to lunch. 3362 */ 3363 ifp->if_timer = 5; 3364 } 3365 } 3366 3367 static void 3368 dc_init(void *xsc) 3369 { 3370 struct dc_softc *sc = xsc; 3371 3372 DC_LOCK(sc); 3373 dc_init_locked(sc); 3374 DC_UNLOCK(sc); 3375 } 3376 3377 static void 3378 dc_init_locked(struct dc_softc *sc) 3379 { 3380 struct ifnet *ifp = sc->dc_ifp; 3381 struct mii_data *mii; 3382 3383 DC_LOCK_ASSERT(sc); 3384 3385 mii = device_get_softc(sc->dc_miibus); 3386 3387 /* 3388 * Cancel pending I/O and free all RX/TX buffers. 3389 */ 3390 dc_stop(sc); 3391 dc_reset(sc); 3392 3393 /* 3394 * Set cache alignment and burst length. 3395 */ 3396 if (DC_IS_ASIX(sc) || DC_IS_DAVICOM(sc)) 3397 CSR_WRITE_4(sc, DC_BUSCTL, 0); 3398 else 3399 CSR_WRITE_4(sc, DC_BUSCTL, DC_BUSCTL_MRME | DC_BUSCTL_MRLE); 3400 /* 3401 * Evenly share the bus between receive and transmit process. 3402 */ 3403 if (DC_IS_INTEL(sc)) 3404 DC_SETBIT(sc, DC_BUSCTL, DC_BUSCTL_ARBITRATION); 3405 if (DC_IS_DAVICOM(sc) || DC_IS_INTEL(sc)) { 3406 DC_SETBIT(sc, DC_BUSCTL, DC_BURSTLEN_USECA); 3407 } else { 3408 DC_SETBIT(sc, DC_BUSCTL, DC_BURSTLEN_16LONG); 3409 } 3410 if (sc->dc_flags & DC_TX_POLL) 3411 DC_SETBIT(sc, DC_BUSCTL, DC_TXPOLL_1); 3412 switch(sc->dc_cachesize) { 3413 case 32: 3414 DC_SETBIT(sc, DC_BUSCTL, DC_CACHEALIGN_32LONG); 3415 break; 3416 case 16: 3417 DC_SETBIT(sc, DC_BUSCTL, DC_CACHEALIGN_16LONG); 3418 break; 3419 case 8: 3420 DC_SETBIT(sc, DC_BUSCTL, DC_CACHEALIGN_8LONG); 3421 break; 3422 case 0: 3423 default: 3424 DC_SETBIT(sc, DC_BUSCTL, DC_CACHEALIGN_NONE); 3425 break; 3426 } 3427 3428 if (sc->dc_flags & DC_TX_STORENFWD) 3429 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_STORENFWD); 3430 else { 3431 if (sc->dc_txthresh > DC_TXTHRESH_MAX) { 3432 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_STORENFWD); 3433 } else { 3434 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_STORENFWD); 3435 DC_SETBIT(sc, DC_NETCFG, sc->dc_txthresh); 3436 } 3437 } 3438 3439 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_NO_RXCRC); 3440 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_TX_BACKOFF); 3441 3442 if (DC_IS_MACRONIX(sc) || DC_IS_PNICII(sc)) { 3443 /* 3444 * The app notes for the 98713 and 98715A say that 3445 * in order to have the chips operate properly, a magic 3446 * number must be written to CSR16. Macronix does not 3447 * document the meaning of these bits so there's no way 3448 * to know exactly what they do. The 98713 has a magic 3449 * number all its own; the rest all use a different one. 3450 */ 3451 DC_CLRBIT(sc, DC_MX_MAGICPACKET, 0xFFFF0000); 3452 if (sc->dc_type == DC_TYPE_98713) 3453 DC_SETBIT(sc, DC_MX_MAGICPACKET, DC_MX_MAGIC_98713); 3454 else 3455 DC_SETBIT(sc, DC_MX_MAGICPACKET, DC_MX_MAGIC_98715); 3456 } 3457 3458 if (DC_IS_XIRCOM(sc)) { 3459 /* 3460 * setup General Purpose Port mode and data so the tulip 3461 * can talk to the MII. 3462 */ 3463 CSR_WRITE_4(sc, DC_SIAGP, DC_SIAGP_WRITE_EN | DC_SIAGP_INT1_EN | 3464 DC_SIAGP_MD_GP2_OUTPUT | DC_SIAGP_MD_GP0_OUTPUT); 3465 DELAY(10); 3466 CSR_WRITE_4(sc, DC_SIAGP, DC_SIAGP_INT1_EN | 3467 DC_SIAGP_MD_GP2_OUTPUT | DC_SIAGP_MD_GP0_OUTPUT); 3468 DELAY(10); 3469 } 3470 3471 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_TX_THRESH); 3472 DC_SETBIT(sc, DC_NETCFG, DC_TXTHRESH_MIN); 3473 3474 /* Init circular RX list. */ 3475 if (dc_list_rx_init(sc) == ENOBUFS) { 3476 if_printf(ifp, 3477 "initialization failed: no memory for rx buffers\n"); 3478 dc_stop(sc); 3479 return; 3480 } 3481 3482 /* 3483 * Init TX descriptors. 3484 */ 3485 dc_list_tx_init(sc); 3486 3487 /* 3488 * Load the address of the RX list. 3489 */ 3490 CSR_WRITE_4(sc, DC_RXADDR, DC_RXDESC(sc, 0)); 3491 CSR_WRITE_4(sc, DC_TXADDR, DC_TXDESC(sc, 0)); 3492 3493 /* 3494 * Enable interrupts. 3495 */ 3496 #ifdef DEVICE_POLLING 3497 /* 3498 * ... but only if we are not polling, and make sure they are off in 3499 * the case of polling. Some cards (e.g. fxp) turn interrupts on 3500 * after a reset. 3501 */ 3502 if (ifp->if_capenable & IFCAP_POLLING) 3503 CSR_WRITE_4(sc, DC_IMR, 0x00000000); 3504 else 3505 #endif 3506 CSR_WRITE_4(sc, DC_IMR, DC_INTRS); 3507 CSR_WRITE_4(sc, DC_ISR, 0xFFFFFFFF); 3508 3509 /* Enable transmitter. */ 3510 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_TX_ON); 3511 3512 /* 3513 * If this is an Intel 21143 and we're not using the 3514 * MII port, program the LED control pins so we get 3515 * link and activity indications. 3516 */ 3517 if (sc->dc_flags & DC_TULIP_LEDS) { 3518 CSR_WRITE_4(sc, DC_WATCHDOG, 3519 DC_WDOG_CTLWREN | DC_WDOG_LINK | DC_WDOG_ACTIVITY); 3520 CSR_WRITE_4(sc, DC_WATCHDOG, 0); 3521 } 3522 3523 /* 3524 * Load the RX/multicast filter. We do this sort of late 3525 * because the filter programming scheme on the 21143 and 3526 * some clones requires DMAing a setup frame via the TX 3527 * engine, and we need the transmitter enabled for that. 3528 */ 3529 dc_setfilt(sc); 3530 3531 /* Enable receiver. */ 3532 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_ON); 3533 CSR_WRITE_4(sc, DC_RXSTART, 0xFFFFFFFF); 3534 3535 mii_mediachg(mii); 3536 dc_setcfg(sc, sc->dc_if_media); 3537 3538 ifp->if_drv_flags |= IFF_DRV_RUNNING; 3539 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 3540 3541 /* Don't start the ticker if this is a homePNA link. */ 3542 if (IFM_SUBTYPE(mii->mii_media.ifm_media) == IFM_HPNA_1) 3543 sc->dc_link = 1; 3544 else { 3545 if (sc->dc_flags & DC_21143_NWAY) 3546 callout_reset(&sc->dc_stat_ch, hz/10, dc_tick, sc); 3547 else 3548 callout_reset(&sc->dc_stat_ch, hz, dc_tick, sc); 3549 } 3550 } 3551 3552 /* 3553 * Set media options. 3554 */ 3555 static int 3556 dc_ifmedia_upd(struct ifnet *ifp) 3557 { 3558 struct dc_softc *sc; 3559 struct mii_data *mii; 3560 struct ifmedia *ifm; 3561 3562 sc = ifp->if_softc; 3563 mii = device_get_softc(sc->dc_miibus); 3564 DC_LOCK(sc); 3565 mii_mediachg(mii); 3566 ifm = &mii->mii_media; 3567 3568 if (DC_IS_DAVICOM(sc) && 3569 IFM_SUBTYPE(ifm->ifm_media) == IFM_HPNA_1) 3570 dc_setcfg(sc, ifm->ifm_media); 3571 else 3572 sc->dc_link = 0; 3573 DC_UNLOCK(sc); 3574 3575 return (0); 3576 } 3577 3578 /* 3579 * Report current media status. 3580 */ 3581 static void 3582 dc_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 3583 { 3584 struct dc_softc *sc; 3585 struct mii_data *mii; 3586 struct ifmedia *ifm; 3587 3588 sc = ifp->if_softc; 3589 mii = device_get_softc(sc->dc_miibus); 3590 DC_LOCK(sc); 3591 mii_pollstat(mii); 3592 ifm = &mii->mii_media; 3593 if (DC_IS_DAVICOM(sc)) { 3594 if (IFM_SUBTYPE(ifm->ifm_media) == IFM_HPNA_1) { 3595 ifmr->ifm_active = ifm->ifm_media; 3596 ifmr->ifm_status = 0; 3597 return; 3598 } 3599 } 3600 ifmr->ifm_active = mii->mii_media_active; 3601 ifmr->ifm_status = mii->mii_media_status; 3602 DC_UNLOCK(sc); 3603 } 3604 3605 static int 3606 dc_ioctl(struct ifnet *ifp, u_long command, caddr_t data) 3607 { 3608 struct dc_softc *sc = ifp->if_softc; 3609 struct ifreq *ifr = (struct ifreq *)data; 3610 struct mii_data *mii; 3611 int error = 0; 3612 3613 switch (command) { 3614 case SIOCSIFFLAGS: 3615 DC_LOCK(sc); 3616 if (ifp->if_flags & IFF_UP) { 3617 int need_setfilt = (ifp->if_flags ^ sc->dc_if_flags) & 3618 (IFF_PROMISC | IFF_ALLMULTI); 3619 3620 if (ifp->if_drv_flags & IFF_DRV_RUNNING) { 3621 if (need_setfilt) 3622 dc_setfilt(sc); 3623 } else { 3624 sc->dc_txthresh = 0; 3625 dc_init_locked(sc); 3626 } 3627 } else { 3628 if (ifp->if_drv_flags & IFF_DRV_RUNNING) 3629 dc_stop(sc); 3630 } 3631 sc->dc_if_flags = ifp->if_flags; 3632 DC_UNLOCK(sc); 3633 error = 0; 3634 break; 3635 case SIOCADDMULTI: 3636 case SIOCDELMULTI: 3637 DC_LOCK(sc); 3638 dc_setfilt(sc); 3639 DC_UNLOCK(sc); 3640 error = 0; 3641 break; 3642 case SIOCGIFMEDIA: 3643 case SIOCSIFMEDIA: 3644 mii = device_get_softc(sc->dc_miibus); 3645 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 3646 break; 3647 case SIOCSIFCAP: 3648 #ifdef DEVICE_POLLING 3649 if (ifr->ifr_reqcap & IFCAP_POLLING && 3650 !(ifp->if_capenable & IFCAP_POLLING)) { 3651 error = ether_poll_register(dc_poll, ifp); 3652 if (error) 3653 return(error); 3654 DC_LOCK(sc); 3655 /* Disable interrupts */ 3656 CSR_WRITE_4(sc, DC_IMR, 0x00000000); 3657 ifp->if_capenable |= IFCAP_POLLING; 3658 DC_UNLOCK(sc); 3659 return (error); 3660 3661 } 3662 if (!(ifr->ifr_reqcap & IFCAP_POLLING) && 3663 ifp->if_capenable & IFCAP_POLLING) { 3664 error = ether_poll_deregister(ifp); 3665 /* Enable interrupts. */ 3666 DC_LOCK(sc); 3667 CSR_WRITE_4(sc, DC_IMR, DC_INTRS); 3668 ifp->if_capenable &= ~IFCAP_POLLING; 3669 DC_UNLOCK(sc); 3670 return (error); 3671 } 3672 #endif /* DEVICE_POLLING */ 3673 break; 3674 default: 3675 error = ether_ioctl(ifp, command, data); 3676 break; 3677 } 3678 3679 return (error); 3680 } 3681 3682 static void 3683 dc_watchdog(struct ifnet *ifp) 3684 { 3685 struct dc_softc *sc; 3686 3687 sc = ifp->if_softc; 3688 3689 DC_LOCK(sc); 3690 3691 ifp->if_oerrors++; 3692 if_printf(ifp, "watchdog timeout\n"); 3693 3694 dc_stop(sc); 3695 dc_reset(sc); 3696 dc_init_locked(sc); 3697 3698 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 3699 dc_start_locked(ifp); 3700 3701 DC_UNLOCK(sc); 3702 } 3703 3704 /* 3705 * Stop the adapter and free any mbufs allocated to the 3706 * RX and TX lists. 3707 */ 3708 static void 3709 dc_stop(struct dc_softc *sc) 3710 { 3711 struct ifnet *ifp; 3712 struct dc_list_data *ld; 3713 struct dc_chain_data *cd; 3714 int i; 3715 u_int32_t ctl; 3716 3717 DC_LOCK_ASSERT(sc); 3718 3719 ifp = sc->dc_ifp; 3720 ifp->if_timer = 0; 3721 ld = sc->dc_ldata; 3722 cd = &sc->dc_cdata; 3723 3724 callout_stop(&sc->dc_stat_ch); 3725 3726 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE); 3727 3728 DC_CLRBIT(sc, DC_NETCFG, (DC_NETCFG_RX_ON | DC_NETCFG_TX_ON)); 3729 CSR_WRITE_4(sc, DC_IMR, 0x00000000); 3730 CSR_WRITE_4(sc, DC_TXADDR, 0x00000000); 3731 CSR_WRITE_4(sc, DC_RXADDR, 0x00000000); 3732 sc->dc_link = 0; 3733 3734 /* 3735 * Free data in the RX lists. 3736 */ 3737 for (i = 0; i < DC_RX_LIST_CNT; i++) { 3738 if (cd->dc_rx_chain[i] != NULL) { 3739 m_freem(cd->dc_rx_chain[i]); 3740 cd->dc_rx_chain[i] = NULL; 3741 } 3742 } 3743 bzero(&ld->dc_rx_list, sizeof(ld->dc_rx_list)); 3744 3745 /* 3746 * Free the TX list buffers. 3747 */ 3748 for (i = 0; i < DC_TX_LIST_CNT; i++) { 3749 if (cd->dc_tx_chain[i] != NULL) { 3750 ctl = le32toh(ld->dc_tx_list[i].dc_ctl); 3751 if ((ctl & DC_TXCTL_SETUP) || 3752 !(ctl & DC_TXCTL_LASTFRAG)) { 3753 cd->dc_tx_chain[i] = NULL; 3754 continue; 3755 } 3756 bus_dmamap_unload(sc->dc_mtag, cd->dc_tx_map[i]); 3757 m_freem(cd->dc_tx_chain[i]); 3758 cd->dc_tx_chain[i] = NULL; 3759 } 3760 } 3761 bzero(&ld->dc_tx_list, sizeof(ld->dc_tx_list)); 3762 } 3763 3764 /* 3765 * Device suspend routine. Stop the interface and save some PCI 3766 * settings in case the BIOS doesn't restore them properly on 3767 * resume. 3768 */ 3769 static int 3770 dc_suspend(device_t dev) 3771 { 3772 struct dc_softc *sc; 3773 3774 sc = device_get_softc(dev); 3775 DC_LOCK(sc); 3776 dc_stop(sc); 3777 sc->suspended = 1; 3778 DC_UNLOCK(sc); 3779 3780 return (0); 3781 } 3782 3783 /* 3784 * Device resume routine. Restore some PCI settings in case the BIOS 3785 * doesn't, re-enable busmastering, and restart the interface if 3786 * appropriate. 3787 */ 3788 static int 3789 dc_resume(device_t dev) 3790 { 3791 struct dc_softc *sc; 3792 struct ifnet *ifp; 3793 3794 sc = device_get_softc(dev); 3795 ifp = sc->dc_ifp; 3796 3797 /* reinitialize interface if necessary */ 3798 DC_LOCK(sc); 3799 if (ifp->if_flags & IFF_UP) 3800 dc_init_locked(sc); 3801 3802 sc->suspended = 0; 3803 DC_UNLOCK(sc); 3804 3805 return (0); 3806 } 3807 3808 /* 3809 * Stop all chip I/O so that the kernel's probe routines don't 3810 * get confused by errant DMAs when rebooting. 3811 */ 3812 static void 3813 dc_shutdown(device_t dev) 3814 { 3815 struct dc_softc *sc; 3816 3817 sc = device_get_softc(dev); 3818 3819 DC_LOCK(sc); 3820 dc_stop(sc); 3821 DC_UNLOCK(sc); 3822 } 3823