1 /* 2 * Copyright (c) 1997, 1998, 1999 3 * Bill Paul <wpaul@ee.columbia.edu>. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 3. All advertising materials mentioning features or use of this software 14 * must display the following acknowledgement: 15 * This product includes software developed by Bill Paul. 16 * 4. Neither the name of the author nor the names of any co-contributors 17 * may be used to endorse or promote products derived from this software 18 * without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30 * THE POSSIBILITY OF SUCH DAMAGE. 31 * 32 * $FreeBSD$ 33 */ 34 35 /* 36 * DEC "tulip" clone ethernet driver. Supports the DEC/Intel 21143 37 * series chips and several workalikes including the following: 38 * 39 * Macronix 98713/98715/98725 PMAC (www.macronix.com) 40 * Macronix/Lite-On 82c115 PNIC II (www.macronix.com) 41 * Lite-On 82c168/82c169 PNIC (www.litecom.com) 42 * ASIX Electronics AX88140A (www.asix.com.tw) 43 * ASIX Electronics AX88141 (www.asix.com.tw) 44 * ADMtek AL981 (www.admtek.com.tw) 45 * ADMtek AN985 (www.admtek.com.tw) 46 * Davicom DM9100, DM9102, DM9102A (www.davicom8.com) 47 * 48 * Datasheets for the 21143 are available at developer.intel.com. 49 * Datasheets for the clone parts can be found at their respective sites. 50 * (Except for the PNIC; see www.freebsd.org/~wpaul/PNIC/pnic.ps.gz.) 51 * The PNIC II is essentially a Macronix 98715A chip; the only difference 52 * worth noting is that its multicast hash table is only 128 bits wide 53 * instead of 512. 54 * 55 * Written by Bill Paul <wpaul@ee.columbia.edu> 56 * Electrical Engineering Department 57 * Columbia University, New York City 58 */ 59 60 /* 61 * The Intel 21143 is the successor to the DEC 21140. It is basically 62 * the same as the 21140 but with a few new features. The 21143 supports 63 * three kinds of media attachments: 64 * 65 * o MII port, for 10Mbps and 100Mbps support and NWAY 66 * autonegotiation provided by an external PHY. 67 * o SYM port, for symbol mode 100Mbps support. 68 * o 10baseT port. 69 * o AUI/BNC port. 70 * 71 * The 100Mbps SYM port and 10baseT port can be used together in 72 * combination with the internal NWAY support to create a 10/100 73 * autosensing configuration. 74 * 75 * Knowing which media is available on a given card is tough: you're 76 * supposed to go slogging through the EEPROM looking for media 77 * description structures. Unfortunately, some card vendors that use 78 * the 21143 don't obey the DEC SROM spec correctly, which means that 79 * what you find in the EEPROM may not agree with reality. Fortunately, 80 * the 21143 provides us a way to get around this issue: lurking in 81 * PCI configuration space is the Configuration Wake-Up Command Register. 82 * This register is loaded with a value from the EEPROM when wake on LAN 83 * mode is enabled; this value tells us quite clearly what kind of media 84 * is attached to the NIC. The main purpose of this register is to tell 85 * the NIC what media to scan when in wake on LAN mode, however by 86 * forcibly enabling wake on LAN mode, we can use to learn what kind of 87 * media a given NIC has available and adapt ourselves accordingly. 88 * 89 * Of course, if the media description blocks in the EEPROM are bogus. 90 * what are the odds that the CWUC aren't bogus as well, right? Well, 91 * the CWUC value is more likely to be correct since wake on LAN mode 92 * won't work correctly without it, and wake on LAN is a big selling 93 * point these days. It's also harder to screw up a single byte than 94 * a whole media descriptor block. 95 * 96 * Note that not all tulip workalikes are handled in this driver: we only 97 * deal with those which are relatively well behaved. The Winbond is 98 * handled separately due to its different register offsets and the 99 * special handling needed for its various bugs. The PNIC is handled 100 * here, but I'm not thrilled about it. 101 * 102 * All of the workalike chips use some form of MII transceiver support 103 * with the exception of the Macronix chips, which also have a SYM port. 104 * The ASIX AX88140A is also documented to have a SYM port, but all 105 * the cards I've seen use an MII transceiver, probably because the 106 * AX88140A doesn't support internal NWAY. 107 */ 108 109 #include <sys/param.h> 110 #include <sys/systm.h> 111 #include <sys/sockio.h> 112 #include <sys/mbuf.h> 113 #include <sys/malloc.h> 114 #include <sys/kernel.h> 115 #include <sys/socket.h> 116 117 #include <net/if.h> 118 #include <net/if_arp.h> 119 #include <net/ethernet.h> 120 #include <net/if_dl.h> 121 #include <net/if_media.h> 122 123 #include <net/bpf.h> 124 125 #include <vm/vm.h> /* for vtophys */ 126 #include <vm/pmap.h> /* for vtophys */ 127 #include <machine/clock.h> /* for DELAY */ 128 #include <machine/bus_pio.h> 129 #include <machine/bus_memio.h> 130 #include <machine/bus.h> 131 #include <machine/resource.h> 132 #include <sys/bus.h> 133 #include <sys/rman.h> 134 135 #include <dev/mii/mii.h> 136 #include <dev/mii/miivar.h> 137 138 #include <pci/pcireg.h> 139 #include <pci/pcivar.h> 140 141 #define DC_USEIOSPACE 142 143 #include <pci/if_dcreg.h> 144 145 MODULE_DEPEND(dc, miibus, 1, 1, 1); 146 147 /* "controller miibus0" required. See GENERIC if you get errors here. */ 148 #include "miibus_if.h" 149 150 #ifndef lint 151 static const char rcsid[] = 152 "$FreeBSD$"; 153 #endif 154 155 /* 156 * Various supported device vendors/types and their names. 157 */ 158 static struct dc_type dc_devs[] = { 159 { DC_VENDORID_DEC, DC_DEVICEID_21143, 160 "Intel 21143 10/100BaseTX" }, 161 { DC_VENDORID_DAVICOM, DC_DEVICEID_DM9100, 162 "Davicom DM9100 10/100BaseTX" }, 163 { DC_VENDORID_DAVICOM, DC_DEVICEID_DM9102, 164 "Davicom DM9102 10/100BaseTX" }, 165 { DC_VENDORID_DAVICOM, DC_DEVICEID_DM9102, 166 "Davicom DM9102A 10/100BaseTX" }, 167 { DC_VENDORID_ADMTEK, DC_DEVICEID_AL981, 168 "ADMtek AL981 10/100BaseTX" }, 169 { DC_VENDORID_ADMTEK, DC_DEVICEID_AN985, 170 "ADMtek AN985 10/100BaseTX" }, 171 { DC_VENDORID_ASIX, DC_DEVICEID_AX88140A, 172 "ASIX AX88140A 10/100BaseTX" }, 173 { DC_VENDORID_ASIX, DC_DEVICEID_AX88140A, 174 "ASIX AX88141 10/100BaseTX" }, 175 { DC_VENDORID_MX, DC_DEVICEID_98713, 176 "Macronix 98713 10/100BaseTX" }, 177 { DC_VENDORID_MX, DC_DEVICEID_98713, 178 "Macronix 98713A 10/100BaseTX" }, 179 { DC_VENDORID_CP, DC_DEVICEID_98713_CP, 180 "Compex RL100-TX 10/100BaseTX" }, 181 { DC_VENDORID_CP, DC_DEVICEID_98713_CP, 182 "Compex RL100-TX 10/100BaseTX" }, 183 { DC_VENDORID_MX, DC_DEVICEID_987x5, 184 "Macronix 98715/98715A 10/100BaseTX" }, 185 { DC_VENDORID_MX, DC_DEVICEID_987x5, 186 "Macronix 98725 10/100BaseTX" }, 187 { DC_VENDORID_LO, DC_DEVICEID_82C115, 188 "LC82C115 PNIC II 10/100BaseTX" }, 189 { DC_VENDORID_LO, DC_DEVICEID_82C168, 190 "82c168 PNIC 10/100BaseTX" }, 191 { DC_VENDORID_LO, DC_DEVICEID_82C168, 192 "82c169 PNIC 10/100BaseTX" }, 193 { 0, 0, NULL } 194 }; 195 196 static int dc_probe __P((device_t)); 197 static int dc_attach __P((device_t)); 198 static int dc_detach __P((device_t)); 199 static void dc_acpi __P((device_t)); 200 static struct dc_type *dc_devtype __P((device_t)); 201 static int dc_newbuf __P((struct dc_softc *, int, struct mbuf *)); 202 static int dc_encap __P((struct dc_softc *, struct mbuf *, 203 u_int32_t *)); 204 static int dc_coal __P((struct dc_softc *, struct mbuf **)); 205 static void dc_pnic_rx_bug_war __P((struct dc_softc *, int)); 206 static int dc_rx_resync __P((struct dc_softc *)); 207 static void dc_rxeof __P((struct dc_softc *)); 208 static void dc_txeof __P((struct dc_softc *)); 209 static void dc_tick __P((void *)); 210 static void dc_intr __P((void *)); 211 static void dc_start __P((struct ifnet *)); 212 static int dc_ioctl __P((struct ifnet *, u_long, caddr_t)); 213 static void dc_init __P((void *)); 214 static void dc_stop __P((struct dc_softc *)); 215 static void dc_watchdog __P((struct ifnet *)); 216 static void dc_shutdown __P((device_t)); 217 static int dc_ifmedia_upd __P((struct ifnet *)); 218 static void dc_ifmedia_sts __P((struct ifnet *, struct ifmediareq *)); 219 220 static void dc_delay __P((struct dc_softc *)); 221 static void dc_eeprom_idle __P((struct dc_softc *)); 222 static void dc_eeprom_putbyte __P((struct dc_softc *, int)); 223 static void dc_eeprom_getword __P((struct dc_softc *, int, u_int16_t *)); 224 static void dc_eeprom_getword_pnic 225 __P((struct dc_softc *, int, u_int16_t *)); 226 static void dc_read_eeprom __P((struct dc_softc *, caddr_t, int, 227 int, int)); 228 229 static void dc_mii_writebit __P((struct dc_softc *, int)); 230 static int dc_mii_readbit __P((struct dc_softc *)); 231 static void dc_mii_sync __P((struct dc_softc *)); 232 static void dc_mii_send __P((struct dc_softc *, u_int32_t, int)); 233 static int dc_mii_readreg __P((struct dc_softc *, struct dc_mii_frame *)); 234 static int dc_mii_writereg __P((struct dc_softc *, struct dc_mii_frame *)); 235 static int dc_miibus_readreg __P((device_t, int, int)); 236 static int dc_miibus_writereg __P((device_t, int, int, int)); 237 static void dc_miibus_statchg __P((device_t)); 238 static void dc_miibus_mediainit __P((device_t)); 239 240 static void dc_setcfg __P((struct dc_softc *, int)); 241 static u_int32_t dc_crc_le __P((struct dc_softc *, caddr_t)); 242 static u_int32_t dc_crc_be __P((caddr_t)); 243 static void dc_setfilt_21143 __P((struct dc_softc *)); 244 static void dc_setfilt_asix __P((struct dc_softc *)); 245 static void dc_setfilt_admtek __P((struct dc_softc *)); 246 247 static void dc_setfilt __P((struct dc_softc *)); 248 249 static void dc_reset __P((struct dc_softc *)); 250 static int dc_list_rx_init __P((struct dc_softc *)); 251 static int dc_list_tx_init __P((struct dc_softc *)); 252 253 #ifdef DC_USEIOSPACE 254 #define DC_RES SYS_RES_IOPORT 255 #define DC_RID DC_PCI_CFBIO 256 #else 257 #define DC_RES SYS_RES_MEMORY 258 #define DC_RID DC_PCI_CFBMA 259 #endif 260 261 static device_method_t dc_methods[] = { 262 /* Device interface */ 263 DEVMETHOD(device_probe, dc_probe), 264 DEVMETHOD(device_attach, dc_attach), 265 DEVMETHOD(device_detach, dc_detach), 266 DEVMETHOD(device_shutdown, dc_shutdown), 267 268 /* bus interface */ 269 DEVMETHOD(bus_print_child, bus_generic_print_child), 270 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 271 272 /* MII interface */ 273 DEVMETHOD(miibus_readreg, dc_miibus_readreg), 274 DEVMETHOD(miibus_writereg, dc_miibus_writereg), 275 DEVMETHOD(miibus_statchg, dc_miibus_statchg), 276 DEVMETHOD(miibus_mediainit, dc_miibus_mediainit), 277 278 { 0, 0 } 279 }; 280 281 static driver_t dc_driver = { 282 "dc", 283 dc_methods, 284 sizeof(struct dc_softc) 285 }; 286 287 static devclass_t dc_devclass; 288 289 DRIVER_MODULE(if_dc, pci, dc_driver, dc_devclass, 0, 0); 290 DRIVER_MODULE(miibus, dc, miibus_driver, miibus_devclass, 0, 0); 291 292 #define DC_SETBIT(sc, reg, x) \ 293 CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) | (x)) 294 295 #define DC_CLRBIT(sc, reg, x) \ 296 CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) & ~(x)) 297 298 #define SIO_SET(x) DC_SETBIT(sc, DC_SIO, (x)) 299 #define SIO_CLR(x) DC_CLRBIT(sc, DC_SIO, (x)) 300 301 static void dc_delay(sc) 302 struct dc_softc *sc; 303 { 304 int idx; 305 306 for (idx = (300 / 33) + 1; idx > 0; idx--) 307 CSR_READ_4(sc, DC_BUSCTL); 308 } 309 310 static void dc_eeprom_idle(sc) 311 struct dc_softc *sc; 312 { 313 register int i; 314 315 CSR_WRITE_4(sc, DC_SIO, DC_SIO_EESEL); 316 dc_delay(sc); 317 DC_SETBIT(sc, DC_SIO, DC_SIO_ROMCTL_READ); 318 dc_delay(sc); 319 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); 320 dc_delay(sc); 321 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CS); 322 dc_delay(sc); 323 324 for (i = 0; i < 25; i++) { 325 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); 326 dc_delay(sc); 327 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CLK); 328 dc_delay(sc); 329 } 330 331 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); 332 dc_delay(sc); 333 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CS); 334 dc_delay(sc); 335 CSR_WRITE_4(sc, DC_SIO, 0x00000000); 336 337 return; 338 } 339 340 /* 341 * Send a read command and address to the EEPROM, check for ACK. 342 */ 343 static void dc_eeprom_putbyte(sc, addr) 344 struct dc_softc *sc; 345 int addr; 346 { 347 register int d, i; 348 349 /* 350 * The AN985 has a 93C66 EEPROM on it instead of 351 * a 93C46. It uses a different bit sequence for 352 * specifying the "read" opcode. 353 */ 354 if (DC_IS_CENTAUR(sc)) 355 d = addr | (DC_EECMD_READ << 2); 356 else 357 d = addr | DC_EECMD_READ; 358 359 /* 360 * Feed in each bit and strobe the clock. 361 */ 362 for (i = 0x400; i; i >>= 1) { 363 if (d & i) { 364 SIO_SET(DC_SIO_EE_DATAIN); 365 } else { 366 SIO_CLR(DC_SIO_EE_DATAIN); 367 } 368 dc_delay(sc); 369 SIO_SET(DC_SIO_EE_CLK); 370 dc_delay(sc); 371 SIO_CLR(DC_SIO_EE_CLK); 372 dc_delay(sc); 373 } 374 375 return; 376 } 377 378 /* 379 * Read a word of data stored in the EEPROM at address 'addr.' 380 * The PNIC 82c168/82c169 has its own non-standard way to read 381 * the EEPROM. 382 */ 383 static void dc_eeprom_getword_pnic(sc, addr, dest) 384 struct dc_softc *sc; 385 int addr; 386 u_int16_t *dest; 387 { 388 register int i; 389 u_int32_t r; 390 391 CSR_WRITE_4(sc, DC_PN_SIOCTL, DC_PN_EEOPCODE_READ|addr); 392 393 for (i = 0; i < DC_TIMEOUT; i++) { 394 DELAY(1); 395 r = CSR_READ_4(sc, DC_SIO); 396 if (!(r & DC_PN_SIOCTL_BUSY)) { 397 *dest = (u_int16_t)(r & 0xFFFF); 398 return; 399 } 400 } 401 402 return; 403 } 404 405 /* 406 * Read a word of data stored in the EEPROM at address 'addr.' 407 */ 408 static void dc_eeprom_getword(sc, addr, dest) 409 struct dc_softc *sc; 410 int addr; 411 u_int16_t *dest; 412 { 413 register int i; 414 u_int16_t word = 0; 415 416 /* Force EEPROM to idle state. */ 417 dc_eeprom_idle(sc); 418 419 /* Enter EEPROM access mode. */ 420 CSR_WRITE_4(sc, DC_SIO, DC_SIO_EESEL); 421 dc_delay(sc); 422 DC_SETBIT(sc, DC_SIO, DC_SIO_ROMCTL_READ); 423 dc_delay(sc); 424 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); 425 dc_delay(sc); 426 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CS); 427 dc_delay(sc); 428 429 /* 430 * Send address of word we want to read. 431 */ 432 dc_eeprom_putbyte(sc, addr); 433 434 /* 435 * Start reading bits from EEPROM. 436 */ 437 for (i = 0x8000; i; i >>= 1) { 438 SIO_SET(DC_SIO_EE_CLK); 439 dc_delay(sc); 440 if (CSR_READ_4(sc, DC_SIO) & DC_SIO_EE_DATAOUT) 441 word |= i; 442 dc_delay(sc); 443 SIO_CLR(DC_SIO_EE_CLK); 444 dc_delay(sc); 445 } 446 447 /* Turn off EEPROM access mode. */ 448 dc_eeprom_idle(sc); 449 450 *dest = word; 451 452 return; 453 } 454 455 /* 456 * Read a sequence of words from the EEPROM. 457 */ 458 static void dc_read_eeprom(sc, dest, off, cnt, swap) 459 struct dc_softc *sc; 460 caddr_t dest; 461 int off; 462 int cnt; 463 int swap; 464 { 465 int i; 466 u_int16_t word = 0, *ptr; 467 468 for (i = 0; i < cnt; i++) { 469 if (DC_IS_PNIC(sc)) 470 dc_eeprom_getword_pnic(sc, off + i, &word); 471 else 472 dc_eeprom_getword(sc, off + i, &word); 473 ptr = (u_int16_t *)(dest + (i * 2)); 474 if (swap) 475 *ptr = ntohs(word); 476 else 477 *ptr = word; 478 } 479 480 return; 481 } 482 483 /* 484 * The following two routines are taken from the Macronix 98713 485 * Application Notes pp.19-21. 486 */ 487 /* 488 * Write a bit to the MII bus. 489 */ 490 static void dc_mii_writebit(sc, bit) 491 struct dc_softc *sc; 492 int bit; 493 { 494 if (bit) 495 CSR_WRITE_4(sc, DC_SIO, 496 DC_SIO_ROMCTL_WRITE|DC_SIO_MII_DATAOUT); 497 else 498 CSR_WRITE_4(sc, DC_SIO, DC_SIO_ROMCTL_WRITE); 499 500 DC_SETBIT(sc, DC_SIO, DC_SIO_MII_CLK); 501 DC_CLRBIT(sc, DC_SIO, DC_SIO_MII_CLK); 502 503 return; 504 } 505 506 /* 507 * Read a bit from the MII bus. 508 */ 509 static int dc_mii_readbit(sc) 510 struct dc_softc *sc; 511 { 512 CSR_WRITE_4(sc, DC_SIO, DC_SIO_ROMCTL_READ|DC_SIO_MII_DIR); 513 CSR_READ_4(sc, DC_SIO); 514 DC_SETBIT(sc, DC_SIO, DC_SIO_MII_CLK); 515 DC_CLRBIT(sc, DC_SIO, DC_SIO_MII_CLK); 516 if (CSR_READ_4(sc, DC_SIO) & DC_SIO_MII_DATAIN) 517 return(1); 518 519 return(0); 520 } 521 522 /* 523 * Sync the PHYs by setting data bit and strobing the clock 32 times. 524 */ 525 static void dc_mii_sync(sc) 526 struct dc_softc *sc; 527 { 528 register int i; 529 530 CSR_WRITE_4(sc, DC_SIO, DC_SIO_ROMCTL_WRITE); 531 532 for (i = 0; i < 32; i++) 533 dc_mii_writebit(sc, 1); 534 535 return; 536 } 537 538 /* 539 * Clock a series of bits through the MII. 540 */ 541 static void dc_mii_send(sc, bits, cnt) 542 struct dc_softc *sc; 543 u_int32_t bits; 544 int cnt; 545 { 546 int i; 547 548 for (i = (0x1 << (cnt - 1)); i; i >>= 1) 549 dc_mii_writebit(sc, bits & i); 550 } 551 552 /* 553 * Read an PHY register through the MII. 554 */ 555 static int dc_mii_readreg(sc, frame) 556 struct dc_softc *sc; 557 struct dc_mii_frame *frame; 558 559 { 560 int i, ack, s; 561 562 s = splimp(); 563 564 /* 565 * Set up frame for RX. 566 */ 567 frame->mii_stdelim = DC_MII_STARTDELIM; 568 frame->mii_opcode = DC_MII_READOP; 569 frame->mii_turnaround = 0; 570 frame->mii_data = 0; 571 572 /* 573 * Sync the PHYs. 574 */ 575 dc_mii_sync(sc); 576 577 /* 578 * Send command/address info. 579 */ 580 dc_mii_send(sc, frame->mii_stdelim, 2); 581 dc_mii_send(sc, frame->mii_opcode, 2); 582 dc_mii_send(sc, frame->mii_phyaddr, 5); 583 dc_mii_send(sc, frame->mii_regaddr, 5); 584 585 #ifdef notdef 586 /* Idle bit */ 587 dc_mii_writebit(sc, 1); 588 dc_mii_writebit(sc, 0); 589 #endif 590 591 /* Check for ack */ 592 ack = dc_mii_readbit(sc); 593 594 /* 595 * Now try reading data bits. If the ack failed, we still 596 * need to clock through 16 cycles to keep the PHY(s) in sync. 597 */ 598 if (ack) { 599 for(i = 0; i < 16; i++) { 600 dc_mii_readbit(sc); 601 } 602 goto fail; 603 } 604 605 for (i = 0x8000; i; i >>= 1) { 606 if (!ack) { 607 if (dc_mii_readbit(sc)) 608 frame->mii_data |= i; 609 } 610 } 611 612 fail: 613 614 dc_mii_writebit(sc, 0); 615 dc_mii_writebit(sc, 0); 616 617 splx(s); 618 619 if (ack) 620 return(1); 621 return(0); 622 } 623 624 /* 625 * Write to a PHY register through the MII. 626 */ 627 static int dc_mii_writereg(sc, frame) 628 struct dc_softc *sc; 629 struct dc_mii_frame *frame; 630 631 { 632 int s; 633 634 s = splimp(); 635 /* 636 * Set up frame for TX. 637 */ 638 639 frame->mii_stdelim = DC_MII_STARTDELIM; 640 frame->mii_opcode = DC_MII_WRITEOP; 641 frame->mii_turnaround = DC_MII_TURNAROUND; 642 643 /* 644 * Sync the PHYs. 645 */ 646 dc_mii_sync(sc); 647 648 dc_mii_send(sc, frame->mii_stdelim, 2); 649 dc_mii_send(sc, frame->mii_opcode, 2); 650 dc_mii_send(sc, frame->mii_phyaddr, 5); 651 dc_mii_send(sc, frame->mii_regaddr, 5); 652 dc_mii_send(sc, frame->mii_turnaround, 2); 653 dc_mii_send(sc, frame->mii_data, 16); 654 655 /* Idle bit. */ 656 dc_mii_writebit(sc, 0); 657 dc_mii_writebit(sc, 0); 658 659 splx(s); 660 661 return(0); 662 } 663 664 static int dc_miibus_readreg(dev, phy, reg) 665 device_t dev; 666 int phy, reg; 667 { 668 struct dc_mii_frame frame; 669 struct dc_softc *sc; 670 int i, rval, phy_reg; 671 672 sc = device_get_softc(dev); 673 bzero((char *)&frame, sizeof(frame)); 674 675 /* 676 * Note: both the AL981 and AN985 have internal PHYs, 677 * however the AL981 provides direct access to the PHY 678 * registers while the AN985 uses a serial MII interface. 679 * The AN985's MII interface is also buggy in that you 680 * can read from any MII address (0 to 31), but only address 1 681 * behaves normally. To deal with both cases, we pretend 682 * that the PHY is at MII address 1. 683 */ 684 if (DC_IS_ADMTEK(sc) && phy != DC_ADMTEK_PHYADDR) 685 return(0); 686 687 if (sc->dc_pmode == DC_PMODE_SYM) { 688 if (phy == (MII_NPHY - 1)) { 689 switch(reg) { 690 case MII_BMSR: 691 /* 692 * Fake something to make the probe 693 * code think there's a PHY here. 694 */ 695 return(BMSR_MEDIAMASK); 696 break; 697 case MII_PHYIDR1: 698 if (DC_IS_PNIC(sc)) 699 return(DC_VENDORID_LO); 700 return(DC_VENDORID_DEC); 701 break; 702 case MII_PHYIDR2: 703 if (DC_IS_PNIC(sc)) 704 return(DC_DEVICEID_82C168); 705 return(DC_DEVICEID_21143); 706 break; 707 default: 708 return(0); 709 break; 710 } 711 } else 712 return(0); 713 } 714 715 if (DC_IS_PNIC(sc)) { 716 CSR_WRITE_4(sc, DC_PN_MII, DC_PN_MIIOPCODE_READ | 717 (phy << 23) | (reg << 18)); 718 for (i = 0; i < DC_TIMEOUT; i++) { 719 DELAY(1); 720 rval = CSR_READ_4(sc, DC_PN_MII); 721 if (!(rval & DC_PN_MII_BUSY)) { 722 rval &= 0xFFFF; 723 return(rval == 0xFFFF ? 0 : rval); 724 } 725 } 726 return(0); 727 } 728 729 if (DC_IS_COMET(sc)) { 730 switch(reg) { 731 case MII_BMCR: 732 phy_reg = DC_AL_BMCR; 733 break; 734 case MII_BMSR: 735 phy_reg = DC_AL_BMSR; 736 break; 737 case MII_PHYIDR1: 738 phy_reg = DC_AL_VENID; 739 break; 740 case MII_PHYIDR2: 741 phy_reg = DC_AL_DEVID; 742 break; 743 case MII_ANAR: 744 phy_reg = DC_AL_ANAR; 745 break; 746 case MII_ANLPAR: 747 phy_reg = DC_AL_LPAR; 748 break; 749 case MII_ANER: 750 phy_reg = DC_AL_ANER; 751 break; 752 default: 753 printf("dc%d: phy_read: bad phy register %x\n", 754 sc->dc_unit, reg); 755 return(0); 756 break; 757 } 758 759 rval = CSR_READ_4(sc, phy_reg) & 0x0000FFFF; 760 761 if (rval == 0xFFFF) 762 return(0); 763 return(rval); 764 } 765 766 frame.mii_phyaddr = phy; 767 frame.mii_regaddr = reg; 768 phy_reg = CSR_READ_4(sc, DC_NETCFG); 769 CSR_WRITE_4(sc, DC_NETCFG, phy_reg & ~DC_NETCFG_PORTSEL); 770 dc_mii_readreg(sc, &frame); 771 CSR_WRITE_4(sc, DC_NETCFG, phy_reg); 772 773 return(frame.mii_data); 774 } 775 776 static int dc_miibus_writereg(dev, phy, reg, data) 777 device_t dev; 778 int phy, reg, data; 779 { 780 struct dc_softc *sc; 781 struct dc_mii_frame frame; 782 int i, phy_reg; 783 784 sc = device_get_softc(dev); 785 bzero((char *)&frame, sizeof(frame)); 786 787 if (DC_IS_ADMTEK(sc) && phy != DC_ADMTEK_PHYADDR) 788 return(0); 789 790 if (DC_IS_PNIC(sc)) { 791 CSR_WRITE_4(sc, DC_PN_MII, DC_PN_MIIOPCODE_WRITE | 792 (phy << 23) | (reg << 10) | data); 793 for (i = 0; i < DC_TIMEOUT; i++) { 794 if (!(CSR_READ_4(sc, DC_PN_MII) & DC_PN_MII_BUSY)) 795 break; 796 } 797 return(0); 798 } 799 800 if (DC_IS_COMET(sc)) { 801 switch(reg) { 802 case MII_BMCR: 803 phy_reg = DC_AL_BMCR; 804 break; 805 case MII_BMSR: 806 phy_reg = DC_AL_BMSR; 807 break; 808 case MII_PHYIDR1: 809 phy_reg = DC_AL_VENID; 810 break; 811 case MII_PHYIDR2: 812 phy_reg = DC_AL_DEVID; 813 break; 814 case MII_ANAR: 815 phy_reg = DC_AL_ANAR; 816 break; 817 case MII_ANLPAR: 818 phy_reg = DC_AL_LPAR; 819 break; 820 case MII_ANER: 821 phy_reg = DC_AL_ANER; 822 break; 823 default: 824 printf("dc%d: phy_write: bad phy register %x\n", 825 sc->dc_unit, reg); 826 return(0); 827 break; 828 } 829 830 CSR_WRITE_4(sc, phy_reg, data); 831 return(0); 832 } 833 834 frame.mii_phyaddr = phy; 835 frame.mii_regaddr = reg; 836 frame.mii_data = data; 837 838 phy_reg = CSR_READ_4(sc, DC_NETCFG); 839 CSR_WRITE_4(sc, DC_NETCFG, phy_reg & ~DC_NETCFG_PORTSEL); 840 dc_mii_writereg(sc, &frame); 841 CSR_WRITE_4(sc, DC_NETCFG, phy_reg); 842 843 return(0); 844 } 845 846 static void dc_miibus_statchg(dev) 847 device_t dev; 848 { 849 struct dc_softc *sc; 850 struct mii_data *mii; 851 struct ifmedia *ifm; 852 853 sc = device_get_softc(dev); 854 if (DC_IS_ADMTEK(sc)) 855 return; 856 mii = device_get_softc(sc->dc_miibus); 857 ifm = &mii->mii_media; 858 if (DC_IS_DAVICOM(sc) && 859 IFM_SUBTYPE(ifm->ifm_media) == IFM_homePNA) { 860 dc_setcfg(sc, ifm->ifm_media); 861 sc->dc_if_media = ifm->ifm_media; 862 } else { 863 dc_setcfg(sc, mii->mii_media_active); 864 sc->dc_if_media = mii->mii_media_active; 865 } 866 867 return; 868 } 869 870 /* 871 * Special support for DM9102A cards with HomePNA PHYs. Note: 872 * with the Davicom DM9102A/DM9801 eval board that I have, it seems 873 * to be impossible to talk to the management interface of the DM9801 874 * PHY (its MDIO pin is not connected to anything). Consequently, 875 * the driver has to just 'know' about the additional mode and deal 876 * with it itself. *sigh* 877 */ 878 static void dc_miibus_mediainit(dev) 879 device_t dev; 880 { 881 struct dc_softc *sc; 882 struct mii_data *mii; 883 struct ifmedia *ifm; 884 int rev; 885 886 rev = pci_read_config(dev, DC_PCI_CFRV, 4) & 0xFF; 887 888 sc = device_get_softc(dev); 889 mii = device_get_softc(sc->dc_miibus); 890 ifm = &mii->mii_media; 891 892 if (DC_IS_DAVICOM(sc) && rev >= DC_REVISION_DM9102A) 893 ifmedia_add(ifm, IFM_ETHER|IFM_homePNA, 0, NULL); 894 895 return; 896 } 897 898 #define DC_POLY 0xEDB88320 899 #define DC_BITS 9 900 #define DC_BITS_PNIC_II 7 901 902 static u_int32_t dc_crc_le(sc, addr) 903 struct dc_softc *sc; 904 caddr_t addr; 905 { 906 u_int32_t idx, bit, data, crc; 907 908 /* Compute CRC for the address value. */ 909 crc = 0xFFFFFFFF; /* initial value */ 910 911 for (idx = 0; idx < 6; idx++) { 912 for (data = *addr++, bit = 0; bit < 8; bit++, data >>= 1) 913 crc = (crc >> 1) ^ (((crc ^ data) & 1) ? DC_POLY : 0); 914 } 915 916 /* The hash table on the PNIC II is only 128 bits wide. */ 917 if (DC_IS_PNICII(sc)) 918 return (crc & ((1 << DC_BITS_PNIC_II) - 1)); 919 920 return (crc & ((1 << DC_BITS) - 1)); 921 } 922 923 /* 924 * Calculate CRC of a multicast group address, return the lower 6 bits. 925 */ 926 static u_int32_t dc_crc_be(addr) 927 caddr_t addr; 928 { 929 u_int32_t crc, carry; 930 int i, j; 931 u_int8_t c; 932 933 /* Compute CRC for the address value. */ 934 crc = 0xFFFFFFFF; /* initial value */ 935 936 for (i = 0; i < 6; i++) { 937 c = *(addr + i); 938 for (j = 0; j < 8; j++) { 939 carry = ((crc & 0x80000000) ? 1 : 0) ^ (c & 0x01); 940 crc <<= 1; 941 c >>= 1; 942 if (carry) 943 crc = (crc ^ 0x04c11db6) | carry; 944 } 945 } 946 947 /* return the filter bit position */ 948 return((crc >> 26) & 0x0000003F); 949 } 950 951 /* 952 * 21143-style RX filter setup routine. Filter programming is done by 953 * downloading a special setup frame into the TX engine. 21143, Macronix, 954 * PNIC, PNIC II and Davicom chips are programmed this way. 955 * 956 * We always program the chip using 'hash perfect' mode, i.e. one perfect 957 * address (our node address) and a 512-bit hash filter for multicast 958 * frames. We also sneak the broadcast address into the hash filter since 959 * we need that too. 960 */ 961 void dc_setfilt_21143(sc) 962 struct dc_softc *sc; 963 { 964 struct dc_desc *sframe; 965 u_int32_t h, *sp; 966 struct ifmultiaddr *ifma; 967 struct ifnet *ifp; 968 int i; 969 970 ifp = &sc->arpcom.ac_if; 971 972 i = sc->dc_cdata.dc_tx_prod; 973 DC_INC(sc->dc_cdata.dc_tx_prod, DC_TX_LIST_CNT); 974 sc->dc_cdata.dc_tx_cnt++; 975 sframe = &sc->dc_ldata->dc_tx_list[i]; 976 sp = (u_int32_t *)&sc->dc_cdata.dc_sbuf; 977 bzero((char *)sp, DC_SFRAME_LEN); 978 979 sframe->dc_data = vtophys(&sc->dc_cdata.dc_sbuf); 980 sframe->dc_ctl = DC_SFRAME_LEN | DC_TXCTL_SETUP | DC_TXCTL_TLINK | 981 DC_FILTER_HASHPERF | DC_TXCTL_FINT; 982 983 sc->dc_cdata.dc_tx_chain[i] = (struct mbuf *)&sc->dc_cdata.dc_sbuf; 984 985 /* If we want promiscuous mode, set the allframes bit. */ 986 if (ifp->if_flags & IFF_PROMISC) 987 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC); 988 else 989 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC); 990 991 if (ifp->if_flags & IFF_ALLMULTI) 992 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI); 993 else 994 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI); 995 996 for (ifma = ifp->if_multiaddrs.lh_first; ifma != NULL; 997 ifma = ifma->ifma_link.le_next) { 998 if (ifma->ifma_addr->sa_family != AF_LINK) 999 continue; 1000 h = dc_crc_le(sc, 1001 LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 1002 sp[h >> 4] |= 1 << (h & 0xF); 1003 } 1004 1005 if (ifp->if_flags & IFF_BROADCAST) { 1006 h = dc_crc_le(sc, (caddr_t)ðerbroadcastaddr); 1007 sp[h >> 4] |= 1 << (h & 0xF); 1008 } 1009 1010 /* Set our MAC address */ 1011 sp[39] = ((u_int16_t *)sc->arpcom.ac_enaddr)[0]; 1012 sp[40] = ((u_int16_t *)sc->arpcom.ac_enaddr)[1]; 1013 sp[41] = ((u_int16_t *)sc->arpcom.ac_enaddr)[2]; 1014 1015 sframe->dc_status = DC_TXSTAT_OWN; 1016 CSR_WRITE_4(sc, DC_TXSTART, 0xFFFFFFFF); 1017 1018 /* 1019 * The PNIC takes an exceedingly long time to process its 1020 * setup frame; wait 10ms after posting the setup frame 1021 * before proceeding, just so it has time to swallow its 1022 * medicine. 1023 */ 1024 DELAY(10000); 1025 1026 ifp->if_timer = 5; 1027 1028 return; 1029 } 1030 1031 void dc_setfilt_admtek(sc) 1032 struct dc_softc *sc; 1033 { 1034 struct ifnet *ifp; 1035 int h = 0; 1036 u_int32_t hashes[2] = { 0, 0 }; 1037 struct ifmultiaddr *ifma; 1038 1039 ifp = &sc->arpcom.ac_if; 1040 1041 /* Init our MAC address */ 1042 CSR_WRITE_4(sc, DC_AL_PAR0, *(u_int32_t *)(&sc->arpcom.ac_enaddr[0])); 1043 CSR_WRITE_4(sc, DC_AL_PAR1, *(u_int32_t *)(&sc->arpcom.ac_enaddr[4])); 1044 1045 /* If we want promiscuous mode, set the allframes bit. */ 1046 if (ifp->if_flags & IFF_PROMISC) 1047 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC); 1048 else 1049 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC); 1050 1051 if (ifp->if_flags & IFF_ALLMULTI) 1052 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI); 1053 else 1054 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI); 1055 1056 /* first, zot all the existing hash bits */ 1057 CSR_WRITE_4(sc, DC_AL_MAR0, 0); 1058 CSR_WRITE_4(sc, DC_AL_MAR1, 0); 1059 1060 /* 1061 * If we're already in promisc or allmulti mode, we 1062 * don't have to bother programming the multicast filter. 1063 */ 1064 if (ifp->if_flags & (IFF_PROMISC|IFF_ALLMULTI)) 1065 return; 1066 1067 /* now program new ones */ 1068 for (ifma = ifp->if_multiaddrs.lh_first; ifma != NULL; 1069 ifma = ifma->ifma_link.le_next) { 1070 if (ifma->ifma_addr->sa_family != AF_LINK) 1071 continue; 1072 h = dc_crc_be(LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 1073 if (h < 32) 1074 hashes[0] |= (1 << h); 1075 else 1076 hashes[1] |= (1 << (h - 32)); 1077 } 1078 1079 CSR_WRITE_4(sc, DC_AL_MAR0, hashes[0]); 1080 CSR_WRITE_4(sc, DC_AL_MAR1, hashes[1]); 1081 1082 return; 1083 } 1084 1085 void dc_setfilt_asix(sc) 1086 struct dc_softc *sc; 1087 { 1088 struct ifnet *ifp; 1089 int h = 0; 1090 u_int32_t hashes[2] = { 0, 0 }; 1091 struct ifmultiaddr *ifma; 1092 1093 ifp = &sc->arpcom.ac_if; 1094 1095 /* Init our MAC address */ 1096 CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_PAR0); 1097 CSR_WRITE_4(sc, DC_AX_FILTDATA, 1098 *(u_int32_t *)(&sc->arpcom.ac_enaddr[0])); 1099 CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_PAR1); 1100 CSR_WRITE_4(sc, DC_AX_FILTDATA, 1101 *(u_int32_t *)(&sc->arpcom.ac_enaddr[4])); 1102 1103 /* If we want promiscuous mode, set the allframes bit. */ 1104 if (ifp->if_flags & IFF_PROMISC) 1105 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC); 1106 else 1107 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC); 1108 1109 if (ifp->if_flags & IFF_ALLMULTI) 1110 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI); 1111 else 1112 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI); 1113 1114 /* 1115 * The ASIX chip has a special bit to enable reception 1116 * of broadcast frames. 1117 */ 1118 if (ifp->if_flags & IFF_BROADCAST) 1119 DC_SETBIT(sc, DC_NETCFG, DC_AX_NETCFG_RX_BROAD); 1120 else 1121 DC_CLRBIT(sc, DC_NETCFG, DC_AX_NETCFG_RX_BROAD); 1122 1123 /* first, zot all the existing hash bits */ 1124 CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_MAR0); 1125 CSR_WRITE_4(sc, DC_AX_FILTDATA, 0); 1126 CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_MAR1); 1127 CSR_WRITE_4(sc, DC_AX_FILTDATA, 0); 1128 1129 /* 1130 * If we're already in promisc or allmulti mode, we 1131 * don't have to bother programming the multicast filter. 1132 */ 1133 if (ifp->if_flags & (IFF_PROMISC|IFF_ALLMULTI)) 1134 return; 1135 1136 /* now program new ones */ 1137 for (ifma = ifp->if_multiaddrs.lh_first; ifma != NULL; 1138 ifma = ifma->ifma_link.le_next) { 1139 if (ifma->ifma_addr->sa_family != AF_LINK) 1140 continue; 1141 h = dc_crc_be(LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 1142 if (h < 32) 1143 hashes[0] |= (1 << h); 1144 else 1145 hashes[1] |= (1 << (h - 32)); 1146 } 1147 1148 CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_MAR0); 1149 CSR_WRITE_4(sc, DC_AX_FILTDATA, hashes[0]); 1150 CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_MAR1); 1151 CSR_WRITE_4(sc, DC_AX_FILTDATA, hashes[1]); 1152 1153 return; 1154 } 1155 1156 static void dc_setfilt(sc) 1157 struct dc_softc *sc; 1158 { 1159 if (DC_IS_INTEL(sc) || DC_IS_MACRONIX(sc) || DC_IS_PNIC(sc) || 1160 DC_IS_PNICII(sc) || DC_IS_DAVICOM(sc)) 1161 dc_setfilt_21143(sc); 1162 1163 if (DC_IS_ASIX(sc)) 1164 dc_setfilt_asix(sc); 1165 1166 if (DC_IS_ADMTEK(sc)) 1167 dc_setfilt_admtek(sc); 1168 1169 return; 1170 } 1171 1172 /* 1173 * In order to fiddle with the 1174 * 'full-duplex' and '100Mbps' bits in the netconfig register, we 1175 * first have to put the transmit and/or receive logic in the idle state. 1176 */ 1177 static void dc_setcfg(sc, media) 1178 struct dc_softc *sc; 1179 int media; 1180 { 1181 int i, restart = 0; 1182 u_int32_t isr; 1183 1184 if (IFM_SUBTYPE(media) == IFM_NONE) 1185 return; 1186 1187 if (CSR_READ_4(sc, DC_NETCFG) & (DC_NETCFG_TX_ON|DC_NETCFG_RX_ON)) { 1188 restart = 1; 1189 DC_CLRBIT(sc, DC_NETCFG, (DC_NETCFG_TX_ON|DC_NETCFG_RX_ON)); 1190 1191 for (i = 0; i < DC_TIMEOUT; i++) { 1192 DELAY(10); 1193 isr = CSR_READ_4(sc, DC_ISR); 1194 if (isr & DC_ISR_TX_IDLE || 1195 (isr & DC_ISR_RX_STATE) == DC_RXSTATE_STOPPED) 1196 break; 1197 } 1198 1199 if (i == DC_TIMEOUT) 1200 printf("dc%d: failed to force tx and " 1201 "rx to idle state\n", sc->dc_unit); 1202 1203 } 1204 1205 if (IFM_SUBTYPE(media) == IFM_100_TX) { 1206 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_SPEEDSEL); 1207 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_HEARTBEAT); 1208 if (sc->dc_pmode == DC_PMODE_MII) { 1209 DC_SETBIT(sc, DC_WATCHDOG, DC_WDOG_JABBERDIS); 1210 DC_CLRBIT(sc, DC_NETCFG, (DC_NETCFG_PCS| 1211 DC_NETCFG_PORTSEL|DC_NETCFG_SCRAMBLER)); 1212 if (sc->dc_type == DC_TYPE_98713) 1213 DC_SETBIT(sc, DC_NETCFG, (DC_NETCFG_PCS| 1214 DC_NETCFG_SCRAMBLER)); 1215 if (!DC_IS_DAVICOM(sc)) 1216 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL); 1217 DC_CLRBIT(sc, DC_10BTCTRL, 0xFFFF); 1218 } else { 1219 if (DC_IS_PNIC(sc)) { 1220 DC_PN_GPIO_SETBIT(sc, DC_PN_GPIO_SPEEDSEL); 1221 DC_PN_GPIO_SETBIT(sc, DC_PN_GPIO_100TX_LOOP); 1222 DC_SETBIT(sc, DC_PN_NWAY, DC_PN_NWAY_SPEEDSEL); 1223 } 1224 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL| 1225 DC_NETCFG_PCS|DC_NETCFG_SCRAMBLER); 1226 } 1227 } 1228 1229 if (IFM_SUBTYPE(media) == IFM_10_T) { 1230 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_SPEEDSEL); 1231 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_HEARTBEAT); 1232 if (sc->dc_pmode == DC_PMODE_MII) { 1233 DC_SETBIT(sc, DC_WATCHDOG, DC_WDOG_JABBERDIS); 1234 DC_CLRBIT(sc, DC_NETCFG, (DC_NETCFG_PCS| 1235 DC_NETCFG_PORTSEL|DC_NETCFG_SCRAMBLER)); 1236 if (sc->dc_type == DC_TYPE_98713) 1237 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PCS); 1238 if (!DC_IS_DAVICOM(sc)) 1239 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL); 1240 DC_CLRBIT(sc, DC_10BTCTRL, 0xFFFF); 1241 } else { 1242 if (DC_IS_PNIC(sc)) { 1243 DC_PN_GPIO_CLRBIT(sc, DC_PN_GPIO_SPEEDSEL); 1244 DC_PN_GPIO_SETBIT(sc, DC_PN_GPIO_100TX_LOOP); 1245 DC_CLRBIT(sc, DC_PN_NWAY, DC_PN_NWAY_SPEEDSEL); 1246 } 1247 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL); 1248 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_SCRAMBLER); 1249 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PCS); 1250 } 1251 } 1252 1253 /* 1254 * If this is a Davicom DM9102A card with a DM9801 HomePNA 1255 * PHY and we want HomePNA mode, set the portsel bit to turn 1256 * on the external MII port. 1257 */ 1258 if (DC_IS_DAVICOM(sc)) { 1259 if (IFM_SUBTYPE(media) == IFM_homePNA) { 1260 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL); 1261 sc->dc_link = 1; 1262 } else { 1263 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL); 1264 } 1265 } 1266 1267 if ((media & IFM_GMASK) == IFM_FDX) { 1268 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_FULLDUPLEX); 1269 if (sc->dc_pmode == DC_PMODE_SYM && DC_IS_PNIC(sc)) 1270 DC_SETBIT(sc, DC_PN_NWAY, DC_PN_NWAY_DUPLEX); 1271 } else { 1272 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_FULLDUPLEX); 1273 if (sc->dc_pmode == DC_PMODE_SYM && DC_IS_PNIC(sc)) 1274 DC_CLRBIT(sc, DC_PN_NWAY, DC_PN_NWAY_DUPLEX); 1275 } 1276 1277 if (restart) 1278 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_TX_ON|DC_NETCFG_RX_ON); 1279 1280 return; 1281 } 1282 1283 static void dc_reset(sc) 1284 struct dc_softc *sc; 1285 { 1286 register int i; 1287 1288 DC_SETBIT(sc, DC_BUSCTL, DC_BUSCTL_RESET); 1289 1290 for (i = 0; i < DC_TIMEOUT; i++) { 1291 DELAY(10); 1292 if (!(CSR_READ_4(sc, DC_BUSCTL) & DC_BUSCTL_RESET)) 1293 break; 1294 } 1295 1296 if (DC_IS_ASIX(sc) || DC_IS_ADMTEK(sc)) { 1297 DELAY(10000); 1298 DC_CLRBIT(sc, DC_BUSCTL, DC_BUSCTL_RESET); 1299 i = 0; 1300 } 1301 1302 if (i == DC_TIMEOUT) 1303 printf("dc%d: reset never completed!\n", sc->dc_unit); 1304 1305 /* Wait a little while for the chip to get its brains in order. */ 1306 DELAY(1000); 1307 1308 CSR_WRITE_4(sc, DC_IMR, 0x00000000); 1309 CSR_WRITE_4(sc, DC_BUSCTL, 0x00000000); 1310 CSR_WRITE_4(sc, DC_NETCFG, 0x00000000); 1311 1312 /* 1313 * Bring the SIA out of reset. In some cases, it looks 1314 * like failing to unreset the SIA soon enough gets it 1315 * into a state where it will never come out of reset 1316 * until we reset the whole chip again. 1317 */ 1318 if (DC_IS_INTEL(sc)) 1319 DC_SETBIT(sc, DC_SIARESET, DC_SIA_RESET); 1320 1321 return; 1322 } 1323 1324 static struct dc_type *dc_devtype(dev) 1325 device_t dev; 1326 { 1327 struct dc_type *t; 1328 u_int32_t rev; 1329 1330 t = dc_devs; 1331 1332 while(t->dc_name != NULL) { 1333 if ((pci_get_vendor(dev) == t->dc_vid) && 1334 (pci_get_device(dev) == t->dc_did)) { 1335 /* Check the PCI revision */ 1336 rev = pci_read_config(dev, DC_PCI_CFRV, 4) & 0xFF; 1337 if (t->dc_did == DC_DEVICEID_98713 && 1338 rev >= DC_REVISION_98713A) 1339 t++; 1340 if (t->dc_did == DC_DEVICEID_98713_CP && 1341 rev >= DC_REVISION_98713A) 1342 t++; 1343 if (t->dc_did == DC_DEVICEID_987x5 && 1344 rev >= DC_REVISION_98725) 1345 t++; 1346 if (t->dc_did == DC_DEVICEID_AX88140A && 1347 rev >= DC_REVISION_88141) 1348 t++; 1349 if (t->dc_did == DC_DEVICEID_82C168 && 1350 rev >= DC_REVISION_82C169) 1351 t++; 1352 if (t->dc_did == DC_DEVICEID_DM9102 && 1353 rev >= DC_REVISION_DM9102A) 1354 t++; 1355 return(t); 1356 } 1357 t++; 1358 } 1359 1360 return(NULL); 1361 } 1362 1363 /* 1364 * Probe for a 21143 or clone chip. Check the PCI vendor and device 1365 * IDs against our list and return a device name if we find a match. 1366 * We do a little bit of extra work to identify the exact type of 1367 * chip. The MX98713 and MX98713A have the same PCI vendor/device ID, 1368 * but different revision IDs. The same is true for 98715/98715A 1369 * chips and the 98725, as well as the ASIX and ADMtek chips. In some 1370 * cases, the exact chip revision affects driver behavior. 1371 */ 1372 static int dc_probe(dev) 1373 device_t dev; 1374 { 1375 struct dc_type *t; 1376 1377 t = dc_devtype(dev); 1378 1379 if (t != NULL) { 1380 device_set_desc(dev, t->dc_name); 1381 return(0); 1382 } 1383 1384 return(ENXIO); 1385 } 1386 1387 static void dc_acpi(dev) 1388 device_t dev; 1389 { 1390 u_int32_t r, cptr; 1391 int unit; 1392 1393 unit = device_get_unit(dev); 1394 1395 /* Find the location of the capabilities block */ 1396 cptr = pci_read_config(dev, DC_PCI_CCAP, 4) & 0xFF; 1397 1398 r = pci_read_config(dev, cptr, 4) & 0xFF; 1399 if (r == 0x01) { 1400 1401 r = pci_read_config(dev, cptr + 4, 4); 1402 if (r & DC_PSTATE_D3) { 1403 u_int32_t iobase, membase, irq; 1404 1405 /* Save important PCI config data. */ 1406 iobase = pci_read_config(dev, DC_PCI_CFBIO, 4); 1407 membase = pci_read_config(dev, DC_PCI_CFBMA, 4); 1408 irq = pci_read_config(dev, DC_PCI_CFIT, 4); 1409 1410 /* Reset the power state. */ 1411 printf("dc%d: chip is in D%d power mode " 1412 "-- setting to D0\n", unit, r & DC_PSTATE_D3); 1413 r &= 0xFFFFFFFC; 1414 pci_write_config(dev, cptr + 4, r, 4); 1415 1416 /* Restore PCI config data. */ 1417 pci_write_config(dev, DC_PCI_CFBIO, iobase, 4); 1418 pci_write_config(dev, DC_PCI_CFBMA, membase, 4); 1419 pci_write_config(dev, DC_PCI_CFIT, irq, 4); 1420 } 1421 } 1422 return; 1423 } 1424 1425 /* 1426 * Attach the interface. Allocate softc structures, do ifmedia 1427 * setup and ethernet/BPF attach. 1428 */ 1429 static int dc_attach(dev) 1430 device_t dev; 1431 { 1432 int s; 1433 u_char eaddr[ETHER_ADDR_LEN]; 1434 u_int32_t command; 1435 struct dc_softc *sc; 1436 struct ifnet *ifp; 1437 u_int32_t revision; 1438 int unit, error = 0, rid, mac_offset; 1439 1440 s = splimp(); 1441 1442 sc = device_get_softc(dev); 1443 unit = device_get_unit(dev); 1444 bzero(sc, sizeof(struct dc_softc)); 1445 1446 /* 1447 * Handle power management nonsense. 1448 */ 1449 dc_acpi(dev); 1450 1451 /* 1452 * Map control/status registers. 1453 */ 1454 command = pci_read_config(dev, PCI_COMMAND_STATUS_REG, 4); 1455 command |= (PCIM_CMD_PORTEN|PCIM_CMD_MEMEN|PCIM_CMD_BUSMASTEREN); 1456 pci_write_config(dev, PCI_COMMAND_STATUS_REG, command, 4); 1457 command = pci_read_config(dev, PCI_COMMAND_STATUS_REG, 4); 1458 1459 #ifdef DC_USEIOSPACE 1460 if (!(command & PCIM_CMD_PORTEN)) { 1461 printf("dc%d: failed to enable I/O ports!\n", unit); 1462 error = ENXIO; 1463 goto fail; 1464 } 1465 #else 1466 if (!(command & PCIM_CMD_MEMEN)) { 1467 printf("dc%d: failed to enable memory mapping!\n", unit); 1468 error = ENXIO; 1469 goto fail; 1470 } 1471 #endif 1472 1473 rid = DC_RID; 1474 sc->dc_res = bus_alloc_resource(dev, DC_RES, &rid, 1475 0, ~0, 1, RF_ACTIVE); 1476 1477 if (sc->dc_res == NULL) { 1478 printf("dc%d: couldn't map ports/memory\n", unit); 1479 error = ENXIO; 1480 goto fail; 1481 } 1482 1483 sc->dc_btag = rman_get_bustag(sc->dc_res); 1484 sc->dc_bhandle = rman_get_bushandle(sc->dc_res); 1485 1486 /* Allocate interrupt */ 1487 rid = 0; 1488 sc->dc_irq = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, 0, ~0, 1, 1489 RF_SHAREABLE | RF_ACTIVE); 1490 1491 if (sc->dc_irq == NULL) { 1492 printf("dc%d: couldn't map interrupt\n", unit); 1493 bus_release_resource(dev, DC_RES, DC_RID, sc->dc_res); 1494 error = ENXIO; 1495 goto fail; 1496 } 1497 1498 error = bus_setup_intr(dev, sc->dc_irq, INTR_TYPE_NET, 1499 dc_intr, sc, &sc->dc_intrhand); 1500 1501 if (error) { 1502 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->dc_irq); 1503 bus_release_resource(dev, DC_RES, DC_RID, sc->dc_res); 1504 printf("dc%d: couldn't set up irq\n", unit); 1505 goto fail; 1506 } 1507 1508 /* Need this info to decide on a chip type. */ 1509 sc->dc_info = dc_devtype(dev); 1510 revision = pci_read_config(dev, DC_PCI_CFRV, 4) & 0x000000FF; 1511 1512 switch(sc->dc_info->dc_did) { 1513 case DC_DEVICEID_21143: 1514 sc->dc_type = DC_TYPE_21143; 1515 sc->dc_flags |= DC_TX_POLL|DC_TX_USE_TX_INTR; 1516 sc->dc_flags |= DC_REDUCED_MII_POLL; 1517 break; 1518 case DC_DEVICEID_DM9100: 1519 case DC_DEVICEID_DM9102: 1520 sc->dc_type = DC_TYPE_DM9102; 1521 sc->dc_flags |= DC_TX_COALESCE|DC_TX_USE_TX_INTR; 1522 sc->dc_flags |= DC_REDUCED_MII_POLL; 1523 sc->dc_pmode = DC_PMODE_MII; 1524 break; 1525 case DC_DEVICEID_AL981: 1526 sc->dc_type = DC_TYPE_AL981; 1527 sc->dc_flags |= DC_TX_USE_TX_INTR; 1528 sc->dc_flags |= DC_TX_ADMTEK_WAR; 1529 sc->dc_pmode = DC_PMODE_MII; 1530 break; 1531 case DC_DEVICEID_AN985: 1532 sc->dc_type = DC_TYPE_AN985; 1533 sc->dc_flags |= DC_TX_USE_TX_INTR; 1534 sc->dc_flags |= DC_TX_ADMTEK_WAR; 1535 sc->dc_pmode = DC_PMODE_MII; 1536 break; 1537 case DC_DEVICEID_98713: 1538 case DC_DEVICEID_98713_CP: 1539 if (revision < DC_REVISION_98713A) { 1540 sc->dc_type = DC_TYPE_98713; 1541 sc->dc_flags |= DC_REDUCED_MII_POLL; 1542 } 1543 if (revision >= DC_REVISION_98713A) 1544 sc->dc_type = DC_TYPE_98713A; 1545 sc->dc_flags |= DC_TX_POLL|DC_TX_USE_TX_INTR; 1546 break; 1547 case DC_DEVICEID_987x5: 1548 sc->dc_type = DC_TYPE_987x5; 1549 sc->dc_flags |= DC_TX_POLL|DC_TX_USE_TX_INTR; 1550 break; 1551 case DC_DEVICEID_82C115: 1552 sc->dc_type = DC_TYPE_PNICII; 1553 sc->dc_flags |= DC_TX_POLL|DC_TX_USE_TX_INTR; 1554 break; 1555 case DC_DEVICEID_82C168: 1556 sc->dc_type = DC_TYPE_PNIC; 1557 sc->dc_flags |= DC_TX_STORENFWD|DC_TX_INTR_ALWAYS; 1558 sc->dc_flags |= DC_PNIC_RX_BUG_WAR; 1559 sc->dc_pnic_rx_buf = malloc(DC_RXLEN * 5, M_DEVBUF, M_NOWAIT); 1560 if (revision < DC_REVISION_82C169) 1561 sc->dc_pmode = DC_PMODE_SYM; 1562 break; 1563 case DC_DEVICEID_AX88140A: 1564 sc->dc_type = DC_TYPE_ASIX; 1565 sc->dc_flags |= DC_TX_USE_TX_INTR|DC_TX_INTR_FIRSTFRAG; 1566 sc->dc_flags |= DC_REDUCED_MII_POLL; 1567 sc->dc_pmode = DC_PMODE_MII; 1568 break; 1569 default: 1570 printf("dc%d: unknown device: %x\n", sc->dc_unit, 1571 sc->dc_info->dc_did); 1572 break; 1573 } 1574 1575 /* Save the cache line size. */ 1576 if (DC_IS_DAVICOM(sc)) 1577 sc->dc_cachesize = 0; 1578 else 1579 sc->dc_cachesize = pci_read_config(dev, 1580 DC_PCI_CFLT, 4) & 0xFF; 1581 1582 /* Reset the adapter. */ 1583 dc_reset(sc); 1584 1585 /* Take 21143 out of snooze mode */ 1586 if (DC_IS_INTEL(sc)) { 1587 command = pci_read_config(dev, DC_PCI_CFDD, 4); 1588 command &= ~(DC_CFDD_SNOOZE_MODE|DC_CFDD_SLEEP_MODE); 1589 pci_write_config(dev, DC_PCI_CFDD, command, 4); 1590 } 1591 1592 /* 1593 * Try to learn something about the supported media. 1594 * We know that ASIX and ADMtek and Davicom devices 1595 * will *always* be using MII media, so that's a no-brainer. 1596 * The tricky ones are the Macronix/PNIC II and the 1597 * Intel 21143. 1598 */ 1599 if (DC_IS_INTEL(sc)) { 1600 u_int32_t media, cwuc; 1601 cwuc = pci_read_config(dev, DC_PCI_CWUC, 4); 1602 cwuc |= DC_CWUC_FORCE_WUL; 1603 pci_write_config(dev, DC_PCI_CWUC, cwuc, 4); 1604 DELAY(10000); 1605 media = pci_read_config(dev, DC_PCI_CWUC, 4); 1606 cwuc &= ~DC_CWUC_FORCE_WUL; 1607 pci_write_config(dev, DC_PCI_CWUC, cwuc, 4); 1608 DELAY(10000); 1609 if (media & DC_CWUC_MII_ABILITY) 1610 sc->dc_pmode = DC_PMODE_MII; 1611 if (media & DC_CWUC_SYM_ABILITY) 1612 sc->dc_pmode = DC_PMODE_SYM; 1613 /* 1614 * If none of the bits are set, then this NIC 1615 * isn't meant to support 'wake up LAN' mode. 1616 * This is usually only the case on multiport 1617 * cards, and these cards almost always have 1618 * MII transceivers. 1619 */ 1620 if (media == 0) 1621 sc->dc_pmode = DC_PMODE_MII; 1622 } else if (DC_IS_MACRONIX(sc) || DC_IS_PNICII(sc)) { 1623 if (sc->dc_type == DC_TYPE_98713) 1624 sc->dc_pmode = DC_PMODE_MII; 1625 else 1626 sc->dc_pmode = DC_PMODE_SYM; 1627 } else if (!sc->dc_pmode) 1628 sc->dc_pmode = DC_PMODE_MII; 1629 1630 /* 1631 * Get station address from the EEPROM. 1632 */ 1633 switch(sc->dc_type) { 1634 case DC_TYPE_98713: 1635 case DC_TYPE_98713A: 1636 case DC_TYPE_987x5: 1637 case DC_TYPE_PNICII: 1638 dc_read_eeprom(sc, (caddr_t)&mac_offset, 1639 (DC_EE_NODEADDR_OFFSET / 2), 1, 0); 1640 dc_read_eeprom(sc, (caddr_t)&eaddr, (mac_offset / 2), 3, 0); 1641 break; 1642 case DC_TYPE_PNIC: 1643 dc_read_eeprom(sc, (caddr_t)&eaddr, 0, 3, 1); 1644 break; 1645 case DC_TYPE_DM9102: 1646 case DC_TYPE_21143: 1647 case DC_TYPE_ASIX: 1648 dc_read_eeprom(sc, (caddr_t)&eaddr, DC_EE_NODEADDR, 3, 0); 1649 break; 1650 case DC_TYPE_AL981: 1651 case DC_TYPE_AN985: 1652 dc_read_eeprom(sc, (caddr_t)&eaddr, DC_AL_EE_NODEADDR, 3, 0); 1653 break; 1654 default: 1655 dc_read_eeprom(sc, (caddr_t)&eaddr, DC_EE_NODEADDR, 3, 0); 1656 break; 1657 } 1658 1659 /* 1660 * A 21143 or clone chip was detected. Inform the world. 1661 */ 1662 printf("dc%d: Ethernet address: %6D\n", unit, eaddr, ":"); 1663 1664 sc->dc_unit = unit; 1665 bcopy(eaddr, (char *)&sc->arpcom.ac_enaddr, ETHER_ADDR_LEN); 1666 1667 sc->dc_ldata = contigmalloc(sizeof(struct dc_list_data), M_DEVBUF, 1668 M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0); 1669 1670 if (sc->dc_ldata == NULL) { 1671 printf("dc%d: no memory for list buffers!\n", unit); 1672 bus_teardown_intr(dev, sc->dc_irq, sc->dc_intrhand); 1673 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->dc_irq); 1674 bus_release_resource(dev, DC_RES, DC_RID, sc->dc_res); 1675 error = ENXIO; 1676 goto fail; 1677 } 1678 1679 bzero(sc->dc_ldata, sizeof(struct dc_list_data)); 1680 1681 ifp = &sc->arpcom.ac_if; 1682 ifp->if_softc = sc; 1683 ifp->if_unit = unit; 1684 ifp->if_name = "dc"; 1685 ifp->if_mtu = ETHERMTU; 1686 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 1687 ifp->if_ioctl = dc_ioctl; 1688 ifp->if_output = ether_output; 1689 ifp->if_start = dc_start; 1690 ifp->if_watchdog = dc_watchdog; 1691 ifp->if_init = dc_init; 1692 ifp->if_baudrate = 10000000; 1693 ifp->if_snd.ifq_maxlen = DC_TX_LIST_CNT - 1; 1694 1695 /* 1696 * Do MII setup. 1697 */ 1698 error = mii_phy_probe(dev, &sc->dc_miibus, 1699 dc_ifmedia_upd, dc_ifmedia_sts); 1700 1701 if (error && DC_IS_INTEL(sc)) { 1702 sc->dc_pmode = DC_PMODE_SYM; 1703 mii_phy_probe(dev, &sc->dc_miibus, 1704 dc_ifmedia_upd, dc_ifmedia_sts); 1705 error = 0; 1706 } 1707 1708 if (error) { 1709 printf("dc%d: MII without any PHY!\n", sc->dc_unit); 1710 bus_teardown_intr(dev, sc->dc_irq, sc->dc_intrhand); 1711 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->dc_irq); 1712 bus_release_resource(dev, DC_RES, DC_RID, sc->dc_res); 1713 error = ENXIO; 1714 goto fail; 1715 } 1716 1717 /* 1718 * Call MI attach routines. 1719 */ 1720 if_attach(ifp); 1721 ether_ifattach(ifp); 1722 callout_handle_init(&sc->dc_stat_ch); 1723 1724 bpfattach(ifp, DLT_EN10MB, sizeof(struct ether_header)); 1725 1726 #ifdef __alpha__ 1727 sc->dc_srm_media = 0; 1728 1729 /* Remember the SRM console media setting */ 1730 if (DC_IS_INTEL(sc)) { 1731 command = pci_read_config(dev, DC_PCI_CFDD, 4); 1732 command &= ~(DC_CFDD_SNOOZE_MODE|DC_CFDD_SLEEP_MODE); 1733 switch ((command >> 8) & 0xff) { 1734 case 3: 1735 sc->dc_srm_media = IFM_10_T; 1736 break; 1737 case 4: 1738 sc->dc_srm_media = IFM_10_T | IFM_FDX; 1739 break; 1740 case 5: 1741 sc->dc_srm_media = IFM_100_TX; 1742 break; 1743 case 6: 1744 sc->dc_srm_media = IFM_100_TX | IFM_FDX; 1745 break; 1746 } 1747 if (sc->dc_srm_media) 1748 sc->dc_srm_media |= IFM_ACTIVE | IFM_ETHER; 1749 } 1750 #endif 1751 1752 1753 fail: 1754 splx(s); 1755 1756 return(error); 1757 } 1758 1759 static int dc_detach(dev) 1760 device_t dev; 1761 { 1762 struct dc_softc *sc; 1763 struct ifnet *ifp; 1764 int s; 1765 1766 s = splimp(); 1767 1768 sc = device_get_softc(dev); 1769 ifp = &sc->arpcom.ac_if; 1770 1771 dc_stop(sc); 1772 if_detach(ifp); 1773 1774 bus_generic_detach(dev); 1775 device_delete_child(dev, sc->dc_miibus); 1776 1777 bus_teardown_intr(dev, sc->dc_irq, sc->dc_intrhand); 1778 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->dc_irq); 1779 bus_release_resource(dev, DC_RES, DC_RID, sc->dc_res); 1780 1781 contigfree(sc->dc_ldata, sizeof(struct dc_list_data), M_DEVBUF); 1782 if (sc->dc_pnic_rx_buf != NULL) 1783 free(sc->dc_pnic_rx_buf, M_DEVBUF); 1784 1785 splx(s); 1786 1787 return(0); 1788 } 1789 1790 /* 1791 * Initialize the transmit descriptors. 1792 */ 1793 static int dc_list_tx_init(sc) 1794 struct dc_softc *sc; 1795 { 1796 struct dc_chain_data *cd; 1797 struct dc_list_data *ld; 1798 int i; 1799 1800 cd = &sc->dc_cdata; 1801 ld = sc->dc_ldata; 1802 for (i = 0; i < DC_TX_LIST_CNT; i++) { 1803 if (i == (DC_TX_LIST_CNT - 1)) { 1804 ld->dc_tx_list[i].dc_next = 1805 vtophys(&ld->dc_tx_list[0]); 1806 } else { 1807 ld->dc_tx_list[i].dc_next = 1808 vtophys(&ld->dc_tx_list[i + 1]); 1809 } 1810 cd->dc_tx_chain[i] = NULL; 1811 ld->dc_tx_list[i].dc_data = 0; 1812 ld->dc_tx_list[i].dc_ctl = 0; 1813 } 1814 1815 cd->dc_tx_prod = cd->dc_tx_cons = cd->dc_tx_cnt = 0; 1816 1817 return(0); 1818 } 1819 1820 1821 /* 1822 * Initialize the RX descriptors and allocate mbufs for them. Note that 1823 * we arrange the descriptors in a closed ring, so that the last descriptor 1824 * points back to the first. 1825 */ 1826 static int dc_list_rx_init(sc) 1827 struct dc_softc *sc; 1828 { 1829 struct dc_chain_data *cd; 1830 struct dc_list_data *ld; 1831 int i; 1832 1833 cd = &sc->dc_cdata; 1834 ld = sc->dc_ldata; 1835 1836 for (i = 0; i < DC_RX_LIST_CNT; i++) { 1837 if (dc_newbuf(sc, i, NULL) == ENOBUFS) 1838 return(ENOBUFS); 1839 if (i == (DC_RX_LIST_CNT - 1)) { 1840 ld->dc_rx_list[i].dc_next = 1841 vtophys(&ld->dc_rx_list[0]); 1842 } else { 1843 ld->dc_rx_list[i].dc_next = 1844 vtophys(&ld->dc_rx_list[i + 1]); 1845 } 1846 } 1847 1848 cd->dc_rx_prod = 0; 1849 1850 return(0); 1851 } 1852 1853 /* 1854 * Initialize an RX descriptor and attach an MBUF cluster. 1855 */ 1856 static int dc_newbuf(sc, i, m) 1857 struct dc_softc *sc; 1858 int i; 1859 struct mbuf *m; 1860 { 1861 struct mbuf *m_new = NULL; 1862 struct dc_desc *c; 1863 1864 c = &sc->dc_ldata->dc_rx_list[i]; 1865 1866 if (m == NULL) { 1867 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 1868 if (m_new == NULL) { 1869 printf("dc%d: no memory for rx list " 1870 "-- packet dropped!\n", sc->dc_unit); 1871 return(ENOBUFS); 1872 } 1873 1874 MCLGET(m_new, M_DONTWAIT); 1875 if (!(m_new->m_flags & M_EXT)) { 1876 printf("dc%d: no memory for rx list " 1877 "-- packet dropped!\n", sc->dc_unit); 1878 m_freem(m_new); 1879 return(ENOBUFS); 1880 } 1881 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 1882 } else { 1883 m_new = m; 1884 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 1885 m_new->m_data = m_new->m_ext.ext_buf; 1886 } 1887 1888 m_adj(m_new, sizeof(u_int64_t)); 1889 1890 /* 1891 * If this is a PNIC chip, zero the buffer. This is part 1892 * of the workaround for the receive bug in the 82c168 and 1893 * 82c169 chips. 1894 */ 1895 if (sc->dc_flags & DC_PNIC_RX_BUG_WAR) 1896 bzero((char *)mtod(m_new, char *), m_new->m_len); 1897 1898 sc->dc_cdata.dc_rx_chain[i] = m_new; 1899 c->dc_data = vtophys(mtod(m_new, caddr_t)); 1900 c->dc_ctl = DC_RXCTL_RLINK | DC_RXLEN; 1901 c->dc_status = DC_RXSTAT_OWN; 1902 1903 return(0); 1904 } 1905 1906 /* 1907 * Grrrrr. 1908 * The PNIC chip has a terrible bug in it that manifests itself during 1909 * periods of heavy activity. The exact mode of failure if difficult to 1910 * pinpoint: sometimes it only happens in promiscuous mode, sometimes it 1911 * will happen on slow machines. The bug is that sometimes instead of 1912 * uploading one complete frame during reception, it uploads what looks 1913 * like the entire contents of its FIFO memory. The frame we want is at 1914 * the end of the whole mess, but we never know exactly how much data has 1915 * been uploaded, so salvaging the frame is hard. 1916 * 1917 * There is only one way to do it reliably, and it's disgusting. 1918 * Here's what we know: 1919 * 1920 * - We know there will always be somewhere between one and three extra 1921 * descriptors uploaded. 1922 * 1923 * - We know the desired received frame will always be at the end of the 1924 * total data upload. 1925 * 1926 * - We know the size of the desired received frame because it will be 1927 * provided in the length field of the status word in the last descriptor. 1928 * 1929 * Here's what we do: 1930 * 1931 * - When we allocate buffers for the receive ring, we bzero() them. 1932 * This means that we know that the buffer contents should be all 1933 * zeros, except for data uploaded by the chip. 1934 * 1935 * - We also force the PNIC chip to upload frames that include the 1936 * ethernet CRC at the end. 1937 * 1938 * - We gather all of the bogus frame data into a single buffer. 1939 * 1940 * - We then position a pointer at the end of this buffer and scan 1941 * backwards until we encounter the first non-zero byte of data. 1942 * This is the end of the received frame. We know we will encounter 1943 * some data at the end of the frame because the CRC will always be 1944 * there, so even if the sender transmits a packet of all zeros, 1945 * we won't be fooled. 1946 * 1947 * - We know the size of the actual received frame, so we subtract 1948 * that value from the current pointer location. This brings us 1949 * to the start of the actual received packet. 1950 * 1951 * - We copy this into an mbuf and pass it on, along with the actual 1952 * frame length. 1953 * 1954 * The performance hit is tremendous, but it beats dropping frames all 1955 * the time. 1956 */ 1957 1958 #define DC_WHOLEFRAME (DC_RXSTAT_FIRSTFRAG|DC_RXSTAT_LASTFRAG) 1959 static void dc_pnic_rx_bug_war(sc, idx) 1960 struct dc_softc *sc; 1961 int idx; 1962 { 1963 struct dc_desc *cur_rx; 1964 struct dc_desc *c = NULL; 1965 struct mbuf *m = NULL; 1966 unsigned char *ptr; 1967 int i, total_len; 1968 u_int32_t rxstat = 0; 1969 1970 i = sc->dc_pnic_rx_bug_save; 1971 cur_rx = &sc->dc_ldata->dc_rx_list[idx]; 1972 ptr = sc->dc_pnic_rx_buf; 1973 bzero(ptr, sizeof(DC_RXLEN * 5)); 1974 1975 /* Copy all the bytes from the bogus buffers. */ 1976 while (1) { 1977 c = &sc->dc_ldata->dc_rx_list[i]; 1978 rxstat = c->dc_status; 1979 m = sc->dc_cdata.dc_rx_chain[i]; 1980 bcopy(mtod(m, char *), ptr, DC_RXLEN); 1981 ptr += DC_RXLEN; 1982 /* If this is the last buffer, break out. */ 1983 if (i == idx || rxstat & DC_RXSTAT_LASTFRAG) 1984 break; 1985 dc_newbuf(sc, i, m); 1986 DC_INC(i, DC_RX_LIST_CNT); 1987 } 1988 1989 /* Find the length of the actual receive frame. */ 1990 total_len = DC_RXBYTES(rxstat); 1991 1992 /* Scan backwards until we hit a non-zero byte. */ 1993 while(*ptr == 0x00) 1994 ptr--; 1995 1996 /* Round off. */ 1997 if ((uintptr_t)(ptr) & 0x3) 1998 ptr -= 1; 1999 2000 /* Now find the start of the frame. */ 2001 ptr -= total_len; 2002 if (ptr < sc->dc_pnic_rx_buf) 2003 ptr = sc->dc_pnic_rx_buf; 2004 2005 /* 2006 * Now copy the salvaged frame to the last mbuf and fake up 2007 * the status word to make it look like a successful 2008 * frame reception. 2009 */ 2010 dc_newbuf(sc, i, m); 2011 bcopy(ptr, mtod(m, char *), total_len); 2012 cur_rx->dc_status = rxstat | DC_RXSTAT_FIRSTFRAG; 2013 2014 return; 2015 } 2016 2017 /* 2018 * This routine searches the RX ring for dirty descriptors in the 2019 * event that the rxeof routine falls out of sync with the chip's 2020 * current descriptor pointer. This may happen sometimes as a result 2021 * of a "no RX buffer available" condition that happens when the chip 2022 * consumes all of the RX buffers before the driver has a chance to 2023 * process the RX ring. This routine may need to be called more than 2024 * once to bring the driver back in sync with the chip, however we 2025 * should still be getting RX DONE interrupts to drive the search 2026 * for new packets in the RX ring, so we should catch up eventually. 2027 */ 2028 static int dc_rx_resync(sc) 2029 struct dc_softc *sc; 2030 { 2031 int i, pos; 2032 struct dc_desc *cur_rx; 2033 2034 pos = sc->dc_cdata.dc_rx_prod; 2035 2036 for (i = 0; i < DC_RX_LIST_CNT; i++) { 2037 cur_rx = &sc->dc_ldata->dc_rx_list[pos]; 2038 if (!(cur_rx->dc_status & DC_RXSTAT_OWN)) 2039 break; 2040 DC_INC(pos, DC_RX_LIST_CNT); 2041 } 2042 2043 /* If the ring really is empty, then just return. */ 2044 if (i == DC_RX_LIST_CNT) 2045 return(0); 2046 2047 /* We've fallen behing the chip: catch it. */ 2048 sc->dc_cdata.dc_rx_prod = pos; 2049 2050 return(EAGAIN); 2051 } 2052 2053 /* 2054 * A frame has been uploaded: pass the resulting mbuf chain up to 2055 * the higher level protocols. 2056 */ 2057 static void dc_rxeof(sc) 2058 struct dc_softc *sc; 2059 { 2060 struct ether_header *eh; 2061 struct mbuf *m; 2062 struct ifnet *ifp; 2063 struct dc_desc *cur_rx; 2064 int i, total_len = 0; 2065 u_int32_t rxstat; 2066 2067 ifp = &sc->arpcom.ac_if; 2068 i = sc->dc_cdata.dc_rx_prod; 2069 2070 while(!(sc->dc_ldata->dc_rx_list[i].dc_status & DC_RXSTAT_OWN)) { 2071 struct mbuf *m0 = NULL; 2072 2073 cur_rx = &sc->dc_ldata->dc_rx_list[i]; 2074 rxstat = cur_rx->dc_status; 2075 m = sc->dc_cdata.dc_rx_chain[i]; 2076 total_len = DC_RXBYTES(rxstat); 2077 2078 if (sc->dc_flags & DC_PNIC_RX_BUG_WAR) { 2079 if ((rxstat & DC_WHOLEFRAME) != DC_WHOLEFRAME) { 2080 if (rxstat & DC_RXSTAT_FIRSTFRAG) 2081 sc->dc_pnic_rx_bug_save = i; 2082 if ((rxstat & DC_RXSTAT_LASTFRAG) == 0) { 2083 DC_INC(i, DC_RX_LIST_CNT); 2084 continue; 2085 } 2086 dc_pnic_rx_bug_war(sc, i); 2087 rxstat = cur_rx->dc_status; 2088 total_len = DC_RXBYTES(rxstat); 2089 } 2090 } 2091 2092 sc->dc_cdata.dc_rx_chain[i] = NULL; 2093 2094 /* 2095 * If an error occurs, update stats, clear the 2096 * status word and leave the mbuf cluster in place: 2097 * it should simply get re-used next time this descriptor 2098 * comes up in the ring. 2099 */ 2100 if (rxstat & DC_RXSTAT_RXERR) { 2101 ifp->if_ierrors++; 2102 if (rxstat & DC_RXSTAT_COLLSEEN) 2103 ifp->if_collisions++; 2104 dc_newbuf(sc, i, m); 2105 if (rxstat & DC_RXSTAT_CRCERR) { 2106 DC_INC(i, DC_RX_LIST_CNT); 2107 continue; 2108 } else { 2109 dc_init(sc); 2110 return; 2111 } 2112 } 2113 2114 /* No errors; receive the packet. */ 2115 total_len -= ETHER_CRC_LEN; 2116 2117 m0 = m_devget(mtod(m, char *) - ETHER_ALIGN, 2118 total_len + ETHER_ALIGN, 0, ifp, NULL); 2119 dc_newbuf(sc, i, m); 2120 DC_INC(i, DC_RX_LIST_CNT); 2121 if (m0 == NULL) { 2122 ifp->if_ierrors++; 2123 continue; 2124 } 2125 m_adj(m0, ETHER_ALIGN); 2126 m = m0; 2127 2128 ifp->if_ipackets++; 2129 eh = mtod(m, struct ether_header *); 2130 2131 /* Remove header from mbuf and pass it on. */ 2132 m_adj(m, sizeof(struct ether_header)); 2133 ether_input(ifp, eh, m); 2134 } 2135 2136 sc->dc_cdata.dc_rx_prod = i; 2137 } 2138 2139 /* 2140 * A frame was downloaded to the chip. It's safe for us to clean up 2141 * the list buffers. 2142 */ 2143 2144 static void dc_txeof(sc) 2145 struct dc_softc *sc; 2146 { 2147 struct dc_desc *cur_tx = NULL; 2148 struct ifnet *ifp; 2149 int idx; 2150 2151 ifp = &sc->arpcom.ac_if; 2152 2153 /* Clear the timeout timer. */ 2154 ifp->if_timer = 0; 2155 2156 /* 2157 * Go through our tx list and free mbufs for those 2158 * frames that have been transmitted. 2159 */ 2160 idx = sc->dc_cdata.dc_tx_cons; 2161 while(idx != sc->dc_cdata.dc_tx_prod) { 2162 u_int32_t txstat; 2163 2164 cur_tx = &sc->dc_ldata->dc_tx_list[idx]; 2165 txstat = cur_tx->dc_status; 2166 2167 if (txstat & DC_TXSTAT_OWN) 2168 break; 2169 2170 if (!(cur_tx->dc_ctl & DC_TXCTL_LASTFRAG) || 2171 cur_tx->dc_ctl & DC_TXCTL_SETUP) { 2172 sc->dc_cdata.dc_tx_cnt--; 2173 if (cur_tx->dc_ctl & DC_TXCTL_SETUP) { 2174 /* 2175 * Yes, the PNIC is so brain damaged 2176 * that it will sometimes generate a TX 2177 * underrun error while DMAing the RX 2178 * filter setup frame. If we detect this, 2179 * we have to send the setup frame again, 2180 * or else the filter won't be programmed 2181 * correctly. 2182 */ 2183 if (DC_IS_PNIC(sc)) { 2184 if (txstat & DC_TXSTAT_ERRSUM) 2185 dc_setfilt(sc); 2186 } 2187 sc->dc_cdata.dc_tx_chain[idx] = NULL; 2188 } 2189 DC_INC(idx, DC_TX_LIST_CNT); 2190 continue; 2191 } 2192 2193 if (/*sc->dc_type == DC_TYPE_21143 &&*/ 2194 sc->dc_pmode == DC_PMODE_MII && 2195 ((txstat & 0xFFFF) & ~(DC_TXSTAT_ERRSUM| 2196 DC_TXSTAT_NOCARRIER|DC_TXSTAT_CARRLOST))) 2197 txstat &= ~DC_TXSTAT_ERRSUM; 2198 2199 if (txstat & DC_TXSTAT_ERRSUM) { 2200 ifp->if_oerrors++; 2201 if (txstat & DC_TXSTAT_EXCESSCOLL) 2202 ifp->if_collisions++; 2203 if (txstat & DC_TXSTAT_LATECOLL) 2204 ifp->if_collisions++; 2205 if (!(txstat & DC_TXSTAT_UNDERRUN)) { 2206 dc_init(sc); 2207 return; 2208 } 2209 } 2210 2211 ifp->if_collisions += (txstat & DC_TXSTAT_COLLCNT) >> 3; 2212 2213 ifp->if_opackets++; 2214 if (sc->dc_cdata.dc_tx_chain[idx] != NULL) { 2215 m_freem(sc->dc_cdata.dc_tx_chain[idx]); 2216 sc->dc_cdata.dc_tx_chain[idx] = NULL; 2217 } 2218 2219 sc->dc_cdata.dc_tx_cnt--; 2220 DC_INC(idx, DC_TX_LIST_CNT); 2221 } 2222 2223 sc->dc_cdata.dc_tx_cons = idx; 2224 if (cur_tx != NULL) 2225 ifp->if_flags &= ~IFF_OACTIVE; 2226 2227 return; 2228 } 2229 2230 static void dc_tick(xsc) 2231 void *xsc; 2232 { 2233 struct dc_softc *sc; 2234 struct mii_data *mii; 2235 struct ifnet *ifp; 2236 int s; 2237 u_int32_t r; 2238 2239 s = splimp(); 2240 2241 sc = xsc; 2242 ifp = &sc->arpcom.ac_if; 2243 mii = device_get_softc(sc->dc_miibus); 2244 2245 if (sc->dc_flags & DC_REDUCED_MII_POLL) { 2246 r = CSR_READ_4(sc, DC_ISR); 2247 if (DC_IS_INTEL(sc)) { 2248 if (r & DC_ISR_LINKFAIL) 2249 sc->dc_link = 0; 2250 if (sc->dc_link == 0) 2251 mii_tick(mii); 2252 } else { 2253 if ((r & DC_ISR_RX_STATE) == DC_RXSTATE_WAIT && 2254 sc->dc_cdata.dc_tx_prod == 0) 2255 mii_tick(mii); 2256 } 2257 } else 2258 mii_tick(mii); 2259 2260 /* 2261 * When the init routine completes, we expect to be able to send 2262 * packets right away, and in fact the network code will send a 2263 * gratuitous ARP the moment the init routine marks the interface 2264 * as running. However, even though the MAC may have been initialized, 2265 * there may be a delay of a few seconds before the PHY completes 2266 * autonegotiation and the link is brought up. Any transmissions 2267 * made during that delay will be lost. Dealing with this is tricky: 2268 * we can't just pause in the init routine while waiting for the 2269 * PHY to come ready since that would bring the whole system to 2270 * a screeching halt for several seconds. 2271 * 2272 * What we do here is prevent the TX start routine from sending 2273 * any packets until a link has been established. After the 2274 * interface has been initialized, the tick routine will poll 2275 * the state of the PHY until the IFM_ACTIVE flag is set. Until 2276 * that time, packets will stay in the send queue, and once the 2277 * link comes up, they will be flushed out to the wire. 2278 */ 2279 if (!sc->dc_link) { 2280 mii_pollstat(mii); 2281 if (mii->mii_media_status & IFM_ACTIVE && 2282 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) { 2283 sc->dc_link++; 2284 if (ifp->if_snd.ifq_head != NULL) 2285 dc_start(ifp); 2286 } 2287 } 2288 2289 sc->dc_stat_ch = timeout(dc_tick, sc, hz); 2290 2291 splx(s); 2292 2293 return; 2294 } 2295 2296 static void dc_intr(arg) 2297 void *arg; 2298 { 2299 struct dc_softc *sc; 2300 struct ifnet *ifp; 2301 u_int32_t status; 2302 2303 sc = arg; 2304 ifp = &sc->arpcom.ac_if; 2305 2306 /* Supress unwanted interrupts */ 2307 if (!(ifp->if_flags & IFF_UP)) { 2308 if (CSR_READ_4(sc, DC_ISR) & DC_INTRS) 2309 dc_stop(sc); 2310 return; 2311 } 2312 2313 /* Disable interrupts. */ 2314 CSR_WRITE_4(sc, DC_IMR, 0x00000000); 2315 2316 while((status = CSR_READ_4(sc, DC_ISR)) & DC_INTRS) { 2317 2318 CSR_WRITE_4(sc, DC_ISR, status); 2319 2320 if (status & DC_ISR_RX_OK) { 2321 int curpkts; 2322 curpkts = ifp->if_ipackets; 2323 dc_rxeof(sc); 2324 if (curpkts == ifp->if_ipackets) { 2325 while(dc_rx_resync(sc)) 2326 dc_rxeof(sc); 2327 } 2328 } 2329 2330 if (status & (DC_ISR_TX_OK|DC_ISR_TX_NOBUF)) 2331 dc_txeof(sc); 2332 2333 if (status & DC_ISR_TX_IDLE) { 2334 dc_txeof(sc); 2335 if (sc->dc_cdata.dc_tx_cnt) { 2336 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_TX_ON); 2337 CSR_WRITE_4(sc, DC_TXSTART, 0xFFFFFFFF); 2338 } 2339 } 2340 2341 if (status & DC_ISR_TX_UNDERRUN) { 2342 u_int32_t cfg; 2343 2344 printf("dc%d: TX underrun -- ", sc->dc_unit); 2345 if (DC_IS_DAVICOM(sc) || DC_IS_INTEL(sc)) 2346 dc_init(sc); 2347 cfg = CSR_READ_4(sc, DC_NETCFG); 2348 cfg &= ~DC_NETCFG_TX_THRESH; 2349 if (sc->dc_txthresh == DC_TXTHRESH_160BYTES) { 2350 printf("using store and forward mode\n"); 2351 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_STORENFWD); 2352 } else if (sc->dc_flags & DC_TX_STORENFWD) { 2353 printf("resetting\n"); 2354 } else { 2355 sc->dc_txthresh += 0x4000; 2356 printf("increasing TX threshold\n"); 2357 CSR_WRITE_4(sc, DC_NETCFG, cfg); 2358 DC_SETBIT(sc, DC_NETCFG, sc->dc_txthresh); 2359 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_STORENFWD); 2360 } 2361 } 2362 2363 if ((status & DC_ISR_RX_WATDOGTIMEO) 2364 || (status & DC_ISR_RX_NOBUF)) { 2365 int curpkts; 2366 curpkts = ifp->if_ipackets; 2367 dc_rxeof(sc); 2368 if (curpkts == ifp->if_ipackets) { 2369 while(dc_rx_resync(sc)) 2370 dc_rxeof(sc); 2371 } 2372 } 2373 2374 if (status & DC_ISR_BUS_ERR) { 2375 dc_reset(sc); 2376 dc_init(sc); 2377 } 2378 } 2379 2380 /* Re-enable interrupts. */ 2381 CSR_WRITE_4(sc, DC_IMR, DC_INTRS); 2382 2383 if (ifp->if_snd.ifq_head != NULL) 2384 dc_start(ifp); 2385 2386 return; 2387 } 2388 2389 /* 2390 * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data 2391 * pointers to the fragment pointers. 2392 */ 2393 static int dc_encap(sc, m_head, txidx) 2394 struct dc_softc *sc; 2395 struct mbuf *m_head; 2396 u_int32_t *txidx; 2397 { 2398 struct dc_desc *f = NULL; 2399 struct mbuf *m; 2400 int frag, cur, cnt = 0; 2401 2402 /* 2403 * Start packing the mbufs in this chain into 2404 * the fragment pointers. Stop when we run out 2405 * of fragments or hit the end of the mbuf chain. 2406 */ 2407 m = m_head; 2408 cur = frag = *txidx; 2409 2410 for (m = m_head; m != NULL; m = m->m_next) { 2411 if (m->m_len != 0) { 2412 if (sc->dc_flags & DC_TX_ADMTEK_WAR) { 2413 if (*txidx != sc->dc_cdata.dc_tx_prod && 2414 frag == (DC_TX_LIST_CNT - 1)) 2415 return(ENOBUFS); 2416 } 2417 if ((DC_TX_LIST_CNT - 2418 (sc->dc_cdata.dc_tx_cnt + cnt)) < 5) 2419 return(ENOBUFS); 2420 2421 f = &sc->dc_ldata->dc_tx_list[frag]; 2422 f->dc_ctl = DC_TXCTL_TLINK | m->m_len; 2423 if (cnt == 0) { 2424 f->dc_status = 0; 2425 f->dc_ctl |= DC_TXCTL_FIRSTFRAG; 2426 } else 2427 f->dc_status = DC_TXSTAT_OWN; 2428 f->dc_data = vtophys(mtod(m, vm_offset_t)); 2429 cur = frag; 2430 DC_INC(frag, DC_TX_LIST_CNT); 2431 cnt++; 2432 } 2433 } 2434 2435 if (m != NULL) 2436 return(ENOBUFS); 2437 2438 sc->dc_cdata.dc_tx_cnt += cnt; 2439 sc->dc_cdata.dc_tx_chain[cur] = m_head; 2440 sc->dc_ldata->dc_tx_list[cur].dc_ctl |= DC_TXCTL_LASTFRAG; 2441 if (sc->dc_flags & DC_TX_INTR_FIRSTFRAG) 2442 sc->dc_ldata->dc_tx_list[*txidx].dc_ctl |= DC_TXCTL_FINT; 2443 if (sc->dc_flags & DC_TX_INTR_ALWAYS) 2444 sc->dc_ldata->dc_tx_list[cur].dc_ctl |= DC_TXCTL_FINT; 2445 if (sc->dc_flags & DC_TX_USE_TX_INTR && sc->dc_cdata.dc_tx_cnt > 64) 2446 sc->dc_ldata->dc_tx_list[cur].dc_ctl |= DC_TXCTL_FINT; 2447 sc->dc_ldata->dc_tx_list[*txidx].dc_status = DC_TXSTAT_OWN; 2448 *txidx = frag; 2449 2450 return(0); 2451 } 2452 2453 /* 2454 * Coalesce an mbuf chain into a single mbuf cluster buffer. 2455 * Needed for some really badly behaved chips that just can't 2456 * do scatter/gather correctly. 2457 */ 2458 static int dc_coal(sc, m_head) 2459 struct dc_softc *sc; 2460 struct mbuf **m_head; 2461 { 2462 struct mbuf *m_new, *m; 2463 2464 m = *m_head; 2465 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 2466 if (m_new == NULL) { 2467 printf("dc%d: no memory for tx list", sc->dc_unit); 2468 return(ENOBUFS); 2469 } 2470 if (m->m_pkthdr.len > MHLEN) { 2471 MCLGET(m_new, M_DONTWAIT); 2472 if (!(m_new->m_flags & M_EXT)) { 2473 m_freem(m_new); 2474 printf("dc%d: no memory for tx list", sc->dc_unit); 2475 return(ENOBUFS); 2476 } 2477 } 2478 m_copydata(m, 0, m->m_pkthdr.len, mtod(m_new, caddr_t)); 2479 m_new->m_pkthdr.len = m_new->m_len = m->m_pkthdr.len; 2480 m_freem(m); 2481 *m_head = m_new; 2482 2483 return(0); 2484 } 2485 2486 /* 2487 * Main transmit routine. To avoid having to do mbuf copies, we put pointers 2488 * to the mbuf data regions directly in the transmit lists. We also save a 2489 * copy of the pointers since the transmit list fragment pointers are 2490 * physical addresses. 2491 */ 2492 2493 static void dc_start(ifp) 2494 struct ifnet *ifp; 2495 { 2496 struct dc_softc *sc; 2497 struct mbuf *m_head = NULL; 2498 int idx; 2499 2500 sc = ifp->if_softc; 2501 2502 if (!sc->dc_link) 2503 return; 2504 2505 if (ifp->if_flags & IFF_OACTIVE) 2506 return; 2507 2508 idx = sc->dc_cdata.dc_tx_prod; 2509 2510 while(sc->dc_cdata.dc_tx_chain[idx] == NULL) { 2511 IF_DEQUEUE(&ifp->if_snd, m_head); 2512 if (m_head == NULL) 2513 break; 2514 2515 if (sc->dc_flags & DC_TX_COALESCE) { 2516 if (dc_coal(sc, &m_head)) { 2517 IF_PREPEND(&ifp->if_snd, m_head); 2518 ifp->if_flags |= IFF_OACTIVE; 2519 break; 2520 } 2521 } 2522 2523 if (dc_encap(sc, m_head, &idx)) { 2524 IF_PREPEND(&ifp->if_snd, m_head); 2525 ifp->if_flags |= IFF_OACTIVE; 2526 break; 2527 } 2528 2529 /* 2530 * If there's a BPF listener, bounce a copy of this frame 2531 * to him. 2532 */ 2533 if (ifp->if_bpf) 2534 bpf_mtap(ifp, m_head); 2535 } 2536 2537 /* Transmit */ 2538 sc->dc_cdata.dc_tx_prod = idx; 2539 if (!(sc->dc_flags & DC_TX_POLL)) 2540 CSR_WRITE_4(sc, DC_TXSTART, 0xFFFFFFFF); 2541 2542 /* 2543 * Set a timeout in case the chip goes out to lunch. 2544 */ 2545 ifp->if_timer = 5; 2546 2547 return; 2548 } 2549 2550 static void dc_init(xsc) 2551 void *xsc; 2552 { 2553 struct dc_softc *sc = xsc; 2554 struct ifnet *ifp = &sc->arpcom.ac_if; 2555 struct mii_data *mii; 2556 int s; 2557 2558 s = splimp(); 2559 2560 mii = device_get_softc(sc->dc_miibus); 2561 2562 /* 2563 * Cancel pending I/O and free all RX/TX buffers. 2564 */ 2565 dc_stop(sc); 2566 dc_reset(sc); 2567 2568 /* 2569 * Set cache alignment and burst length. 2570 */ 2571 if (DC_IS_ASIX(sc) || DC_IS_DAVICOM(sc)) 2572 CSR_WRITE_4(sc, DC_BUSCTL, 0); 2573 else 2574 CSR_WRITE_4(sc, DC_BUSCTL, DC_BUSCTL_MRME|DC_BUSCTL_MRLE); 2575 if (DC_IS_DAVICOM(sc) || DC_IS_INTEL(sc)) { 2576 DC_SETBIT(sc, DC_BUSCTL, DC_BURSTLEN_USECA); 2577 } else { 2578 DC_SETBIT(sc, DC_BUSCTL, DC_BURSTLEN_16LONG); 2579 } 2580 if (sc->dc_flags & DC_TX_POLL) 2581 DC_SETBIT(sc, DC_BUSCTL, DC_TXPOLL_1); 2582 switch(sc->dc_cachesize) { 2583 case 32: 2584 DC_SETBIT(sc, DC_BUSCTL, DC_CACHEALIGN_32LONG); 2585 break; 2586 case 16: 2587 DC_SETBIT(sc, DC_BUSCTL, DC_CACHEALIGN_16LONG); 2588 break; 2589 case 8: 2590 DC_SETBIT(sc, DC_BUSCTL, DC_CACHEALIGN_8LONG); 2591 break; 2592 case 0: 2593 default: 2594 DC_SETBIT(sc, DC_BUSCTL, DC_CACHEALIGN_NONE); 2595 break; 2596 } 2597 2598 if (sc->dc_flags & DC_TX_STORENFWD) 2599 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_STORENFWD); 2600 else { 2601 if (sc->dc_txthresh == DC_TXTHRESH_160BYTES) { 2602 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_STORENFWD); 2603 } else { 2604 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_STORENFWD); 2605 DC_SETBIT(sc, DC_NETCFG, sc->dc_txthresh); 2606 } 2607 } 2608 2609 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_NO_RXCRC); 2610 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_TX_BACKOFF); 2611 2612 if (DC_IS_MACRONIX(sc) || DC_IS_PNICII(sc)) { 2613 /* 2614 * The app notes for the 98713 and 98715A say that 2615 * in order to have the chips operate properly, a magic 2616 * number must be written to CSR16. Macronix does not 2617 * document the meaning of these bits so there's no way 2618 * to know exactly what they do. The 98713 has a magic 2619 * number all its own; the rest all use a different one. 2620 */ 2621 DC_CLRBIT(sc, DC_MX_MAGICPACKET, 0xFFFF0000); 2622 if (sc->dc_type == DC_TYPE_98713) 2623 DC_SETBIT(sc, DC_MX_MAGICPACKET, DC_MX_MAGIC_98713); 2624 else 2625 DC_SETBIT(sc, DC_MX_MAGICPACKET, DC_MX_MAGIC_98715); 2626 } 2627 2628 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_TX_THRESH); 2629 DC_SETBIT(sc, DC_NETCFG, DC_TXTHRESH_72BYTES); 2630 2631 /* Init circular RX list. */ 2632 if (dc_list_rx_init(sc) == ENOBUFS) { 2633 printf("dc%d: initialization failed: no " 2634 "memory for rx buffers\n", sc->dc_unit); 2635 dc_stop(sc); 2636 (void)splx(s); 2637 return; 2638 } 2639 2640 /* 2641 * Init tx descriptors. 2642 */ 2643 dc_list_tx_init(sc); 2644 2645 /* 2646 * Load the address of the RX list. 2647 */ 2648 CSR_WRITE_4(sc, DC_RXADDR, vtophys(&sc->dc_ldata->dc_rx_list[0])); 2649 CSR_WRITE_4(sc, DC_TXADDR, vtophys(&sc->dc_ldata->dc_tx_list[0])); 2650 2651 /* 2652 * Enable interrupts. 2653 */ 2654 CSR_WRITE_4(sc, DC_IMR, DC_INTRS); 2655 CSR_WRITE_4(sc, DC_ISR, 0xFFFFFFFF); 2656 2657 /* Enable transmitter. */ 2658 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_TX_ON); 2659 2660 /* 2661 * Load the RX/multicast filter. We do this sort of late 2662 * because the filter programming scheme on the 21143 and 2663 * some clones requires DMAing a setup frame via the TX 2664 * engine, and we need the transmitter enabled for that. 2665 */ 2666 dc_setfilt(sc); 2667 2668 /* Enable receiver. */ 2669 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_ON); 2670 CSR_WRITE_4(sc, DC_RXSTART, 0xFFFFFFFF); 2671 2672 mii_mediachg(mii); 2673 dc_setcfg(sc, sc->dc_if_media); 2674 2675 ifp->if_flags |= IFF_RUNNING; 2676 ifp->if_flags &= ~IFF_OACTIVE; 2677 2678 (void)splx(s); 2679 2680 sc->dc_stat_ch = timeout(dc_tick, sc, hz); 2681 2682 #ifdef __alpha__ 2683 if(sc->dc_srm_media) { 2684 struct ifreq ifr; 2685 2686 ifr.ifr_media = sc->dc_srm_media; 2687 ifmedia_ioctl(ifp, &ifr, &mii->mii_media, SIOCSIFMEDIA); 2688 sc->dc_srm_media = 0; 2689 } 2690 #endif 2691 return; 2692 } 2693 2694 /* 2695 * Set media options. 2696 */ 2697 static int dc_ifmedia_upd(ifp) 2698 struct ifnet *ifp; 2699 { 2700 struct dc_softc *sc; 2701 struct mii_data *mii; 2702 struct ifmedia *ifm; 2703 2704 sc = ifp->if_softc; 2705 mii = device_get_softc(sc->dc_miibus); 2706 mii_mediachg(mii); 2707 ifm = &mii->mii_media; 2708 2709 if (DC_IS_DAVICOM(sc) && 2710 IFM_SUBTYPE(ifm->ifm_media) == IFM_homePNA) 2711 dc_setcfg(sc, ifm->ifm_media); 2712 else 2713 sc->dc_link = 0; 2714 2715 return(0); 2716 } 2717 2718 /* 2719 * Report current media status. 2720 */ 2721 static void dc_ifmedia_sts(ifp, ifmr) 2722 struct ifnet *ifp; 2723 struct ifmediareq *ifmr; 2724 { 2725 struct dc_softc *sc; 2726 struct mii_data *mii; 2727 struct ifmedia *ifm; 2728 2729 sc = ifp->if_softc; 2730 mii = device_get_softc(sc->dc_miibus); 2731 mii_pollstat(mii); 2732 ifm = &mii->mii_media; 2733 if (DC_IS_DAVICOM(sc)) { 2734 if (IFM_SUBTYPE(ifm->ifm_media) == IFM_homePNA) { 2735 ifmr->ifm_active = ifm->ifm_media; 2736 ifmr->ifm_status = 0; 2737 return; 2738 } 2739 } 2740 ifmr->ifm_active = mii->mii_media_active; 2741 ifmr->ifm_status = mii->mii_media_status; 2742 2743 return; 2744 } 2745 2746 static int dc_ioctl(ifp, command, data) 2747 struct ifnet *ifp; 2748 u_long command; 2749 caddr_t data; 2750 { 2751 struct dc_softc *sc = ifp->if_softc; 2752 struct ifreq *ifr = (struct ifreq *) data; 2753 struct mii_data *mii; 2754 int s, error = 0; 2755 2756 s = splimp(); 2757 2758 switch(command) { 2759 case SIOCSIFADDR: 2760 case SIOCGIFADDR: 2761 case SIOCSIFMTU: 2762 error = ether_ioctl(ifp, command, data); 2763 break; 2764 case SIOCSIFFLAGS: 2765 if (ifp->if_flags & IFF_UP) { 2766 if (ifp->if_flags & IFF_RUNNING && 2767 ifp->if_flags & IFF_PROMISC && 2768 !(sc->dc_if_flags & IFF_PROMISC)) { 2769 dc_setfilt(sc); 2770 } else if (ifp->if_flags & IFF_RUNNING && 2771 !(ifp->if_flags & IFF_PROMISC) && 2772 sc->dc_if_flags & IFF_PROMISC) { 2773 dc_setfilt(sc); 2774 } else if (!(ifp->if_flags & IFF_RUNNING)) { 2775 sc->dc_txthresh = 0; 2776 dc_init(sc); 2777 } 2778 } else { 2779 if (ifp->if_flags & IFF_RUNNING) 2780 dc_stop(sc); 2781 } 2782 sc->dc_if_flags = ifp->if_flags; 2783 error = 0; 2784 break; 2785 case SIOCADDMULTI: 2786 case SIOCDELMULTI: 2787 dc_setfilt(sc); 2788 error = 0; 2789 break; 2790 case SIOCGIFMEDIA: 2791 case SIOCSIFMEDIA: 2792 mii = device_get_softc(sc->dc_miibus); 2793 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 2794 #ifdef __alpha__ 2795 if (sc->dc_srm_media) 2796 sc->dc_srm_media = 0; 2797 #endif 2798 break; 2799 default: 2800 error = EINVAL; 2801 break; 2802 } 2803 2804 (void)splx(s); 2805 2806 return(error); 2807 } 2808 2809 static void dc_watchdog(ifp) 2810 struct ifnet *ifp; 2811 { 2812 struct dc_softc *sc; 2813 2814 sc = ifp->if_softc; 2815 2816 ifp->if_oerrors++; 2817 printf("dc%d: watchdog timeout\n", sc->dc_unit); 2818 2819 dc_stop(sc); 2820 dc_reset(sc); 2821 dc_init(sc); 2822 2823 if (ifp->if_snd.ifq_head != NULL) 2824 dc_start(ifp); 2825 2826 return; 2827 } 2828 2829 /* 2830 * Stop the adapter and free any mbufs allocated to the 2831 * RX and TX lists. 2832 */ 2833 static void dc_stop(sc) 2834 struct dc_softc *sc; 2835 { 2836 register int i; 2837 struct ifnet *ifp; 2838 2839 ifp = &sc->arpcom.ac_if; 2840 ifp->if_timer = 0; 2841 2842 untimeout(dc_tick, sc, sc->dc_stat_ch); 2843 2844 DC_CLRBIT(sc, DC_NETCFG, (DC_NETCFG_RX_ON|DC_NETCFG_TX_ON)); 2845 CSR_WRITE_4(sc, DC_IMR, 0x00000000); 2846 CSR_WRITE_4(sc, DC_TXADDR, 0x00000000); 2847 CSR_WRITE_4(sc, DC_RXADDR, 0x00000000); 2848 sc->dc_link = 0; 2849 2850 /* 2851 * Free data in the RX lists. 2852 */ 2853 for (i = 0; i < DC_RX_LIST_CNT; i++) { 2854 if (sc->dc_cdata.dc_rx_chain[i] != NULL) { 2855 m_freem(sc->dc_cdata.dc_rx_chain[i]); 2856 sc->dc_cdata.dc_rx_chain[i] = NULL; 2857 } 2858 } 2859 bzero((char *)&sc->dc_ldata->dc_rx_list, 2860 sizeof(sc->dc_ldata->dc_rx_list)); 2861 2862 /* 2863 * Free the TX list buffers. 2864 */ 2865 for (i = 0; i < DC_TX_LIST_CNT; i++) { 2866 if (sc->dc_cdata.dc_tx_chain[i] != NULL) { 2867 if (sc->dc_ldata->dc_tx_list[i].dc_ctl & 2868 DC_TXCTL_SETUP) { 2869 sc->dc_cdata.dc_tx_chain[i] = NULL; 2870 continue; 2871 } 2872 m_freem(sc->dc_cdata.dc_tx_chain[i]); 2873 sc->dc_cdata.dc_tx_chain[i] = NULL; 2874 } 2875 } 2876 2877 bzero((char *)&sc->dc_ldata->dc_tx_list, 2878 sizeof(sc->dc_ldata->dc_tx_list)); 2879 2880 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 2881 2882 return; 2883 } 2884 2885 /* 2886 * Stop all chip I/O so that the kernel's probe routines don't 2887 * get confused by errant DMAs when rebooting. 2888 */ 2889 static void dc_shutdown(dev) 2890 device_t dev; 2891 { 2892 struct dc_softc *sc; 2893 2894 sc = device_get_softc(dev); 2895 2896 dc_stop(sc); 2897 2898 return; 2899 } 2900