1 /* 2 * Copyright (c) 1997, 1998, 1999 3 * Bill Paul <wpaul@ee.columbia.edu>. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 3. All advertising materials mentioning features or use of this software 14 * must display the following acknowledgement: 15 * This product includes software developed by Bill Paul. 16 * 4. Neither the name of the author nor the names of any co-contributors 17 * may be used to endorse or promote products derived from this software 18 * without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30 * THE POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33 /* 34 * DEC "tulip" clone ethernet driver. Supports the DEC/Intel 21143 35 * series chips and several workalikes including the following: 36 * 37 * Macronix 98713/98715/98725/98727/98732 PMAC (www.macronix.com) 38 * Macronix/Lite-On 82c115 PNIC II (www.macronix.com) 39 * Lite-On 82c168/82c169 PNIC (www.litecom.com) 40 * ASIX Electronics AX88140A (www.asix.com.tw) 41 * ASIX Electronics AX88141 (www.asix.com.tw) 42 * ADMtek AL981 (www.admtek.com.tw) 43 * ADMtek AN985 (www.admtek.com.tw) 44 * Davicom DM9100, DM9102, DM9102A (www.davicom8.com) 45 * Accton EN1217 (www.accton.com) 46 * Xircom X3201 (www.xircom.com) 47 * Abocom FE2500 48 * Conexant LANfinity (www.conexant.com) 49 * 50 * Datasheets for the 21143 are available at developer.intel.com. 51 * Datasheets for the clone parts can be found at their respective sites. 52 * (Except for the PNIC; see www.freebsd.org/~wpaul/PNIC/pnic.ps.gz.) 53 * The PNIC II is essentially a Macronix 98715A chip; the only difference 54 * worth noting is that its multicast hash table is only 128 bits wide 55 * instead of 512. 56 * 57 * Written by Bill Paul <wpaul@ee.columbia.edu> 58 * Electrical Engineering Department 59 * Columbia University, New York City 60 */ 61 62 /* 63 * The Intel 21143 is the successor to the DEC 21140. It is basically 64 * the same as the 21140 but with a few new features. The 21143 supports 65 * three kinds of media attachments: 66 * 67 * o MII port, for 10Mbps and 100Mbps support and NWAY 68 * autonegotiation provided by an external PHY. 69 * o SYM port, for symbol mode 100Mbps support. 70 * o 10baseT port. 71 * o AUI/BNC port. 72 * 73 * The 100Mbps SYM port and 10baseT port can be used together in 74 * combination with the internal NWAY support to create a 10/100 75 * autosensing configuration. 76 * 77 * Note that not all tulip workalikes are handled in this driver: we only 78 * deal with those which are relatively well behaved. The Winbond is 79 * handled separately due to its different register offsets and the 80 * special handling needed for its various bugs. The PNIC is handled 81 * here, but I'm not thrilled about it. 82 * 83 * All of the workalike chips use some form of MII transceiver support 84 * with the exception of the Macronix chips, which also have a SYM port. 85 * The ASIX AX88140A is also documented to have a SYM port, but all 86 * the cards I've seen use an MII transceiver, probably because the 87 * AX88140A doesn't support internal NWAY. 88 */ 89 90 #include <sys/cdefs.h> 91 __FBSDID("$FreeBSD$"); 92 93 #include <sys/param.h> 94 #include <sys/systm.h> 95 #include <sys/sockio.h> 96 #include <sys/mbuf.h> 97 #include <sys/malloc.h> 98 #include <sys/kernel.h> 99 #include <sys/socket.h> 100 #include <sys/sysctl.h> 101 102 #include <net/if.h> 103 #include <net/if_arp.h> 104 #include <net/ethernet.h> 105 #include <net/if_dl.h> 106 #include <net/if_media.h> 107 #include <net/if_types.h> 108 #include <net/if_vlan_var.h> 109 110 #include <net/bpf.h> 111 112 #include <vm/vm.h> /* for vtophys */ 113 #include <vm/pmap.h> /* for vtophys */ 114 #include <machine/bus_pio.h> 115 #include <machine/bus_memio.h> 116 #include <machine/bus.h> 117 #include <machine/resource.h> 118 #include <sys/bus.h> 119 #include <sys/rman.h> 120 121 #include <dev/mii/mii.h> 122 #include <dev/mii/miivar.h> 123 124 #include <pci/pcireg.h> 125 #include <pci/pcivar.h> 126 127 #define DC_USEIOSPACE 128 #ifdef __alpha__ 129 #define SRM_MEDIA 130 #endif 131 132 #include <pci/if_dcreg.h> 133 134 MODULE_DEPEND(dc, miibus, 1, 1, 1); 135 136 /* "controller miibus0" required. See GENERIC if you get errors here. */ 137 #include "miibus_if.h" 138 139 /* 140 * Various supported device vendors/types and their names. 141 */ 142 static struct dc_type dc_devs[] = { 143 { DC_VENDORID_DEC, DC_DEVICEID_21143, 144 "Intel 21143 10/100BaseTX" }, 145 { DC_VENDORID_DAVICOM, DC_DEVICEID_DM9009, 146 "Davicom DM9009 10/100BaseTX" }, 147 { DC_VENDORID_DAVICOM, DC_DEVICEID_DM9100, 148 "Davicom DM9100 10/100BaseTX" }, 149 { DC_VENDORID_DAVICOM, DC_DEVICEID_DM9102, 150 "Davicom DM9102 10/100BaseTX" }, 151 { DC_VENDORID_DAVICOM, DC_DEVICEID_DM9102, 152 "Davicom DM9102A 10/100BaseTX" }, 153 { DC_VENDORID_ADMTEK, DC_DEVICEID_AL981, 154 "ADMtek AL981 10/100BaseTX" }, 155 { DC_VENDORID_ADMTEK, DC_DEVICEID_AN985, 156 "ADMtek AN985 10/100BaseTX" }, 157 { DC_VENDORID_ASIX, DC_DEVICEID_AX88140A, 158 "ASIX AX88140A 10/100BaseTX" }, 159 { DC_VENDORID_ASIX, DC_DEVICEID_AX88140A, 160 "ASIX AX88141 10/100BaseTX" }, 161 { DC_VENDORID_MX, DC_DEVICEID_98713, 162 "Macronix 98713 10/100BaseTX" }, 163 { DC_VENDORID_MX, DC_DEVICEID_98713, 164 "Macronix 98713A 10/100BaseTX" }, 165 { DC_VENDORID_CP, DC_DEVICEID_98713_CP, 166 "Compex RL100-TX 10/100BaseTX" }, 167 { DC_VENDORID_CP, DC_DEVICEID_98713_CP, 168 "Compex RL100-TX 10/100BaseTX" }, 169 { DC_VENDORID_MX, DC_DEVICEID_987x5, 170 "Macronix 98715/98715A 10/100BaseTX" }, 171 { DC_VENDORID_MX, DC_DEVICEID_987x5, 172 "Macronix 98715AEC-C 10/100BaseTX" }, 173 { DC_VENDORID_MX, DC_DEVICEID_987x5, 174 "Macronix 98725 10/100BaseTX" }, 175 { DC_VENDORID_MX, DC_DEVICEID_98727, 176 "Macronix 98727/98732 10/100BaseTX" }, 177 { DC_VENDORID_LO, DC_DEVICEID_82C115, 178 "LC82C115 PNIC II 10/100BaseTX" }, 179 { DC_VENDORID_LO, DC_DEVICEID_82C168, 180 "82c168 PNIC 10/100BaseTX" }, 181 { DC_VENDORID_LO, DC_DEVICEID_82C168, 182 "82c169 PNIC 10/100BaseTX" }, 183 { DC_VENDORID_ACCTON, DC_DEVICEID_EN1217, 184 "Accton EN1217 10/100BaseTX" }, 185 { DC_VENDORID_ACCTON, DC_DEVICEID_EN2242, 186 "Accton EN2242 MiniPCI 10/100BaseTX" }, 187 { DC_VENDORID_XIRCOM, DC_DEVICEID_X3201, 188 "Xircom X3201 10/100BaseTX" }, 189 { DC_VENDORID_ABOCOM, DC_DEVICEID_FE2500, 190 "Abocom FE2500 10/100BaseTX" }, 191 { DC_VENDORID_CONEXANT, DC_DEVICEID_RS7112, 192 "Conexant LANfinity MiniPCI 10/100BaseTX" }, 193 { DC_VENDORID_HAWKING, DC_DEVICEID_HAWKING_PN672TX, 194 "Hawking CB102 CardBus 10/100" }, 195 { 0, 0, NULL } 196 }; 197 198 static int dc_probe (device_t); 199 static int dc_attach (device_t); 200 static int dc_detach (device_t); 201 static int dc_suspend (device_t); 202 static int dc_resume (device_t); 203 static void dc_acpi (device_t); 204 static struct dc_type *dc_devtype (device_t); 205 static int dc_newbuf (struct dc_softc *, int, struct mbuf *); 206 static int dc_encap (struct dc_softc *, struct mbuf *, u_int32_t *); 207 static void dc_pnic_rx_bug_war (struct dc_softc *, int); 208 static int dc_rx_resync (struct dc_softc *); 209 static void dc_rxeof (struct dc_softc *); 210 static void dc_txeof (struct dc_softc *); 211 static void dc_tick (void *); 212 static void dc_tx_underrun (struct dc_softc *); 213 static void dc_intr (void *); 214 static void dc_start (struct ifnet *); 215 static int dc_ioctl (struct ifnet *, u_long, caddr_t); 216 static void dc_init (void *); 217 static void dc_stop (struct dc_softc *); 218 static void dc_watchdog (struct ifnet *); 219 static void dc_shutdown (device_t); 220 static int dc_ifmedia_upd (struct ifnet *); 221 static void dc_ifmedia_sts (struct ifnet *, struct ifmediareq *); 222 223 static void dc_delay (struct dc_softc *); 224 static void dc_eeprom_idle (struct dc_softc *); 225 static void dc_eeprom_putbyte (struct dc_softc *, int); 226 static void dc_eeprom_getword (struct dc_softc *, int, u_int16_t *); 227 static void dc_eeprom_getword_pnic 228 (struct dc_softc *, int, u_int16_t *); 229 static void dc_eeprom_getword_xircom 230 (struct dc_softc *, int, u_int16_t *); 231 static void dc_eeprom_width (struct dc_softc *); 232 static void dc_read_eeprom (struct dc_softc *, caddr_t, int, int, int); 233 234 static void dc_mii_writebit (struct dc_softc *, int); 235 static int dc_mii_readbit (struct dc_softc *); 236 static void dc_mii_sync (struct dc_softc *); 237 static void dc_mii_send (struct dc_softc *, u_int32_t, int); 238 static int dc_mii_readreg (struct dc_softc *, struct dc_mii_frame *); 239 static int dc_mii_writereg (struct dc_softc *, struct dc_mii_frame *); 240 static int dc_miibus_readreg (device_t, int, int); 241 static int dc_miibus_writereg (device_t, int, int, int); 242 static void dc_miibus_statchg (device_t); 243 static void dc_miibus_mediainit (device_t); 244 245 static void dc_setcfg (struct dc_softc *, int); 246 static u_int32_t dc_crc_le (struct dc_softc *, caddr_t); 247 static u_int32_t dc_crc_be (caddr_t); 248 static void dc_setfilt_21143 (struct dc_softc *); 249 static void dc_setfilt_asix (struct dc_softc *); 250 static void dc_setfilt_admtek (struct dc_softc *); 251 static void dc_setfilt_xircom (struct dc_softc *); 252 253 static void dc_setfilt (struct dc_softc *); 254 255 static void dc_reset (struct dc_softc *); 256 static int dc_list_rx_init (struct dc_softc *); 257 static int dc_list_tx_init (struct dc_softc *); 258 259 static void dc_read_srom (struct dc_softc *, int); 260 static void dc_parse_21143_srom (struct dc_softc *); 261 static void dc_decode_leaf_sia (struct dc_softc *, struct dc_eblock_sia *); 262 static void dc_decode_leaf_mii (struct dc_softc *, struct dc_eblock_mii *); 263 static void dc_decode_leaf_sym (struct dc_softc *, struct dc_eblock_sym *); 264 static void dc_apply_fixup (struct dc_softc *, int); 265 266 #ifdef DC_USEIOSPACE 267 #define DC_RES SYS_RES_IOPORT 268 #define DC_RID DC_PCI_CFBIO 269 #else 270 #define DC_RES SYS_RES_MEMORY 271 #define DC_RID DC_PCI_CFBMA 272 #endif 273 274 static device_method_t dc_methods[] = { 275 /* Device interface */ 276 DEVMETHOD(device_probe, dc_probe), 277 DEVMETHOD(device_attach, dc_attach), 278 DEVMETHOD(device_detach, dc_detach), 279 DEVMETHOD(device_suspend, dc_suspend), 280 DEVMETHOD(device_resume, dc_resume), 281 DEVMETHOD(device_shutdown, dc_shutdown), 282 283 /* bus interface */ 284 DEVMETHOD(bus_print_child, bus_generic_print_child), 285 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 286 287 /* MII interface */ 288 DEVMETHOD(miibus_readreg, dc_miibus_readreg), 289 DEVMETHOD(miibus_writereg, dc_miibus_writereg), 290 DEVMETHOD(miibus_statchg, dc_miibus_statchg), 291 DEVMETHOD(miibus_mediainit, dc_miibus_mediainit), 292 293 { 0, 0 } 294 }; 295 296 static driver_t dc_driver = { 297 "dc", 298 dc_methods, 299 sizeof(struct dc_softc) 300 }; 301 302 static devclass_t dc_devclass; 303 #ifdef __i386__ 304 static int dc_quick=1; 305 SYSCTL_INT(_hw, OID_AUTO, dc_quick, CTLFLAG_RW, 306 &dc_quick,0,"do not mdevget in dc driver"); 307 #endif 308 309 DRIVER_MODULE(if_dc, cardbus, dc_driver, dc_devclass, 0, 0); 310 DRIVER_MODULE(if_dc, pci, dc_driver, dc_devclass, 0, 0); 311 DRIVER_MODULE(miibus, dc, miibus_driver, miibus_devclass, 0, 0); 312 313 #define DC_SETBIT(sc, reg, x) \ 314 CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) | (x)) 315 316 #define DC_CLRBIT(sc, reg, x) \ 317 CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) & ~(x)) 318 319 #define SIO_SET(x) DC_SETBIT(sc, DC_SIO, (x)) 320 #define SIO_CLR(x) DC_CLRBIT(sc, DC_SIO, (x)) 321 322 #define IS_MPSAFE 0 323 324 static void 325 dc_delay(sc) 326 struct dc_softc *sc; 327 { 328 int idx; 329 330 for (idx = (300 / 33) + 1; idx > 0; idx--) 331 CSR_READ_4(sc, DC_BUSCTL); 332 } 333 334 static void 335 dc_eeprom_width(sc) 336 struct dc_softc *sc; 337 { 338 int i; 339 340 /* Force EEPROM to idle state. */ 341 dc_eeprom_idle(sc); 342 343 /* Enter EEPROM access mode. */ 344 CSR_WRITE_4(sc, DC_SIO, DC_SIO_EESEL); 345 dc_delay(sc); 346 DC_SETBIT(sc, DC_SIO, DC_SIO_ROMCTL_READ); 347 dc_delay(sc); 348 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); 349 dc_delay(sc); 350 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CS); 351 dc_delay(sc); 352 353 for (i = 3; i--;) { 354 if (6 & (1 << i)) 355 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_DATAIN); 356 else 357 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_DATAIN); 358 dc_delay(sc); 359 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CLK); 360 dc_delay(sc); 361 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); 362 dc_delay(sc); 363 } 364 365 for (i = 1; i <= 12; i++) { 366 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CLK); 367 dc_delay(sc); 368 if (!(CSR_READ_4(sc, DC_SIO) & DC_SIO_EE_DATAOUT)) { 369 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); 370 dc_delay(sc); 371 break; 372 } 373 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); 374 dc_delay(sc); 375 } 376 377 /* Turn off EEPROM access mode. */ 378 dc_eeprom_idle(sc); 379 380 if (i < 4 || i > 12) 381 sc->dc_romwidth = 6; 382 else 383 sc->dc_romwidth = i; 384 385 /* Enter EEPROM access mode. */ 386 CSR_WRITE_4(sc, DC_SIO, DC_SIO_EESEL); 387 dc_delay(sc); 388 DC_SETBIT(sc, DC_SIO, DC_SIO_ROMCTL_READ); 389 dc_delay(sc); 390 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); 391 dc_delay(sc); 392 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CS); 393 dc_delay(sc); 394 395 /* Turn off EEPROM access mode. */ 396 dc_eeprom_idle(sc); 397 } 398 399 static void 400 dc_eeprom_idle(sc) 401 struct dc_softc *sc; 402 { 403 register int i; 404 405 CSR_WRITE_4(sc, DC_SIO, DC_SIO_EESEL); 406 dc_delay(sc); 407 DC_SETBIT(sc, DC_SIO, DC_SIO_ROMCTL_READ); 408 dc_delay(sc); 409 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); 410 dc_delay(sc); 411 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CS); 412 dc_delay(sc); 413 414 for (i = 0; i < 25; i++) { 415 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); 416 dc_delay(sc); 417 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CLK); 418 dc_delay(sc); 419 } 420 421 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); 422 dc_delay(sc); 423 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CS); 424 dc_delay(sc); 425 CSR_WRITE_4(sc, DC_SIO, 0x00000000); 426 427 return; 428 } 429 430 /* 431 * Send a read command and address to the EEPROM, check for ACK. 432 */ 433 static void 434 dc_eeprom_putbyte(sc, addr) 435 struct dc_softc *sc; 436 int addr; 437 { 438 register int d, i; 439 440 d = DC_EECMD_READ >> 6; 441 for (i = 3; i--; ) { 442 if (d & (1 << i)) 443 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_DATAIN); 444 else 445 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_DATAIN); 446 dc_delay(sc); 447 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CLK); 448 dc_delay(sc); 449 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); 450 dc_delay(sc); 451 } 452 453 /* 454 * Feed in each bit and strobe the clock. 455 */ 456 for (i = sc->dc_romwidth; i--;) { 457 if (addr & (1 << i)) { 458 SIO_SET(DC_SIO_EE_DATAIN); 459 } else { 460 SIO_CLR(DC_SIO_EE_DATAIN); 461 } 462 dc_delay(sc); 463 SIO_SET(DC_SIO_EE_CLK); 464 dc_delay(sc); 465 SIO_CLR(DC_SIO_EE_CLK); 466 dc_delay(sc); 467 } 468 469 return; 470 } 471 472 /* 473 * Read a word of data stored in the EEPROM at address 'addr.' 474 * The PNIC 82c168/82c169 has its own non-standard way to read 475 * the EEPROM. 476 */ 477 static void 478 dc_eeprom_getword_pnic(sc, addr, dest) 479 struct dc_softc *sc; 480 int addr; 481 u_int16_t *dest; 482 { 483 register int i; 484 u_int32_t r; 485 486 CSR_WRITE_4(sc, DC_PN_SIOCTL, DC_PN_EEOPCODE_READ|addr); 487 488 for (i = 0; i < DC_TIMEOUT; i++) { 489 DELAY(1); 490 r = CSR_READ_4(sc, DC_SIO); 491 if (!(r & DC_PN_SIOCTL_BUSY)) { 492 *dest = (u_int16_t)(r & 0xFFFF); 493 return; 494 } 495 } 496 497 return; 498 } 499 500 /* 501 * Read a word of data stored in the EEPROM at address 'addr.' 502 * The Xircom X3201 has its own non-standard way to read 503 * the EEPROM, too. 504 */ 505 static void 506 dc_eeprom_getword_xircom(sc, addr, dest) 507 struct dc_softc *sc; 508 int addr; 509 u_int16_t *dest; 510 { 511 SIO_SET(DC_SIO_ROMSEL | DC_SIO_ROMCTL_READ); 512 513 addr *= 2; 514 CSR_WRITE_4(sc, DC_ROM, addr | 0x160); 515 *dest = (u_int16_t)CSR_READ_4(sc, DC_SIO)&0xff; 516 addr += 1; 517 CSR_WRITE_4(sc, DC_ROM, addr | 0x160); 518 *dest |= ((u_int16_t)CSR_READ_4(sc, DC_SIO)&0xff) << 8; 519 520 SIO_CLR(DC_SIO_ROMSEL | DC_SIO_ROMCTL_READ); 521 return; 522 } 523 524 /* 525 * Read a word of data stored in the EEPROM at address 'addr.' 526 */ 527 static void 528 dc_eeprom_getword(sc, addr, dest) 529 struct dc_softc *sc; 530 int addr; 531 u_int16_t *dest; 532 { 533 register int i; 534 u_int16_t word = 0; 535 536 /* Force EEPROM to idle state. */ 537 dc_eeprom_idle(sc); 538 539 /* Enter EEPROM access mode. */ 540 CSR_WRITE_4(sc, DC_SIO, DC_SIO_EESEL); 541 dc_delay(sc); 542 DC_SETBIT(sc, DC_SIO, DC_SIO_ROMCTL_READ); 543 dc_delay(sc); 544 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); 545 dc_delay(sc); 546 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CS); 547 dc_delay(sc); 548 549 /* 550 * Send address of word we want to read. 551 */ 552 dc_eeprom_putbyte(sc, addr); 553 554 /* 555 * Start reading bits from EEPROM. 556 */ 557 for (i = 0x8000; i; i >>= 1) { 558 SIO_SET(DC_SIO_EE_CLK); 559 dc_delay(sc); 560 if (CSR_READ_4(sc, DC_SIO) & DC_SIO_EE_DATAOUT) 561 word |= i; 562 dc_delay(sc); 563 SIO_CLR(DC_SIO_EE_CLK); 564 dc_delay(sc); 565 } 566 567 /* Turn off EEPROM access mode. */ 568 dc_eeprom_idle(sc); 569 570 *dest = word; 571 572 return; 573 } 574 575 /* 576 * Read a sequence of words from the EEPROM. 577 */ 578 static void 579 dc_read_eeprom(sc, dest, off, cnt, swap) 580 struct dc_softc *sc; 581 caddr_t dest; 582 int off; 583 int cnt; 584 int swap; 585 { 586 int i; 587 u_int16_t word = 0, *ptr; 588 589 for (i = 0; i < cnt; i++) { 590 if (DC_IS_PNIC(sc)) 591 dc_eeprom_getword_pnic(sc, off + i, &word); 592 else if (DC_IS_XIRCOM(sc)) 593 dc_eeprom_getword_xircom(sc, off + i, &word); 594 else 595 dc_eeprom_getword(sc, off + i, &word); 596 ptr = (u_int16_t *)(dest + (i * 2)); 597 if (swap) 598 *ptr = ntohs(word); 599 else 600 *ptr = word; 601 } 602 603 return; 604 } 605 606 /* 607 * The following two routines are taken from the Macronix 98713 608 * Application Notes pp.19-21. 609 */ 610 /* 611 * Write a bit to the MII bus. 612 */ 613 static void 614 dc_mii_writebit(sc, bit) 615 struct dc_softc *sc; 616 int bit; 617 { 618 if (bit) 619 CSR_WRITE_4(sc, DC_SIO, 620 DC_SIO_ROMCTL_WRITE|DC_SIO_MII_DATAOUT); 621 else 622 CSR_WRITE_4(sc, DC_SIO, DC_SIO_ROMCTL_WRITE); 623 624 DC_SETBIT(sc, DC_SIO, DC_SIO_MII_CLK); 625 DC_CLRBIT(sc, DC_SIO, DC_SIO_MII_CLK); 626 627 return; 628 } 629 630 /* 631 * Read a bit from the MII bus. 632 */ 633 static int 634 dc_mii_readbit(sc) 635 struct dc_softc *sc; 636 { 637 CSR_WRITE_4(sc, DC_SIO, DC_SIO_ROMCTL_READ|DC_SIO_MII_DIR); 638 CSR_READ_4(sc, DC_SIO); 639 DC_SETBIT(sc, DC_SIO, DC_SIO_MII_CLK); 640 DC_CLRBIT(sc, DC_SIO, DC_SIO_MII_CLK); 641 if (CSR_READ_4(sc, DC_SIO) & DC_SIO_MII_DATAIN) 642 return(1); 643 644 return(0); 645 } 646 647 /* 648 * Sync the PHYs by setting data bit and strobing the clock 32 times. 649 */ 650 static void 651 dc_mii_sync(sc) 652 struct dc_softc *sc; 653 { 654 register int i; 655 656 CSR_WRITE_4(sc, DC_SIO, DC_SIO_ROMCTL_WRITE); 657 658 for (i = 0; i < 32; i++) 659 dc_mii_writebit(sc, 1); 660 661 return; 662 } 663 664 /* 665 * Clock a series of bits through the MII. 666 */ 667 static void 668 dc_mii_send(sc, bits, cnt) 669 struct dc_softc *sc; 670 u_int32_t bits; 671 int cnt; 672 { 673 int i; 674 675 for (i = (0x1 << (cnt - 1)); i; i >>= 1) 676 dc_mii_writebit(sc, bits & i); 677 } 678 679 /* 680 * Read an PHY register through the MII. 681 */ 682 static int 683 dc_mii_readreg(sc, frame) 684 struct dc_softc *sc; 685 struct dc_mii_frame *frame; 686 687 { 688 int i, ack; 689 690 DC_LOCK(sc); 691 692 /* 693 * Set up frame for RX. 694 */ 695 frame->mii_stdelim = DC_MII_STARTDELIM; 696 frame->mii_opcode = DC_MII_READOP; 697 frame->mii_turnaround = 0; 698 frame->mii_data = 0; 699 700 /* 701 * Sync the PHYs. 702 */ 703 dc_mii_sync(sc); 704 705 /* 706 * Send command/address info. 707 */ 708 dc_mii_send(sc, frame->mii_stdelim, 2); 709 dc_mii_send(sc, frame->mii_opcode, 2); 710 dc_mii_send(sc, frame->mii_phyaddr, 5); 711 dc_mii_send(sc, frame->mii_regaddr, 5); 712 713 #ifdef notdef 714 /* Idle bit */ 715 dc_mii_writebit(sc, 1); 716 dc_mii_writebit(sc, 0); 717 #endif 718 719 /* Check for ack */ 720 ack = dc_mii_readbit(sc); 721 722 /* 723 * Now try reading data bits. If the ack failed, we still 724 * need to clock through 16 cycles to keep the PHY(s) in sync. 725 */ 726 if (ack) { 727 for(i = 0; i < 16; i++) { 728 dc_mii_readbit(sc); 729 } 730 goto fail; 731 } 732 733 for (i = 0x8000; i; i >>= 1) { 734 if (!ack) { 735 if (dc_mii_readbit(sc)) 736 frame->mii_data |= i; 737 } 738 } 739 740 fail: 741 742 dc_mii_writebit(sc, 0); 743 dc_mii_writebit(sc, 0); 744 745 DC_UNLOCK(sc); 746 747 if (ack) 748 return(1); 749 return(0); 750 } 751 752 /* 753 * Write to a PHY register through the MII. 754 */ 755 static int 756 dc_mii_writereg(sc, frame) 757 struct dc_softc *sc; 758 struct dc_mii_frame *frame; 759 760 { 761 DC_LOCK(sc); 762 /* 763 * Set up frame for TX. 764 */ 765 766 frame->mii_stdelim = DC_MII_STARTDELIM; 767 frame->mii_opcode = DC_MII_WRITEOP; 768 frame->mii_turnaround = DC_MII_TURNAROUND; 769 770 /* 771 * Sync the PHYs. 772 */ 773 dc_mii_sync(sc); 774 775 dc_mii_send(sc, frame->mii_stdelim, 2); 776 dc_mii_send(sc, frame->mii_opcode, 2); 777 dc_mii_send(sc, frame->mii_phyaddr, 5); 778 dc_mii_send(sc, frame->mii_regaddr, 5); 779 dc_mii_send(sc, frame->mii_turnaround, 2); 780 dc_mii_send(sc, frame->mii_data, 16); 781 782 /* Idle bit. */ 783 dc_mii_writebit(sc, 0); 784 dc_mii_writebit(sc, 0); 785 786 DC_UNLOCK(sc); 787 788 return(0); 789 } 790 791 static int 792 dc_miibus_readreg(dev, phy, reg) 793 device_t dev; 794 int phy, reg; 795 { 796 struct dc_mii_frame frame; 797 struct dc_softc *sc; 798 int i, rval, phy_reg = 0; 799 800 sc = device_get_softc(dev); 801 bzero((char *)&frame, sizeof(frame)); 802 803 /* 804 * Note: both the AL981 and AN985 have internal PHYs, 805 * however the AL981 provides direct access to the PHY 806 * registers while the AN985 uses a serial MII interface. 807 * The AN985's MII interface is also buggy in that you 808 * can read from any MII address (0 to 31), but only address 1 809 * behaves normally. To deal with both cases, we pretend 810 * that the PHY is at MII address 1. 811 */ 812 if (DC_IS_ADMTEK(sc) && phy != DC_ADMTEK_PHYADDR) 813 return(0); 814 815 /* 816 * Note: the ukphy probes of the RS7112 report a PHY at 817 * MII address 0 (possibly HomePNA?) and 1 (ethernet) 818 * so we only respond to correct one. 819 */ 820 if (DC_IS_CONEXANT(sc) && phy != DC_CONEXANT_PHYADDR) 821 return(0); 822 823 if (sc->dc_pmode != DC_PMODE_MII) { 824 if (phy == (MII_NPHY - 1)) { 825 switch(reg) { 826 case MII_BMSR: 827 /* 828 * Fake something to make the probe 829 * code think there's a PHY here. 830 */ 831 return(BMSR_MEDIAMASK); 832 break; 833 case MII_PHYIDR1: 834 if (DC_IS_PNIC(sc)) 835 return(DC_VENDORID_LO); 836 return(DC_VENDORID_DEC); 837 break; 838 case MII_PHYIDR2: 839 if (DC_IS_PNIC(sc)) 840 return(DC_DEVICEID_82C168); 841 return(DC_DEVICEID_21143); 842 break; 843 default: 844 return(0); 845 break; 846 } 847 } else 848 return(0); 849 } 850 851 if (DC_IS_PNIC(sc)) { 852 CSR_WRITE_4(sc, DC_PN_MII, DC_PN_MIIOPCODE_READ | 853 (phy << 23) | (reg << 18)); 854 for (i = 0; i < DC_TIMEOUT; i++) { 855 DELAY(1); 856 rval = CSR_READ_4(sc, DC_PN_MII); 857 if (!(rval & DC_PN_MII_BUSY)) { 858 rval &= 0xFFFF; 859 return(rval == 0xFFFF ? 0 : rval); 860 } 861 } 862 return(0); 863 } 864 865 if (DC_IS_COMET(sc)) { 866 switch(reg) { 867 case MII_BMCR: 868 phy_reg = DC_AL_BMCR; 869 break; 870 case MII_BMSR: 871 phy_reg = DC_AL_BMSR; 872 break; 873 case MII_PHYIDR1: 874 phy_reg = DC_AL_VENID; 875 break; 876 case MII_PHYIDR2: 877 phy_reg = DC_AL_DEVID; 878 break; 879 case MII_ANAR: 880 phy_reg = DC_AL_ANAR; 881 break; 882 case MII_ANLPAR: 883 phy_reg = DC_AL_LPAR; 884 break; 885 case MII_ANER: 886 phy_reg = DC_AL_ANER; 887 break; 888 default: 889 printf("dc%d: phy_read: bad phy register %x\n", 890 sc->dc_unit, reg); 891 return(0); 892 break; 893 } 894 895 rval = CSR_READ_4(sc, phy_reg) & 0x0000FFFF; 896 897 if (rval == 0xFFFF) 898 return(0); 899 return(rval); 900 } 901 902 frame.mii_phyaddr = phy; 903 frame.mii_regaddr = reg; 904 if (sc->dc_type == DC_TYPE_98713) { 905 phy_reg = CSR_READ_4(sc, DC_NETCFG); 906 CSR_WRITE_4(sc, DC_NETCFG, phy_reg & ~DC_NETCFG_PORTSEL); 907 } 908 dc_mii_readreg(sc, &frame); 909 if (sc->dc_type == DC_TYPE_98713) 910 CSR_WRITE_4(sc, DC_NETCFG, phy_reg); 911 912 return(frame.mii_data); 913 } 914 915 static int 916 dc_miibus_writereg(dev, phy, reg, data) 917 device_t dev; 918 int phy, reg, data; 919 { 920 struct dc_softc *sc; 921 struct dc_mii_frame frame; 922 int i, phy_reg = 0; 923 924 sc = device_get_softc(dev); 925 bzero((char *)&frame, sizeof(frame)); 926 927 if (DC_IS_ADMTEK(sc) && phy != DC_ADMTEK_PHYADDR) 928 return(0); 929 930 if (DC_IS_CONEXANT(sc) && phy != DC_CONEXANT_PHYADDR) 931 return(0); 932 933 if (DC_IS_PNIC(sc)) { 934 CSR_WRITE_4(sc, DC_PN_MII, DC_PN_MIIOPCODE_WRITE | 935 (phy << 23) | (reg << 10) | data); 936 for (i = 0; i < DC_TIMEOUT; i++) { 937 if (!(CSR_READ_4(sc, DC_PN_MII) & DC_PN_MII_BUSY)) 938 break; 939 } 940 return(0); 941 } 942 943 if (DC_IS_COMET(sc)) { 944 switch(reg) { 945 case MII_BMCR: 946 phy_reg = DC_AL_BMCR; 947 break; 948 case MII_BMSR: 949 phy_reg = DC_AL_BMSR; 950 break; 951 case MII_PHYIDR1: 952 phy_reg = DC_AL_VENID; 953 break; 954 case MII_PHYIDR2: 955 phy_reg = DC_AL_DEVID; 956 break; 957 case MII_ANAR: 958 phy_reg = DC_AL_ANAR; 959 break; 960 case MII_ANLPAR: 961 phy_reg = DC_AL_LPAR; 962 break; 963 case MII_ANER: 964 phy_reg = DC_AL_ANER; 965 break; 966 default: 967 printf("dc%d: phy_write: bad phy register %x\n", 968 sc->dc_unit, reg); 969 return(0); 970 break; 971 } 972 973 CSR_WRITE_4(sc, phy_reg, data); 974 return(0); 975 } 976 977 frame.mii_phyaddr = phy; 978 frame.mii_regaddr = reg; 979 frame.mii_data = data; 980 981 if (sc->dc_type == DC_TYPE_98713) { 982 phy_reg = CSR_READ_4(sc, DC_NETCFG); 983 CSR_WRITE_4(sc, DC_NETCFG, phy_reg & ~DC_NETCFG_PORTSEL); 984 } 985 dc_mii_writereg(sc, &frame); 986 if (sc->dc_type == DC_TYPE_98713) 987 CSR_WRITE_4(sc, DC_NETCFG, phy_reg); 988 989 return(0); 990 } 991 992 static void 993 dc_miibus_statchg(dev) 994 device_t dev; 995 { 996 struct dc_softc *sc; 997 struct mii_data *mii; 998 struct ifmedia *ifm; 999 1000 sc = device_get_softc(dev); 1001 if (DC_IS_ADMTEK(sc)) 1002 return; 1003 1004 mii = device_get_softc(sc->dc_miibus); 1005 ifm = &mii->mii_media; 1006 if (DC_IS_DAVICOM(sc) && 1007 IFM_SUBTYPE(ifm->ifm_media) == IFM_HPNA_1) { 1008 dc_setcfg(sc, ifm->ifm_media); 1009 sc->dc_if_media = ifm->ifm_media; 1010 } else { 1011 dc_setcfg(sc, mii->mii_media_active); 1012 sc->dc_if_media = mii->mii_media_active; 1013 } 1014 1015 return; 1016 } 1017 1018 /* 1019 * Special support for DM9102A cards with HomePNA PHYs. Note: 1020 * with the Davicom DM9102A/DM9801 eval board that I have, it seems 1021 * to be impossible to talk to the management interface of the DM9801 1022 * PHY (its MDIO pin is not connected to anything). Consequently, 1023 * the driver has to just 'know' about the additional mode and deal 1024 * with it itself. *sigh* 1025 */ 1026 static void 1027 dc_miibus_mediainit(dev) 1028 device_t dev; 1029 { 1030 struct dc_softc *sc; 1031 struct mii_data *mii; 1032 struct ifmedia *ifm; 1033 int rev; 1034 1035 rev = pci_read_config(dev, DC_PCI_CFRV, 4) & 0xFF; 1036 1037 sc = device_get_softc(dev); 1038 mii = device_get_softc(sc->dc_miibus); 1039 ifm = &mii->mii_media; 1040 1041 if (DC_IS_DAVICOM(sc) && rev >= DC_REVISION_DM9102A) 1042 ifmedia_add(ifm, IFM_ETHER|IFM_HPNA_1, 0, NULL); 1043 1044 return; 1045 } 1046 1047 #define DC_POLY 0xEDB88320 1048 #define DC_BITS_512 9 1049 #define DC_BITS_128 7 1050 #define DC_BITS_64 6 1051 1052 static u_int32_t 1053 dc_crc_le(sc, addr) 1054 struct dc_softc *sc; 1055 caddr_t addr; 1056 { 1057 u_int32_t idx, bit, data, crc; 1058 1059 /* Compute CRC for the address value. */ 1060 crc = 0xFFFFFFFF; /* initial value */ 1061 1062 for (idx = 0; idx < 6; idx++) { 1063 for (data = *addr++, bit = 0; bit < 8; bit++, data >>= 1) 1064 crc = (crc >> 1) ^ (((crc ^ data) & 1) ? DC_POLY : 0); 1065 } 1066 1067 /* 1068 * The hash table on the PNIC II and the MX98715AEC-C/D/E 1069 * chips is only 128 bits wide. 1070 */ 1071 if (sc->dc_flags & DC_128BIT_HASH) 1072 return (crc & ((1 << DC_BITS_128) - 1)); 1073 1074 /* The hash table on the MX98715BEC is only 64 bits wide. */ 1075 if (sc->dc_flags & DC_64BIT_HASH) 1076 return (crc & ((1 << DC_BITS_64) - 1)); 1077 1078 /* Xircom's hash filtering table is different (read: weird) */ 1079 /* Xircom uses the LEAST significant bits */ 1080 if (DC_IS_XIRCOM(sc)) { 1081 if ((crc & 0x180) == 0x180) 1082 return (crc & 0x0F) + (crc & 0x70)*3 + (14 << 4); 1083 else 1084 return (crc & 0x1F) + ((crc>>1) & 0xF0)*3 + (12 << 4); 1085 } 1086 1087 return (crc & ((1 << DC_BITS_512) - 1)); 1088 } 1089 1090 /* 1091 * Calculate CRC of a multicast group address, return the lower 6 bits. 1092 */ 1093 static u_int32_t 1094 dc_crc_be(addr) 1095 caddr_t addr; 1096 { 1097 u_int32_t crc, carry; 1098 int i, j; 1099 u_int8_t c; 1100 1101 /* Compute CRC for the address value. */ 1102 crc = 0xFFFFFFFF; /* initial value */ 1103 1104 for (i = 0; i < 6; i++) { 1105 c = *(addr + i); 1106 for (j = 0; j < 8; j++) { 1107 carry = ((crc & 0x80000000) ? 1 : 0) ^ (c & 0x01); 1108 crc <<= 1; 1109 c >>= 1; 1110 if (carry) 1111 crc = (crc ^ 0x04c11db6) | carry; 1112 } 1113 } 1114 1115 /* return the filter bit position */ 1116 return((crc >> 26) & 0x0000003F); 1117 } 1118 1119 /* 1120 * 21143-style RX filter setup routine. Filter programming is done by 1121 * downloading a special setup frame into the TX engine. 21143, Macronix, 1122 * PNIC, PNIC II and Davicom chips are programmed this way. 1123 * 1124 * We always program the chip using 'hash perfect' mode, i.e. one perfect 1125 * address (our node address) and a 512-bit hash filter for multicast 1126 * frames. We also sneak the broadcast address into the hash filter since 1127 * we need that too. 1128 */ 1129 static void 1130 dc_setfilt_21143(sc) 1131 struct dc_softc *sc; 1132 { 1133 struct dc_desc *sframe; 1134 u_int32_t h, *sp; 1135 struct ifmultiaddr *ifma; 1136 struct ifnet *ifp; 1137 int i; 1138 1139 ifp = &sc->arpcom.ac_if; 1140 1141 i = sc->dc_cdata.dc_tx_prod; 1142 DC_INC(sc->dc_cdata.dc_tx_prod, DC_TX_LIST_CNT); 1143 sc->dc_cdata.dc_tx_cnt++; 1144 sframe = &sc->dc_ldata->dc_tx_list[i]; 1145 sp = (u_int32_t *)&sc->dc_cdata.dc_sbuf; 1146 bzero((char *)sp, DC_SFRAME_LEN); 1147 1148 sframe->dc_data = vtophys(&sc->dc_cdata.dc_sbuf); 1149 sframe->dc_ctl = DC_SFRAME_LEN | DC_TXCTL_SETUP | DC_TXCTL_TLINK | 1150 DC_FILTER_HASHPERF | DC_TXCTL_FINT; 1151 1152 sc->dc_cdata.dc_tx_chain[i] = (struct mbuf *)&sc->dc_cdata.dc_sbuf; 1153 1154 /* If we want promiscuous mode, set the allframes bit. */ 1155 if (ifp->if_flags & IFF_PROMISC) 1156 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC); 1157 else 1158 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC); 1159 1160 if (ifp->if_flags & IFF_ALLMULTI) 1161 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI); 1162 else 1163 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI); 1164 1165 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 1166 if (ifma->ifma_addr->sa_family != AF_LINK) 1167 continue; 1168 h = dc_crc_le(sc, 1169 LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 1170 sp[h >> 4] |= 1 << (h & 0xF); 1171 } 1172 1173 if (ifp->if_flags & IFF_BROADCAST) { 1174 h = dc_crc_le(sc, (caddr_t)ifp->if_broadcastaddr); 1175 sp[h >> 4] |= 1 << (h & 0xF); 1176 } 1177 1178 /* Set our MAC address */ 1179 sp[39] = ((u_int16_t *)sc->arpcom.ac_enaddr)[0]; 1180 sp[40] = ((u_int16_t *)sc->arpcom.ac_enaddr)[1]; 1181 sp[41] = ((u_int16_t *)sc->arpcom.ac_enaddr)[2]; 1182 1183 sframe->dc_status = DC_TXSTAT_OWN; 1184 CSR_WRITE_4(sc, DC_TXSTART, 0xFFFFFFFF); 1185 1186 /* 1187 * The PNIC takes an exceedingly long time to process its 1188 * setup frame; wait 10ms after posting the setup frame 1189 * before proceeding, just so it has time to swallow its 1190 * medicine. 1191 */ 1192 DELAY(10000); 1193 1194 ifp->if_timer = 5; 1195 1196 return; 1197 } 1198 1199 static void 1200 dc_setfilt_admtek(sc) 1201 struct dc_softc *sc; 1202 { 1203 struct ifnet *ifp; 1204 int h = 0; 1205 u_int32_t hashes[2] = { 0, 0 }; 1206 struct ifmultiaddr *ifma; 1207 1208 ifp = &sc->arpcom.ac_if; 1209 1210 /* Init our MAC address */ 1211 CSR_WRITE_4(sc, DC_AL_PAR0, *(u_int32_t *)(&sc->arpcom.ac_enaddr[0])); 1212 CSR_WRITE_4(sc, DC_AL_PAR1, *(u_int32_t *)(&sc->arpcom.ac_enaddr[4])); 1213 1214 /* If we want promiscuous mode, set the allframes bit. */ 1215 if (ifp->if_flags & IFF_PROMISC) 1216 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC); 1217 else 1218 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC); 1219 1220 if (ifp->if_flags & IFF_ALLMULTI) 1221 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI); 1222 else 1223 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI); 1224 1225 /* first, zot all the existing hash bits */ 1226 CSR_WRITE_4(sc, DC_AL_MAR0, 0); 1227 CSR_WRITE_4(sc, DC_AL_MAR1, 0); 1228 1229 /* 1230 * If we're already in promisc or allmulti mode, we 1231 * don't have to bother programming the multicast filter. 1232 */ 1233 if (ifp->if_flags & (IFF_PROMISC|IFF_ALLMULTI)) 1234 return; 1235 1236 /* now program new ones */ 1237 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 1238 if (ifma->ifma_addr->sa_family != AF_LINK) 1239 continue; 1240 h = dc_crc_be(LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 1241 if (h < 32) 1242 hashes[0] |= (1 << h); 1243 else 1244 hashes[1] |= (1 << (h - 32)); 1245 } 1246 1247 CSR_WRITE_4(sc, DC_AL_MAR0, hashes[0]); 1248 CSR_WRITE_4(sc, DC_AL_MAR1, hashes[1]); 1249 1250 return; 1251 } 1252 1253 static void 1254 dc_setfilt_asix(sc) 1255 struct dc_softc *sc; 1256 { 1257 struct ifnet *ifp; 1258 int h = 0; 1259 u_int32_t hashes[2] = { 0, 0 }; 1260 struct ifmultiaddr *ifma; 1261 1262 ifp = &sc->arpcom.ac_if; 1263 1264 /* Init our MAC address */ 1265 CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_PAR0); 1266 CSR_WRITE_4(sc, DC_AX_FILTDATA, 1267 *(u_int32_t *)(&sc->arpcom.ac_enaddr[0])); 1268 CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_PAR1); 1269 CSR_WRITE_4(sc, DC_AX_FILTDATA, 1270 *(u_int32_t *)(&sc->arpcom.ac_enaddr[4])); 1271 1272 /* If we want promiscuous mode, set the allframes bit. */ 1273 if (ifp->if_flags & IFF_PROMISC) 1274 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC); 1275 else 1276 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC); 1277 1278 if (ifp->if_flags & IFF_ALLMULTI) 1279 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI); 1280 else 1281 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI); 1282 1283 /* 1284 * The ASIX chip has a special bit to enable reception 1285 * of broadcast frames. 1286 */ 1287 if (ifp->if_flags & IFF_BROADCAST) 1288 DC_SETBIT(sc, DC_NETCFG, DC_AX_NETCFG_RX_BROAD); 1289 else 1290 DC_CLRBIT(sc, DC_NETCFG, DC_AX_NETCFG_RX_BROAD); 1291 1292 /* first, zot all the existing hash bits */ 1293 CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_MAR0); 1294 CSR_WRITE_4(sc, DC_AX_FILTDATA, 0); 1295 CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_MAR1); 1296 CSR_WRITE_4(sc, DC_AX_FILTDATA, 0); 1297 1298 /* 1299 * If we're already in promisc or allmulti mode, we 1300 * don't have to bother programming the multicast filter. 1301 */ 1302 if (ifp->if_flags & (IFF_PROMISC|IFF_ALLMULTI)) 1303 return; 1304 1305 /* now program new ones */ 1306 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 1307 if (ifma->ifma_addr->sa_family != AF_LINK) 1308 continue; 1309 h = dc_crc_be(LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 1310 if (h < 32) 1311 hashes[0] |= (1 << h); 1312 else 1313 hashes[1] |= (1 << (h - 32)); 1314 } 1315 1316 CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_MAR0); 1317 CSR_WRITE_4(sc, DC_AX_FILTDATA, hashes[0]); 1318 CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_MAR1); 1319 CSR_WRITE_4(sc, DC_AX_FILTDATA, hashes[1]); 1320 1321 return; 1322 } 1323 1324 static void 1325 dc_setfilt_xircom(sc) 1326 struct dc_softc *sc; 1327 { 1328 struct dc_desc *sframe; 1329 u_int32_t h, *sp; 1330 struct ifmultiaddr *ifma; 1331 struct ifnet *ifp; 1332 int i; 1333 1334 ifp = &sc->arpcom.ac_if; 1335 DC_CLRBIT(sc, DC_NETCFG, (DC_NETCFG_TX_ON|DC_NETCFG_RX_ON)); 1336 1337 i = sc->dc_cdata.dc_tx_prod; 1338 DC_INC(sc->dc_cdata.dc_tx_prod, DC_TX_LIST_CNT); 1339 sc->dc_cdata.dc_tx_cnt++; 1340 sframe = &sc->dc_ldata->dc_tx_list[i]; 1341 sp = (u_int32_t *)&sc->dc_cdata.dc_sbuf; 1342 bzero((char *)sp, DC_SFRAME_LEN); 1343 1344 sframe->dc_data = vtophys(&sc->dc_cdata.dc_sbuf); 1345 sframe->dc_ctl = DC_SFRAME_LEN | DC_TXCTL_SETUP | DC_TXCTL_TLINK | 1346 DC_FILTER_HASHPERF | DC_TXCTL_FINT; 1347 1348 sc->dc_cdata.dc_tx_chain[i] = (struct mbuf *)&sc->dc_cdata.dc_sbuf; 1349 1350 /* If we want promiscuous mode, set the allframes bit. */ 1351 if (ifp->if_flags & IFF_PROMISC) 1352 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC); 1353 else 1354 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC); 1355 1356 if (ifp->if_flags & IFF_ALLMULTI) 1357 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI); 1358 else 1359 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI); 1360 1361 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 1362 if (ifma->ifma_addr->sa_family != AF_LINK) 1363 continue; 1364 h = dc_crc_le(sc, 1365 LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 1366 sp[h >> 4] |= 1 << (h & 0xF); 1367 } 1368 1369 if (ifp->if_flags & IFF_BROADCAST) { 1370 h = dc_crc_le(sc, (caddr_t)ifp->if_broadcastaddr); 1371 sp[h >> 4] |= 1 << (h & 0xF); 1372 } 1373 1374 /* Set our MAC address */ 1375 sp[0] = ((u_int16_t *)sc->arpcom.ac_enaddr)[0]; 1376 sp[1] = ((u_int16_t *)sc->arpcom.ac_enaddr)[1]; 1377 sp[2] = ((u_int16_t *)sc->arpcom.ac_enaddr)[2]; 1378 1379 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_TX_ON); 1380 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_ON); 1381 ifp->if_flags |= IFF_RUNNING; 1382 sframe->dc_status = DC_TXSTAT_OWN; 1383 CSR_WRITE_4(sc, DC_TXSTART, 0xFFFFFFFF); 1384 1385 /* 1386 * wait some time... 1387 */ 1388 DELAY(1000); 1389 1390 ifp->if_timer = 5; 1391 1392 return; 1393 } 1394 1395 static void 1396 dc_setfilt(sc) 1397 struct dc_softc *sc; 1398 { 1399 if (DC_IS_INTEL(sc) || DC_IS_MACRONIX(sc) || DC_IS_PNIC(sc) || 1400 DC_IS_PNICII(sc) || DC_IS_DAVICOM(sc) || DC_IS_CONEXANT(sc)) 1401 dc_setfilt_21143(sc); 1402 1403 if (DC_IS_ASIX(sc)) 1404 dc_setfilt_asix(sc); 1405 1406 if (DC_IS_ADMTEK(sc)) 1407 dc_setfilt_admtek(sc); 1408 1409 if (DC_IS_XIRCOM(sc)) 1410 dc_setfilt_xircom(sc); 1411 1412 return; 1413 } 1414 1415 /* 1416 * In order to fiddle with the 1417 * 'full-duplex' and '100Mbps' bits in the netconfig register, we 1418 * first have to put the transmit and/or receive logic in the idle state. 1419 */ 1420 static void 1421 dc_setcfg(sc, media) 1422 struct dc_softc *sc; 1423 int media; 1424 { 1425 int i, restart = 0; 1426 u_int32_t isr; 1427 1428 if (IFM_SUBTYPE(media) == IFM_NONE) 1429 return; 1430 1431 if (CSR_READ_4(sc, DC_NETCFG) & (DC_NETCFG_TX_ON|DC_NETCFG_RX_ON)) { 1432 restart = 1; 1433 DC_CLRBIT(sc, DC_NETCFG, (DC_NETCFG_TX_ON|DC_NETCFG_RX_ON)); 1434 1435 for (i = 0; i < DC_TIMEOUT; i++) { 1436 isr = CSR_READ_4(sc, DC_ISR); 1437 if (isr & DC_ISR_TX_IDLE && 1438 ((isr & DC_ISR_RX_STATE) == DC_RXSTATE_STOPPED || 1439 (isr & DC_ISR_RX_STATE) == DC_RXSTATE_WAIT)) 1440 break; 1441 DELAY(10); 1442 } 1443 1444 if (i == DC_TIMEOUT) 1445 printf("dc%d: failed to force tx and " 1446 "rx to idle state\n", sc->dc_unit); 1447 } 1448 1449 if (IFM_SUBTYPE(media) == IFM_100_TX) { 1450 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_SPEEDSEL); 1451 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_HEARTBEAT); 1452 if (sc->dc_pmode == DC_PMODE_MII) { 1453 int watchdogreg; 1454 1455 if (DC_IS_INTEL(sc)) { 1456 /* there's a write enable bit here that reads as 1 */ 1457 watchdogreg = CSR_READ_4(sc, DC_WATCHDOG); 1458 watchdogreg &= ~DC_WDOG_CTLWREN; 1459 watchdogreg |= DC_WDOG_JABBERDIS; 1460 CSR_WRITE_4(sc, DC_WATCHDOG, watchdogreg); 1461 } else { 1462 DC_SETBIT(sc, DC_WATCHDOG, DC_WDOG_JABBERDIS); 1463 } 1464 DC_CLRBIT(sc, DC_NETCFG, (DC_NETCFG_PCS| 1465 DC_NETCFG_PORTSEL|DC_NETCFG_SCRAMBLER)); 1466 if (sc->dc_type == DC_TYPE_98713) 1467 DC_SETBIT(sc, DC_NETCFG, (DC_NETCFG_PCS| 1468 DC_NETCFG_SCRAMBLER)); 1469 if (!DC_IS_DAVICOM(sc)) 1470 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL); 1471 DC_CLRBIT(sc, DC_10BTCTRL, 0xFFFF); 1472 if (DC_IS_INTEL(sc)) 1473 dc_apply_fixup(sc, IFM_AUTO); 1474 } else { 1475 if (DC_IS_PNIC(sc)) { 1476 DC_PN_GPIO_SETBIT(sc, DC_PN_GPIO_SPEEDSEL); 1477 DC_PN_GPIO_SETBIT(sc, DC_PN_GPIO_100TX_LOOP); 1478 DC_SETBIT(sc, DC_PN_NWAY, DC_PN_NWAY_SPEEDSEL); 1479 } 1480 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL); 1481 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PCS); 1482 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_SCRAMBLER); 1483 if (DC_IS_INTEL(sc)) 1484 dc_apply_fixup(sc, 1485 (media & IFM_GMASK) == IFM_FDX ? 1486 IFM_100_TX|IFM_FDX : IFM_100_TX); 1487 } 1488 } 1489 1490 if (IFM_SUBTYPE(media) == IFM_10_T) { 1491 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_SPEEDSEL); 1492 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_HEARTBEAT); 1493 if (sc->dc_pmode == DC_PMODE_MII) { 1494 int watchdogreg; 1495 1496 /* there's a write enable bit here that reads as 1 */ 1497 if (DC_IS_INTEL(sc)) { 1498 watchdogreg = CSR_READ_4(sc, DC_WATCHDOG); 1499 watchdogreg &= ~DC_WDOG_CTLWREN; 1500 watchdogreg |= DC_WDOG_JABBERDIS; 1501 CSR_WRITE_4(sc, DC_WATCHDOG, watchdogreg); 1502 } else { 1503 DC_SETBIT(sc, DC_WATCHDOG, DC_WDOG_JABBERDIS); 1504 } 1505 DC_CLRBIT(sc, DC_NETCFG, (DC_NETCFG_PCS| 1506 DC_NETCFG_PORTSEL|DC_NETCFG_SCRAMBLER)); 1507 if (sc->dc_type == DC_TYPE_98713) 1508 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PCS); 1509 if (!DC_IS_DAVICOM(sc)) 1510 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL); 1511 DC_CLRBIT(sc, DC_10BTCTRL, 0xFFFF); 1512 if (DC_IS_INTEL(sc)) 1513 dc_apply_fixup(sc, IFM_AUTO); 1514 } else { 1515 if (DC_IS_PNIC(sc)) { 1516 DC_PN_GPIO_CLRBIT(sc, DC_PN_GPIO_SPEEDSEL); 1517 DC_PN_GPIO_SETBIT(sc, DC_PN_GPIO_100TX_LOOP); 1518 DC_CLRBIT(sc, DC_PN_NWAY, DC_PN_NWAY_SPEEDSEL); 1519 } 1520 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL); 1521 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_PCS); 1522 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_SCRAMBLER); 1523 if (DC_IS_INTEL(sc)) { 1524 DC_CLRBIT(sc, DC_SIARESET, DC_SIA_RESET); 1525 DC_CLRBIT(sc, DC_10BTCTRL, 0xFFFF); 1526 if ((media & IFM_GMASK) == IFM_FDX) 1527 DC_SETBIT(sc, DC_10BTCTRL, 0x7F3D); 1528 else 1529 DC_SETBIT(sc, DC_10BTCTRL, 0x7F3F); 1530 DC_SETBIT(sc, DC_SIARESET, DC_SIA_RESET); 1531 DC_CLRBIT(sc, DC_10BTCTRL, 1532 DC_TCTL_AUTONEGENBL); 1533 dc_apply_fixup(sc, 1534 (media & IFM_GMASK) == IFM_FDX ? 1535 IFM_10_T|IFM_FDX : IFM_10_T); 1536 DELAY(20000); 1537 } 1538 } 1539 } 1540 1541 /* 1542 * If this is a Davicom DM9102A card with a DM9801 HomePNA 1543 * PHY and we want HomePNA mode, set the portsel bit to turn 1544 * on the external MII port. 1545 */ 1546 if (DC_IS_DAVICOM(sc)) { 1547 if (IFM_SUBTYPE(media) == IFM_HPNA_1) { 1548 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL); 1549 sc->dc_link = 1; 1550 } else { 1551 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL); 1552 } 1553 } 1554 1555 if ((media & IFM_GMASK) == IFM_FDX) { 1556 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_FULLDUPLEX); 1557 if (sc->dc_pmode == DC_PMODE_SYM && DC_IS_PNIC(sc)) 1558 DC_SETBIT(sc, DC_PN_NWAY, DC_PN_NWAY_DUPLEX); 1559 } else { 1560 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_FULLDUPLEX); 1561 if (sc->dc_pmode == DC_PMODE_SYM && DC_IS_PNIC(sc)) 1562 DC_CLRBIT(sc, DC_PN_NWAY, DC_PN_NWAY_DUPLEX); 1563 } 1564 1565 if (restart) 1566 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_TX_ON|DC_NETCFG_RX_ON); 1567 1568 return; 1569 } 1570 1571 static void 1572 dc_reset(sc) 1573 struct dc_softc *sc; 1574 { 1575 register int i; 1576 1577 DC_SETBIT(sc, DC_BUSCTL, DC_BUSCTL_RESET); 1578 1579 for (i = 0; i < DC_TIMEOUT; i++) { 1580 DELAY(10); 1581 if (!(CSR_READ_4(sc, DC_BUSCTL) & DC_BUSCTL_RESET)) 1582 break; 1583 } 1584 1585 if (DC_IS_ASIX(sc) || DC_IS_ADMTEK(sc) || DC_IS_CONEXANT(sc) || 1586 DC_IS_XIRCOM(sc) || DC_IS_INTEL(sc)) { 1587 DELAY(10000); 1588 DC_CLRBIT(sc, DC_BUSCTL, DC_BUSCTL_RESET); 1589 i = 0; 1590 } 1591 1592 if (i == DC_TIMEOUT) 1593 printf("dc%d: reset never completed!\n", sc->dc_unit); 1594 1595 /* Wait a little while for the chip to get its brains in order. */ 1596 DELAY(1000); 1597 1598 CSR_WRITE_4(sc, DC_IMR, 0x00000000); 1599 CSR_WRITE_4(sc, DC_BUSCTL, 0x00000000); 1600 CSR_WRITE_4(sc, DC_NETCFG, 0x00000000); 1601 1602 /* 1603 * Bring the SIA out of reset. In some cases, it looks 1604 * like failing to unreset the SIA soon enough gets it 1605 * into a state where it will never come out of reset 1606 * until we reset the whole chip again. 1607 */ 1608 if (DC_IS_INTEL(sc)) { 1609 DC_SETBIT(sc, DC_SIARESET, DC_SIA_RESET); 1610 CSR_WRITE_4(sc, DC_10BTCTRL, 0); 1611 CSR_WRITE_4(sc, DC_WATCHDOG, 0); 1612 } 1613 1614 return; 1615 } 1616 1617 static struct dc_type * 1618 dc_devtype(dev) 1619 device_t dev; 1620 { 1621 struct dc_type *t; 1622 u_int32_t rev; 1623 1624 t = dc_devs; 1625 1626 while(t->dc_name != NULL) { 1627 if ((pci_get_vendor(dev) == t->dc_vid) && 1628 (pci_get_device(dev) == t->dc_did)) { 1629 /* Check the PCI revision */ 1630 rev = pci_read_config(dev, DC_PCI_CFRV, 4) & 0xFF; 1631 if (t->dc_did == DC_DEVICEID_98713 && 1632 rev >= DC_REVISION_98713A) 1633 t++; 1634 if (t->dc_did == DC_DEVICEID_98713_CP && 1635 rev >= DC_REVISION_98713A) 1636 t++; 1637 if (t->dc_did == DC_DEVICEID_987x5 && 1638 rev >= DC_REVISION_98715AEC_C) 1639 t++; 1640 if (t->dc_did == DC_DEVICEID_987x5 && 1641 rev >= DC_REVISION_98725) 1642 t++; 1643 if (t->dc_did == DC_DEVICEID_AX88140A && 1644 rev >= DC_REVISION_88141) 1645 t++; 1646 if (t->dc_did == DC_DEVICEID_82C168 && 1647 rev >= DC_REVISION_82C169) 1648 t++; 1649 if (t->dc_did == DC_DEVICEID_DM9102 && 1650 rev >= DC_REVISION_DM9102A) 1651 t++; 1652 return(t); 1653 } 1654 t++; 1655 } 1656 1657 return(NULL); 1658 } 1659 1660 /* 1661 * Probe for a 21143 or clone chip. Check the PCI vendor and device 1662 * IDs against our list and return a device name if we find a match. 1663 * We do a little bit of extra work to identify the exact type of 1664 * chip. The MX98713 and MX98713A have the same PCI vendor/device ID, 1665 * but different revision IDs. The same is true for 98715/98715A 1666 * chips and the 98725, as well as the ASIX and ADMtek chips. In some 1667 * cases, the exact chip revision affects driver behavior. 1668 */ 1669 static int 1670 dc_probe(dev) 1671 device_t dev; 1672 { 1673 struct dc_type *t; 1674 1675 t = dc_devtype(dev); 1676 1677 if (t != NULL) { 1678 device_set_desc(dev, t->dc_name); 1679 return(0); 1680 } 1681 1682 return(ENXIO); 1683 } 1684 1685 static void 1686 dc_acpi(dev) 1687 device_t dev; 1688 { 1689 int unit; 1690 1691 unit = device_get_unit(dev); 1692 1693 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) { 1694 u_int32_t iobase, membase, irq; 1695 1696 /* Save important PCI config data. */ 1697 iobase = pci_read_config(dev, DC_PCI_CFBIO, 4); 1698 membase = pci_read_config(dev, DC_PCI_CFBMA, 4); 1699 irq = pci_read_config(dev, DC_PCI_CFIT, 4); 1700 1701 /* Reset the power state. */ 1702 printf("dc%d: chip is in D%d power mode " 1703 "-- setting to D0\n", unit, 1704 pci_get_powerstate(dev)); 1705 pci_set_powerstate(dev, PCI_POWERSTATE_D0); 1706 1707 /* Restore PCI config data. */ 1708 pci_write_config(dev, DC_PCI_CFBIO, iobase, 4); 1709 pci_write_config(dev, DC_PCI_CFBMA, membase, 4); 1710 pci_write_config(dev, DC_PCI_CFIT, irq, 4); 1711 } 1712 1713 return; 1714 } 1715 1716 static void 1717 dc_apply_fixup(sc, media) 1718 struct dc_softc *sc; 1719 int media; 1720 { 1721 struct dc_mediainfo *m; 1722 u_int8_t *p; 1723 int i; 1724 u_int32_t reg; 1725 1726 m = sc->dc_mi; 1727 1728 while (m != NULL) { 1729 if (m->dc_media == media) 1730 break; 1731 m = m->dc_next; 1732 } 1733 1734 if (m == NULL) 1735 return; 1736 1737 for (i = 0, p = m->dc_reset_ptr; i < m->dc_reset_len; i++, p += 2) { 1738 reg = (p[0] | (p[1] << 8)) << 16; 1739 CSR_WRITE_4(sc, DC_WATCHDOG, reg); 1740 } 1741 1742 for (i = 0, p = m->dc_gp_ptr; i < m->dc_gp_len; i++, p += 2) { 1743 reg = (p[0] | (p[1] << 8)) << 16; 1744 CSR_WRITE_4(sc, DC_WATCHDOG, reg); 1745 } 1746 1747 return; 1748 } 1749 1750 static void 1751 dc_decode_leaf_sia(sc, l) 1752 struct dc_softc *sc; 1753 struct dc_eblock_sia *l; 1754 { 1755 struct dc_mediainfo *m; 1756 1757 m = malloc(sizeof(struct dc_mediainfo), M_DEVBUF, M_NOWAIT); 1758 bzero(m, sizeof(struct dc_mediainfo)); 1759 if (l->dc_sia_code == DC_SIA_CODE_10BT) 1760 m->dc_media = IFM_10_T; 1761 1762 if (l->dc_sia_code == DC_SIA_CODE_10BT_FDX) 1763 m->dc_media = IFM_10_T|IFM_FDX; 1764 1765 if (l->dc_sia_code == DC_SIA_CODE_10B2) 1766 m->dc_media = IFM_10_2; 1767 1768 if (l->dc_sia_code == DC_SIA_CODE_10B5) 1769 m->dc_media = IFM_10_5; 1770 1771 m->dc_gp_len = 2; 1772 m->dc_gp_ptr = (u_int8_t *)&l->dc_sia_gpio_ctl; 1773 1774 m->dc_next = sc->dc_mi; 1775 sc->dc_mi = m; 1776 1777 sc->dc_pmode = DC_PMODE_SIA; 1778 1779 return; 1780 } 1781 1782 static void 1783 dc_decode_leaf_sym(sc, l) 1784 struct dc_softc *sc; 1785 struct dc_eblock_sym *l; 1786 { 1787 struct dc_mediainfo *m; 1788 1789 m = malloc(sizeof(struct dc_mediainfo), M_DEVBUF, M_NOWAIT); 1790 bzero(m, sizeof(struct dc_mediainfo)); 1791 if (l->dc_sym_code == DC_SYM_CODE_100BT) 1792 m->dc_media = IFM_100_TX; 1793 1794 if (l->dc_sym_code == DC_SYM_CODE_100BT_FDX) 1795 m->dc_media = IFM_100_TX|IFM_FDX; 1796 1797 m->dc_gp_len = 2; 1798 m->dc_gp_ptr = (u_int8_t *)&l->dc_sym_gpio_ctl; 1799 1800 m->dc_next = sc->dc_mi; 1801 sc->dc_mi = m; 1802 1803 sc->dc_pmode = DC_PMODE_SYM; 1804 1805 return; 1806 } 1807 1808 static void 1809 dc_decode_leaf_mii(sc, l) 1810 struct dc_softc *sc; 1811 struct dc_eblock_mii *l; 1812 { 1813 u_int8_t *p; 1814 struct dc_mediainfo *m; 1815 1816 m = malloc(sizeof(struct dc_mediainfo), M_DEVBUF, M_NOWAIT); 1817 bzero(m, sizeof(struct dc_mediainfo)); 1818 /* We abuse IFM_AUTO to represent MII. */ 1819 m->dc_media = IFM_AUTO; 1820 m->dc_gp_len = l->dc_gpr_len; 1821 1822 p = (u_int8_t *)l; 1823 p += sizeof(struct dc_eblock_mii); 1824 m->dc_gp_ptr = p; 1825 p += 2 * l->dc_gpr_len; 1826 m->dc_reset_len = *p; 1827 p++; 1828 m->dc_reset_ptr = p; 1829 1830 m->dc_next = sc->dc_mi; 1831 sc->dc_mi = m; 1832 1833 return; 1834 } 1835 1836 static void 1837 dc_read_srom(sc, bits) 1838 struct dc_softc *sc; 1839 int bits; 1840 { 1841 int size; 1842 1843 size = 2 << bits; 1844 sc->dc_srom = malloc(size, M_DEVBUF, M_NOWAIT); 1845 dc_read_eeprom(sc, (caddr_t)sc->dc_srom, 0, (size / 2), 0); 1846 } 1847 1848 static void 1849 dc_parse_21143_srom(sc) 1850 struct dc_softc *sc; 1851 { 1852 struct dc_leaf_hdr *lhdr; 1853 struct dc_eblock_hdr *hdr; 1854 int i, loff; 1855 char *ptr; 1856 1857 loff = sc->dc_srom[27]; 1858 lhdr = (struct dc_leaf_hdr *)&(sc->dc_srom[loff]); 1859 1860 ptr = (char *)lhdr; 1861 ptr += sizeof(struct dc_leaf_hdr) - 1; 1862 for (i = 0; i < lhdr->dc_mcnt; i++) { 1863 hdr = (struct dc_eblock_hdr *)ptr; 1864 switch(hdr->dc_type) { 1865 case DC_EBLOCK_MII: 1866 dc_decode_leaf_mii(sc, (struct dc_eblock_mii *)hdr); 1867 break; 1868 case DC_EBLOCK_SIA: 1869 dc_decode_leaf_sia(sc, (struct dc_eblock_sia *)hdr); 1870 break; 1871 case DC_EBLOCK_SYM: 1872 dc_decode_leaf_sym(sc, (struct dc_eblock_sym *)hdr); 1873 break; 1874 default: 1875 /* Don't care. Yet. */ 1876 break; 1877 } 1878 ptr += (hdr->dc_len & 0x7F); 1879 ptr++; 1880 } 1881 1882 return; 1883 } 1884 1885 /* 1886 * Attach the interface. Allocate softc structures, do ifmedia 1887 * setup and ethernet/BPF attach. 1888 */ 1889 static int 1890 dc_attach(dev) 1891 device_t dev; 1892 { 1893 int tmp = 0; 1894 u_char eaddr[ETHER_ADDR_LEN]; 1895 u_int32_t command; 1896 struct dc_softc *sc; 1897 struct ifnet *ifp; 1898 u_int32_t revision; 1899 int unit, error = 0, rid, mac_offset; 1900 u_int8_t *mac; 1901 1902 sc = device_get_softc(dev); 1903 unit = device_get_unit(dev); 1904 1905 mtx_init(&sc->dc_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 1906 MTX_DEF | MTX_RECURSE); 1907 1908 /* 1909 * Handle power management nonsense. 1910 */ 1911 dc_acpi(dev); 1912 1913 /* 1914 * Map control/status registers. 1915 */ 1916 pci_enable_busmaster(dev); 1917 pci_enable_io(dev, SYS_RES_IOPORT); 1918 pci_enable_io(dev, SYS_RES_MEMORY); 1919 command = pci_read_config(dev, PCIR_COMMAND, 4); 1920 1921 #ifdef DC_USEIOSPACE 1922 if (!(command & PCIM_CMD_PORTEN)) { 1923 printf("dc%d: failed to enable I/O ports!\n", unit); 1924 error = ENXIO; 1925 goto fail; 1926 } 1927 #else 1928 if (!(command & PCIM_CMD_MEMEN)) { 1929 printf("dc%d: failed to enable memory mapping!\n", unit); 1930 error = ENXIO; 1931 goto fail; 1932 } 1933 #endif 1934 1935 rid = DC_RID; 1936 sc->dc_res = bus_alloc_resource(dev, DC_RES, &rid, 1937 0, ~0, 1, RF_ACTIVE); 1938 1939 if (sc->dc_res == NULL) { 1940 printf("dc%d: couldn't map ports/memory\n", unit); 1941 error = ENXIO; 1942 goto fail; 1943 } 1944 1945 sc->dc_btag = rman_get_bustag(sc->dc_res); 1946 sc->dc_bhandle = rman_get_bushandle(sc->dc_res); 1947 1948 /* Allocate interrupt */ 1949 rid = 0; 1950 sc->dc_irq = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, 0, ~0, 1, 1951 RF_SHAREABLE | RF_ACTIVE); 1952 1953 if (sc->dc_irq == NULL) { 1954 printf("dc%d: couldn't map interrupt\n", unit); 1955 error = ENXIO; 1956 goto fail; 1957 } 1958 1959 /* Need this info to decide on a chip type. */ 1960 sc->dc_info = dc_devtype(dev); 1961 revision = pci_read_config(dev, DC_PCI_CFRV, 4) & 0x000000FF; 1962 1963 /* Get the eeprom width, but PNIC and XIRCOM have diff eeprom */ 1964 if (sc->dc_info->dc_did != DC_DEVICEID_82C168 && 1965 sc->dc_info->dc_did != DC_DEVICEID_X3201) 1966 dc_eeprom_width(sc); 1967 1968 switch(sc->dc_info->dc_did) { 1969 case DC_DEVICEID_21143: 1970 sc->dc_type = DC_TYPE_21143; 1971 sc->dc_flags |= DC_TX_POLL|DC_TX_USE_TX_INTR; 1972 sc->dc_flags |= DC_REDUCED_MII_POLL; 1973 /* Save EEPROM contents so we can parse them later. */ 1974 dc_read_srom(sc, sc->dc_romwidth); 1975 break; 1976 case DC_DEVICEID_DM9009: 1977 case DC_DEVICEID_DM9100: 1978 case DC_DEVICEID_DM9102: 1979 sc->dc_type = DC_TYPE_DM9102; 1980 sc->dc_flags |= DC_TX_COALESCE|DC_TX_INTR_ALWAYS; 1981 sc->dc_flags |= DC_REDUCED_MII_POLL|DC_TX_STORENFWD; 1982 sc->dc_pmode = DC_PMODE_MII; 1983 /* Increase the latency timer value. */ 1984 command = pci_read_config(dev, DC_PCI_CFLT, 4); 1985 command &= 0xFFFF00FF; 1986 command |= 0x00008000; 1987 pci_write_config(dev, DC_PCI_CFLT, command, 4); 1988 break; 1989 case DC_DEVICEID_AL981: 1990 sc->dc_type = DC_TYPE_AL981; 1991 sc->dc_flags |= DC_TX_USE_TX_INTR; 1992 sc->dc_flags |= DC_TX_ADMTEK_WAR; 1993 sc->dc_pmode = DC_PMODE_MII; 1994 dc_read_srom(sc, sc->dc_romwidth); 1995 break; 1996 case DC_DEVICEID_AN985: 1997 case DC_DEVICEID_FE2500: 1998 case DC_DEVICEID_EN2242: 1999 case DC_DEVICEID_HAWKING_PN672TX: 2000 sc->dc_type = DC_TYPE_AN985; 2001 sc->dc_flags |= DC_TX_USE_TX_INTR; 2002 sc->dc_flags |= DC_TX_ADMTEK_WAR; 2003 sc->dc_pmode = DC_PMODE_MII; 2004 dc_read_srom(sc, sc->dc_romwidth); 2005 break; 2006 case DC_DEVICEID_98713: 2007 case DC_DEVICEID_98713_CP: 2008 if (revision < DC_REVISION_98713A) { 2009 sc->dc_type = DC_TYPE_98713; 2010 } 2011 if (revision >= DC_REVISION_98713A) { 2012 sc->dc_type = DC_TYPE_98713A; 2013 sc->dc_flags |= DC_21143_NWAY; 2014 } 2015 sc->dc_flags |= DC_REDUCED_MII_POLL; 2016 sc->dc_flags |= DC_TX_POLL|DC_TX_USE_TX_INTR; 2017 break; 2018 case DC_DEVICEID_987x5: 2019 case DC_DEVICEID_EN1217: 2020 /* 2021 * Macronix MX98715AEC-C/D/E parts have only a 2022 * 128-bit hash table. We need to deal with these 2023 * in the same manner as the PNIC II so that we 2024 * get the right number of bits out of the 2025 * CRC routine. 2026 */ 2027 if (revision >= DC_REVISION_98715AEC_C && 2028 revision < DC_REVISION_98725) 2029 sc->dc_flags |= DC_128BIT_HASH; 2030 sc->dc_type = DC_TYPE_987x5; 2031 sc->dc_flags |= DC_TX_POLL|DC_TX_USE_TX_INTR; 2032 sc->dc_flags |= DC_REDUCED_MII_POLL|DC_21143_NWAY; 2033 break; 2034 case DC_DEVICEID_98727: 2035 sc->dc_type = DC_TYPE_987x5; 2036 sc->dc_flags |= DC_TX_POLL|DC_TX_USE_TX_INTR; 2037 sc->dc_flags |= DC_REDUCED_MII_POLL|DC_21143_NWAY; 2038 break; 2039 case DC_DEVICEID_82C115: 2040 sc->dc_type = DC_TYPE_PNICII; 2041 sc->dc_flags |= DC_TX_POLL|DC_TX_USE_TX_INTR|DC_128BIT_HASH; 2042 sc->dc_flags |= DC_REDUCED_MII_POLL|DC_21143_NWAY; 2043 break; 2044 case DC_DEVICEID_82C168: 2045 sc->dc_type = DC_TYPE_PNIC; 2046 sc->dc_flags |= DC_TX_STORENFWD|DC_TX_INTR_ALWAYS; 2047 sc->dc_flags |= DC_PNIC_RX_BUG_WAR; 2048 sc->dc_pnic_rx_buf = malloc(DC_RXLEN * 5, M_DEVBUF, M_NOWAIT); 2049 if (revision < DC_REVISION_82C169) 2050 sc->dc_pmode = DC_PMODE_SYM; 2051 break; 2052 case DC_DEVICEID_AX88140A: 2053 sc->dc_type = DC_TYPE_ASIX; 2054 sc->dc_flags |= DC_TX_USE_TX_INTR|DC_TX_INTR_FIRSTFRAG; 2055 sc->dc_flags |= DC_REDUCED_MII_POLL; 2056 sc->dc_pmode = DC_PMODE_MII; 2057 break; 2058 case DC_DEVICEID_X3201: 2059 sc->dc_type = DC_TYPE_XIRCOM; 2060 sc->dc_flags |= DC_TX_INTR_ALWAYS | DC_TX_COALESCE | 2061 DC_TX_ALIGN; 2062 /* 2063 * We don't actually need to coalesce, but we're doing 2064 * it to obtain a double word aligned buffer. 2065 * The DC_TX_COALESCE flag is required. 2066 */ 2067 sc->dc_pmode = DC_PMODE_MII; 2068 break; 2069 case DC_DEVICEID_RS7112: 2070 sc->dc_type = DC_TYPE_CONEXANT; 2071 sc->dc_flags |= DC_TX_INTR_ALWAYS; 2072 sc->dc_flags |= DC_REDUCED_MII_POLL; 2073 sc->dc_pmode = DC_PMODE_MII; 2074 dc_read_srom(sc, sc->dc_romwidth); 2075 break; 2076 default: 2077 printf("dc%d: unknown device: %x\n", sc->dc_unit, 2078 sc->dc_info->dc_did); 2079 break; 2080 } 2081 2082 /* Save the cache line size. */ 2083 if (DC_IS_DAVICOM(sc)) 2084 sc->dc_cachesize = 0; 2085 else 2086 sc->dc_cachesize = pci_read_config(dev, 2087 DC_PCI_CFLT, 4) & 0xFF; 2088 2089 /* Reset the adapter. */ 2090 dc_reset(sc); 2091 2092 /* Take 21143 out of snooze mode */ 2093 if (DC_IS_INTEL(sc) || DC_IS_XIRCOM(sc)) { 2094 command = pci_read_config(dev, DC_PCI_CFDD, 4); 2095 command &= ~(DC_CFDD_SNOOZE_MODE|DC_CFDD_SLEEP_MODE); 2096 pci_write_config(dev, DC_PCI_CFDD, command, 4); 2097 } 2098 2099 /* 2100 * Try to learn something about the supported media. 2101 * We know that ASIX and ADMtek and Davicom devices 2102 * will *always* be using MII media, so that's a no-brainer. 2103 * The tricky ones are the Macronix/PNIC II and the 2104 * Intel 21143. 2105 */ 2106 if (DC_IS_INTEL(sc)) 2107 dc_parse_21143_srom(sc); 2108 else if (DC_IS_MACRONIX(sc) || DC_IS_PNICII(sc)) { 2109 if (sc->dc_type == DC_TYPE_98713) 2110 sc->dc_pmode = DC_PMODE_MII; 2111 else 2112 sc->dc_pmode = DC_PMODE_SYM; 2113 } else if (!sc->dc_pmode) 2114 sc->dc_pmode = DC_PMODE_MII; 2115 2116 /* 2117 * Get station address from the EEPROM. 2118 */ 2119 switch(sc->dc_type) { 2120 case DC_TYPE_98713: 2121 case DC_TYPE_98713A: 2122 case DC_TYPE_987x5: 2123 case DC_TYPE_PNICII: 2124 dc_read_eeprom(sc, (caddr_t)&mac_offset, 2125 (DC_EE_NODEADDR_OFFSET / 2), 1, 0); 2126 dc_read_eeprom(sc, (caddr_t)&eaddr, (mac_offset / 2), 3, 0); 2127 break; 2128 case DC_TYPE_PNIC: 2129 dc_read_eeprom(sc, (caddr_t)&eaddr, 0, 3, 1); 2130 break; 2131 case DC_TYPE_DM9102: 2132 case DC_TYPE_21143: 2133 case DC_TYPE_ASIX: 2134 dc_read_eeprom(sc, (caddr_t)&eaddr, DC_EE_NODEADDR, 3, 0); 2135 break; 2136 case DC_TYPE_AL981: 2137 case DC_TYPE_AN985: 2138 bcopy(&sc->dc_srom[DC_AL_EE_NODEADDR], (caddr_t)&eaddr, 2139 ETHER_ADDR_LEN); 2140 dc_read_eeprom(sc, (caddr_t)&eaddr, DC_AL_EE_NODEADDR, 3, 0); 2141 break; 2142 case DC_TYPE_CONEXANT: 2143 bcopy(sc->dc_srom + DC_CONEXANT_EE_NODEADDR, &eaddr, 6); 2144 break; 2145 case DC_TYPE_XIRCOM: 2146 /* The MAC comes from the CIS */ 2147 mac = pci_get_ether(dev); 2148 if (!mac) { 2149 device_printf(dev, "No station address in CIS!\n"); 2150 error = ENXIO; 2151 goto fail; 2152 } 2153 bcopy(mac, eaddr, ETHER_ADDR_LEN); 2154 break; 2155 default: 2156 dc_read_eeprom(sc, (caddr_t)&eaddr, DC_EE_NODEADDR, 3, 0); 2157 break; 2158 } 2159 2160 /* 2161 * A 21143 or clone chip was detected. Inform the world. 2162 */ 2163 printf("dc%d: Ethernet address: %6D\n", unit, eaddr, ":"); 2164 2165 sc->dc_unit = unit; 2166 bcopy(eaddr, (char *)&sc->arpcom.ac_enaddr, ETHER_ADDR_LEN); 2167 2168 sc->dc_ldata = contigmalloc(sizeof(struct dc_list_data), M_DEVBUF, 2169 M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0); 2170 2171 if (sc->dc_ldata == NULL) { 2172 printf("dc%d: no memory for list buffers!\n", unit); 2173 error = ENXIO; 2174 goto fail; 2175 } 2176 2177 bzero(sc->dc_ldata, sizeof(struct dc_list_data)); 2178 2179 ifp = &sc->arpcom.ac_if; 2180 ifp->if_softc = sc; 2181 ifp->if_unit = unit; 2182 ifp->if_name = "dc"; 2183 /* XXX: bleah, MTU gets overwritten in ether_ifattach() */ 2184 ifp->if_mtu = ETHERMTU; 2185 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 2186 ifp->if_ioctl = dc_ioctl; 2187 ifp->if_output = ether_output; 2188 ifp->if_start = dc_start; 2189 ifp->if_watchdog = dc_watchdog; 2190 ifp->if_init = dc_init; 2191 ifp->if_baudrate = 10000000; 2192 ifp->if_snd.ifq_maxlen = DC_TX_LIST_CNT - 1; 2193 2194 /* 2195 * Do MII setup. If this is a 21143, check for a PHY on the 2196 * MII bus after applying any necessary fixups to twiddle the 2197 * GPIO bits. If we don't end up finding a PHY, restore the 2198 * old selection (SIA only or SIA/SYM) and attach the dcphy 2199 * driver instead. 2200 */ 2201 if (DC_IS_INTEL(sc)) { 2202 dc_apply_fixup(sc, IFM_AUTO); 2203 tmp = sc->dc_pmode; 2204 sc->dc_pmode = DC_PMODE_MII; 2205 } 2206 2207 error = mii_phy_probe(dev, &sc->dc_miibus, 2208 dc_ifmedia_upd, dc_ifmedia_sts); 2209 2210 if (error && DC_IS_INTEL(sc)) { 2211 sc->dc_pmode = tmp; 2212 if (sc->dc_pmode != DC_PMODE_SIA) 2213 sc->dc_pmode = DC_PMODE_SYM; 2214 sc->dc_flags |= DC_21143_NWAY; 2215 mii_phy_probe(dev, &sc->dc_miibus, 2216 dc_ifmedia_upd, dc_ifmedia_sts); 2217 /* 2218 * For non-MII cards, we need to have the 21143 2219 * drive the LEDs. Except there are some systems 2220 * like the NEC VersaPro NoteBook PC which have no 2221 * LEDs, and twiddling these bits has adverse effects 2222 * on them. (I.e. you suddenly can't get a link.) 2223 */ 2224 if (pci_read_config(dev, DC_PCI_CSID, 4) != 0x80281033) 2225 sc->dc_flags |= DC_TULIP_LEDS; 2226 error = 0; 2227 } 2228 2229 if (error) { 2230 printf("dc%d: MII without any PHY!\n", sc->dc_unit); 2231 goto fail; 2232 } 2233 2234 if (DC_IS_XIRCOM(sc)) { 2235 /* 2236 * setup General Purpose Port mode and data so the tulip 2237 * can talk to the MII. 2238 */ 2239 CSR_WRITE_4(sc, DC_SIAGP, DC_SIAGP_WRITE_EN | DC_SIAGP_INT1_EN | 2240 DC_SIAGP_MD_GP2_OUTPUT | DC_SIAGP_MD_GP0_OUTPUT); 2241 DELAY(10); 2242 CSR_WRITE_4(sc, DC_SIAGP, DC_SIAGP_INT1_EN | 2243 DC_SIAGP_MD_GP2_OUTPUT | DC_SIAGP_MD_GP0_OUTPUT); 2244 DELAY(10); 2245 } 2246 2247 if (DC_IS_ADMTEK(sc)) { 2248 /* 2249 * Set automatic TX underrun recovery for the ADMtek chips 2250 */ 2251 DC_SETBIT(sc, DC_AL_CR, DC_AL_CR_ATUR); 2252 } 2253 2254 /* 2255 * Tell the upper layer(s) we support long frames. 2256 */ 2257 ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header); 2258 ifp->if_capabilities |= IFCAP_VLAN_MTU; 2259 2260 callout_init(&sc->dc_stat_ch, IS_MPSAFE); 2261 2262 #ifdef SRM_MEDIA 2263 sc->dc_srm_media = 0; 2264 2265 /* Remember the SRM console media setting */ 2266 if (DC_IS_INTEL(sc)) { 2267 command = pci_read_config(dev, DC_PCI_CFDD, 4); 2268 command &= ~(DC_CFDD_SNOOZE_MODE|DC_CFDD_SLEEP_MODE); 2269 switch ((command >> 8) & 0xff) { 2270 case 3: 2271 sc->dc_srm_media = IFM_10_T; 2272 break; 2273 case 4: 2274 sc->dc_srm_media = IFM_10_T | IFM_FDX; 2275 break; 2276 case 5: 2277 sc->dc_srm_media = IFM_100_TX; 2278 break; 2279 case 6: 2280 sc->dc_srm_media = IFM_100_TX | IFM_FDX; 2281 break; 2282 } 2283 if (sc->dc_srm_media) 2284 sc->dc_srm_media |= IFM_ACTIVE | IFM_ETHER; 2285 } 2286 #endif 2287 2288 /* 2289 * Call MI attach routine. 2290 */ 2291 ether_ifattach(ifp, eaddr); 2292 2293 /* Hook interrupt last to avoid having to lock softc */ 2294 error = bus_setup_intr(dev, sc->dc_irq, INTR_TYPE_NET | 2295 (IS_MPSAFE ? INTR_MPSAFE : 0), 2296 dc_intr, sc, &sc->dc_intrhand); 2297 2298 if (error) { 2299 printf("dc%d: couldn't set up irq\n", unit); 2300 goto fail; 2301 } 2302 2303 fail: 2304 if (error) 2305 dc_detach(dev); 2306 return (error); 2307 } 2308 2309 static int 2310 dc_detach(dev) 2311 device_t dev; 2312 { 2313 struct dc_softc *sc; 2314 struct ifnet *ifp; 2315 struct dc_mediainfo *m; 2316 2317 sc = device_get_softc(dev); 2318 KASSERT(mtx_initialized(&sc->dc_mtx), ("dc mutex not initialized")); 2319 DC_LOCK(sc); 2320 2321 ifp = &sc->arpcom.ac_if; 2322 2323 if (device_is_alive(dev)) { 2324 if (bus_child_present(dev)) 2325 dc_stop(sc); 2326 ether_ifdetach(ifp); 2327 device_delete_child(dev, sc->dc_miibus); 2328 bus_generic_detach(dev); 2329 } 2330 2331 if (sc->dc_intrhand) 2332 bus_teardown_intr(dev, sc->dc_irq, sc->dc_intrhand); 2333 if (sc->dc_irq) 2334 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->dc_irq); 2335 if (sc->dc_res) 2336 bus_release_resource(dev, DC_RES, DC_RID, sc->dc_res); 2337 2338 if (sc->dc_ldata) 2339 contigfree(sc->dc_ldata, sizeof(struct dc_list_data), M_DEVBUF); 2340 free(sc->dc_pnic_rx_buf, M_DEVBUF); 2341 2342 while(sc->dc_mi != NULL) { 2343 m = sc->dc_mi->dc_next; 2344 free(sc->dc_mi, M_DEVBUF); 2345 sc->dc_mi = m; 2346 } 2347 free(sc->dc_srom, M_DEVBUF); 2348 2349 DC_UNLOCK(sc); 2350 mtx_destroy(&sc->dc_mtx); 2351 2352 return(0); 2353 } 2354 2355 /* 2356 * Initialize the transmit descriptors. 2357 */ 2358 static int 2359 dc_list_tx_init(sc) 2360 struct dc_softc *sc; 2361 { 2362 struct dc_chain_data *cd; 2363 struct dc_list_data *ld; 2364 int i, nexti; 2365 2366 cd = &sc->dc_cdata; 2367 ld = sc->dc_ldata; 2368 for (i = 0; i < DC_TX_LIST_CNT; i++) { 2369 nexti = (i == (DC_TX_LIST_CNT - 1)) ? 0 : i+1; 2370 ld->dc_tx_list[i].dc_next = vtophys(&ld->dc_tx_list[nexti]); 2371 cd->dc_tx_chain[i] = NULL; 2372 ld->dc_tx_list[i].dc_data = 0; 2373 ld->dc_tx_list[i].dc_ctl = 0; 2374 } 2375 2376 cd->dc_tx_prod = cd->dc_tx_cons = cd->dc_tx_cnt = 0; 2377 2378 return(0); 2379 } 2380 2381 2382 /* 2383 * Initialize the RX descriptors and allocate mbufs for them. Note that 2384 * we arrange the descriptors in a closed ring, so that the last descriptor 2385 * points back to the first. 2386 */ 2387 static int 2388 dc_list_rx_init(sc) 2389 struct dc_softc *sc; 2390 { 2391 struct dc_chain_data *cd; 2392 struct dc_list_data *ld; 2393 int i, nexti; 2394 2395 cd = &sc->dc_cdata; 2396 ld = sc->dc_ldata; 2397 2398 for (i = 0; i < DC_RX_LIST_CNT; i++) { 2399 if (dc_newbuf(sc, i, NULL) == ENOBUFS) 2400 return(ENOBUFS); 2401 nexti = (i == (DC_RX_LIST_CNT - 1)) ? 0 : i+1; 2402 ld->dc_rx_list[i].dc_next = vtophys(&ld->dc_rx_list[nexti]); 2403 } 2404 2405 cd->dc_rx_prod = 0; 2406 2407 return(0); 2408 } 2409 2410 /* 2411 * Initialize an RX descriptor and attach an MBUF cluster. 2412 */ 2413 static int 2414 dc_newbuf(sc, i, m) 2415 struct dc_softc *sc; 2416 int i; 2417 struct mbuf *m; 2418 { 2419 struct mbuf *m_new = NULL; 2420 struct dc_desc *c; 2421 2422 c = &sc->dc_ldata->dc_rx_list[i]; 2423 2424 if (m == NULL) { 2425 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 2426 if (m_new == NULL) 2427 return(ENOBUFS); 2428 2429 MCLGET(m_new, M_DONTWAIT); 2430 if (!(m_new->m_flags & M_EXT)) { 2431 m_freem(m_new); 2432 return(ENOBUFS); 2433 } 2434 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 2435 } else { 2436 m_new = m; 2437 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 2438 m_new->m_data = m_new->m_ext.ext_buf; 2439 } 2440 2441 m_adj(m_new, sizeof(u_int64_t)); 2442 2443 /* 2444 * If this is a PNIC chip, zero the buffer. This is part 2445 * of the workaround for the receive bug in the 82c168 and 2446 * 82c169 chips. 2447 */ 2448 if (sc->dc_flags & DC_PNIC_RX_BUG_WAR) 2449 bzero((char *)mtod(m_new, char *), m_new->m_len); 2450 2451 sc->dc_cdata.dc_rx_chain[i] = m_new; 2452 c->dc_data = vtophys(mtod(m_new, caddr_t)); 2453 c->dc_ctl = DC_RXCTL_RLINK | DC_RXLEN; 2454 c->dc_status = DC_RXSTAT_OWN; 2455 2456 return(0); 2457 } 2458 2459 /* 2460 * Grrrrr. 2461 * The PNIC chip has a terrible bug in it that manifests itself during 2462 * periods of heavy activity. The exact mode of failure if difficult to 2463 * pinpoint: sometimes it only happens in promiscuous mode, sometimes it 2464 * will happen on slow machines. The bug is that sometimes instead of 2465 * uploading one complete frame during reception, it uploads what looks 2466 * like the entire contents of its FIFO memory. The frame we want is at 2467 * the end of the whole mess, but we never know exactly how much data has 2468 * been uploaded, so salvaging the frame is hard. 2469 * 2470 * There is only one way to do it reliably, and it's disgusting. 2471 * Here's what we know: 2472 * 2473 * - We know there will always be somewhere between one and three extra 2474 * descriptors uploaded. 2475 * 2476 * - We know the desired received frame will always be at the end of the 2477 * total data upload. 2478 * 2479 * - We know the size of the desired received frame because it will be 2480 * provided in the length field of the status word in the last descriptor. 2481 * 2482 * Here's what we do: 2483 * 2484 * - When we allocate buffers for the receive ring, we bzero() them. 2485 * This means that we know that the buffer contents should be all 2486 * zeros, except for data uploaded by the chip. 2487 * 2488 * - We also force the PNIC chip to upload frames that include the 2489 * ethernet CRC at the end. 2490 * 2491 * - We gather all of the bogus frame data into a single buffer. 2492 * 2493 * - We then position a pointer at the end of this buffer and scan 2494 * backwards until we encounter the first non-zero byte of data. 2495 * This is the end of the received frame. We know we will encounter 2496 * some data at the end of the frame because the CRC will always be 2497 * there, so even if the sender transmits a packet of all zeros, 2498 * we won't be fooled. 2499 * 2500 * - We know the size of the actual received frame, so we subtract 2501 * that value from the current pointer location. This brings us 2502 * to the start of the actual received packet. 2503 * 2504 * - We copy this into an mbuf and pass it on, along with the actual 2505 * frame length. 2506 * 2507 * The performance hit is tremendous, but it beats dropping frames all 2508 * the time. 2509 */ 2510 2511 #define DC_WHOLEFRAME (DC_RXSTAT_FIRSTFRAG|DC_RXSTAT_LASTFRAG) 2512 static void 2513 dc_pnic_rx_bug_war(sc, idx) 2514 struct dc_softc *sc; 2515 int idx; 2516 { 2517 struct dc_desc *cur_rx; 2518 struct dc_desc *c = NULL; 2519 struct mbuf *m = NULL; 2520 unsigned char *ptr; 2521 int i, total_len; 2522 u_int32_t rxstat = 0; 2523 2524 i = sc->dc_pnic_rx_bug_save; 2525 cur_rx = &sc->dc_ldata->dc_rx_list[idx]; 2526 ptr = sc->dc_pnic_rx_buf; 2527 bzero(ptr, sizeof(DC_RXLEN * 5)); 2528 2529 /* Copy all the bytes from the bogus buffers. */ 2530 while (1) { 2531 c = &sc->dc_ldata->dc_rx_list[i]; 2532 rxstat = c->dc_status; 2533 m = sc->dc_cdata.dc_rx_chain[i]; 2534 bcopy(mtod(m, char *), ptr, DC_RXLEN); 2535 ptr += DC_RXLEN; 2536 /* If this is the last buffer, break out. */ 2537 if (i == idx || rxstat & DC_RXSTAT_LASTFRAG) 2538 break; 2539 dc_newbuf(sc, i, m); 2540 DC_INC(i, DC_RX_LIST_CNT); 2541 } 2542 2543 /* Find the length of the actual receive frame. */ 2544 total_len = DC_RXBYTES(rxstat); 2545 2546 /* Scan backwards until we hit a non-zero byte. */ 2547 while(*ptr == 0x00) 2548 ptr--; 2549 2550 /* Round off. */ 2551 if ((uintptr_t)(ptr) & 0x3) 2552 ptr -= 1; 2553 2554 /* Now find the start of the frame. */ 2555 ptr -= total_len; 2556 if (ptr < sc->dc_pnic_rx_buf) 2557 ptr = sc->dc_pnic_rx_buf; 2558 2559 /* 2560 * Now copy the salvaged frame to the last mbuf and fake up 2561 * the status word to make it look like a successful 2562 * frame reception. 2563 */ 2564 dc_newbuf(sc, i, m); 2565 bcopy(ptr, mtod(m, char *), total_len); 2566 cur_rx->dc_status = rxstat | DC_RXSTAT_FIRSTFRAG; 2567 2568 return; 2569 } 2570 2571 /* 2572 * This routine searches the RX ring for dirty descriptors in the 2573 * event that the rxeof routine falls out of sync with the chip's 2574 * current descriptor pointer. This may happen sometimes as a result 2575 * of a "no RX buffer available" condition that happens when the chip 2576 * consumes all of the RX buffers before the driver has a chance to 2577 * process the RX ring. This routine may need to be called more than 2578 * once to bring the driver back in sync with the chip, however we 2579 * should still be getting RX DONE interrupts to drive the search 2580 * for new packets in the RX ring, so we should catch up eventually. 2581 */ 2582 static int 2583 dc_rx_resync(sc) 2584 struct dc_softc *sc; 2585 { 2586 int i, pos; 2587 struct dc_desc *cur_rx; 2588 2589 pos = sc->dc_cdata.dc_rx_prod; 2590 2591 for (i = 0; i < DC_RX_LIST_CNT; i++) { 2592 cur_rx = &sc->dc_ldata->dc_rx_list[pos]; 2593 if (!(cur_rx->dc_status & DC_RXSTAT_OWN)) 2594 break; 2595 DC_INC(pos, DC_RX_LIST_CNT); 2596 } 2597 2598 /* If the ring really is empty, then just return. */ 2599 if (i == DC_RX_LIST_CNT) 2600 return(0); 2601 2602 /* We've fallen behing the chip: catch it. */ 2603 sc->dc_cdata.dc_rx_prod = pos; 2604 2605 return(EAGAIN); 2606 } 2607 2608 /* 2609 * A frame has been uploaded: pass the resulting mbuf chain up to 2610 * the higher level protocols. 2611 */ 2612 static void 2613 dc_rxeof(sc) 2614 struct dc_softc *sc; 2615 { 2616 struct mbuf *m; 2617 struct ifnet *ifp; 2618 struct dc_desc *cur_rx; 2619 int i, total_len = 0; 2620 u_int32_t rxstat; 2621 2622 ifp = &sc->arpcom.ac_if; 2623 i = sc->dc_cdata.dc_rx_prod; 2624 2625 while(!(sc->dc_ldata->dc_rx_list[i].dc_status & DC_RXSTAT_OWN)) { 2626 2627 #ifdef DEVICE_POLLING 2628 if (ifp->if_flags & IFF_POLLING) { 2629 if (sc->rxcycles <= 0) 2630 break; 2631 sc->rxcycles--; 2632 } 2633 #endif /* DEVICE_POLLING */ 2634 cur_rx = &sc->dc_ldata->dc_rx_list[i]; 2635 rxstat = cur_rx->dc_status; 2636 m = sc->dc_cdata.dc_rx_chain[i]; 2637 total_len = DC_RXBYTES(rxstat); 2638 2639 if (sc->dc_flags & DC_PNIC_RX_BUG_WAR) { 2640 if ((rxstat & DC_WHOLEFRAME) != DC_WHOLEFRAME) { 2641 if (rxstat & DC_RXSTAT_FIRSTFRAG) 2642 sc->dc_pnic_rx_bug_save = i; 2643 if ((rxstat & DC_RXSTAT_LASTFRAG) == 0) { 2644 DC_INC(i, DC_RX_LIST_CNT); 2645 continue; 2646 } 2647 dc_pnic_rx_bug_war(sc, i); 2648 rxstat = cur_rx->dc_status; 2649 total_len = DC_RXBYTES(rxstat); 2650 } 2651 } 2652 2653 sc->dc_cdata.dc_rx_chain[i] = NULL; 2654 2655 /* 2656 * If an error occurs, update stats, clear the 2657 * status word and leave the mbuf cluster in place: 2658 * it should simply get re-used next time this descriptor 2659 * comes up in the ring. However, don't report long 2660 * frames as errors since they could be vlans 2661 */ 2662 if ((rxstat & DC_RXSTAT_RXERR)){ 2663 if (!(rxstat & DC_RXSTAT_GIANT) || 2664 (rxstat & (DC_RXSTAT_CRCERR | DC_RXSTAT_DRIBBLE | 2665 DC_RXSTAT_MIIERE | DC_RXSTAT_COLLSEEN | 2666 DC_RXSTAT_RUNT | DC_RXSTAT_DE))) { 2667 ifp->if_ierrors++; 2668 if (rxstat & DC_RXSTAT_COLLSEEN) 2669 ifp->if_collisions++; 2670 dc_newbuf(sc, i, m); 2671 if (rxstat & DC_RXSTAT_CRCERR) { 2672 DC_INC(i, DC_RX_LIST_CNT); 2673 continue; 2674 } else { 2675 dc_init(sc); 2676 return; 2677 } 2678 } 2679 } 2680 2681 /* No errors; receive the packet. */ 2682 total_len -= ETHER_CRC_LEN; 2683 #ifdef __i386__ 2684 /* 2685 * On the x86 we do not have alignment problems, so try to 2686 * allocate a new buffer for the receive ring, and pass up 2687 * the one where the packet is already, saving the expensive 2688 * copy done in m_devget(). 2689 * If we are on an architecture with alignment problems, or 2690 * if the allocation fails, then use m_devget and leave the 2691 * existing buffer in the receive ring. 2692 */ 2693 if (dc_quick && dc_newbuf(sc, i, NULL) == 0) { 2694 m->m_pkthdr.rcvif = ifp; 2695 m->m_pkthdr.len = m->m_len = total_len; 2696 DC_INC(i, DC_RX_LIST_CNT); 2697 } else 2698 #endif 2699 { 2700 struct mbuf *m0; 2701 2702 m0 = m_devget(mtod(m, char *), total_len, 2703 ETHER_ALIGN, ifp, NULL); 2704 dc_newbuf(sc, i, m); 2705 DC_INC(i, DC_RX_LIST_CNT); 2706 if (m0 == NULL) { 2707 ifp->if_ierrors++; 2708 continue; 2709 } 2710 m = m0; 2711 } 2712 2713 ifp->if_ipackets++; 2714 (*ifp->if_input)(ifp, m); 2715 } 2716 2717 sc->dc_cdata.dc_rx_prod = i; 2718 } 2719 2720 /* 2721 * A frame was downloaded to the chip. It's safe for us to clean up 2722 * the list buffers. 2723 */ 2724 2725 static void 2726 dc_txeof(sc) 2727 struct dc_softc *sc; 2728 { 2729 struct dc_desc *cur_tx = NULL; 2730 struct ifnet *ifp; 2731 int idx; 2732 2733 ifp = &sc->arpcom.ac_if; 2734 2735 /* 2736 * Go through our tx list and free mbufs for those 2737 * frames that have been transmitted. 2738 */ 2739 idx = sc->dc_cdata.dc_tx_cons; 2740 while(idx != sc->dc_cdata.dc_tx_prod) { 2741 u_int32_t txstat; 2742 2743 cur_tx = &sc->dc_ldata->dc_tx_list[idx]; 2744 txstat = cur_tx->dc_status; 2745 2746 if (txstat & DC_TXSTAT_OWN) 2747 break; 2748 2749 if (!(cur_tx->dc_ctl & DC_TXCTL_LASTFRAG) || 2750 cur_tx->dc_ctl & DC_TXCTL_SETUP) { 2751 if (cur_tx->dc_ctl & DC_TXCTL_SETUP) { 2752 /* 2753 * Yes, the PNIC is so brain damaged 2754 * that it will sometimes generate a TX 2755 * underrun error while DMAing the RX 2756 * filter setup frame. If we detect this, 2757 * we have to send the setup frame again, 2758 * or else the filter won't be programmed 2759 * correctly. 2760 */ 2761 if (DC_IS_PNIC(sc)) { 2762 if (txstat & DC_TXSTAT_ERRSUM) 2763 dc_setfilt(sc); 2764 } 2765 sc->dc_cdata.dc_tx_chain[idx] = NULL; 2766 } 2767 sc->dc_cdata.dc_tx_cnt--; 2768 DC_INC(idx, DC_TX_LIST_CNT); 2769 continue; 2770 } 2771 2772 if (DC_IS_XIRCOM(sc) || DC_IS_CONEXANT(sc)) { 2773 /* 2774 * XXX: Why does my Xircom taunt me so? 2775 * For some reason it likes setting the CARRLOST flag 2776 * even when the carrier is there. wtf?!? 2777 * Who knows, but Conexant chips have the 2778 * same problem. Maybe they took lessons 2779 * from Xircom. 2780 */ 2781 if (/*sc->dc_type == DC_TYPE_21143 &&*/ 2782 sc->dc_pmode == DC_PMODE_MII && 2783 ((txstat & 0xFFFF) & ~(DC_TXSTAT_ERRSUM| 2784 DC_TXSTAT_NOCARRIER))) 2785 txstat &= ~DC_TXSTAT_ERRSUM; 2786 } else { 2787 if (/*sc->dc_type == DC_TYPE_21143 &&*/ 2788 sc->dc_pmode == DC_PMODE_MII && 2789 ((txstat & 0xFFFF) & ~(DC_TXSTAT_ERRSUM| 2790 DC_TXSTAT_NOCARRIER|DC_TXSTAT_CARRLOST))) 2791 txstat &= ~DC_TXSTAT_ERRSUM; 2792 } 2793 2794 if (txstat & DC_TXSTAT_ERRSUM) { 2795 ifp->if_oerrors++; 2796 if (txstat & DC_TXSTAT_EXCESSCOLL) 2797 ifp->if_collisions++; 2798 if (txstat & DC_TXSTAT_LATECOLL) 2799 ifp->if_collisions++; 2800 if (!(txstat & DC_TXSTAT_UNDERRUN)) { 2801 dc_init(sc); 2802 return; 2803 } 2804 } 2805 2806 ifp->if_collisions += (txstat & DC_TXSTAT_COLLCNT) >> 3; 2807 2808 ifp->if_opackets++; 2809 if (sc->dc_cdata.dc_tx_chain[idx] != NULL) { 2810 m_freem(sc->dc_cdata.dc_tx_chain[idx]); 2811 sc->dc_cdata.dc_tx_chain[idx] = NULL; 2812 } 2813 2814 sc->dc_cdata.dc_tx_cnt--; 2815 DC_INC(idx, DC_TX_LIST_CNT); 2816 } 2817 2818 if (idx != sc->dc_cdata.dc_tx_cons) { 2819 /* some buffers have been freed */ 2820 sc->dc_cdata.dc_tx_cons = idx; 2821 ifp->if_flags &= ~IFF_OACTIVE; 2822 } 2823 ifp->if_timer = (sc->dc_cdata.dc_tx_cnt == 0) ? 0 : 5; 2824 2825 return; 2826 } 2827 2828 static void 2829 dc_tick(xsc) 2830 void *xsc; 2831 { 2832 struct dc_softc *sc; 2833 struct mii_data *mii; 2834 struct ifnet *ifp; 2835 u_int32_t r; 2836 2837 sc = xsc; 2838 DC_LOCK(sc); 2839 ifp = &sc->arpcom.ac_if; 2840 mii = device_get_softc(sc->dc_miibus); 2841 2842 if (sc->dc_flags & DC_REDUCED_MII_POLL) { 2843 if (sc->dc_flags & DC_21143_NWAY) { 2844 r = CSR_READ_4(sc, DC_10BTSTAT); 2845 if (IFM_SUBTYPE(mii->mii_media_active) == 2846 IFM_100_TX && (r & DC_TSTAT_LS100)) { 2847 sc->dc_link = 0; 2848 mii_mediachg(mii); 2849 } 2850 if (IFM_SUBTYPE(mii->mii_media_active) == 2851 IFM_10_T && (r & DC_TSTAT_LS10)) { 2852 sc->dc_link = 0; 2853 mii_mediachg(mii); 2854 } 2855 if (sc->dc_link == 0) 2856 mii_tick(mii); 2857 } else { 2858 r = CSR_READ_4(sc, DC_ISR); 2859 if ((r & DC_ISR_RX_STATE) == DC_RXSTATE_WAIT && 2860 sc->dc_cdata.dc_tx_cnt == 0) { 2861 mii_tick(mii); 2862 if (!(mii->mii_media_status & IFM_ACTIVE)) 2863 sc->dc_link = 0; 2864 } 2865 } 2866 } else 2867 mii_tick(mii); 2868 2869 /* 2870 * When the init routine completes, we expect to be able to send 2871 * packets right away, and in fact the network code will send a 2872 * gratuitous ARP the moment the init routine marks the interface 2873 * as running. However, even though the MAC may have been initialized, 2874 * there may be a delay of a few seconds before the PHY completes 2875 * autonegotiation and the link is brought up. Any transmissions 2876 * made during that delay will be lost. Dealing with this is tricky: 2877 * we can't just pause in the init routine while waiting for the 2878 * PHY to come ready since that would bring the whole system to 2879 * a screeching halt for several seconds. 2880 * 2881 * What we do here is prevent the TX start routine from sending 2882 * any packets until a link has been established. After the 2883 * interface has been initialized, the tick routine will poll 2884 * the state of the PHY until the IFM_ACTIVE flag is set. Until 2885 * that time, packets will stay in the send queue, and once the 2886 * link comes up, they will be flushed out to the wire. 2887 */ 2888 if (!sc->dc_link && mii->mii_media_status & IFM_ACTIVE && 2889 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) { 2890 sc->dc_link++; 2891 if (ifp->if_snd.ifq_head != NULL) 2892 dc_start(ifp); 2893 } 2894 2895 if (sc->dc_flags & DC_21143_NWAY && !sc->dc_link) 2896 callout_reset(&sc->dc_stat_ch, hz/10, dc_tick, sc); 2897 else 2898 callout_reset(&sc->dc_stat_ch, hz, dc_tick, sc); 2899 2900 DC_UNLOCK(sc); 2901 2902 return; 2903 } 2904 2905 /* 2906 * A transmit underrun has occurred. Back off the transmit threshold, 2907 * or switch to store and forward mode if we have to. 2908 */ 2909 static void 2910 dc_tx_underrun(sc) 2911 struct dc_softc *sc; 2912 { 2913 u_int32_t isr; 2914 int i; 2915 2916 if (DC_IS_DAVICOM(sc)) 2917 dc_init(sc); 2918 2919 if (DC_IS_INTEL(sc)) { 2920 /* 2921 * The real 21143 requires that the transmitter be idle 2922 * in order to change the transmit threshold or store 2923 * and forward state. 2924 */ 2925 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_TX_ON); 2926 2927 for (i = 0; i < DC_TIMEOUT; i++) { 2928 isr = CSR_READ_4(sc, DC_ISR); 2929 if (isr & DC_ISR_TX_IDLE) 2930 break; 2931 DELAY(10); 2932 } 2933 if (i == DC_TIMEOUT) { 2934 printf("dc%d: failed to force tx to idle state\n", 2935 sc->dc_unit); 2936 dc_init(sc); 2937 } 2938 } 2939 2940 printf("dc%d: TX underrun -- ", sc->dc_unit); 2941 sc->dc_txthresh += DC_TXTHRESH_INC; 2942 if (sc->dc_txthresh > DC_TXTHRESH_MAX) { 2943 printf("using store and forward mode\n"); 2944 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_STORENFWD); 2945 } else { 2946 printf("increasing TX threshold\n"); 2947 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_TX_THRESH); 2948 DC_SETBIT(sc, DC_NETCFG, sc->dc_txthresh); 2949 } 2950 2951 if (DC_IS_INTEL(sc)) 2952 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_TX_ON); 2953 2954 return; 2955 } 2956 2957 #ifdef DEVICE_POLLING 2958 static poll_handler_t dc_poll; 2959 2960 static void 2961 dc_poll(struct ifnet *ifp, enum poll_cmd cmd, int count) 2962 { 2963 struct dc_softc *sc = ifp->if_softc; 2964 2965 if (cmd == POLL_DEREGISTER) { /* final call, enable interrupts */ 2966 /* Re-enable interrupts. */ 2967 CSR_WRITE_4(sc, DC_IMR, DC_INTRS); 2968 return; 2969 } 2970 sc->rxcycles = count; 2971 dc_rxeof(sc); 2972 dc_txeof(sc); 2973 if (ifp->if_snd.ifq_head != NULL && !(ifp->if_flags & IFF_OACTIVE)) 2974 dc_start(ifp); 2975 2976 if (cmd == POLL_AND_CHECK_STATUS) { /* also check status register */ 2977 u_int32_t status; 2978 2979 status = CSR_READ_4(sc, DC_ISR); 2980 status &= (DC_ISR_RX_WATDOGTIMEO|DC_ISR_RX_NOBUF| 2981 DC_ISR_TX_NOBUF|DC_ISR_TX_IDLE|DC_ISR_TX_UNDERRUN| 2982 DC_ISR_BUS_ERR); 2983 if (!status) 2984 return; 2985 /* ack what we have */ 2986 CSR_WRITE_4(sc, DC_ISR, status); 2987 2988 if (status & (DC_ISR_RX_WATDOGTIMEO|DC_ISR_RX_NOBUF)) { 2989 u_int32_t r = CSR_READ_4(sc, DC_FRAMESDISCARDED); 2990 ifp->if_ierrors += (r & 0xffff) + ((r >> 17) & 0x7ff); 2991 2992 if (dc_rx_resync(sc)) 2993 dc_rxeof(sc); 2994 } 2995 /* restart transmit unit if necessary */ 2996 if (status & DC_ISR_TX_IDLE && sc->dc_cdata.dc_tx_cnt) 2997 CSR_WRITE_4(sc, DC_TXSTART, 0xFFFFFFFF); 2998 2999 if (status & DC_ISR_TX_UNDERRUN) 3000 dc_tx_underrun(sc); 3001 3002 if (status & DC_ISR_BUS_ERR) { 3003 printf("dc_poll: dc%d bus error\n", sc->dc_unit); 3004 dc_reset(sc); 3005 dc_init(sc); 3006 } 3007 } 3008 } 3009 #endif /* DEVICE_POLLING */ 3010 3011 static void 3012 dc_intr(arg) 3013 void *arg; 3014 { 3015 struct dc_softc *sc; 3016 struct ifnet *ifp; 3017 u_int32_t status; 3018 3019 sc = arg; 3020 3021 if (sc->suspended) { 3022 return; 3023 } 3024 3025 if ((CSR_READ_4(sc, DC_ISR) & DC_INTRS) == 0) 3026 return; 3027 3028 DC_LOCK(sc); 3029 ifp = &sc->arpcom.ac_if; 3030 #ifdef DEVICE_POLLING 3031 if (ifp->if_flags & IFF_POLLING) 3032 goto done; 3033 if (ether_poll_register(dc_poll, ifp)) { /* ok, disable interrupts */ 3034 CSR_WRITE_4(sc, DC_IMR, 0x00000000); 3035 goto done; 3036 } 3037 #endif /* DEVICE_POLLING */ 3038 3039 /* Suppress unwanted interrupts */ 3040 if (!(ifp->if_flags & IFF_UP)) { 3041 if (CSR_READ_4(sc, DC_ISR) & DC_INTRS) 3042 dc_stop(sc); 3043 DC_UNLOCK(sc); 3044 return; 3045 } 3046 3047 /* Disable interrupts. */ 3048 CSR_WRITE_4(sc, DC_IMR, 0x00000000); 3049 3050 while(((status = CSR_READ_4(sc, DC_ISR)) & DC_INTRS) 3051 && status != 0xFFFFFFFF) { 3052 3053 CSR_WRITE_4(sc, DC_ISR, status); 3054 3055 if (status & DC_ISR_RX_OK) { 3056 int curpkts; 3057 curpkts = ifp->if_ipackets; 3058 dc_rxeof(sc); 3059 if (curpkts == ifp->if_ipackets) { 3060 while(dc_rx_resync(sc)) 3061 dc_rxeof(sc); 3062 } 3063 } 3064 3065 if (status & (DC_ISR_TX_OK|DC_ISR_TX_NOBUF)) 3066 dc_txeof(sc); 3067 3068 if (status & DC_ISR_TX_IDLE) { 3069 dc_txeof(sc); 3070 if (sc->dc_cdata.dc_tx_cnt) { 3071 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_TX_ON); 3072 CSR_WRITE_4(sc, DC_TXSTART, 0xFFFFFFFF); 3073 } 3074 } 3075 3076 if (status & DC_ISR_TX_UNDERRUN) 3077 dc_tx_underrun(sc); 3078 3079 if ((status & DC_ISR_RX_WATDOGTIMEO) 3080 || (status & DC_ISR_RX_NOBUF)) { 3081 int curpkts; 3082 curpkts = ifp->if_ipackets; 3083 dc_rxeof(sc); 3084 if (curpkts == ifp->if_ipackets) { 3085 while(dc_rx_resync(sc)) 3086 dc_rxeof(sc); 3087 } 3088 } 3089 3090 if (status & DC_ISR_BUS_ERR) { 3091 dc_reset(sc); 3092 dc_init(sc); 3093 } 3094 } 3095 3096 /* Re-enable interrupts. */ 3097 CSR_WRITE_4(sc, DC_IMR, DC_INTRS); 3098 3099 if (ifp->if_snd.ifq_head != NULL) 3100 dc_start(ifp); 3101 3102 #ifdef DEVICE_POLLING 3103 done: 3104 #endif /* DEVICE_POLLING */ 3105 3106 DC_UNLOCK(sc); 3107 3108 return; 3109 } 3110 3111 /* 3112 * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data 3113 * pointers to the fragment pointers. 3114 */ 3115 static int 3116 dc_encap(sc, m_head, txidx) 3117 struct dc_softc *sc; 3118 struct mbuf *m_head; 3119 u_int32_t *txidx; 3120 { 3121 struct dc_desc *f = NULL; 3122 struct mbuf *m; 3123 int frag, cur, cnt = 0, chainlen = 0; 3124 3125 /* 3126 * If there's no way we can send any packets, return now. 3127 */ 3128 if (DC_TX_LIST_CNT - sc->dc_cdata.dc_tx_cnt < 6) 3129 return (ENOBUFS); 3130 3131 /* 3132 * Count the number of frags in this chain to see if 3133 * we need to m_defrag. Since the descriptor list is shared 3134 * by all packets, we'll m_defrag long chains so that they 3135 * do not use up the entire list, even if they would fit. 3136 */ 3137 3138 for (m = m_head; m != NULL; m = m->m_next) 3139 chainlen++; 3140 3141 if ((chainlen > DC_TX_LIST_CNT / 4) || 3142 ((DC_TX_LIST_CNT - (chainlen + sc->dc_cdata.dc_tx_cnt)) < 6)) { 3143 m = m_defrag(m_head, M_DONTWAIT); 3144 if (m == NULL) 3145 return (ENOBUFS); 3146 m_head = m; 3147 } 3148 3149 /* 3150 * Start packing the mbufs in this chain into 3151 * the fragment pointers. Stop when we run out 3152 * of fragments or hit the end of the mbuf chain. 3153 */ 3154 m = m_head; 3155 cur = frag = *txidx; 3156 3157 for (m = m_head; m != NULL; m = m->m_next) { 3158 if (m->m_len != 0) { 3159 if (sc->dc_flags & DC_TX_ADMTEK_WAR) { 3160 if (*txidx != sc->dc_cdata.dc_tx_prod && 3161 frag == (DC_TX_LIST_CNT - 1)) 3162 return(ENOBUFS); 3163 } 3164 if ((DC_TX_LIST_CNT - 3165 (sc->dc_cdata.dc_tx_cnt + cnt)) < 5) 3166 return(ENOBUFS); 3167 3168 f = &sc->dc_ldata->dc_tx_list[frag]; 3169 f->dc_ctl = DC_TXCTL_TLINK | m->m_len; 3170 if (cnt == 0) { 3171 f->dc_status = 0; 3172 f->dc_ctl |= DC_TXCTL_FIRSTFRAG; 3173 } else 3174 f->dc_status = DC_TXSTAT_OWN; 3175 f->dc_data = vtophys(mtod(m, vm_offset_t)); 3176 cur = frag; 3177 DC_INC(frag, DC_TX_LIST_CNT); 3178 cnt++; 3179 } 3180 } 3181 3182 if (m != NULL) 3183 return(ENOBUFS); 3184 3185 sc->dc_cdata.dc_tx_cnt += cnt; 3186 sc->dc_cdata.dc_tx_chain[cur] = m_head; 3187 sc->dc_ldata->dc_tx_list[cur].dc_ctl |= DC_TXCTL_LASTFRAG; 3188 if (sc->dc_flags & DC_TX_INTR_FIRSTFRAG) 3189 sc->dc_ldata->dc_tx_list[*txidx].dc_ctl |= DC_TXCTL_FINT; 3190 if (sc->dc_flags & DC_TX_INTR_ALWAYS) 3191 sc->dc_ldata->dc_tx_list[cur].dc_ctl |= DC_TXCTL_FINT; 3192 if (sc->dc_flags & DC_TX_USE_TX_INTR && sc->dc_cdata.dc_tx_cnt > 64) 3193 sc->dc_ldata->dc_tx_list[cur].dc_ctl |= DC_TXCTL_FINT; 3194 sc->dc_ldata->dc_tx_list[*txidx].dc_status = DC_TXSTAT_OWN; 3195 *txidx = frag; 3196 3197 return(0); 3198 } 3199 3200 /* 3201 * Main transmit routine. To avoid having to do mbuf copies, we put pointers 3202 * to the mbuf data regions directly in the transmit lists. We also save a 3203 * copy of the pointers since the transmit list fragment pointers are 3204 * physical addresses. 3205 */ 3206 3207 static void 3208 dc_start(ifp) 3209 struct ifnet *ifp; 3210 { 3211 struct dc_softc *sc; 3212 struct mbuf *m_head = NULL, *m; 3213 int idx; 3214 3215 sc = ifp->if_softc; 3216 3217 DC_LOCK(sc); 3218 3219 if (!sc->dc_link && ifp->if_snd.ifq_len < 10) { 3220 DC_UNLOCK(sc); 3221 return; 3222 } 3223 3224 if (ifp->if_flags & IFF_OACTIVE) { 3225 DC_UNLOCK(sc); 3226 return; 3227 } 3228 3229 idx = sc->dc_cdata.dc_tx_prod; 3230 3231 while(sc->dc_cdata.dc_tx_chain[idx] == NULL) { 3232 IF_DEQUEUE(&ifp->if_snd, m_head); 3233 if (m_head == NULL) 3234 break; 3235 3236 if (sc->dc_flags & DC_TX_COALESCE && 3237 (m_head->m_next != NULL || 3238 sc->dc_flags & DC_TX_ALIGN)) { 3239 m = m_defrag(m_head, M_DONTWAIT); 3240 if (m == NULL) { 3241 IF_PREPEND(&ifp->if_snd, m_head); 3242 ifp->if_flags |= IFF_OACTIVE; 3243 break; 3244 } else { 3245 m_head = m; 3246 } 3247 } 3248 3249 if (dc_encap(sc, m_head, &idx)) { 3250 IF_PREPEND(&ifp->if_snd, m_head); 3251 ifp->if_flags |= IFF_OACTIVE; 3252 break; 3253 } 3254 3255 /* 3256 * If there's a BPF listener, bounce a copy of this frame 3257 * to him. 3258 */ 3259 BPF_MTAP(ifp, m_head); 3260 3261 if (sc->dc_flags & DC_TX_ONE) { 3262 ifp->if_flags |= IFF_OACTIVE; 3263 break; 3264 } 3265 } 3266 3267 /* Transmit */ 3268 sc->dc_cdata.dc_tx_prod = idx; 3269 if (!(sc->dc_flags & DC_TX_POLL)) 3270 CSR_WRITE_4(sc, DC_TXSTART, 0xFFFFFFFF); 3271 3272 /* 3273 * Set a timeout in case the chip goes out to lunch. 3274 */ 3275 ifp->if_timer = 5; 3276 3277 DC_UNLOCK(sc); 3278 3279 return; 3280 } 3281 3282 static void 3283 dc_init(xsc) 3284 void *xsc; 3285 { 3286 struct dc_softc *sc = xsc; 3287 struct ifnet *ifp = &sc->arpcom.ac_if; 3288 struct mii_data *mii; 3289 3290 DC_LOCK(sc); 3291 3292 mii = device_get_softc(sc->dc_miibus); 3293 3294 /* 3295 * Cancel pending I/O and free all RX/TX buffers. 3296 */ 3297 dc_stop(sc); 3298 dc_reset(sc); 3299 3300 /* 3301 * Set cache alignment and burst length. 3302 */ 3303 if (DC_IS_ASIX(sc) || DC_IS_DAVICOM(sc)) 3304 CSR_WRITE_4(sc, DC_BUSCTL, 0); 3305 else 3306 CSR_WRITE_4(sc, DC_BUSCTL, DC_BUSCTL_MRME|DC_BUSCTL_MRLE); 3307 /* 3308 * Evenly share the bus between receive and transmit process. 3309 */ 3310 if (DC_IS_INTEL(sc)) 3311 DC_SETBIT(sc, DC_BUSCTL, DC_BUSCTL_ARBITRATION); 3312 if (DC_IS_DAVICOM(sc) || DC_IS_INTEL(sc)) { 3313 DC_SETBIT(sc, DC_BUSCTL, DC_BURSTLEN_USECA); 3314 } else { 3315 DC_SETBIT(sc, DC_BUSCTL, DC_BURSTLEN_16LONG); 3316 } 3317 if (sc->dc_flags & DC_TX_POLL) 3318 DC_SETBIT(sc, DC_BUSCTL, DC_TXPOLL_1); 3319 switch(sc->dc_cachesize) { 3320 case 32: 3321 DC_SETBIT(sc, DC_BUSCTL, DC_CACHEALIGN_32LONG); 3322 break; 3323 case 16: 3324 DC_SETBIT(sc, DC_BUSCTL, DC_CACHEALIGN_16LONG); 3325 break; 3326 case 8: 3327 DC_SETBIT(sc, DC_BUSCTL, DC_CACHEALIGN_8LONG); 3328 break; 3329 case 0: 3330 default: 3331 DC_SETBIT(sc, DC_BUSCTL, DC_CACHEALIGN_NONE); 3332 break; 3333 } 3334 3335 if (sc->dc_flags & DC_TX_STORENFWD) 3336 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_STORENFWD); 3337 else { 3338 if (sc->dc_txthresh > DC_TXTHRESH_MAX) { 3339 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_STORENFWD); 3340 } else { 3341 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_STORENFWD); 3342 DC_SETBIT(sc, DC_NETCFG, sc->dc_txthresh); 3343 } 3344 } 3345 3346 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_NO_RXCRC); 3347 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_TX_BACKOFF); 3348 3349 if (DC_IS_MACRONIX(sc) || DC_IS_PNICII(sc)) { 3350 /* 3351 * The app notes for the 98713 and 98715A say that 3352 * in order to have the chips operate properly, a magic 3353 * number must be written to CSR16. Macronix does not 3354 * document the meaning of these bits so there's no way 3355 * to know exactly what they do. The 98713 has a magic 3356 * number all its own; the rest all use a different one. 3357 */ 3358 DC_CLRBIT(sc, DC_MX_MAGICPACKET, 0xFFFF0000); 3359 if (sc->dc_type == DC_TYPE_98713) 3360 DC_SETBIT(sc, DC_MX_MAGICPACKET, DC_MX_MAGIC_98713); 3361 else 3362 DC_SETBIT(sc, DC_MX_MAGICPACKET, DC_MX_MAGIC_98715); 3363 } 3364 3365 if (DC_IS_XIRCOM(sc)) { 3366 /* 3367 * setup General Purpose Port mode and data so the tulip 3368 * can talk to the MII. 3369 */ 3370 CSR_WRITE_4(sc, DC_SIAGP, DC_SIAGP_WRITE_EN | DC_SIAGP_INT1_EN | 3371 DC_SIAGP_MD_GP2_OUTPUT | DC_SIAGP_MD_GP0_OUTPUT); 3372 DELAY(10); 3373 CSR_WRITE_4(sc, DC_SIAGP, DC_SIAGP_INT1_EN | 3374 DC_SIAGP_MD_GP2_OUTPUT | DC_SIAGP_MD_GP0_OUTPUT); 3375 DELAY(10); 3376 } 3377 3378 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_TX_THRESH); 3379 DC_SETBIT(sc, DC_NETCFG, DC_TXTHRESH_MIN); 3380 3381 /* Init circular RX list. */ 3382 if (dc_list_rx_init(sc) == ENOBUFS) { 3383 printf("dc%d: initialization failed: no " 3384 "memory for rx buffers\n", sc->dc_unit); 3385 dc_stop(sc); 3386 DC_UNLOCK(sc); 3387 return; 3388 } 3389 3390 /* 3391 * Init tx descriptors. 3392 */ 3393 dc_list_tx_init(sc); 3394 3395 /* 3396 * Load the address of the RX list. 3397 */ 3398 CSR_WRITE_4(sc, DC_RXADDR, vtophys(&sc->dc_ldata->dc_rx_list[0])); 3399 CSR_WRITE_4(sc, DC_TXADDR, vtophys(&sc->dc_ldata->dc_tx_list[0])); 3400 3401 /* 3402 * Enable interrupts. 3403 */ 3404 #ifdef DEVICE_POLLING 3405 /* 3406 * ... but only if we are not polling, and make sure they are off in 3407 * the case of polling. Some cards (e.g. fxp) turn interrupts on 3408 * after a reset. 3409 */ 3410 if (ifp->if_flags & IFF_POLLING) 3411 CSR_WRITE_4(sc, DC_IMR, 0x00000000); 3412 else 3413 #endif 3414 CSR_WRITE_4(sc, DC_IMR, DC_INTRS); 3415 CSR_WRITE_4(sc, DC_ISR, 0xFFFFFFFF); 3416 3417 /* Enable transmitter. */ 3418 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_TX_ON); 3419 3420 /* 3421 * If this is an Intel 21143 and we're not using the 3422 * MII port, program the LED control pins so we get 3423 * link and activity indications. 3424 */ 3425 if (sc->dc_flags & DC_TULIP_LEDS) { 3426 CSR_WRITE_4(sc, DC_WATCHDOG, 3427 DC_WDOG_CTLWREN|DC_WDOG_LINK|DC_WDOG_ACTIVITY); 3428 CSR_WRITE_4(sc, DC_WATCHDOG, 0); 3429 } 3430 3431 /* 3432 * Load the RX/multicast filter. We do this sort of late 3433 * because the filter programming scheme on the 21143 and 3434 * some clones requires DMAing a setup frame via the TX 3435 * engine, and we need the transmitter enabled for that. 3436 */ 3437 dc_setfilt(sc); 3438 3439 /* Enable receiver. */ 3440 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_ON); 3441 CSR_WRITE_4(sc, DC_RXSTART, 0xFFFFFFFF); 3442 3443 mii_mediachg(mii); 3444 dc_setcfg(sc, sc->dc_if_media); 3445 3446 ifp->if_flags |= IFF_RUNNING; 3447 ifp->if_flags &= ~IFF_OACTIVE; 3448 3449 /* Don't start the ticker if this is a homePNA link. */ 3450 if (IFM_SUBTYPE(mii->mii_media.ifm_media) == IFM_HPNA_1) 3451 sc->dc_link = 1; 3452 else { 3453 if (sc->dc_flags & DC_21143_NWAY) 3454 callout_reset(&sc->dc_stat_ch, hz/10, dc_tick, sc); 3455 else 3456 callout_reset(&sc->dc_stat_ch, hz, dc_tick, sc); 3457 } 3458 3459 #ifdef SRM_MEDIA 3460 if(sc->dc_srm_media) { 3461 struct ifreq ifr; 3462 3463 ifr.ifr_media = sc->dc_srm_media; 3464 ifmedia_ioctl(ifp, &ifr, &mii->mii_media, SIOCSIFMEDIA); 3465 sc->dc_srm_media = 0; 3466 } 3467 #endif 3468 DC_UNLOCK(sc); 3469 return; 3470 } 3471 3472 /* 3473 * Set media options. 3474 */ 3475 static int 3476 dc_ifmedia_upd(ifp) 3477 struct ifnet *ifp; 3478 { 3479 struct dc_softc *sc; 3480 struct mii_data *mii; 3481 struct ifmedia *ifm; 3482 3483 sc = ifp->if_softc; 3484 mii = device_get_softc(sc->dc_miibus); 3485 mii_mediachg(mii); 3486 ifm = &mii->mii_media; 3487 3488 if (DC_IS_DAVICOM(sc) && 3489 IFM_SUBTYPE(ifm->ifm_media) == IFM_HPNA_1) 3490 dc_setcfg(sc, ifm->ifm_media); 3491 else 3492 sc->dc_link = 0; 3493 3494 return(0); 3495 } 3496 3497 /* 3498 * Report current media status. 3499 */ 3500 static void 3501 dc_ifmedia_sts(ifp, ifmr) 3502 struct ifnet *ifp; 3503 struct ifmediareq *ifmr; 3504 { 3505 struct dc_softc *sc; 3506 struct mii_data *mii; 3507 struct ifmedia *ifm; 3508 3509 sc = ifp->if_softc; 3510 mii = device_get_softc(sc->dc_miibus); 3511 mii_pollstat(mii); 3512 ifm = &mii->mii_media; 3513 if (DC_IS_DAVICOM(sc)) { 3514 if (IFM_SUBTYPE(ifm->ifm_media) == IFM_HPNA_1) { 3515 ifmr->ifm_active = ifm->ifm_media; 3516 ifmr->ifm_status = 0; 3517 return; 3518 } 3519 } 3520 ifmr->ifm_active = mii->mii_media_active; 3521 ifmr->ifm_status = mii->mii_media_status; 3522 3523 return; 3524 } 3525 3526 static int 3527 dc_ioctl(ifp, command, data) 3528 struct ifnet *ifp; 3529 u_long command; 3530 caddr_t data; 3531 { 3532 struct dc_softc *sc = ifp->if_softc; 3533 struct ifreq *ifr = (struct ifreq *) data; 3534 struct mii_data *mii; 3535 int error = 0; 3536 3537 DC_LOCK(sc); 3538 3539 switch(command) { 3540 case SIOCSIFFLAGS: 3541 if (ifp->if_flags & IFF_UP) { 3542 int need_setfilt = (ifp->if_flags ^ sc->dc_if_flags) & 3543 (IFF_PROMISC | IFF_ALLMULTI); 3544 3545 if (ifp->if_flags & IFF_RUNNING) { 3546 if (need_setfilt) 3547 dc_setfilt(sc); 3548 } else { 3549 sc->dc_txthresh = 0; 3550 dc_init(sc); 3551 } 3552 } else { 3553 if (ifp->if_flags & IFF_RUNNING) 3554 dc_stop(sc); 3555 } 3556 sc->dc_if_flags = ifp->if_flags; 3557 error = 0; 3558 break; 3559 case SIOCADDMULTI: 3560 case SIOCDELMULTI: 3561 dc_setfilt(sc); 3562 error = 0; 3563 break; 3564 case SIOCGIFMEDIA: 3565 case SIOCSIFMEDIA: 3566 mii = device_get_softc(sc->dc_miibus); 3567 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 3568 #ifdef SRM_MEDIA 3569 if (sc->dc_srm_media) 3570 sc->dc_srm_media = 0; 3571 #endif 3572 break; 3573 default: 3574 error = ether_ioctl(ifp, command, data); 3575 break; 3576 } 3577 3578 DC_UNLOCK(sc); 3579 3580 return(error); 3581 } 3582 3583 static void 3584 dc_watchdog(ifp) 3585 struct ifnet *ifp; 3586 { 3587 struct dc_softc *sc; 3588 3589 sc = ifp->if_softc; 3590 3591 DC_LOCK(sc); 3592 3593 ifp->if_oerrors++; 3594 printf("dc%d: watchdog timeout\n", sc->dc_unit); 3595 3596 dc_stop(sc); 3597 dc_reset(sc); 3598 dc_init(sc); 3599 3600 if (ifp->if_snd.ifq_head != NULL) 3601 dc_start(ifp); 3602 3603 DC_UNLOCK(sc); 3604 3605 return; 3606 } 3607 3608 /* 3609 * Stop the adapter and free any mbufs allocated to the 3610 * RX and TX lists. 3611 */ 3612 static void 3613 dc_stop(sc) 3614 struct dc_softc *sc; 3615 { 3616 register int i; 3617 struct ifnet *ifp; 3618 3619 DC_LOCK(sc); 3620 3621 ifp = &sc->arpcom.ac_if; 3622 ifp->if_timer = 0; 3623 3624 callout_stop(&sc->dc_stat_ch); 3625 3626 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 3627 #ifdef DEVICE_POLLING 3628 ether_poll_deregister(ifp); 3629 #endif 3630 3631 DC_CLRBIT(sc, DC_NETCFG, (DC_NETCFG_RX_ON|DC_NETCFG_TX_ON)); 3632 CSR_WRITE_4(sc, DC_IMR, 0x00000000); 3633 CSR_WRITE_4(sc, DC_TXADDR, 0x00000000); 3634 CSR_WRITE_4(sc, DC_RXADDR, 0x00000000); 3635 sc->dc_link = 0; 3636 3637 /* 3638 * Free data in the RX lists. 3639 */ 3640 for (i = 0; i < DC_RX_LIST_CNT; i++) { 3641 if (sc->dc_cdata.dc_rx_chain[i] != NULL) { 3642 m_freem(sc->dc_cdata.dc_rx_chain[i]); 3643 sc->dc_cdata.dc_rx_chain[i] = NULL; 3644 } 3645 } 3646 bzero((char *)&sc->dc_ldata->dc_rx_list, 3647 sizeof(sc->dc_ldata->dc_rx_list)); 3648 3649 /* 3650 * Free the TX list buffers. 3651 */ 3652 for (i = 0; i < DC_TX_LIST_CNT; i++) { 3653 if (sc->dc_cdata.dc_tx_chain[i] != NULL) { 3654 if (sc->dc_ldata->dc_tx_list[i].dc_ctl & 3655 DC_TXCTL_SETUP) { 3656 sc->dc_cdata.dc_tx_chain[i] = NULL; 3657 continue; 3658 } 3659 m_freem(sc->dc_cdata.dc_tx_chain[i]); 3660 sc->dc_cdata.dc_tx_chain[i] = NULL; 3661 } 3662 } 3663 3664 bzero((char *)&sc->dc_ldata->dc_tx_list, 3665 sizeof(sc->dc_ldata->dc_tx_list)); 3666 3667 DC_UNLOCK(sc); 3668 3669 return; 3670 } 3671 3672 /* 3673 * Device suspend routine. Stop the interface and save some PCI 3674 * settings in case the BIOS doesn't restore them properly on 3675 * resume. 3676 */ 3677 static int 3678 dc_suspend(dev) 3679 device_t dev; 3680 { 3681 register int i; 3682 int s; 3683 struct dc_softc *sc; 3684 3685 s = splimp(); 3686 3687 sc = device_get_softc(dev); 3688 3689 dc_stop(sc); 3690 3691 for (i = 0; i < 5; i++) 3692 sc->saved_maps[i] = pci_read_config(dev, PCIR_MAPS + i * 4, 4); 3693 sc->saved_biosaddr = pci_read_config(dev, PCIR_BIOS, 4); 3694 sc->saved_intline = pci_read_config(dev, PCIR_INTLINE, 1); 3695 sc->saved_cachelnsz = pci_read_config(dev, PCIR_CACHELNSZ, 1); 3696 sc->saved_lattimer = pci_read_config(dev, PCIR_LATTIMER, 1); 3697 3698 sc->suspended = 1; 3699 3700 splx(s); 3701 return (0); 3702 } 3703 3704 /* 3705 * Device resume routine. Restore some PCI settings in case the BIOS 3706 * doesn't, re-enable busmastering, and restart the interface if 3707 * appropriate. 3708 */ 3709 static int 3710 dc_resume(dev) 3711 device_t dev; 3712 { 3713 register int i; 3714 int s; 3715 struct dc_softc *sc; 3716 struct ifnet *ifp; 3717 3718 s = splimp(); 3719 3720 sc = device_get_softc(dev); 3721 ifp = &sc->arpcom.ac_if; 3722 3723 dc_acpi(dev); 3724 3725 /* better way to do this? */ 3726 for (i = 0; i < 5; i++) 3727 pci_write_config(dev, PCIR_MAPS + i * 4, sc->saved_maps[i], 4); 3728 pci_write_config(dev, PCIR_BIOS, sc->saved_biosaddr, 4); 3729 pci_write_config(dev, PCIR_INTLINE, sc->saved_intline, 1); 3730 pci_write_config(dev, PCIR_CACHELNSZ, sc->saved_cachelnsz, 1); 3731 pci_write_config(dev, PCIR_LATTIMER, sc->saved_lattimer, 1); 3732 3733 /* reenable busmastering */ 3734 pci_enable_busmaster(dev); 3735 pci_enable_io(dev, DC_RES); 3736 3737 /* reinitialize interface if necessary */ 3738 if (ifp->if_flags & IFF_UP) 3739 dc_init(sc); 3740 3741 sc->suspended = 0; 3742 3743 splx(s); 3744 return (0); 3745 } 3746 3747 /* 3748 * Stop all chip I/O so that the kernel's probe routines don't 3749 * get confused by errant DMAs when rebooting. 3750 */ 3751 static void 3752 dc_shutdown(dev) 3753 device_t dev; 3754 { 3755 struct dc_softc *sc; 3756 3757 sc = device_get_softc(dev); 3758 3759 dc_stop(sc); 3760 3761 return; 3762 } 3763