1 /* 2 * Copyright (c) 1997, 1998, 1999 3 * Bill Paul <wpaul@ee.columbia.edu>. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 3. All advertising materials mentioning features or use of this software 14 * must display the following acknowledgement: 15 * This product includes software developed by Bill Paul. 16 * 4. Neither the name of the author nor the names of any co-contributors 17 * may be used to endorse or promote products derived from this software 18 * without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30 * THE POSSIBILITY OF SUCH DAMAGE. 31 * 32 * $FreeBSD$ 33 */ 34 35 /* 36 * DEC "tulip" clone ethernet driver. Supports the DEC/Intel 21143 37 * series chips and several workalikes including the following: 38 * 39 * Macronix 98713/98715/98725 PMAC (www.macronix.com) 40 * Macronix/Lite-On 82c115 PNIC II (www.macronix.com) 41 * Lite-On 82c168/82c169 PNIC (www.litecom.com) 42 * ASIX Electronics AX88140A (www.asix.com.tw) 43 * ASIX Electronics AX88141 (www.asix.com.tw) 44 * ADMtek AL981 (www.admtek.com.tw) 45 * ADMtek AN985 (www.admtek.com.tw) 46 * Davicom DM9100, DM9102 (www.davicom8.com) 47 * 48 * Datasheets for the 21143 are available at developer.intel.com. 49 * Datasheets for the clone parts can be found at their respective sites. 50 * (Except for the PNIC; see www.freebsd.org/~wpaul/PNIC/pnic.ps.gz.) 51 * The PNIC II is essentially a Macronix 98715A chip; the only difference 52 * worth noting is that its multicast hash table is only 128 bits wide 53 * instead of 512. 54 * 55 * Written by Bill Paul <wpaul@ee.columbia.edu> 56 * Electrical Engineering Department 57 * Columbia University, New York City 58 */ 59 60 /* 61 * The Intel 21143 is the successor to the DEC 21140. It is basically 62 * the same as the 21140 but with a few new features. The 21143 supports 63 * three kinds of media attachments: 64 * 65 * o MII port, for 10Mbps and 100Mbps support and NWAY 66 * autonegotiation provided by an external PHY. 67 * o SYM port, for symbol mode 100Mbps support. 68 * o 10baseT port. 69 * o AUI/BNC port. 70 * 71 * The 100Mbps SYM port and 10baseT port can be used together in 72 * combination with the internal NWAY support to create a 10/100 73 * autosensing configuration. 74 * 75 * Knowing which media is available on a given card is tough: you're 76 * supposed to go slogging through the EEPROM looking for media 77 * description structures. Unfortunately, some card vendors that use 78 * the 21143 don't obey the DEC SROM spec correctly, which means that 79 * what you find in the EEPROM may not agree with reality. Fortunately, 80 * the 21143 provides us a way to get around this issue: lurking in 81 * PCI configuration space is the Configuration Wake-Up Command Register. 82 * This register is loaded with a value from the EEPROM when wake on LAN 83 * mode is enabled; this value tells us quite clearly what kind of media 84 * is attached to the NIC. The main purpose of this register is to tell 85 * the NIC what media to scan when in wake on LAN mode, however by 86 * forcibly enabling wake on LAN mode, we can use to learn what kind of 87 * media a given NIC has available and adapt ourselves accordingly. 88 * 89 * Of course, if the media description blocks in the EEPROM are bogus. 90 * what are the odds that the CWUC aren't bogus as well, right? Well, 91 * the CWUC value is more likely to be correct since wake on LAN mode 92 * won't work correctly without it, and wake on LAN is a big selling 93 * point these days. It's also harder to screw up a single byte than 94 * a whole media descriptor block. 95 * 96 * Note that not all tulip workalikes are handled in this driver: we only 97 * deal with those which are relatively well behaved. The Winbond is 98 * handled separately due to its different register offsets and the 99 * special handling needed for its various bugs. The PNIC is handled 100 * here, but I'm not thrilled about it. 101 * 102 * All of the workalike chips use some form of MII transceiver support 103 * with the exception of the Macronix chips, which also have a SYM port. 104 * The ASIX AX88140A is also documented to have a SYM port, but all 105 * the cards I've seen use an MII transceiver, probably because the 106 * AX88140A doesn't support internal NWAY. 107 */ 108 109 #include <sys/param.h> 110 #include <sys/systm.h> 111 #include <sys/sockio.h> 112 #include <sys/mbuf.h> 113 #include <sys/malloc.h> 114 #include <sys/kernel.h> 115 #include <sys/socket.h> 116 117 #include <net/if.h> 118 #include <net/if_arp.h> 119 #include <net/ethernet.h> 120 #include <net/if_dl.h> 121 #include <net/if_media.h> 122 123 #include <net/bpf.h> 124 125 #include <vm/vm.h> /* for vtophys */ 126 #include <vm/pmap.h> /* for vtophys */ 127 #include <machine/clock.h> /* for DELAY */ 128 #include <machine/bus_pio.h> 129 #include <machine/bus_memio.h> 130 #include <machine/bus.h> 131 #include <machine/resource.h> 132 #include <sys/bus.h> 133 #include <sys/rman.h> 134 135 #include <dev/mii/mii.h> 136 #include <dev/mii/miivar.h> 137 138 #include <pci/pcireg.h> 139 #include <pci/pcivar.h> 140 141 #define DC_USEIOSPACE 142 143 #include <pci/if_dcreg.h> 144 145 /* "controller miibus0" required. See GENERIC if you get errors here. */ 146 #include "miibus_if.h" 147 148 #ifndef lint 149 static const char rcsid[] = 150 "$FreeBSD$"; 151 #endif 152 153 /* 154 * Various supported device vendors/types and their names. 155 */ 156 static struct dc_type dc_devs[] = { 157 { DC_VENDORID_DEC, DC_DEVICEID_21143, 158 "Intel 21143 10/100BaseTX" }, 159 { DC_VENDORID_DAVICOM, DC_DEVICEID_DM9100, 160 "Davicom DM9100 10/100BaseTX" }, 161 { DC_VENDORID_DAVICOM, DC_DEVICEID_DM9102, 162 "Davicom DM9102 10/100BaseTX" }, 163 { DC_VENDORID_ADMTEK, DC_DEVICEID_AL981, 164 "ADMtek AL981 10/100BaseTX" }, 165 { DC_VENDORID_ADMTEK, DC_DEVICEID_AN985, 166 "ADMtek AN985 10/100BaseTX" }, 167 { DC_VENDORID_ASIX, DC_DEVICEID_AX88140A, 168 "ASIX AX88140A 10/100BaseTX" }, 169 { DC_VENDORID_ASIX, DC_DEVICEID_AX88140A, 170 "ASIX AX88141 10/100BaseTX" }, 171 { DC_VENDORID_MX, DC_DEVICEID_98713, 172 "Macronix 98713 10/100BaseTX" }, 173 { DC_VENDORID_MX, DC_DEVICEID_98713, 174 "Macronix 98713A 10/100BaseTX" }, 175 { DC_VENDORID_CP, DC_DEVICEID_98713_CP, 176 "Compex RL100-TX 10/100BaseTX" }, 177 { DC_VENDORID_CP, DC_DEVICEID_98713_CP, 178 "Compex RL100-TX 10/100BaseTX" }, 179 { DC_VENDORID_MX, DC_DEVICEID_987x5, 180 "Macronix 98715/98715A 10/100BaseTX" }, 181 { DC_VENDORID_MX, DC_DEVICEID_987x5, 182 "Macronix 98725 10/100BaseTX" }, 183 { DC_VENDORID_LO, DC_DEVICEID_82C115, 184 "LC82C115 PNIC II 10/100BaseTX" }, 185 { DC_VENDORID_LO, DC_DEVICEID_82C168, 186 "82c168 PNIC 10/100BaseTX" }, 187 { DC_VENDORID_LO, DC_DEVICEID_82C168, 188 "82c169 PNIC 10/100BaseTX" }, 189 { 0, 0, NULL } 190 }; 191 192 static int dc_probe __P((device_t)); 193 static int dc_attach __P((device_t)); 194 static int dc_detach __P((device_t)); 195 static void dc_acpi __P((device_t)); 196 static struct dc_type *dc_devtype __P((device_t)); 197 static int dc_newbuf __P((struct dc_softc *, int, struct mbuf *)); 198 static int dc_encap __P((struct dc_softc *, struct mbuf *, 199 u_int32_t *)); 200 static void dc_pnic_rx_bug_war __P((struct dc_softc *, int)); 201 static void dc_rxeof __P((struct dc_softc *)); 202 static void dc_txeof __P((struct dc_softc *)); 203 static void dc_tick __P((void *)); 204 static void dc_intr __P((void *)); 205 static void dc_start __P((struct ifnet *)); 206 static int dc_ioctl __P((struct ifnet *, u_long, caddr_t)); 207 static void dc_init __P((void *)); 208 static void dc_stop __P((struct dc_softc *)); 209 static void dc_watchdog __P((struct ifnet *)); 210 static void dc_shutdown __P((device_t)); 211 static int dc_ifmedia_upd __P((struct ifnet *)); 212 static void dc_ifmedia_sts __P((struct ifnet *, struct ifmediareq *)); 213 214 static void dc_delay __P((struct dc_softc *)); 215 static void dc_eeprom_idle __P((struct dc_softc *)); 216 static void dc_eeprom_putbyte __P((struct dc_softc *, int)); 217 static void dc_eeprom_getword __P((struct dc_softc *, int, u_int16_t *)); 218 static void dc_eeprom_getword_pnic 219 __P((struct dc_softc *, int, u_int16_t *)); 220 static void dc_read_eeprom __P((struct dc_softc *, caddr_t, int, 221 int, int)); 222 223 static void dc_mii_writebit __P((struct dc_softc *, int)); 224 static int dc_mii_readbit __P((struct dc_softc *)); 225 static void dc_mii_sync __P((struct dc_softc *)); 226 static void dc_mii_send __P((struct dc_softc *, u_int32_t, int)); 227 static int dc_mii_readreg __P((struct dc_softc *, struct dc_mii_frame *)); 228 static int dc_mii_writereg __P((struct dc_softc *, struct dc_mii_frame *)); 229 static int dc_miibus_readreg __P((device_t, int, int)); 230 static int dc_miibus_writereg __P((device_t, int, int, int)); 231 static void dc_miibus_statchg __P((device_t)); 232 233 static void dc_setcfg __P((struct dc_softc *, int)); 234 static u_int32_t dc_crc_le __P((struct dc_softc *, caddr_t)); 235 static u_int32_t dc_crc_be __P((caddr_t)); 236 static void dc_setfilt_21143 __P((struct dc_softc *)); 237 static void dc_setfilt_asix __P((struct dc_softc *)); 238 static void dc_setfilt_admtek __P((struct dc_softc *)); 239 240 static void dc_setfilt __P((struct dc_softc *)); 241 242 static void dc_reset __P((struct dc_softc *)); 243 static int dc_list_rx_init __P((struct dc_softc *)); 244 static int dc_list_tx_init __P((struct dc_softc *)); 245 246 #ifdef DC_USEIOSPACE 247 #define DC_RES SYS_RES_IOPORT 248 #define DC_RID DC_PCI_CFBIO 249 #else 250 #define DC_RES SYS_RES_MEMORY 251 #define DC_RID DC_PCI_CFBMA 252 #endif 253 254 static device_method_t dc_methods[] = { 255 /* Device interface */ 256 DEVMETHOD(device_probe, dc_probe), 257 DEVMETHOD(device_attach, dc_attach), 258 DEVMETHOD(device_detach, dc_detach), 259 DEVMETHOD(device_shutdown, dc_shutdown), 260 261 /* bus interface */ 262 DEVMETHOD(bus_print_child, bus_generic_print_child), 263 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 264 265 /* MII interface */ 266 DEVMETHOD(miibus_readreg, dc_miibus_readreg), 267 DEVMETHOD(miibus_writereg, dc_miibus_writereg), 268 DEVMETHOD(miibus_statchg, dc_miibus_statchg), 269 270 { 0, 0 } 271 }; 272 273 static driver_t dc_driver = { 274 "dc", 275 dc_methods, 276 sizeof(struct dc_softc) 277 }; 278 279 static devclass_t dc_devclass; 280 281 DRIVER_MODULE(if_dc, pci, dc_driver, dc_devclass, 0, 0); 282 DRIVER_MODULE(miibus, dc, miibus_driver, miibus_devclass, 0, 0); 283 284 #define DC_SETBIT(sc, reg, x) \ 285 CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) | (x)) 286 287 #define DC_CLRBIT(sc, reg, x) \ 288 CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) & ~(x)) 289 290 #define SIO_SET(x) DC_SETBIT(sc, DC_SIO, (x)) 291 #define SIO_CLR(x) DC_CLRBIT(sc, DC_SIO, (x)) 292 293 static void dc_delay(sc) 294 struct dc_softc *sc; 295 { 296 int idx; 297 298 for (idx = (300 / 33) + 1; idx > 0; idx--) 299 CSR_READ_4(sc, DC_BUSCTL); 300 } 301 302 static void dc_eeprom_idle(sc) 303 struct dc_softc *sc; 304 { 305 register int i; 306 307 CSR_WRITE_4(sc, DC_SIO, DC_SIO_EESEL); 308 dc_delay(sc); 309 DC_SETBIT(sc, DC_SIO, DC_SIO_ROMCTL_READ); 310 dc_delay(sc); 311 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); 312 dc_delay(sc); 313 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CS); 314 dc_delay(sc); 315 316 for (i = 0; i < 25; i++) { 317 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); 318 dc_delay(sc); 319 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CLK); 320 dc_delay(sc); 321 } 322 323 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); 324 dc_delay(sc); 325 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CS); 326 dc_delay(sc); 327 CSR_WRITE_4(sc, DC_SIO, 0x00000000); 328 329 return; 330 } 331 332 /* 333 * Send a read command and address to the EEPROM, check for ACK. 334 */ 335 static void dc_eeprom_putbyte(sc, addr) 336 struct dc_softc *sc; 337 int addr; 338 { 339 register int d, i; 340 341 /* 342 * The AN985 has a 93C66 EEPROM on it instead of 343 * a 93C46. It uses a different bit sequence for 344 * specifying the "read" opcode. 345 */ 346 if (DC_IS_CENTAUR(sc)) 347 d = addr | (DC_EECMD_READ << 2); 348 else 349 d = addr | DC_EECMD_READ; 350 351 /* 352 * Feed in each bit and strobe the clock. 353 */ 354 for (i = 0x400; i; i >>= 1) { 355 if (d & i) { 356 SIO_SET(DC_SIO_EE_DATAIN); 357 } else { 358 SIO_CLR(DC_SIO_EE_DATAIN); 359 } 360 dc_delay(sc); 361 SIO_SET(DC_SIO_EE_CLK); 362 dc_delay(sc); 363 SIO_CLR(DC_SIO_EE_CLK); 364 dc_delay(sc); 365 } 366 367 return; 368 } 369 370 /* 371 * Read a word of data stored in the EEPROM at address 'addr.' 372 * The PNIC 82c168/82c169 has its own non-standard way to read 373 * the EEPROM. 374 */ 375 static void dc_eeprom_getword_pnic(sc, addr, dest) 376 struct dc_softc *sc; 377 int addr; 378 u_int16_t *dest; 379 { 380 register int i; 381 u_int32_t r; 382 383 CSR_WRITE_4(sc, DC_PN_SIOCTL, DC_PN_EEOPCODE_READ|addr); 384 385 for (i = 0; i < DC_TIMEOUT; i++) { 386 DELAY(1); 387 r = CSR_READ_4(sc, DC_SIO); 388 if (!(r & DC_PN_SIOCTL_BUSY)) { 389 *dest = (u_int16_t)(r & 0xFFFF); 390 return; 391 } 392 } 393 394 return; 395 } 396 397 /* 398 * Read a word of data stored in the EEPROM at address 'addr.' 399 */ 400 static void dc_eeprom_getword(sc, addr, dest) 401 struct dc_softc *sc; 402 int addr; 403 u_int16_t *dest; 404 { 405 register int i; 406 u_int16_t word = 0; 407 408 /* Force EEPROM to idle state. */ 409 dc_eeprom_idle(sc); 410 411 /* Enter EEPROM access mode. */ 412 CSR_WRITE_4(sc, DC_SIO, DC_SIO_EESEL); 413 dc_delay(sc); 414 DC_SETBIT(sc, DC_SIO, DC_SIO_ROMCTL_READ); 415 dc_delay(sc); 416 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); 417 dc_delay(sc); 418 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CS); 419 dc_delay(sc); 420 421 /* 422 * Send address of word we want to read. 423 */ 424 dc_eeprom_putbyte(sc, addr); 425 426 /* 427 * Start reading bits from EEPROM. 428 */ 429 for (i = 0x8000; i; i >>= 1) { 430 SIO_SET(DC_SIO_EE_CLK); 431 dc_delay(sc); 432 if (CSR_READ_4(sc, DC_SIO) & DC_SIO_EE_DATAOUT) 433 word |= i; 434 dc_delay(sc); 435 SIO_CLR(DC_SIO_EE_CLK); 436 dc_delay(sc); 437 } 438 439 /* Turn off EEPROM access mode. */ 440 dc_eeprom_idle(sc); 441 442 *dest = word; 443 444 return; 445 } 446 447 /* 448 * Read a sequence of words from the EEPROM. 449 */ 450 static void dc_read_eeprom(sc, dest, off, cnt, swap) 451 struct dc_softc *sc; 452 caddr_t dest; 453 int off; 454 int cnt; 455 int swap; 456 { 457 int i; 458 u_int16_t word = 0, *ptr; 459 460 for (i = 0; i < cnt; i++) { 461 if (DC_IS_PNIC(sc)) 462 dc_eeprom_getword_pnic(sc, off + i, &word); 463 else 464 dc_eeprom_getword(sc, off + i, &word); 465 ptr = (u_int16_t *)(dest + (i * 2)); 466 if (swap) 467 *ptr = ntohs(word); 468 else 469 *ptr = word; 470 } 471 472 return; 473 } 474 475 /* 476 * The following two routines are taken from the Macronix 98713 477 * Application Notes pp.19-21. 478 */ 479 /* 480 * Write a bit to the MII bus. 481 */ 482 static void dc_mii_writebit(sc, bit) 483 struct dc_softc *sc; 484 int bit; 485 { 486 if (bit) 487 CSR_WRITE_4(sc, DC_SIO, 488 DC_SIO_ROMCTL_WRITE|DC_SIO_MII_DATAOUT); 489 else 490 CSR_WRITE_4(sc, DC_SIO, DC_SIO_ROMCTL_WRITE); 491 492 DC_SETBIT(sc, DC_SIO, DC_SIO_MII_CLK); 493 DC_CLRBIT(sc, DC_SIO, DC_SIO_MII_CLK); 494 495 return; 496 } 497 498 /* 499 * Read a bit from the MII bus. 500 */ 501 static int dc_mii_readbit(sc) 502 struct dc_softc *sc; 503 { 504 CSR_WRITE_4(sc, DC_SIO, DC_SIO_ROMCTL_READ|DC_SIO_MII_DIR); 505 CSR_READ_4(sc, DC_SIO); 506 DC_SETBIT(sc, DC_SIO, DC_SIO_MII_CLK); 507 DC_CLRBIT(sc, DC_SIO, DC_SIO_MII_CLK); 508 if (CSR_READ_4(sc, DC_SIO) & DC_SIO_MII_DATAIN) 509 return(1); 510 511 return(0); 512 } 513 514 /* 515 * Sync the PHYs by setting data bit and strobing the clock 32 times. 516 */ 517 static void dc_mii_sync(sc) 518 struct dc_softc *sc; 519 { 520 register int i; 521 522 CSR_WRITE_4(sc, DC_SIO, DC_SIO_ROMCTL_WRITE); 523 524 for (i = 0; i < 32; i++) 525 dc_mii_writebit(sc, 1); 526 527 return; 528 } 529 530 /* 531 * Clock a series of bits through the MII. 532 */ 533 static void dc_mii_send(sc, bits, cnt) 534 struct dc_softc *sc; 535 u_int32_t bits; 536 int cnt; 537 { 538 int i; 539 540 for (i = (0x1 << (cnt - 1)); i; i >>= 1) 541 dc_mii_writebit(sc, bits & i); 542 } 543 544 /* 545 * Read an PHY register through the MII. 546 */ 547 static int dc_mii_readreg(sc, frame) 548 struct dc_softc *sc; 549 struct dc_mii_frame *frame; 550 551 { 552 int i, ack, s; 553 554 s = splimp(); 555 556 /* 557 * Set up frame for RX. 558 */ 559 frame->mii_stdelim = DC_MII_STARTDELIM; 560 frame->mii_opcode = DC_MII_READOP; 561 frame->mii_turnaround = 0; 562 frame->mii_data = 0; 563 564 /* 565 * Sync the PHYs. 566 */ 567 dc_mii_sync(sc); 568 569 /* 570 * Send command/address info. 571 */ 572 dc_mii_send(sc, frame->mii_stdelim, 2); 573 dc_mii_send(sc, frame->mii_opcode, 2); 574 dc_mii_send(sc, frame->mii_phyaddr, 5); 575 dc_mii_send(sc, frame->mii_regaddr, 5); 576 577 #ifdef notdef 578 /* Idle bit */ 579 dc_mii_writebit(sc, 1); 580 dc_mii_writebit(sc, 0); 581 #endif 582 583 /* Check for ack */ 584 ack = dc_mii_readbit(sc); 585 586 /* 587 * Now try reading data bits. If the ack failed, we still 588 * need to clock through 16 cycles to keep the PHY(s) in sync. 589 */ 590 if (ack) { 591 for(i = 0; i < 16; i++) { 592 dc_mii_readbit(sc); 593 } 594 goto fail; 595 } 596 597 for (i = 0x8000; i; i >>= 1) { 598 if (!ack) { 599 if (dc_mii_readbit(sc)) 600 frame->mii_data |= i; 601 } 602 } 603 604 fail: 605 606 dc_mii_writebit(sc, 0); 607 dc_mii_writebit(sc, 0); 608 609 splx(s); 610 611 if (ack) 612 return(1); 613 return(0); 614 } 615 616 /* 617 * Write to a PHY register through the MII. 618 */ 619 static int dc_mii_writereg(sc, frame) 620 struct dc_softc *sc; 621 struct dc_mii_frame *frame; 622 623 { 624 int s; 625 626 s = splimp(); 627 /* 628 * Set up frame for TX. 629 */ 630 631 frame->mii_stdelim = DC_MII_STARTDELIM; 632 frame->mii_opcode = DC_MII_WRITEOP; 633 frame->mii_turnaround = DC_MII_TURNAROUND; 634 635 /* 636 * Sync the PHYs. 637 */ 638 dc_mii_sync(sc); 639 640 dc_mii_send(sc, frame->mii_stdelim, 2); 641 dc_mii_send(sc, frame->mii_opcode, 2); 642 dc_mii_send(sc, frame->mii_phyaddr, 5); 643 dc_mii_send(sc, frame->mii_regaddr, 5); 644 dc_mii_send(sc, frame->mii_turnaround, 2); 645 dc_mii_send(sc, frame->mii_data, 16); 646 647 /* Idle bit. */ 648 dc_mii_writebit(sc, 0); 649 dc_mii_writebit(sc, 0); 650 651 splx(s); 652 653 return(0); 654 } 655 656 static int dc_miibus_readreg(dev, phy, reg) 657 device_t dev; 658 int phy, reg; 659 { 660 struct dc_mii_frame frame; 661 struct dc_softc *sc; 662 int i, rval, phy_reg; 663 664 sc = device_get_softc(dev); 665 bzero((char *)&frame, sizeof(frame)); 666 667 /* 668 * Note: both the AL981 and AN985 have internal PHYs, 669 * however the AL981 provides direct access to the PHY 670 * registers while the AN985 uses a serial MII interface. 671 * The AN985's MII interface is also buggy in that you 672 * can read from any MII address (0 to 31), but only address 1 673 * behaves normally. To deal with both cases, we pretend 674 * that the PHY is at MII address 1. 675 */ 676 if (DC_IS_ADMTEK(sc) && phy != DC_ADMTEK_PHYADDR) 677 return(0); 678 679 if (sc->dc_pmode == DC_PMODE_SYM) { 680 if (phy == (MII_NPHY - 1)) { 681 switch(reg) { 682 case MII_BMSR: 683 /* 684 * Fake something to make the probe 685 * code think there's a PHY here. 686 */ 687 return(BMSR_MEDIAMASK); 688 break; 689 case MII_PHYIDR1: 690 if (DC_IS_PNIC(sc)) 691 return(DC_VENDORID_LO); 692 return(DC_VENDORID_DEC); 693 break; 694 case MII_PHYIDR2: 695 if (DC_IS_PNIC(sc)) 696 return(DC_DEVICEID_82C168); 697 return(DC_DEVICEID_21143); 698 break; 699 default: 700 return(0); 701 break; 702 } 703 } else 704 return(0); 705 } 706 707 if (DC_IS_PNIC(sc)) { 708 CSR_WRITE_4(sc, DC_PN_MII, DC_PN_MIIOPCODE_READ | 709 (phy << 23) | (reg << 18)); 710 for (i = 0; i < DC_TIMEOUT; i++) { 711 DELAY(1); 712 rval = CSR_READ_4(sc, DC_PN_MII); 713 if (!(rval & DC_PN_MII_BUSY)) { 714 rval &= 0xFFFF; 715 return(rval == 0xFFFF ? 0 : rval); 716 } 717 } 718 return(0); 719 } 720 721 if (DC_IS_COMET(sc)) { 722 switch(reg) { 723 case MII_BMCR: 724 phy_reg = DC_AL_BMCR; 725 break; 726 case MII_BMSR: 727 phy_reg = DC_AL_BMSR; 728 break; 729 case MII_PHYIDR1: 730 phy_reg = DC_AL_VENID; 731 break; 732 case MII_PHYIDR2: 733 phy_reg = DC_AL_DEVID; 734 break; 735 case MII_ANAR: 736 phy_reg = DC_AL_ANAR; 737 break; 738 case MII_ANLPAR: 739 phy_reg = DC_AL_LPAR; 740 break; 741 case MII_ANER: 742 phy_reg = DC_AL_ANER; 743 break; 744 default: 745 printf("dc%d: phy_read: bad phy register %x\n", 746 sc->dc_unit, reg); 747 return(0); 748 break; 749 } 750 751 rval = CSR_READ_4(sc, phy_reg) & 0x0000FFFF; 752 753 if (rval == 0xFFFF) 754 return(0); 755 return(rval); 756 } 757 758 frame.mii_phyaddr = phy; 759 frame.mii_regaddr = reg; 760 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL); 761 dc_mii_readreg(sc, &frame); 762 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL); 763 764 return(frame.mii_data); 765 } 766 767 static int dc_miibus_writereg(dev, phy, reg, data) 768 device_t dev; 769 int phy, reg, data; 770 { 771 struct dc_softc *sc; 772 struct dc_mii_frame frame; 773 int i, phy_reg; 774 775 sc = device_get_softc(dev); 776 bzero((char *)&frame, sizeof(frame)); 777 778 if (DC_IS_ADMTEK(sc) && phy != DC_ADMTEK_PHYADDR) 779 return(0); 780 781 if (DC_IS_PNIC(sc)) { 782 CSR_WRITE_4(sc, DC_PN_MII, DC_PN_MIIOPCODE_WRITE | 783 (phy << 23) | (reg << 10) | data); 784 for (i = 0; i < DC_TIMEOUT; i++) { 785 if (!(CSR_READ_4(sc, DC_PN_MII) & DC_PN_MII_BUSY)) 786 break; 787 } 788 return(0); 789 } 790 791 if (DC_IS_COMET(sc)) { 792 switch(reg) { 793 case MII_BMCR: 794 phy_reg = DC_AL_BMCR; 795 break; 796 case MII_BMSR: 797 phy_reg = DC_AL_BMSR; 798 break; 799 case MII_PHYIDR1: 800 phy_reg = DC_AL_VENID; 801 break; 802 case MII_PHYIDR2: 803 phy_reg = DC_AL_DEVID; 804 break; 805 case MII_ANAR: 806 phy_reg = DC_AL_ANAR; 807 break; 808 case MII_ANLPAR: 809 phy_reg = DC_AL_LPAR; 810 break; 811 case MII_ANER: 812 phy_reg = DC_AL_ANER; 813 break; 814 default: 815 printf("dc%d: phy_write: bad phy register %x\n", 816 sc->dc_unit, reg); 817 return(0); 818 break; 819 } 820 821 CSR_WRITE_4(sc, phy_reg, data); 822 return(0); 823 } 824 825 frame.mii_phyaddr = phy; 826 frame.mii_regaddr = reg; 827 frame.mii_data = data; 828 829 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL); 830 dc_mii_writereg(sc, &frame); 831 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL); 832 833 return(0); 834 } 835 836 static void dc_miibus_statchg(dev) 837 device_t dev; 838 { 839 struct dc_softc *sc; 840 struct mii_data *mii; 841 842 sc = device_get_softc(dev); 843 if (DC_IS_ADMTEK(sc)) 844 return; 845 mii = device_get_softc(sc->dc_miibus); 846 dc_setcfg(sc, mii->mii_media_active); 847 sc->dc_if_media = mii->mii_media_active; 848 849 return; 850 } 851 852 #define DC_POLY 0xEDB88320 853 #define DC_BITS 9 854 #define DC_BITS_PNIC_II 7 855 856 static u_int32_t dc_crc_le(sc, addr) 857 struct dc_softc *sc; 858 caddr_t addr; 859 { 860 u_int32_t idx, bit, data, crc; 861 862 /* Compute CRC for the address value. */ 863 crc = 0xFFFFFFFF; /* initial value */ 864 865 for (idx = 0; idx < 6; idx++) { 866 for (data = *addr++, bit = 0; bit < 8; bit++, data >>= 1) 867 crc = (crc >> 1) ^ (((crc ^ data) & 1) ? DC_POLY : 0); 868 } 869 870 /* The hash table on the PNIC II is only 128 bits wide. */ 871 if (DC_IS_PNICII(sc)) 872 return (crc & ((1 << DC_BITS_PNIC_II) - 1)); 873 874 return (crc & ((1 << DC_BITS) - 1)); 875 } 876 877 /* 878 * Calculate CRC of a multicast group address, return the lower 6 bits. 879 */ 880 static u_int32_t dc_crc_be(addr) 881 caddr_t addr; 882 { 883 u_int32_t crc, carry; 884 int i, j; 885 u_int8_t c; 886 887 /* Compute CRC for the address value. */ 888 crc = 0xFFFFFFFF; /* initial value */ 889 890 for (i = 0; i < 6; i++) { 891 c = *(addr + i); 892 for (j = 0; j < 8; j++) { 893 carry = ((crc & 0x80000000) ? 1 : 0) ^ (c & 0x01); 894 crc <<= 1; 895 c >>= 1; 896 if (carry) 897 crc = (crc ^ 0x04c11db6) | carry; 898 } 899 } 900 901 /* return the filter bit position */ 902 return((crc >> 26) & 0x0000003F); 903 } 904 905 /* 906 * 21143-style RX filter setup routine. Filter programming is done by 907 * downloading a special setup frame into the TX engine. 21143, Macronix, 908 * PNIC, PNIC II and Davicom chips are programmed this way. 909 * 910 * We always program the chip using 'hash perfect' mode, i.e. one perfect 911 * address (our node address) and a 512-bit hash filter for multicast 912 * frames. We also sneak the broadcast address into the hash filter since 913 * we need that too. 914 */ 915 void dc_setfilt_21143(sc) 916 struct dc_softc *sc; 917 { 918 struct dc_desc *sframe; 919 u_int32_t h, *sp; 920 struct ifmultiaddr *ifma; 921 struct ifnet *ifp; 922 int i; 923 924 ifp = &sc->arpcom.ac_if; 925 926 i = sc->dc_cdata.dc_tx_prod; 927 DC_INC(sc->dc_cdata.dc_tx_prod, DC_TX_LIST_CNT); 928 sc->dc_cdata.dc_tx_cnt++; 929 sframe = &sc->dc_ldata->dc_tx_list[i]; 930 sp = (u_int32_t *)&sc->dc_cdata.dc_sbuf; 931 bzero((char *)sp, DC_SFRAME_LEN); 932 933 sframe->dc_data = vtophys(&sc->dc_cdata.dc_sbuf); 934 sframe->dc_ctl = DC_SFRAME_LEN | DC_TXCTL_SETUP | DC_TXCTL_TLINK | 935 DC_FILTER_HASHPERF | DC_TXCTL_FINT; 936 937 sc->dc_cdata.dc_tx_chain[i] = (struct mbuf *)&sc->dc_cdata.dc_sbuf; 938 939 /* If we want promiscuous mode, set the allframes bit. */ 940 if (ifp->if_flags & IFF_PROMISC) 941 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC); 942 else 943 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC); 944 945 if (ifp->if_flags & IFF_ALLMULTI) 946 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI); 947 else 948 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI); 949 950 for (ifma = ifp->if_multiaddrs.lh_first; ifma != NULL; 951 ifma = ifma->ifma_link.le_next) { 952 if (ifma->ifma_addr->sa_family != AF_LINK) 953 continue; 954 h = dc_crc_le(sc, 955 LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 956 sp[h >> 4] |= 1 << (h & 0xF); 957 } 958 959 if (ifp->if_flags & IFF_BROADCAST) { 960 h = dc_crc_le(sc, (caddr_t)ðerbroadcastaddr); 961 sp[h >> 4] |= 1 << (h & 0xF); 962 } 963 964 /* Set our MAC address */ 965 sp[39] = ((u_int16_t *)sc->arpcom.ac_enaddr)[0]; 966 sp[40] = ((u_int16_t *)sc->arpcom.ac_enaddr)[1]; 967 sp[41] = ((u_int16_t *)sc->arpcom.ac_enaddr)[2]; 968 969 sframe->dc_status = DC_TXSTAT_OWN; 970 CSR_WRITE_4(sc, DC_TXSTART, 0xFFFFFFFF); 971 972 /* 973 * The PNIC takes an exceedingly long time to process its 974 * setup frame; wait 10ms after posting the setup frame 975 * before proceeding, just so it has time to swallow its 976 * medicine. 977 */ 978 DELAY(10000); 979 980 ifp->if_timer = 5; 981 982 return; 983 } 984 985 void dc_setfilt_admtek(sc) 986 struct dc_softc *sc; 987 { 988 struct ifnet *ifp; 989 int h = 0; 990 u_int32_t hashes[2] = { 0, 0 }; 991 struct ifmultiaddr *ifma; 992 993 ifp = &sc->arpcom.ac_if; 994 995 /* Init our MAC address */ 996 CSR_WRITE_4(sc, DC_AL_PAR0, *(u_int32_t *)(&sc->arpcom.ac_enaddr[0])); 997 CSR_WRITE_4(sc, DC_AL_PAR1, *(u_int32_t *)(&sc->arpcom.ac_enaddr[4])); 998 999 /* If we want promiscuous mode, set the allframes bit. */ 1000 if (ifp->if_flags & IFF_PROMISC) 1001 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC); 1002 else 1003 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC); 1004 1005 if (ifp->if_flags & IFF_ALLMULTI) 1006 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI); 1007 else 1008 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI); 1009 1010 /* first, zot all the existing hash bits */ 1011 CSR_WRITE_4(sc, DC_AL_MAR0, 0); 1012 CSR_WRITE_4(sc, DC_AL_MAR1, 0); 1013 1014 /* 1015 * If we're already in promisc or allmulti mode, we 1016 * don't have to bother programming the multicast filter. 1017 */ 1018 if (ifp->if_flags & (IFF_PROMISC|IFF_ALLMULTI)) 1019 return; 1020 1021 /* now program new ones */ 1022 for (ifma = ifp->if_multiaddrs.lh_first; ifma != NULL; 1023 ifma = ifma->ifma_link.le_next) { 1024 if (ifma->ifma_addr->sa_family != AF_LINK) 1025 continue; 1026 h = dc_crc_be(LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 1027 if (h < 32) 1028 hashes[0] |= (1 << h); 1029 else 1030 hashes[1] |= (1 << (h - 32)); 1031 } 1032 1033 CSR_WRITE_4(sc, DC_AL_MAR0, hashes[0]); 1034 CSR_WRITE_4(sc, DC_AL_MAR1, hashes[1]); 1035 1036 return; 1037 } 1038 1039 void dc_setfilt_asix(sc) 1040 struct dc_softc *sc; 1041 { 1042 struct ifnet *ifp; 1043 int h = 0; 1044 u_int32_t hashes[2] = { 0, 0 }; 1045 struct ifmultiaddr *ifma; 1046 1047 ifp = &sc->arpcom.ac_if; 1048 1049 /* Init our MAC address */ 1050 CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_PAR0); 1051 CSR_WRITE_4(sc, DC_AX_FILTDATA, 1052 *(u_int32_t *)(&sc->arpcom.ac_enaddr[0])); 1053 CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_PAR1); 1054 CSR_WRITE_4(sc, DC_AX_FILTDATA, 1055 *(u_int32_t *)(&sc->arpcom.ac_enaddr[4])); 1056 1057 /* If we want promiscuous mode, set the allframes bit. */ 1058 if (ifp->if_flags & IFF_PROMISC) 1059 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC); 1060 else 1061 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC); 1062 1063 if (ifp->if_flags & IFF_ALLMULTI) 1064 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI); 1065 else 1066 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI); 1067 1068 /* 1069 * The ASIX chip has a special bit to enable reception 1070 * of broadcast frames. 1071 */ 1072 if (ifp->if_flags & IFF_BROADCAST) 1073 DC_SETBIT(sc, DC_NETCFG, DC_AX_NETCFG_RX_BROAD); 1074 else 1075 DC_CLRBIT(sc, DC_NETCFG, DC_AX_NETCFG_RX_BROAD); 1076 1077 /* first, zot all the existing hash bits */ 1078 CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_MAR0); 1079 CSR_WRITE_4(sc, DC_AX_FILTDATA, 0); 1080 CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_MAR1); 1081 CSR_WRITE_4(sc, DC_AX_FILTDATA, 0); 1082 1083 /* 1084 * If we're already in promisc or allmulti mode, we 1085 * don't have to bother programming the multicast filter. 1086 */ 1087 if (ifp->if_flags & (IFF_PROMISC|IFF_ALLMULTI)) 1088 return; 1089 1090 /* now program new ones */ 1091 for (ifma = ifp->if_multiaddrs.lh_first; ifma != NULL; 1092 ifma = ifma->ifma_link.le_next) { 1093 if (ifma->ifma_addr->sa_family != AF_LINK) 1094 continue; 1095 h = dc_crc_be(LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 1096 if (h < 32) 1097 hashes[0] |= (1 << h); 1098 else 1099 hashes[1] |= (1 << (h - 32)); 1100 } 1101 1102 CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_MAR0); 1103 CSR_WRITE_4(sc, DC_AX_FILTDATA, hashes[0]); 1104 CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_MAR1); 1105 CSR_WRITE_4(sc, DC_AX_FILTDATA, hashes[1]); 1106 1107 return; 1108 } 1109 1110 static void dc_setfilt(sc) 1111 struct dc_softc *sc; 1112 { 1113 if (DC_IS_INTEL(sc) || DC_IS_MACRONIX(sc) || DC_IS_PNIC(sc) || 1114 DC_IS_PNICII(sc) || DC_IS_DAVICOM(sc)) 1115 dc_setfilt_21143(sc); 1116 1117 if (DC_IS_ASIX(sc)) 1118 dc_setfilt_asix(sc); 1119 1120 if (DC_IS_ADMTEK(sc)) 1121 dc_setfilt_admtek(sc); 1122 1123 return; 1124 } 1125 1126 /* 1127 * In order to fiddle with the 1128 * 'full-duplex' and '100Mbps' bits in the netconfig register, we 1129 * first have to put the transmit and/or receive logic in the idle state. 1130 */ 1131 static void dc_setcfg(sc, media) 1132 struct dc_softc *sc; 1133 int media; 1134 { 1135 int i, restart = 0; 1136 u_int32_t isr; 1137 1138 if (IFM_SUBTYPE(media) == IFM_NONE) 1139 return; 1140 1141 if (CSR_READ_4(sc, DC_NETCFG) & (DC_NETCFG_TX_ON|DC_NETCFG_RX_ON)) { 1142 restart = 1; 1143 DC_CLRBIT(sc, DC_NETCFG, (DC_NETCFG_TX_ON|DC_NETCFG_RX_ON)); 1144 1145 for (i = 0; i < DC_TIMEOUT; i++) { 1146 DELAY(10); 1147 isr = CSR_READ_4(sc, DC_ISR); 1148 if (isr & DC_ISR_TX_IDLE || 1149 (isr & DC_ISR_RX_STATE) == DC_RXSTATE_STOPPED) 1150 break; 1151 } 1152 1153 if (i == DC_TIMEOUT) 1154 printf("dc%d: failed to force tx and " 1155 "rx to idle state\n", sc->dc_unit); 1156 1157 } 1158 1159 if (IFM_SUBTYPE(media) == IFM_100_TX) { 1160 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_SPEEDSEL); 1161 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_HEARTBEAT); 1162 if (sc->dc_pmode == DC_PMODE_MII) { 1163 DC_SETBIT(sc, DC_WATCHDOG, DC_WDOG_JABBERDIS); 1164 DC_CLRBIT(sc, DC_NETCFG, (DC_NETCFG_PCS| 1165 DC_NETCFG_PORTSEL|DC_NETCFG_SCRAMBLER)); 1166 if (sc->dc_type == DC_TYPE_98713) 1167 DC_SETBIT(sc, DC_NETCFG, (DC_NETCFG_PCS| 1168 DC_NETCFG_SCRAMBLER)); 1169 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL); 1170 DC_CLRBIT(sc, DC_10BTCTRL, 0xFFFF); 1171 } else { 1172 if (DC_IS_PNIC(sc)) { 1173 DC_PN_GPIO_SETBIT(sc, DC_PN_GPIO_SPEEDSEL); 1174 DC_PN_GPIO_SETBIT(sc, DC_PN_GPIO_100TX_LOOP); 1175 DC_SETBIT(sc, DC_PN_NWAY, DC_PN_NWAY_SPEEDSEL); 1176 } 1177 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL| 1178 DC_NETCFG_PCS|DC_NETCFG_SCRAMBLER); 1179 } 1180 } 1181 1182 if (IFM_SUBTYPE(media) == IFM_10_T) { 1183 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_SPEEDSEL); 1184 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_HEARTBEAT); 1185 if (sc->dc_pmode == DC_PMODE_MII) { 1186 DC_SETBIT(sc, DC_WATCHDOG, DC_WDOG_JABBERDIS); 1187 DC_CLRBIT(sc, DC_NETCFG, (DC_NETCFG_PCS| 1188 DC_NETCFG_PORTSEL|DC_NETCFG_SCRAMBLER)); 1189 if (sc->dc_type == DC_TYPE_98713) 1190 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PCS); 1191 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL); 1192 DC_CLRBIT(sc, DC_10BTCTRL, 0xFFFF); 1193 } else { 1194 if (DC_IS_PNIC(sc)) { 1195 DC_PN_GPIO_CLRBIT(sc, DC_PN_GPIO_SPEEDSEL); 1196 DC_PN_GPIO_SETBIT(sc, DC_PN_GPIO_100TX_LOOP); 1197 DC_CLRBIT(sc, DC_PN_NWAY, DC_PN_NWAY_SPEEDSEL); 1198 } 1199 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL); 1200 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_SCRAMBLER); 1201 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PCS); 1202 } 1203 } 1204 1205 if ((media & IFM_GMASK) == IFM_FDX) { 1206 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_FULLDUPLEX); 1207 if (sc->dc_pmode == DC_PMODE_SYM && DC_IS_PNIC(sc)) 1208 DC_SETBIT(sc, DC_PN_NWAY, DC_PN_NWAY_DUPLEX); 1209 } else { 1210 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_FULLDUPLEX); 1211 if (sc->dc_pmode == DC_PMODE_SYM && DC_IS_PNIC(sc)) 1212 DC_CLRBIT(sc, DC_PN_NWAY, DC_PN_NWAY_DUPLEX); 1213 } 1214 1215 if (restart) 1216 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_TX_ON|DC_NETCFG_RX_ON); 1217 1218 return; 1219 } 1220 1221 static void dc_reset(sc) 1222 struct dc_softc *sc; 1223 { 1224 register int i; 1225 1226 DC_SETBIT(sc, DC_BUSCTL, DC_BUSCTL_RESET); 1227 1228 for (i = 0; i < DC_TIMEOUT; i++) { 1229 DELAY(10); 1230 if (!(CSR_READ_4(sc, DC_BUSCTL) & DC_BUSCTL_RESET)) 1231 break; 1232 } 1233 1234 if (DC_IS_ASIX(sc) || DC_IS_ADMTEK(sc)) { 1235 DELAY(10000); 1236 DC_CLRBIT(sc, DC_BUSCTL, DC_BUSCTL_RESET); 1237 i = 0; 1238 } 1239 1240 if (i == DC_TIMEOUT) 1241 printf("dc%d: reset never completed!\n", sc->dc_unit); 1242 1243 /* Wait a little while for the chip to get its brains in order. */ 1244 DELAY(1000); 1245 1246 CSR_WRITE_4(sc, DC_IMR, 0x00000000); 1247 CSR_WRITE_4(sc, DC_BUSCTL, 0x00000000); 1248 CSR_WRITE_4(sc, DC_NETCFG, 0x00000000); 1249 1250 /* 1251 * Bring the SIA out of reset. In some cases, it looks 1252 * like failing to unreset the SIA soon enough gets it 1253 * into a state where it will never come out of reset 1254 * until we reset the whole chip again. 1255 */ 1256 if (DC_IS_INTEL(sc)) 1257 DC_SETBIT(sc, DC_SIARESET, DC_SIA_RESET); 1258 1259 return; 1260 } 1261 1262 static struct dc_type *dc_devtype(dev) 1263 device_t dev; 1264 { 1265 struct dc_type *t; 1266 u_int32_t rev; 1267 1268 t = dc_devs; 1269 1270 while(t->dc_name != NULL) { 1271 if ((pci_get_vendor(dev) == t->dc_vid) && 1272 (pci_get_device(dev) == t->dc_did)) { 1273 /* Check the PCI revision */ 1274 rev = pci_read_config(dev, DC_PCI_CFRV, 4) & 0xFF; 1275 if (t->dc_did == DC_DEVICEID_98713 && 1276 rev >= DC_REVISION_98713A) 1277 t++; 1278 if (t->dc_did == DC_DEVICEID_98713_CP && 1279 rev >= DC_REVISION_98713A) 1280 t++; 1281 if (t->dc_did == DC_DEVICEID_987x5 && 1282 rev >= DC_REVISION_98725) 1283 t++; 1284 if (t->dc_did == DC_DEVICEID_AX88140A && 1285 rev >= DC_REVISION_88141) 1286 t++; 1287 if (t->dc_did == DC_DEVICEID_82C168 && 1288 rev >= DC_REVISION_82C169) 1289 t++; 1290 return(t); 1291 } 1292 t++; 1293 } 1294 1295 return(NULL); 1296 } 1297 1298 /* 1299 * Probe for a 21143 or clone chip. Check the PCI vendor and device 1300 * IDs against our list and return a device name if we find a match. 1301 * We do a little bit of extra work to identify the exact type of 1302 * chip. The MX98713 and MX98713A have the same PCI vendor/device ID, 1303 * but different revision IDs. The same is true for 98715/98715A 1304 * chips and the 98725, as well as the ASIX and ADMtek chips. In some 1305 * cases, the exact chip revision affects driver behavior. 1306 */ 1307 static int dc_probe(dev) 1308 device_t dev; 1309 { 1310 struct dc_type *t; 1311 1312 t = dc_devtype(dev); 1313 1314 if (t != NULL) { 1315 device_set_desc(dev, t->dc_name); 1316 return(0); 1317 } 1318 1319 return(ENXIO); 1320 } 1321 1322 static void dc_acpi(dev) 1323 device_t dev; 1324 { 1325 u_int32_t r, cptr; 1326 int unit; 1327 1328 unit = device_get_unit(dev); 1329 1330 /* Find the location of the capabilities block */ 1331 cptr = pci_read_config(dev, DC_PCI_CCAP, 4) & 0xFF; 1332 1333 r = pci_read_config(dev, cptr, 4) & 0xFF; 1334 if (r == 0x01) { 1335 1336 r = pci_read_config(dev, cptr + 4, 4); 1337 if (r & DC_PSTATE_D3) { 1338 u_int32_t iobase, membase, irq; 1339 1340 /* Save important PCI config data. */ 1341 iobase = pci_read_config(dev, DC_PCI_CFBIO, 4); 1342 membase = pci_read_config(dev, DC_PCI_CFBMA, 4); 1343 irq = pci_read_config(dev, DC_PCI_CFIT, 4); 1344 1345 /* Reset the power state. */ 1346 printf("dc%d: chip is in D%d power mode " 1347 "-- setting to D0\n", unit, r & DC_PSTATE_D3); 1348 r &= 0xFFFFFFFC; 1349 pci_write_config(dev, cptr + 4, r, 4); 1350 1351 /* Restore PCI config data. */ 1352 pci_write_config(dev, DC_PCI_CFBIO, iobase, 4); 1353 pci_write_config(dev, DC_PCI_CFBMA, membase, 4); 1354 pci_write_config(dev, DC_PCI_CFIT, irq, 4); 1355 } 1356 } 1357 return; 1358 } 1359 1360 /* 1361 * Attach the interface. Allocate softc structures, do ifmedia 1362 * setup and ethernet/BPF attach. 1363 */ 1364 static int dc_attach(dev) 1365 device_t dev; 1366 { 1367 int s; 1368 u_char eaddr[ETHER_ADDR_LEN]; 1369 u_int32_t command; 1370 struct dc_softc *sc; 1371 struct ifnet *ifp; 1372 u_int32_t revision; 1373 int unit, error = 0, rid, mac_offset; 1374 1375 s = splimp(); 1376 1377 sc = device_get_softc(dev); 1378 unit = device_get_unit(dev); 1379 bzero(sc, sizeof(struct dc_softc)); 1380 1381 /* 1382 * Handle power management nonsense. 1383 */ 1384 dc_acpi(dev); 1385 1386 /* 1387 * Map control/status registers. 1388 */ 1389 command = pci_read_config(dev, PCI_COMMAND_STATUS_REG, 4); 1390 command |= (PCIM_CMD_PORTEN|PCIM_CMD_MEMEN|PCIM_CMD_BUSMASTEREN); 1391 pci_write_config(dev, PCI_COMMAND_STATUS_REG, command, 4); 1392 command = pci_read_config(dev, PCI_COMMAND_STATUS_REG, 4); 1393 1394 #ifdef DC_USEIOSPACE 1395 if (!(command & PCIM_CMD_PORTEN)) { 1396 printf("dc%d: failed to enable I/O ports!\n", unit); 1397 error = ENXIO; 1398 goto fail; 1399 } 1400 #else 1401 if (!(command & PCIM_CMD_MEMEN)) { 1402 printf("dc%d: failed to enable memory mapping!\n", unit); 1403 error = ENXIO; 1404 goto fail; 1405 } 1406 #endif 1407 1408 rid = DC_RID; 1409 sc->dc_res = bus_alloc_resource(dev, DC_RES, &rid, 1410 0, ~0, 1, RF_ACTIVE); 1411 1412 if (sc->dc_res == NULL) { 1413 printf("dc%d: couldn't map ports/memory\n", unit); 1414 error = ENXIO; 1415 goto fail; 1416 } 1417 1418 sc->dc_btag = rman_get_bustag(sc->dc_res); 1419 sc->dc_bhandle = rman_get_bushandle(sc->dc_res); 1420 1421 /* Allocate interrupt */ 1422 rid = 0; 1423 sc->dc_irq = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, 0, ~0, 1, 1424 RF_SHAREABLE | RF_ACTIVE); 1425 1426 if (sc->dc_irq == NULL) { 1427 printf("dc%d: couldn't map interrupt\n", unit); 1428 bus_release_resource(dev, DC_RES, DC_RID, sc->dc_res); 1429 error = ENXIO; 1430 goto fail; 1431 } 1432 1433 error = bus_setup_intr(dev, sc->dc_irq, INTR_TYPE_NET, 1434 dc_intr, sc, &sc->dc_intrhand); 1435 1436 if (error) { 1437 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->dc_irq); 1438 bus_release_resource(dev, DC_RES, DC_RID, sc->dc_res); 1439 printf("dc%d: couldn't set up irq\n", unit); 1440 goto fail; 1441 } 1442 1443 /* Need this info to decide on a chip type. */ 1444 sc->dc_info = dc_devtype(dev); 1445 revision = pci_read_config(dev, DC_PCI_CFRV, 4) & 0x000000FF; 1446 1447 switch(sc->dc_info->dc_did) { 1448 case DC_DEVICEID_21143: 1449 sc->dc_type = DC_TYPE_21143; 1450 sc->dc_flags |= DC_TX_POLL|DC_TX_USE_TX_INTR; 1451 sc->dc_flags |= DC_REDUCED_MII_POLL; 1452 break; 1453 case DC_DEVICEID_DM9100: 1454 case DC_DEVICEID_DM9102: 1455 sc->dc_type = DC_TYPE_DM9102; 1456 sc->dc_flags |= DC_TX_USE_TX_INTR; 1457 sc->dc_flags |= DC_REDUCED_MII_POLL; 1458 sc->dc_pmode = DC_PMODE_MII; 1459 break; 1460 case DC_DEVICEID_AL981: 1461 sc->dc_type = DC_TYPE_AL981; 1462 sc->dc_flags |= DC_TX_USE_TX_INTR; 1463 sc->dc_flags |= DC_TX_ADMTEK_WAR; 1464 sc->dc_pmode = DC_PMODE_MII; 1465 break; 1466 case DC_DEVICEID_AN985: 1467 sc->dc_type = DC_TYPE_AN985; 1468 sc->dc_flags |= DC_TX_USE_TX_INTR; 1469 sc->dc_flags |= DC_TX_ADMTEK_WAR; 1470 sc->dc_pmode = DC_PMODE_MII; 1471 break; 1472 case DC_DEVICEID_98713: 1473 case DC_DEVICEID_98713_CP: 1474 if (revision < DC_REVISION_98713A) { 1475 sc->dc_type = DC_TYPE_98713; 1476 sc->dc_flags |= DC_REDUCED_MII_POLL; 1477 } 1478 if (revision >= DC_REVISION_98713A) 1479 sc->dc_type = DC_TYPE_98713A; 1480 sc->dc_flags |= DC_TX_POLL|DC_TX_USE_TX_INTR; 1481 break; 1482 case DC_DEVICEID_987x5: 1483 sc->dc_type = DC_TYPE_987x5; 1484 sc->dc_flags |= DC_TX_POLL|DC_TX_USE_TX_INTR; 1485 break; 1486 case DC_DEVICEID_82C115: 1487 sc->dc_type = DC_TYPE_PNICII; 1488 sc->dc_flags |= DC_TX_POLL|DC_TX_USE_TX_INTR; 1489 break; 1490 case DC_DEVICEID_82C168: 1491 sc->dc_type = DC_TYPE_PNIC; 1492 sc->dc_flags |= DC_TX_STORENFWD|DC_TX_INTR_ALWAYS; 1493 sc->dc_flags |= DC_PNIC_RX_BUG_WAR; 1494 sc->dc_pnic_rx_buf = malloc(DC_RXLEN * 5, M_DEVBUF, M_NOWAIT); 1495 if (revision < DC_REVISION_82C169) 1496 sc->dc_pmode = DC_PMODE_SYM; 1497 break; 1498 case DC_DEVICEID_AX88140A: 1499 sc->dc_type = DC_TYPE_ASIX; 1500 sc->dc_flags |= DC_TX_USE_TX_INTR|DC_TX_INTR_FIRSTFRAG; 1501 sc->dc_flags |= DC_REDUCED_MII_POLL; 1502 sc->dc_pmode = DC_PMODE_MII; 1503 break; 1504 default: 1505 printf("dc%d: unknown device: %x\n", sc->dc_unit, 1506 sc->dc_info->dc_did); 1507 break; 1508 } 1509 1510 /* Save the cache line size. */ 1511 sc->dc_cachesize = pci_read_config(dev, DC_PCI_CFLT, 4) & 0xFF; 1512 1513 /* Reset the adapter. */ 1514 dc_reset(sc); 1515 1516 /* Take 21143 out of snooze mode */ 1517 if (DC_IS_INTEL(sc)) { 1518 command = pci_read_config(dev, DC_PCI_CFDD, 4); 1519 command &= ~(DC_CFDD_SNOOZE_MODE|DC_CFDD_SLEEP_MODE); 1520 pci_write_config(dev, DC_PCI_CFDD, command, 4); 1521 } 1522 1523 /* 1524 * Try to learn something about the supported media. 1525 * We know that ASIX and ADMtek and Davicom devices 1526 * will *always* be using MII media, so that's a no-brainer. 1527 * The tricky ones are the Macronix/PNIC II and the 1528 * Intel 21143. 1529 */ 1530 if (DC_IS_INTEL(sc)) { 1531 u_int32_t media, cwuc; 1532 cwuc = pci_read_config(dev, DC_PCI_CWUC, 4); 1533 cwuc |= DC_CWUC_FORCE_WUL; 1534 pci_write_config(dev, DC_PCI_CWUC, cwuc, 4); 1535 DELAY(10000); 1536 media = pci_read_config(dev, DC_PCI_CWUC, 4); 1537 cwuc &= ~DC_CWUC_FORCE_WUL; 1538 pci_write_config(dev, DC_PCI_CWUC, cwuc, 4); 1539 DELAY(10000); 1540 if (media & DC_CWUC_MII_ABILITY) 1541 sc->dc_pmode = DC_PMODE_MII; 1542 if (media & DC_CWUC_SYM_ABILITY) 1543 sc->dc_pmode = DC_PMODE_SYM; 1544 /* 1545 * If none of the bits are set, then this NIC 1546 * isn't meant to support 'wake up LAN' mode. 1547 * This is usually only the case on multiport 1548 * cards, and these cards almost always have 1549 * MII transceivers. 1550 */ 1551 if (media == 0) 1552 sc->dc_pmode = DC_PMODE_MII; 1553 } else if (DC_IS_MACRONIX(sc) || DC_IS_PNICII(sc)) { 1554 if (sc->dc_type == DC_TYPE_98713) 1555 sc->dc_pmode = DC_PMODE_MII; 1556 else 1557 sc->dc_pmode = DC_PMODE_SYM; 1558 } else if (!sc->dc_pmode) 1559 sc->dc_pmode = DC_PMODE_MII; 1560 1561 /* 1562 * Get station address from the EEPROM. 1563 */ 1564 switch(sc->dc_type) { 1565 case DC_TYPE_98713: 1566 case DC_TYPE_98713A: 1567 case DC_TYPE_987x5: 1568 case DC_TYPE_PNICII: 1569 dc_read_eeprom(sc, (caddr_t)&mac_offset, 1570 (DC_EE_NODEADDR_OFFSET / 2), 1, 0); 1571 dc_read_eeprom(sc, (caddr_t)&eaddr, (mac_offset / 2), 3, 0); 1572 break; 1573 case DC_TYPE_PNIC: 1574 dc_read_eeprom(sc, (caddr_t)&eaddr, 0, 3, 1); 1575 break; 1576 case DC_TYPE_DM9102: 1577 case DC_TYPE_21143: 1578 case DC_TYPE_ASIX: 1579 dc_read_eeprom(sc, (caddr_t)&eaddr, DC_EE_NODEADDR, 3, 0); 1580 break; 1581 case DC_TYPE_AL981: 1582 case DC_TYPE_AN985: 1583 dc_read_eeprom(sc, (caddr_t)&eaddr, DC_AL_EE_NODEADDR, 3, 0); 1584 break; 1585 default: 1586 dc_read_eeprom(sc, (caddr_t)&eaddr, DC_EE_NODEADDR, 3, 0); 1587 break; 1588 } 1589 1590 /* 1591 * A 21143 or clone chip was detected. Inform the world. 1592 */ 1593 printf("dc%d: Ethernet address: %6D\n", unit, eaddr, ":"); 1594 1595 sc->dc_unit = unit; 1596 bcopy(eaddr, (char *)&sc->arpcom.ac_enaddr, ETHER_ADDR_LEN); 1597 1598 sc->dc_ldata = contigmalloc(sizeof(struct dc_list_data), M_DEVBUF, 1599 M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0); 1600 1601 if (sc->dc_ldata == NULL) { 1602 printf("dc%d: no memory for list buffers!\n", unit); 1603 bus_teardown_intr(dev, sc->dc_irq, sc->dc_intrhand); 1604 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->dc_irq); 1605 bus_release_resource(dev, DC_RES, DC_RID, sc->dc_res); 1606 error = ENXIO; 1607 goto fail; 1608 } 1609 1610 bzero(sc->dc_ldata, sizeof(struct dc_list_data)); 1611 1612 ifp = &sc->arpcom.ac_if; 1613 ifp->if_softc = sc; 1614 ifp->if_unit = unit; 1615 ifp->if_name = "dc"; 1616 ifp->if_mtu = ETHERMTU; 1617 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 1618 ifp->if_ioctl = dc_ioctl; 1619 ifp->if_output = ether_output; 1620 ifp->if_start = dc_start; 1621 ifp->if_watchdog = dc_watchdog; 1622 ifp->if_init = dc_init; 1623 ifp->if_baudrate = 10000000; 1624 ifp->if_snd.ifq_maxlen = DC_TX_LIST_CNT - 1; 1625 1626 /* 1627 * Do MII setup. 1628 */ 1629 error = mii_phy_probe(dev, &sc->dc_miibus, 1630 dc_ifmedia_upd, dc_ifmedia_sts); 1631 1632 if (error && DC_IS_INTEL(sc)) { 1633 sc->dc_pmode = DC_PMODE_SYM; 1634 mii_phy_probe(dev, &sc->dc_miibus, 1635 dc_ifmedia_upd, dc_ifmedia_sts); 1636 error = 0; 1637 } 1638 1639 if (error) { 1640 printf("dc%d: MII without any PHY!\n", sc->dc_unit); 1641 bus_teardown_intr(dev, sc->dc_irq, sc->dc_intrhand); 1642 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->dc_irq); 1643 bus_release_resource(dev, DC_RES, DC_RID, sc->dc_res); 1644 error = ENXIO; 1645 goto fail; 1646 } 1647 1648 /* 1649 * Call MI attach routines. 1650 */ 1651 if_attach(ifp); 1652 ether_ifattach(ifp); 1653 callout_handle_init(&sc->dc_stat_ch); 1654 1655 bpfattach(ifp, DLT_EN10MB, sizeof(struct ether_header)); 1656 1657 fail: 1658 splx(s); 1659 1660 return(error); 1661 } 1662 1663 static int dc_detach(dev) 1664 device_t dev; 1665 { 1666 struct dc_softc *sc; 1667 struct ifnet *ifp; 1668 int s; 1669 1670 s = splimp(); 1671 1672 sc = device_get_softc(dev); 1673 ifp = &sc->arpcom.ac_if; 1674 1675 dc_stop(sc); 1676 if_detach(ifp); 1677 1678 bus_generic_detach(dev); 1679 device_delete_child(dev, sc->dc_miibus); 1680 1681 bus_teardown_intr(dev, sc->dc_irq, sc->dc_intrhand); 1682 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->dc_irq); 1683 bus_release_resource(dev, DC_RES, DC_RID, sc->dc_res); 1684 1685 contigfree(sc->dc_ldata, sizeof(struct dc_list_data), M_DEVBUF); 1686 if (sc->dc_pnic_rx_buf != NULL) 1687 free(sc->dc_pnic_rx_buf, M_DEVBUF); 1688 1689 splx(s); 1690 1691 return(0); 1692 } 1693 1694 /* 1695 * Initialize the transmit descriptors. 1696 */ 1697 static int dc_list_tx_init(sc) 1698 struct dc_softc *sc; 1699 { 1700 struct dc_chain_data *cd; 1701 struct dc_list_data *ld; 1702 int i; 1703 1704 cd = &sc->dc_cdata; 1705 ld = sc->dc_ldata; 1706 for (i = 0; i < DC_TX_LIST_CNT; i++) { 1707 if (i == (DC_TX_LIST_CNT - 1)) { 1708 ld->dc_tx_list[i].dc_next = 1709 vtophys(&ld->dc_tx_list[0]); 1710 } else { 1711 ld->dc_tx_list[i].dc_next = 1712 vtophys(&ld->dc_tx_list[i + 1]); 1713 } 1714 cd->dc_tx_chain[i] = NULL; 1715 ld->dc_tx_list[i].dc_data = 0; 1716 ld->dc_tx_list[i].dc_ctl = 0; 1717 } 1718 1719 cd->dc_tx_prod = cd->dc_tx_cons = cd->dc_tx_cnt = 0; 1720 1721 return(0); 1722 } 1723 1724 1725 /* 1726 * Initialize the RX descriptors and allocate mbufs for them. Note that 1727 * we arrange the descriptors in a closed ring, so that the last descriptor 1728 * points back to the first. 1729 */ 1730 static int dc_list_rx_init(sc) 1731 struct dc_softc *sc; 1732 { 1733 struct dc_chain_data *cd; 1734 struct dc_list_data *ld; 1735 int i; 1736 1737 cd = &sc->dc_cdata; 1738 ld = sc->dc_ldata; 1739 1740 for (i = 0; i < DC_RX_LIST_CNT; i++) { 1741 if (dc_newbuf(sc, i, NULL) == ENOBUFS) 1742 return(ENOBUFS); 1743 if (i == (DC_RX_LIST_CNT - 1)) { 1744 ld->dc_rx_list[i].dc_next = 1745 vtophys(&ld->dc_rx_list[0]); 1746 } else { 1747 ld->dc_rx_list[i].dc_next = 1748 vtophys(&ld->dc_rx_list[i + 1]); 1749 } 1750 } 1751 1752 cd->dc_rx_prod = 0; 1753 1754 return(0); 1755 } 1756 1757 /* 1758 * Initialize an RX descriptor and attach an MBUF cluster. 1759 */ 1760 static int dc_newbuf(sc, i, m) 1761 struct dc_softc *sc; 1762 int i; 1763 struct mbuf *m; 1764 { 1765 struct mbuf *m_new = NULL; 1766 struct dc_desc *c; 1767 1768 c = &sc->dc_ldata->dc_rx_list[i]; 1769 1770 if (m == NULL) { 1771 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 1772 if (m_new == NULL) { 1773 printf("dc%d: no memory for rx list " 1774 "-- packet dropped!\n", sc->dc_unit); 1775 return(ENOBUFS); 1776 } 1777 1778 MCLGET(m_new, M_DONTWAIT); 1779 if (!(m_new->m_flags & M_EXT)) { 1780 printf("dc%d: no memory for rx list " 1781 "-- packet dropped!\n", sc->dc_unit); 1782 m_freem(m_new); 1783 return(ENOBUFS); 1784 } 1785 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 1786 } else { 1787 m_new = m; 1788 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 1789 m_new->m_data = m_new->m_ext.ext_buf; 1790 } 1791 1792 m_adj(m_new, sizeof(u_int64_t)); 1793 1794 /* 1795 * If this is a PNIC chip, zero the buffer. This is part 1796 * of the workaround for the receive bug in the 82c168 and 1797 * 82c169 chips. 1798 */ 1799 if (sc->dc_flags & DC_PNIC_RX_BUG_WAR) 1800 bzero((char *)mtod(m_new, char *), m_new->m_len); 1801 1802 sc->dc_cdata.dc_rx_chain[i] = m_new; 1803 c->dc_data = vtophys(mtod(m_new, caddr_t)); 1804 c->dc_ctl = DC_RXCTL_RLINK | DC_RXLEN; 1805 c->dc_status = DC_RXSTAT_OWN; 1806 1807 return(0); 1808 } 1809 1810 /* 1811 * Grrrrr. 1812 * The PNIC chip has a terrible bug in it that manifests itself during 1813 * periods of heavy activity. The exact mode of failure if difficult to 1814 * pinpoint: sometimes it only happens in promiscuous mode, sometimes it 1815 * will happen on slow machines. The bug is that sometimes instead of 1816 * uploading one complete frame during reception, it uploads what looks 1817 * like the entire contents of its FIFO memory. The frame we want is at 1818 * the end of the whole mess, but we never know exactly how much data has 1819 * been uploaded, so salvaging the frame is hard. 1820 * 1821 * There is only one way to do it reliably, and it's disgusting. 1822 * Here's what we know: 1823 * 1824 * - We know there will always be somewhere between one and three extra 1825 * descriptors uploaded. 1826 * 1827 * - We know the desired received frame will always be at the end of the 1828 * total data upload. 1829 * 1830 * - We know the size of the desired received frame because it will be 1831 * provided in the length field of the status word in the last descriptor. 1832 * 1833 * Here's what we do: 1834 * 1835 * - When we allocate buffers for the receive ring, we bzero() them. 1836 * This means that we know that the buffer contents should be all 1837 * zeros, except for data uploaded by the chip. 1838 * 1839 * - We also force the PNIC chip to upload frames that include the 1840 * ethernet CRC at the end. 1841 * 1842 * - We gather all of the bogus frame data into a single buffer. 1843 * 1844 * - We then position a pointer at the end of this buffer and scan 1845 * backwards until we encounter the first non-zero byte of data. 1846 * This is the end of the received frame. We know we will encounter 1847 * some data at the end of the frame because the CRC will always be 1848 * there, so even if the sender transmits a packet of all zeros, 1849 * we won't be fooled. 1850 * 1851 * - We know the size of the actual received frame, so we subtract 1852 * that value from the current pointer location. This brings us 1853 * to the start of the actual received packet. 1854 * 1855 * - We copy this into an mbuf and pass it on, along with the actual 1856 * frame length. 1857 * 1858 * The performance hit is tremendous, but it beats dropping frames all 1859 * the time. 1860 */ 1861 1862 #define DC_WHOLEFRAME (DC_RXSTAT_FIRSTFRAG|DC_RXSTAT_LASTFRAG) 1863 static void dc_pnic_rx_bug_war(sc, idx) 1864 struct dc_softc *sc; 1865 int idx; 1866 { 1867 struct dc_desc *cur_rx; 1868 struct dc_desc *c = NULL; 1869 struct mbuf *m = NULL; 1870 unsigned char *ptr; 1871 int i, total_len; 1872 u_int32_t rxstat = 0; 1873 1874 i = sc->dc_pnic_rx_bug_save; 1875 cur_rx = &sc->dc_ldata->dc_rx_list[idx]; 1876 ptr = sc->dc_pnic_rx_buf; 1877 bzero(ptr, sizeof(DC_RXLEN * 5)); 1878 1879 /* Copy all the bytes from the bogus buffers. */ 1880 while (1) { 1881 c = &sc->dc_ldata->dc_rx_list[i]; 1882 rxstat = c->dc_status; 1883 m = sc->dc_cdata.dc_rx_chain[i]; 1884 bcopy(mtod(m, char *), ptr, DC_RXLEN); 1885 ptr += DC_RXLEN; 1886 /* If this is the last buffer, break out. */ 1887 if (i == idx || rxstat & DC_RXSTAT_LASTFRAG) 1888 break; 1889 dc_newbuf(sc, i, m); 1890 DC_INC(i, DC_RX_LIST_CNT); 1891 } 1892 1893 /* Find the length of the actual receive frame. */ 1894 total_len = DC_RXBYTES(rxstat); 1895 1896 /* Scan backwards until we hit a non-zero byte. */ 1897 while(*ptr == 0x00) 1898 ptr--; 1899 1900 /* Round off. */ 1901 if ((uintptr_t)(ptr) & 0x3) 1902 ptr -= 1; 1903 1904 /* Now find the start of the frame. */ 1905 ptr -= total_len; 1906 if (ptr < sc->dc_pnic_rx_buf) 1907 ptr = sc->dc_pnic_rx_buf; 1908 1909 /* 1910 * Now copy the salvaged frame to the last mbuf and fake up 1911 * the status word to make it look like a successful 1912 * frame reception. 1913 */ 1914 dc_newbuf(sc, i, m); 1915 bcopy(ptr, mtod(m, char *), total_len); 1916 cur_rx->dc_status = rxstat | DC_RXSTAT_FIRSTFRAG; 1917 1918 return; 1919 } 1920 1921 /* 1922 * A frame has been uploaded: pass the resulting mbuf chain up to 1923 * the higher level protocols. 1924 */ 1925 static void dc_rxeof(sc) 1926 struct dc_softc *sc; 1927 { 1928 struct ether_header *eh; 1929 struct mbuf *m; 1930 struct ifnet *ifp; 1931 struct dc_desc *cur_rx; 1932 int i, total_len = 0; 1933 u_int32_t rxstat; 1934 1935 ifp = &sc->arpcom.ac_if; 1936 i = sc->dc_cdata.dc_rx_prod; 1937 1938 while(!(sc->dc_ldata->dc_rx_list[i].dc_status & DC_RXSTAT_OWN)) { 1939 struct mbuf *m0 = NULL; 1940 1941 cur_rx = &sc->dc_ldata->dc_rx_list[i]; 1942 rxstat = cur_rx->dc_status; 1943 m = sc->dc_cdata.dc_rx_chain[i]; 1944 total_len = DC_RXBYTES(rxstat); 1945 1946 if (sc->dc_flags & DC_PNIC_RX_BUG_WAR) { 1947 if ((rxstat & DC_WHOLEFRAME) != DC_WHOLEFRAME) { 1948 if (rxstat & DC_RXSTAT_FIRSTFRAG) 1949 sc->dc_pnic_rx_bug_save = i; 1950 if ((rxstat & DC_RXSTAT_LASTFRAG) == 0) { 1951 DC_INC(i, DC_RX_LIST_CNT); 1952 continue; 1953 } 1954 dc_pnic_rx_bug_war(sc, i); 1955 rxstat = cur_rx->dc_status; 1956 total_len = DC_RXBYTES(rxstat); 1957 } 1958 } 1959 1960 sc->dc_cdata.dc_rx_chain[i] = NULL; 1961 1962 /* 1963 * If an error occurs, update stats, clear the 1964 * status word and leave the mbuf cluster in place: 1965 * it should simply get re-used next time this descriptor 1966 * comes up in the ring. 1967 */ 1968 if (rxstat & DC_RXSTAT_RXERR) { 1969 ifp->if_ierrors++; 1970 if (rxstat & DC_RXSTAT_COLLSEEN) 1971 ifp->if_collisions++; 1972 dc_newbuf(sc, i, m); 1973 if (rxstat & DC_RXSTAT_CRCERR) { 1974 DC_INC(i, DC_RX_LIST_CNT); 1975 continue; 1976 } else { 1977 dc_init(sc); 1978 return; 1979 } 1980 } 1981 1982 /* No errors; receive the packet. */ 1983 total_len -= ETHER_CRC_LEN; 1984 1985 m0 = m_devget(mtod(m, char *) - ETHER_ALIGN, 1986 total_len + ETHER_ALIGN, 0, ifp, NULL); 1987 dc_newbuf(sc, i, m); 1988 DC_INC(i, DC_RX_LIST_CNT); 1989 if (m0 == NULL) { 1990 ifp->if_ierrors++; 1991 continue; 1992 } 1993 m_adj(m0, ETHER_ALIGN); 1994 m = m0; 1995 1996 ifp->if_ipackets++; 1997 eh = mtod(m, struct ether_header *); 1998 1999 /* 2000 * Handle BPF listeners. Let the BPF user see the packet, but 2001 * don't pass it up to the ether_input() layer unless it's 2002 * a broadcast packet, multicast packet, matches our ethernet 2003 * address or the interface is in promiscuous mode. 2004 */ 2005 if (ifp->if_bpf) { 2006 bpf_mtap(ifp, m); 2007 if (ifp->if_flags & IFF_PROMISC && 2008 (bcmp(eh->ether_dhost, sc->arpcom.ac_enaddr, 2009 ETHER_ADDR_LEN) && 2010 (eh->ether_dhost[0] & 1) == 0)) { 2011 m_freem(m); 2012 continue; 2013 } 2014 } 2015 2016 /* Remove header from mbuf and pass it on. */ 2017 m_adj(m, sizeof(struct ether_header)); 2018 ether_input(ifp, eh, m); 2019 } 2020 2021 sc->dc_cdata.dc_rx_prod = i; 2022 2023 return; 2024 } 2025 2026 /* 2027 * A frame was downloaded to the chip. It's safe for us to clean up 2028 * the list buffers. 2029 */ 2030 2031 static void dc_txeof(sc) 2032 struct dc_softc *sc; 2033 { 2034 struct dc_desc *cur_tx = NULL; 2035 struct ifnet *ifp; 2036 int idx; 2037 2038 ifp = &sc->arpcom.ac_if; 2039 2040 /* Clear the timeout timer. */ 2041 ifp->if_timer = 0; 2042 2043 /* 2044 * Go through our tx list and free mbufs for those 2045 * frames that have been transmitted. 2046 */ 2047 idx = sc->dc_cdata.dc_tx_cons; 2048 while(idx != sc->dc_cdata.dc_tx_prod) { 2049 u_int32_t txstat; 2050 2051 cur_tx = &sc->dc_ldata->dc_tx_list[idx]; 2052 txstat = cur_tx->dc_status; 2053 2054 if (txstat & DC_TXSTAT_OWN) 2055 break; 2056 2057 if (!(cur_tx->dc_ctl & DC_TXCTL_LASTFRAG) || 2058 cur_tx->dc_ctl & DC_TXCTL_SETUP) { 2059 sc->dc_cdata.dc_tx_cnt--; 2060 if (cur_tx->dc_ctl & DC_TXCTL_SETUP) { 2061 /* 2062 * Yes, the PNIC is so brain damaged 2063 * that it will sometimes generate a TX 2064 * underrun error while DMAing the RX 2065 * filter setup frame. If we detect this, 2066 * we have to send the setup frame again, 2067 * or else the filter won't be programmed 2068 * correctly. 2069 */ 2070 if (DC_IS_PNIC(sc)) { 2071 if (txstat & DC_TXSTAT_ERRSUM) 2072 dc_setfilt(sc); 2073 } 2074 sc->dc_cdata.dc_tx_chain[idx] = NULL; 2075 } 2076 DC_INC(idx, DC_TX_LIST_CNT); 2077 continue; 2078 } 2079 2080 if (/*sc->dc_type == DC_TYPE_21143 &&*/ 2081 sc->dc_pmode == DC_PMODE_MII && 2082 ((txstat & 0xFFFF) & ~(DC_TXSTAT_ERRSUM| 2083 DC_TXSTAT_NOCARRIER|DC_TXSTAT_CARRLOST))) 2084 txstat &= ~DC_TXSTAT_ERRSUM; 2085 2086 if (txstat & DC_TXSTAT_ERRSUM) { 2087 ifp->if_oerrors++; 2088 if (txstat & DC_TXSTAT_EXCESSCOLL) 2089 ifp->if_collisions++; 2090 if (txstat & DC_TXSTAT_LATECOLL) 2091 ifp->if_collisions++; 2092 if (!(txstat & DC_TXSTAT_UNDERRUN)) { 2093 dc_init(sc); 2094 return; 2095 } 2096 } 2097 2098 ifp->if_collisions += (txstat & DC_TXSTAT_COLLCNT) >> 3; 2099 2100 ifp->if_opackets++; 2101 if (sc->dc_cdata.dc_tx_chain[idx] != NULL) { 2102 m_freem(sc->dc_cdata.dc_tx_chain[idx]); 2103 sc->dc_cdata.dc_tx_chain[idx] = NULL; 2104 } 2105 2106 sc->dc_cdata.dc_tx_cnt--; 2107 DC_INC(idx, DC_TX_LIST_CNT); 2108 } 2109 2110 sc->dc_cdata.dc_tx_cons = idx; 2111 if (cur_tx != NULL) 2112 ifp->if_flags &= ~IFF_OACTIVE; 2113 2114 return; 2115 } 2116 2117 static void dc_tick(xsc) 2118 void *xsc; 2119 { 2120 struct dc_softc *sc; 2121 struct mii_data *mii; 2122 struct ifnet *ifp; 2123 int s; 2124 u_int32_t r; 2125 2126 s = splimp(); 2127 2128 sc = xsc; 2129 ifp = &sc->arpcom.ac_if; 2130 mii = device_get_softc(sc->dc_miibus); 2131 2132 if (sc->dc_flags & DC_REDUCED_MII_POLL) { 2133 r = CSR_READ_4(sc, DC_ISR); 2134 if (DC_IS_INTEL(sc)) { 2135 if (r & DC_ISR_LINKFAIL) 2136 sc->dc_link = 0; 2137 if (sc->dc_link == 0) 2138 mii_tick(mii); 2139 } else { 2140 if ((r & DC_ISR_RX_STATE) == DC_RXSTATE_WAIT && 2141 sc->dc_cdata.dc_tx_prod == 0) 2142 mii_tick(mii); 2143 } 2144 } else 2145 mii_tick(mii); 2146 2147 /* 2148 * When the init routine completes, we expect to be able to send 2149 * packets right away, and in fact the network code will send a 2150 * gratuitous ARP the moment the init routine marks the interface 2151 * as running. However, even though the MAC may have been initialized, 2152 * there may be a delay of a few seconds before the PHY completes 2153 * autonegotiation and the link is brought up. Any transmissions 2154 * made during that delay will be lost. Dealing with this is tricky: 2155 * we can't just pause in the init routine while waiting for the 2156 * PHY to come ready since that would bring the whole system to 2157 * a screeching halt for several seconds. 2158 * 2159 * What we do here is prevent the TX start routine from sending 2160 * any packets until a link has been established. After the 2161 * interface has been initialized, the tick routine will poll 2162 * the state of the PHY until the IFM_ACTIVE flag is set. Until 2163 * that time, packets will stay in the send queue, and once the 2164 * link comes up, they will be flushed out to the wire. 2165 */ 2166 if (!sc->dc_link) { 2167 mii_pollstat(mii); 2168 if (mii->mii_media_status & IFM_ACTIVE && 2169 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) { 2170 sc->dc_link++; 2171 if (ifp->if_snd.ifq_head != NULL) 2172 dc_start(ifp); 2173 } 2174 } 2175 2176 sc->dc_stat_ch = timeout(dc_tick, sc, hz); 2177 2178 splx(s); 2179 2180 return; 2181 } 2182 2183 static void dc_intr(arg) 2184 void *arg; 2185 { 2186 struct dc_softc *sc; 2187 struct ifnet *ifp; 2188 u_int32_t status; 2189 2190 sc = arg; 2191 ifp = &sc->arpcom.ac_if; 2192 2193 /* Supress unwanted interrupts */ 2194 if (!(ifp->if_flags & IFF_UP)) { 2195 if (CSR_READ_4(sc, DC_ISR) & DC_INTRS) 2196 dc_stop(sc); 2197 return; 2198 } 2199 2200 /* Disable interrupts. */ 2201 CSR_WRITE_4(sc, DC_IMR, 0x00000000); 2202 2203 while((status = CSR_READ_4(sc, DC_ISR)) & DC_INTRS) { 2204 2205 CSR_WRITE_4(sc, DC_ISR, status); 2206 2207 if (status & DC_ISR_RX_OK) 2208 dc_rxeof(sc); 2209 2210 if (status & (DC_ISR_TX_OK|DC_ISR_TX_NOBUF)) 2211 dc_txeof(sc); 2212 2213 if (status & DC_ISR_TX_IDLE) { 2214 dc_txeof(sc); 2215 if (sc->dc_cdata.dc_tx_cnt) { 2216 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_TX_ON); 2217 CSR_WRITE_4(sc, DC_TXSTART, 0xFFFFFFFF); 2218 } 2219 } 2220 2221 if (status & DC_ISR_TX_UNDERRUN) { 2222 u_int32_t cfg; 2223 2224 printf("dc%d: TX underrun -- ", sc->dc_unit); 2225 if (DC_IS_DAVICOM(sc) || DC_IS_INTEL(sc)) 2226 dc_init(sc); 2227 cfg = CSR_READ_4(sc, DC_NETCFG); 2228 cfg &= ~DC_NETCFG_TX_THRESH; 2229 if (sc->dc_txthresh == DC_TXTHRESH_160BYTES) { 2230 printf("using store and forward mode\n"); 2231 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_STORENFWD); 2232 } else if (sc->dc_flags & DC_TX_STORENFWD) { 2233 printf("resetting\n"); 2234 } else { 2235 sc->dc_txthresh += 0x4000; 2236 printf("increasing TX threshold\n"); 2237 CSR_WRITE_4(sc, DC_NETCFG, cfg); 2238 DC_SETBIT(sc, DC_NETCFG, sc->dc_txthresh); 2239 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_STORENFWD); 2240 } 2241 } 2242 2243 if ((status & DC_ISR_RX_WATDOGTIMEO) 2244 || (status & DC_ISR_RX_NOBUF)) 2245 dc_rxeof(sc); 2246 2247 if (status & DC_ISR_BUS_ERR) { 2248 dc_reset(sc); 2249 dc_init(sc); 2250 } 2251 } 2252 2253 /* Re-enable interrupts. */ 2254 CSR_WRITE_4(sc, DC_IMR, DC_INTRS); 2255 2256 if (ifp->if_snd.ifq_head != NULL) 2257 dc_start(ifp); 2258 2259 return; 2260 } 2261 2262 /* 2263 * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data 2264 * pointers to the fragment pointers. 2265 */ 2266 static int dc_encap(sc, m_head, txidx) 2267 struct dc_softc *sc; 2268 struct mbuf *m_head; 2269 u_int32_t *txidx; 2270 { 2271 struct dc_desc *f = NULL; 2272 struct mbuf *m; 2273 int frag, cur, cnt = 0; 2274 2275 /* 2276 * Start packing the mbufs in this chain into 2277 * the fragment pointers. Stop when we run out 2278 * of fragments or hit the end of the mbuf chain. 2279 */ 2280 m = m_head; 2281 cur = frag = *txidx; 2282 2283 for (m = m_head; m != NULL; m = m->m_next) { 2284 if (m->m_len != 0) { 2285 if (sc->dc_flags & DC_TX_ADMTEK_WAR) { 2286 if (*txidx != sc->dc_cdata.dc_tx_prod && 2287 frag == (DC_TX_LIST_CNT - 1)) 2288 return(ENOBUFS); 2289 } 2290 if ((DC_TX_LIST_CNT - 2291 (sc->dc_cdata.dc_tx_cnt + cnt)) < 5) 2292 return(ENOBUFS); 2293 2294 f = &sc->dc_ldata->dc_tx_list[frag]; 2295 f->dc_ctl = DC_TXCTL_TLINK | m->m_len; 2296 if (cnt == 0) { 2297 f->dc_status = 0; 2298 f->dc_ctl |= DC_TXCTL_FIRSTFRAG; 2299 } else 2300 f->dc_status = DC_TXSTAT_OWN; 2301 f->dc_data = vtophys(mtod(m, vm_offset_t)); 2302 cur = frag; 2303 DC_INC(frag, DC_TX_LIST_CNT); 2304 cnt++; 2305 } 2306 } 2307 2308 if (m != NULL) 2309 return(ENOBUFS); 2310 2311 sc->dc_cdata.dc_tx_cnt += cnt; 2312 sc->dc_cdata.dc_tx_chain[cur] = m_head; 2313 sc->dc_ldata->dc_tx_list[cur].dc_ctl |= DC_TXCTL_LASTFRAG; 2314 if (sc->dc_flags & DC_TX_INTR_FIRSTFRAG) 2315 sc->dc_ldata->dc_tx_list[*txidx].dc_ctl |= DC_TXCTL_FINT; 2316 if (sc->dc_flags & DC_TX_INTR_ALWAYS) 2317 sc->dc_ldata->dc_tx_list[cur].dc_ctl |= DC_TXCTL_FINT; 2318 if (sc->dc_flags & DC_TX_USE_TX_INTR && sc->dc_cdata.dc_tx_cnt > 64) 2319 sc->dc_ldata->dc_tx_list[cur].dc_ctl |= DC_TXCTL_FINT; 2320 sc->dc_ldata->dc_tx_list[*txidx].dc_status = DC_TXSTAT_OWN; 2321 *txidx = frag; 2322 2323 return(0); 2324 } 2325 2326 /* 2327 * Main transmit routine. To avoid having to do mbuf copies, we put pointers 2328 * to the mbuf data regions directly in the transmit lists. We also save a 2329 * copy of the pointers since the transmit list fragment pointers are 2330 * physical addresses. 2331 */ 2332 2333 static void dc_start(ifp) 2334 struct ifnet *ifp; 2335 { 2336 struct dc_softc *sc; 2337 struct mbuf *m_head = NULL; 2338 int idx; 2339 2340 sc = ifp->if_softc; 2341 2342 if (!sc->dc_link) 2343 return; 2344 2345 if (ifp->if_flags & IFF_OACTIVE) 2346 return; 2347 2348 idx = sc->dc_cdata.dc_tx_prod; 2349 2350 while(sc->dc_cdata.dc_tx_chain[idx] == NULL) { 2351 IF_DEQUEUE(&ifp->if_snd, m_head); 2352 if (m_head == NULL) 2353 break; 2354 2355 if (dc_encap(sc, m_head, &idx)) { 2356 IF_PREPEND(&ifp->if_snd, m_head); 2357 ifp->if_flags |= IFF_OACTIVE; 2358 break; 2359 } 2360 2361 /* 2362 * If there's a BPF listener, bounce a copy of this frame 2363 * to him. 2364 */ 2365 if (ifp->if_bpf) 2366 bpf_mtap(ifp, m_head); 2367 } 2368 2369 /* Transmit */ 2370 sc->dc_cdata.dc_tx_prod = idx; 2371 if (!(sc->dc_flags & DC_TX_POLL)) 2372 CSR_WRITE_4(sc, DC_TXSTART, 0xFFFFFFFF); 2373 2374 /* 2375 * Set a timeout in case the chip goes out to lunch. 2376 */ 2377 ifp->if_timer = 5; 2378 2379 return; 2380 } 2381 2382 static void dc_init(xsc) 2383 void *xsc; 2384 { 2385 struct dc_softc *sc = xsc; 2386 struct ifnet *ifp = &sc->arpcom.ac_if; 2387 struct mii_data *mii; 2388 int s; 2389 2390 s = splimp(); 2391 2392 mii = device_get_softc(sc->dc_miibus); 2393 2394 /* 2395 * Cancel pending I/O and free all RX/TX buffers. 2396 */ 2397 dc_stop(sc); 2398 dc_reset(sc); 2399 2400 /* 2401 * Set cache alignment and burst length. 2402 */ 2403 if (DC_IS_ASIX(sc)) 2404 CSR_WRITE_4(sc, DC_BUSCTL, 0); 2405 else 2406 CSR_WRITE_4(sc, DC_BUSCTL, DC_BUSCTL_MRME|DC_BUSCTL_MRLE); 2407 if (DC_IS_DAVICOM(sc) || DC_IS_INTEL(sc)) { 2408 DC_SETBIT(sc, DC_BUSCTL, DC_BURSTLEN_USECA); 2409 } else { 2410 DC_SETBIT(sc, DC_BUSCTL, DC_BURSTLEN_16LONG); 2411 } 2412 if (sc->dc_flags & DC_TX_POLL) 2413 DC_SETBIT(sc, DC_BUSCTL, DC_TXPOLL_1); 2414 switch(sc->dc_cachesize) { 2415 case 32: 2416 DC_SETBIT(sc, DC_BUSCTL, DC_CACHEALIGN_32LONG); 2417 break; 2418 case 16: 2419 DC_SETBIT(sc, DC_BUSCTL, DC_CACHEALIGN_16LONG); 2420 break; 2421 case 8: 2422 DC_SETBIT(sc, DC_BUSCTL, DC_CACHEALIGN_8LONG); 2423 break; 2424 case 0: 2425 default: 2426 DC_SETBIT(sc, DC_BUSCTL, DC_CACHEALIGN_NONE); 2427 break; 2428 } 2429 2430 if (sc->dc_flags & DC_TX_STORENFWD) 2431 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_STORENFWD); 2432 else { 2433 if (sc->dc_txthresh == DC_TXTHRESH_160BYTES) { 2434 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_STORENFWD); 2435 } else { 2436 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_STORENFWD); 2437 DC_SETBIT(sc, DC_NETCFG, sc->dc_txthresh); 2438 } 2439 } 2440 2441 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_NO_RXCRC); 2442 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_TX_BACKOFF); 2443 2444 if (DC_IS_MACRONIX(sc) || DC_IS_PNICII(sc)) { 2445 /* 2446 * The app notes for the 98713 and 98715A say that 2447 * in order to have the chips operate properly, a magic 2448 * number must be written to CSR16. Macronix does not 2449 * document the meaning of these bits so there's no way 2450 * to know exactly what they do. The 98713 has a magic 2451 * number all its own; the rest all use a different one. 2452 */ 2453 DC_CLRBIT(sc, DC_MX_MAGICPACKET, 0xFFFF0000); 2454 if (sc->dc_type == DC_TYPE_98713) 2455 DC_SETBIT(sc, DC_MX_MAGICPACKET, DC_MX_MAGIC_98713); 2456 else 2457 DC_SETBIT(sc, DC_MX_MAGICPACKET, DC_MX_MAGIC_98715); 2458 } 2459 2460 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_TX_THRESH); 2461 DC_SETBIT(sc, DC_NETCFG, DC_TXTHRESH_72BYTES); 2462 2463 /* Init circular RX list. */ 2464 if (dc_list_rx_init(sc) == ENOBUFS) { 2465 printf("dc%d: initialization failed: no " 2466 "memory for rx buffers\n", sc->dc_unit); 2467 dc_stop(sc); 2468 (void)splx(s); 2469 return; 2470 } 2471 2472 /* 2473 * Init tx descriptors. 2474 */ 2475 dc_list_tx_init(sc); 2476 2477 /* 2478 * Load the address of the RX list. 2479 */ 2480 CSR_WRITE_4(sc, DC_RXADDR, vtophys(&sc->dc_ldata->dc_rx_list[0])); 2481 CSR_WRITE_4(sc, DC_TXADDR, vtophys(&sc->dc_ldata->dc_tx_list[0])); 2482 2483 /* 2484 * Enable interrupts. 2485 */ 2486 CSR_WRITE_4(sc, DC_IMR, DC_INTRS); 2487 CSR_WRITE_4(sc, DC_ISR, 0xFFFFFFFF); 2488 2489 /* Enable transmitter. */ 2490 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_TX_ON); 2491 2492 /* 2493 * Load the RX/multicast filter. We do this sort of late 2494 * because the filter programming scheme on the 21143 and 2495 * some clones requires DMAing a setup frame via the TX 2496 * engine, and we need the transmitter enabled for that. 2497 */ 2498 dc_setfilt(sc); 2499 2500 /* Enable receiver. */ 2501 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_ON); 2502 CSR_WRITE_4(sc, DC_RXSTART, 0xFFFFFFFF); 2503 2504 mii_mediachg(mii); 2505 dc_setcfg(sc, sc->dc_if_media); 2506 2507 ifp->if_flags |= IFF_RUNNING; 2508 ifp->if_flags &= ~IFF_OACTIVE; 2509 2510 (void)splx(s); 2511 2512 sc->dc_stat_ch = timeout(dc_tick, sc, hz); 2513 2514 return; 2515 } 2516 2517 /* 2518 * Set media options. 2519 */ 2520 static int dc_ifmedia_upd(ifp) 2521 struct ifnet *ifp; 2522 { 2523 struct dc_softc *sc; 2524 struct mii_data *mii; 2525 2526 sc = ifp->if_softc; 2527 mii = device_get_softc(sc->dc_miibus); 2528 mii_mediachg(mii); 2529 sc->dc_link = 0; 2530 2531 return(0); 2532 } 2533 2534 /* 2535 * Report current media status. 2536 */ 2537 static void dc_ifmedia_sts(ifp, ifmr) 2538 struct ifnet *ifp; 2539 struct ifmediareq *ifmr; 2540 { 2541 struct dc_softc *sc; 2542 struct mii_data *mii; 2543 2544 sc = ifp->if_softc; 2545 mii = device_get_softc(sc->dc_miibus); 2546 mii_pollstat(mii); 2547 ifmr->ifm_active = mii->mii_media_active; 2548 ifmr->ifm_status = mii->mii_media_status; 2549 2550 return; 2551 } 2552 2553 static int dc_ioctl(ifp, command, data) 2554 struct ifnet *ifp; 2555 u_long command; 2556 caddr_t data; 2557 { 2558 struct dc_softc *sc = ifp->if_softc; 2559 struct ifreq *ifr = (struct ifreq *) data; 2560 struct mii_data *mii; 2561 int s, error = 0; 2562 2563 s = splimp(); 2564 2565 switch(command) { 2566 case SIOCSIFADDR: 2567 case SIOCGIFADDR: 2568 case SIOCSIFMTU: 2569 error = ether_ioctl(ifp, command, data); 2570 break; 2571 case SIOCSIFFLAGS: 2572 if (ifp->if_flags & IFF_UP) { 2573 if (ifp->if_flags & IFF_RUNNING && 2574 ifp->if_flags & IFF_PROMISC && 2575 !(sc->dc_if_flags & IFF_PROMISC)) { 2576 dc_setfilt(sc); 2577 } else if (ifp->if_flags & IFF_RUNNING && 2578 !(ifp->if_flags & IFF_PROMISC) && 2579 sc->dc_if_flags & IFF_PROMISC) { 2580 dc_setfilt(sc); 2581 } else if (!(ifp->if_flags & IFF_RUNNING)) { 2582 sc->dc_txthresh = 0; 2583 dc_init(sc); 2584 } 2585 } else { 2586 if (ifp->if_flags & IFF_RUNNING) 2587 dc_stop(sc); 2588 } 2589 sc->dc_if_flags = ifp->if_flags; 2590 error = 0; 2591 break; 2592 case SIOCADDMULTI: 2593 case SIOCDELMULTI: 2594 dc_setfilt(sc); 2595 error = 0; 2596 break; 2597 case SIOCGIFMEDIA: 2598 case SIOCSIFMEDIA: 2599 mii = device_get_softc(sc->dc_miibus); 2600 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 2601 break; 2602 default: 2603 error = EINVAL; 2604 break; 2605 } 2606 2607 (void)splx(s); 2608 2609 return(error); 2610 } 2611 2612 static void dc_watchdog(ifp) 2613 struct ifnet *ifp; 2614 { 2615 struct dc_softc *sc; 2616 2617 sc = ifp->if_softc; 2618 2619 ifp->if_oerrors++; 2620 printf("dc%d: watchdog timeout\n", sc->dc_unit); 2621 2622 dc_stop(sc); 2623 dc_reset(sc); 2624 dc_init(sc); 2625 2626 if (ifp->if_snd.ifq_head != NULL) 2627 dc_start(ifp); 2628 2629 return; 2630 } 2631 2632 /* 2633 * Stop the adapter and free any mbufs allocated to the 2634 * RX and TX lists. 2635 */ 2636 static void dc_stop(sc) 2637 struct dc_softc *sc; 2638 { 2639 register int i; 2640 struct ifnet *ifp; 2641 2642 ifp = &sc->arpcom.ac_if; 2643 ifp->if_timer = 0; 2644 2645 untimeout(dc_tick, sc, sc->dc_stat_ch); 2646 2647 DC_CLRBIT(sc, DC_NETCFG, (DC_NETCFG_RX_ON|DC_NETCFG_TX_ON)); 2648 CSR_WRITE_4(sc, DC_IMR, 0x00000000); 2649 CSR_WRITE_4(sc, DC_TXADDR, 0x00000000); 2650 CSR_WRITE_4(sc, DC_RXADDR, 0x00000000); 2651 sc->dc_link = 0; 2652 2653 /* 2654 * Free data in the RX lists. 2655 */ 2656 for (i = 0; i < DC_RX_LIST_CNT; i++) { 2657 if (sc->dc_cdata.dc_rx_chain[i] != NULL) { 2658 m_freem(sc->dc_cdata.dc_rx_chain[i]); 2659 sc->dc_cdata.dc_rx_chain[i] = NULL; 2660 } 2661 } 2662 bzero((char *)&sc->dc_ldata->dc_rx_list, 2663 sizeof(sc->dc_ldata->dc_rx_list)); 2664 2665 /* 2666 * Free the TX list buffers. 2667 */ 2668 for (i = 0; i < DC_TX_LIST_CNT; i++) { 2669 if (sc->dc_cdata.dc_tx_chain[i] != NULL) { 2670 if (sc->dc_ldata->dc_tx_list[i].dc_ctl & 2671 DC_TXCTL_SETUP) { 2672 sc->dc_cdata.dc_tx_chain[i] = NULL; 2673 continue; 2674 } 2675 m_freem(sc->dc_cdata.dc_tx_chain[i]); 2676 sc->dc_cdata.dc_tx_chain[i] = NULL; 2677 } 2678 } 2679 2680 bzero((char *)&sc->dc_ldata->dc_tx_list, 2681 sizeof(sc->dc_ldata->dc_tx_list)); 2682 2683 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 2684 2685 return; 2686 } 2687 2688 /* 2689 * Stop all chip I/O so that the kernel's probe routines don't 2690 * get confused by errant DMAs when rebooting. 2691 */ 2692 static void dc_shutdown(dev) 2693 device_t dev; 2694 { 2695 struct dc_softc *sc; 2696 2697 sc = device_get_softc(dev); 2698 2699 dc_stop(sc); 2700 2701 return; 2702 } 2703