1 /* 2 * Copyright (c) 1997, 1998, 1999 3 * Bill Paul <wpaul@ee.columbia.edu>. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 3. All advertising materials mentioning features or use of this software 14 * must display the following acknowledgement: 15 * This product includes software developed by Bill Paul. 16 * 4. Neither the name of the author nor the names of any co-contributors 17 * may be used to endorse or promote products derived from this software 18 * without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30 * THE POSSIBILITY OF SUCH DAMAGE. 31 * 32 * $FreeBSD$ 33 */ 34 35 /* 36 * DEC "tulip" clone ethernet driver. Supports the DEC/Intel 21143 37 * series chips and several workalikes including the following: 38 * 39 * Macronix 98713/98715/98725/98727/98732 PMAC (www.macronix.com) 40 * Macronix/Lite-On 82c115 PNIC II (www.macronix.com) 41 * Lite-On 82c168/82c169 PNIC (www.litecom.com) 42 * ASIX Electronics AX88140A (www.asix.com.tw) 43 * ASIX Electronics AX88141 (www.asix.com.tw) 44 * ADMtek AL981 (www.admtek.com.tw) 45 * ADMtek AN985 (www.admtek.com.tw) 46 * Davicom DM9100, DM9102, DM9102A (www.davicom8.com) 47 * Accton EN1217 (www.accton.com) 48 * Xircom X3201 (www.xircom.com) 49 * Abocom FE2500 50 * 51 * Datasheets for the 21143 are available at developer.intel.com. 52 * Datasheets for the clone parts can be found at their respective sites. 53 * (Except for the PNIC; see www.freebsd.org/~wpaul/PNIC/pnic.ps.gz.) 54 * The PNIC II is essentially a Macronix 98715A chip; the only difference 55 * worth noting is that its multicast hash table is only 128 bits wide 56 * instead of 512. 57 * 58 * Written by Bill Paul <wpaul@ee.columbia.edu> 59 * Electrical Engineering Department 60 * Columbia University, New York City 61 */ 62 63 /* 64 * The Intel 21143 is the successor to the DEC 21140. It is basically 65 * the same as the 21140 but with a few new features. The 21143 supports 66 * three kinds of media attachments: 67 * 68 * o MII port, for 10Mbps and 100Mbps support and NWAY 69 * autonegotiation provided by an external PHY. 70 * o SYM port, for symbol mode 100Mbps support. 71 * o 10baseT port. 72 * o AUI/BNC port. 73 * 74 * The 100Mbps SYM port and 10baseT port can be used together in 75 * combination with the internal NWAY support to create a 10/100 76 * autosensing configuration. 77 * 78 * Note that not all tulip workalikes are handled in this driver: we only 79 * deal with those which are relatively well behaved. The Winbond is 80 * handled separately due to its different register offsets and the 81 * special handling needed for its various bugs. The PNIC is handled 82 * here, but I'm not thrilled about it. 83 * 84 * All of the workalike chips use some form of MII transceiver support 85 * with the exception of the Macronix chips, which also have a SYM port. 86 * The ASIX AX88140A is also documented to have a SYM port, but all 87 * the cards I've seen use an MII transceiver, probably because the 88 * AX88140A doesn't support internal NWAY. 89 */ 90 91 #include <sys/param.h> 92 #include <sys/systm.h> 93 #include <sys/sockio.h> 94 #include <sys/mbuf.h> 95 #include <sys/malloc.h> 96 #include <sys/kernel.h> 97 #include <sys/socket.h> 98 99 #include <net/if.h> 100 #include <net/if_arp.h> 101 #include <net/ethernet.h> 102 #include <net/if_dl.h> 103 #include <net/if_media.h> 104 105 #include <net/bpf.h> 106 107 #include <vm/vm.h> /* for vtophys */ 108 #include <vm/pmap.h> /* for vtophys */ 109 #include <machine/bus_pio.h> 110 #include <machine/bus_memio.h> 111 #include <machine/bus.h> 112 #include <machine/resource.h> 113 #include <sys/bus.h> 114 #include <sys/rman.h> 115 116 #include <dev/mii/mii.h> 117 #include <dev/mii/miivar.h> 118 119 #include <pci/pcireg.h> 120 #include <pci/pcivar.h> 121 122 #define DC_USEIOSPACE 123 #ifdef __alpha__ 124 #define SRM_MEDIA 125 #endif 126 127 #include <pci/if_dcreg.h> 128 129 MODULE_DEPEND(dc, miibus, 1, 1, 1); 130 131 /* "controller miibus0" required. See GENERIC if you get errors here. */ 132 #include "miibus_if.h" 133 134 #ifndef lint 135 static const char rcsid[] = 136 "$FreeBSD$"; 137 #endif 138 139 /* 140 * Various supported device vendors/types and their names. 141 */ 142 static struct dc_type dc_devs[] = { 143 { DC_VENDORID_DEC, DC_DEVICEID_21143, 144 "Intel 21143 10/100BaseTX" }, 145 { DC_VENDORID_DAVICOM, DC_DEVICEID_DM9100, 146 "Davicom DM9100 10/100BaseTX" }, 147 { DC_VENDORID_DAVICOM, DC_DEVICEID_DM9102, 148 "Davicom DM9102 10/100BaseTX" }, 149 { DC_VENDORID_DAVICOM, DC_DEVICEID_DM9102, 150 "Davicom DM9102A 10/100BaseTX" }, 151 { DC_VENDORID_ADMTEK, DC_DEVICEID_AL981, 152 "ADMtek AL981 10/100BaseTX" }, 153 { DC_VENDORID_ADMTEK, DC_DEVICEID_AN985, 154 "ADMtek AN985 10/100BaseTX" }, 155 { DC_VENDORID_ASIX, DC_DEVICEID_AX88140A, 156 "ASIX AX88140A 10/100BaseTX" }, 157 { DC_VENDORID_ASIX, DC_DEVICEID_AX88140A, 158 "ASIX AX88141 10/100BaseTX" }, 159 { DC_VENDORID_MX, DC_DEVICEID_98713, 160 "Macronix 98713 10/100BaseTX" }, 161 { DC_VENDORID_MX, DC_DEVICEID_98713, 162 "Macronix 98713A 10/100BaseTX" }, 163 { DC_VENDORID_CP, DC_DEVICEID_98713_CP, 164 "Compex RL100-TX 10/100BaseTX" }, 165 { DC_VENDORID_CP, DC_DEVICEID_98713_CP, 166 "Compex RL100-TX 10/100BaseTX" }, 167 { DC_VENDORID_MX, DC_DEVICEID_987x5, 168 "Macronix 98715/98715A 10/100BaseTX" }, 169 { DC_VENDORID_MX, DC_DEVICEID_987x5, 170 "Macronix 98715AEC-C 10/100BaseTX" }, 171 { DC_VENDORID_MX, DC_DEVICEID_987x5, 172 "Macronix 98725 10/100BaseTX" }, 173 { DC_VENDORID_MX, DC_DEVICEID_98727, 174 "Macronix 98727/98732 10/100BaseTX" }, 175 { DC_VENDORID_LO, DC_DEVICEID_82C115, 176 "LC82C115 PNIC II 10/100BaseTX" }, 177 { DC_VENDORID_LO, DC_DEVICEID_82C168, 178 "82c168 PNIC 10/100BaseTX" }, 179 { DC_VENDORID_LO, DC_DEVICEID_82C168, 180 "82c169 PNIC 10/100BaseTX" }, 181 { DC_VENDORID_ACCTON, DC_DEVICEID_EN1217, 182 "Accton EN1217 10/100BaseTX" }, 183 { DC_VENDORID_ACCTON, DC_DEVICEID_EN2242, 184 "Accton EN2242 MiniPCI 10/100BaseTX" }, 185 { DC_VENDORID_XIRCOM, DC_DEVICEID_X3201, 186 "Xircom X3201 10/100BaseTX" }, 187 { DC_VENDORID_ABOCOM, DC_DEVICEID_FE2500, 188 "Abocom FE2500 10/100BaseTX" }, 189 { 0, 0, NULL } 190 }; 191 192 static int dc_probe __P((device_t)); 193 static int dc_attach __P((device_t)); 194 static int dc_detach __P((device_t)); 195 static void dc_acpi __P((device_t)); 196 static struct dc_type *dc_devtype __P((device_t)); 197 static int dc_newbuf __P((struct dc_softc *, int, struct mbuf *)); 198 static int dc_encap __P((struct dc_softc *, struct mbuf *, 199 u_int32_t *)); 200 static int dc_coal __P((struct dc_softc *, struct mbuf **)); 201 static void dc_pnic_rx_bug_war __P((struct dc_softc *, int)); 202 static int dc_rx_resync __P((struct dc_softc *)); 203 static void dc_rxeof __P((struct dc_softc *)); 204 static void dc_txeof __P((struct dc_softc *)); 205 static void dc_tick __P((void *)); 206 static void dc_intr __P((void *)); 207 static void dc_start __P((struct ifnet *)); 208 static int dc_ioctl __P((struct ifnet *, u_long, caddr_t)); 209 static void dc_init __P((void *)); 210 static void dc_stop __P((struct dc_softc *)); 211 static void dc_watchdog __P((struct ifnet *)); 212 static void dc_shutdown __P((device_t)); 213 static int dc_ifmedia_upd __P((struct ifnet *)); 214 static void dc_ifmedia_sts __P((struct ifnet *, struct ifmediareq *)); 215 216 static void dc_delay __P((struct dc_softc *)); 217 static void dc_eeprom_idle __P((struct dc_softc *)); 218 static void dc_eeprom_putbyte __P((struct dc_softc *, int)); 219 static void dc_eeprom_getword __P((struct dc_softc *, int, u_int16_t *)); 220 static void dc_eeprom_getword_pnic 221 __P((struct dc_softc *, int, u_int16_t *)); 222 static void dc_eeprom_getword_xircom 223 __P((struct dc_softc *, int, u_int16_t *)); 224 static void dc_read_eeprom __P((struct dc_softc *, caddr_t, int, 225 int, int)); 226 227 static void dc_mii_writebit __P((struct dc_softc *, int)); 228 static int dc_mii_readbit __P((struct dc_softc *)); 229 static void dc_mii_sync __P((struct dc_softc *)); 230 static void dc_mii_send __P((struct dc_softc *, u_int32_t, int)); 231 static int dc_mii_readreg __P((struct dc_softc *, struct dc_mii_frame *)); 232 static int dc_mii_writereg __P((struct dc_softc *, struct dc_mii_frame *)); 233 static int dc_miibus_readreg __P((device_t, int, int)); 234 static int dc_miibus_writereg __P((device_t, int, int, int)); 235 static void dc_miibus_statchg __P((device_t)); 236 static void dc_miibus_mediainit __P((device_t)); 237 238 static void dc_setcfg __P((struct dc_softc *, int)); 239 static u_int32_t dc_crc_le __P((struct dc_softc *, caddr_t)); 240 static u_int32_t dc_crc_be __P((caddr_t)); 241 static void dc_setfilt_21143 __P((struct dc_softc *)); 242 static void dc_setfilt_asix __P((struct dc_softc *)); 243 static void dc_setfilt_admtek __P((struct dc_softc *)); 244 static void dc_setfilt_xircom __P((struct dc_softc *)); 245 246 static void dc_setfilt __P((struct dc_softc *)); 247 248 static void dc_reset __P((struct dc_softc *)); 249 static int dc_list_rx_init __P((struct dc_softc *)); 250 static int dc_list_tx_init __P((struct dc_softc *)); 251 252 static void dc_parse_21143_srom __P((struct dc_softc *)); 253 static void dc_decode_leaf_sia __P((struct dc_softc *, 254 struct dc_eblock_sia *)); 255 static void dc_decode_leaf_mii __P((struct dc_softc *, 256 struct dc_eblock_mii *)); 257 static void dc_decode_leaf_sym __P((struct dc_softc *, 258 struct dc_eblock_sym *)); 259 static void dc_apply_fixup __P((struct dc_softc *, int)); 260 261 #ifdef DC_USEIOSPACE 262 #define DC_RES SYS_RES_IOPORT 263 #define DC_RID DC_PCI_CFBIO 264 #else 265 #define DC_RES SYS_RES_MEMORY 266 #define DC_RID DC_PCI_CFBMA 267 #endif 268 269 static device_method_t dc_methods[] = { 270 /* Device interface */ 271 DEVMETHOD(device_probe, dc_probe), 272 DEVMETHOD(device_attach, dc_attach), 273 DEVMETHOD(device_detach, dc_detach), 274 DEVMETHOD(device_shutdown, dc_shutdown), 275 276 /* bus interface */ 277 DEVMETHOD(bus_print_child, bus_generic_print_child), 278 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 279 280 /* MII interface */ 281 DEVMETHOD(miibus_readreg, dc_miibus_readreg), 282 DEVMETHOD(miibus_writereg, dc_miibus_writereg), 283 DEVMETHOD(miibus_statchg, dc_miibus_statchg), 284 DEVMETHOD(miibus_mediainit, dc_miibus_mediainit), 285 286 { 0, 0 } 287 }; 288 289 static driver_t dc_driver = { 290 "dc", 291 dc_methods, 292 sizeof(struct dc_softc) 293 }; 294 295 static devclass_t dc_devclass; 296 297 DRIVER_MODULE(if_dc, cardbus, dc_driver, dc_devclass, 0, 0); 298 DRIVER_MODULE(if_dc, pci, dc_driver, dc_devclass, 0, 0); 299 DRIVER_MODULE(miibus, dc, miibus_driver, miibus_devclass, 0, 0); 300 301 #define DC_SETBIT(sc, reg, x) \ 302 CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) | (x)) 303 304 #define DC_CLRBIT(sc, reg, x) \ 305 CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) & ~(x)) 306 307 #define SIO_SET(x) DC_SETBIT(sc, DC_SIO, (x)) 308 #define SIO_CLR(x) DC_CLRBIT(sc, DC_SIO, (x)) 309 310 #define IS_MPSAFE 0 311 312 static void dc_delay(sc) 313 struct dc_softc *sc; 314 { 315 int idx; 316 317 for (idx = (300 / 33) + 1; idx > 0; idx--) 318 CSR_READ_4(sc, DC_BUSCTL); 319 } 320 321 static void dc_eeprom_idle(sc) 322 struct dc_softc *sc; 323 { 324 register int i; 325 326 CSR_WRITE_4(sc, DC_SIO, DC_SIO_EESEL); 327 dc_delay(sc); 328 DC_SETBIT(sc, DC_SIO, DC_SIO_ROMCTL_READ); 329 dc_delay(sc); 330 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); 331 dc_delay(sc); 332 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CS); 333 dc_delay(sc); 334 335 for (i = 0; i < 25; i++) { 336 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); 337 dc_delay(sc); 338 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CLK); 339 dc_delay(sc); 340 } 341 342 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); 343 dc_delay(sc); 344 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CS); 345 dc_delay(sc); 346 CSR_WRITE_4(sc, DC_SIO, 0x00000000); 347 348 return; 349 } 350 351 /* 352 * Send a read command and address to the EEPROM, check for ACK. 353 */ 354 static void dc_eeprom_putbyte(sc, addr) 355 struct dc_softc *sc; 356 int addr; 357 { 358 register int d, i; 359 360 /* 361 * The AN985 has a 93C66 EEPROM on it instead of 362 * a 93C46. It uses a different bit sequence for 363 * specifying the "read" opcode. 364 */ 365 if (DC_IS_CENTAUR(sc)) 366 d = addr | (DC_EECMD_READ << 2); 367 else 368 d = addr | DC_EECMD_READ; 369 370 /* 371 * Feed in each bit and strobe the clock. 372 */ 373 for (i = 0x400; i; i >>= 1) { 374 if (d & i) { 375 SIO_SET(DC_SIO_EE_DATAIN); 376 } else { 377 SIO_CLR(DC_SIO_EE_DATAIN); 378 } 379 dc_delay(sc); 380 SIO_SET(DC_SIO_EE_CLK); 381 dc_delay(sc); 382 SIO_CLR(DC_SIO_EE_CLK); 383 dc_delay(sc); 384 } 385 386 return; 387 } 388 389 /* 390 * Read a word of data stored in the EEPROM at address 'addr.' 391 * The PNIC 82c168/82c169 has its own non-standard way to read 392 * the EEPROM. 393 */ 394 static void dc_eeprom_getword_pnic(sc, addr, dest) 395 struct dc_softc *sc; 396 int addr; 397 u_int16_t *dest; 398 { 399 register int i; 400 u_int32_t r; 401 402 CSR_WRITE_4(sc, DC_PN_SIOCTL, DC_PN_EEOPCODE_READ|addr); 403 404 for (i = 0; i < DC_TIMEOUT; i++) { 405 DELAY(1); 406 r = CSR_READ_4(sc, DC_SIO); 407 if (!(r & DC_PN_SIOCTL_BUSY)) { 408 *dest = (u_int16_t)(r & 0xFFFF); 409 return; 410 } 411 } 412 413 return; 414 } 415 416 /* 417 * Read a word of data stored in the EEPROM at address 'addr.' 418 * The Xircom X3201 has its own non-standard way to read 419 * the EEPROM, too. 420 */ 421 static void dc_eeprom_getword_xircom(sc, addr, dest) 422 struct dc_softc *sc; 423 int addr; 424 u_int16_t *dest; 425 { 426 SIO_SET(DC_SIO_ROMSEL | DC_SIO_ROMCTL_READ); 427 428 addr *= 2; 429 CSR_WRITE_4(sc, DC_ROM, addr | 0x160); 430 *dest = (u_int16_t)CSR_READ_4(sc, DC_SIO)&0xff; 431 addr += 1; 432 CSR_WRITE_4(sc, DC_ROM, addr | 0x160); 433 *dest |= ((u_int16_t)CSR_READ_4(sc, DC_SIO)&0xff) << 8; 434 435 SIO_CLR(DC_SIO_ROMSEL | DC_SIO_ROMCTL_READ); 436 return; 437 } 438 439 /* 440 * Read a word of data stored in the EEPROM at address 'addr.' 441 */ 442 static void dc_eeprom_getword(sc, addr, dest) 443 struct dc_softc *sc; 444 int addr; 445 u_int16_t *dest; 446 { 447 register int i; 448 u_int16_t word = 0; 449 450 /* Force EEPROM to idle state. */ 451 dc_eeprom_idle(sc); 452 453 /* Enter EEPROM access mode. */ 454 CSR_WRITE_4(sc, DC_SIO, DC_SIO_EESEL); 455 dc_delay(sc); 456 DC_SETBIT(sc, DC_SIO, DC_SIO_ROMCTL_READ); 457 dc_delay(sc); 458 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); 459 dc_delay(sc); 460 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CS); 461 dc_delay(sc); 462 463 /* 464 * Send address of word we want to read. 465 */ 466 dc_eeprom_putbyte(sc, addr); 467 468 /* 469 * Start reading bits from EEPROM. 470 */ 471 for (i = 0x8000; i; i >>= 1) { 472 SIO_SET(DC_SIO_EE_CLK); 473 dc_delay(sc); 474 if (CSR_READ_4(sc, DC_SIO) & DC_SIO_EE_DATAOUT) 475 word |= i; 476 dc_delay(sc); 477 SIO_CLR(DC_SIO_EE_CLK); 478 dc_delay(sc); 479 } 480 481 /* Turn off EEPROM access mode. */ 482 dc_eeprom_idle(sc); 483 484 *dest = word; 485 486 return; 487 } 488 489 /* 490 * Read a sequence of words from the EEPROM. 491 */ 492 static void dc_read_eeprom(sc, dest, off, cnt, swap) 493 struct dc_softc *sc; 494 caddr_t dest; 495 int off; 496 int cnt; 497 int swap; 498 { 499 int i; 500 u_int16_t word = 0, *ptr; 501 502 for (i = 0; i < cnt; i++) { 503 if (DC_IS_PNIC(sc)) 504 dc_eeprom_getword_pnic(sc, off + i, &word); 505 else if (DC_IS_XIRCOM(sc)) 506 dc_eeprom_getword_xircom(sc, off + i, &word); 507 else 508 dc_eeprom_getword(sc, off + i, &word); 509 ptr = (u_int16_t *)(dest + (i * 2)); 510 if (swap) 511 *ptr = ntohs(word); 512 else 513 *ptr = word; 514 } 515 516 return; 517 } 518 519 /* 520 * The following two routines are taken from the Macronix 98713 521 * Application Notes pp.19-21. 522 */ 523 /* 524 * Write a bit to the MII bus. 525 */ 526 static void dc_mii_writebit(sc, bit) 527 struct dc_softc *sc; 528 int bit; 529 { 530 if (bit) 531 CSR_WRITE_4(sc, DC_SIO, 532 DC_SIO_ROMCTL_WRITE|DC_SIO_MII_DATAOUT); 533 else 534 CSR_WRITE_4(sc, DC_SIO, DC_SIO_ROMCTL_WRITE); 535 536 DC_SETBIT(sc, DC_SIO, DC_SIO_MII_CLK); 537 DC_CLRBIT(sc, DC_SIO, DC_SIO_MII_CLK); 538 539 return; 540 } 541 542 /* 543 * Read a bit from the MII bus. 544 */ 545 static int dc_mii_readbit(sc) 546 struct dc_softc *sc; 547 { 548 CSR_WRITE_4(sc, DC_SIO, DC_SIO_ROMCTL_READ|DC_SIO_MII_DIR); 549 CSR_READ_4(sc, DC_SIO); 550 DC_SETBIT(sc, DC_SIO, DC_SIO_MII_CLK); 551 DC_CLRBIT(sc, DC_SIO, DC_SIO_MII_CLK); 552 if (CSR_READ_4(sc, DC_SIO) & DC_SIO_MII_DATAIN) 553 return(1); 554 555 return(0); 556 } 557 558 /* 559 * Sync the PHYs by setting data bit and strobing the clock 32 times. 560 */ 561 static void dc_mii_sync(sc) 562 struct dc_softc *sc; 563 { 564 register int i; 565 566 CSR_WRITE_4(sc, DC_SIO, DC_SIO_ROMCTL_WRITE); 567 568 for (i = 0; i < 32; i++) 569 dc_mii_writebit(sc, 1); 570 571 return; 572 } 573 574 /* 575 * Clock a series of bits through the MII. 576 */ 577 static void dc_mii_send(sc, bits, cnt) 578 struct dc_softc *sc; 579 u_int32_t bits; 580 int cnt; 581 { 582 int i; 583 584 for (i = (0x1 << (cnt - 1)); i; i >>= 1) 585 dc_mii_writebit(sc, bits & i); 586 } 587 588 /* 589 * Read an PHY register through the MII. 590 */ 591 static int dc_mii_readreg(sc, frame) 592 struct dc_softc *sc; 593 struct dc_mii_frame *frame; 594 595 { 596 int i, ack; 597 598 DC_LOCK(sc); 599 600 /* 601 * Set up frame for RX. 602 */ 603 frame->mii_stdelim = DC_MII_STARTDELIM; 604 frame->mii_opcode = DC_MII_READOP; 605 frame->mii_turnaround = 0; 606 frame->mii_data = 0; 607 608 /* 609 * Sync the PHYs. 610 */ 611 dc_mii_sync(sc); 612 613 /* 614 * Send command/address info. 615 */ 616 dc_mii_send(sc, frame->mii_stdelim, 2); 617 dc_mii_send(sc, frame->mii_opcode, 2); 618 dc_mii_send(sc, frame->mii_phyaddr, 5); 619 dc_mii_send(sc, frame->mii_regaddr, 5); 620 621 #ifdef notdef 622 /* Idle bit */ 623 dc_mii_writebit(sc, 1); 624 dc_mii_writebit(sc, 0); 625 #endif 626 627 /* Check for ack */ 628 ack = dc_mii_readbit(sc); 629 630 /* 631 * Now try reading data bits. If the ack failed, we still 632 * need to clock through 16 cycles to keep the PHY(s) in sync. 633 */ 634 if (ack) { 635 for(i = 0; i < 16; i++) { 636 dc_mii_readbit(sc); 637 } 638 goto fail; 639 } 640 641 for (i = 0x8000; i; i >>= 1) { 642 if (!ack) { 643 if (dc_mii_readbit(sc)) 644 frame->mii_data |= i; 645 } 646 } 647 648 fail: 649 650 dc_mii_writebit(sc, 0); 651 dc_mii_writebit(sc, 0); 652 653 DC_UNLOCK(sc); 654 655 if (ack) 656 return(1); 657 return(0); 658 } 659 660 /* 661 * Write to a PHY register through the MII. 662 */ 663 static int dc_mii_writereg(sc, frame) 664 struct dc_softc *sc; 665 struct dc_mii_frame *frame; 666 667 { 668 DC_LOCK(sc); 669 /* 670 * Set up frame for TX. 671 */ 672 673 frame->mii_stdelim = DC_MII_STARTDELIM; 674 frame->mii_opcode = DC_MII_WRITEOP; 675 frame->mii_turnaround = DC_MII_TURNAROUND; 676 677 /* 678 * Sync the PHYs. 679 */ 680 dc_mii_sync(sc); 681 682 dc_mii_send(sc, frame->mii_stdelim, 2); 683 dc_mii_send(sc, frame->mii_opcode, 2); 684 dc_mii_send(sc, frame->mii_phyaddr, 5); 685 dc_mii_send(sc, frame->mii_regaddr, 5); 686 dc_mii_send(sc, frame->mii_turnaround, 2); 687 dc_mii_send(sc, frame->mii_data, 16); 688 689 /* Idle bit. */ 690 dc_mii_writebit(sc, 0); 691 dc_mii_writebit(sc, 0); 692 693 DC_UNLOCK(sc); 694 695 return(0); 696 } 697 698 static int dc_miibus_readreg(dev, phy, reg) 699 device_t dev; 700 int phy, reg; 701 { 702 struct dc_mii_frame frame; 703 struct dc_softc *sc; 704 int i, rval, phy_reg = 0; 705 706 sc = device_get_softc(dev); 707 bzero((char *)&frame, sizeof(frame)); 708 709 /* 710 * Note: both the AL981 and AN985 have internal PHYs, 711 * however the AL981 provides direct access to the PHY 712 * registers while the AN985 uses a serial MII interface. 713 * The AN985's MII interface is also buggy in that you 714 * can read from any MII address (0 to 31), but only address 1 715 * behaves normally. To deal with both cases, we pretend 716 * that the PHY is at MII address 1. 717 */ 718 if (DC_IS_ADMTEK(sc) && phy != DC_ADMTEK_PHYADDR) 719 return(0); 720 721 if (sc->dc_pmode != DC_PMODE_MII) { 722 if (phy == (MII_NPHY - 1)) { 723 switch(reg) { 724 case MII_BMSR: 725 /* 726 * Fake something to make the probe 727 * code think there's a PHY here. 728 */ 729 return(BMSR_MEDIAMASK); 730 break; 731 case MII_PHYIDR1: 732 if (DC_IS_PNIC(sc)) 733 return(DC_VENDORID_LO); 734 return(DC_VENDORID_DEC); 735 break; 736 case MII_PHYIDR2: 737 if (DC_IS_PNIC(sc)) 738 return(DC_DEVICEID_82C168); 739 return(DC_DEVICEID_21143); 740 break; 741 default: 742 return(0); 743 break; 744 } 745 } else 746 return(0); 747 } 748 749 if (DC_IS_PNIC(sc)) { 750 CSR_WRITE_4(sc, DC_PN_MII, DC_PN_MIIOPCODE_READ | 751 (phy << 23) | (reg << 18)); 752 for (i = 0; i < DC_TIMEOUT; i++) { 753 DELAY(1); 754 rval = CSR_READ_4(sc, DC_PN_MII); 755 if (!(rval & DC_PN_MII_BUSY)) { 756 rval &= 0xFFFF; 757 return(rval == 0xFFFF ? 0 : rval); 758 } 759 } 760 return(0); 761 } 762 763 if (DC_IS_COMET(sc)) { 764 switch(reg) { 765 case MII_BMCR: 766 phy_reg = DC_AL_BMCR; 767 break; 768 case MII_BMSR: 769 phy_reg = DC_AL_BMSR; 770 break; 771 case MII_PHYIDR1: 772 phy_reg = DC_AL_VENID; 773 break; 774 case MII_PHYIDR2: 775 phy_reg = DC_AL_DEVID; 776 break; 777 case MII_ANAR: 778 phy_reg = DC_AL_ANAR; 779 break; 780 case MII_ANLPAR: 781 phy_reg = DC_AL_LPAR; 782 break; 783 case MII_ANER: 784 phy_reg = DC_AL_ANER; 785 break; 786 default: 787 printf("dc%d: phy_read: bad phy register %x\n", 788 sc->dc_unit, reg); 789 return(0); 790 break; 791 } 792 793 rval = CSR_READ_4(sc, phy_reg) & 0x0000FFFF; 794 795 if (rval == 0xFFFF) 796 return(0); 797 return(rval); 798 } 799 800 frame.mii_phyaddr = phy; 801 frame.mii_regaddr = reg; 802 if (sc->dc_type == DC_TYPE_98713) { 803 phy_reg = CSR_READ_4(sc, DC_NETCFG); 804 CSR_WRITE_4(sc, DC_NETCFG, phy_reg & ~DC_NETCFG_PORTSEL); 805 } 806 dc_mii_readreg(sc, &frame); 807 if (sc->dc_type == DC_TYPE_98713) 808 CSR_WRITE_4(sc, DC_NETCFG, phy_reg); 809 810 return(frame.mii_data); 811 } 812 813 static int dc_miibus_writereg(dev, phy, reg, data) 814 device_t dev; 815 int phy, reg, data; 816 { 817 struct dc_softc *sc; 818 struct dc_mii_frame frame; 819 int i, phy_reg = 0; 820 821 sc = device_get_softc(dev); 822 bzero((char *)&frame, sizeof(frame)); 823 824 if (DC_IS_ADMTEK(sc) && phy != DC_ADMTEK_PHYADDR) 825 return(0); 826 827 if (DC_IS_PNIC(sc)) { 828 CSR_WRITE_4(sc, DC_PN_MII, DC_PN_MIIOPCODE_WRITE | 829 (phy << 23) | (reg << 10) | data); 830 for (i = 0; i < DC_TIMEOUT; i++) { 831 if (!(CSR_READ_4(sc, DC_PN_MII) & DC_PN_MII_BUSY)) 832 break; 833 } 834 return(0); 835 } 836 837 if (DC_IS_COMET(sc)) { 838 switch(reg) { 839 case MII_BMCR: 840 phy_reg = DC_AL_BMCR; 841 break; 842 case MII_BMSR: 843 phy_reg = DC_AL_BMSR; 844 break; 845 case MII_PHYIDR1: 846 phy_reg = DC_AL_VENID; 847 break; 848 case MII_PHYIDR2: 849 phy_reg = DC_AL_DEVID; 850 break; 851 case MII_ANAR: 852 phy_reg = DC_AL_ANAR; 853 break; 854 case MII_ANLPAR: 855 phy_reg = DC_AL_LPAR; 856 break; 857 case MII_ANER: 858 phy_reg = DC_AL_ANER; 859 break; 860 default: 861 printf("dc%d: phy_write: bad phy register %x\n", 862 sc->dc_unit, reg); 863 return(0); 864 break; 865 } 866 867 CSR_WRITE_4(sc, phy_reg, data); 868 return(0); 869 } 870 871 frame.mii_phyaddr = phy; 872 frame.mii_regaddr = reg; 873 frame.mii_data = data; 874 875 if (sc->dc_type == DC_TYPE_98713) { 876 phy_reg = CSR_READ_4(sc, DC_NETCFG); 877 CSR_WRITE_4(sc, DC_NETCFG, phy_reg & ~DC_NETCFG_PORTSEL); 878 } 879 dc_mii_writereg(sc, &frame); 880 if (sc->dc_type == DC_TYPE_98713) 881 CSR_WRITE_4(sc, DC_NETCFG, phy_reg); 882 883 return(0); 884 } 885 886 static void dc_miibus_statchg(dev) 887 device_t dev; 888 { 889 struct dc_softc *sc; 890 struct mii_data *mii; 891 struct ifmedia *ifm; 892 893 sc = device_get_softc(dev); 894 if (DC_IS_ADMTEK(sc)) 895 return; 896 897 mii = device_get_softc(sc->dc_miibus); 898 ifm = &mii->mii_media; 899 if (DC_IS_DAVICOM(sc) && 900 IFM_SUBTYPE(ifm->ifm_media) == IFM_homePNA) { 901 dc_setcfg(sc, ifm->ifm_media); 902 sc->dc_if_media = ifm->ifm_media; 903 } else { 904 dc_setcfg(sc, mii->mii_media_active); 905 sc->dc_if_media = mii->mii_media_active; 906 } 907 908 return; 909 } 910 911 /* 912 * Special support for DM9102A cards with HomePNA PHYs. Note: 913 * with the Davicom DM9102A/DM9801 eval board that I have, it seems 914 * to be impossible to talk to the management interface of the DM9801 915 * PHY (its MDIO pin is not connected to anything). Consequently, 916 * the driver has to just 'know' about the additional mode and deal 917 * with it itself. *sigh* 918 */ 919 static void dc_miibus_mediainit(dev) 920 device_t dev; 921 { 922 struct dc_softc *sc; 923 struct mii_data *mii; 924 struct ifmedia *ifm; 925 int rev; 926 927 rev = pci_read_config(dev, DC_PCI_CFRV, 4) & 0xFF; 928 929 sc = device_get_softc(dev); 930 mii = device_get_softc(sc->dc_miibus); 931 ifm = &mii->mii_media; 932 933 if (DC_IS_DAVICOM(sc) && rev >= DC_REVISION_DM9102A) 934 ifmedia_add(ifm, IFM_ETHER|IFM_homePNA, 0, NULL); 935 936 return; 937 } 938 939 #define DC_POLY 0xEDB88320 940 #define DC_BITS_512 9 941 #define DC_BITS_128 7 942 #define DC_BITS_64 6 943 944 static u_int32_t dc_crc_le(sc, addr) 945 struct dc_softc *sc; 946 caddr_t addr; 947 { 948 u_int32_t idx, bit, data, crc; 949 950 /* Compute CRC for the address value. */ 951 crc = 0xFFFFFFFF; /* initial value */ 952 953 for (idx = 0; idx < 6; idx++) { 954 for (data = *addr++, bit = 0; bit < 8; bit++, data >>= 1) 955 crc = (crc >> 1) ^ (((crc ^ data) & 1) ? DC_POLY : 0); 956 } 957 958 /* 959 * The hash table on the PNIC II and the MX98715AEC-C/D/E 960 * chips is only 128 bits wide. 961 */ 962 if (sc->dc_flags & DC_128BIT_HASH) 963 return (crc & ((1 << DC_BITS_128) - 1)); 964 965 /* The hash table on the MX98715BEC is only 64 bits wide. */ 966 if (sc->dc_flags & DC_64BIT_HASH) 967 return (crc & ((1 << DC_BITS_64) - 1)); 968 969 /* Xircom's hash filtering table is different (read: weird) */ 970 /* Xircom uses the LEAST significant bits */ 971 if (DC_IS_XIRCOM(sc)) { 972 if ((crc & 0x180) == 0x180) 973 return (crc & 0x0F) + (crc & 0x70)*3 + (14 << 4); 974 else 975 return (crc & 0x1F) + ((crc>>1) & 0xF0)*3 + (12 << 4); 976 } 977 978 return (crc & ((1 << DC_BITS_512) - 1)); 979 } 980 981 /* 982 * Calculate CRC of a multicast group address, return the lower 6 bits. 983 */ 984 static u_int32_t dc_crc_be(addr) 985 caddr_t addr; 986 { 987 u_int32_t crc, carry; 988 int i, j; 989 u_int8_t c; 990 991 /* Compute CRC for the address value. */ 992 crc = 0xFFFFFFFF; /* initial value */ 993 994 for (i = 0; i < 6; i++) { 995 c = *(addr + i); 996 for (j = 0; j < 8; j++) { 997 carry = ((crc & 0x80000000) ? 1 : 0) ^ (c & 0x01); 998 crc <<= 1; 999 c >>= 1; 1000 if (carry) 1001 crc = (crc ^ 0x04c11db6) | carry; 1002 } 1003 } 1004 1005 /* return the filter bit position */ 1006 return((crc >> 26) & 0x0000003F); 1007 } 1008 1009 /* 1010 * 21143-style RX filter setup routine. Filter programming is done by 1011 * downloading a special setup frame into the TX engine. 21143, Macronix, 1012 * PNIC, PNIC II and Davicom chips are programmed this way. 1013 * 1014 * We always program the chip using 'hash perfect' mode, i.e. one perfect 1015 * address (our node address) and a 512-bit hash filter for multicast 1016 * frames. We also sneak the broadcast address into the hash filter since 1017 * we need that too. 1018 */ 1019 void dc_setfilt_21143(sc) 1020 struct dc_softc *sc; 1021 { 1022 struct dc_desc *sframe; 1023 u_int32_t h, *sp; 1024 struct ifmultiaddr *ifma; 1025 struct ifnet *ifp; 1026 int i; 1027 1028 ifp = &sc->arpcom.ac_if; 1029 1030 i = sc->dc_cdata.dc_tx_prod; 1031 DC_INC(sc->dc_cdata.dc_tx_prod, DC_TX_LIST_CNT); 1032 sc->dc_cdata.dc_tx_cnt++; 1033 sframe = &sc->dc_ldata->dc_tx_list[i]; 1034 sp = (u_int32_t *)&sc->dc_cdata.dc_sbuf; 1035 bzero((char *)sp, DC_SFRAME_LEN); 1036 1037 sframe->dc_data = vtophys(&sc->dc_cdata.dc_sbuf); 1038 sframe->dc_ctl = DC_SFRAME_LEN | DC_TXCTL_SETUP | DC_TXCTL_TLINK | 1039 DC_FILTER_HASHPERF | DC_TXCTL_FINT; 1040 1041 sc->dc_cdata.dc_tx_chain[i] = (struct mbuf *)&sc->dc_cdata.dc_sbuf; 1042 1043 /* If we want promiscuous mode, set the allframes bit. */ 1044 if (ifp->if_flags & IFF_PROMISC) 1045 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC); 1046 else 1047 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC); 1048 1049 if (ifp->if_flags & IFF_ALLMULTI) 1050 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI); 1051 else 1052 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI); 1053 1054 for (ifma = ifp->if_multiaddrs.lh_first; ifma != NULL; 1055 ifma = ifma->ifma_link.le_next) { 1056 if (ifma->ifma_addr->sa_family != AF_LINK) 1057 continue; 1058 h = dc_crc_le(sc, 1059 LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 1060 sp[h >> 4] |= 1 << (h & 0xF); 1061 } 1062 1063 if (ifp->if_flags & IFF_BROADCAST) { 1064 h = dc_crc_le(sc, (caddr_t)ðerbroadcastaddr); 1065 sp[h >> 4] |= 1 << (h & 0xF); 1066 } 1067 1068 /* Set our MAC address */ 1069 sp[39] = ((u_int16_t *)sc->arpcom.ac_enaddr)[0]; 1070 sp[40] = ((u_int16_t *)sc->arpcom.ac_enaddr)[1]; 1071 sp[41] = ((u_int16_t *)sc->arpcom.ac_enaddr)[2]; 1072 1073 sframe->dc_status = DC_TXSTAT_OWN; 1074 CSR_WRITE_4(sc, DC_TXSTART, 0xFFFFFFFF); 1075 1076 /* 1077 * The PNIC takes an exceedingly long time to process its 1078 * setup frame; wait 10ms after posting the setup frame 1079 * before proceeding, just so it has time to swallow its 1080 * medicine. 1081 */ 1082 DELAY(10000); 1083 1084 ifp->if_timer = 5; 1085 1086 return; 1087 } 1088 1089 void dc_setfilt_admtek(sc) 1090 struct dc_softc *sc; 1091 { 1092 struct ifnet *ifp; 1093 int h = 0; 1094 u_int32_t hashes[2] = { 0, 0 }; 1095 struct ifmultiaddr *ifma; 1096 1097 ifp = &sc->arpcom.ac_if; 1098 1099 /* Init our MAC address */ 1100 CSR_WRITE_4(sc, DC_AL_PAR0, *(u_int32_t *)(&sc->arpcom.ac_enaddr[0])); 1101 CSR_WRITE_4(sc, DC_AL_PAR1, *(u_int32_t *)(&sc->arpcom.ac_enaddr[4])); 1102 1103 /* If we want promiscuous mode, set the allframes bit. */ 1104 if (ifp->if_flags & IFF_PROMISC) 1105 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC); 1106 else 1107 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC); 1108 1109 if (ifp->if_flags & IFF_ALLMULTI) 1110 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI); 1111 else 1112 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI); 1113 1114 /* first, zot all the existing hash bits */ 1115 CSR_WRITE_4(sc, DC_AL_MAR0, 0); 1116 CSR_WRITE_4(sc, DC_AL_MAR1, 0); 1117 1118 /* 1119 * If we're already in promisc or allmulti mode, we 1120 * don't have to bother programming the multicast filter. 1121 */ 1122 if (ifp->if_flags & (IFF_PROMISC|IFF_ALLMULTI)) 1123 return; 1124 1125 /* now program new ones */ 1126 for (ifma = ifp->if_multiaddrs.lh_first; ifma != NULL; 1127 ifma = ifma->ifma_link.le_next) { 1128 if (ifma->ifma_addr->sa_family != AF_LINK) 1129 continue; 1130 h = dc_crc_be(LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 1131 if (h < 32) 1132 hashes[0] |= (1 << h); 1133 else 1134 hashes[1] |= (1 << (h - 32)); 1135 } 1136 1137 CSR_WRITE_4(sc, DC_AL_MAR0, hashes[0]); 1138 CSR_WRITE_4(sc, DC_AL_MAR1, hashes[1]); 1139 1140 return; 1141 } 1142 1143 void dc_setfilt_asix(sc) 1144 struct dc_softc *sc; 1145 { 1146 struct ifnet *ifp; 1147 int h = 0; 1148 u_int32_t hashes[2] = { 0, 0 }; 1149 struct ifmultiaddr *ifma; 1150 1151 ifp = &sc->arpcom.ac_if; 1152 1153 /* Init our MAC address */ 1154 CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_PAR0); 1155 CSR_WRITE_4(sc, DC_AX_FILTDATA, 1156 *(u_int32_t *)(&sc->arpcom.ac_enaddr[0])); 1157 CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_PAR1); 1158 CSR_WRITE_4(sc, DC_AX_FILTDATA, 1159 *(u_int32_t *)(&sc->arpcom.ac_enaddr[4])); 1160 1161 /* If we want promiscuous mode, set the allframes bit. */ 1162 if (ifp->if_flags & IFF_PROMISC) 1163 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC); 1164 else 1165 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC); 1166 1167 if (ifp->if_flags & IFF_ALLMULTI) 1168 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI); 1169 else 1170 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI); 1171 1172 /* 1173 * The ASIX chip has a special bit to enable reception 1174 * of broadcast frames. 1175 */ 1176 if (ifp->if_flags & IFF_BROADCAST) 1177 DC_SETBIT(sc, DC_NETCFG, DC_AX_NETCFG_RX_BROAD); 1178 else 1179 DC_CLRBIT(sc, DC_NETCFG, DC_AX_NETCFG_RX_BROAD); 1180 1181 /* first, zot all the existing hash bits */ 1182 CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_MAR0); 1183 CSR_WRITE_4(sc, DC_AX_FILTDATA, 0); 1184 CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_MAR1); 1185 CSR_WRITE_4(sc, DC_AX_FILTDATA, 0); 1186 1187 /* 1188 * If we're already in promisc or allmulti mode, we 1189 * don't have to bother programming the multicast filter. 1190 */ 1191 if (ifp->if_flags & (IFF_PROMISC|IFF_ALLMULTI)) 1192 return; 1193 1194 /* now program new ones */ 1195 for (ifma = ifp->if_multiaddrs.lh_first; ifma != NULL; 1196 ifma = ifma->ifma_link.le_next) { 1197 if (ifma->ifma_addr->sa_family != AF_LINK) 1198 continue; 1199 h = dc_crc_be(LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 1200 if (h < 32) 1201 hashes[0] |= (1 << h); 1202 else 1203 hashes[1] |= (1 << (h - 32)); 1204 } 1205 1206 CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_MAR0); 1207 CSR_WRITE_4(sc, DC_AX_FILTDATA, hashes[0]); 1208 CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_MAR1); 1209 CSR_WRITE_4(sc, DC_AX_FILTDATA, hashes[1]); 1210 1211 return; 1212 } 1213 1214 void dc_setfilt_xircom(sc) 1215 struct dc_softc *sc; 1216 { 1217 struct dc_desc *sframe; 1218 u_int32_t h, *sp; 1219 struct ifmultiaddr *ifma; 1220 struct ifnet *ifp; 1221 int i; 1222 1223 ifp = &sc->arpcom.ac_if; 1224 DC_CLRBIT(sc, DC_NETCFG, (DC_NETCFG_TX_ON|DC_NETCFG_RX_ON)); 1225 1226 i = sc->dc_cdata.dc_tx_prod; 1227 DC_INC(sc->dc_cdata.dc_tx_prod, DC_TX_LIST_CNT); 1228 sc->dc_cdata.dc_tx_cnt++; 1229 sframe = &sc->dc_ldata->dc_tx_list[i]; 1230 sp = (u_int32_t *)&sc->dc_cdata.dc_sbuf; 1231 bzero((char *)sp, DC_SFRAME_LEN); 1232 1233 sframe->dc_data = vtophys(&sc->dc_cdata.dc_sbuf); 1234 sframe->dc_ctl = DC_SFRAME_LEN | DC_TXCTL_SETUP | DC_TXCTL_TLINK | 1235 DC_FILTER_HASHPERF | DC_TXCTL_FINT; 1236 1237 sc->dc_cdata.dc_tx_chain[i] = (struct mbuf *)&sc->dc_cdata.dc_sbuf; 1238 1239 /* If we want promiscuous mode, set the allframes bit. */ 1240 if (ifp->if_flags & IFF_PROMISC) 1241 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC); 1242 else 1243 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC); 1244 1245 if (ifp->if_flags & IFF_ALLMULTI) 1246 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI); 1247 else 1248 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI); 1249 1250 for (ifma = ifp->if_multiaddrs.lh_first; ifma != NULL; 1251 ifma = ifma->ifma_link.le_next) { 1252 if (ifma->ifma_addr->sa_family != AF_LINK) 1253 continue; 1254 h = dc_crc_le(sc, 1255 LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 1256 sp[h >> 4] |= 1 << (h & 0xF); 1257 } 1258 1259 if (ifp->if_flags & IFF_BROADCAST) { 1260 h = dc_crc_le(sc, (caddr_t)ðerbroadcastaddr); 1261 sp[h >> 4] |= 1 << (h & 0xF); 1262 } 1263 1264 /* Set our MAC address */ 1265 sp[0] = ((u_int16_t *)sc->arpcom.ac_enaddr)[0]; 1266 sp[1] = ((u_int16_t *)sc->arpcom.ac_enaddr)[1]; 1267 sp[2] = ((u_int16_t *)sc->arpcom.ac_enaddr)[2]; 1268 1269 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_TX_ON); 1270 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_ON); 1271 ifp->if_flags |= IFF_RUNNING; 1272 sframe->dc_status = DC_TXSTAT_OWN; 1273 CSR_WRITE_4(sc, DC_TXSTART, 0xFFFFFFFF); 1274 1275 /* 1276 * wait some time... 1277 */ 1278 DELAY(1000); 1279 1280 ifp->if_timer = 5; 1281 1282 return; 1283 } 1284 1285 static void dc_setfilt(sc) 1286 struct dc_softc *sc; 1287 { 1288 if (DC_IS_INTEL(sc) || DC_IS_MACRONIX(sc) || DC_IS_PNIC(sc) || 1289 DC_IS_PNICII(sc) || DC_IS_DAVICOM(sc)) 1290 dc_setfilt_21143(sc); 1291 1292 if (DC_IS_ASIX(sc)) 1293 dc_setfilt_asix(sc); 1294 1295 if (DC_IS_ADMTEK(sc)) 1296 dc_setfilt_admtek(sc); 1297 1298 if (DC_IS_XIRCOM(sc)) 1299 dc_setfilt_xircom(sc); 1300 1301 return; 1302 } 1303 1304 /* 1305 * In order to fiddle with the 1306 * 'full-duplex' and '100Mbps' bits in the netconfig register, we 1307 * first have to put the transmit and/or receive logic in the idle state. 1308 */ 1309 static void dc_setcfg(sc, media) 1310 struct dc_softc *sc; 1311 int media; 1312 { 1313 int i, restart = 0; 1314 u_int32_t isr; 1315 1316 if (IFM_SUBTYPE(media) == IFM_NONE) 1317 return; 1318 1319 if (CSR_READ_4(sc, DC_NETCFG) & (DC_NETCFG_TX_ON|DC_NETCFG_RX_ON)) { 1320 restart = 1; 1321 DC_CLRBIT(sc, DC_NETCFG, (DC_NETCFG_TX_ON|DC_NETCFG_RX_ON)); 1322 1323 for (i = 0; i < DC_TIMEOUT; i++) { 1324 DELAY(10); 1325 isr = CSR_READ_4(sc, DC_ISR); 1326 if (isr & DC_ISR_TX_IDLE || 1327 (isr & DC_ISR_RX_STATE) == DC_RXSTATE_STOPPED) 1328 break; 1329 } 1330 1331 if (i == DC_TIMEOUT) 1332 printf("dc%d: failed to force tx and " 1333 "rx to idle state\n", sc->dc_unit); 1334 1335 } 1336 1337 if (IFM_SUBTYPE(media) == IFM_100_TX) { 1338 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_SPEEDSEL); 1339 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_HEARTBEAT); 1340 if (sc->dc_pmode == DC_PMODE_MII) { 1341 int watchdogreg; 1342 1343 if (DC_IS_INTEL(sc)) { 1344 /* there's a write enable bit here that reads as 1 */ 1345 watchdogreg = CSR_READ_4(sc, DC_WATCHDOG); 1346 watchdogreg &= ~DC_WDOG_CTLWREN; 1347 watchdogreg |= DC_WDOG_JABBERDIS; 1348 CSR_WRITE_4(sc, DC_WATCHDOG, watchdogreg); 1349 } else { 1350 DC_SETBIT(sc, DC_WATCHDOG, DC_WDOG_JABBERDIS); 1351 } 1352 DC_CLRBIT(sc, DC_NETCFG, (DC_NETCFG_PCS| 1353 DC_NETCFG_PORTSEL|DC_NETCFG_SCRAMBLER)); 1354 if (sc->dc_type == DC_TYPE_98713) 1355 DC_SETBIT(sc, DC_NETCFG, (DC_NETCFG_PCS| 1356 DC_NETCFG_SCRAMBLER)); 1357 if (!DC_IS_DAVICOM(sc)) 1358 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL); 1359 DC_CLRBIT(sc, DC_10BTCTRL, 0xFFFF); 1360 if (DC_IS_INTEL(sc)) 1361 dc_apply_fixup(sc, IFM_AUTO); 1362 } else { 1363 if (DC_IS_PNIC(sc)) { 1364 DC_PN_GPIO_SETBIT(sc, DC_PN_GPIO_SPEEDSEL); 1365 DC_PN_GPIO_SETBIT(sc, DC_PN_GPIO_100TX_LOOP); 1366 DC_SETBIT(sc, DC_PN_NWAY, DC_PN_NWAY_SPEEDSEL); 1367 } 1368 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL); 1369 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PCS); 1370 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_SCRAMBLER); 1371 if (DC_IS_INTEL(sc)) 1372 dc_apply_fixup(sc, 1373 (media & IFM_GMASK) == IFM_FDX ? 1374 IFM_100_TX|IFM_FDX : IFM_100_TX); 1375 } 1376 } 1377 1378 if (IFM_SUBTYPE(media) == IFM_10_T) { 1379 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_SPEEDSEL); 1380 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_HEARTBEAT); 1381 if (sc->dc_pmode == DC_PMODE_MII) { 1382 int watchdogreg; 1383 1384 /* there's a write enable bit here that reads as 1 */ 1385 if (DC_IS_INTEL(sc)) { 1386 watchdogreg = CSR_READ_4(sc, DC_WATCHDOG); 1387 watchdogreg &= ~DC_WDOG_CTLWREN; 1388 watchdogreg |= DC_WDOG_JABBERDIS; 1389 CSR_WRITE_4(sc, DC_WATCHDOG, watchdogreg); 1390 } else { 1391 DC_SETBIT(sc, DC_WATCHDOG, DC_WDOG_JABBERDIS); 1392 } 1393 DC_CLRBIT(sc, DC_NETCFG, (DC_NETCFG_PCS| 1394 DC_NETCFG_PORTSEL|DC_NETCFG_SCRAMBLER)); 1395 if (sc->dc_type == DC_TYPE_98713) 1396 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PCS); 1397 if (!DC_IS_DAVICOM(sc)) 1398 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL); 1399 DC_CLRBIT(sc, DC_10BTCTRL, 0xFFFF); 1400 if (DC_IS_INTEL(sc)) 1401 dc_apply_fixup(sc, IFM_AUTO); 1402 } else { 1403 if (DC_IS_PNIC(sc)) { 1404 DC_PN_GPIO_CLRBIT(sc, DC_PN_GPIO_SPEEDSEL); 1405 DC_PN_GPIO_SETBIT(sc, DC_PN_GPIO_100TX_LOOP); 1406 DC_CLRBIT(sc, DC_PN_NWAY, DC_PN_NWAY_SPEEDSEL); 1407 } 1408 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL); 1409 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_PCS); 1410 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_SCRAMBLER); 1411 if (DC_IS_INTEL(sc)) { 1412 DC_CLRBIT(sc, DC_SIARESET, DC_SIA_RESET); 1413 DC_CLRBIT(sc, DC_10BTCTRL, 0xFFFF); 1414 if ((media & IFM_GMASK) == IFM_FDX) 1415 DC_SETBIT(sc, DC_10BTCTRL, 0x7F3D); 1416 else 1417 DC_SETBIT(sc, DC_10BTCTRL, 0x7F3F); 1418 DC_SETBIT(sc, DC_SIARESET, DC_SIA_RESET); 1419 DC_CLRBIT(sc, DC_10BTCTRL, 1420 DC_TCTL_AUTONEGENBL); 1421 dc_apply_fixup(sc, 1422 (media & IFM_GMASK) == IFM_FDX ? 1423 IFM_10_T|IFM_FDX : IFM_10_T); 1424 DELAY(20000); 1425 } 1426 } 1427 } 1428 1429 /* 1430 * If this is a Davicom DM9102A card with a DM9801 HomePNA 1431 * PHY and we want HomePNA mode, set the portsel bit to turn 1432 * on the external MII port. 1433 */ 1434 if (DC_IS_DAVICOM(sc)) { 1435 if (IFM_SUBTYPE(media) == IFM_homePNA) { 1436 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL); 1437 sc->dc_link = 1; 1438 } else { 1439 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL); 1440 } 1441 } 1442 1443 if ((media & IFM_GMASK) == IFM_FDX) { 1444 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_FULLDUPLEX); 1445 if (sc->dc_pmode == DC_PMODE_SYM && DC_IS_PNIC(sc)) 1446 DC_SETBIT(sc, DC_PN_NWAY, DC_PN_NWAY_DUPLEX); 1447 } else { 1448 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_FULLDUPLEX); 1449 if (sc->dc_pmode == DC_PMODE_SYM && DC_IS_PNIC(sc)) 1450 DC_CLRBIT(sc, DC_PN_NWAY, DC_PN_NWAY_DUPLEX); 1451 } 1452 1453 if (restart) 1454 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_TX_ON|DC_NETCFG_RX_ON); 1455 1456 return; 1457 } 1458 1459 static void dc_reset(sc) 1460 struct dc_softc *sc; 1461 { 1462 register int i; 1463 1464 DC_SETBIT(sc, DC_BUSCTL, DC_BUSCTL_RESET); 1465 1466 for (i = 0; i < DC_TIMEOUT; i++) { 1467 DELAY(10); 1468 if (!(CSR_READ_4(sc, DC_BUSCTL) & DC_BUSCTL_RESET)) 1469 break; 1470 } 1471 1472 if (DC_IS_ASIX(sc) || DC_IS_ADMTEK(sc) || 1473 DC_IS_XIRCOM(sc) || DC_IS_INTEL(sc)) { 1474 DELAY(10000); 1475 DC_CLRBIT(sc, DC_BUSCTL, DC_BUSCTL_RESET); 1476 i = 0; 1477 } 1478 1479 if (i == DC_TIMEOUT) 1480 printf("dc%d: reset never completed!\n", sc->dc_unit); 1481 1482 /* Wait a little while for the chip to get its brains in order. */ 1483 DELAY(1000); 1484 1485 CSR_WRITE_4(sc, DC_IMR, 0x00000000); 1486 CSR_WRITE_4(sc, DC_BUSCTL, 0x00000000); 1487 CSR_WRITE_4(sc, DC_NETCFG, 0x00000000); 1488 1489 /* 1490 * Bring the SIA out of reset. In some cases, it looks 1491 * like failing to unreset the SIA soon enough gets it 1492 * into a state where it will never come out of reset 1493 * until we reset the whole chip again. 1494 */ 1495 if (DC_IS_INTEL(sc)) { 1496 DC_SETBIT(sc, DC_SIARESET, DC_SIA_RESET); 1497 CSR_WRITE_4(sc, DC_10BTCTRL, 0); 1498 CSR_WRITE_4(sc, DC_WATCHDOG, 0); 1499 } 1500 1501 return; 1502 } 1503 1504 static struct dc_type *dc_devtype(dev) 1505 device_t dev; 1506 { 1507 struct dc_type *t; 1508 u_int32_t rev; 1509 1510 t = dc_devs; 1511 1512 while(t->dc_name != NULL) { 1513 if ((pci_get_vendor(dev) == t->dc_vid) && 1514 (pci_get_device(dev) == t->dc_did)) { 1515 /* Check the PCI revision */ 1516 rev = pci_read_config(dev, DC_PCI_CFRV, 4) & 0xFF; 1517 if (t->dc_did == DC_DEVICEID_98713 && 1518 rev >= DC_REVISION_98713A) 1519 t++; 1520 if (t->dc_did == DC_DEVICEID_98713_CP && 1521 rev >= DC_REVISION_98713A) 1522 t++; 1523 if (t->dc_did == DC_DEVICEID_987x5 && 1524 rev >= DC_REVISION_98715AEC_C) 1525 t++; 1526 if (t->dc_did == DC_DEVICEID_987x5 && 1527 rev >= DC_REVISION_98725) 1528 t++; 1529 if (t->dc_did == DC_DEVICEID_AX88140A && 1530 rev >= DC_REVISION_88141) 1531 t++; 1532 if (t->dc_did == DC_DEVICEID_82C168 && 1533 rev >= DC_REVISION_82C169) 1534 t++; 1535 if (t->dc_did == DC_DEVICEID_DM9102 && 1536 rev >= DC_REVISION_DM9102A) 1537 t++; 1538 return(t); 1539 } 1540 t++; 1541 } 1542 1543 return(NULL); 1544 } 1545 1546 /* 1547 * Probe for a 21143 or clone chip. Check the PCI vendor and device 1548 * IDs against our list and return a device name if we find a match. 1549 * We do a little bit of extra work to identify the exact type of 1550 * chip. The MX98713 and MX98713A have the same PCI vendor/device ID, 1551 * but different revision IDs. The same is true for 98715/98715A 1552 * chips and the 98725, as well as the ASIX and ADMtek chips. In some 1553 * cases, the exact chip revision affects driver behavior. 1554 */ 1555 static int dc_probe(dev) 1556 device_t dev; 1557 { 1558 struct dc_type *t; 1559 1560 t = dc_devtype(dev); 1561 1562 if (t != NULL) { 1563 device_set_desc(dev, t->dc_name); 1564 return(0); 1565 } 1566 1567 return(ENXIO); 1568 } 1569 1570 static void dc_acpi(dev) 1571 device_t dev; 1572 { 1573 int unit; 1574 1575 unit = device_get_unit(dev); 1576 1577 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) { 1578 u_int32_t iobase, membase, irq; 1579 1580 /* Save important PCI config data. */ 1581 iobase = pci_read_config(dev, DC_PCI_CFBIO, 4); 1582 membase = pci_read_config(dev, DC_PCI_CFBMA, 4); 1583 irq = pci_read_config(dev, DC_PCI_CFIT, 4); 1584 1585 /* Reset the power state. */ 1586 printf("dc%d: chip is in D%d power mode " 1587 "-- setting to D0\n", unit, 1588 pci_get_powerstate(dev)); 1589 pci_set_powerstate(dev, PCI_POWERSTATE_D0); 1590 1591 /* Restore PCI config data. */ 1592 pci_write_config(dev, DC_PCI_CFBIO, iobase, 4); 1593 pci_write_config(dev, DC_PCI_CFBMA, membase, 4); 1594 pci_write_config(dev, DC_PCI_CFIT, irq, 4); 1595 } 1596 1597 return; 1598 } 1599 1600 static void dc_apply_fixup(sc, media) 1601 struct dc_softc *sc; 1602 int media; 1603 { 1604 struct dc_mediainfo *m; 1605 u_int8_t *p; 1606 int i; 1607 u_int32_t reg; 1608 1609 m = sc->dc_mi; 1610 1611 while (m != NULL) { 1612 if (m->dc_media == media) 1613 break; 1614 m = m->dc_next; 1615 } 1616 1617 if (m == NULL) 1618 return; 1619 1620 for (i = 0, p = m->dc_reset_ptr; i < m->dc_reset_len; i++, p += 2) { 1621 reg = (p[0] | (p[1] << 8)) << 16; 1622 CSR_WRITE_4(sc, DC_WATCHDOG, reg); 1623 } 1624 1625 for (i = 0, p = m->dc_gp_ptr; i < m->dc_gp_len; i++, p += 2) { 1626 reg = (p[0] | (p[1] << 8)) << 16; 1627 CSR_WRITE_4(sc, DC_WATCHDOG, reg); 1628 } 1629 1630 return; 1631 } 1632 1633 static void dc_decode_leaf_sia(sc, l) 1634 struct dc_softc *sc; 1635 struct dc_eblock_sia *l; 1636 { 1637 struct dc_mediainfo *m; 1638 1639 m = malloc(sizeof(struct dc_mediainfo), M_DEVBUF, M_NOWAIT); 1640 bzero(m, sizeof(struct dc_mediainfo)); 1641 if (l->dc_sia_code == DC_SIA_CODE_10BT) 1642 m->dc_media = IFM_10_T; 1643 1644 if (l->dc_sia_code == DC_SIA_CODE_10BT_FDX) 1645 m->dc_media = IFM_10_T|IFM_FDX; 1646 1647 if (l->dc_sia_code == DC_SIA_CODE_10B2) 1648 m->dc_media = IFM_10_2; 1649 1650 if (l->dc_sia_code == DC_SIA_CODE_10B5) 1651 m->dc_media = IFM_10_5; 1652 1653 m->dc_gp_len = 2; 1654 m->dc_gp_ptr = (u_int8_t *)&l->dc_sia_gpio_ctl; 1655 1656 m->dc_next = sc->dc_mi; 1657 sc->dc_mi = m; 1658 1659 sc->dc_pmode = DC_PMODE_SIA; 1660 1661 return; 1662 } 1663 1664 static void dc_decode_leaf_sym(sc, l) 1665 struct dc_softc *sc; 1666 struct dc_eblock_sym *l; 1667 { 1668 struct dc_mediainfo *m; 1669 1670 m = malloc(sizeof(struct dc_mediainfo), M_DEVBUF, M_NOWAIT); 1671 bzero(m, sizeof(struct dc_mediainfo)); 1672 if (l->dc_sym_code == DC_SYM_CODE_100BT) 1673 m->dc_media = IFM_100_TX; 1674 1675 if (l->dc_sym_code == DC_SYM_CODE_100BT_FDX) 1676 m->dc_media = IFM_100_TX|IFM_FDX; 1677 1678 m->dc_gp_len = 2; 1679 m->dc_gp_ptr = (u_int8_t *)&l->dc_sym_gpio_ctl; 1680 1681 m->dc_next = sc->dc_mi; 1682 sc->dc_mi = m; 1683 1684 sc->dc_pmode = DC_PMODE_SYM; 1685 1686 return; 1687 } 1688 1689 static void dc_decode_leaf_mii(sc, l) 1690 struct dc_softc *sc; 1691 struct dc_eblock_mii *l; 1692 { 1693 u_int8_t *p; 1694 struct dc_mediainfo *m; 1695 1696 m = malloc(sizeof(struct dc_mediainfo), M_DEVBUF, M_NOWAIT); 1697 bzero(m, sizeof(struct dc_mediainfo)); 1698 /* We abuse IFM_AUTO to represent MII. */ 1699 m->dc_media = IFM_AUTO; 1700 m->dc_gp_len = l->dc_gpr_len; 1701 1702 p = (u_int8_t *)l; 1703 p += sizeof(struct dc_eblock_mii); 1704 m->dc_gp_ptr = p; 1705 p += 2 * l->dc_gpr_len; 1706 m->dc_reset_len = *p; 1707 p++; 1708 m->dc_reset_ptr = p; 1709 1710 m->dc_next = sc->dc_mi; 1711 sc->dc_mi = m; 1712 1713 return; 1714 } 1715 1716 static void dc_parse_21143_srom(sc) 1717 struct dc_softc *sc; 1718 { 1719 struct dc_leaf_hdr *lhdr; 1720 struct dc_eblock_hdr *hdr; 1721 int i, loff; 1722 char *ptr; 1723 1724 loff = sc->dc_srom[27]; 1725 lhdr = (struct dc_leaf_hdr *)&(sc->dc_srom[loff]); 1726 1727 ptr = (char *)lhdr; 1728 ptr += sizeof(struct dc_leaf_hdr) - 1; 1729 for (i = 0; i < lhdr->dc_mcnt; i++) { 1730 hdr = (struct dc_eblock_hdr *)ptr; 1731 switch(hdr->dc_type) { 1732 case DC_EBLOCK_MII: 1733 dc_decode_leaf_mii(sc, (struct dc_eblock_mii *)hdr); 1734 break; 1735 case DC_EBLOCK_SIA: 1736 dc_decode_leaf_sia(sc, (struct dc_eblock_sia *)hdr); 1737 break; 1738 case DC_EBLOCK_SYM: 1739 dc_decode_leaf_sym(sc, (struct dc_eblock_sym *)hdr); 1740 break; 1741 default: 1742 /* Don't care. Yet. */ 1743 break; 1744 } 1745 ptr += (hdr->dc_len & 0x7F); 1746 ptr++; 1747 } 1748 1749 return; 1750 } 1751 1752 /* 1753 * Attach the interface. Allocate softc structures, do ifmedia 1754 * setup and ethernet/BPF attach. 1755 */ 1756 static int dc_attach(dev) 1757 device_t dev; 1758 { 1759 int tmp = 0; 1760 u_char eaddr[ETHER_ADDR_LEN]; 1761 u_int32_t command; 1762 struct dc_softc *sc; 1763 struct ifnet *ifp; 1764 u_int32_t revision; 1765 int unit, error = 0, rid, mac_offset; 1766 1767 sc = device_get_softc(dev); 1768 unit = device_get_unit(dev); 1769 bzero(sc, sizeof(struct dc_softc)); 1770 1771 mtx_init(&sc->dc_mtx, device_get_nameunit(dev), MTX_DEF | MTX_RECURSE); 1772 DC_LOCK(sc); 1773 1774 /* 1775 * Handle power management nonsense. 1776 */ 1777 dc_acpi(dev); 1778 1779 /* 1780 * Map control/status registers. 1781 */ 1782 command = pci_read_config(dev, PCIR_COMMAND, 4); 1783 command |= (PCIM_CMD_PORTEN|PCIM_CMD_MEMEN|PCIM_CMD_BUSMASTEREN); 1784 pci_write_config(dev, PCIR_COMMAND, command, 4); 1785 command = pci_read_config(dev, PCIR_COMMAND, 4); 1786 1787 #ifdef DC_USEIOSPACE 1788 if (!(command & PCIM_CMD_PORTEN)) { 1789 printf("dc%d: failed to enable I/O ports!\n", unit); 1790 error = ENXIO; 1791 goto fail; 1792 } 1793 #else 1794 if (!(command & PCIM_CMD_MEMEN)) { 1795 printf("dc%d: failed to enable memory mapping!\n", unit); 1796 error = ENXIO; 1797 goto fail; 1798 } 1799 #endif 1800 1801 rid = DC_RID; 1802 sc->dc_res = bus_alloc_resource(dev, DC_RES, &rid, 1803 0, ~0, 1, RF_ACTIVE); 1804 1805 if (sc->dc_res == NULL) { 1806 printf("dc%d: couldn't map ports/memory\n", unit); 1807 error = ENXIO; 1808 goto fail; 1809 } 1810 1811 sc->dc_btag = rman_get_bustag(sc->dc_res); 1812 sc->dc_bhandle = rman_get_bushandle(sc->dc_res); 1813 1814 /* Allocate interrupt */ 1815 rid = 0; 1816 sc->dc_irq = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, 0, ~0, 1, 1817 RF_SHAREABLE | RF_ACTIVE); 1818 1819 if (sc->dc_irq == NULL) { 1820 printf("dc%d: couldn't map interrupt\n", unit); 1821 bus_release_resource(dev, DC_RES, DC_RID, sc->dc_res); 1822 error = ENXIO; 1823 goto fail; 1824 } 1825 1826 error = bus_setup_intr(dev, sc->dc_irq, INTR_TYPE_NET | 1827 (IS_MPSAFE ? INTR_MPSAFE : 0), 1828 dc_intr, sc, &sc->dc_intrhand); 1829 1830 if (error) { 1831 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->dc_irq); 1832 bus_release_resource(dev, DC_RES, DC_RID, sc->dc_res); 1833 printf("dc%d: couldn't set up irq\n", unit); 1834 goto fail; 1835 } 1836 1837 /* Need this info to decide on a chip type. */ 1838 sc->dc_info = dc_devtype(dev); 1839 revision = pci_read_config(dev, DC_PCI_CFRV, 4) & 0x000000FF; 1840 1841 switch(sc->dc_info->dc_did) { 1842 case DC_DEVICEID_21143: 1843 sc->dc_type = DC_TYPE_21143; 1844 sc->dc_flags |= DC_TX_POLL|DC_TX_USE_TX_INTR; 1845 sc->dc_flags |= DC_REDUCED_MII_POLL; 1846 /* Save EEPROM contents so we can parse them later. */ 1847 dc_read_eeprom(sc, (caddr_t)&sc->dc_srom, 0, 512, 0); 1848 break; 1849 case DC_DEVICEID_DM9100: 1850 case DC_DEVICEID_DM9102: 1851 sc->dc_type = DC_TYPE_DM9102; 1852 sc->dc_flags |= DC_TX_COALESCE|DC_TX_INTR_ALWAYS; 1853 sc->dc_flags |= DC_REDUCED_MII_POLL|DC_TX_STORENFWD; 1854 sc->dc_pmode = DC_PMODE_MII; 1855 /* Increase the latency timer value. */ 1856 command = pci_read_config(dev, DC_PCI_CFLT, 4); 1857 command &= 0xFFFF00FF; 1858 command |= 0x00008000; 1859 pci_write_config(dev, DC_PCI_CFLT, command, 4); 1860 break; 1861 case DC_DEVICEID_AL981: 1862 sc->dc_type = DC_TYPE_AL981; 1863 sc->dc_flags |= DC_TX_USE_TX_INTR; 1864 sc->dc_flags |= DC_TX_ADMTEK_WAR; 1865 sc->dc_pmode = DC_PMODE_MII; 1866 break; 1867 case DC_DEVICEID_AN985: 1868 case DC_DEVICEID_FE2500: 1869 case DC_DEVICEID_EN2242: 1870 sc->dc_type = DC_TYPE_AN985; 1871 sc->dc_flags |= DC_TX_USE_TX_INTR; 1872 sc->dc_flags |= DC_TX_ADMTEK_WAR; 1873 sc->dc_pmode = DC_PMODE_MII; 1874 break; 1875 case DC_DEVICEID_98713: 1876 case DC_DEVICEID_98713_CP: 1877 if (revision < DC_REVISION_98713A) { 1878 sc->dc_type = DC_TYPE_98713; 1879 } 1880 if (revision >= DC_REVISION_98713A) { 1881 sc->dc_type = DC_TYPE_98713A; 1882 sc->dc_flags |= DC_21143_NWAY; 1883 } 1884 sc->dc_flags |= DC_REDUCED_MII_POLL; 1885 sc->dc_flags |= DC_TX_POLL|DC_TX_USE_TX_INTR; 1886 break; 1887 case DC_DEVICEID_987x5: 1888 case DC_DEVICEID_EN1217: 1889 /* 1890 * Macronix MX98715AEC-C/D/E parts have only a 1891 * 128-bit hash table. We need to deal with these 1892 * in the same manner as the PNIC II so that we 1893 * get the right number of bits out of the 1894 * CRC routine. 1895 */ 1896 if (revision >= DC_REVISION_98715AEC_C && 1897 revision < DC_REVISION_98725) 1898 sc->dc_flags |= DC_128BIT_HASH; 1899 sc->dc_type = DC_TYPE_987x5; 1900 sc->dc_flags |= DC_TX_POLL|DC_TX_USE_TX_INTR; 1901 sc->dc_flags |= DC_REDUCED_MII_POLL|DC_21143_NWAY; 1902 break; 1903 case DC_DEVICEID_98727: 1904 sc->dc_type = DC_TYPE_987x5; 1905 sc->dc_flags |= DC_TX_POLL|DC_TX_USE_TX_INTR; 1906 sc->dc_flags |= DC_REDUCED_MII_POLL|DC_21143_NWAY; 1907 break; 1908 case DC_DEVICEID_82C115: 1909 sc->dc_type = DC_TYPE_PNICII; 1910 sc->dc_flags |= DC_TX_POLL|DC_TX_USE_TX_INTR|DC_128BIT_HASH; 1911 sc->dc_flags |= DC_REDUCED_MII_POLL|DC_21143_NWAY; 1912 break; 1913 case DC_DEVICEID_82C168: 1914 sc->dc_type = DC_TYPE_PNIC; 1915 sc->dc_flags |= DC_TX_STORENFWD|DC_TX_INTR_ALWAYS; 1916 sc->dc_flags |= DC_PNIC_RX_BUG_WAR; 1917 sc->dc_pnic_rx_buf = malloc(DC_RXLEN * 5, M_DEVBUF, M_NOWAIT); 1918 if (revision < DC_REVISION_82C169) 1919 sc->dc_pmode = DC_PMODE_SYM; 1920 break; 1921 case DC_DEVICEID_AX88140A: 1922 sc->dc_type = DC_TYPE_ASIX; 1923 sc->dc_flags |= DC_TX_USE_TX_INTR|DC_TX_INTR_FIRSTFRAG; 1924 sc->dc_flags |= DC_REDUCED_MII_POLL; 1925 sc->dc_pmode = DC_PMODE_MII; 1926 break; 1927 case DC_DEVICEID_X3201: 1928 sc->dc_type = DC_TYPE_XIRCOM; 1929 sc->dc_flags |= DC_TX_INTR_ALWAYS | DC_TX_COALESCE; 1930 /* 1931 * We don't actually need to coalesce, but we're doing 1932 * it to obtain a double word aligned buffer. 1933 */ 1934 break; 1935 default: 1936 printf("dc%d: unknown device: %x\n", sc->dc_unit, 1937 sc->dc_info->dc_did); 1938 break; 1939 } 1940 1941 /* Save the cache line size. */ 1942 if (DC_IS_DAVICOM(sc)) 1943 sc->dc_cachesize = 0; 1944 else 1945 sc->dc_cachesize = pci_read_config(dev, 1946 DC_PCI_CFLT, 4) & 0xFF; 1947 1948 /* Reset the adapter. */ 1949 dc_reset(sc); 1950 1951 /* Take 21143 out of snooze mode */ 1952 if (DC_IS_INTEL(sc) || DC_IS_XIRCOM(sc)) { 1953 command = pci_read_config(dev, DC_PCI_CFDD, 4); 1954 command &= ~(DC_CFDD_SNOOZE_MODE|DC_CFDD_SLEEP_MODE); 1955 pci_write_config(dev, DC_PCI_CFDD, command, 4); 1956 } 1957 1958 /* 1959 * Try to learn something about the supported media. 1960 * We know that ASIX and ADMtek and Davicom devices 1961 * will *always* be using MII media, so that's a no-brainer. 1962 * The tricky ones are the Macronix/PNIC II and the 1963 * Intel 21143. 1964 */ 1965 if (DC_IS_INTEL(sc)) 1966 dc_parse_21143_srom(sc); 1967 else if (DC_IS_MACRONIX(sc) || DC_IS_PNICII(sc)) { 1968 if (sc->dc_type == DC_TYPE_98713) 1969 sc->dc_pmode = DC_PMODE_MII; 1970 else 1971 sc->dc_pmode = DC_PMODE_SYM; 1972 } else if (!sc->dc_pmode) 1973 sc->dc_pmode = DC_PMODE_MII; 1974 1975 /* 1976 * Get station address from the EEPROM. 1977 */ 1978 switch(sc->dc_type) { 1979 case DC_TYPE_98713: 1980 case DC_TYPE_98713A: 1981 case DC_TYPE_987x5: 1982 case DC_TYPE_PNICII: 1983 dc_read_eeprom(sc, (caddr_t)&mac_offset, 1984 (DC_EE_NODEADDR_OFFSET / 2), 1, 0); 1985 dc_read_eeprom(sc, (caddr_t)&eaddr, (mac_offset / 2), 3, 0); 1986 break; 1987 case DC_TYPE_PNIC: 1988 dc_read_eeprom(sc, (caddr_t)&eaddr, 0, 3, 1); 1989 break; 1990 case DC_TYPE_DM9102: 1991 case DC_TYPE_21143: 1992 case DC_TYPE_ASIX: 1993 dc_read_eeprom(sc, (caddr_t)&eaddr, DC_EE_NODEADDR, 3, 0); 1994 break; 1995 case DC_TYPE_AL981: 1996 case DC_TYPE_AN985: 1997 dc_read_eeprom(sc, (caddr_t)&eaddr, DC_AL_EE_NODEADDR, 3, 0); 1998 break; 1999 case DC_TYPE_XIRCOM: 2000 dc_read_eeprom(sc, (caddr_t)&eaddr, 3, 3, 0); 2001 break; 2002 default: 2003 dc_read_eeprom(sc, (caddr_t)&eaddr, DC_EE_NODEADDR, 3, 0); 2004 break; 2005 } 2006 2007 /* 2008 * A 21143 or clone chip was detected. Inform the world. 2009 */ 2010 printf("dc%d: Ethernet address: %6D\n", unit, eaddr, ":"); 2011 2012 sc->dc_unit = unit; 2013 bcopy(eaddr, (char *)&sc->arpcom.ac_enaddr, ETHER_ADDR_LEN); 2014 2015 sc->dc_ldata = contigmalloc(sizeof(struct dc_list_data), M_DEVBUF, 2016 M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0); 2017 2018 if (sc->dc_ldata == NULL) { 2019 printf("dc%d: no memory for list buffers!\n", unit); 2020 bus_teardown_intr(dev, sc->dc_irq, sc->dc_intrhand); 2021 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->dc_irq); 2022 bus_release_resource(dev, DC_RES, DC_RID, sc->dc_res); 2023 error = ENXIO; 2024 goto fail; 2025 } 2026 2027 bzero(sc->dc_ldata, sizeof(struct dc_list_data)); 2028 2029 ifp = &sc->arpcom.ac_if; 2030 ifp->if_softc = sc; 2031 ifp->if_unit = unit; 2032 ifp->if_name = "dc"; 2033 /* XXX: bleah, MTU gets overwritten in ether_ifattach() */ 2034 ifp->if_mtu = ETHERMTU; 2035 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 2036 ifp->if_ioctl = dc_ioctl; 2037 ifp->if_output = ether_output; 2038 ifp->if_start = dc_start; 2039 ifp->if_watchdog = dc_watchdog; 2040 ifp->if_init = dc_init; 2041 ifp->if_baudrate = 10000000; 2042 ifp->if_snd.ifq_maxlen = DC_TX_LIST_CNT - 1; 2043 ifp->if_mpsafe = IS_MPSAFE; 2044 2045 /* 2046 * Do MII setup. If this is a 21143, check for a PHY on the 2047 * MII bus after applying any necessary fixups to twiddle the 2048 * GPIO bits. If we don't end up finding a PHY, restore the 2049 * old selection (SIA only or SIA/SYM) and attach the dcphy 2050 * driver instead. 2051 */ 2052 if (DC_IS_INTEL(sc)) { 2053 dc_apply_fixup(sc, IFM_AUTO); 2054 tmp = sc->dc_pmode; 2055 sc->dc_pmode = DC_PMODE_MII; 2056 } 2057 2058 error = mii_phy_probe(dev, &sc->dc_miibus, 2059 dc_ifmedia_upd, dc_ifmedia_sts); 2060 2061 if (error && DC_IS_INTEL(sc)) { 2062 sc->dc_pmode = tmp; 2063 if (sc->dc_pmode != DC_PMODE_SIA) 2064 sc->dc_pmode = DC_PMODE_SYM; 2065 sc->dc_flags |= DC_21143_NWAY; 2066 mii_phy_probe(dev, &sc->dc_miibus, 2067 dc_ifmedia_upd, dc_ifmedia_sts); 2068 /* 2069 * For non-MII cards, we need to have the 21143 2070 * drive the LEDs. Except there are some systems 2071 * like the NEC VersaPro NoteBook PC which have no 2072 * LEDs, and twiddling these bits has adverse effects 2073 * on them. (I.e. you suddenly can't get a link.) 2074 */ 2075 if (pci_read_config(dev, DC_PCI_CSID, 4) != 0x80281033) 2076 sc->dc_flags |= DC_TULIP_LEDS; 2077 error = 0; 2078 } 2079 2080 if (error) { 2081 printf("dc%d: MII without any PHY!\n", sc->dc_unit); 2082 bus_teardown_intr(dev, sc->dc_irq, sc->dc_intrhand); 2083 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->dc_irq); 2084 bus_release_resource(dev, DC_RES, DC_RID, sc->dc_res); 2085 error = ENXIO; 2086 goto fail; 2087 } 2088 2089 if (DC_IS_XIRCOM(sc)) { 2090 /* 2091 * setup General Purpose Port mode and data so the tulip 2092 * can talk to the MII. 2093 */ 2094 CSR_WRITE_4(sc, DC_SIAGP, DC_SIAGP_WRITE_EN | DC_SIAGP_INT1_EN | 2095 DC_SIAGP_MD_GP2_OUTPUT | DC_SIAGP_MD_GP0_OUTPUT); 2096 DELAY(10); 2097 CSR_WRITE_4(sc, DC_SIAGP, DC_SIAGP_INT1_EN | 2098 DC_SIAGP_MD_GP2_OUTPUT | DC_SIAGP_MD_GP0_OUTPUT); 2099 DELAY(10); 2100 } 2101 2102 /* 2103 * Call MI attach routine. 2104 */ 2105 ether_ifattach(ifp, ETHER_BPF_SUPPORTED); 2106 callout_init(&sc->dc_stat_ch, IS_MPSAFE); 2107 2108 #ifdef SRM_MEDIA 2109 sc->dc_srm_media = 0; 2110 2111 /* Remember the SRM console media setting */ 2112 if (DC_IS_INTEL(sc)) { 2113 command = pci_read_config(dev, DC_PCI_CFDD, 4); 2114 command &= ~(DC_CFDD_SNOOZE_MODE|DC_CFDD_SLEEP_MODE); 2115 switch ((command >> 8) & 0xff) { 2116 case 3: 2117 sc->dc_srm_media = IFM_10_T; 2118 break; 2119 case 4: 2120 sc->dc_srm_media = IFM_10_T | IFM_FDX; 2121 break; 2122 case 5: 2123 sc->dc_srm_media = IFM_100_TX; 2124 break; 2125 case 6: 2126 sc->dc_srm_media = IFM_100_TX | IFM_FDX; 2127 break; 2128 } 2129 if (sc->dc_srm_media) 2130 sc->dc_srm_media |= IFM_ACTIVE | IFM_ETHER; 2131 } 2132 #endif 2133 2134 DC_UNLOCK(sc); 2135 return(0); 2136 2137 fail: 2138 DC_UNLOCK(sc); 2139 mtx_destroy(&sc->dc_mtx); 2140 return(error); 2141 } 2142 2143 static int dc_detach(dev) 2144 device_t dev; 2145 { 2146 struct dc_softc *sc; 2147 struct ifnet *ifp; 2148 struct dc_mediainfo *m; 2149 2150 sc = device_get_softc(dev); 2151 2152 DC_LOCK(sc); 2153 2154 ifp = &sc->arpcom.ac_if; 2155 2156 dc_stop(sc); 2157 ether_ifdetach(ifp, ETHER_BPF_SUPPORTED); 2158 2159 bus_generic_detach(dev); 2160 device_delete_child(dev, sc->dc_miibus); 2161 2162 bus_teardown_intr(dev, sc->dc_irq, sc->dc_intrhand); 2163 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->dc_irq); 2164 bus_release_resource(dev, DC_RES, DC_RID, sc->dc_res); 2165 2166 contigfree(sc->dc_ldata, sizeof(struct dc_list_data), M_DEVBUF); 2167 if (sc->dc_pnic_rx_buf != NULL) 2168 free(sc->dc_pnic_rx_buf, M_DEVBUF); 2169 2170 while(sc->dc_mi != NULL) { 2171 m = sc->dc_mi->dc_next; 2172 free(sc->dc_mi, M_DEVBUF); 2173 sc->dc_mi = m; 2174 } 2175 2176 DC_UNLOCK(sc); 2177 mtx_destroy(&sc->dc_mtx); 2178 2179 return(0); 2180 } 2181 2182 /* 2183 * Initialize the transmit descriptors. 2184 */ 2185 static int dc_list_tx_init(sc) 2186 struct dc_softc *sc; 2187 { 2188 struct dc_chain_data *cd; 2189 struct dc_list_data *ld; 2190 int i; 2191 2192 cd = &sc->dc_cdata; 2193 ld = sc->dc_ldata; 2194 for (i = 0; i < DC_TX_LIST_CNT; i++) { 2195 if (i == (DC_TX_LIST_CNT - 1)) { 2196 ld->dc_tx_list[i].dc_next = 2197 vtophys(&ld->dc_tx_list[0]); 2198 } else { 2199 ld->dc_tx_list[i].dc_next = 2200 vtophys(&ld->dc_tx_list[i + 1]); 2201 } 2202 cd->dc_tx_chain[i] = NULL; 2203 ld->dc_tx_list[i].dc_data = 0; 2204 ld->dc_tx_list[i].dc_ctl = 0; 2205 } 2206 2207 cd->dc_tx_prod = cd->dc_tx_cons = cd->dc_tx_cnt = 0; 2208 2209 return(0); 2210 } 2211 2212 2213 /* 2214 * Initialize the RX descriptors and allocate mbufs for them. Note that 2215 * we arrange the descriptors in a closed ring, so that the last descriptor 2216 * points back to the first. 2217 */ 2218 static int dc_list_rx_init(sc) 2219 struct dc_softc *sc; 2220 { 2221 struct dc_chain_data *cd; 2222 struct dc_list_data *ld; 2223 int i; 2224 2225 cd = &sc->dc_cdata; 2226 ld = sc->dc_ldata; 2227 2228 for (i = 0; i < DC_RX_LIST_CNT; i++) { 2229 if (dc_newbuf(sc, i, NULL) == ENOBUFS) 2230 return(ENOBUFS); 2231 if (i == (DC_RX_LIST_CNT - 1)) { 2232 ld->dc_rx_list[i].dc_next = 2233 vtophys(&ld->dc_rx_list[0]); 2234 } else { 2235 ld->dc_rx_list[i].dc_next = 2236 vtophys(&ld->dc_rx_list[i + 1]); 2237 } 2238 } 2239 2240 cd->dc_rx_prod = 0; 2241 2242 return(0); 2243 } 2244 2245 /* 2246 * Initialize an RX descriptor and attach an MBUF cluster. 2247 */ 2248 static int dc_newbuf(sc, i, m) 2249 struct dc_softc *sc; 2250 int i; 2251 struct mbuf *m; 2252 { 2253 struct mbuf *m_new = NULL; 2254 struct dc_desc *c; 2255 2256 c = &sc->dc_ldata->dc_rx_list[i]; 2257 2258 if (m == NULL) { 2259 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 2260 if (m_new == NULL) { 2261 printf("dc%d: no memory for rx list " 2262 "-- packet dropped!\n", sc->dc_unit); 2263 return(ENOBUFS); 2264 } 2265 2266 MCLGET(m_new, M_DONTWAIT); 2267 if (!(m_new->m_flags & M_EXT)) { 2268 printf("dc%d: no memory for rx list " 2269 "-- packet dropped!\n", sc->dc_unit); 2270 m_freem(m_new); 2271 return(ENOBUFS); 2272 } 2273 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 2274 } else { 2275 m_new = m; 2276 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 2277 m_new->m_data = m_new->m_ext.ext_buf; 2278 } 2279 2280 m_adj(m_new, sizeof(u_int64_t)); 2281 2282 /* 2283 * If this is a PNIC chip, zero the buffer. This is part 2284 * of the workaround for the receive bug in the 82c168 and 2285 * 82c169 chips. 2286 */ 2287 if (sc->dc_flags & DC_PNIC_RX_BUG_WAR) 2288 bzero((char *)mtod(m_new, char *), m_new->m_len); 2289 2290 sc->dc_cdata.dc_rx_chain[i] = m_new; 2291 c->dc_data = vtophys(mtod(m_new, caddr_t)); 2292 c->dc_ctl = DC_RXCTL_RLINK | DC_RXLEN; 2293 c->dc_status = DC_RXSTAT_OWN; 2294 2295 return(0); 2296 } 2297 2298 /* 2299 * Grrrrr. 2300 * The PNIC chip has a terrible bug in it that manifests itself during 2301 * periods of heavy activity. The exact mode of failure if difficult to 2302 * pinpoint: sometimes it only happens in promiscuous mode, sometimes it 2303 * will happen on slow machines. The bug is that sometimes instead of 2304 * uploading one complete frame during reception, it uploads what looks 2305 * like the entire contents of its FIFO memory. The frame we want is at 2306 * the end of the whole mess, but we never know exactly how much data has 2307 * been uploaded, so salvaging the frame is hard. 2308 * 2309 * There is only one way to do it reliably, and it's disgusting. 2310 * Here's what we know: 2311 * 2312 * - We know there will always be somewhere between one and three extra 2313 * descriptors uploaded. 2314 * 2315 * - We know the desired received frame will always be at the end of the 2316 * total data upload. 2317 * 2318 * - We know the size of the desired received frame because it will be 2319 * provided in the length field of the status word in the last descriptor. 2320 * 2321 * Here's what we do: 2322 * 2323 * - When we allocate buffers for the receive ring, we bzero() them. 2324 * This means that we know that the buffer contents should be all 2325 * zeros, except for data uploaded by the chip. 2326 * 2327 * - We also force the PNIC chip to upload frames that include the 2328 * ethernet CRC at the end. 2329 * 2330 * - We gather all of the bogus frame data into a single buffer. 2331 * 2332 * - We then position a pointer at the end of this buffer and scan 2333 * backwards until we encounter the first non-zero byte of data. 2334 * This is the end of the received frame. We know we will encounter 2335 * some data at the end of the frame because the CRC will always be 2336 * there, so even if the sender transmits a packet of all zeros, 2337 * we won't be fooled. 2338 * 2339 * - We know the size of the actual received frame, so we subtract 2340 * that value from the current pointer location. This brings us 2341 * to the start of the actual received packet. 2342 * 2343 * - We copy this into an mbuf and pass it on, along with the actual 2344 * frame length. 2345 * 2346 * The performance hit is tremendous, but it beats dropping frames all 2347 * the time. 2348 */ 2349 2350 #define DC_WHOLEFRAME (DC_RXSTAT_FIRSTFRAG|DC_RXSTAT_LASTFRAG) 2351 static void dc_pnic_rx_bug_war(sc, idx) 2352 struct dc_softc *sc; 2353 int idx; 2354 { 2355 struct dc_desc *cur_rx; 2356 struct dc_desc *c = NULL; 2357 struct mbuf *m = NULL; 2358 unsigned char *ptr; 2359 int i, total_len; 2360 u_int32_t rxstat = 0; 2361 2362 i = sc->dc_pnic_rx_bug_save; 2363 cur_rx = &sc->dc_ldata->dc_rx_list[idx]; 2364 ptr = sc->dc_pnic_rx_buf; 2365 bzero(ptr, sizeof(DC_RXLEN * 5)); 2366 2367 /* Copy all the bytes from the bogus buffers. */ 2368 while (1) { 2369 c = &sc->dc_ldata->dc_rx_list[i]; 2370 rxstat = c->dc_status; 2371 m = sc->dc_cdata.dc_rx_chain[i]; 2372 bcopy(mtod(m, char *), ptr, DC_RXLEN); 2373 ptr += DC_RXLEN; 2374 /* If this is the last buffer, break out. */ 2375 if (i == idx || rxstat & DC_RXSTAT_LASTFRAG) 2376 break; 2377 dc_newbuf(sc, i, m); 2378 DC_INC(i, DC_RX_LIST_CNT); 2379 } 2380 2381 /* Find the length of the actual receive frame. */ 2382 total_len = DC_RXBYTES(rxstat); 2383 2384 /* Scan backwards until we hit a non-zero byte. */ 2385 while(*ptr == 0x00) 2386 ptr--; 2387 2388 /* Round off. */ 2389 if ((uintptr_t)(ptr) & 0x3) 2390 ptr -= 1; 2391 2392 /* Now find the start of the frame. */ 2393 ptr -= total_len; 2394 if (ptr < sc->dc_pnic_rx_buf) 2395 ptr = sc->dc_pnic_rx_buf; 2396 2397 /* 2398 * Now copy the salvaged frame to the last mbuf and fake up 2399 * the status word to make it look like a successful 2400 * frame reception. 2401 */ 2402 dc_newbuf(sc, i, m); 2403 bcopy(ptr, mtod(m, char *), total_len); 2404 cur_rx->dc_status = rxstat | DC_RXSTAT_FIRSTFRAG; 2405 2406 return; 2407 } 2408 2409 /* 2410 * This routine searches the RX ring for dirty descriptors in the 2411 * event that the rxeof routine falls out of sync with the chip's 2412 * current descriptor pointer. This may happen sometimes as a result 2413 * of a "no RX buffer available" condition that happens when the chip 2414 * consumes all of the RX buffers before the driver has a chance to 2415 * process the RX ring. This routine may need to be called more than 2416 * once to bring the driver back in sync with the chip, however we 2417 * should still be getting RX DONE interrupts to drive the search 2418 * for new packets in the RX ring, so we should catch up eventually. 2419 */ 2420 static int dc_rx_resync(sc) 2421 struct dc_softc *sc; 2422 { 2423 int i, pos; 2424 struct dc_desc *cur_rx; 2425 2426 pos = sc->dc_cdata.dc_rx_prod; 2427 2428 for (i = 0; i < DC_RX_LIST_CNT; i++) { 2429 cur_rx = &sc->dc_ldata->dc_rx_list[pos]; 2430 if (!(cur_rx->dc_status & DC_RXSTAT_OWN)) 2431 break; 2432 DC_INC(pos, DC_RX_LIST_CNT); 2433 } 2434 2435 /* If the ring really is empty, then just return. */ 2436 if (i == DC_RX_LIST_CNT) 2437 return(0); 2438 2439 /* We've fallen behing the chip: catch it. */ 2440 sc->dc_cdata.dc_rx_prod = pos; 2441 2442 return(EAGAIN); 2443 } 2444 2445 /* 2446 * A frame has been uploaded: pass the resulting mbuf chain up to 2447 * the higher level protocols. 2448 */ 2449 static void dc_rxeof(sc) 2450 struct dc_softc *sc; 2451 { 2452 struct ether_header *eh; 2453 struct mbuf *m; 2454 struct ifnet *ifp; 2455 struct dc_desc *cur_rx; 2456 int i, total_len = 0; 2457 u_int32_t rxstat; 2458 2459 ifp = &sc->arpcom.ac_if; 2460 i = sc->dc_cdata.dc_rx_prod; 2461 2462 while(!(sc->dc_ldata->dc_rx_list[i].dc_status & DC_RXSTAT_OWN)) { 2463 struct mbuf *m0 = NULL; 2464 2465 cur_rx = &sc->dc_ldata->dc_rx_list[i]; 2466 rxstat = cur_rx->dc_status; 2467 m = sc->dc_cdata.dc_rx_chain[i]; 2468 total_len = DC_RXBYTES(rxstat); 2469 2470 if (sc->dc_flags & DC_PNIC_RX_BUG_WAR) { 2471 if ((rxstat & DC_WHOLEFRAME) != DC_WHOLEFRAME) { 2472 if (rxstat & DC_RXSTAT_FIRSTFRAG) 2473 sc->dc_pnic_rx_bug_save = i; 2474 if ((rxstat & DC_RXSTAT_LASTFRAG) == 0) { 2475 DC_INC(i, DC_RX_LIST_CNT); 2476 continue; 2477 } 2478 dc_pnic_rx_bug_war(sc, i); 2479 rxstat = cur_rx->dc_status; 2480 total_len = DC_RXBYTES(rxstat); 2481 } 2482 } 2483 2484 sc->dc_cdata.dc_rx_chain[i] = NULL; 2485 2486 /* 2487 * If an error occurs, update stats, clear the 2488 * status word and leave the mbuf cluster in place: 2489 * it should simply get re-used next time this descriptor 2490 * comes up in the ring. 2491 */ 2492 if (rxstat & DC_RXSTAT_RXERR) { 2493 ifp->if_ierrors++; 2494 if (rxstat & DC_RXSTAT_COLLSEEN) 2495 ifp->if_collisions++; 2496 dc_newbuf(sc, i, m); 2497 if (rxstat & DC_RXSTAT_CRCERR) { 2498 DC_INC(i, DC_RX_LIST_CNT); 2499 continue; 2500 } else { 2501 dc_init(sc); 2502 return; 2503 } 2504 } 2505 2506 /* No errors; receive the packet. */ 2507 total_len -= ETHER_CRC_LEN; 2508 2509 m0 = m_devget(mtod(m, char *) - ETHER_ALIGN, 2510 total_len + ETHER_ALIGN, 0, ifp, NULL); 2511 dc_newbuf(sc, i, m); 2512 DC_INC(i, DC_RX_LIST_CNT); 2513 if (m0 == NULL) { 2514 ifp->if_ierrors++; 2515 continue; 2516 } 2517 m_adj(m0, ETHER_ALIGN); 2518 m = m0; 2519 2520 ifp->if_ipackets++; 2521 eh = mtod(m, struct ether_header *); 2522 2523 /* Remove header from mbuf and pass it on. */ 2524 m_adj(m, sizeof(struct ether_header)); 2525 ether_input(ifp, eh, m); 2526 } 2527 2528 sc->dc_cdata.dc_rx_prod = i; 2529 } 2530 2531 /* 2532 * A frame was downloaded to the chip. It's safe for us to clean up 2533 * the list buffers. 2534 */ 2535 2536 static void dc_txeof(sc) 2537 struct dc_softc *sc; 2538 { 2539 struct dc_desc *cur_tx = NULL; 2540 struct ifnet *ifp; 2541 int idx; 2542 2543 ifp = &sc->arpcom.ac_if; 2544 2545 /* Clear the timeout timer. */ 2546 ifp->if_timer = 0; 2547 2548 /* 2549 * Go through our tx list and free mbufs for those 2550 * frames that have been transmitted. 2551 */ 2552 idx = sc->dc_cdata.dc_tx_cons; 2553 while(idx != sc->dc_cdata.dc_tx_prod) { 2554 u_int32_t txstat; 2555 2556 cur_tx = &sc->dc_ldata->dc_tx_list[idx]; 2557 txstat = cur_tx->dc_status; 2558 2559 if (txstat & DC_TXSTAT_OWN) 2560 break; 2561 2562 if (!(cur_tx->dc_ctl & DC_TXCTL_LASTFRAG) || 2563 cur_tx->dc_ctl & DC_TXCTL_SETUP) { 2564 sc->dc_cdata.dc_tx_cnt--; 2565 if (cur_tx->dc_ctl & DC_TXCTL_SETUP) { 2566 /* 2567 * Yes, the PNIC is so brain damaged 2568 * that it will sometimes generate a TX 2569 * underrun error while DMAing the RX 2570 * filter setup frame. If we detect this, 2571 * we have to send the setup frame again, 2572 * or else the filter won't be programmed 2573 * correctly. 2574 */ 2575 if (DC_IS_PNIC(sc)) { 2576 if (txstat & DC_TXSTAT_ERRSUM) 2577 dc_setfilt(sc); 2578 } 2579 sc->dc_cdata.dc_tx_chain[idx] = NULL; 2580 } 2581 DC_INC(idx, DC_TX_LIST_CNT); 2582 continue; 2583 } 2584 2585 if (DC_IS_XIRCOM(sc)) { 2586 /* 2587 * XXX: Why does my Xircom taunt me so? 2588 * For some reason it likes setting the CARRLOST flag 2589 * even when the carrier is there. wtf?!? */ 2590 if (/*sc->dc_type == DC_TYPE_21143 &&*/ 2591 sc->dc_pmode == DC_PMODE_MII && 2592 ((txstat & 0xFFFF) & ~(DC_TXSTAT_ERRSUM| 2593 DC_TXSTAT_NOCARRIER))) 2594 txstat &= ~DC_TXSTAT_ERRSUM; 2595 } else { 2596 if (/*sc->dc_type == DC_TYPE_21143 &&*/ 2597 sc->dc_pmode == DC_PMODE_MII && 2598 ((txstat & 0xFFFF) & ~(DC_TXSTAT_ERRSUM| 2599 DC_TXSTAT_NOCARRIER|DC_TXSTAT_CARRLOST))) 2600 txstat &= ~DC_TXSTAT_ERRSUM; 2601 } 2602 2603 if (txstat & DC_TXSTAT_ERRSUM) { 2604 ifp->if_oerrors++; 2605 if (txstat & DC_TXSTAT_EXCESSCOLL) 2606 ifp->if_collisions++; 2607 if (txstat & DC_TXSTAT_LATECOLL) 2608 ifp->if_collisions++; 2609 if (!(txstat & DC_TXSTAT_UNDERRUN)) { 2610 dc_init(sc); 2611 return; 2612 } 2613 } 2614 2615 ifp->if_collisions += (txstat & DC_TXSTAT_COLLCNT) >> 3; 2616 2617 ifp->if_opackets++; 2618 if (sc->dc_cdata.dc_tx_chain[idx] != NULL) { 2619 m_freem(sc->dc_cdata.dc_tx_chain[idx]); 2620 sc->dc_cdata.dc_tx_chain[idx] = NULL; 2621 } 2622 2623 sc->dc_cdata.dc_tx_cnt--; 2624 DC_INC(idx, DC_TX_LIST_CNT); 2625 } 2626 2627 sc->dc_cdata.dc_tx_cons = idx; 2628 if (cur_tx != NULL) 2629 ifp->if_flags &= ~IFF_OACTIVE; 2630 2631 return; 2632 } 2633 2634 static void dc_tick(xsc) 2635 void *xsc; 2636 { 2637 struct dc_softc *sc; 2638 struct mii_data *mii; 2639 struct ifnet *ifp; 2640 u_int32_t r; 2641 2642 sc = xsc; 2643 DC_LOCK(sc); 2644 ifp = &sc->arpcom.ac_if; 2645 mii = device_get_softc(sc->dc_miibus); 2646 2647 if (sc->dc_flags & DC_REDUCED_MII_POLL) { 2648 if (sc->dc_flags & DC_21143_NWAY) { 2649 r = CSR_READ_4(sc, DC_10BTSTAT); 2650 if (IFM_SUBTYPE(mii->mii_media_active) == 2651 IFM_100_TX && (r & DC_TSTAT_LS100)) { 2652 sc->dc_link = 0; 2653 mii_mediachg(mii); 2654 } 2655 if (IFM_SUBTYPE(mii->mii_media_active) == 2656 IFM_10_T && (r & DC_TSTAT_LS10)) { 2657 sc->dc_link = 0; 2658 mii_mediachg(mii); 2659 } 2660 if (sc->dc_link == 0) 2661 mii_tick(mii); 2662 } else { 2663 r = CSR_READ_4(sc, DC_ISR); 2664 if ((r & DC_ISR_RX_STATE) == DC_RXSTATE_WAIT && 2665 sc->dc_cdata.dc_tx_cnt == 0) 2666 mii_tick(mii); 2667 if (!(mii->mii_media_status & IFM_ACTIVE)) 2668 sc->dc_link = 0; 2669 } 2670 } else 2671 mii_tick(mii); 2672 2673 /* 2674 * When the init routine completes, we expect to be able to send 2675 * packets right away, and in fact the network code will send a 2676 * gratuitous ARP the moment the init routine marks the interface 2677 * as running. However, even though the MAC may have been initialized, 2678 * there may be a delay of a few seconds before the PHY completes 2679 * autonegotiation and the link is brought up. Any transmissions 2680 * made during that delay will be lost. Dealing with this is tricky: 2681 * we can't just pause in the init routine while waiting for the 2682 * PHY to come ready since that would bring the whole system to 2683 * a screeching halt for several seconds. 2684 * 2685 * What we do here is prevent the TX start routine from sending 2686 * any packets until a link has been established. After the 2687 * interface has been initialized, the tick routine will poll 2688 * the state of the PHY until the IFM_ACTIVE flag is set. Until 2689 * that time, packets will stay in the send queue, and once the 2690 * link comes up, they will be flushed out to the wire. 2691 */ 2692 if (!sc->dc_link) { 2693 mii_pollstat(mii); 2694 if (mii->mii_media_status & IFM_ACTIVE && 2695 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) { 2696 sc->dc_link++; 2697 if (ifp->if_snd.ifq_head != NULL) 2698 dc_start(ifp); 2699 } 2700 } 2701 2702 if (sc->dc_flags & DC_21143_NWAY && !sc->dc_link) 2703 callout_reset(&sc->dc_stat_ch, hz/10, dc_tick, sc); 2704 else 2705 callout_reset(&sc->dc_stat_ch, hz, dc_tick, sc); 2706 2707 DC_UNLOCK(sc); 2708 2709 return; 2710 } 2711 2712 static void dc_intr(arg) 2713 void *arg; 2714 { 2715 struct dc_softc *sc; 2716 struct ifnet *ifp; 2717 u_int32_t status; 2718 2719 sc = arg; 2720 DC_LOCK(sc); 2721 ifp = &sc->arpcom.ac_if; 2722 2723 /* Supress unwanted interrupts */ 2724 if (!(ifp->if_flags & IFF_UP)) { 2725 if (CSR_READ_4(sc, DC_ISR) & DC_INTRS) 2726 dc_stop(sc); 2727 DC_UNLOCK(sc); 2728 return; 2729 } 2730 2731 /* Disable interrupts. */ 2732 CSR_WRITE_4(sc, DC_IMR, 0x00000000); 2733 2734 while(((status = CSR_READ_4(sc, DC_ISR)) & DC_INTRS) 2735 && status != 0xFFFFFFFF) { 2736 2737 CSR_WRITE_4(sc, DC_ISR, status); 2738 2739 if (status & DC_ISR_RX_OK) { 2740 int curpkts; 2741 curpkts = ifp->if_ipackets; 2742 dc_rxeof(sc); 2743 if (curpkts == ifp->if_ipackets) { 2744 while(dc_rx_resync(sc)) 2745 dc_rxeof(sc); 2746 } 2747 } 2748 2749 if (status & (DC_ISR_TX_OK|DC_ISR_TX_NOBUF)) 2750 dc_txeof(sc); 2751 2752 if (status & DC_ISR_TX_IDLE) { 2753 dc_txeof(sc); 2754 if (sc->dc_cdata.dc_tx_cnt) { 2755 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_TX_ON); 2756 CSR_WRITE_4(sc, DC_TXSTART, 0xFFFFFFFF); 2757 } 2758 } 2759 2760 if (status & DC_ISR_TX_UNDERRUN) { 2761 u_int32_t cfg; 2762 2763 printf("dc%d: TX underrun -- ", sc->dc_unit); 2764 if (DC_IS_DAVICOM(sc) || DC_IS_INTEL(sc)) 2765 dc_init(sc); 2766 cfg = CSR_READ_4(sc, DC_NETCFG); 2767 cfg &= ~DC_NETCFG_TX_THRESH; 2768 if (sc->dc_txthresh == DC_TXTHRESH_160BYTES) { 2769 printf("using store and forward mode\n"); 2770 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_STORENFWD); 2771 } else if (sc->dc_flags & DC_TX_STORENFWD) { 2772 printf("resetting\n"); 2773 } else { 2774 sc->dc_txthresh += 0x4000; 2775 printf("increasing TX threshold\n"); 2776 CSR_WRITE_4(sc, DC_NETCFG, cfg); 2777 DC_SETBIT(sc, DC_NETCFG, sc->dc_txthresh); 2778 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_STORENFWD); 2779 } 2780 } 2781 2782 if ((status & DC_ISR_RX_WATDOGTIMEO) 2783 || (status & DC_ISR_RX_NOBUF)) { 2784 int curpkts; 2785 curpkts = ifp->if_ipackets; 2786 dc_rxeof(sc); 2787 if (curpkts == ifp->if_ipackets) { 2788 while(dc_rx_resync(sc)) 2789 dc_rxeof(sc); 2790 } 2791 } 2792 2793 if (status & DC_ISR_BUS_ERR) { 2794 dc_reset(sc); 2795 dc_init(sc); 2796 } 2797 } 2798 2799 /* Re-enable interrupts. */ 2800 CSR_WRITE_4(sc, DC_IMR, DC_INTRS); 2801 2802 if (ifp->if_snd.ifq_head != NULL) 2803 dc_start(ifp); 2804 2805 DC_UNLOCK(sc); 2806 2807 return; 2808 } 2809 2810 /* 2811 * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data 2812 * pointers to the fragment pointers. 2813 */ 2814 static int dc_encap(sc, m_head, txidx) 2815 struct dc_softc *sc; 2816 struct mbuf *m_head; 2817 u_int32_t *txidx; 2818 { 2819 struct dc_desc *f = NULL; 2820 struct mbuf *m; 2821 int frag, cur, cnt = 0; 2822 2823 /* 2824 * Start packing the mbufs in this chain into 2825 * the fragment pointers. Stop when we run out 2826 * of fragments or hit the end of the mbuf chain. 2827 */ 2828 m = m_head; 2829 cur = frag = *txidx; 2830 2831 for (m = m_head; m != NULL; m = m->m_next) { 2832 if (m->m_len != 0) { 2833 if (sc->dc_flags & DC_TX_ADMTEK_WAR) { 2834 if (*txidx != sc->dc_cdata.dc_tx_prod && 2835 frag == (DC_TX_LIST_CNT - 1)) 2836 return(ENOBUFS); 2837 } 2838 if ((DC_TX_LIST_CNT - 2839 (sc->dc_cdata.dc_tx_cnt + cnt)) < 5) 2840 return(ENOBUFS); 2841 2842 f = &sc->dc_ldata->dc_tx_list[frag]; 2843 f->dc_ctl = DC_TXCTL_TLINK | m->m_len; 2844 if (cnt == 0) { 2845 f->dc_status = 0; 2846 f->dc_ctl |= DC_TXCTL_FIRSTFRAG; 2847 } else 2848 f->dc_status = DC_TXSTAT_OWN; 2849 f->dc_data = vtophys(mtod(m, vm_offset_t)); 2850 cur = frag; 2851 DC_INC(frag, DC_TX_LIST_CNT); 2852 cnt++; 2853 } 2854 } 2855 2856 if (m != NULL) 2857 return(ENOBUFS); 2858 2859 sc->dc_cdata.dc_tx_cnt += cnt; 2860 sc->dc_cdata.dc_tx_chain[cur] = m_head; 2861 sc->dc_ldata->dc_tx_list[cur].dc_ctl |= DC_TXCTL_LASTFRAG; 2862 if (sc->dc_flags & DC_TX_INTR_FIRSTFRAG) 2863 sc->dc_ldata->dc_tx_list[*txidx].dc_ctl |= DC_TXCTL_FINT; 2864 if (sc->dc_flags & DC_TX_INTR_ALWAYS) 2865 sc->dc_ldata->dc_tx_list[cur].dc_ctl |= DC_TXCTL_FINT; 2866 if (sc->dc_flags & DC_TX_USE_TX_INTR && sc->dc_cdata.dc_tx_cnt > 64) 2867 sc->dc_ldata->dc_tx_list[cur].dc_ctl |= DC_TXCTL_FINT; 2868 sc->dc_ldata->dc_tx_list[*txidx].dc_status = DC_TXSTAT_OWN; 2869 *txidx = frag; 2870 2871 return(0); 2872 } 2873 2874 /* 2875 * Coalesce an mbuf chain into a single mbuf cluster buffer. 2876 * Needed for some really badly behaved chips that just can't 2877 * do scatter/gather correctly. 2878 */ 2879 static int dc_coal(sc, m_head) 2880 struct dc_softc *sc; 2881 struct mbuf **m_head; 2882 { 2883 struct mbuf *m_new, *m; 2884 2885 m = *m_head; 2886 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 2887 if (m_new == NULL) { 2888 printf("dc%d: no memory for tx list", sc->dc_unit); 2889 return(ENOBUFS); 2890 } 2891 if (m->m_pkthdr.len > MHLEN) { 2892 MCLGET(m_new, M_DONTWAIT); 2893 if (!(m_new->m_flags & M_EXT)) { 2894 m_freem(m_new); 2895 printf("dc%d: no memory for tx list", sc->dc_unit); 2896 return(ENOBUFS); 2897 } 2898 } 2899 m_copydata(m, 0, m->m_pkthdr.len, mtod(m_new, caddr_t)); 2900 m_new->m_pkthdr.len = m_new->m_len = m->m_pkthdr.len; 2901 m_freem(m); 2902 *m_head = m_new; 2903 2904 return(0); 2905 } 2906 2907 /* 2908 * Main transmit routine. To avoid having to do mbuf copies, we put pointers 2909 * to the mbuf data regions directly in the transmit lists. We also save a 2910 * copy of the pointers since the transmit list fragment pointers are 2911 * physical addresses. 2912 */ 2913 2914 static void dc_start(ifp) 2915 struct ifnet *ifp; 2916 { 2917 struct dc_softc *sc; 2918 struct mbuf *m_head = NULL; 2919 int idx; 2920 2921 sc = ifp->if_softc; 2922 2923 DC_LOCK(sc); 2924 2925 if (!sc->dc_link) { 2926 DC_UNLOCK(sc); 2927 return; 2928 } 2929 2930 if (ifp->if_flags & IFF_OACTIVE) { 2931 DC_UNLOCK(sc); 2932 return; 2933 } 2934 2935 idx = sc->dc_cdata.dc_tx_prod; 2936 2937 while(sc->dc_cdata.dc_tx_chain[idx] == NULL) { 2938 IF_DEQUEUE(&ifp->if_snd, m_head); 2939 if (m_head == NULL) 2940 break; 2941 2942 if (sc->dc_flags & DC_TX_COALESCE) { 2943 if (dc_coal(sc, &m_head)) { 2944 IF_PREPEND(&ifp->if_snd, m_head); 2945 ifp->if_flags |= IFF_OACTIVE; 2946 break; 2947 } 2948 } 2949 2950 if (dc_encap(sc, m_head, &idx)) { 2951 IF_PREPEND(&ifp->if_snd, m_head); 2952 ifp->if_flags |= IFF_OACTIVE; 2953 break; 2954 } 2955 2956 /* 2957 * If there's a BPF listener, bounce a copy of this frame 2958 * to him. 2959 */ 2960 if (ifp->if_bpf) 2961 bpf_mtap(ifp, m_head); 2962 2963 if (sc->dc_flags & DC_TX_ONE) { 2964 ifp->if_flags |= IFF_OACTIVE; 2965 break; 2966 } 2967 } 2968 2969 /* Transmit */ 2970 sc->dc_cdata.dc_tx_prod = idx; 2971 if (!(sc->dc_flags & DC_TX_POLL)) 2972 CSR_WRITE_4(sc, DC_TXSTART, 0xFFFFFFFF); 2973 2974 /* 2975 * Set a timeout in case the chip goes out to lunch. 2976 */ 2977 ifp->if_timer = 5; 2978 2979 DC_UNLOCK(sc); 2980 2981 return; 2982 } 2983 2984 static void dc_init(xsc) 2985 void *xsc; 2986 { 2987 struct dc_softc *sc = xsc; 2988 struct ifnet *ifp = &sc->arpcom.ac_if; 2989 struct mii_data *mii; 2990 2991 DC_LOCK(sc); 2992 2993 mii = device_get_softc(sc->dc_miibus); 2994 2995 /* 2996 * Cancel pending I/O and free all RX/TX buffers. 2997 */ 2998 dc_stop(sc); 2999 dc_reset(sc); 3000 3001 /* 3002 * Set cache alignment and burst length. 3003 */ 3004 if (DC_IS_ASIX(sc) || DC_IS_DAVICOM(sc)) 3005 CSR_WRITE_4(sc, DC_BUSCTL, 0); 3006 else 3007 CSR_WRITE_4(sc, DC_BUSCTL, DC_BUSCTL_MRME|DC_BUSCTL_MRLE); 3008 if (DC_IS_DAVICOM(sc) || DC_IS_INTEL(sc)) { 3009 DC_SETBIT(sc, DC_BUSCTL, DC_BURSTLEN_USECA); 3010 } else { 3011 DC_SETBIT(sc, DC_BUSCTL, DC_BURSTLEN_16LONG); 3012 } 3013 if (sc->dc_flags & DC_TX_POLL) 3014 DC_SETBIT(sc, DC_BUSCTL, DC_TXPOLL_1); 3015 switch(sc->dc_cachesize) { 3016 case 32: 3017 DC_SETBIT(sc, DC_BUSCTL, DC_CACHEALIGN_32LONG); 3018 break; 3019 case 16: 3020 DC_SETBIT(sc, DC_BUSCTL, DC_CACHEALIGN_16LONG); 3021 break; 3022 case 8: 3023 DC_SETBIT(sc, DC_BUSCTL, DC_CACHEALIGN_8LONG); 3024 break; 3025 case 0: 3026 default: 3027 DC_SETBIT(sc, DC_BUSCTL, DC_CACHEALIGN_NONE); 3028 break; 3029 } 3030 3031 if (sc->dc_flags & DC_TX_STORENFWD) 3032 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_STORENFWD); 3033 else { 3034 if (sc->dc_txthresh == DC_TXTHRESH_160BYTES) { 3035 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_STORENFWD); 3036 } else { 3037 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_STORENFWD); 3038 DC_SETBIT(sc, DC_NETCFG, sc->dc_txthresh); 3039 } 3040 } 3041 3042 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_NO_RXCRC); 3043 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_TX_BACKOFF); 3044 3045 if (DC_IS_MACRONIX(sc) || DC_IS_PNICII(sc)) { 3046 /* 3047 * The app notes for the 98713 and 98715A say that 3048 * in order to have the chips operate properly, a magic 3049 * number must be written to CSR16. Macronix does not 3050 * document the meaning of these bits so there's no way 3051 * to know exactly what they do. The 98713 has a magic 3052 * number all its own; the rest all use a different one. 3053 */ 3054 DC_CLRBIT(sc, DC_MX_MAGICPACKET, 0xFFFF0000); 3055 if (sc->dc_type == DC_TYPE_98713) 3056 DC_SETBIT(sc, DC_MX_MAGICPACKET, DC_MX_MAGIC_98713); 3057 else 3058 DC_SETBIT(sc, DC_MX_MAGICPACKET, DC_MX_MAGIC_98715); 3059 } 3060 3061 if (DC_IS_XIRCOM(sc)) { 3062 /* 3063 * setup General Purpose Port mode and data so the tulip 3064 * can talk to the MII. 3065 */ 3066 CSR_WRITE_4(sc, DC_SIAGP, DC_SIAGP_WRITE_EN | DC_SIAGP_INT1_EN | 3067 DC_SIAGP_MD_GP2_OUTPUT | DC_SIAGP_MD_GP0_OUTPUT); 3068 DELAY(10); 3069 CSR_WRITE_4(sc, DC_SIAGP, DC_SIAGP_INT1_EN | 3070 DC_SIAGP_MD_GP2_OUTPUT | DC_SIAGP_MD_GP0_OUTPUT); 3071 DELAY(10); 3072 } 3073 3074 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_TX_THRESH); 3075 DC_SETBIT(sc, DC_NETCFG, DC_TXTHRESH_72BYTES); 3076 3077 /* Init circular RX list. */ 3078 if (dc_list_rx_init(sc) == ENOBUFS) { 3079 printf("dc%d: initialization failed: no " 3080 "memory for rx buffers\n", sc->dc_unit); 3081 dc_stop(sc); 3082 DC_UNLOCK(sc); 3083 return; 3084 } 3085 3086 /* 3087 * Init tx descriptors. 3088 */ 3089 dc_list_tx_init(sc); 3090 3091 /* 3092 * Load the address of the RX list. 3093 */ 3094 CSR_WRITE_4(sc, DC_RXADDR, vtophys(&sc->dc_ldata->dc_rx_list[0])); 3095 CSR_WRITE_4(sc, DC_TXADDR, vtophys(&sc->dc_ldata->dc_tx_list[0])); 3096 3097 /* 3098 * Enable interrupts. 3099 */ 3100 CSR_WRITE_4(sc, DC_IMR, DC_INTRS); 3101 CSR_WRITE_4(sc, DC_ISR, 0xFFFFFFFF); 3102 3103 /* Enable transmitter. */ 3104 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_TX_ON); 3105 3106 /* 3107 * If this is an Intel 21143 and we're not using the 3108 * MII port, program the LED control pins so we get 3109 * link and activity indications. 3110 */ 3111 if (sc->dc_flags & DC_TULIP_LEDS) { 3112 CSR_WRITE_4(sc, DC_WATCHDOG, 3113 DC_WDOG_CTLWREN|DC_WDOG_LINK|DC_WDOG_ACTIVITY); 3114 CSR_WRITE_4(sc, DC_WATCHDOG, 0); 3115 } 3116 3117 /* 3118 * Load the RX/multicast filter. We do this sort of late 3119 * because the filter programming scheme on the 21143 and 3120 * some clones requires DMAing a setup frame via the TX 3121 * engine, and we need the transmitter enabled for that. 3122 */ 3123 dc_setfilt(sc); 3124 3125 /* Enable receiver. */ 3126 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_ON); 3127 CSR_WRITE_4(sc, DC_RXSTART, 0xFFFFFFFF); 3128 3129 mii_mediachg(mii); 3130 dc_setcfg(sc, sc->dc_if_media); 3131 3132 ifp->if_flags |= IFF_RUNNING; 3133 ifp->if_flags &= ~IFF_OACTIVE; 3134 3135 /* Don't start the ticker if this is a homePNA link. */ 3136 if (IFM_SUBTYPE(mii->mii_media.ifm_media) == IFM_homePNA) 3137 sc->dc_link = 1; 3138 else { 3139 if (sc->dc_flags & DC_21143_NWAY) 3140 callout_reset(&sc->dc_stat_ch, hz/10, dc_tick, sc); 3141 else 3142 callout_reset(&sc->dc_stat_ch, hz, dc_tick, sc); 3143 } 3144 3145 #ifdef SRM_MEDIA 3146 if(sc->dc_srm_media) { 3147 struct ifreq ifr; 3148 3149 ifr.ifr_media = sc->dc_srm_media; 3150 ifmedia_ioctl(ifp, &ifr, &mii->mii_media, SIOCSIFMEDIA); 3151 sc->dc_srm_media = 0; 3152 } 3153 #endif 3154 DC_UNLOCK(sc); 3155 return; 3156 } 3157 3158 /* 3159 * Set media options. 3160 */ 3161 static int dc_ifmedia_upd(ifp) 3162 struct ifnet *ifp; 3163 { 3164 struct dc_softc *sc; 3165 struct mii_data *mii; 3166 struct ifmedia *ifm; 3167 3168 sc = ifp->if_softc; 3169 mii = device_get_softc(sc->dc_miibus); 3170 mii_mediachg(mii); 3171 ifm = &mii->mii_media; 3172 3173 if (DC_IS_DAVICOM(sc) && 3174 IFM_SUBTYPE(ifm->ifm_media) == IFM_homePNA) 3175 dc_setcfg(sc, ifm->ifm_media); 3176 else 3177 sc->dc_link = 0; 3178 3179 return(0); 3180 } 3181 3182 /* 3183 * Report current media status. 3184 */ 3185 static void dc_ifmedia_sts(ifp, ifmr) 3186 struct ifnet *ifp; 3187 struct ifmediareq *ifmr; 3188 { 3189 struct dc_softc *sc; 3190 struct mii_data *mii; 3191 struct ifmedia *ifm; 3192 3193 sc = ifp->if_softc; 3194 mii = device_get_softc(sc->dc_miibus); 3195 mii_pollstat(mii); 3196 ifm = &mii->mii_media; 3197 if (DC_IS_DAVICOM(sc)) { 3198 if (IFM_SUBTYPE(ifm->ifm_media) == IFM_homePNA) { 3199 ifmr->ifm_active = ifm->ifm_media; 3200 ifmr->ifm_status = 0; 3201 return; 3202 } 3203 } 3204 ifmr->ifm_active = mii->mii_media_active; 3205 ifmr->ifm_status = mii->mii_media_status; 3206 3207 return; 3208 } 3209 3210 static int dc_ioctl(ifp, command, data) 3211 struct ifnet *ifp; 3212 u_long command; 3213 caddr_t data; 3214 { 3215 struct dc_softc *sc = ifp->if_softc; 3216 struct ifreq *ifr = (struct ifreq *) data; 3217 struct mii_data *mii; 3218 int error = 0; 3219 3220 DC_LOCK(sc); 3221 3222 switch(command) { 3223 case SIOCSIFADDR: 3224 case SIOCGIFADDR: 3225 case SIOCSIFMTU: 3226 error = ether_ioctl(ifp, command, data); 3227 break; 3228 case SIOCSIFFLAGS: 3229 if (ifp->if_flags & IFF_UP) { 3230 if (ifp->if_flags & IFF_RUNNING && 3231 ifp->if_flags & IFF_PROMISC && 3232 !(sc->dc_if_flags & IFF_PROMISC)) { 3233 dc_setfilt(sc); 3234 } else if (ifp->if_flags & IFF_RUNNING && 3235 !(ifp->if_flags & IFF_PROMISC) && 3236 sc->dc_if_flags & IFF_PROMISC) { 3237 dc_setfilt(sc); 3238 } else if (!(ifp->if_flags & IFF_RUNNING)) { 3239 sc->dc_txthresh = 0; 3240 dc_init(sc); 3241 } 3242 } else { 3243 if (ifp->if_flags & IFF_RUNNING) 3244 dc_stop(sc); 3245 } 3246 sc->dc_if_flags = ifp->if_flags; 3247 error = 0; 3248 break; 3249 case SIOCADDMULTI: 3250 case SIOCDELMULTI: 3251 dc_setfilt(sc); 3252 error = 0; 3253 break; 3254 case SIOCGIFMEDIA: 3255 case SIOCSIFMEDIA: 3256 mii = device_get_softc(sc->dc_miibus); 3257 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 3258 #ifdef SRM_MEDIA 3259 if (sc->dc_srm_media) 3260 sc->dc_srm_media = 0; 3261 #endif 3262 break; 3263 default: 3264 error = EINVAL; 3265 break; 3266 } 3267 3268 DC_UNLOCK(sc); 3269 3270 return(error); 3271 } 3272 3273 static void dc_watchdog(ifp) 3274 struct ifnet *ifp; 3275 { 3276 struct dc_softc *sc; 3277 3278 sc = ifp->if_softc; 3279 3280 DC_LOCK(sc); 3281 3282 ifp->if_oerrors++; 3283 printf("dc%d: watchdog timeout\n", sc->dc_unit); 3284 3285 dc_stop(sc); 3286 dc_reset(sc); 3287 dc_init(sc); 3288 3289 if (ifp->if_snd.ifq_head != NULL) 3290 dc_start(ifp); 3291 3292 DC_UNLOCK(sc); 3293 3294 return; 3295 } 3296 3297 /* 3298 * Stop the adapter and free any mbufs allocated to the 3299 * RX and TX lists. 3300 */ 3301 static void dc_stop(sc) 3302 struct dc_softc *sc; 3303 { 3304 register int i; 3305 struct ifnet *ifp; 3306 3307 DC_LOCK(sc); 3308 3309 ifp = &sc->arpcom.ac_if; 3310 ifp->if_timer = 0; 3311 3312 callout_stop(&sc->dc_stat_ch); 3313 3314 DC_CLRBIT(sc, DC_NETCFG, (DC_NETCFG_RX_ON|DC_NETCFG_TX_ON)); 3315 CSR_WRITE_4(sc, DC_IMR, 0x00000000); 3316 CSR_WRITE_4(sc, DC_TXADDR, 0x00000000); 3317 CSR_WRITE_4(sc, DC_RXADDR, 0x00000000); 3318 sc->dc_link = 0; 3319 3320 /* 3321 * Free data in the RX lists. 3322 */ 3323 for (i = 0; i < DC_RX_LIST_CNT; i++) { 3324 if (sc->dc_cdata.dc_rx_chain[i] != NULL) { 3325 m_freem(sc->dc_cdata.dc_rx_chain[i]); 3326 sc->dc_cdata.dc_rx_chain[i] = NULL; 3327 } 3328 } 3329 bzero((char *)&sc->dc_ldata->dc_rx_list, 3330 sizeof(sc->dc_ldata->dc_rx_list)); 3331 3332 /* 3333 * Free the TX list buffers. 3334 */ 3335 for (i = 0; i < DC_TX_LIST_CNT; i++) { 3336 if (sc->dc_cdata.dc_tx_chain[i] != NULL) { 3337 if (sc->dc_ldata->dc_tx_list[i].dc_ctl & 3338 DC_TXCTL_SETUP) { 3339 sc->dc_cdata.dc_tx_chain[i] = NULL; 3340 continue; 3341 } 3342 m_freem(sc->dc_cdata.dc_tx_chain[i]); 3343 sc->dc_cdata.dc_tx_chain[i] = NULL; 3344 } 3345 } 3346 3347 bzero((char *)&sc->dc_ldata->dc_tx_list, 3348 sizeof(sc->dc_ldata->dc_tx_list)); 3349 3350 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 3351 3352 DC_UNLOCK(sc); 3353 3354 return; 3355 } 3356 3357 /* 3358 * Stop all chip I/O so that the kernel's probe routines don't 3359 * get confused by errant DMAs when rebooting. 3360 */ 3361 static void dc_shutdown(dev) 3362 device_t dev; 3363 { 3364 struct dc_softc *sc; 3365 3366 sc = device_get_softc(dev); 3367 3368 dc_stop(sc); 3369 3370 return; 3371 } 3372