1 /*- 2 * Copyright (c) 1997, 1998, 1999 3 * Bill Paul <wpaul@ee.columbia.edu>. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 3. All advertising materials mentioning features or use of this software 14 * must display the following acknowledgement: 15 * This product includes software developed by Bill Paul. 16 * 4. Neither the name of the author nor the names of any co-contributors 17 * may be used to endorse or promote products derived from this software 18 * without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30 * THE POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33 #include <sys/cdefs.h> 34 __FBSDID("$FreeBSD$"); 35 36 /* 37 * DEC "tulip" clone ethernet driver. Supports the DEC/Intel 21143 38 * series chips and several workalikes including the following: 39 * 40 * Macronix 98713/98715/98725/98727/98732 PMAC (www.macronix.com) 41 * Macronix/Lite-On 82c115 PNIC II (www.macronix.com) 42 * Lite-On 82c168/82c169 PNIC (www.litecom.com) 43 * ASIX Electronics AX88140A (www.asix.com.tw) 44 * ASIX Electronics AX88141 (www.asix.com.tw) 45 * ADMtek AL981 (www.admtek.com.tw) 46 * ADMtek AN985 (www.admtek.com.tw) 47 * Netgear FA511 (www.netgear.com) Appears to be rebadged ADMTek AN985 48 * Davicom DM9100, DM9102, DM9102A (www.davicom8.com) 49 * Accton EN1217 (www.accton.com) 50 * Xircom X3201 (www.xircom.com) 51 * Abocom FE2500 52 * Conexant LANfinity (www.conexant.com) 53 * 3Com OfficeConnect 10/100B 3CSOHO100B (www.3com.com) 54 * 55 * Datasheets for the 21143 are available at developer.intel.com. 56 * Datasheets for the clone parts can be found at their respective sites. 57 * (Except for the PNIC; see www.freebsd.org/~wpaul/PNIC/pnic.ps.gz.) 58 * The PNIC II is essentially a Macronix 98715A chip; the only difference 59 * worth noting is that its multicast hash table is only 128 bits wide 60 * instead of 512. 61 * 62 * Written by Bill Paul <wpaul@ee.columbia.edu> 63 * Electrical Engineering Department 64 * Columbia University, New York City 65 */ 66 /* 67 * The Intel 21143 is the successor to the DEC 21140. It is basically 68 * the same as the 21140 but with a few new features. The 21143 supports 69 * three kinds of media attachments: 70 * 71 * o MII port, for 10Mbps and 100Mbps support and NWAY 72 * autonegotiation provided by an external PHY. 73 * o SYM port, for symbol mode 100Mbps support. 74 * o 10baseT port. 75 * o AUI/BNC port. 76 * 77 * The 100Mbps SYM port and 10baseT port can be used together in 78 * combination with the internal NWAY support to create a 10/100 79 * autosensing configuration. 80 * 81 * Note that not all tulip workalikes are handled in this driver: we only 82 * deal with those which are relatively well behaved. The Winbond is 83 * handled separately due to its different register offsets and the 84 * special handling needed for its various bugs. The PNIC is handled 85 * here, but I'm not thrilled about it. 86 * 87 * All of the workalike chips use some form of MII transceiver support 88 * with the exception of the Macronix chips, which also have a SYM port. 89 * The ASIX AX88140A is also documented to have a SYM port, but all 90 * the cards I've seen use an MII transceiver, probably because the 91 * AX88140A doesn't support internal NWAY. 92 */ 93 94 #ifdef HAVE_KERNEL_OPTION_HEADERS 95 #include "opt_device_polling.h" 96 #endif 97 98 #include <sys/param.h> 99 #include <sys/endian.h> 100 #include <sys/systm.h> 101 #include <sys/sockio.h> 102 #include <sys/mbuf.h> 103 #include <sys/malloc.h> 104 #include <sys/kernel.h> 105 #include <sys/module.h> 106 #include <sys/socket.h> 107 108 #include <net/if.h> 109 #include <net/if_arp.h> 110 #include <net/ethernet.h> 111 #include <net/if_dl.h> 112 #include <net/if_media.h> 113 #include <net/if_types.h> 114 #include <net/if_vlan_var.h> 115 116 #include <net/bpf.h> 117 118 #include <machine/bus.h> 119 #include <machine/resource.h> 120 #include <sys/bus.h> 121 #include <sys/rman.h> 122 123 #include <dev/mii/mii.h> 124 #include <dev/mii/miivar.h> 125 126 #include <dev/pci/pcireg.h> 127 #include <dev/pci/pcivar.h> 128 129 #define DC_USEIOSPACE 130 131 #include <dev/dc/if_dcreg.h> 132 133 #ifdef __sparc64__ 134 #include <dev/ofw/openfirm.h> 135 #include <machine/ofw_machdep.h> 136 #endif 137 138 MODULE_DEPEND(dc, pci, 1, 1, 1); 139 MODULE_DEPEND(dc, ether, 1, 1, 1); 140 MODULE_DEPEND(dc, miibus, 1, 1, 1); 141 142 /* 143 * "device miibus" is required in kernel config. See GENERIC if you get 144 * errors here. 145 */ 146 #include "miibus_if.h" 147 148 /* 149 * Various supported device vendors/types and their names. 150 */ 151 static const struct dc_type dc_devs[] = { 152 { DC_DEVID(DC_VENDORID_DEC, DC_DEVICEID_21143), 0, 153 "Intel 21143 10/100BaseTX" }, 154 { DC_DEVID(DC_VENDORID_DAVICOM, DC_DEVICEID_DM9009), 0, 155 "Davicom DM9009 10/100BaseTX" }, 156 { DC_DEVID(DC_VENDORID_DAVICOM, DC_DEVICEID_DM9100), 0, 157 "Davicom DM9100 10/100BaseTX" }, 158 { DC_DEVID(DC_VENDORID_DAVICOM, DC_DEVICEID_DM9102), DC_REVISION_DM9102A, 159 "Davicom DM9102A 10/100BaseTX" }, 160 { DC_DEVID(DC_VENDORID_DAVICOM, DC_DEVICEID_DM9102), 0, 161 "Davicom DM9102 10/100BaseTX" }, 162 { DC_DEVID(DC_VENDORID_ADMTEK, DC_DEVICEID_AL981), 0, 163 "ADMtek AL981 10/100BaseTX" }, 164 { DC_DEVID(DC_VENDORID_ADMTEK, DC_DEVICEID_AN985), 0, 165 "ADMtek AN985 10/100BaseTX" }, 166 { DC_DEVID(DC_VENDORID_ADMTEK, DC_DEVICEID_ADM9511), 0, 167 "ADMtek ADM9511 10/100BaseTX" }, 168 { DC_DEVID(DC_VENDORID_ADMTEK, DC_DEVICEID_ADM9513), 0, 169 "ADMtek ADM9513 10/100BaseTX" }, 170 { DC_DEVID(DC_VENDORID_ADMTEK, DC_DEVICEID_FA511), 0, 171 "Netgear FA511 10/100BaseTX" }, 172 { DC_DEVID(DC_VENDORID_ASIX, DC_DEVICEID_AX88140A), DC_REVISION_88141, 173 "ASIX AX88141 10/100BaseTX" }, 174 { DC_DEVID(DC_VENDORID_ASIX, DC_DEVICEID_AX88140A), 0, 175 "ASIX AX88140A 10/100BaseTX" }, 176 { DC_DEVID(DC_VENDORID_MX, DC_DEVICEID_98713), DC_REVISION_98713A, 177 "Macronix 98713A 10/100BaseTX" }, 178 { DC_DEVID(DC_VENDORID_MX, DC_DEVICEID_98713), 0, 179 "Macronix 98713 10/100BaseTX" }, 180 { DC_DEVID(DC_VENDORID_CP, DC_DEVICEID_98713_CP), DC_REVISION_98713A, 181 "Compex RL100-TX 10/100BaseTX" }, 182 { DC_DEVID(DC_VENDORID_CP, DC_DEVICEID_98713_CP), 0, 183 "Compex RL100-TX 10/100BaseTX" }, 184 { DC_DEVID(DC_VENDORID_MX, DC_DEVICEID_987x5), DC_REVISION_98725, 185 "Macronix 98725 10/100BaseTX" }, 186 { DC_DEVID(DC_VENDORID_MX, DC_DEVICEID_987x5), DC_REVISION_98715AEC_C, 187 "Macronix 98715AEC-C 10/100BaseTX" }, 188 { DC_DEVID(DC_VENDORID_MX, DC_DEVICEID_987x5), 0, 189 "Macronix 98715/98715A 10/100BaseTX" }, 190 { DC_DEVID(DC_VENDORID_MX, DC_DEVICEID_98727), 0, 191 "Macronix 98727/98732 10/100BaseTX" }, 192 { DC_DEVID(DC_VENDORID_LO, DC_DEVICEID_82C115), 0, 193 "LC82C115 PNIC II 10/100BaseTX" }, 194 { DC_DEVID(DC_VENDORID_LO, DC_DEVICEID_82C168), DC_REVISION_82C169, 195 "82c169 PNIC 10/100BaseTX" }, 196 { DC_DEVID(DC_VENDORID_LO, DC_DEVICEID_82C168), 0, 197 "82c168 PNIC 10/100BaseTX" }, 198 { DC_DEVID(DC_VENDORID_ACCTON, DC_DEVICEID_EN1217), 0, 199 "Accton EN1217 10/100BaseTX" }, 200 { DC_DEVID(DC_VENDORID_ACCTON, DC_DEVICEID_EN2242), 0, 201 "Accton EN2242 MiniPCI 10/100BaseTX" }, 202 { DC_DEVID(DC_VENDORID_XIRCOM, DC_DEVICEID_X3201), 0, 203 "Xircom X3201 10/100BaseTX" }, 204 { DC_DEVID(DC_VENDORID_DLINK, DC_DEVICEID_DRP32TXD), 0, 205 "Neteasy DRP-32TXD Cardbus 10/100" }, 206 { DC_DEVID(DC_VENDORID_ABOCOM, DC_DEVICEID_FE2500), 0, 207 "Abocom FE2500 10/100BaseTX" }, 208 { DC_DEVID(DC_VENDORID_ABOCOM, DC_DEVICEID_FE2500MX), 0, 209 "Abocom FE2500MX 10/100BaseTX" }, 210 { DC_DEVID(DC_VENDORID_CONEXANT, DC_DEVICEID_RS7112), 0, 211 "Conexant LANfinity MiniPCI 10/100BaseTX" }, 212 { DC_DEVID(DC_VENDORID_HAWKING, DC_DEVICEID_HAWKING_PN672TX), 0, 213 "Hawking CB102 CardBus 10/100" }, 214 { DC_DEVID(DC_VENDORID_PLANEX, DC_DEVICEID_FNW3602T), 0, 215 "PlaneX FNW-3602-T CardBus 10/100" }, 216 { DC_DEVID(DC_VENDORID_3COM, DC_DEVICEID_3CSOHOB), 0, 217 "3Com OfficeConnect 10/100B" }, 218 { DC_DEVID(DC_VENDORID_MICROSOFT, DC_DEVICEID_MSMN120), 0, 219 "Microsoft MN-120 CardBus 10/100" }, 220 { DC_DEVID(DC_VENDORID_MICROSOFT, DC_DEVICEID_MSMN130), 0, 221 "Microsoft MN-130 10/100" }, 222 { DC_DEVID(DC_VENDORID_LINKSYS, DC_DEVICEID_PCMPC200_AB08), 0, 223 "Linksys PCMPC200 CardBus 10/100" }, 224 { DC_DEVID(DC_VENDORID_LINKSYS, DC_DEVICEID_PCMPC200_AB09), 0, 225 "Linksys PCMPC200 CardBus 10/100" }, 226 { 0, 0, NULL } 227 }; 228 229 static int dc_probe(device_t); 230 static int dc_attach(device_t); 231 static int dc_detach(device_t); 232 static int dc_suspend(device_t); 233 static int dc_resume(device_t); 234 static const struct dc_type *dc_devtype(device_t); 235 static int dc_newbuf(struct dc_softc *, int, int); 236 static int dc_encap(struct dc_softc *, struct mbuf **); 237 static void dc_pnic_rx_bug_war(struct dc_softc *, int); 238 static int dc_rx_resync(struct dc_softc *); 239 static void dc_rxeof(struct dc_softc *); 240 static void dc_txeof(struct dc_softc *); 241 static void dc_tick(void *); 242 static void dc_tx_underrun(struct dc_softc *); 243 static void dc_intr(void *); 244 static void dc_start(struct ifnet *); 245 static void dc_start_locked(struct ifnet *); 246 static int dc_ioctl(struct ifnet *, u_long, caddr_t); 247 static void dc_init(void *); 248 static void dc_init_locked(struct dc_softc *); 249 static void dc_stop(struct dc_softc *); 250 static void dc_watchdog(void *); 251 static int dc_shutdown(device_t); 252 static int dc_ifmedia_upd(struct ifnet *); 253 static void dc_ifmedia_sts(struct ifnet *, struct ifmediareq *); 254 255 static void dc_delay(struct dc_softc *); 256 static void dc_eeprom_idle(struct dc_softc *); 257 static void dc_eeprom_putbyte(struct dc_softc *, int); 258 static void dc_eeprom_getword(struct dc_softc *, int, u_int16_t *); 259 static void dc_eeprom_getword_pnic(struct dc_softc *, int, u_int16_t *); 260 static void dc_eeprom_getword_xircom(struct dc_softc *, int, u_int16_t *); 261 static void dc_eeprom_width(struct dc_softc *); 262 static void dc_read_eeprom(struct dc_softc *, caddr_t, int, int, int); 263 264 static void dc_mii_writebit(struct dc_softc *, int); 265 static int dc_mii_readbit(struct dc_softc *); 266 static void dc_mii_sync(struct dc_softc *); 267 static void dc_mii_send(struct dc_softc *, u_int32_t, int); 268 static int dc_mii_readreg(struct dc_softc *, struct dc_mii_frame *); 269 static int dc_mii_writereg(struct dc_softc *, struct dc_mii_frame *); 270 static int dc_miibus_readreg(device_t, int, int); 271 static int dc_miibus_writereg(device_t, int, int, int); 272 static void dc_miibus_statchg(device_t); 273 static void dc_miibus_mediainit(device_t); 274 275 static void dc_setcfg(struct dc_softc *, int); 276 static uint32_t dc_mchash_le(struct dc_softc *, const uint8_t *); 277 static uint32_t dc_mchash_be(const uint8_t *); 278 static void dc_setfilt_21143(struct dc_softc *); 279 static void dc_setfilt_asix(struct dc_softc *); 280 static void dc_setfilt_admtek(struct dc_softc *); 281 static void dc_setfilt_xircom(struct dc_softc *); 282 283 static void dc_setfilt(struct dc_softc *); 284 285 static void dc_reset(struct dc_softc *); 286 static int dc_list_rx_init(struct dc_softc *); 287 static int dc_list_tx_init(struct dc_softc *); 288 289 static void dc_read_srom(struct dc_softc *, int); 290 static void dc_parse_21143_srom(struct dc_softc *); 291 static void dc_decode_leaf_sia(struct dc_softc *, struct dc_eblock_sia *); 292 static void dc_decode_leaf_mii(struct dc_softc *, struct dc_eblock_mii *); 293 static void dc_decode_leaf_sym(struct dc_softc *, struct dc_eblock_sym *); 294 static void dc_apply_fixup(struct dc_softc *, int); 295 296 #ifdef DC_USEIOSPACE 297 #define DC_RES SYS_RES_IOPORT 298 #define DC_RID DC_PCI_CFBIO 299 #else 300 #define DC_RES SYS_RES_MEMORY 301 #define DC_RID DC_PCI_CFBMA 302 #endif 303 304 static device_method_t dc_methods[] = { 305 /* Device interface */ 306 DEVMETHOD(device_probe, dc_probe), 307 DEVMETHOD(device_attach, dc_attach), 308 DEVMETHOD(device_detach, dc_detach), 309 DEVMETHOD(device_suspend, dc_suspend), 310 DEVMETHOD(device_resume, dc_resume), 311 DEVMETHOD(device_shutdown, dc_shutdown), 312 313 /* bus interface */ 314 DEVMETHOD(bus_print_child, bus_generic_print_child), 315 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 316 317 /* MII interface */ 318 DEVMETHOD(miibus_readreg, dc_miibus_readreg), 319 DEVMETHOD(miibus_writereg, dc_miibus_writereg), 320 DEVMETHOD(miibus_statchg, dc_miibus_statchg), 321 DEVMETHOD(miibus_mediainit, dc_miibus_mediainit), 322 323 { 0, 0 } 324 }; 325 326 static driver_t dc_driver = { 327 "dc", 328 dc_methods, 329 sizeof(struct dc_softc) 330 }; 331 332 static devclass_t dc_devclass; 333 334 DRIVER_MODULE(dc, cardbus, dc_driver, dc_devclass, 0, 0); 335 DRIVER_MODULE(dc, pci, dc_driver, dc_devclass, 0, 0); 336 DRIVER_MODULE(miibus, dc, miibus_driver, miibus_devclass, 0, 0); 337 338 #define DC_SETBIT(sc, reg, x) \ 339 CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) | (x)) 340 341 #define DC_CLRBIT(sc, reg, x) \ 342 CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) & ~(x)) 343 344 #define SIO_SET(x) DC_SETBIT(sc, DC_SIO, (x)) 345 #define SIO_CLR(x) DC_CLRBIT(sc, DC_SIO, (x)) 346 347 static void 348 dc_delay(struct dc_softc *sc) 349 { 350 int idx; 351 352 for (idx = (300 / 33) + 1; idx > 0; idx--) 353 CSR_READ_4(sc, DC_BUSCTL); 354 } 355 356 static void 357 dc_eeprom_width(struct dc_softc *sc) 358 { 359 int i; 360 361 /* Force EEPROM to idle state. */ 362 dc_eeprom_idle(sc); 363 364 /* Enter EEPROM access mode. */ 365 CSR_WRITE_4(sc, DC_SIO, DC_SIO_EESEL); 366 dc_delay(sc); 367 DC_SETBIT(sc, DC_SIO, DC_SIO_ROMCTL_READ); 368 dc_delay(sc); 369 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); 370 dc_delay(sc); 371 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CS); 372 dc_delay(sc); 373 374 for (i = 3; i--;) { 375 if (6 & (1 << i)) 376 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_DATAIN); 377 else 378 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_DATAIN); 379 dc_delay(sc); 380 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CLK); 381 dc_delay(sc); 382 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); 383 dc_delay(sc); 384 } 385 386 for (i = 1; i <= 12; i++) { 387 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CLK); 388 dc_delay(sc); 389 if (!(CSR_READ_4(sc, DC_SIO) & DC_SIO_EE_DATAOUT)) { 390 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); 391 dc_delay(sc); 392 break; 393 } 394 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); 395 dc_delay(sc); 396 } 397 398 /* Turn off EEPROM access mode. */ 399 dc_eeprom_idle(sc); 400 401 if (i < 4 || i > 12) 402 sc->dc_romwidth = 6; 403 else 404 sc->dc_romwidth = i; 405 406 /* Enter EEPROM access mode. */ 407 CSR_WRITE_4(sc, DC_SIO, DC_SIO_EESEL); 408 dc_delay(sc); 409 DC_SETBIT(sc, DC_SIO, DC_SIO_ROMCTL_READ); 410 dc_delay(sc); 411 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); 412 dc_delay(sc); 413 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CS); 414 dc_delay(sc); 415 416 /* Turn off EEPROM access mode. */ 417 dc_eeprom_idle(sc); 418 } 419 420 static void 421 dc_eeprom_idle(struct dc_softc *sc) 422 { 423 int i; 424 425 CSR_WRITE_4(sc, DC_SIO, DC_SIO_EESEL); 426 dc_delay(sc); 427 DC_SETBIT(sc, DC_SIO, DC_SIO_ROMCTL_READ); 428 dc_delay(sc); 429 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); 430 dc_delay(sc); 431 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CS); 432 dc_delay(sc); 433 434 for (i = 0; i < 25; i++) { 435 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); 436 dc_delay(sc); 437 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CLK); 438 dc_delay(sc); 439 } 440 441 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); 442 dc_delay(sc); 443 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CS); 444 dc_delay(sc); 445 CSR_WRITE_4(sc, DC_SIO, 0x00000000); 446 } 447 448 /* 449 * Send a read command and address to the EEPROM, check for ACK. 450 */ 451 static void 452 dc_eeprom_putbyte(struct dc_softc *sc, int addr) 453 { 454 int d, i; 455 456 d = DC_EECMD_READ >> 6; 457 for (i = 3; i--; ) { 458 if (d & (1 << i)) 459 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_DATAIN); 460 else 461 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_DATAIN); 462 dc_delay(sc); 463 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CLK); 464 dc_delay(sc); 465 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); 466 dc_delay(sc); 467 } 468 469 /* 470 * Feed in each bit and strobe the clock. 471 */ 472 for (i = sc->dc_romwidth; i--;) { 473 if (addr & (1 << i)) { 474 SIO_SET(DC_SIO_EE_DATAIN); 475 } else { 476 SIO_CLR(DC_SIO_EE_DATAIN); 477 } 478 dc_delay(sc); 479 SIO_SET(DC_SIO_EE_CLK); 480 dc_delay(sc); 481 SIO_CLR(DC_SIO_EE_CLK); 482 dc_delay(sc); 483 } 484 } 485 486 /* 487 * Read a word of data stored in the EEPROM at address 'addr.' 488 * The PNIC 82c168/82c169 has its own non-standard way to read 489 * the EEPROM. 490 */ 491 static void 492 dc_eeprom_getword_pnic(struct dc_softc *sc, int addr, u_int16_t *dest) 493 { 494 int i; 495 u_int32_t r; 496 497 CSR_WRITE_4(sc, DC_PN_SIOCTL, DC_PN_EEOPCODE_READ | addr); 498 499 for (i = 0; i < DC_TIMEOUT; i++) { 500 DELAY(1); 501 r = CSR_READ_4(sc, DC_SIO); 502 if (!(r & DC_PN_SIOCTL_BUSY)) { 503 *dest = (u_int16_t)(r & 0xFFFF); 504 return; 505 } 506 } 507 } 508 509 /* 510 * Read a word of data stored in the EEPROM at address 'addr.' 511 * The Xircom X3201 has its own non-standard way to read 512 * the EEPROM, too. 513 */ 514 static void 515 dc_eeprom_getword_xircom(struct dc_softc *sc, int addr, u_int16_t *dest) 516 { 517 518 SIO_SET(DC_SIO_ROMSEL | DC_SIO_ROMCTL_READ); 519 520 addr *= 2; 521 CSR_WRITE_4(sc, DC_ROM, addr | 0x160); 522 *dest = (u_int16_t)CSR_READ_4(sc, DC_SIO) & 0xff; 523 addr += 1; 524 CSR_WRITE_4(sc, DC_ROM, addr | 0x160); 525 *dest |= ((u_int16_t)CSR_READ_4(sc, DC_SIO) & 0xff) << 8; 526 527 SIO_CLR(DC_SIO_ROMSEL | DC_SIO_ROMCTL_READ); 528 } 529 530 /* 531 * Read a word of data stored in the EEPROM at address 'addr.' 532 */ 533 static void 534 dc_eeprom_getword(struct dc_softc *sc, int addr, u_int16_t *dest) 535 { 536 int i; 537 u_int16_t word = 0; 538 539 /* Force EEPROM to idle state. */ 540 dc_eeprom_idle(sc); 541 542 /* Enter EEPROM access mode. */ 543 CSR_WRITE_4(sc, DC_SIO, DC_SIO_EESEL); 544 dc_delay(sc); 545 DC_SETBIT(sc, DC_SIO, DC_SIO_ROMCTL_READ); 546 dc_delay(sc); 547 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); 548 dc_delay(sc); 549 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CS); 550 dc_delay(sc); 551 552 /* 553 * Send address of word we want to read. 554 */ 555 dc_eeprom_putbyte(sc, addr); 556 557 /* 558 * Start reading bits from EEPROM. 559 */ 560 for (i = 0x8000; i; i >>= 1) { 561 SIO_SET(DC_SIO_EE_CLK); 562 dc_delay(sc); 563 if (CSR_READ_4(sc, DC_SIO) & DC_SIO_EE_DATAOUT) 564 word |= i; 565 dc_delay(sc); 566 SIO_CLR(DC_SIO_EE_CLK); 567 dc_delay(sc); 568 } 569 570 /* Turn off EEPROM access mode. */ 571 dc_eeprom_idle(sc); 572 573 *dest = word; 574 } 575 576 /* 577 * Read a sequence of words from the EEPROM. 578 */ 579 static void 580 dc_read_eeprom(struct dc_softc *sc, caddr_t dest, int off, int cnt, int be) 581 { 582 int i; 583 u_int16_t word = 0, *ptr; 584 585 for (i = 0; i < cnt; i++) { 586 if (DC_IS_PNIC(sc)) 587 dc_eeprom_getword_pnic(sc, off + i, &word); 588 else if (DC_IS_XIRCOM(sc)) 589 dc_eeprom_getword_xircom(sc, off + i, &word); 590 else 591 dc_eeprom_getword(sc, off + i, &word); 592 ptr = (u_int16_t *)(dest + (i * 2)); 593 if (be) 594 *ptr = be16toh(word); 595 else 596 *ptr = le16toh(word); 597 } 598 } 599 600 /* 601 * The following two routines are taken from the Macronix 98713 602 * Application Notes pp.19-21. 603 */ 604 /* 605 * Write a bit to the MII bus. 606 */ 607 static void 608 dc_mii_writebit(struct dc_softc *sc, int bit) 609 { 610 uint32_t reg; 611 612 reg = DC_SIO_ROMCTL_WRITE | (bit != 0 ? DC_SIO_MII_DATAOUT : 0); 613 CSR_WRITE_4(sc, DC_SIO, reg); 614 CSR_BARRIER_4(sc, DC_SIO, 615 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 616 DELAY(1); 617 618 CSR_WRITE_4(sc, DC_SIO, reg | DC_SIO_MII_CLK); 619 CSR_BARRIER_4(sc, DC_SIO, 620 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 621 DELAY(1); 622 CSR_WRITE_4(sc, DC_SIO, reg); 623 CSR_BARRIER_4(sc, DC_SIO, 624 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 625 DELAY(1); 626 } 627 628 /* 629 * Read a bit from the MII bus. 630 */ 631 static int 632 dc_mii_readbit(struct dc_softc *sc) 633 { 634 uint32_t reg; 635 636 reg = DC_SIO_ROMCTL_READ | DC_SIO_MII_DIR; 637 CSR_WRITE_4(sc, DC_SIO, reg); 638 CSR_BARRIER_4(sc, DC_SIO, 639 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 640 DELAY(1); 641 (void)CSR_READ_4(sc, DC_SIO); 642 CSR_WRITE_4(sc, DC_SIO, reg | DC_SIO_MII_CLK); 643 CSR_BARRIER_4(sc, DC_SIO, 644 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 645 DELAY(1); 646 CSR_WRITE_4(sc, DC_SIO, reg); 647 CSR_BARRIER_4(sc, DC_SIO, 648 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 649 DELAY(1); 650 if (CSR_READ_4(sc, DC_SIO) & DC_SIO_MII_DATAIN) 651 return (1); 652 653 return (0); 654 } 655 656 /* 657 * Sync the PHYs by setting data bit and strobing the clock 32 times. 658 */ 659 static void 660 dc_mii_sync(struct dc_softc *sc) 661 { 662 int i; 663 664 CSR_WRITE_4(sc, DC_SIO, DC_SIO_ROMCTL_WRITE); 665 CSR_BARRIER_4(sc, DC_SIO, 666 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 667 DELAY(1); 668 669 for (i = 0; i < 32; i++) 670 dc_mii_writebit(sc, 1); 671 } 672 673 /* 674 * Clock a series of bits through the MII. 675 */ 676 static void 677 dc_mii_send(struct dc_softc *sc, u_int32_t bits, int cnt) 678 { 679 int i; 680 681 for (i = (0x1 << (cnt - 1)); i; i >>= 1) 682 dc_mii_writebit(sc, bits & i); 683 } 684 685 /* 686 * Read an PHY register through the MII. 687 */ 688 static int 689 dc_mii_readreg(struct dc_softc *sc, struct dc_mii_frame *frame) 690 { 691 int i; 692 693 /* 694 * Set up frame for RX. 695 */ 696 frame->mii_stdelim = DC_MII_STARTDELIM; 697 frame->mii_opcode = DC_MII_READOP; 698 699 /* 700 * Sync the PHYs. 701 */ 702 dc_mii_sync(sc); 703 704 /* 705 * Send command/address info. 706 */ 707 dc_mii_send(sc, frame->mii_stdelim, 2); 708 dc_mii_send(sc, frame->mii_opcode, 2); 709 dc_mii_send(sc, frame->mii_phyaddr, 5); 710 dc_mii_send(sc, frame->mii_regaddr, 5); 711 712 /* 713 * Now try reading data bits. If the turnaround failed, we still 714 * need to clock through 16 cycles to keep the PHY(s) in sync. 715 */ 716 frame->mii_turnaround = dc_mii_readbit(sc); 717 if (frame->mii_turnaround != 0) { 718 for (i = 0; i < 16; i++) 719 dc_mii_readbit(sc); 720 goto fail; 721 } 722 for (i = 0x8000; i; i >>= 1) { 723 if (dc_mii_readbit(sc)) 724 frame->mii_data |= i; 725 } 726 727 fail: 728 729 /* Clock the idle bits. */ 730 dc_mii_writebit(sc, 0); 731 dc_mii_writebit(sc, 0); 732 733 if (frame->mii_turnaround != 0) 734 return (1); 735 return (0); 736 } 737 738 /* 739 * Write to a PHY register through the MII. 740 */ 741 static int 742 dc_mii_writereg(struct dc_softc *sc, struct dc_mii_frame *frame) 743 { 744 745 /* 746 * Set up frame for TX. 747 */ 748 frame->mii_stdelim = DC_MII_STARTDELIM; 749 frame->mii_opcode = DC_MII_WRITEOP; 750 frame->mii_turnaround = DC_MII_TURNAROUND; 751 752 /* 753 * Sync the PHYs. 754 */ 755 dc_mii_sync(sc); 756 757 dc_mii_send(sc, frame->mii_stdelim, 2); 758 dc_mii_send(sc, frame->mii_opcode, 2); 759 dc_mii_send(sc, frame->mii_phyaddr, 5); 760 dc_mii_send(sc, frame->mii_regaddr, 5); 761 dc_mii_send(sc, frame->mii_turnaround, 2); 762 dc_mii_send(sc, frame->mii_data, 16); 763 764 /* Clock the idle bits. */ 765 dc_mii_writebit(sc, 0); 766 dc_mii_writebit(sc, 0); 767 768 return (0); 769 } 770 771 static int 772 dc_miibus_readreg(device_t dev, int phy, int reg) 773 { 774 struct dc_mii_frame frame; 775 struct dc_softc *sc; 776 int i, rval, phy_reg = 0; 777 778 sc = device_get_softc(dev); 779 bzero(&frame, sizeof(frame)); 780 781 /* 782 * Note: both the AL981 and AN985 have internal PHYs, 783 * however the AL981 provides direct access to the PHY 784 * registers while the AN985 uses a serial MII interface. 785 * The AN985's MII interface is also buggy in that you 786 * can read from any MII address (0 to 31), but only address 1 787 * behaves normally. To deal with both cases, we pretend 788 * that the PHY is at MII address 1. 789 */ 790 if (DC_IS_ADMTEK(sc) && phy != DC_ADMTEK_PHYADDR) 791 return (0); 792 793 /* 794 * Note: the ukphy probes of the RS7112 report a PHY at 795 * MII address 0 (possibly HomePNA?) and 1 (ethernet) 796 * so we only respond to correct one. 797 */ 798 if (DC_IS_CONEXANT(sc) && phy != DC_CONEXANT_PHYADDR) 799 return (0); 800 801 if (sc->dc_pmode != DC_PMODE_MII) { 802 if (phy == (MII_NPHY - 1)) { 803 switch (reg) { 804 case MII_BMSR: 805 /* 806 * Fake something to make the probe 807 * code think there's a PHY here. 808 */ 809 return (BMSR_MEDIAMASK); 810 break; 811 case MII_PHYIDR1: 812 if (DC_IS_PNIC(sc)) 813 return (DC_VENDORID_LO); 814 return (DC_VENDORID_DEC); 815 break; 816 case MII_PHYIDR2: 817 if (DC_IS_PNIC(sc)) 818 return (DC_DEVICEID_82C168); 819 return (DC_DEVICEID_21143); 820 break; 821 default: 822 return (0); 823 break; 824 } 825 } else 826 return (0); 827 } 828 829 if (DC_IS_PNIC(sc)) { 830 CSR_WRITE_4(sc, DC_PN_MII, DC_PN_MIIOPCODE_READ | 831 (phy << 23) | (reg << 18)); 832 for (i = 0; i < DC_TIMEOUT; i++) { 833 DELAY(1); 834 rval = CSR_READ_4(sc, DC_PN_MII); 835 if (!(rval & DC_PN_MII_BUSY)) { 836 rval &= 0xFFFF; 837 return (rval == 0xFFFF ? 0 : rval); 838 } 839 } 840 return (0); 841 } 842 843 if (DC_IS_COMET(sc)) { 844 switch (reg) { 845 case MII_BMCR: 846 phy_reg = DC_AL_BMCR; 847 break; 848 case MII_BMSR: 849 phy_reg = DC_AL_BMSR; 850 break; 851 case MII_PHYIDR1: 852 phy_reg = DC_AL_VENID; 853 break; 854 case MII_PHYIDR2: 855 phy_reg = DC_AL_DEVID; 856 break; 857 case MII_ANAR: 858 phy_reg = DC_AL_ANAR; 859 break; 860 case MII_ANLPAR: 861 phy_reg = DC_AL_LPAR; 862 break; 863 case MII_ANER: 864 phy_reg = DC_AL_ANER; 865 break; 866 default: 867 device_printf(dev, "phy_read: bad phy register %x\n", 868 reg); 869 return (0); 870 break; 871 } 872 873 rval = CSR_READ_4(sc, phy_reg) & 0x0000FFFF; 874 875 if (rval == 0xFFFF) 876 return (0); 877 return (rval); 878 } 879 880 frame.mii_phyaddr = phy; 881 frame.mii_regaddr = reg; 882 if (sc->dc_type == DC_TYPE_98713) { 883 phy_reg = CSR_READ_4(sc, DC_NETCFG); 884 CSR_WRITE_4(sc, DC_NETCFG, phy_reg & ~DC_NETCFG_PORTSEL); 885 } 886 dc_mii_readreg(sc, &frame); 887 if (sc->dc_type == DC_TYPE_98713) 888 CSR_WRITE_4(sc, DC_NETCFG, phy_reg); 889 890 return (frame.mii_data); 891 } 892 893 static int 894 dc_miibus_writereg(device_t dev, int phy, int reg, int data) 895 { 896 struct dc_softc *sc; 897 struct dc_mii_frame frame; 898 int i, phy_reg = 0; 899 900 sc = device_get_softc(dev); 901 bzero(&frame, sizeof(frame)); 902 903 if (DC_IS_ADMTEK(sc) && phy != DC_ADMTEK_PHYADDR) 904 return (0); 905 906 if (DC_IS_CONEXANT(sc) && phy != DC_CONEXANT_PHYADDR) 907 return (0); 908 909 if (DC_IS_PNIC(sc)) { 910 CSR_WRITE_4(sc, DC_PN_MII, DC_PN_MIIOPCODE_WRITE | 911 (phy << 23) | (reg << 10) | data); 912 for (i = 0; i < DC_TIMEOUT; i++) { 913 if (!(CSR_READ_4(sc, DC_PN_MII) & DC_PN_MII_BUSY)) 914 break; 915 } 916 return (0); 917 } 918 919 if (DC_IS_COMET(sc)) { 920 switch (reg) { 921 case MII_BMCR: 922 phy_reg = DC_AL_BMCR; 923 break; 924 case MII_BMSR: 925 phy_reg = DC_AL_BMSR; 926 break; 927 case MII_PHYIDR1: 928 phy_reg = DC_AL_VENID; 929 break; 930 case MII_PHYIDR2: 931 phy_reg = DC_AL_DEVID; 932 break; 933 case MII_ANAR: 934 phy_reg = DC_AL_ANAR; 935 break; 936 case MII_ANLPAR: 937 phy_reg = DC_AL_LPAR; 938 break; 939 case MII_ANER: 940 phy_reg = DC_AL_ANER; 941 break; 942 default: 943 device_printf(dev, "phy_write: bad phy register %x\n", 944 reg); 945 return (0); 946 break; 947 } 948 949 CSR_WRITE_4(sc, phy_reg, data); 950 return (0); 951 } 952 953 frame.mii_phyaddr = phy; 954 frame.mii_regaddr = reg; 955 frame.mii_data = data; 956 957 if (sc->dc_type == DC_TYPE_98713) { 958 phy_reg = CSR_READ_4(sc, DC_NETCFG); 959 CSR_WRITE_4(sc, DC_NETCFG, phy_reg & ~DC_NETCFG_PORTSEL); 960 } 961 dc_mii_writereg(sc, &frame); 962 if (sc->dc_type == DC_TYPE_98713) 963 CSR_WRITE_4(sc, DC_NETCFG, phy_reg); 964 965 return (0); 966 } 967 968 static void 969 dc_miibus_statchg(device_t dev) 970 { 971 struct dc_softc *sc; 972 struct mii_data *mii; 973 struct ifmedia *ifm; 974 975 sc = device_get_softc(dev); 976 if (DC_IS_ADMTEK(sc)) 977 return; 978 979 mii = device_get_softc(sc->dc_miibus); 980 ifm = &mii->mii_media; 981 if (DC_IS_DAVICOM(sc) && 982 IFM_SUBTYPE(ifm->ifm_media) == IFM_HPNA_1) { 983 dc_setcfg(sc, ifm->ifm_media); 984 sc->dc_if_media = ifm->ifm_media; 985 } else { 986 dc_setcfg(sc, mii->mii_media_active); 987 sc->dc_if_media = mii->mii_media_active; 988 } 989 } 990 991 /* 992 * Special support for DM9102A cards with HomePNA PHYs. Note: 993 * with the Davicom DM9102A/DM9801 eval board that I have, it seems 994 * to be impossible to talk to the management interface of the DM9801 995 * PHY (its MDIO pin is not connected to anything). Consequently, 996 * the driver has to just 'know' about the additional mode and deal 997 * with it itself. *sigh* 998 */ 999 static void 1000 dc_miibus_mediainit(device_t dev) 1001 { 1002 struct dc_softc *sc; 1003 struct mii_data *mii; 1004 struct ifmedia *ifm; 1005 int rev; 1006 1007 rev = pci_get_revid(dev); 1008 1009 sc = device_get_softc(dev); 1010 mii = device_get_softc(sc->dc_miibus); 1011 ifm = &mii->mii_media; 1012 1013 if (DC_IS_DAVICOM(sc) && rev >= DC_REVISION_DM9102A) 1014 ifmedia_add(ifm, IFM_ETHER | IFM_HPNA_1, 0, NULL); 1015 } 1016 1017 #define DC_BITS_512 9 1018 #define DC_BITS_128 7 1019 #define DC_BITS_64 6 1020 1021 static uint32_t 1022 dc_mchash_le(struct dc_softc *sc, const uint8_t *addr) 1023 { 1024 uint32_t crc; 1025 1026 /* Compute CRC for the address value. */ 1027 crc = ether_crc32_le(addr, ETHER_ADDR_LEN); 1028 1029 /* 1030 * The hash table on the PNIC II and the MX98715AEC-C/D/E 1031 * chips is only 128 bits wide. 1032 */ 1033 if (sc->dc_flags & DC_128BIT_HASH) 1034 return (crc & ((1 << DC_BITS_128) - 1)); 1035 1036 /* The hash table on the MX98715BEC is only 64 bits wide. */ 1037 if (sc->dc_flags & DC_64BIT_HASH) 1038 return (crc & ((1 << DC_BITS_64) - 1)); 1039 1040 /* Xircom's hash filtering table is different (read: weird) */ 1041 /* Xircom uses the LEAST significant bits */ 1042 if (DC_IS_XIRCOM(sc)) { 1043 if ((crc & 0x180) == 0x180) 1044 return ((crc & 0x0F) + (crc & 0x70) * 3 + (14 << 4)); 1045 else 1046 return ((crc & 0x1F) + ((crc >> 1) & 0xF0) * 3 + 1047 (12 << 4)); 1048 } 1049 1050 return (crc & ((1 << DC_BITS_512) - 1)); 1051 } 1052 1053 /* 1054 * Calculate CRC of a multicast group address, return the lower 6 bits. 1055 */ 1056 static uint32_t 1057 dc_mchash_be(const uint8_t *addr) 1058 { 1059 uint32_t crc; 1060 1061 /* Compute CRC for the address value. */ 1062 crc = ether_crc32_be(addr, ETHER_ADDR_LEN); 1063 1064 /* Return the filter bit position. */ 1065 return ((crc >> 26) & 0x0000003F); 1066 } 1067 1068 /* 1069 * 21143-style RX filter setup routine. Filter programming is done by 1070 * downloading a special setup frame into the TX engine. 21143, Macronix, 1071 * PNIC, PNIC II and Davicom chips are programmed this way. 1072 * 1073 * We always program the chip using 'hash perfect' mode, i.e. one perfect 1074 * address (our node address) and a 512-bit hash filter for multicast 1075 * frames. We also sneak the broadcast address into the hash filter since 1076 * we need that too. 1077 */ 1078 static void 1079 dc_setfilt_21143(struct dc_softc *sc) 1080 { 1081 uint16_t eaddr[(ETHER_ADDR_LEN+1)/2]; 1082 struct dc_desc *sframe; 1083 u_int32_t h, *sp; 1084 struct ifmultiaddr *ifma; 1085 struct ifnet *ifp; 1086 int i; 1087 1088 ifp = sc->dc_ifp; 1089 1090 i = sc->dc_cdata.dc_tx_prod; 1091 DC_INC(sc->dc_cdata.dc_tx_prod, DC_TX_LIST_CNT); 1092 sc->dc_cdata.dc_tx_cnt++; 1093 sframe = &sc->dc_ldata->dc_tx_list[i]; 1094 sp = sc->dc_cdata.dc_sbuf; 1095 bzero(sp, DC_SFRAME_LEN); 1096 1097 sframe->dc_data = htole32(sc->dc_saddr); 1098 sframe->dc_ctl = htole32(DC_SFRAME_LEN | DC_TXCTL_SETUP | 1099 DC_TXCTL_TLINK | DC_FILTER_HASHPERF | DC_TXCTL_FINT); 1100 1101 sc->dc_cdata.dc_tx_chain[i] = (struct mbuf *)sc->dc_cdata.dc_sbuf; 1102 1103 /* If we want promiscuous mode, set the allframes bit. */ 1104 if (ifp->if_flags & IFF_PROMISC) 1105 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC); 1106 else 1107 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC); 1108 1109 if (ifp->if_flags & IFF_ALLMULTI) 1110 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI); 1111 else 1112 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI); 1113 1114 IF_ADDR_LOCK(ifp); 1115 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 1116 if (ifma->ifma_addr->sa_family != AF_LINK) 1117 continue; 1118 h = dc_mchash_le(sc, 1119 LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 1120 sp[h >> 4] |= htole32(1 << (h & 0xF)); 1121 } 1122 IF_ADDR_UNLOCK(ifp); 1123 1124 if (ifp->if_flags & IFF_BROADCAST) { 1125 h = dc_mchash_le(sc, ifp->if_broadcastaddr); 1126 sp[h >> 4] |= htole32(1 << (h & 0xF)); 1127 } 1128 1129 /* Set our MAC address. */ 1130 bcopy(IF_LLADDR(sc->dc_ifp), eaddr, ETHER_ADDR_LEN); 1131 sp[39] = DC_SP_MAC(eaddr[0]); 1132 sp[40] = DC_SP_MAC(eaddr[1]); 1133 sp[41] = DC_SP_MAC(eaddr[2]); 1134 1135 sframe->dc_status = htole32(DC_TXSTAT_OWN); 1136 CSR_WRITE_4(sc, DC_TXSTART, 0xFFFFFFFF); 1137 1138 /* 1139 * The PNIC takes an exceedingly long time to process its 1140 * setup frame; wait 10ms after posting the setup frame 1141 * before proceeding, just so it has time to swallow its 1142 * medicine. 1143 */ 1144 DELAY(10000); 1145 1146 sc->dc_wdog_timer = 5; 1147 } 1148 1149 static void 1150 dc_setfilt_admtek(struct dc_softc *sc) 1151 { 1152 uint8_t eaddr[ETHER_ADDR_LEN]; 1153 struct ifnet *ifp; 1154 struct ifmultiaddr *ifma; 1155 int h = 0; 1156 u_int32_t hashes[2] = { 0, 0 }; 1157 1158 ifp = sc->dc_ifp; 1159 1160 /* Init our MAC address. */ 1161 bcopy(IF_LLADDR(sc->dc_ifp), eaddr, ETHER_ADDR_LEN); 1162 CSR_WRITE_4(sc, DC_AL_PAR0, eaddr[3] << 24 | eaddr[2] << 16 | 1163 eaddr[1] << 8 | eaddr[0]); 1164 CSR_WRITE_4(sc, DC_AL_PAR1, eaddr[5] << 8 | eaddr[4]); 1165 1166 /* If we want promiscuous mode, set the allframes bit. */ 1167 if (ifp->if_flags & IFF_PROMISC) 1168 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC); 1169 else 1170 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC); 1171 1172 if (ifp->if_flags & IFF_ALLMULTI) 1173 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI); 1174 else 1175 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI); 1176 1177 /* First, zot all the existing hash bits. */ 1178 CSR_WRITE_4(sc, DC_AL_MAR0, 0); 1179 CSR_WRITE_4(sc, DC_AL_MAR1, 0); 1180 1181 /* 1182 * If we're already in promisc or allmulti mode, we 1183 * don't have to bother programming the multicast filter. 1184 */ 1185 if (ifp->if_flags & (IFF_PROMISC | IFF_ALLMULTI)) 1186 return; 1187 1188 /* Now program new ones. */ 1189 IF_ADDR_LOCK(ifp); 1190 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 1191 if (ifma->ifma_addr->sa_family != AF_LINK) 1192 continue; 1193 if (DC_IS_CENTAUR(sc)) 1194 h = dc_mchash_le(sc, 1195 LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 1196 else 1197 h = dc_mchash_be( 1198 LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 1199 if (h < 32) 1200 hashes[0] |= (1 << h); 1201 else 1202 hashes[1] |= (1 << (h - 32)); 1203 } 1204 IF_ADDR_UNLOCK(ifp); 1205 1206 CSR_WRITE_4(sc, DC_AL_MAR0, hashes[0]); 1207 CSR_WRITE_4(sc, DC_AL_MAR1, hashes[1]); 1208 } 1209 1210 static void 1211 dc_setfilt_asix(struct dc_softc *sc) 1212 { 1213 uint32_t eaddr[(ETHER_ADDR_LEN+3)/4]; 1214 struct ifnet *ifp; 1215 struct ifmultiaddr *ifma; 1216 int h = 0; 1217 u_int32_t hashes[2] = { 0, 0 }; 1218 1219 ifp = sc->dc_ifp; 1220 1221 /* Init our MAC address. */ 1222 bcopy(IF_LLADDR(sc->dc_ifp), eaddr, ETHER_ADDR_LEN); 1223 CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_PAR0); 1224 CSR_WRITE_4(sc, DC_AX_FILTDATA, eaddr[0]); 1225 CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_PAR1); 1226 CSR_WRITE_4(sc, DC_AX_FILTDATA, eaddr[1]); 1227 1228 /* If we want promiscuous mode, set the allframes bit. */ 1229 if (ifp->if_flags & IFF_PROMISC) 1230 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC); 1231 else 1232 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC); 1233 1234 if (ifp->if_flags & IFF_ALLMULTI) 1235 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI); 1236 else 1237 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI); 1238 1239 /* 1240 * The ASIX chip has a special bit to enable reception 1241 * of broadcast frames. 1242 */ 1243 if (ifp->if_flags & IFF_BROADCAST) 1244 DC_SETBIT(sc, DC_NETCFG, DC_AX_NETCFG_RX_BROAD); 1245 else 1246 DC_CLRBIT(sc, DC_NETCFG, DC_AX_NETCFG_RX_BROAD); 1247 1248 /* first, zot all the existing hash bits */ 1249 CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_MAR0); 1250 CSR_WRITE_4(sc, DC_AX_FILTDATA, 0); 1251 CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_MAR1); 1252 CSR_WRITE_4(sc, DC_AX_FILTDATA, 0); 1253 1254 /* 1255 * If we're already in promisc or allmulti mode, we 1256 * don't have to bother programming the multicast filter. 1257 */ 1258 if (ifp->if_flags & (IFF_PROMISC | IFF_ALLMULTI)) 1259 return; 1260 1261 /* now program new ones */ 1262 IF_ADDR_LOCK(ifp); 1263 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 1264 if (ifma->ifma_addr->sa_family != AF_LINK) 1265 continue; 1266 h = dc_mchash_be(LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 1267 if (h < 32) 1268 hashes[0] |= (1 << h); 1269 else 1270 hashes[1] |= (1 << (h - 32)); 1271 } 1272 IF_ADDR_UNLOCK(ifp); 1273 1274 CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_MAR0); 1275 CSR_WRITE_4(sc, DC_AX_FILTDATA, hashes[0]); 1276 CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_MAR1); 1277 CSR_WRITE_4(sc, DC_AX_FILTDATA, hashes[1]); 1278 } 1279 1280 static void 1281 dc_setfilt_xircom(struct dc_softc *sc) 1282 { 1283 uint16_t eaddr[(ETHER_ADDR_LEN+1)/2]; 1284 struct ifnet *ifp; 1285 struct ifmultiaddr *ifma; 1286 struct dc_desc *sframe; 1287 u_int32_t h, *sp; 1288 int i; 1289 1290 ifp = sc->dc_ifp; 1291 DC_CLRBIT(sc, DC_NETCFG, (DC_NETCFG_TX_ON | DC_NETCFG_RX_ON)); 1292 1293 i = sc->dc_cdata.dc_tx_prod; 1294 DC_INC(sc->dc_cdata.dc_tx_prod, DC_TX_LIST_CNT); 1295 sc->dc_cdata.dc_tx_cnt++; 1296 sframe = &sc->dc_ldata->dc_tx_list[i]; 1297 sp = sc->dc_cdata.dc_sbuf; 1298 bzero(sp, DC_SFRAME_LEN); 1299 1300 sframe->dc_data = htole32(sc->dc_saddr); 1301 sframe->dc_ctl = htole32(DC_SFRAME_LEN | DC_TXCTL_SETUP | 1302 DC_TXCTL_TLINK | DC_FILTER_HASHPERF | DC_TXCTL_FINT); 1303 1304 sc->dc_cdata.dc_tx_chain[i] = (struct mbuf *)sc->dc_cdata.dc_sbuf; 1305 1306 /* If we want promiscuous mode, set the allframes bit. */ 1307 if (ifp->if_flags & IFF_PROMISC) 1308 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC); 1309 else 1310 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC); 1311 1312 if (ifp->if_flags & IFF_ALLMULTI) 1313 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI); 1314 else 1315 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI); 1316 1317 IF_ADDR_LOCK(ifp); 1318 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 1319 if (ifma->ifma_addr->sa_family != AF_LINK) 1320 continue; 1321 h = dc_mchash_le(sc, 1322 LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 1323 sp[h >> 4] |= htole32(1 << (h & 0xF)); 1324 } 1325 IF_ADDR_UNLOCK(ifp); 1326 1327 if (ifp->if_flags & IFF_BROADCAST) { 1328 h = dc_mchash_le(sc, ifp->if_broadcastaddr); 1329 sp[h >> 4] |= htole32(1 << (h & 0xF)); 1330 } 1331 1332 /* Set our MAC address. */ 1333 bcopy(IF_LLADDR(sc->dc_ifp), eaddr, ETHER_ADDR_LEN); 1334 sp[0] = DC_SP_MAC(eaddr[0]); 1335 sp[1] = DC_SP_MAC(eaddr[1]); 1336 sp[2] = DC_SP_MAC(eaddr[2]); 1337 1338 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_TX_ON); 1339 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_ON); 1340 ifp->if_drv_flags |= IFF_DRV_RUNNING; 1341 sframe->dc_status = htole32(DC_TXSTAT_OWN); 1342 CSR_WRITE_4(sc, DC_TXSTART, 0xFFFFFFFF); 1343 1344 /* 1345 * Wait some time... 1346 */ 1347 DELAY(1000); 1348 1349 sc->dc_wdog_timer = 5; 1350 } 1351 1352 static void 1353 dc_setfilt(struct dc_softc *sc) 1354 { 1355 1356 if (DC_IS_INTEL(sc) || DC_IS_MACRONIX(sc) || DC_IS_PNIC(sc) || 1357 DC_IS_PNICII(sc) || DC_IS_DAVICOM(sc) || DC_IS_CONEXANT(sc)) 1358 dc_setfilt_21143(sc); 1359 1360 if (DC_IS_ASIX(sc)) 1361 dc_setfilt_asix(sc); 1362 1363 if (DC_IS_ADMTEK(sc)) 1364 dc_setfilt_admtek(sc); 1365 1366 if (DC_IS_XIRCOM(sc)) 1367 dc_setfilt_xircom(sc); 1368 } 1369 1370 /* 1371 * In order to fiddle with the 'full-duplex' and '100Mbps' bits in 1372 * the netconfig register, we first have to put the transmit and/or 1373 * receive logic in the idle state. 1374 */ 1375 static void 1376 dc_setcfg(struct dc_softc *sc, int media) 1377 { 1378 int i, restart = 0, watchdogreg; 1379 u_int32_t isr; 1380 1381 if (IFM_SUBTYPE(media) == IFM_NONE) 1382 return; 1383 1384 if (CSR_READ_4(sc, DC_NETCFG) & (DC_NETCFG_TX_ON | DC_NETCFG_RX_ON)) { 1385 restart = 1; 1386 DC_CLRBIT(sc, DC_NETCFG, (DC_NETCFG_TX_ON | DC_NETCFG_RX_ON)); 1387 1388 for (i = 0; i < DC_TIMEOUT; i++) { 1389 isr = CSR_READ_4(sc, DC_ISR); 1390 if (isr & DC_ISR_TX_IDLE && 1391 ((isr & DC_ISR_RX_STATE) == DC_RXSTATE_STOPPED || 1392 (isr & DC_ISR_RX_STATE) == DC_RXSTATE_WAIT)) 1393 break; 1394 DELAY(10); 1395 } 1396 1397 if (i == DC_TIMEOUT) { 1398 if (!(isr & DC_ISR_TX_IDLE) && !DC_IS_ASIX(sc)) 1399 device_printf(sc->dc_dev, 1400 "%s: failed to force tx to idle state\n", 1401 __func__); 1402 if (!((isr & DC_ISR_RX_STATE) == DC_RXSTATE_STOPPED || 1403 (isr & DC_ISR_RX_STATE) == DC_RXSTATE_WAIT) && 1404 !DC_HAS_BROKEN_RXSTATE(sc)) 1405 device_printf(sc->dc_dev, 1406 "%s: failed to force rx to idle state\n", 1407 __func__); 1408 } 1409 } 1410 1411 if (IFM_SUBTYPE(media) == IFM_100_TX) { 1412 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_SPEEDSEL); 1413 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_HEARTBEAT); 1414 if (sc->dc_pmode == DC_PMODE_MII) { 1415 if (DC_IS_INTEL(sc)) { 1416 /* There's a write enable bit here that reads as 1. */ 1417 watchdogreg = CSR_READ_4(sc, DC_WATCHDOG); 1418 watchdogreg &= ~DC_WDOG_CTLWREN; 1419 watchdogreg |= DC_WDOG_JABBERDIS; 1420 CSR_WRITE_4(sc, DC_WATCHDOG, watchdogreg); 1421 } else { 1422 DC_SETBIT(sc, DC_WATCHDOG, DC_WDOG_JABBERDIS); 1423 } 1424 DC_CLRBIT(sc, DC_NETCFG, (DC_NETCFG_PCS | 1425 DC_NETCFG_PORTSEL | DC_NETCFG_SCRAMBLER)); 1426 if (sc->dc_type == DC_TYPE_98713) 1427 DC_SETBIT(sc, DC_NETCFG, (DC_NETCFG_PCS | 1428 DC_NETCFG_SCRAMBLER)); 1429 if (!DC_IS_DAVICOM(sc)) 1430 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL); 1431 DC_CLRBIT(sc, DC_10BTCTRL, 0xFFFF); 1432 if (DC_IS_INTEL(sc)) 1433 dc_apply_fixup(sc, IFM_AUTO); 1434 } else { 1435 if (DC_IS_PNIC(sc)) { 1436 DC_PN_GPIO_SETBIT(sc, DC_PN_GPIO_SPEEDSEL); 1437 DC_PN_GPIO_SETBIT(sc, DC_PN_GPIO_100TX_LOOP); 1438 DC_SETBIT(sc, DC_PN_NWAY, DC_PN_NWAY_SPEEDSEL); 1439 } 1440 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL); 1441 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PCS); 1442 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_SCRAMBLER); 1443 if (DC_IS_INTEL(sc)) 1444 dc_apply_fixup(sc, 1445 (media & IFM_GMASK) == IFM_FDX ? 1446 IFM_100_TX | IFM_FDX : IFM_100_TX); 1447 } 1448 } 1449 1450 if (IFM_SUBTYPE(media) == IFM_10_T) { 1451 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_SPEEDSEL); 1452 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_HEARTBEAT); 1453 if (sc->dc_pmode == DC_PMODE_MII) { 1454 /* There's a write enable bit here that reads as 1. */ 1455 if (DC_IS_INTEL(sc)) { 1456 watchdogreg = CSR_READ_4(sc, DC_WATCHDOG); 1457 watchdogreg &= ~DC_WDOG_CTLWREN; 1458 watchdogreg |= DC_WDOG_JABBERDIS; 1459 CSR_WRITE_4(sc, DC_WATCHDOG, watchdogreg); 1460 } else { 1461 DC_SETBIT(sc, DC_WATCHDOG, DC_WDOG_JABBERDIS); 1462 } 1463 DC_CLRBIT(sc, DC_NETCFG, (DC_NETCFG_PCS | 1464 DC_NETCFG_PORTSEL | DC_NETCFG_SCRAMBLER)); 1465 if (sc->dc_type == DC_TYPE_98713) 1466 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PCS); 1467 if (!DC_IS_DAVICOM(sc)) 1468 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL); 1469 DC_CLRBIT(sc, DC_10BTCTRL, 0xFFFF); 1470 if (DC_IS_INTEL(sc)) 1471 dc_apply_fixup(sc, IFM_AUTO); 1472 } else { 1473 if (DC_IS_PNIC(sc)) { 1474 DC_PN_GPIO_CLRBIT(sc, DC_PN_GPIO_SPEEDSEL); 1475 DC_PN_GPIO_SETBIT(sc, DC_PN_GPIO_100TX_LOOP); 1476 DC_CLRBIT(sc, DC_PN_NWAY, DC_PN_NWAY_SPEEDSEL); 1477 } 1478 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL); 1479 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_PCS); 1480 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_SCRAMBLER); 1481 if (DC_IS_INTEL(sc)) { 1482 DC_CLRBIT(sc, DC_SIARESET, DC_SIA_RESET); 1483 DC_CLRBIT(sc, DC_10BTCTRL, 0xFFFF); 1484 if ((media & IFM_GMASK) == IFM_FDX) 1485 DC_SETBIT(sc, DC_10BTCTRL, 0x7F3D); 1486 else 1487 DC_SETBIT(sc, DC_10BTCTRL, 0x7F3F); 1488 DC_SETBIT(sc, DC_SIARESET, DC_SIA_RESET); 1489 DC_CLRBIT(sc, DC_10BTCTRL, 1490 DC_TCTL_AUTONEGENBL); 1491 dc_apply_fixup(sc, 1492 (media & IFM_GMASK) == IFM_FDX ? 1493 IFM_10_T | IFM_FDX : IFM_10_T); 1494 DELAY(20000); 1495 } 1496 } 1497 } 1498 1499 /* 1500 * If this is a Davicom DM9102A card with a DM9801 HomePNA 1501 * PHY and we want HomePNA mode, set the portsel bit to turn 1502 * on the external MII port. 1503 */ 1504 if (DC_IS_DAVICOM(sc)) { 1505 if (IFM_SUBTYPE(media) == IFM_HPNA_1) { 1506 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL); 1507 sc->dc_link = 1; 1508 } else { 1509 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL); 1510 } 1511 } 1512 1513 if ((media & IFM_GMASK) == IFM_FDX) { 1514 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_FULLDUPLEX); 1515 if (sc->dc_pmode == DC_PMODE_SYM && DC_IS_PNIC(sc)) 1516 DC_SETBIT(sc, DC_PN_NWAY, DC_PN_NWAY_DUPLEX); 1517 } else { 1518 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_FULLDUPLEX); 1519 if (sc->dc_pmode == DC_PMODE_SYM && DC_IS_PNIC(sc)) 1520 DC_CLRBIT(sc, DC_PN_NWAY, DC_PN_NWAY_DUPLEX); 1521 } 1522 1523 if (restart) 1524 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_TX_ON | DC_NETCFG_RX_ON); 1525 } 1526 1527 static void 1528 dc_reset(struct dc_softc *sc) 1529 { 1530 int i; 1531 1532 DC_SETBIT(sc, DC_BUSCTL, DC_BUSCTL_RESET); 1533 1534 for (i = 0; i < DC_TIMEOUT; i++) { 1535 DELAY(10); 1536 if (!(CSR_READ_4(sc, DC_BUSCTL) & DC_BUSCTL_RESET)) 1537 break; 1538 } 1539 1540 if (DC_IS_ASIX(sc) || DC_IS_ADMTEK(sc) || DC_IS_CONEXANT(sc) || 1541 DC_IS_XIRCOM(sc) || DC_IS_INTEL(sc)) { 1542 DELAY(10000); 1543 DC_CLRBIT(sc, DC_BUSCTL, DC_BUSCTL_RESET); 1544 i = 0; 1545 } 1546 1547 if (i == DC_TIMEOUT) 1548 device_printf(sc->dc_dev, "reset never completed!\n"); 1549 1550 /* Wait a little while for the chip to get its brains in order. */ 1551 DELAY(1000); 1552 1553 CSR_WRITE_4(sc, DC_IMR, 0x00000000); 1554 CSR_WRITE_4(sc, DC_BUSCTL, 0x00000000); 1555 CSR_WRITE_4(sc, DC_NETCFG, 0x00000000); 1556 1557 /* 1558 * Bring the SIA out of reset. In some cases, it looks 1559 * like failing to unreset the SIA soon enough gets it 1560 * into a state where it will never come out of reset 1561 * until we reset the whole chip again. 1562 */ 1563 if (DC_IS_INTEL(sc)) { 1564 DC_SETBIT(sc, DC_SIARESET, DC_SIA_RESET); 1565 CSR_WRITE_4(sc, DC_10BTCTRL, 0); 1566 CSR_WRITE_4(sc, DC_WATCHDOG, 0); 1567 } 1568 } 1569 1570 static const struct dc_type * 1571 dc_devtype(device_t dev) 1572 { 1573 const struct dc_type *t; 1574 u_int32_t devid; 1575 u_int8_t rev; 1576 1577 t = dc_devs; 1578 devid = pci_get_devid(dev); 1579 rev = pci_get_revid(dev); 1580 1581 while (t->dc_name != NULL) { 1582 if (devid == t->dc_devid && rev >= t->dc_minrev) 1583 return (t); 1584 t++; 1585 } 1586 1587 return (NULL); 1588 } 1589 1590 /* 1591 * Probe for a 21143 or clone chip. Check the PCI vendor and device 1592 * IDs against our list and return a device name if we find a match. 1593 * We do a little bit of extra work to identify the exact type of 1594 * chip. The MX98713 and MX98713A have the same PCI vendor/device ID, 1595 * but different revision IDs. The same is true for 98715/98715A 1596 * chips and the 98725, as well as the ASIX and ADMtek chips. In some 1597 * cases, the exact chip revision affects driver behavior. 1598 */ 1599 static int 1600 dc_probe(device_t dev) 1601 { 1602 const struct dc_type *t; 1603 1604 t = dc_devtype(dev); 1605 1606 if (t != NULL) { 1607 device_set_desc(dev, t->dc_name); 1608 return (BUS_PROBE_DEFAULT); 1609 } 1610 1611 return (ENXIO); 1612 } 1613 1614 static void 1615 dc_apply_fixup(struct dc_softc *sc, int media) 1616 { 1617 struct dc_mediainfo *m; 1618 u_int8_t *p; 1619 int i; 1620 u_int32_t reg; 1621 1622 m = sc->dc_mi; 1623 1624 while (m != NULL) { 1625 if (m->dc_media == media) 1626 break; 1627 m = m->dc_next; 1628 } 1629 1630 if (m == NULL) 1631 return; 1632 1633 for (i = 0, p = m->dc_reset_ptr; i < m->dc_reset_len; i++, p += 2) { 1634 reg = (p[0] | (p[1] << 8)) << 16; 1635 CSR_WRITE_4(sc, DC_WATCHDOG, reg); 1636 } 1637 1638 for (i = 0, p = m->dc_gp_ptr; i < m->dc_gp_len; i++, p += 2) { 1639 reg = (p[0] | (p[1] << 8)) << 16; 1640 CSR_WRITE_4(sc, DC_WATCHDOG, reg); 1641 } 1642 } 1643 1644 static void 1645 dc_decode_leaf_sia(struct dc_softc *sc, struct dc_eblock_sia *l) 1646 { 1647 struct dc_mediainfo *m; 1648 1649 m = malloc(sizeof(struct dc_mediainfo), M_DEVBUF, M_NOWAIT | M_ZERO); 1650 switch (l->dc_sia_code & ~DC_SIA_CODE_EXT) { 1651 case DC_SIA_CODE_10BT: 1652 m->dc_media = IFM_10_T; 1653 break; 1654 case DC_SIA_CODE_10BT_FDX: 1655 m->dc_media = IFM_10_T | IFM_FDX; 1656 break; 1657 case DC_SIA_CODE_10B2: 1658 m->dc_media = IFM_10_2; 1659 break; 1660 case DC_SIA_CODE_10B5: 1661 m->dc_media = IFM_10_5; 1662 break; 1663 default: 1664 break; 1665 } 1666 1667 /* 1668 * We need to ignore CSR13, CSR14, CSR15 for SIA mode. 1669 * Things apparently already work for cards that do 1670 * supply Media Specific Data. 1671 */ 1672 if (l->dc_sia_code & DC_SIA_CODE_EXT) { 1673 m->dc_gp_len = 2; 1674 m->dc_gp_ptr = 1675 (u_int8_t *)&l->dc_un.dc_sia_ext.dc_sia_gpio_ctl; 1676 } else { 1677 m->dc_gp_len = 2; 1678 m->dc_gp_ptr = 1679 (u_int8_t *)&l->dc_un.dc_sia_noext.dc_sia_gpio_ctl; 1680 } 1681 1682 m->dc_next = sc->dc_mi; 1683 sc->dc_mi = m; 1684 1685 sc->dc_pmode = DC_PMODE_SIA; 1686 } 1687 1688 static void 1689 dc_decode_leaf_sym(struct dc_softc *sc, struct dc_eblock_sym *l) 1690 { 1691 struct dc_mediainfo *m; 1692 1693 m = malloc(sizeof(struct dc_mediainfo), M_DEVBUF, M_NOWAIT | M_ZERO); 1694 if (l->dc_sym_code == DC_SYM_CODE_100BT) 1695 m->dc_media = IFM_100_TX; 1696 1697 if (l->dc_sym_code == DC_SYM_CODE_100BT_FDX) 1698 m->dc_media = IFM_100_TX | IFM_FDX; 1699 1700 m->dc_gp_len = 2; 1701 m->dc_gp_ptr = (u_int8_t *)&l->dc_sym_gpio_ctl; 1702 1703 m->dc_next = sc->dc_mi; 1704 sc->dc_mi = m; 1705 1706 sc->dc_pmode = DC_PMODE_SYM; 1707 } 1708 1709 static void 1710 dc_decode_leaf_mii(struct dc_softc *sc, struct dc_eblock_mii *l) 1711 { 1712 struct dc_mediainfo *m; 1713 u_int8_t *p; 1714 1715 m = malloc(sizeof(struct dc_mediainfo), M_DEVBUF, M_NOWAIT | M_ZERO); 1716 /* We abuse IFM_AUTO to represent MII. */ 1717 m->dc_media = IFM_AUTO; 1718 m->dc_gp_len = l->dc_gpr_len; 1719 1720 p = (u_int8_t *)l; 1721 p += sizeof(struct dc_eblock_mii); 1722 m->dc_gp_ptr = p; 1723 p += 2 * l->dc_gpr_len; 1724 m->dc_reset_len = *p; 1725 p++; 1726 m->dc_reset_ptr = p; 1727 1728 m->dc_next = sc->dc_mi; 1729 sc->dc_mi = m; 1730 } 1731 1732 static void 1733 dc_read_srom(struct dc_softc *sc, int bits) 1734 { 1735 int size; 1736 1737 size = 2 << bits; 1738 sc->dc_srom = malloc(size, M_DEVBUF, M_NOWAIT); 1739 dc_read_eeprom(sc, (caddr_t)sc->dc_srom, 0, (size / 2), 0); 1740 } 1741 1742 static void 1743 dc_parse_21143_srom(struct dc_softc *sc) 1744 { 1745 struct dc_leaf_hdr *lhdr; 1746 struct dc_eblock_hdr *hdr; 1747 int have_mii, i, loff; 1748 char *ptr; 1749 1750 have_mii = 0; 1751 loff = sc->dc_srom[27]; 1752 lhdr = (struct dc_leaf_hdr *)&(sc->dc_srom[loff]); 1753 1754 ptr = (char *)lhdr; 1755 ptr += sizeof(struct dc_leaf_hdr) - 1; 1756 /* 1757 * Look if we got a MII media block. 1758 */ 1759 for (i = 0; i < lhdr->dc_mcnt; i++) { 1760 hdr = (struct dc_eblock_hdr *)ptr; 1761 if (hdr->dc_type == DC_EBLOCK_MII) 1762 have_mii++; 1763 1764 ptr += (hdr->dc_len & 0x7F); 1765 ptr++; 1766 } 1767 1768 /* 1769 * Do the same thing again. Only use SIA and SYM media 1770 * blocks if no MII media block is available. 1771 */ 1772 ptr = (char *)lhdr; 1773 ptr += sizeof(struct dc_leaf_hdr) - 1; 1774 for (i = 0; i < lhdr->dc_mcnt; i++) { 1775 hdr = (struct dc_eblock_hdr *)ptr; 1776 switch (hdr->dc_type) { 1777 case DC_EBLOCK_MII: 1778 dc_decode_leaf_mii(sc, (struct dc_eblock_mii *)hdr); 1779 break; 1780 case DC_EBLOCK_SIA: 1781 if (! have_mii) 1782 dc_decode_leaf_sia(sc, 1783 (struct dc_eblock_sia *)hdr); 1784 break; 1785 case DC_EBLOCK_SYM: 1786 if (! have_mii) 1787 dc_decode_leaf_sym(sc, 1788 (struct dc_eblock_sym *)hdr); 1789 break; 1790 default: 1791 /* Don't care. Yet. */ 1792 break; 1793 } 1794 ptr += (hdr->dc_len & 0x7F); 1795 ptr++; 1796 } 1797 } 1798 1799 static void 1800 dc_dma_map_addr(void *arg, bus_dma_segment_t *segs, int nseg, int error) 1801 { 1802 u_int32_t *paddr; 1803 1804 KASSERT(nseg == 1, 1805 ("%s: wrong number of segments (%d)", __func__, nseg)); 1806 paddr = arg; 1807 *paddr = segs->ds_addr; 1808 } 1809 1810 /* 1811 * Attach the interface. Allocate softc structures, do ifmedia 1812 * setup and ethernet/BPF attach. 1813 */ 1814 static int 1815 dc_attach(device_t dev) 1816 { 1817 int tmp = 0; 1818 uint32_t eaddr[(ETHER_ADDR_LEN+3)/4]; 1819 u_int32_t command; 1820 struct dc_softc *sc; 1821 struct ifnet *ifp; 1822 u_int32_t reg, revision; 1823 int error = 0, rid, mac_offset; 1824 int i; 1825 u_int8_t *mac; 1826 1827 sc = device_get_softc(dev); 1828 sc->dc_dev = dev; 1829 1830 mtx_init(&sc->dc_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 1831 MTX_DEF); 1832 1833 /* 1834 * Map control/status registers. 1835 */ 1836 pci_enable_busmaster(dev); 1837 1838 rid = DC_RID; 1839 sc->dc_res = bus_alloc_resource_any(dev, DC_RES, &rid, RF_ACTIVE); 1840 1841 if (sc->dc_res == NULL) { 1842 device_printf(dev, "couldn't map ports/memory\n"); 1843 error = ENXIO; 1844 goto fail; 1845 } 1846 1847 sc->dc_btag = rman_get_bustag(sc->dc_res); 1848 sc->dc_bhandle = rman_get_bushandle(sc->dc_res); 1849 1850 /* Allocate interrupt. */ 1851 rid = 0; 1852 sc->dc_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 1853 RF_SHAREABLE | RF_ACTIVE); 1854 1855 if (sc->dc_irq == NULL) { 1856 device_printf(dev, "couldn't map interrupt\n"); 1857 error = ENXIO; 1858 goto fail; 1859 } 1860 1861 /* Need this info to decide on a chip type. */ 1862 sc->dc_info = dc_devtype(dev); 1863 revision = pci_get_revid(dev); 1864 1865 /* Get the eeprom width, but PNIC and XIRCOM have diff eeprom */ 1866 if (sc->dc_info->dc_devid != 1867 DC_DEVID(DC_VENDORID_LO, DC_DEVICEID_82C168) && 1868 sc->dc_info->dc_devid != 1869 DC_DEVID(DC_VENDORID_XIRCOM, DC_DEVICEID_X3201)) 1870 dc_eeprom_width(sc); 1871 1872 switch (sc->dc_info->dc_devid) { 1873 case DC_DEVID(DC_VENDORID_DEC, DC_DEVICEID_21143): 1874 sc->dc_type = DC_TYPE_21143; 1875 sc->dc_flags |= DC_TX_POLL | DC_TX_USE_TX_INTR; 1876 sc->dc_flags |= DC_REDUCED_MII_POLL; 1877 /* Save EEPROM contents so we can parse them later. */ 1878 dc_read_srom(sc, sc->dc_romwidth); 1879 break; 1880 case DC_DEVID(DC_VENDORID_DAVICOM, DC_DEVICEID_DM9009): 1881 case DC_DEVID(DC_VENDORID_DAVICOM, DC_DEVICEID_DM9100): 1882 case DC_DEVID(DC_VENDORID_DAVICOM, DC_DEVICEID_DM9102): 1883 sc->dc_type = DC_TYPE_DM9102; 1884 sc->dc_flags |= DC_TX_COALESCE | DC_TX_INTR_ALWAYS; 1885 sc->dc_flags |= DC_REDUCED_MII_POLL | DC_TX_STORENFWD; 1886 sc->dc_flags |= DC_TX_ALIGN; 1887 sc->dc_pmode = DC_PMODE_MII; 1888 1889 /* Increase the latency timer value. */ 1890 pci_write_config(dev, PCIR_LATTIMER, 0x80, 1); 1891 break; 1892 case DC_DEVID(DC_VENDORID_ADMTEK, DC_DEVICEID_AL981): 1893 sc->dc_type = DC_TYPE_AL981; 1894 sc->dc_flags |= DC_TX_USE_TX_INTR; 1895 sc->dc_flags |= DC_TX_ADMTEK_WAR; 1896 sc->dc_pmode = DC_PMODE_MII; 1897 dc_read_srom(sc, sc->dc_romwidth); 1898 break; 1899 case DC_DEVID(DC_VENDORID_ADMTEK, DC_DEVICEID_AN985): 1900 case DC_DEVID(DC_VENDORID_ADMTEK, DC_DEVICEID_ADM9511): 1901 case DC_DEVID(DC_VENDORID_ADMTEK, DC_DEVICEID_ADM9513): 1902 case DC_DEVID(DC_VENDORID_DLINK, DC_DEVICEID_DRP32TXD): 1903 case DC_DEVID(DC_VENDORID_ADMTEK, DC_DEVICEID_FA511): 1904 case DC_DEVID(DC_VENDORID_ABOCOM, DC_DEVICEID_FE2500): 1905 case DC_DEVID(DC_VENDORID_ABOCOM, DC_DEVICEID_FE2500MX): 1906 case DC_DEVID(DC_VENDORID_ACCTON, DC_DEVICEID_EN2242): 1907 case DC_DEVID(DC_VENDORID_HAWKING, DC_DEVICEID_HAWKING_PN672TX): 1908 case DC_DEVID(DC_VENDORID_PLANEX, DC_DEVICEID_FNW3602T): 1909 case DC_DEVID(DC_VENDORID_3COM, DC_DEVICEID_3CSOHOB): 1910 case DC_DEVID(DC_VENDORID_MICROSOFT, DC_DEVICEID_MSMN120): 1911 case DC_DEVID(DC_VENDORID_MICROSOFT, DC_DEVICEID_MSMN130): 1912 case DC_DEVID(DC_VENDORID_LINKSYS, DC_DEVICEID_PCMPC200_AB08): 1913 case DC_DEVID(DC_VENDORID_LINKSYS, DC_DEVICEID_PCMPC200_AB09): 1914 sc->dc_type = DC_TYPE_AN985; 1915 sc->dc_flags |= DC_64BIT_HASH; 1916 sc->dc_flags |= DC_TX_USE_TX_INTR; 1917 sc->dc_flags |= DC_TX_ADMTEK_WAR; 1918 sc->dc_pmode = DC_PMODE_MII; 1919 /* Don't read SROM for - auto-loaded on reset */ 1920 break; 1921 case DC_DEVID(DC_VENDORID_MX, DC_DEVICEID_98713): 1922 case DC_DEVID(DC_VENDORID_CP, DC_DEVICEID_98713_CP): 1923 if (revision < DC_REVISION_98713A) { 1924 sc->dc_type = DC_TYPE_98713; 1925 } 1926 if (revision >= DC_REVISION_98713A) { 1927 sc->dc_type = DC_TYPE_98713A; 1928 sc->dc_flags |= DC_21143_NWAY; 1929 } 1930 sc->dc_flags |= DC_REDUCED_MII_POLL; 1931 sc->dc_flags |= DC_TX_POLL | DC_TX_USE_TX_INTR; 1932 break; 1933 case DC_DEVID(DC_VENDORID_MX, DC_DEVICEID_987x5): 1934 case DC_DEVID(DC_VENDORID_ACCTON, DC_DEVICEID_EN1217): 1935 /* 1936 * Macronix MX98715AEC-C/D/E parts have only a 1937 * 128-bit hash table. We need to deal with these 1938 * in the same manner as the PNIC II so that we 1939 * get the right number of bits out of the 1940 * CRC routine. 1941 */ 1942 if (revision >= DC_REVISION_98715AEC_C && 1943 revision < DC_REVISION_98725) 1944 sc->dc_flags |= DC_128BIT_HASH; 1945 sc->dc_type = DC_TYPE_987x5; 1946 sc->dc_flags |= DC_TX_POLL | DC_TX_USE_TX_INTR; 1947 sc->dc_flags |= DC_REDUCED_MII_POLL | DC_21143_NWAY; 1948 break; 1949 case DC_DEVID(DC_VENDORID_MX, DC_DEVICEID_98727): 1950 sc->dc_type = DC_TYPE_987x5; 1951 sc->dc_flags |= DC_TX_POLL | DC_TX_USE_TX_INTR; 1952 sc->dc_flags |= DC_REDUCED_MII_POLL | DC_21143_NWAY; 1953 break; 1954 case DC_DEVID(DC_VENDORID_LO, DC_DEVICEID_82C115): 1955 sc->dc_type = DC_TYPE_PNICII; 1956 sc->dc_flags |= DC_TX_POLL | DC_TX_USE_TX_INTR | DC_128BIT_HASH; 1957 sc->dc_flags |= DC_REDUCED_MII_POLL | DC_21143_NWAY; 1958 break; 1959 case DC_DEVID(DC_VENDORID_LO, DC_DEVICEID_82C168): 1960 sc->dc_type = DC_TYPE_PNIC; 1961 sc->dc_flags |= DC_TX_STORENFWD | DC_TX_INTR_ALWAYS; 1962 sc->dc_flags |= DC_PNIC_RX_BUG_WAR; 1963 sc->dc_pnic_rx_buf = malloc(DC_RXLEN * 5, M_DEVBUF, M_NOWAIT); 1964 if (revision < DC_REVISION_82C169) 1965 sc->dc_pmode = DC_PMODE_SYM; 1966 break; 1967 case DC_DEVID(DC_VENDORID_ASIX, DC_DEVICEID_AX88140A): 1968 sc->dc_type = DC_TYPE_ASIX; 1969 sc->dc_flags |= DC_TX_USE_TX_INTR | DC_TX_INTR_FIRSTFRAG; 1970 sc->dc_flags |= DC_REDUCED_MII_POLL; 1971 sc->dc_pmode = DC_PMODE_MII; 1972 break; 1973 case DC_DEVID(DC_VENDORID_XIRCOM, DC_DEVICEID_X3201): 1974 sc->dc_type = DC_TYPE_XIRCOM; 1975 sc->dc_flags |= DC_TX_INTR_ALWAYS | DC_TX_COALESCE | 1976 DC_TX_ALIGN; 1977 /* 1978 * We don't actually need to coalesce, but we're doing 1979 * it to obtain a double word aligned buffer. 1980 * The DC_TX_COALESCE flag is required. 1981 */ 1982 sc->dc_pmode = DC_PMODE_MII; 1983 break; 1984 case DC_DEVID(DC_VENDORID_CONEXANT, DC_DEVICEID_RS7112): 1985 sc->dc_type = DC_TYPE_CONEXANT; 1986 sc->dc_flags |= DC_TX_INTR_ALWAYS; 1987 sc->dc_flags |= DC_REDUCED_MII_POLL; 1988 sc->dc_pmode = DC_PMODE_MII; 1989 dc_read_srom(sc, sc->dc_romwidth); 1990 break; 1991 default: 1992 device_printf(dev, "unknown device: %x\n", 1993 sc->dc_info->dc_devid); 1994 break; 1995 } 1996 1997 /* Save the cache line size. */ 1998 if (DC_IS_DAVICOM(sc)) 1999 sc->dc_cachesize = 0; 2000 else 2001 sc->dc_cachesize = pci_get_cachelnsz(dev); 2002 2003 /* Reset the adapter. */ 2004 dc_reset(sc); 2005 2006 /* Take 21143 out of snooze mode */ 2007 if (DC_IS_INTEL(sc) || DC_IS_XIRCOM(sc)) { 2008 command = pci_read_config(dev, DC_PCI_CFDD, 4); 2009 command &= ~(DC_CFDD_SNOOZE_MODE | DC_CFDD_SLEEP_MODE); 2010 pci_write_config(dev, DC_PCI_CFDD, command, 4); 2011 } 2012 2013 /* 2014 * Try to learn something about the supported media. 2015 * We know that ASIX and ADMtek and Davicom devices 2016 * will *always* be using MII media, so that's a no-brainer. 2017 * The tricky ones are the Macronix/PNIC II and the 2018 * Intel 21143. 2019 */ 2020 if (DC_IS_INTEL(sc)) 2021 dc_parse_21143_srom(sc); 2022 else if (DC_IS_MACRONIX(sc) || DC_IS_PNICII(sc)) { 2023 if (sc->dc_type == DC_TYPE_98713) 2024 sc->dc_pmode = DC_PMODE_MII; 2025 else 2026 sc->dc_pmode = DC_PMODE_SYM; 2027 } else if (!sc->dc_pmode) 2028 sc->dc_pmode = DC_PMODE_MII; 2029 2030 /* 2031 * Get station address from the EEPROM. 2032 */ 2033 switch(sc->dc_type) { 2034 case DC_TYPE_98713: 2035 case DC_TYPE_98713A: 2036 case DC_TYPE_987x5: 2037 case DC_TYPE_PNICII: 2038 dc_read_eeprom(sc, (caddr_t)&mac_offset, 2039 (DC_EE_NODEADDR_OFFSET / 2), 1, 0); 2040 dc_read_eeprom(sc, (caddr_t)&eaddr, (mac_offset / 2), 3, 0); 2041 break; 2042 case DC_TYPE_PNIC: 2043 dc_read_eeprom(sc, (caddr_t)&eaddr, 0, 3, 1); 2044 break; 2045 case DC_TYPE_DM9102: 2046 dc_read_eeprom(sc, (caddr_t)&eaddr, DC_EE_NODEADDR, 3, 0); 2047 #ifdef __sparc64__ 2048 /* 2049 * If this is an onboard dc(4) the station address read from 2050 * the EEPROM is all zero and we have to get it from the FCode. 2051 */ 2052 if (eaddr[0] == 0 && (eaddr[1] & ~0xffff) == 0) 2053 OF_getetheraddr(dev, (caddr_t)&eaddr); 2054 #endif 2055 break; 2056 case DC_TYPE_21143: 2057 case DC_TYPE_ASIX: 2058 dc_read_eeprom(sc, (caddr_t)&eaddr, DC_EE_NODEADDR, 3, 0); 2059 break; 2060 case DC_TYPE_AL981: 2061 case DC_TYPE_AN985: 2062 reg = CSR_READ_4(sc, DC_AL_PAR0); 2063 mac = (uint8_t *)&eaddr[0]; 2064 mac[0] = (reg >> 0) & 0xff; 2065 mac[1] = (reg >> 8) & 0xff; 2066 mac[2] = (reg >> 16) & 0xff; 2067 mac[3] = (reg >> 24) & 0xff; 2068 reg = CSR_READ_4(sc, DC_AL_PAR1); 2069 mac[4] = (reg >> 0) & 0xff; 2070 mac[5] = (reg >> 8) & 0xff; 2071 break; 2072 case DC_TYPE_CONEXANT: 2073 bcopy(sc->dc_srom + DC_CONEXANT_EE_NODEADDR, &eaddr, 2074 ETHER_ADDR_LEN); 2075 break; 2076 case DC_TYPE_XIRCOM: 2077 /* The MAC comes from the CIS. */ 2078 mac = pci_get_ether(dev); 2079 if (!mac) { 2080 device_printf(dev, "No station address in CIS!\n"); 2081 error = ENXIO; 2082 goto fail; 2083 } 2084 bcopy(mac, eaddr, ETHER_ADDR_LEN); 2085 break; 2086 default: 2087 dc_read_eeprom(sc, (caddr_t)&eaddr, DC_EE_NODEADDR, 3, 0); 2088 break; 2089 } 2090 2091 /* Allocate a busdma tag and DMA safe memory for TX/RX descriptors. */ 2092 error = bus_dma_tag_create(bus_get_dma_tag(dev), PAGE_SIZE, 0, 2093 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL, 2094 sizeof(struct dc_list_data), 1, sizeof(struct dc_list_data), 2095 0, NULL, NULL, &sc->dc_ltag); 2096 if (error) { 2097 device_printf(dev, "failed to allocate busdma tag\n"); 2098 error = ENXIO; 2099 goto fail; 2100 } 2101 error = bus_dmamem_alloc(sc->dc_ltag, (void **)&sc->dc_ldata, 2102 BUS_DMA_NOWAIT | BUS_DMA_ZERO, &sc->dc_lmap); 2103 if (error) { 2104 device_printf(dev, "failed to allocate DMA safe memory\n"); 2105 error = ENXIO; 2106 goto fail; 2107 } 2108 error = bus_dmamap_load(sc->dc_ltag, sc->dc_lmap, sc->dc_ldata, 2109 sizeof(struct dc_list_data), dc_dma_map_addr, &sc->dc_laddr, 2110 BUS_DMA_NOWAIT); 2111 if (error) { 2112 device_printf(dev, "cannot get address of the descriptors\n"); 2113 error = ENXIO; 2114 goto fail; 2115 } 2116 2117 /* 2118 * Allocate a busdma tag and DMA safe memory for the multicast 2119 * setup frame. 2120 */ 2121 error = bus_dma_tag_create(bus_get_dma_tag(dev), PAGE_SIZE, 0, 2122 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL, 2123 DC_SFRAME_LEN + DC_MIN_FRAMELEN, 1, DC_SFRAME_LEN + DC_MIN_FRAMELEN, 2124 0, NULL, NULL, &sc->dc_stag); 2125 if (error) { 2126 device_printf(dev, "failed to allocate busdma tag\n"); 2127 error = ENXIO; 2128 goto fail; 2129 } 2130 error = bus_dmamem_alloc(sc->dc_stag, (void **)&sc->dc_cdata.dc_sbuf, 2131 BUS_DMA_NOWAIT, &sc->dc_smap); 2132 if (error) { 2133 device_printf(dev, "failed to allocate DMA safe memory\n"); 2134 error = ENXIO; 2135 goto fail; 2136 } 2137 error = bus_dmamap_load(sc->dc_stag, sc->dc_smap, sc->dc_cdata.dc_sbuf, 2138 DC_SFRAME_LEN, dc_dma_map_addr, &sc->dc_saddr, BUS_DMA_NOWAIT); 2139 if (error) { 2140 device_printf(dev, "cannot get address of the descriptors\n"); 2141 error = ENXIO; 2142 goto fail; 2143 } 2144 2145 /* Allocate a busdma tag for mbufs. */ 2146 error = bus_dma_tag_create(bus_get_dma_tag(dev), 1, 0, 2147 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL, 2148 MCLBYTES * DC_MAXFRAGS, DC_MAXFRAGS, MCLBYTES, 2149 0, NULL, NULL, &sc->dc_mtag); 2150 if (error) { 2151 device_printf(dev, "failed to allocate busdma tag\n"); 2152 error = ENXIO; 2153 goto fail; 2154 } 2155 2156 /* Create the TX/RX busdma maps. */ 2157 for (i = 0; i < DC_TX_LIST_CNT; i++) { 2158 error = bus_dmamap_create(sc->dc_mtag, 0, 2159 &sc->dc_cdata.dc_tx_map[i]); 2160 if (error) { 2161 device_printf(dev, "failed to init TX ring\n"); 2162 error = ENXIO; 2163 goto fail; 2164 } 2165 } 2166 for (i = 0; i < DC_RX_LIST_CNT; i++) { 2167 error = bus_dmamap_create(sc->dc_mtag, 0, 2168 &sc->dc_cdata.dc_rx_map[i]); 2169 if (error) { 2170 device_printf(dev, "failed to init RX ring\n"); 2171 error = ENXIO; 2172 goto fail; 2173 } 2174 } 2175 error = bus_dmamap_create(sc->dc_mtag, 0, &sc->dc_sparemap); 2176 if (error) { 2177 device_printf(dev, "failed to init RX ring\n"); 2178 error = ENXIO; 2179 goto fail; 2180 } 2181 2182 ifp = sc->dc_ifp = if_alloc(IFT_ETHER); 2183 if (ifp == NULL) { 2184 device_printf(dev, "can not if_alloc()\n"); 2185 error = ENOSPC; 2186 goto fail; 2187 } 2188 ifp->if_softc = sc; 2189 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 2190 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 2191 ifp->if_ioctl = dc_ioctl; 2192 ifp->if_start = dc_start; 2193 ifp->if_init = dc_init; 2194 IFQ_SET_MAXLEN(&ifp->if_snd, DC_TX_LIST_CNT - 1); 2195 ifp->if_snd.ifq_drv_maxlen = DC_TX_LIST_CNT - 1; 2196 IFQ_SET_READY(&ifp->if_snd); 2197 2198 /* 2199 * Do MII setup. If this is a 21143, check for a PHY on the 2200 * MII bus after applying any necessary fixups to twiddle the 2201 * GPIO bits. If we don't end up finding a PHY, restore the 2202 * old selection (SIA only or SIA/SYM) and attach the dcphy 2203 * driver instead. 2204 */ 2205 if (DC_IS_INTEL(sc)) { 2206 dc_apply_fixup(sc, IFM_AUTO); 2207 tmp = sc->dc_pmode; 2208 sc->dc_pmode = DC_PMODE_MII; 2209 } 2210 2211 /* 2212 * Setup General Purpose port mode and data so the tulip can talk 2213 * to the MII. This needs to be done before mii_phy_probe so that 2214 * we can actually see them. 2215 */ 2216 if (DC_IS_XIRCOM(sc)) { 2217 CSR_WRITE_4(sc, DC_SIAGP, DC_SIAGP_WRITE_EN | DC_SIAGP_INT1_EN | 2218 DC_SIAGP_MD_GP2_OUTPUT | DC_SIAGP_MD_GP0_OUTPUT); 2219 DELAY(10); 2220 CSR_WRITE_4(sc, DC_SIAGP, DC_SIAGP_INT1_EN | 2221 DC_SIAGP_MD_GP2_OUTPUT | DC_SIAGP_MD_GP0_OUTPUT); 2222 DELAY(10); 2223 } 2224 2225 error = mii_phy_probe(dev, &sc->dc_miibus, 2226 dc_ifmedia_upd, dc_ifmedia_sts); 2227 2228 if (error && DC_IS_INTEL(sc)) { 2229 sc->dc_pmode = tmp; 2230 if (sc->dc_pmode != DC_PMODE_SIA) 2231 sc->dc_pmode = DC_PMODE_SYM; 2232 sc->dc_flags |= DC_21143_NWAY; 2233 mii_phy_probe(dev, &sc->dc_miibus, 2234 dc_ifmedia_upd, dc_ifmedia_sts); 2235 /* 2236 * For non-MII cards, we need to have the 21143 2237 * drive the LEDs. Except there are some systems 2238 * like the NEC VersaPro NoteBook PC which have no 2239 * LEDs, and twiddling these bits has adverse effects 2240 * on them. (I.e. you suddenly can't get a link.) 2241 */ 2242 if (!(pci_get_subvendor(dev) == 0x1033 && 2243 pci_get_subdevice(dev) == 0x8028)) 2244 sc->dc_flags |= DC_TULIP_LEDS; 2245 error = 0; 2246 } 2247 2248 if (error) { 2249 device_printf(dev, "MII without any PHY!\n"); 2250 goto fail; 2251 } 2252 2253 if (DC_IS_ADMTEK(sc)) { 2254 /* 2255 * Set automatic TX underrun recovery for the ADMtek chips 2256 */ 2257 DC_SETBIT(sc, DC_AL_CR, DC_AL_CR_ATUR); 2258 } 2259 2260 /* 2261 * Tell the upper layer(s) we support long frames. 2262 */ 2263 ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header); 2264 ifp->if_capabilities |= IFCAP_VLAN_MTU; 2265 ifp->if_capenable = ifp->if_capabilities; 2266 #ifdef DEVICE_POLLING 2267 ifp->if_capabilities |= IFCAP_POLLING; 2268 #endif 2269 2270 callout_init_mtx(&sc->dc_stat_ch, &sc->dc_mtx, 0); 2271 callout_init_mtx(&sc->dc_wdog_ch, &sc->dc_mtx, 0); 2272 2273 /* 2274 * Call MI attach routine. 2275 */ 2276 ether_ifattach(ifp, (caddr_t)eaddr); 2277 2278 /* Hook interrupt last to avoid having to lock softc */ 2279 error = bus_setup_intr(dev, sc->dc_irq, INTR_TYPE_NET | INTR_MPSAFE, 2280 NULL, dc_intr, sc, &sc->dc_intrhand); 2281 2282 if (error) { 2283 device_printf(dev, "couldn't set up irq\n"); 2284 ether_ifdetach(ifp); 2285 goto fail; 2286 } 2287 2288 fail: 2289 if (error) 2290 dc_detach(dev); 2291 return (error); 2292 } 2293 2294 /* 2295 * Shutdown hardware and free up resources. This can be called any 2296 * time after the mutex has been initialized. It is called in both 2297 * the error case in attach and the normal detach case so it needs 2298 * to be careful about only freeing resources that have actually been 2299 * allocated. 2300 */ 2301 static int 2302 dc_detach(device_t dev) 2303 { 2304 struct dc_softc *sc; 2305 struct ifnet *ifp; 2306 struct dc_mediainfo *m; 2307 int i; 2308 2309 sc = device_get_softc(dev); 2310 KASSERT(mtx_initialized(&sc->dc_mtx), ("dc mutex not initialized")); 2311 2312 ifp = sc->dc_ifp; 2313 2314 #ifdef DEVICE_POLLING 2315 if (ifp->if_capenable & IFCAP_POLLING) 2316 ether_poll_deregister(ifp); 2317 #endif 2318 2319 /* These should only be active if attach succeeded */ 2320 if (device_is_attached(dev)) { 2321 DC_LOCK(sc); 2322 dc_stop(sc); 2323 DC_UNLOCK(sc); 2324 callout_drain(&sc->dc_stat_ch); 2325 callout_drain(&sc->dc_wdog_ch); 2326 ether_ifdetach(ifp); 2327 } 2328 if (sc->dc_miibus) 2329 device_delete_child(dev, sc->dc_miibus); 2330 bus_generic_detach(dev); 2331 2332 if (sc->dc_intrhand) 2333 bus_teardown_intr(dev, sc->dc_irq, sc->dc_intrhand); 2334 if (sc->dc_irq) 2335 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->dc_irq); 2336 if (sc->dc_res) 2337 bus_release_resource(dev, DC_RES, DC_RID, sc->dc_res); 2338 2339 if (ifp) 2340 if_free(ifp); 2341 2342 if (sc->dc_cdata.dc_sbuf != NULL) 2343 bus_dmamem_free(sc->dc_stag, sc->dc_cdata.dc_sbuf, sc->dc_smap); 2344 if (sc->dc_ldata != NULL) 2345 bus_dmamem_free(sc->dc_ltag, sc->dc_ldata, sc->dc_lmap); 2346 if (sc->dc_mtag) { 2347 for (i = 0; i < DC_TX_LIST_CNT; i++) 2348 if (sc->dc_cdata.dc_tx_map[i] != NULL) 2349 bus_dmamap_destroy(sc->dc_mtag, 2350 sc->dc_cdata.dc_tx_map[i]); 2351 for (i = 0; i < DC_RX_LIST_CNT; i++) 2352 if (sc->dc_cdata.dc_rx_map[i] != NULL) 2353 bus_dmamap_destroy(sc->dc_mtag, 2354 sc->dc_cdata.dc_rx_map[i]); 2355 bus_dmamap_destroy(sc->dc_mtag, sc->dc_sparemap); 2356 } 2357 if (sc->dc_stag) 2358 bus_dma_tag_destroy(sc->dc_stag); 2359 if (sc->dc_mtag) 2360 bus_dma_tag_destroy(sc->dc_mtag); 2361 if (sc->dc_ltag) 2362 bus_dma_tag_destroy(sc->dc_ltag); 2363 2364 free(sc->dc_pnic_rx_buf, M_DEVBUF); 2365 2366 while (sc->dc_mi != NULL) { 2367 m = sc->dc_mi->dc_next; 2368 free(sc->dc_mi, M_DEVBUF); 2369 sc->dc_mi = m; 2370 } 2371 free(sc->dc_srom, M_DEVBUF); 2372 2373 mtx_destroy(&sc->dc_mtx); 2374 2375 return (0); 2376 } 2377 2378 /* 2379 * Initialize the transmit descriptors. 2380 */ 2381 static int 2382 dc_list_tx_init(struct dc_softc *sc) 2383 { 2384 struct dc_chain_data *cd; 2385 struct dc_list_data *ld; 2386 int i, nexti; 2387 2388 cd = &sc->dc_cdata; 2389 ld = sc->dc_ldata; 2390 for (i = 0; i < DC_TX_LIST_CNT; i++) { 2391 if (i == DC_TX_LIST_CNT - 1) 2392 nexti = 0; 2393 else 2394 nexti = i + 1; 2395 ld->dc_tx_list[i].dc_next = htole32(DC_TXDESC(sc, nexti)); 2396 cd->dc_tx_chain[i] = NULL; 2397 ld->dc_tx_list[i].dc_data = 0; 2398 ld->dc_tx_list[i].dc_ctl = 0; 2399 } 2400 2401 cd->dc_tx_prod = cd->dc_tx_cons = cd->dc_tx_cnt = 0; 2402 bus_dmamap_sync(sc->dc_ltag, sc->dc_lmap, 2403 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2404 return (0); 2405 } 2406 2407 2408 /* 2409 * Initialize the RX descriptors and allocate mbufs for them. Note that 2410 * we arrange the descriptors in a closed ring, so that the last descriptor 2411 * points back to the first. 2412 */ 2413 static int 2414 dc_list_rx_init(struct dc_softc *sc) 2415 { 2416 struct dc_chain_data *cd; 2417 struct dc_list_data *ld; 2418 int i, nexti; 2419 2420 cd = &sc->dc_cdata; 2421 ld = sc->dc_ldata; 2422 2423 for (i = 0; i < DC_RX_LIST_CNT; i++) { 2424 if (dc_newbuf(sc, i, 1) != 0) 2425 return (ENOBUFS); 2426 if (i == DC_RX_LIST_CNT - 1) 2427 nexti = 0; 2428 else 2429 nexti = i + 1; 2430 ld->dc_rx_list[i].dc_next = htole32(DC_RXDESC(sc, nexti)); 2431 } 2432 2433 cd->dc_rx_prod = 0; 2434 bus_dmamap_sync(sc->dc_ltag, sc->dc_lmap, 2435 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2436 return (0); 2437 } 2438 2439 /* 2440 * Initialize an RX descriptor and attach an MBUF cluster. 2441 */ 2442 static int 2443 dc_newbuf(struct dc_softc *sc, int i, int alloc) 2444 { 2445 struct mbuf *m_new; 2446 bus_dmamap_t tmp; 2447 bus_dma_segment_t segs[1]; 2448 int error, nseg; 2449 2450 if (alloc) { 2451 m_new = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR); 2452 if (m_new == NULL) 2453 return (ENOBUFS); 2454 } else { 2455 m_new = sc->dc_cdata.dc_rx_chain[i]; 2456 m_new->m_data = m_new->m_ext.ext_buf; 2457 } 2458 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 2459 m_adj(m_new, sizeof(u_int64_t)); 2460 2461 /* 2462 * If this is a PNIC chip, zero the buffer. This is part 2463 * of the workaround for the receive bug in the 82c168 and 2464 * 82c169 chips. 2465 */ 2466 if (sc->dc_flags & DC_PNIC_RX_BUG_WAR) 2467 bzero(mtod(m_new, char *), m_new->m_len); 2468 2469 /* No need to remap the mbuf if we're reusing it. */ 2470 if (alloc) { 2471 error = bus_dmamap_load_mbuf_sg(sc->dc_mtag, sc->dc_sparemap, 2472 m_new, segs, &nseg, 0); 2473 if (error) { 2474 m_freem(m_new); 2475 return (error); 2476 } 2477 KASSERT(nseg == 1, 2478 ("%s: wrong number of segments (%d)", __func__, nseg)); 2479 sc->dc_ldata->dc_rx_list[i].dc_data = htole32(segs->ds_addr); 2480 bus_dmamap_unload(sc->dc_mtag, sc->dc_cdata.dc_rx_map[i]); 2481 tmp = sc->dc_cdata.dc_rx_map[i]; 2482 sc->dc_cdata.dc_rx_map[i] = sc->dc_sparemap; 2483 sc->dc_sparemap = tmp; 2484 sc->dc_cdata.dc_rx_chain[i] = m_new; 2485 } 2486 2487 sc->dc_ldata->dc_rx_list[i].dc_ctl = htole32(DC_RXCTL_RLINK | DC_RXLEN); 2488 sc->dc_ldata->dc_rx_list[i].dc_status = htole32(DC_RXSTAT_OWN); 2489 bus_dmamap_sync(sc->dc_mtag, sc->dc_cdata.dc_rx_map[i], 2490 BUS_DMASYNC_PREREAD); 2491 bus_dmamap_sync(sc->dc_ltag, sc->dc_lmap, 2492 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2493 return (0); 2494 } 2495 2496 /* 2497 * Grrrrr. 2498 * The PNIC chip has a terrible bug in it that manifests itself during 2499 * periods of heavy activity. The exact mode of failure if difficult to 2500 * pinpoint: sometimes it only happens in promiscuous mode, sometimes it 2501 * will happen on slow machines. The bug is that sometimes instead of 2502 * uploading one complete frame during reception, it uploads what looks 2503 * like the entire contents of its FIFO memory. The frame we want is at 2504 * the end of the whole mess, but we never know exactly how much data has 2505 * been uploaded, so salvaging the frame is hard. 2506 * 2507 * There is only one way to do it reliably, and it's disgusting. 2508 * Here's what we know: 2509 * 2510 * - We know there will always be somewhere between one and three extra 2511 * descriptors uploaded. 2512 * 2513 * - We know the desired received frame will always be at the end of the 2514 * total data upload. 2515 * 2516 * - We know the size of the desired received frame because it will be 2517 * provided in the length field of the status word in the last descriptor. 2518 * 2519 * Here's what we do: 2520 * 2521 * - When we allocate buffers for the receive ring, we bzero() them. 2522 * This means that we know that the buffer contents should be all 2523 * zeros, except for data uploaded by the chip. 2524 * 2525 * - We also force the PNIC chip to upload frames that include the 2526 * ethernet CRC at the end. 2527 * 2528 * - We gather all of the bogus frame data into a single buffer. 2529 * 2530 * - We then position a pointer at the end of this buffer and scan 2531 * backwards until we encounter the first non-zero byte of data. 2532 * This is the end of the received frame. We know we will encounter 2533 * some data at the end of the frame because the CRC will always be 2534 * there, so even if the sender transmits a packet of all zeros, 2535 * we won't be fooled. 2536 * 2537 * - We know the size of the actual received frame, so we subtract 2538 * that value from the current pointer location. This brings us 2539 * to the start of the actual received packet. 2540 * 2541 * - We copy this into an mbuf and pass it on, along with the actual 2542 * frame length. 2543 * 2544 * The performance hit is tremendous, but it beats dropping frames all 2545 * the time. 2546 */ 2547 2548 #define DC_WHOLEFRAME (DC_RXSTAT_FIRSTFRAG | DC_RXSTAT_LASTFRAG) 2549 static void 2550 dc_pnic_rx_bug_war(struct dc_softc *sc, int idx) 2551 { 2552 struct dc_desc *cur_rx; 2553 struct dc_desc *c = NULL; 2554 struct mbuf *m = NULL; 2555 unsigned char *ptr; 2556 int i, total_len; 2557 u_int32_t rxstat = 0; 2558 2559 i = sc->dc_pnic_rx_bug_save; 2560 cur_rx = &sc->dc_ldata->dc_rx_list[idx]; 2561 ptr = sc->dc_pnic_rx_buf; 2562 bzero(ptr, DC_RXLEN * 5); 2563 2564 /* Copy all the bytes from the bogus buffers. */ 2565 while (1) { 2566 c = &sc->dc_ldata->dc_rx_list[i]; 2567 rxstat = le32toh(c->dc_status); 2568 m = sc->dc_cdata.dc_rx_chain[i]; 2569 bcopy(mtod(m, char *), ptr, DC_RXLEN); 2570 ptr += DC_RXLEN; 2571 /* If this is the last buffer, break out. */ 2572 if (i == idx || rxstat & DC_RXSTAT_LASTFRAG) 2573 break; 2574 dc_newbuf(sc, i, 0); 2575 DC_INC(i, DC_RX_LIST_CNT); 2576 } 2577 2578 /* Find the length of the actual receive frame. */ 2579 total_len = DC_RXBYTES(rxstat); 2580 2581 /* Scan backwards until we hit a non-zero byte. */ 2582 while (*ptr == 0x00) 2583 ptr--; 2584 2585 /* Round off. */ 2586 if ((uintptr_t)(ptr) & 0x3) 2587 ptr -= 1; 2588 2589 /* Now find the start of the frame. */ 2590 ptr -= total_len; 2591 if (ptr < sc->dc_pnic_rx_buf) 2592 ptr = sc->dc_pnic_rx_buf; 2593 2594 /* 2595 * Now copy the salvaged frame to the last mbuf and fake up 2596 * the status word to make it look like a successful 2597 * frame reception. 2598 */ 2599 dc_newbuf(sc, i, 0); 2600 bcopy(ptr, mtod(m, char *), total_len); 2601 cur_rx->dc_status = htole32(rxstat | DC_RXSTAT_FIRSTFRAG); 2602 } 2603 2604 /* 2605 * This routine searches the RX ring for dirty descriptors in the 2606 * event that the rxeof routine falls out of sync with the chip's 2607 * current descriptor pointer. This may happen sometimes as a result 2608 * of a "no RX buffer available" condition that happens when the chip 2609 * consumes all of the RX buffers before the driver has a chance to 2610 * process the RX ring. This routine may need to be called more than 2611 * once to bring the driver back in sync with the chip, however we 2612 * should still be getting RX DONE interrupts to drive the search 2613 * for new packets in the RX ring, so we should catch up eventually. 2614 */ 2615 static int 2616 dc_rx_resync(struct dc_softc *sc) 2617 { 2618 struct dc_desc *cur_rx; 2619 int i, pos; 2620 2621 pos = sc->dc_cdata.dc_rx_prod; 2622 2623 for (i = 0; i < DC_RX_LIST_CNT; i++) { 2624 cur_rx = &sc->dc_ldata->dc_rx_list[pos]; 2625 if (!(le32toh(cur_rx->dc_status) & DC_RXSTAT_OWN)) 2626 break; 2627 DC_INC(pos, DC_RX_LIST_CNT); 2628 } 2629 2630 /* If the ring really is empty, then just return. */ 2631 if (i == DC_RX_LIST_CNT) 2632 return (0); 2633 2634 /* We've fallen behing the chip: catch it. */ 2635 sc->dc_cdata.dc_rx_prod = pos; 2636 2637 return (EAGAIN); 2638 } 2639 2640 /* 2641 * A frame has been uploaded: pass the resulting mbuf chain up to 2642 * the higher level protocols. 2643 */ 2644 static void 2645 dc_rxeof(struct dc_softc *sc) 2646 { 2647 struct mbuf *m, *m0; 2648 struct ifnet *ifp; 2649 struct dc_desc *cur_rx; 2650 int i, total_len = 0; 2651 u_int32_t rxstat; 2652 2653 DC_LOCK_ASSERT(sc); 2654 2655 ifp = sc->dc_ifp; 2656 i = sc->dc_cdata.dc_rx_prod; 2657 2658 bus_dmamap_sync(sc->dc_ltag, sc->dc_lmap, BUS_DMASYNC_POSTREAD); 2659 while (!(le32toh(sc->dc_ldata->dc_rx_list[i].dc_status) & 2660 DC_RXSTAT_OWN)) { 2661 #ifdef DEVICE_POLLING 2662 if (ifp->if_capenable & IFCAP_POLLING) { 2663 if (sc->rxcycles <= 0) 2664 break; 2665 sc->rxcycles--; 2666 } 2667 #endif 2668 cur_rx = &sc->dc_ldata->dc_rx_list[i]; 2669 rxstat = le32toh(cur_rx->dc_status); 2670 m = sc->dc_cdata.dc_rx_chain[i]; 2671 bus_dmamap_sync(sc->dc_mtag, sc->dc_cdata.dc_rx_map[i], 2672 BUS_DMASYNC_POSTREAD); 2673 total_len = DC_RXBYTES(rxstat); 2674 2675 if (sc->dc_flags & DC_PNIC_RX_BUG_WAR) { 2676 if ((rxstat & DC_WHOLEFRAME) != DC_WHOLEFRAME) { 2677 if (rxstat & DC_RXSTAT_FIRSTFRAG) 2678 sc->dc_pnic_rx_bug_save = i; 2679 if ((rxstat & DC_RXSTAT_LASTFRAG) == 0) { 2680 DC_INC(i, DC_RX_LIST_CNT); 2681 continue; 2682 } 2683 dc_pnic_rx_bug_war(sc, i); 2684 rxstat = le32toh(cur_rx->dc_status); 2685 total_len = DC_RXBYTES(rxstat); 2686 } 2687 } 2688 2689 /* 2690 * If an error occurs, update stats, clear the 2691 * status word and leave the mbuf cluster in place: 2692 * it should simply get re-used next time this descriptor 2693 * comes up in the ring. However, don't report long 2694 * frames as errors since they could be vlans. 2695 */ 2696 if ((rxstat & DC_RXSTAT_RXERR)) { 2697 if (!(rxstat & DC_RXSTAT_GIANT) || 2698 (rxstat & (DC_RXSTAT_CRCERR | DC_RXSTAT_DRIBBLE | 2699 DC_RXSTAT_MIIERE | DC_RXSTAT_COLLSEEN | 2700 DC_RXSTAT_RUNT | DC_RXSTAT_DE))) { 2701 ifp->if_ierrors++; 2702 if (rxstat & DC_RXSTAT_COLLSEEN) 2703 ifp->if_collisions++; 2704 dc_newbuf(sc, i, 0); 2705 if (rxstat & DC_RXSTAT_CRCERR) { 2706 DC_INC(i, DC_RX_LIST_CNT); 2707 continue; 2708 } else { 2709 dc_init_locked(sc); 2710 return; 2711 } 2712 } 2713 } 2714 2715 /* No errors; receive the packet. */ 2716 total_len -= ETHER_CRC_LEN; 2717 #ifdef __NO_STRICT_ALIGNMENT 2718 /* 2719 * On architectures without alignment problems we try to 2720 * allocate a new buffer for the receive ring, and pass up 2721 * the one where the packet is already, saving the expensive 2722 * copy done in m_devget(). 2723 * If we are on an architecture with alignment problems, or 2724 * if the allocation fails, then use m_devget and leave the 2725 * existing buffer in the receive ring. 2726 */ 2727 if (dc_newbuf(sc, i, 1) == 0) { 2728 m->m_pkthdr.rcvif = ifp; 2729 m->m_pkthdr.len = m->m_len = total_len; 2730 DC_INC(i, DC_RX_LIST_CNT); 2731 } else 2732 #endif 2733 { 2734 m0 = m_devget(mtod(m, char *), total_len, 2735 ETHER_ALIGN, ifp, NULL); 2736 dc_newbuf(sc, i, 0); 2737 DC_INC(i, DC_RX_LIST_CNT); 2738 if (m0 == NULL) { 2739 ifp->if_ierrors++; 2740 continue; 2741 } 2742 m = m0; 2743 } 2744 2745 ifp->if_ipackets++; 2746 DC_UNLOCK(sc); 2747 (*ifp->if_input)(ifp, m); 2748 DC_LOCK(sc); 2749 } 2750 2751 sc->dc_cdata.dc_rx_prod = i; 2752 } 2753 2754 /* 2755 * A frame was downloaded to the chip. It's safe for us to clean up 2756 * the list buffers. 2757 */ 2758 static void 2759 dc_txeof(struct dc_softc *sc) 2760 { 2761 struct dc_desc *cur_tx = NULL; 2762 struct ifnet *ifp; 2763 int idx; 2764 u_int32_t ctl, txstat; 2765 2766 ifp = sc->dc_ifp; 2767 2768 /* 2769 * Go through our tx list and free mbufs for those 2770 * frames that have been transmitted. 2771 */ 2772 bus_dmamap_sync(sc->dc_ltag, sc->dc_lmap, BUS_DMASYNC_POSTREAD); 2773 idx = sc->dc_cdata.dc_tx_cons; 2774 while (idx != sc->dc_cdata.dc_tx_prod) { 2775 2776 cur_tx = &sc->dc_ldata->dc_tx_list[idx]; 2777 txstat = le32toh(cur_tx->dc_status); 2778 ctl = le32toh(cur_tx->dc_ctl); 2779 2780 if (txstat & DC_TXSTAT_OWN) 2781 break; 2782 2783 if (!(ctl & DC_TXCTL_LASTFRAG) || ctl & DC_TXCTL_SETUP) { 2784 if (ctl & DC_TXCTL_SETUP) { 2785 /* 2786 * Yes, the PNIC is so brain damaged 2787 * that it will sometimes generate a TX 2788 * underrun error while DMAing the RX 2789 * filter setup frame. If we detect this, 2790 * we have to send the setup frame again, 2791 * or else the filter won't be programmed 2792 * correctly. 2793 */ 2794 if (DC_IS_PNIC(sc)) { 2795 if (txstat & DC_TXSTAT_ERRSUM) 2796 dc_setfilt(sc); 2797 } 2798 sc->dc_cdata.dc_tx_chain[idx] = NULL; 2799 } 2800 sc->dc_cdata.dc_tx_cnt--; 2801 DC_INC(idx, DC_TX_LIST_CNT); 2802 continue; 2803 } 2804 2805 if (DC_IS_XIRCOM(sc) || DC_IS_CONEXANT(sc)) { 2806 /* 2807 * XXX: Why does my Xircom taunt me so? 2808 * For some reason it likes setting the CARRLOST flag 2809 * even when the carrier is there. wtf?!? 2810 * Who knows, but Conexant chips have the 2811 * same problem. Maybe they took lessons 2812 * from Xircom. 2813 */ 2814 if (/*sc->dc_type == DC_TYPE_21143 &&*/ 2815 sc->dc_pmode == DC_PMODE_MII && 2816 ((txstat & 0xFFFF) & ~(DC_TXSTAT_ERRSUM | 2817 DC_TXSTAT_NOCARRIER))) 2818 txstat &= ~DC_TXSTAT_ERRSUM; 2819 } else { 2820 if (/*sc->dc_type == DC_TYPE_21143 &&*/ 2821 sc->dc_pmode == DC_PMODE_MII && 2822 ((txstat & 0xFFFF) & ~(DC_TXSTAT_ERRSUM | 2823 DC_TXSTAT_NOCARRIER | DC_TXSTAT_CARRLOST))) 2824 txstat &= ~DC_TXSTAT_ERRSUM; 2825 } 2826 2827 if (txstat & DC_TXSTAT_ERRSUM) { 2828 ifp->if_oerrors++; 2829 if (txstat & DC_TXSTAT_EXCESSCOLL) 2830 ifp->if_collisions++; 2831 if (txstat & DC_TXSTAT_LATECOLL) 2832 ifp->if_collisions++; 2833 if (!(txstat & DC_TXSTAT_UNDERRUN)) { 2834 dc_init_locked(sc); 2835 return; 2836 } 2837 } 2838 2839 ifp->if_collisions += (txstat & DC_TXSTAT_COLLCNT) >> 3; 2840 2841 ifp->if_opackets++; 2842 if (sc->dc_cdata.dc_tx_chain[idx] != NULL) { 2843 bus_dmamap_sync(sc->dc_mtag, 2844 sc->dc_cdata.dc_tx_map[idx], 2845 BUS_DMASYNC_POSTWRITE); 2846 bus_dmamap_unload(sc->dc_mtag, 2847 sc->dc_cdata.dc_tx_map[idx]); 2848 m_freem(sc->dc_cdata.dc_tx_chain[idx]); 2849 sc->dc_cdata.dc_tx_chain[idx] = NULL; 2850 } 2851 2852 sc->dc_cdata.dc_tx_cnt--; 2853 DC_INC(idx, DC_TX_LIST_CNT); 2854 } 2855 sc->dc_cdata.dc_tx_cons = idx; 2856 2857 if (DC_TX_LIST_CNT - sc->dc_cdata.dc_tx_cnt > DC_TX_LIST_RSVD) 2858 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 2859 2860 if (sc->dc_cdata.dc_tx_cnt == 0) 2861 sc->dc_wdog_timer = 0; 2862 } 2863 2864 static void 2865 dc_tick(void *xsc) 2866 { 2867 struct dc_softc *sc; 2868 struct mii_data *mii; 2869 struct ifnet *ifp; 2870 u_int32_t r; 2871 2872 sc = xsc; 2873 DC_LOCK_ASSERT(sc); 2874 ifp = sc->dc_ifp; 2875 mii = device_get_softc(sc->dc_miibus); 2876 2877 if (sc->dc_flags & DC_REDUCED_MII_POLL) { 2878 if (sc->dc_flags & DC_21143_NWAY) { 2879 r = CSR_READ_4(sc, DC_10BTSTAT); 2880 if (IFM_SUBTYPE(mii->mii_media_active) == 2881 IFM_100_TX && (r & DC_TSTAT_LS100)) { 2882 sc->dc_link = 0; 2883 mii_mediachg(mii); 2884 } 2885 if (IFM_SUBTYPE(mii->mii_media_active) == 2886 IFM_10_T && (r & DC_TSTAT_LS10)) { 2887 sc->dc_link = 0; 2888 mii_mediachg(mii); 2889 } 2890 if (sc->dc_link == 0) 2891 mii_tick(mii); 2892 } else { 2893 /* 2894 * For NICs which never report DC_RXSTATE_WAIT, we 2895 * have to bite the bullet... 2896 */ 2897 if ((DC_HAS_BROKEN_RXSTATE(sc) || (CSR_READ_4(sc, 2898 DC_ISR) & DC_ISR_RX_STATE) == DC_RXSTATE_WAIT) && 2899 sc->dc_cdata.dc_tx_cnt == 0) { 2900 mii_tick(mii); 2901 if (!(mii->mii_media_status & IFM_ACTIVE)) 2902 sc->dc_link = 0; 2903 } 2904 } 2905 } else 2906 mii_tick(mii); 2907 2908 /* 2909 * When the init routine completes, we expect to be able to send 2910 * packets right away, and in fact the network code will send a 2911 * gratuitous ARP the moment the init routine marks the interface 2912 * as running. However, even though the MAC may have been initialized, 2913 * there may be a delay of a few seconds before the PHY completes 2914 * autonegotiation and the link is brought up. Any transmissions 2915 * made during that delay will be lost. Dealing with this is tricky: 2916 * we can't just pause in the init routine while waiting for the 2917 * PHY to come ready since that would bring the whole system to 2918 * a screeching halt for several seconds. 2919 * 2920 * What we do here is prevent the TX start routine from sending 2921 * any packets until a link has been established. After the 2922 * interface has been initialized, the tick routine will poll 2923 * the state of the PHY until the IFM_ACTIVE flag is set. Until 2924 * that time, packets will stay in the send queue, and once the 2925 * link comes up, they will be flushed out to the wire. 2926 */ 2927 if (!sc->dc_link && mii->mii_media_status & IFM_ACTIVE && 2928 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) { 2929 sc->dc_link++; 2930 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 2931 dc_start_locked(ifp); 2932 } 2933 2934 if (sc->dc_flags & DC_21143_NWAY && !sc->dc_link) 2935 callout_reset(&sc->dc_stat_ch, hz/10, dc_tick, sc); 2936 else 2937 callout_reset(&sc->dc_stat_ch, hz, dc_tick, sc); 2938 } 2939 2940 /* 2941 * A transmit underrun has occurred. Back off the transmit threshold, 2942 * or switch to store and forward mode if we have to. 2943 */ 2944 static void 2945 dc_tx_underrun(struct dc_softc *sc) 2946 { 2947 u_int32_t isr; 2948 int i; 2949 2950 if (DC_IS_DAVICOM(sc)) 2951 dc_init_locked(sc); 2952 2953 if (DC_IS_INTEL(sc)) { 2954 /* 2955 * The real 21143 requires that the transmitter be idle 2956 * in order to change the transmit threshold or store 2957 * and forward state. 2958 */ 2959 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_TX_ON); 2960 2961 for (i = 0; i < DC_TIMEOUT; i++) { 2962 isr = CSR_READ_4(sc, DC_ISR); 2963 if (isr & DC_ISR_TX_IDLE) 2964 break; 2965 DELAY(10); 2966 } 2967 if (i == DC_TIMEOUT) { 2968 device_printf(sc->dc_dev, 2969 "%s: failed to force tx to idle state\n", 2970 __func__); 2971 dc_init_locked(sc); 2972 } 2973 } 2974 2975 device_printf(sc->dc_dev, "TX underrun -- "); 2976 sc->dc_txthresh += DC_TXTHRESH_INC; 2977 if (sc->dc_txthresh > DC_TXTHRESH_MAX) { 2978 printf("using store and forward mode\n"); 2979 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_STORENFWD); 2980 } else { 2981 printf("increasing TX threshold\n"); 2982 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_TX_THRESH); 2983 DC_SETBIT(sc, DC_NETCFG, sc->dc_txthresh); 2984 } 2985 2986 if (DC_IS_INTEL(sc)) 2987 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_TX_ON); 2988 } 2989 2990 #ifdef DEVICE_POLLING 2991 static poll_handler_t dc_poll; 2992 2993 static void 2994 dc_poll(struct ifnet *ifp, enum poll_cmd cmd, int count) 2995 { 2996 struct dc_softc *sc = ifp->if_softc; 2997 2998 DC_LOCK(sc); 2999 3000 if (!(ifp->if_drv_flags & IFF_DRV_RUNNING)) { 3001 DC_UNLOCK(sc); 3002 return; 3003 } 3004 3005 sc->rxcycles = count; 3006 dc_rxeof(sc); 3007 dc_txeof(sc); 3008 if (!IFQ_IS_EMPTY(&ifp->if_snd) && 3009 !(ifp->if_drv_flags & IFF_DRV_OACTIVE)) 3010 dc_start_locked(ifp); 3011 3012 if (cmd == POLL_AND_CHECK_STATUS) { /* also check status register */ 3013 u_int32_t status; 3014 3015 status = CSR_READ_4(sc, DC_ISR); 3016 status &= (DC_ISR_RX_WATDOGTIMEO | DC_ISR_RX_NOBUF | 3017 DC_ISR_TX_NOBUF | DC_ISR_TX_IDLE | DC_ISR_TX_UNDERRUN | 3018 DC_ISR_BUS_ERR); 3019 if (!status) { 3020 DC_UNLOCK(sc); 3021 return; 3022 } 3023 /* ack what we have */ 3024 CSR_WRITE_4(sc, DC_ISR, status); 3025 3026 if (status & (DC_ISR_RX_WATDOGTIMEO | DC_ISR_RX_NOBUF)) { 3027 u_int32_t r = CSR_READ_4(sc, DC_FRAMESDISCARDED); 3028 ifp->if_ierrors += (r & 0xffff) + ((r >> 17) & 0x7ff); 3029 3030 if (dc_rx_resync(sc)) 3031 dc_rxeof(sc); 3032 } 3033 /* restart transmit unit if necessary */ 3034 if (status & DC_ISR_TX_IDLE && sc->dc_cdata.dc_tx_cnt) 3035 CSR_WRITE_4(sc, DC_TXSTART, 0xFFFFFFFF); 3036 3037 if (status & DC_ISR_TX_UNDERRUN) 3038 dc_tx_underrun(sc); 3039 3040 if (status & DC_ISR_BUS_ERR) { 3041 if_printf(ifp, "%s: bus error\n", __func__); 3042 dc_reset(sc); 3043 dc_init_locked(sc); 3044 } 3045 } 3046 DC_UNLOCK(sc); 3047 } 3048 #endif /* DEVICE_POLLING */ 3049 3050 static void 3051 dc_intr(void *arg) 3052 { 3053 struct dc_softc *sc; 3054 struct ifnet *ifp; 3055 u_int32_t status; 3056 3057 sc = arg; 3058 3059 if (sc->suspended) 3060 return; 3061 3062 if ((CSR_READ_4(sc, DC_ISR) & DC_INTRS) == 0) 3063 return; 3064 3065 DC_LOCK(sc); 3066 ifp = sc->dc_ifp; 3067 #ifdef DEVICE_POLLING 3068 if (ifp->if_capenable & IFCAP_POLLING) { 3069 DC_UNLOCK(sc); 3070 return; 3071 } 3072 #endif 3073 3074 /* Suppress unwanted interrupts */ 3075 if (!(ifp->if_flags & IFF_UP)) { 3076 if (CSR_READ_4(sc, DC_ISR) & DC_INTRS) 3077 dc_stop(sc); 3078 DC_UNLOCK(sc); 3079 return; 3080 } 3081 3082 /* Disable interrupts. */ 3083 CSR_WRITE_4(sc, DC_IMR, 0x00000000); 3084 3085 while (((status = CSR_READ_4(sc, DC_ISR)) & DC_INTRS) && 3086 status != 0xFFFFFFFF && 3087 (ifp->if_drv_flags & IFF_DRV_RUNNING)) { 3088 3089 CSR_WRITE_4(sc, DC_ISR, status); 3090 3091 if (status & DC_ISR_RX_OK) { 3092 int curpkts; 3093 curpkts = ifp->if_ipackets; 3094 dc_rxeof(sc); 3095 if (curpkts == ifp->if_ipackets) { 3096 while (dc_rx_resync(sc)) 3097 dc_rxeof(sc); 3098 } 3099 } 3100 3101 if (status & (DC_ISR_TX_OK | DC_ISR_TX_NOBUF)) 3102 dc_txeof(sc); 3103 3104 if (status & DC_ISR_TX_IDLE) { 3105 dc_txeof(sc); 3106 if (sc->dc_cdata.dc_tx_cnt) { 3107 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_TX_ON); 3108 CSR_WRITE_4(sc, DC_TXSTART, 0xFFFFFFFF); 3109 } 3110 } 3111 3112 if (status & DC_ISR_TX_UNDERRUN) 3113 dc_tx_underrun(sc); 3114 3115 if ((status & DC_ISR_RX_WATDOGTIMEO) 3116 || (status & DC_ISR_RX_NOBUF)) { 3117 int curpkts; 3118 curpkts = ifp->if_ipackets; 3119 dc_rxeof(sc); 3120 if (curpkts == ifp->if_ipackets) { 3121 while (dc_rx_resync(sc)) 3122 dc_rxeof(sc); 3123 } 3124 } 3125 3126 if (status & DC_ISR_BUS_ERR) { 3127 dc_reset(sc); 3128 dc_init_locked(sc); 3129 } 3130 } 3131 3132 /* Re-enable interrupts. */ 3133 CSR_WRITE_4(sc, DC_IMR, DC_INTRS); 3134 3135 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 3136 dc_start_locked(ifp); 3137 3138 DC_UNLOCK(sc); 3139 } 3140 3141 /* 3142 * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data 3143 * pointers to the fragment pointers. 3144 */ 3145 static int 3146 dc_encap(struct dc_softc *sc, struct mbuf **m_head) 3147 { 3148 bus_dma_segment_t segs[DC_MAXFRAGS]; 3149 struct dc_desc *f; 3150 struct mbuf *m; 3151 int cur, defragged, error, first, frag, i, idx, nseg; 3152 3153 /* 3154 * If there's no way we can send any packets, return now. 3155 */ 3156 if (DC_TX_LIST_CNT - sc->dc_cdata.dc_tx_cnt <= DC_TX_LIST_RSVD) 3157 return (ENOBUFS); 3158 3159 m = NULL; 3160 defragged = 0; 3161 if (sc->dc_flags & DC_TX_COALESCE && 3162 ((*m_head)->m_next != NULL || sc->dc_flags & DC_TX_ALIGN)) { 3163 m = m_defrag(*m_head, M_DONTWAIT); 3164 defragged = 1; 3165 } else { 3166 /* 3167 * Count the number of frags in this chain to see if we 3168 * need to m_collapse. Since the descriptor list is shared 3169 * by all packets, we'll m_collapse long chains so that they 3170 * do not use up the entire list, even if they would fit. 3171 */ 3172 i = 0; 3173 for (m = *m_head; m != NULL; m = m->m_next) 3174 i++; 3175 if (i > DC_TX_LIST_CNT / 4 || 3176 DC_TX_LIST_CNT - i + sc->dc_cdata.dc_tx_cnt <= 3177 DC_TX_LIST_RSVD) { 3178 m = m_collapse(*m_head, M_DONTWAIT, DC_MAXFRAGS); 3179 defragged = 1; 3180 } 3181 } 3182 if (defragged != 0) { 3183 if (m == NULL) { 3184 m_freem(*m_head); 3185 *m_head = NULL; 3186 return (ENOBUFS); 3187 } 3188 *m_head = m; 3189 } 3190 3191 idx = sc->dc_cdata.dc_tx_prod; 3192 error = bus_dmamap_load_mbuf_sg(sc->dc_mtag, 3193 sc->dc_cdata.dc_tx_map[idx], *m_head, segs, &nseg, 0); 3194 if (error == EFBIG) { 3195 if (defragged != 0 || (m = m_collapse(*m_head, M_DONTWAIT, 3196 DC_MAXFRAGS)) == NULL) { 3197 m_freem(*m_head); 3198 *m_head = NULL; 3199 return (defragged != 0 ? error : ENOBUFS); 3200 } 3201 *m_head = m; 3202 error = bus_dmamap_load_mbuf_sg(sc->dc_mtag, 3203 sc->dc_cdata.dc_tx_map[idx], *m_head, segs, &nseg, 0); 3204 if (error != 0) { 3205 m_freem(*m_head); 3206 *m_head = NULL; 3207 return (error); 3208 } 3209 } else if (error != 0) 3210 return (error); 3211 KASSERT(nseg <= DC_MAXFRAGS, 3212 ("%s: wrong number of segments (%d)", __func__, nseg)); 3213 if (nseg == 0) { 3214 m_freem(*m_head); 3215 *m_head = NULL; 3216 return (EIO); 3217 } 3218 3219 first = cur = frag = sc->dc_cdata.dc_tx_prod; 3220 for (i = 0; i < nseg; i++) { 3221 if ((sc->dc_flags & DC_TX_ADMTEK_WAR) && 3222 (frag == (DC_TX_LIST_CNT - 1)) && 3223 (first != sc->dc_cdata.dc_tx_first)) { 3224 bus_dmamap_unload(sc->dc_mtag, 3225 sc->dc_cdata.dc_tx_map[first]); 3226 m_freem(*m_head); 3227 *m_head = NULL; 3228 return (ENOBUFS); 3229 } 3230 3231 f = &sc->dc_ldata->dc_tx_list[frag]; 3232 f->dc_ctl = htole32(DC_TXCTL_TLINK | segs[i].ds_len); 3233 if (i == 0) { 3234 f->dc_status = 0; 3235 f->dc_ctl |= htole32(DC_TXCTL_FIRSTFRAG); 3236 } else 3237 f->dc_status = htole32(DC_TXSTAT_OWN); 3238 f->dc_data = htole32(segs[i].ds_addr); 3239 cur = frag; 3240 DC_INC(frag, DC_TX_LIST_CNT); 3241 } 3242 3243 sc->dc_cdata.dc_tx_prod = frag; 3244 sc->dc_cdata.dc_tx_cnt += nseg; 3245 sc->dc_cdata.dc_tx_chain[cur] = *m_head; 3246 sc->dc_ldata->dc_tx_list[cur].dc_ctl |= htole32(DC_TXCTL_LASTFRAG); 3247 if (sc->dc_flags & DC_TX_INTR_FIRSTFRAG) 3248 sc->dc_ldata->dc_tx_list[first].dc_ctl |= 3249 htole32(DC_TXCTL_FINT); 3250 if (sc->dc_flags & DC_TX_INTR_ALWAYS) 3251 sc->dc_ldata->dc_tx_list[cur].dc_ctl |= htole32(DC_TXCTL_FINT); 3252 if (sc->dc_flags & DC_TX_USE_TX_INTR && sc->dc_cdata.dc_tx_cnt > 64) 3253 sc->dc_ldata->dc_tx_list[cur].dc_ctl |= htole32(DC_TXCTL_FINT); 3254 sc->dc_ldata->dc_tx_list[first].dc_status = htole32(DC_TXSTAT_OWN); 3255 3256 bus_dmamap_sync(sc->dc_mtag, sc->dc_cdata.dc_tx_map[idx], 3257 BUS_DMASYNC_PREWRITE); 3258 bus_dmamap_sync(sc->dc_ltag, sc->dc_lmap, 3259 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3260 return (0); 3261 } 3262 3263 static void 3264 dc_start(struct ifnet *ifp) 3265 { 3266 struct dc_softc *sc; 3267 3268 sc = ifp->if_softc; 3269 DC_LOCK(sc); 3270 dc_start_locked(ifp); 3271 DC_UNLOCK(sc); 3272 } 3273 3274 /* 3275 * Main transmit routine 3276 * To avoid having to do mbuf copies, we put pointers to the mbuf data 3277 * regions directly in the transmit lists. We also save a copy of the 3278 * pointers since the transmit list fragment pointers are physical 3279 * addresses. 3280 */ 3281 static void 3282 dc_start_locked(struct ifnet *ifp) 3283 { 3284 struct dc_softc *sc; 3285 struct mbuf *m_head = NULL; 3286 unsigned int queued = 0; 3287 int idx; 3288 3289 sc = ifp->if_softc; 3290 3291 DC_LOCK_ASSERT(sc); 3292 3293 if (!sc->dc_link && ifp->if_snd.ifq_len < 10) 3294 return; 3295 3296 if (ifp->if_drv_flags & IFF_DRV_OACTIVE) 3297 return; 3298 3299 idx = sc->dc_cdata.dc_tx_first = sc->dc_cdata.dc_tx_prod; 3300 3301 while (sc->dc_cdata.dc_tx_chain[idx] == NULL) { 3302 IFQ_DRV_DEQUEUE(&ifp->if_snd, m_head); 3303 if (m_head == NULL) 3304 break; 3305 3306 if (dc_encap(sc, &m_head)) { 3307 if (m_head == NULL) 3308 break; 3309 IFQ_DRV_PREPEND(&ifp->if_snd, m_head); 3310 ifp->if_drv_flags |= IFF_DRV_OACTIVE; 3311 break; 3312 } 3313 idx = sc->dc_cdata.dc_tx_prod; 3314 3315 queued++; 3316 /* 3317 * If there's a BPF listener, bounce a copy of this frame 3318 * to him. 3319 */ 3320 BPF_MTAP(ifp, m_head); 3321 3322 if (sc->dc_flags & DC_TX_ONE) { 3323 ifp->if_drv_flags |= IFF_DRV_OACTIVE; 3324 break; 3325 } 3326 } 3327 3328 if (queued > 0) { 3329 /* Transmit */ 3330 if (!(sc->dc_flags & DC_TX_POLL)) 3331 CSR_WRITE_4(sc, DC_TXSTART, 0xFFFFFFFF); 3332 3333 /* 3334 * Set a timeout in case the chip goes out to lunch. 3335 */ 3336 sc->dc_wdog_timer = 5; 3337 } 3338 } 3339 3340 static void 3341 dc_init(void *xsc) 3342 { 3343 struct dc_softc *sc = xsc; 3344 3345 DC_LOCK(sc); 3346 dc_init_locked(sc); 3347 DC_UNLOCK(sc); 3348 } 3349 3350 static void 3351 dc_init_locked(struct dc_softc *sc) 3352 { 3353 struct ifnet *ifp = sc->dc_ifp; 3354 struct mii_data *mii; 3355 3356 DC_LOCK_ASSERT(sc); 3357 3358 mii = device_get_softc(sc->dc_miibus); 3359 3360 /* 3361 * Cancel pending I/O and free all RX/TX buffers. 3362 */ 3363 dc_stop(sc); 3364 dc_reset(sc); 3365 3366 /* 3367 * Set cache alignment and burst length. 3368 */ 3369 if (DC_IS_ASIX(sc) || DC_IS_DAVICOM(sc)) 3370 CSR_WRITE_4(sc, DC_BUSCTL, 0); 3371 else 3372 CSR_WRITE_4(sc, DC_BUSCTL, DC_BUSCTL_MRME | DC_BUSCTL_MRLE); 3373 /* 3374 * Evenly share the bus between receive and transmit process. 3375 */ 3376 if (DC_IS_INTEL(sc)) 3377 DC_SETBIT(sc, DC_BUSCTL, DC_BUSCTL_ARBITRATION); 3378 if (DC_IS_DAVICOM(sc) || DC_IS_INTEL(sc)) { 3379 DC_SETBIT(sc, DC_BUSCTL, DC_BURSTLEN_USECA); 3380 } else { 3381 DC_SETBIT(sc, DC_BUSCTL, DC_BURSTLEN_16LONG); 3382 } 3383 if (sc->dc_flags & DC_TX_POLL) 3384 DC_SETBIT(sc, DC_BUSCTL, DC_TXPOLL_1); 3385 switch(sc->dc_cachesize) { 3386 case 32: 3387 DC_SETBIT(sc, DC_BUSCTL, DC_CACHEALIGN_32LONG); 3388 break; 3389 case 16: 3390 DC_SETBIT(sc, DC_BUSCTL, DC_CACHEALIGN_16LONG); 3391 break; 3392 case 8: 3393 DC_SETBIT(sc, DC_BUSCTL, DC_CACHEALIGN_8LONG); 3394 break; 3395 case 0: 3396 default: 3397 DC_SETBIT(sc, DC_BUSCTL, DC_CACHEALIGN_NONE); 3398 break; 3399 } 3400 3401 if (sc->dc_flags & DC_TX_STORENFWD) 3402 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_STORENFWD); 3403 else { 3404 if (sc->dc_txthresh > DC_TXTHRESH_MAX) { 3405 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_STORENFWD); 3406 } else { 3407 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_STORENFWD); 3408 DC_SETBIT(sc, DC_NETCFG, sc->dc_txthresh); 3409 } 3410 } 3411 3412 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_NO_RXCRC); 3413 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_TX_BACKOFF); 3414 3415 if (DC_IS_MACRONIX(sc) || DC_IS_PNICII(sc)) { 3416 /* 3417 * The app notes for the 98713 and 98715A say that 3418 * in order to have the chips operate properly, a magic 3419 * number must be written to CSR16. Macronix does not 3420 * document the meaning of these bits so there's no way 3421 * to know exactly what they do. The 98713 has a magic 3422 * number all its own; the rest all use a different one. 3423 */ 3424 DC_CLRBIT(sc, DC_MX_MAGICPACKET, 0xFFFF0000); 3425 if (sc->dc_type == DC_TYPE_98713) 3426 DC_SETBIT(sc, DC_MX_MAGICPACKET, DC_MX_MAGIC_98713); 3427 else 3428 DC_SETBIT(sc, DC_MX_MAGICPACKET, DC_MX_MAGIC_98715); 3429 } 3430 3431 if (DC_IS_XIRCOM(sc)) { 3432 /* 3433 * setup General Purpose Port mode and data so the tulip 3434 * can talk to the MII. 3435 */ 3436 CSR_WRITE_4(sc, DC_SIAGP, DC_SIAGP_WRITE_EN | DC_SIAGP_INT1_EN | 3437 DC_SIAGP_MD_GP2_OUTPUT | DC_SIAGP_MD_GP0_OUTPUT); 3438 DELAY(10); 3439 CSR_WRITE_4(sc, DC_SIAGP, DC_SIAGP_INT1_EN | 3440 DC_SIAGP_MD_GP2_OUTPUT | DC_SIAGP_MD_GP0_OUTPUT); 3441 DELAY(10); 3442 } 3443 3444 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_TX_THRESH); 3445 DC_SETBIT(sc, DC_NETCFG, DC_TXTHRESH_MIN); 3446 3447 /* Init circular RX list. */ 3448 if (dc_list_rx_init(sc) == ENOBUFS) { 3449 device_printf(sc->dc_dev, 3450 "initialization failed: no memory for rx buffers\n"); 3451 dc_stop(sc); 3452 return; 3453 } 3454 3455 /* 3456 * Init TX descriptors. 3457 */ 3458 dc_list_tx_init(sc); 3459 3460 /* 3461 * Load the address of the RX list. 3462 */ 3463 CSR_WRITE_4(sc, DC_RXADDR, DC_RXDESC(sc, 0)); 3464 CSR_WRITE_4(sc, DC_TXADDR, DC_TXDESC(sc, 0)); 3465 3466 /* 3467 * Enable interrupts. 3468 */ 3469 #ifdef DEVICE_POLLING 3470 /* 3471 * ... but only if we are not polling, and make sure they are off in 3472 * the case of polling. Some cards (e.g. fxp) turn interrupts on 3473 * after a reset. 3474 */ 3475 if (ifp->if_capenable & IFCAP_POLLING) 3476 CSR_WRITE_4(sc, DC_IMR, 0x00000000); 3477 else 3478 #endif 3479 CSR_WRITE_4(sc, DC_IMR, DC_INTRS); 3480 CSR_WRITE_4(sc, DC_ISR, 0xFFFFFFFF); 3481 3482 /* Enable transmitter. */ 3483 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_TX_ON); 3484 3485 /* 3486 * If this is an Intel 21143 and we're not using the 3487 * MII port, program the LED control pins so we get 3488 * link and activity indications. 3489 */ 3490 if (sc->dc_flags & DC_TULIP_LEDS) { 3491 CSR_WRITE_4(sc, DC_WATCHDOG, 3492 DC_WDOG_CTLWREN | DC_WDOG_LINK | DC_WDOG_ACTIVITY); 3493 CSR_WRITE_4(sc, DC_WATCHDOG, 0); 3494 } 3495 3496 /* 3497 * Load the RX/multicast filter. We do this sort of late 3498 * because the filter programming scheme on the 21143 and 3499 * some clones requires DMAing a setup frame via the TX 3500 * engine, and we need the transmitter enabled for that. 3501 */ 3502 dc_setfilt(sc); 3503 3504 /* Enable receiver. */ 3505 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_ON); 3506 CSR_WRITE_4(sc, DC_RXSTART, 0xFFFFFFFF); 3507 3508 mii_mediachg(mii); 3509 dc_setcfg(sc, sc->dc_if_media); 3510 3511 ifp->if_drv_flags |= IFF_DRV_RUNNING; 3512 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 3513 3514 /* Don't start the ticker if this is a homePNA link. */ 3515 if (IFM_SUBTYPE(mii->mii_media.ifm_media) == IFM_HPNA_1) 3516 sc->dc_link = 1; 3517 else { 3518 if (sc->dc_flags & DC_21143_NWAY) 3519 callout_reset(&sc->dc_stat_ch, hz/10, dc_tick, sc); 3520 else 3521 callout_reset(&sc->dc_stat_ch, hz, dc_tick, sc); 3522 } 3523 3524 sc->dc_wdog_timer = 0; 3525 callout_reset(&sc->dc_wdog_ch, hz, dc_watchdog, sc); 3526 } 3527 3528 /* 3529 * Set media options. 3530 */ 3531 static int 3532 dc_ifmedia_upd(struct ifnet *ifp) 3533 { 3534 struct dc_softc *sc; 3535 struct mii_data *mii; 3536 struct ifmedia *ifm; 3537 3538 sc = ifp->if_softc; 3539 mii = device_get_softc(sc->dc_miibus); 3540 DC_LOCK(sc); 3541 mii_mediachg(mii); 3542 ifm = &mii->mii_media; 3543 3544 if (DC_IS_DAVICOM(sc) && 3545 IFM_SUBTYPE(ifm->ifm_media) == IFM_HPNA_1) 3546 dc_setcfg(sc, ifm->ifm_media); 3547 else 3548 sc->dc_link = 0; 3549 DC_UNLOCK(sc); 3550 3551 return (0); 3552 } 3553 3554 /* 3555 * Report current media status. 3556 */ 3557 static void 3558 dc_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 3559 { 3560 struct dc_softc *sc; 3561 struct mii_data *mii; 3562 struct ifmedia *ifm; 3563 3564 sc = ifp->if_softc; 3565 mii = device_get_softc(sc->dc_miibus); 3566 DC_LOCK(sc); 3567 mii_pollstat(mii); 3568 ifm = &mii->mii_media; 3569 if (DC_IS_DAVICOM(sc)) { 3570 if (IFM_SUBTYPE(ifm->ifm_media) == IFM_HPNA_1) { 3571 ifmr->ifm_active = ifm->ifm_media; 3572 ifmr->ifm_status = 0; 3573 DC_UNLOCK(sc); 3574 return; 3575 } 3576 } 3577 ifmr->ifm_active = mii->mii_media_active; 3578 ifmr->ifm_status = mii->mii_media_status; 3579 DC_UNLOCK(sc); 3580 } 3581 3582 static int 3583 dc_ioctl(struct ifnet *ifp, u_long command, caddr_t data) 3584 { 3585 struct dc_softc *sc = ifp->if_softc; 3586 struct ifreq *ifr = (struct ifreq *)data; 3587 struct mii_data *mii; 3588 int error = 0; 3589 3590 switch (command) { 3591 case SIOCSIFFLAGS: 3592 DC_LOCK(sc); 3593 if (ifp->if_flags & IFF_UP) { 3594 int need_setfilt = (ifp->if_flags ^ sc->dc_if_flags) & 3595 (IFF_PROMISC | IFF_ALLMULTI); 3596 3597 if (ifp->if_drv_flags & IFF_DRV_RUNNING) { 3598 if (need_setfilt) 3599 dc_setfilt(sc); 3600 } else { 3601 sc->dc_txthresh = 0; 3602 dc_init_locked(sc); 3603 } 3604 } else { 3605 if (ifp->if_drv_flags & IFF_DRV_RUNNING) 3606 dc_stop(sc); 3607 } 3608 sc->dc_if_flags = ifp->if_flags; 3609 DC_UNLOCK(sc); 3610 error = 0; 3611 break; 3612 case SIOCADDMULTI: 3613 case SIOCDELMULTI: 3614 DC_LOCK(sc); 3615 dc_setfilt(sc); 3616 DC_UNLOCK(sc); 3617 error = 0; 3618 break; 3619 case SIOCGIFMEDIA: 3620 case SIOCSIFMEDIA: 3621 mii = device_get_softc(sc->dc_miibus); 3622 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 3623 break; 3624 case SIOCSIFCAP: 3625 #ifdef DEVICE_POLLING 3626 if (ifr->ifr_reqcap & IFCAP_POLLING && 3627 !(ifp->if_capenable & IFCAP_POLLING)) { 3628 error = ether_poll_register(dc_poll, ifp); 3629 if (error) 3630 return(error); 3631 DC_LOCK(sc); 3632 /* Disable interrupts */ 3633 CSR_WRITE_4(sc, DC_IMR, 0x00000000); 3634 ifp->if_capenable |= IFCAP_POLLING; 3635 DC_UNLOCK(sc); 3636 return (error); 3637 } 3638 if (!(ifr->ifr_reqcap & IFCAP_POLLING) && 3639 ifp->if_capenable & IFCAP_POLLING) { 3640 error = ether_poll_deregister(ifp); 3641 /* Enable interrupts. */ 3642 DC_LOCK(sc); 3643 CSR_WRITE_4(sc, DC_IMR, DC_INTRS); 3644 ifp->if_capenable &= ~IFCAP_POLLING; 3645 DC_UNLOCK(sc); 3646 return (error); 3647 } 3648 #endif /* DEVICE_POLLING */ 3649 break; 3650 default: 3651 error = ether_ioctl(ifp, command, data); 3652 break; 3653 } 3654 3655 return (error); 3656 } 3657 3658 static void 3659 dc_watchdog(void *xsc) 3660 { 3661 struct dc_softc *sc = xsc; 3662 struct ifnet *ifp; 3663 3664 DC_LOCK_ASSERT(sc); 3665 3666 if (sc->dc_wdog_timer == 0 || --sc->dc_wdog_timer != 0) { 3667 callout_reset(&sc->dc_wdog_ch, hz, dc_watchdog, sc); 3668 return; 3669 } 3670 3671 ifp = sc->dc_ifp; 3672 ifp->if_oerrors++; 3673 device_printf(sc->dc_dev, "watchdog timeout\n"); 3674 3675 dc_stop(sc); 3676 dc_reset(sc); 3677 dc_init_locked(sc); 3678 3679 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 3680 dc_start_locked(ifp); 3681 } 3682 3683 /* 3684 * Stop the adapter and free any mbufs allocated to the 3685 * RX and TX lists. 3686 */ 3687 static void 3688 dc_stop(struct dc_softc *sc) 3689 { 3690 struct ifnet *ifp; 3691 struct dc_list_data *ld; 3692 struct dc_chain_data *cd; 3693 int i; 3694 u_int32_t ctl; 3695 3696 DC_LOCK_ASSERT(sc); 3697 3698 ifp = sc->dc_ifp; 3699 ld = sc->dc_ldata; 3700 cd = &sc->dc_cdata; 3701 3702 callout_stop(&sc->dc_stat_ch); 3703 callout_stop(&sc->dc_wdog_ch); 3704 sc->dc_wdog_timer = 0; 3705 3706 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE); 3707 3708 DC_CLRBIT(sc, DC_NETCFG, (DC_NETCFG_RX_ON | DC_NETCFG_TX_ON)); 3709 CSR_WRITE_4(sc, DC_IMR, 0x00000000); 3710 CSR_WRITE_4(sc, DC_TXADDR, 0x00000000); 3711 CSR_WRITE_4(sc, DC_RXADDR, 0x00000000); 3712 sc->dc_link = 0; 3713 3714 /* 3715 * Free data in the RX lists. 3716 */ 3717 for (i = 0; i < DC_RX_LIST_CNT; i++) { 3718 if (cd->dc_rx_chain[i] != NULL) { 3719 m_freem(cd->dc_rx_chain[i]); 3720 cd->dc_rx_chain[i] = NULL; 3721 } 3722 } 3723 bzero(&ld->dc_rx_list, sizeof(ld->dc_rx_list)); 3724 3725 /* 3726 * Free the TX list buffers. 3727 */ 3728 for (i = 0; i < DC_TX_LIST_CNT; i++) { 3729 if (cd->dc_tx_chain[i] != NULL) { 3730 ctl = le32toh(ld->dc_tx_list[i].dc_ctl); 3731 if ((ctl & DC_TXCTL_SETUP) || 3732 !(ctl & DC_TXCTL_LASTFRAG)) { 3733 cd->dc_tx_chain[i] = NULL; 3734 continue; 3735 } 3736 bus_dmamap_unload(sc->dc_mtag, cd->dc_tx_map[i]); 3737 m_freem(cd->dc_tx_chain[i]); 3738 cd->dc_tx_chain[i] = NULL; 3739 } 3740 } 3741 bzero(&ld->dc_tx_list, sizeof(ld->dc_tx_list)); 3742 } 3743 3744 /* 3745 * Device suspend routine. Stop the interface and save some PCI 3746 * settings in case the BIOS doesn't restore them properly on 3747 * resume. 3748 */ 3749 static int 3750 dc_suspend(device_t dev) 3751 { 3752 struct dc_softc *sc; 3753 3754 sc = device_get_softc(dev); 3755 DC_LOCK(sc); 3756 dc_stop(sc); 3757 sc->suspended = 1; 3758 DC_UNLOCK(sc); 3759 3760 return (0); 3761 } 3762 3763 /* 3764 * Device resume routine. Restore some PCI settings in case the BIOS 3765 * doesn't, re-enable busmastering, and restart the interface if 3766 * appropriate. 3767 */ 3768 static int 3769 dc_resume(device_t dev) 3770 { 3771 struct dc_softc *sc; 3772 struct ifnet *ifp; 3773 3774 sc = device_get_softc(dev); 3775 ifp = sc->dc_ifp; 3776 3777 /* reinitialize interface if necessary */ 3778 DC_LOCK(sc); 3779 if (ifp->if_flags & IFF_UP) 3780 dc_init_locked(sc); 3781 3782 sc->suspended = 0; 3783 DC_UNLOCK(sc); 3784 3785 return (0); 3786 } 3787 3788 /* 3789 * Stop all chip I/O so that the kernel's probe routines don't 3790 * get confused by errant DMAs when rebooting. 3791 */ 3792 static int 3793 dc_shutdown(device_t dev) 3794 { 3795 struct dc_softc *sc; 3796 3797 sc = device_get_softc(dev); 3798 3799 DC_LOCK(sc); 3800 dc_stop(sc); 3801 DC_UNLOCK(sc); 3802 3803 return (0); 3804 } 3805