1 /* 2 * Copyright (c) 1997, 1998, 1999 3 * Bill Paul <wpaul@ee.columbia.edu>. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 3. All advertising materials mentioning features or use of this software 14 * must display the following acknowledgement: 15 * This product includes software developed by Bill Paul. 16 * 4. Neither the name of the author nor the names of any co-contributors 17 * may be used to endorse or promote products derived from this software 18 * without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30 * THE POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33 /* 34 * DEC "tulip" clone ethernet driver. Supports the DEC/Intel 21143 35 * series chips and several workalikes including the following: 36 * 37 * Macronix 98713/98715/98725/98727/98732 PMAC (www.macronix.com) 38 * Macronix/Lite-On 82c115 PNIC II (www.macronix.com) 39 * Lite-On 82c168/82c169 PNIC (www.litecom.com) 40 * ASIX Electronics AX88140A (www.asix.com.tw) 41 * ASIX Electronics AX88141 (www.asix.com.tw) 42 * ADMtek AL981 (www.admtek.com.tw) 43 * ADMtek AN985 (www.admtek.com.tw) 44 * Davicom DM9100, DM9102, DM9102A (www.davicom8.com) 45 * Accton EN1217 (www.accton.com) 46 * Xircom X3201 (www.xircom.com) 47 * Abocom FE2500 48 * Conexant LANfinity (www.conexant.com) 49 * 3Com OfficeConnect 10/100B 3CSOHO100B (www.3com.com) 50 * 51 * Datasheets for the 21143 are available at developer.intel.com. 52 * Datasheets for the clone parts can be found at their respective sites. 53 * (Except for the PNIC; see www.freebsd.org/~wpaul/PNIC/pnic.ps.gz.) 54 * The PNIC II is essentially a Macronix 98715A chip; the only difference 55 * worth noting is that its multicast hash table is only 128 bits wide 56 * instead of 512. 57 * 58 * Written by Bill Paul <wpaul@ee.columbia.edu> 59 * Electrical Engineering Department 60 * Columbia University, New York City 61 */ 62 63 /* 64 * The Intel 21143 is the successor to the DEC 21140. It is basically 65 * the same as the 21140 but with a few new features. The 21143 supports 66 * three kinds of media attachments: 67 * 68 * o MII port, for 10Mbps and 100Mbps support and NWAY 69 * autonegotiation provided by an external PHY. 70 * o SYM port, for symbol mode 100Mbps support. 71 * o 10baseT port. 72 * o AUI/BNC port. 73 * 74 * The 100Mbps SYM port and 10baseT port can be used together in 75 * combination with the internal NWAY support to create a 10/100 76 * autosensing configuration. 77 * 78 * Note that not all tulip workalikes are handled in this driver: we only 79 * deal with those which are relatively well behaved. The Winbond is 80 * handled separately due to its different register offsets and the 81 * special handling needed for its various bugs. The PNIC is handled 82 * here, but I'm not thrilled about it. 83 * 84 * All of the workalike chips use some form of MII transceiver support 85 * with the exception of the Macronix chips, which also have a SYM port. 86 * The ASIX AX88140A is also documented to have a SYM port, but all 87 * the cards I've seen use an MII transceiver, probably because the 88 * AX88140A doesn't support internal NWAY. 89 */ 90 91 #include <sys/cdefs.h> 92 __FBSDID("$FreeBSD$"); 93 94 #include <sys/param.h> 95 #include <sys/systm.h> 96 #include <sys/sockio.h> 97 #include <sys/mbuf.h> 98 #include <sys/malloc.h> 99 #include <sys/kernel.h> 100 #include <sys/socket.h> 101 #include <sys/sysctl.h> 102 103 #include <net/if.h> 104 #include <net/if_arp.h> 105 #include <net/ethernet.h> 106 #include <net/if_dl.h> 107 #include <net/if_media.h> 108 #include <net/if_types.h> 109 #include <net/if_vlan_var.h> 110 111 #include <net/bpf.h> 112 113 #include <vm/vm.h> /* for vtophys */ 114 #include <vm/pmap.h> /* for vtophys */ 115 #include <machine/bus_pio.h> 116 #include <machine/bus_memio.h> 117 #include <machine/bus.h> 118 #include <machine/resource.h> 119 #include <sys/bus.h> 120 #include <sys/rman.h> 121 122 #include <dev/mii/mii.h> 123 #include <dev/mii/miivar.h> 124 125 #include <pci/pcireg.h> 126 #include <pci/pcivar.h> 127 128 #define DC_USEIOSPACE 129 #ifdef __alpha__ 130 #define SRM_MEDIA 131 #endif 132 133 #include <pci/if_dcreg.h> 134 135 MODULE_DEPEND(dc, pci, 1, 1, 1); 136 MODULE_DEPEND(dc, ether, 1, 1, 1); 137 MODULE_DEPEND(dc, miibus, 1, 1, 1); 138 139 /* "controller miibus0" required. See GENERIC if you get errors here. */ 140 #include "miibus_if.h" 141 142 /* 143 * Various supported device vendors/types and their names. 144 */ 145 static struct dc_type dc_devs[] = { 146 { DC_VENDORID_DEC, DC_DEVICEID_21143, 147 "Intel 21143 10/100BaseTX" }, 148 { DC_VENDORID_DAVICOM, DC_DEVICEID_DM9009, 149 "Davicom DM9009 10/100BaseTX" }, 150 { DC_VENDORID_DAVICOM, DC_DEVICEID_DM9100, 151 "Davicom DM9100 10/100BaseTX" }, 152 { DC_VENDORID_DAVICOM, DC_DEVICEID_DM9102, 153 "Davicom DM9102 10/100BaseTX" }, 154 { DC_VENDORID_DAVICOM, DC_DEVICEID_DM9102, 155 "Davicom DM9102A 10/100BaseTX" }, 156 { DC_VENDORID_ADMTEK, DC_DEVICEID_AL981, 157 "ADMtek AL981 10/100BaseTX" }, 158 { DC_VENDORID_ADMTEK, DC_DEVICEID_AN985, 159 "ADMtek AN985 10/100BaseTX" }, 160 { DC_VENDORID_ASIX, DC_DEVICEID_AX88140A, 161 "ASIX AX88140A 10/100BaseTX" }, 162 { DC_VENDORID_ASIX, DC_DEVICEID_AX88140A, 163 "ASIX AX88141 10/100BaseTX" }, 164 { DC_VENDORID_MX, DC_DEVICEID_98713, 165 "Macronix 98713 10/100BaseTX" }, 166 { DC_VENDORID_MX, DC_DEVICEID_98713, 167 "Macronix 98713A 10/100BaseTX" }, 168 { DC_VENDORID_CP, DC_DEVICEID_98713_CP, 169 "Compex RL100-TX 10/100BaseTX" }, 170 { DC_VENDORID_CP, DC_DEVICEID_98713_CP, 171 "Compex RL100-TX 10/100BaseTX" }, 172 { DC_VENDORID_MX, DC_DEVICEID_987x5, 173 "Macronix 98715/98715A 10/100BaseTX" }, 174 { DC_VENDORID_MX, DC_DEVICEID_987x5, 175 "Macronix 98715AEC-C 10/100BaseTX" }, 176 { DC_VENDORID_MX, DC_DEVICEID_987x5, 177 "Macronix 98725 10/100BaseTX" }, 178 { DC_VENDORID_MX, DC_DEVICEID_98727, 179 "Macronix 98727/98732 10/100BaseTX" }, 180 { DC_VENDORID_LO, DC_DEVICEID_82C115, 181 "LC82C115 PNIC II 10/100BaseTX" }, 182 { DC_VENDORID_LO, DC_DEVICEID_82C168, 183 "82c168 PNIC 10/100BaseTX" }, 184 { DC_VENDORID_LO, DC_DEVICEID_82C168, 185 "82c169 PNIC 10/100BaseTX" }, 186 { DC_VENDORID_ACCTON, DC_DEVICEID_EN1217, 187 "Accton EN1217 10/100BaseTX" }, 188 { DC_VENDORID_ACCTON, DC_DEVICEID_EN2242, 189 "Accton EN2242 MiniPCI 10/100BaseTX" }, 190 { DC_VENDORID_XIRCOM, DC_DEVICEID_X3201, 191 "Xircom X3201 10/100BaseTX" }, 192 { DC_VENDORID_ABOCOM, DC_DEVICEID_FE2500, 193 "Abocom FE2500 10/100BaseTX" }, 194 { DC_VENDORID_CONEXANT, DC_DEVICEID_RS7112, 195 "Conexant LANfinity MiniPCI 10/100BaseTX" }, 196 { DC_VENDORID_HAWKING, DC_DEVICEID_HAWKING_PN672TX, 197 "Hawking CB102 CardBus 10/100" }, 198 { DC_VENDORID_PLANEX, DC_DEVICEID_FNW3602T, 199 "PlaneX FNW-3602-T CardBus 10/100" }, 200 { DC_VENDORID_3COM, DC_DEVICEID_3CSOHOB, 201 "3Com OfficeConnect 10/100B" }, 202 { 0, 0, NULL } 203 }; 204 205 static int dc_probe (device_t); 206 static int dc_attach (device_t); 207 static int dc_detach (device_t); 208 static int dc_suspend (device_t); 209 static int dc_resume (device_t); 210 static void dc_acpi (device_t); 211 static struct dc_type *dc_devtype (device_t); 212 static int dc_newbuf (struct dc_softc *, int, struct mbuf *); 213 static int dc_encap (struct dc_softc *, struct mbuf *, u_int32_t *); 214 static void dc_pnic_rx_bug_war (struct dc_softc *, int); 215 static int dc_rx_resync (struct dc_softc *); 216 static void dc_rxeof (struct dc_softc *); 217 static void dc_txeof (struct dc_softc *); 218 static void dc_tick (void *); 219 static void dc_tx_underrun (struct dc_softc *); 220 static void dc_intr (void *); 221 static void dc_start (struct ifnet *); 222 static int dc_ioctl (struct ifnet *, u_long, caddr_t); 223 static void dc_init (void *); 224 static void dc_stop (struct dc_softc *); 225 static void dc_watchdog (struct ifnet *); 226 static void dc_shutdown (device_t); 227 static int dc_ifmedia_upd (struct ifnet *); 228 static void dc_ifmedia_sts (struct ifnet *, struct ifmediareq *); 229 230 static void dc_delay (struct dc_softc *); 231 static void dc_eeprom_idle (struct dc_softc *); 232 static void dc_eeprom_putbyte (struct dc_softc *, int); 233 static void dc_eeprom_getword (struct dc_softc *, int, u_int16_t *); 234 static void dc_eeprom_getword_pnic 235 (struct dc_softc *, int, u_int16_t *); 236 static void dc_eeprom_getword_xircom 237 (struct dc_softc *, int, u_int16_t *); 238 static void dc_eeprom_width (struct dc_softc *); 239 static void dc_read_eeprom (struct dc_softc *, caddr_t, int, int, int); 240 241 static void dc_mii_writebit (struct dc_softc *, int); 242 static int dc_mii_readbit (struct dc_softc *); 243 static void dc_mii_sync (struct dc_softc *); 244 static void dc_mii_send (struct dc_softc *, u_int32_t, int); 245 static int dc_mii_readreg (struct dc_softc *, struct dc_mii_frame *); 246 static int dc_mii_writereg (struct dc_softc *, struct dc_mii_frame *); 247 static int dc_miibus_readreg (device_t, int, int); 248 static int dc_miibus_writereg (device_t, int, int, int); 249 static void dc_miibus_statchg (device_t); 250 static void dc_miibus_mediainit (device_t); 251 252 static void dc_setcfg (struct dc_softc *, int); 253 static u_int32_t dc_crc_le (struct dc_softc *, caddr_t); 254 static u_int32_t dc_crc_be (caddr_t); 255 static void dc_setfilt_21143 (struct dc_softc *); 256 static void dc_setfilt_asix (struct dc_softc *); 257 static void dc_setfilt_admtek (struct dc_softc *); 258 static void dc_setfilt_xircom (struct dc_softc *); 259 260 static void dc_setfilt (struct dc_softc *); 261 262 static void dc_reset (struct dc_softc *); 263 static int dc_list_rx_init (struct dc_softc *); 264 static int dc_list_tx_init (struct dc_softc *); 265 266 static void dc_read_srom (struct dc_softc *, int); 267 static void dc_parse_21143_srom (struct dc_softc *); 268 static void dc_decode_leaf_sia (struct dc_softc *, struct dc_eblock_sia *); 269 static void dc_decode_leaf_mii (struct dc_softc *, struct dc_eblock_mii *); 270 static void dc_decode_leaf_sym (struct dc_softc *, struct dc_eblock_sym *); 271 static void dc_apply_fixup (struct dc_softc *, int); 272 273 #ifdef DC_USEIOSPACE 274 #define DC_RES SYS_RES_IOPORT 275 #define DC_RID DC_PCI_CFBIO 276 #else 277 #define DC_RES SYS_RES_MEMORY 278 #define DC_RID DC_PCI_CFBMA 279 #endif 280 281 static device_method_t dc_methods[] = { 282 /* Device interface */ 283 DEVMETHOD(device_probe, dc_probe), 284 DEVMETHOD(device_attach, dc_attach), 285 DEVMETHOD(device_detach, dc_detach), 286 DEVMETHOD(device_suspend, dc_suspend), 287 DEVMETHOD(device_resume, dc_resume), 288 DEVMETHOD(device_shutdown, dc_shutdown), 289 290 /* bus interface */ 291 DEVMETHOD(bus_print_child, bus_generic_print_child), 292 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 293 294 /* MII interface */ 295 DEVMETHOD(miibus_readreg, dc_miibus_readreg), 296 DEVMETHOD(miibus_writereg, dc_miibus_writereg), 297 DEVMETHOD(miibus_statchg, dc_miibus_statchg), 298 DEVMETHOD(miibus_mediainit, dc_miibus_mediainit), 299 300 { 0, 0 } 301 }; 302 303 static driver_t dc_driver = { 304 "dc", 305 dc_methods, 306 sizeof(struct dc_softc) 307 }; 308 309 static devclass_t dc_devclass; 310 #ifdef __i386__ 311 static int dc_quick = 1; 312 SYSCTL_INT(_hw, OID_AUTO, dc_quick, CTLFLAG_RW, 313 &dc_quick,0,"do not mdevget in dc driver"); 314 #endif 315 316 DRIVER_MODULE(dc, cardbus, dc_driver, dc_devclass, 0, 0); 317 DRIVER_MODULE(dc, pci, dc_driver, dc_devclass, 0, 0); 318 DRIVER_MODULE(miibus, dc, miibus_driver, miibus_devclass, 0, 0); 319 320 #define DC_SETBIT(sc, reg, x) \ 321 CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) | (x)) 322 323 #define DC_CLRBIT(sc, reg, x) \ 324 CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) & ~(x)) 325 326 #define SIO_SET(x) DC_SETBIT(sc, DC_SIO, (x)) 327 #define SIO_CLR(x) DC_CLRBIT(sc, DC_SIO, (x)) 328 329 #define IS_MPSAFE 0 330 331 static void 332 dc_delay(struct dc_softc *sc) 333 { 334 int idx; 335 336 for (idx = (300 / 33) + 1; idx > 0; idx--) 337 CSR_READ_4(sc, DC_BUSCTL); 338 } 339 340 static void 341 dc_eeprom_width(struct dc_softc *sc) 342 { 343 int i; 344 345 /* Force EEPROM to idle state. */ 346 dc_eeprom_idle(sc); 347 348 /* Enter EEPROM access mode. */ 349 CSR_WRITE_4(sc, DC_SIO, DC_SIO_EESEL); 350 dc_delay(sc); 351 DC_SETBIT(sc, DC_SIO, DC_SIO_ROMCTL_READ); 352 dc_delay(sc); 353 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); 354 dc_delay(sc); 355 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CS); 356 dc_delay(sc); 357 358 for (i = 3; i--;) { 359 if (6 & (1 << i)) 360 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_DATAIN); 361 else 362 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_DATAIN); 363 dc_delay(sc); 364 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CLK); 365 dc_delay(sc); 366 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); 367 dc_delay(sc); 368 } 369 370 for (i = 1; i <= 12; i++) { 371 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CLK); 372 dc_delay(sc); 373 if (!(CSR_READ_4(sc, DC_SIO) & DC_SIO_EE_DATAOUT)) { 374 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); 375 dc_delay(sc); 376 break; 377 } 378 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); 379 dc_delay(sc); 380 } 381 382 /* Turn off EEPROM access mode. */ 383 dc_eeprom_idle(sc); 384 385 if (i < 4 || i > 12) 386 sc->dc_romwidth = 6; 387 else 388 sc->dc_romwidth = i; 389 390 /* Enter EEPROM access mode. */ 391 CSR_WRITE_4(sc, DC_SIO, DC_SIO_EESEL); 392 dc_delay(sc); 393 DC_SETBIT(sc, DC_SIO, DC_SIO_ROMCTL_READ); 394 dc_delay(sc); 395 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); 396 dc_delay(sc); 397 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CS); 398 dc_delay(sc); 399 400 /* Turn off EEPROM access mode. */ 401 dc_eeprom_idle(sc); 402 } 403 404 static void 405 dc_eeprom_idle(struct dc_softc *sc) 406 { 407 int i; 408 409 CSR_WRITE_4(sc, DC_SIO, DC_SIO_EESEL); 410 dc_delay(sc); 411 DC_SETBIT(sc, DC_SIO, DC_SIO_ROMCTL_READ); 412 dc_delay(sc); 413 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); 414 dc_delay(sc); 415 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CS); 416 dc_delay(sc); 417 418 for (i = 0; i < 25; i++) { 419 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); 420 dc_delay(sc); 421 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CLK); 422 dc_delay(sc); 423 } 424 425 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); 426 dc_delay(sc); 427 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CS); 428 dc_delay(sc); 429 CSR_WRITE_4(sc, DC_SIO, 0x00000000); 430 } 431 432 /* 433 * Send a read command and address to the EEPROM, check for ACK. 434 */ 435 static void 436 dc_eeprom_putbyte(struct dc_softc *sc, int addr) 437 { 438 int d, i; 439 440 d = DC_EECMD_READ >> 6; 441 for (i = 3; i--; ) { 442 if (d & (1 << i)) 443 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_DATAIN); 444 else 445 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_DATAIN); 446 dc_delay(sc); 447 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CLK); 448 dc_delay(sc); 449 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); 450 dc_delay(sc); 451 } 452 453 /* 454 * Feed in each bit and strobe the clock. 455 */ 456 for (i = sc->dc_romwidth; i--;) { 457 if (addr & (1 << i)) { 458 SIO_SET(DC_SIO_EE_DATAIN); 459 } else { 460 SIO_CLR(DC_SIO_EE_DATAIN); 461 } 462 dc_delay(sc); 463 SIO_SET(DC_SIO_EE_CLK); 464 dc_delay(sc); 465 SIO_CLR(DC_SIO_EE_CLK); 466 dc_delay(sc); 467 } 468 } 469 470 /* 471 * Read a word of data stored in the EEPROM at address 'addr.' 472 * The PNIC 82c168/82c169 has its own non-standard way to read 473 * the EEPROM. 474 */ 475 static void 476 dc_eeprom_getword_pnic(struct dc_softc *sc, int addr, u_int16_t *dest) 477 { 478 int i; 479 u_int32_t r; 480 481 CSR_WRITE_4(sc, DC_PN_SIOCTL, DC_PN_EEOPCODE_READ | addr); 482 483 for (i = 0; i < DC_TIMEOUT; i++) { 484 DELAY(1); 485 r = CSR_READ_4(sc, DC_SIO); 486 if (!(r & DC_PN_SIOCTL_BUSY)) { 487 *dest = (u_int16_t)(r & 0xFFFF); 488 return; 489 } 490 } 491 } 492 493 /* 494 * Read a word of data stored in the EEPROM at address 'addr.' 495 * The Xircom X3201 has its own non-standard way to read 496 * the EEPROM, too. 497 */ 498 static void 499 dc_eeprom_getword_xircom(struct dc_softc *sc, int addr, u_int16_t *dest) 500 { 501 502 SIO_SET(DC_SIO_ROMSEL | DC_SIO_ROMCTL_READ); 503 504 addr *= 2; 505 CSR_WRITE_4(sc, DC_ROM, addr | 0x160); 506 *dest = (u_int16_t)CSR_READ_4(sc, DC_SIO) & 0xff; 507 addr += 1; 508 CSR_WRITE_4(sc, DC_ROM, addr | 0x160); 509 *dest |= ((u_int16_t)CSR_READ_4(sc, DC_SIO) & 0xff) << 8; 510 511 SIO_CLR(DC_SIO_ROMSEL | DC_SIO_ROMCTL_READ); 512 } 513 514 /* 515 * Read a word of data stored in the EEPROM at address 'addr.' 516 */ 517 static void 518 dc_eeprom_getword(struct dc_softc *sc, int addr, u_int16_t *dest) 519 { 520 int i; 521 u_int16_t word = 0; 522 523 /* Force EEPROM to idle state. */ 524 dc_eeprom_idle(sc); 525 526 /* Enter EEPROM access mode. */ 527 CSR_WRITE_4(sc, DC_SIO, DC_SIO_EESEL); 528 dc_delay(sc); 529 DC_SETBIT(sc, DC_SIO, DC_SIO_ROMCTL_READ); 530 dc_delay(sc); 531 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); 532 dc_delay(sc); 533 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CS); 534 dc_delay(sc); 535 536 /* 537 * Send address of word we want to read. 538 */ 539 dc_eeprom_putbyte(sc, addr); 540 541 /* 542 * Start reading bits from EEPROM. 543 */ 544 for (i = 0x8000; i; i >>= 1) { 545 SIO_SET(DC_SIO_EE_CLK); 546 dc_delay(sc); 547 if (CSR_READ_4(sc, DC_SIO) & DC_SIO_EE_DATAOUT) 548 word |= i; 549 dc_delay(sc); 550 SIO_CLR(DC_SIO_EE_CLK); 551 dc_delay(sc); 552 } 553 554 /* Turn off EEPROM access mode. */ 555 dc_eeprom_idle(sc); 556 557 *dest = word; 558 } 559 560 /* 561 * Read a sequence of words from the EEPROM. 562 */ 563 static void 564 dc_read_eeprom(struct dc_softc *sc, caddr_t dest, int off, int cnt, int swap) 565 { 566 int i; 567 u_int16_t word = 0, *ptr; 568 569 for (i = 0; i < cnt; i++) { 570 if (DC_IS_PNIC(sc)) 571 dc_eeprom_getword_pnic(sc, off + i, &word); 572 else if (DC_IS_XIRCOM(sc)) 573 dc_eeprom_getword_xircom(sc, off + i, &word); 574 else 575 dc_eeprom_getword(sc, off + i, &word); 576 ptr = (u_int16_t *)(dest + (i * 2)); 577 if (swap) 578 *ptr = ntohs(word); 579 else 580 *ptr = word; 581 } 582 } 583 584 /* 585 * The following two routines are taken from the Macronix 98713 586 * Application Notes pp.19-21. 587 */ 588 /* 589 * Write a bit to the MII bus. 590 */ 591 static void 592 dc_mii_writebit(struct dc_softc *sc, int bit) 593 { 594 595 if (bit) 596 CSR_WRITE_4(sc, DC_SIO, 597 DC_SIO_ROMCTL_WRITE | DC_SIO_MII_DATAOUT); 598 else 599 CSR_WRITE_4(sc, DC_SIO, DC_SIO_ROMCTL_WRITE); 600 601 DC_SETBIT(sc, DC_SIO, DC_SIO_MII_CLK); 602 DC_CLRBIT(sc, DC_SIO, DC_SIO_MII_CLK); 603 } 604 605 /* 606 * Read a bit from the MII bus. 607 */ 608 static int 609 dc_mii_readbit(struct dc_softc *sc) 610 { 611 612 CSR_WRITE_4(sc, DC_SIO, DC_SIO_ROMCTL_READ | DC_SIO_MII_DIR); 613 CSR_READ_4(sc, DC_SIO); 614 DC_SETBIT(sc, DC_SIO, DC_SIO_MII_CLK); 615 DC_CLRBIT(sc, DC_SIO, DC_SIO_MII_CLK); 616 if (CSR_READ_4(sc, DC_SIO) & DC_SIO_MII_DATAIN) 617 return (1); 618 619 return (0); 620 } 621 622 /* 623 * Sync the PHYs by setting data bit and strobing the clock 32 times. 624 */ 625 static void 626 dc_mii_sync(struct dc_softc *sc) 627 { 628 int i; 629 630 CSR_WRITE_4(sc, DC_SIO, DC_SIO_ROMCTL_WRITE); 631 632 for (i = 0; i < 32; i++) 633 dc_mii_writebit(sc, 1); 634 } 635 636 /* 637 * Clock a series of bits through the MII. 638 */ 639 static void 640 dc_mii_send(struct dc_softc *sc, u_int32_t bits, int cnt) 641 { 642 int i; 643 644 for (i = (0x1 << (cnt - 1)); i; i >>= 1) 645 dc_mii_writebit(sc, bits & i); 646 } 647 648 /* 649 * Read an PHY register through the MII. 650 */ 651 static int 652 dc_mii_readreg(struct dc_softc *sc, struct dc_mii_frame *frame) 653 { 654 int i, ack; 655 656 DC_LOCK(sc); 657 658 /* 659 * Set up frame for RX. 660 */ 661 frame->mii_stdelim = DC_MII_STARTDELIM; 662 frame->mii_opcode = DC_MII_READOP; 663 frame->mii_turnaround = 0; 664 frame->mii_data = 0; 665 666 /* 667 * Sync the PHYs. 668 */ 669 dc_mii_sync(sc); 670 671 /* 672 * Send command/address info. 673 */ 674 dc_mii_send(sc, frame->mii_stdelim, 2); 675 dc_mii_send(sc, frame->mii_opcode, 2); 676 dc_mii_send(sc, frame->mii_phyaddr, 5); 677 dc_mii_send(sc, frame->mii_regaddr, 5); 678 679 #ifdef notdef 680 /* Idle bit */ 681 dc_mii_writebit(sc, 1); 682 dc_mii_writebit(sc, 0); 683 #endif 684 685 /* Check for ack. */ 686 ack = dc_mii_readbit(sc); 687 688 /* 689 * Now try reading data bits. If the ack failed, we still 690 * need to clock through 16 cycles to keep the PHY(s) in sync. 691 */ 692 if (ack) { 693 for (i = 0; i < 16; i++) 694 dc_mii_readbit(sc); 695 goto fail; 696 } 697 698 for (i = 0x8000; i; i >>= 1) { 699 if (!ack) { 700 if (dc_mii_readbit(sc)) 701 frame->mii_data |= i; 702 } 703 } 704 705 fail: 706 707 dc_mii_writebit(sc, 0); 708 dc_mii_writebit(sc, 0); 709 710 DC_UNLOCK(sc); 711 712 if (ack) 713 return (1); 714 return (0); 715 } 716 717 /* 718 * Write to a PHY register through the MII. 719 */ 720 static int 721 dc_mii_writereg(struct dc_softc *sc, struct dc_mii_frame *frame) 722 { 723 724 DC_LOCK(sc); 725 /* 726 * Set up frame for TX. 727 */ 728 729 frame->mii_stdelim = DC_MII_STARTDELIM; 730 frame->mii_opcode = DC_MII_WRITEOP; 731 frame->mii_turnaround = DC_MII_TURNAROUND; 732 733 /* 734 * Sync the PHYs. 735 */ 736 dc_mii_sync(sc); 737 738 dc_mii_send(sc, frame->mii_stdelim, 2); 739 dc_mii_send(sc, frame->mii_opcode, 2); 740 dc_mii_send(sc, frame->mii_phyaddr, 5); 741 dc_mii_send(sc, frame->mii_regaddr, 5); 742 dc_mii_send(sc, frame->mii_turnaround, 2); 743 dc_mii_send(sc, frame->mii_data, 16); 744 745 /* Idle bit. */ 746 dc_mii_writebit(sc, 0); 747 dc_mii_writebit(sc, 0); 748 749 DC_UNLOCK(sc); 750 751 return (0); 752 } 753 754 static int 755 dc_miibus_readreg(device_t dev, int phy, int reg) 756 { 757 struct dc_mii_frame frame; 758 struct dc_softc *sc; 759 int i, rval, phy_reg = 0; 760 761 sc = device_get_softc(dev); 762 bzero(&frame, sizeof(frame)); 763 764 /* 765 * Note: both the AL981 and AN985 have internal PHYs, 766 * however the AL981 provides direct access to the PHY 767 * registers while the AN985 uses a serial MII interface. 768 * The AN985's MII interface is also buggy in that you 769 * can read from any MII address (0 to 31), but only address 1 770 * behaves normally. To deal with both cases, we pretend 771 * that the PHY is at MII address 1. 772 */ 773 if (DC_IS_ADMTEK(sc) && phy != DC_ADMTEK_PHYADDR) 774 return (0); 775 776 /* 777 * Note: the ukphy probes of the RS7112 report a PHY at 778 * MII address 0 (possibly HomePNA?) and 1 (ethernet) 779 * so we only respond to correct one. 780 */ 781 if (DC_IS_CONEXANT(sc) && phy != DC_CONEXANT_PHYADDR) 782 return (0); 783 784 if (sc->dc_pmode != DC_PMODE_MII) { 785 if (phy == (MII_NPHY - 1)) { 786 switch (reg) { 787 case MII_BMSR: 788 /* 789 * Fake something to make the probe 790 * code think there's a PHY here. 791 */ 792 return (BMSR_MEDIAMASK); 793 break; 794 case MII_PHYIDR1: 795 if (DC_IS_PNIC(sc)) 796 return (DC_VENDORID_LO); 797 return (DC_VENDORID_DEC); 798 break; 799 case MII_PHYIDR2: 800 if (DC_IS_PNIC(sc)) 801 return (DC_DEVICEID_82C168); 802 return (DC_DEVICEID_21143); 803 break; 804 default: 805 return (0); 806 break; 807 } 808 } else 809 return (0); 810 } 811 812 if (DC_IS_PNIC(sc)) { 813 CSR_WRITE_4(sc, DC_PN_MII, DC_PN_MIIOPCODE_READ | 814 (phy << 23) | (reg << 18)); 815 for (i = 0; i < DC_TIMEOUT; i++) { 816 DELAY(1); 817 rval = CSR_READ_4(sc, DC_PN_MII); 818 if (!(rval & DC_PN_MII_BUSY)) { 819 rval &= 0xFFFF; 820 return (rval == 0xFFFF ? 0 : rval); 821 } 822 } 823 return (0); 824 } 825 826 if (DC_IS_COMET(sc)) { 827 switch (reg) { 828 case MII_BMCR: 829 phy_reg = DC_AL_BMCR; 830 break; 831 case MII_BMSR: 832 phy_reg = DC_AL_BMSR; 833 break; 834 case MII_PHYIDR1: 835 phy_reg = DC_AL_VENID; 836 break; 837 case MII_PHYIDR2: 838 phy_reg = DC_AL_DEVID; 839 break; 840 case MII_ANAR: 841 phy_reg = DC_AL_ANAR; 842 break; 843 case MII_ANLPAR: 844 phy_reg = DC_AL_LPAR; 845 break; 846 case MII_ANER: 847 phy_reg = DC_AL_ANER; 848 break; 849 default: 850 printf("dc%d: phy_read: bad phy register %x\n", 851 sc->dc_unit, reg); 852 return (0); 853 break; 854 } 855 856 rval = CSR_READ_4(sc, phy_reg) & 0x0000FFFF; 857 858 if (rval == 0xFFFF) 859 return (0); 860 return (rval); 861 } 862 863 frame.mii_phyaddr = phy; 864 frame.mii_regaddr = reg; 865 if (sc->dc_type == DC_TYPE_98713) { 866 phy_reg = CSR_READ_4(sc, DC_NETCFG); 867 CSR_WRITE_4(sc, DC_NETCFG, phy_reg & ~DC_NETCFG_PORTSEL); 868 } 869 dc_mii_readreg(sc, &frame); 870 if (sc->dc_type == DC_TYPE_98713) 871 CSR_WRITE_4(sc, DC_NETCFG, phy_reg); 872 873 return (frame.mii_data); 874 } 875 876 static int 877 dc_miibus_writereg(device_t dev, int phy, int reg, int data) 878 { 879 struct dc_softc *sc; 880 struct dc_mii_frame frame; 881 int i, phy_reg = 0; 882 883 sc = device_get_softc(dev); 884 bzero(&frame, sizeof(frame)); 885 886 if (DC_IS_ADMTEK(sc) && phy != DC_ADMTEK_PHYADDR) 887 return (0); 888 889 if (DC_IS_CONEXANT(sc) && phy != DC_CONEXANT_PHYADDR) 890 return (0); 891 892 if (DC_IS_PNIC(sc)) { 893 CSR_WRITE_4(sc, DC_PN_MII, DC_PN_MIIOPCODE_WRITE | 894 (phy << 23) | (reg << 10) | data); 895 for (i = 0; i < DC_TIMEOUT; i++) { 896 if (!(CSR_READ_4(sc, DC_PN_MII) & DC_PN_MII_BUSY)) 897 break; 898 } 899 return (0); 900 } 901 902 if (DC_IS_COMET(sc)) { 903 switch (reg) { 904 case MII_BMCR: 905 phy_reg = DC_AL_BMCR; 906 break; 907 case MII_BMSR: 908 phy_reg = DC_AL_BMSR; 909 break; 910 case MII_PHYIDR1: 911 phy_reg = DC_AL_VENID; 912 break; 913 case MII_PHYIDR2: 914 phy_reg = DC_AL_DEVID; 915 break; 916 case MII_ANAR: 917 phy_reg = DC_AL_ANAR; 918 break; 919 case MII_ANLPAR: 920 phy_reg = DC_AL_LPAR; 921 break; 922 case MII_ANER: 923 phy_reg = DC_AL_ANER; 924 break; 925 default: 926 printf("dc%d: phy_write: bad phy register %x\n", 927 sc->dc_unit, reg); 928 return (0); 929 break; 930 } 931 932 CSR_WRITE_4(sc, phy_reg, data); 933 return (0); 934 } 935 936 frame.mii_phyaddr = phy; 937 frame.mii_regaddr = reg; 938 frame.mii_data = data; 939 940 if (sc->dc_type == DC_TYPE_98713) { 941 phy_reg = CSR_READ_4(sc, DC_NETCFG); 942 CSR_WRITE_4(sc, DC_NETCFG, phy_reg & ~DC_NETCFG_PORTSEL); 943 } 944 dc_mii_writereg(sc, &frame); 945 if (sc->dc_type == DC_TYPE_98713) 946 CSR_WRITE_4(sc, DC_NETCFG, phy_reg); 947 948 return (0); 949 } 950 951 static void 952 dc_miibus_statchg(device_t dev) 953 { 954 struct dc_softc *sc; 955 struct mii_data *mii; 956 struct ifmedia *ifm; 957 958 sc = device_get_softc(dev); 959 if (DC_IS_ADMTEK(sc)) 960 return; 961 962 mii = device_get_softc(sc->dc_miibus); 963 ifm = &mii->mii_media; 964 if (DC_IS_DAVICOM(sc) && 965 IFM_SUBTYPE(ifm->ifm_media) == IFM_HPNA_1) { 966 dc_setcfg(sc, ifm->ifm_media); 967 sc->dc_if_media = ifm->ifm_media; 968 } else { 969 dc_setcfg(sc, mii->mii_media_active); 970 sc->dc_if_media = mii->mii_media_active; 971 } 972 } 973 974 /* 975 * Special support for DM9102A cards with HomePNA PHYs. Note: 976 * with the Davicom DM9102A/DM9801 eval board that I have, it seems 977 * to be impossible to talk to the management interface of the DM9801 978 * PHY (its MDIO pin is not connected to anything). Consequently, 979 * the driver has to just 'know' about the additional mode and deal 980 * with it itself. *sigh* 981 */ 982 static void 983 dc_miibus_mediainit(device_t dev) 984 { 985 struct dc_softc *sc; 986 struct mii_data *mii; 987 struct ifmedia *ifm; 988 int rev; 989 990 rev = pci_read_config(dev, DC_PCI_CFRV, 4) & 0xFF; 991 992 sc = device_get_softc(dev); 993 mii = device_get_softc(sc->dc_miibus); 994 ifm = &mii->mii_media; 995 996 if (DC_IS_DAVICOM(sc) && rev >= DC_REVISION_DM9102A) 997 ifmedia_add(ifm, IFM_ETHER | IFM_HPNA_1, 0, NULL); 998 } 999 1000 #define DC_POLY 0xEDB88320 1001 #define DC_BITS_512 9 1002 #define DC_BITS_128 7 1003 #define DC_BITS_64 6 1004 1005 static u_int32_t 1006 dc_crc_le(struct dc_softc *sc, caddr_t addr) 1007 { 1008 u_int32_t idx, bit, data, crc; 1009 1010 /* Compute CRC for the address value. */ 1011 crc = 0xFFFFFFFF; /* initial value */ 1012 1013 for (idx = 0; idx < 6; idx++) { 1014 for (data = *addr++, bit = 0; bit < 8; bit++, data >>= 1) 1015 crc = (crc >> 1) ^ (((crc ^ data) & 1) ? DC_POLY : 0); 1016 } 1017 1018 /* 1019 * The hash table on the PNIC II and the MX98715AEC-C/D/E 1020 * chips is only 128 bits wide. 1021 */ 1022 if (sc->dc_flags & DC_128BIT_HASH) 1023 return (crc & ((1 << DC_BITS_128) - 1)); 1024 1025 /* The hash table on the MX98715BEC is only 64 bits wide. */ 1026 if (sc->dc_flags & DC_64BIT_HASH) 1027 return (crc & ((1 << DC_BITS_64) - 1)); 1028 1029 /* Xircom's hash filtering table is different (read: weird) */ 1030 /* Xircom uses the LEAST significant bits */ 1031 if (DC_IS_XIRCOM(sc)) { 1032 if ((crc & 0x180) == 0x180) 1033 return ((crc & 0x0F) + (crc & 0x70) * 3 + (14 << 4)); 1034 else 1035 return ((crc & 0x1F) + ((crc >> 1) & 0xF0) * 3 + 1036 (12 << 4)); 1037 } 1038 1039 return (crc & ((1 << DC_BITS_512) - 1)); 1040 } 1041 1042 /* 1043 * Calculate CRC of a multicast group address, return the lower 6 bits. 1044 */ 1045 static u_int32_t 1046 dc_crc_be(caddr_t addr) 1047 { 1048 u_int32_t crc, carry; 1049 int i, j; 1050 u_int8_t c; 1051 1052 /* Compute CRC for the address value. */ 1053 crc = 0xFFFFFFFF; /* initial value */ 1054 1055 for (i = 0; i < 6; i++) { 1056 c = *(addr + i); 1057 for (j = 0; j < 8; j++) { 1058 carry = ((crc & 0x80000000) ? 1 : 0) ^ (c & 0x01); 1059 crc <<= 1; 1060 c >>= 1; 1061 if (carry) 1062 crc = (crc ^ 0x04c11db6) | carry; 1063 } 1064 } 1065 1066 /* Return the filter bit position. */ 1067 return ((crc >> 26) & 0x0000003F); 1068 } 1069 1070 /* 1071 * 21143-style RX filter setup routine. Filter programming is done by 1072 * downloading a special setup frame into the TX engine. 21143, Macronix, 1073 * PNIC, PNIC II and Davicom chips are programmed this way. 1074 * 1075 * We always program the chip using 'hash perfect' mode, i.e. one perfect 1076 * address (our node address) and a 512-bit hash filter for multicast 1077 * frames. We also sneak the broadcast address into the hash filter since 1078 * we need that too. 1079 */ 1080 static void 1081 dc_setfilt_21143(struct dc_softc *sc) 1082 { 1083 struct dc_desc *sframe; 1084 u_int32_t h, *sp; 1085 struct ifmultiaddr *ifma; 1086 struct ifnet *ifp; 1087 int i; 1088 1089 ifp = &sc->arpcom.ac_if; 1090 1091 i = sc->dc_cdata.dc_tx_prod; 1092 DC_INC(sc->dc_cdata.dc_tx_prod, DC_TX_LIST_CNT); 1093 sc->dc_cdata.dc_tx_cnt++; 1094 sframe = &sc->dc_ldata->dc_tx_list[i]; 1095 sp = (u_int32_t *)&sc->dc_cdata.dc_sbuf; 1096 bzero(sp, DC_SFRAME_LEN); 1097 1098 sframe->dc_data = vtophys(&sc->dc_cdata.dc_sbuf); 1099 sframe->dc_ctl = DC_SFRAME_LEN | DC_TXCTL_SETUP | DC_TXCTL_TLINK | 1100 DC_FILTER_HASHPERF | DC_TXCTL_FINT; 1101 1102 sc->dc_cdata.dc_tx_chain[i] = (struct mbuf *)&sc->dc_cdata.dc_sbuf; 1103 1104 /* If we want promiscuous mode, set the allframes bit. */ 1105 if (ifp->if_flags & IFF_PROMISC) 1106 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC); 1107 else 1108 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC); 1109 1110 if (ifp->if_flags & IFF_ALLMULTI) 1111 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI); 1112 else 1113 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI); 1114 1115 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 1116 if (ifma->ifma_addr->sa_family != AF_LINK) 1117 continue; 1118 h = dc_crc_le(sc, 1119 LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 1120 sp[h >> 4] |= 1 << (h & 0xF); 1121 } 1122 1123 if (ifp->if_flags & IFF_BROADCAST) { 1124 h = dc_crc_le(sc, (caddr_t)ifp->if_broadcastaddr); 1125 sp[h >> 4] |= 1 << (h & 0xF); 1126 } 1127 1128 /* Set our MAC address */ 1129 sp[39] = ((u_int16_t *)sc->arpcom.ac_enaddr)[0]; 1130 sp[40] = ((u_int16_t *)sc->arpcom.ac_enaddr)[1]; 1131 sp[41] = ((u_int16_t *)sc->arpcom.ac_enaddr)[2]; 1132 1133 sframe->dc_status = DC_TXSTAT_OWN; 1134 CSR_WRITE_4(sc, DC_TXSTART, 0xFFFFFFFF); 1135 1136 /* 1137 * The PNIC takes an exceedingly long time to process its 1138 * setup frame; wait 10ms after posting the setup frame 1139 * before proceeding, just so it has time to swallow its 1140 * medicine. 1141 */ 1142 DELAY(10000); 1143 1144 ifp->if_timer = 5; 1145 } 1146 1147 static void 1148 dc_setfilt_admtek(struct dc_softc *sc) 1149 { 1150 struct ifnet *ifp; 1151 struct ifmultiaddr *ifma; 1152 int h = 0; 1153 u_int32_t hashes[2] = { 0, 0 }; 1154 1155 ifp = &sc->arpcom.ac_if; 1156 1157 /* Init our MAC address. */ 1158 CSR_WRITE_4(sc, DC_AL_PAR0, *(u_int32_t *)(&sc->arpcom.ac_enaddr[0])); 1159 CSR_WRITE_4(sc, DC_AL_PAR1, *(u_int32_t *)(&sc->arpcom.ac_enaddr[4])); 1160 1161 /* If we want promiscuous mode, set the allframes bit. */ 1162 if (ifp->if_flags & IFF_PROMISC) 1163 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC); 1164 else 1165 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC); 1166 1167 if (ifp->if_flags & IFF_ALLMULTI) 1168 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI); 1169 else 1170 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI); 1171 1172 /* First, zot all the existing hash bits. */ 1173 CSR_WRITE_4(sc, DC_AL_MAR0, 0); 1174 CSR_WRITE_4(sc, DC_AL_MAR1, 0); 1175 1176 /* 1177 * If we're already in promisc or allmulti mode, we 1178 * don't have to bother programming the multicast filter. 1179 */ 1180 if (ifp->if_flags & (IFF_PROMISC | IFF_ALLMULTI)) 1181 return; 1182 1183 /* Now program new ones. */ 1184 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 1185 if (ifma->ifma_addr->sa_family != AF_LINK) 1186 continue; 1187 if (DC_IS_CENTAUR(sc)) 1188 h = dc_crc_le(sc, LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 1189 else 1190 h = dc_crc_be(LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 1191 if (h < 32) 1192 hashes[0] |= (1 << h); 1193 else 1194 hashes[1] |= (1 << (h - 32)); 1195 } 1196 1197 CSR_WRITE_4(sc, DC_AL_MAR0, hashes[0]); 1198 CSR_WRITE_4(sc, DC_AL_MAR1, hashes[1]); 1199 } 1200 1201 static void 1202 dc_setfilt_asix(struct dc_softc *sc) 1203 { 1204 struct ifnet *ifp; 1205 struct ifmultiaddr *ifma; 1206 int h = 0; 1207 u_int32_t hashes[2] = { 0, 0 }; 1208 1209 ifp = &sc->arpcom.ac_if; 1210 1211 /* Init our MAC address */ 1212 CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_PAR0); 1213 CSR_WRITE_4(sc, DC_AX_FILTDATA, 1214 *(u_int32_t *)(&sc->arpcom.ac_enaddr[0])); 1215 CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_PAR1); 1216 CSR_WRITE_4(sc, DC_AX_FILTDATA, 1217 *(u_int32_t *)(&sc->arpcom.ac_enaddr[4])); 1218 1219 /* If we want promiscuous mode, set the allframes bit. */ 1220 if (ifp->if_flags & IFF_PROMISC) 1221 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC); 1222 else 1223 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC); 1224 1225 if (ifp->if_flags & IFF_ALLMULTI) 1226 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI); 1227 else 1228 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI); 1229 1230 /* 1231 * The ASIX chip has a special bit to enable reception 1232 * of broadcast frames. 1233 */ 1234 if (ifp->if_flags & IFF_BROADCAST) 1235 DC_SETBIT(sc, DC_NETCFG, DC_AX_NETCFG_RX_BROAD); 1236 else 1237 DC_CLRBIT(sc, DC_NETCFG, DC_AX_NETCFG_RX_BROAD); 1238 1239 /* first, zot all the existing hash bits */ 1240 CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_MAR0); 1241 CSR_WRITE_4(sc, DC_AX_FILTDATA, 0); 1242 CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_MAR1); 1243 CSR_WRITE_4(sc, DC_AX_FILTDATA, 0); 1244 1245 /* 1246 * If we're already in promisc or allmulti mode, we 1247 * don't have to bother programming the multicast filter. 1248 */ 1249 if (ifp->if_flags & (IFF_PROMISC | IFF_ALLMULTI)) 1250 return; 1251 1252 /* now program new ones */ 1253 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 1254 if (ifma->ifma_addr->sa_family != AF_LINK) 1255 continue; 1256 h = dc_crc_be(LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 1257 if (h < 32) 1258 hashes[0] |= (1 << h); 1259 else 1260 hashes[1] |= (1 << (h - 32)); 1261 } 1262 1263 CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_MAR0); 1264 CSR_WRITE_4(sc, DC_AX_FILTDATA, hashes[0]); 1265 CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_MAR1); 1266 CSR_WRITE_4(sc, DC_AX_FILTDATA, hashes[1]); 1267 } 1268 1269 static void 1270 dc_setfilt_xircom(struct dc_softc *sc) 1271 { 1272 struct ifnet *ifp; 1273 struct ifmultiaddr *ifma; 1274 struct dc_desc *sframe; 1275 u_int32_t h, *sp; 1276 int i; 1277 1278 ifp = &sc->arpcom.ac_if; 1279 DC_CLRBIT(sc, DC_NETCFG, (DC_NETCFG_TX_ON | DC_NETCFG_RX_ON)); 1280 1281 i = sc->dc_cdata.dc_tx_prod; 1282 DC_INC(sc->dc_cdata.dc_tx_prod, DC_TX_LIST_CNT); 1283 sc->dc_cdata.dc_tx_cnt++; 1284 sframe = &sc->dc_ldata->dc_tx_list[i]; 1285 sp = (u_int32_t *)&sc->dc_cdata.dc_sbuf; 1286 bzero(sp, DC_SFRAME_LEN); 1287 1288 sframe->dc_data = vtophys(&sc->dc_cdata.dc_sbuf); 1289 sframe->dc_ctl = DC_SFRAME_LEN | DC_TXCTL_SETUP | DC_TXCTL_TLINK | 1290 DC_FILTER_HASHPERF | DC_TXCTL_FINT; 1291 1292 sc->dc_cdata.dc_tx_chain[i] = (struct mbuf *)&sc->dc_cdata.dc_sbuf; 1293 1294 /* If we want promiscuous mode, set the allframes bit. */ 1295 if (ifp->if_flags & IFF_PROMISC) 1296 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC); 1297 else 1298 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC); 1299 1300 if (ifp->if_flags & IFF_ALLMULTI) 1301 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI); 1302 else 1303 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI); 1304 1305 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 1306 if (ifma->ifma_addr->sa_family != AF_LINK) 1307 continue; 1308 h = dc_crc_le(sc, 1309 LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 1310 sp[h >> 4] |= 1 << (h & 0xF); 1311 } 1312 1313 if (ifp->if_flags & IFF_BROADCAST) { 1314 h = dc_crc_le(sc, (caddr_t)ifp->if_broadcastaddr); 1315 sp[h >> 4] |= 1 << (h & 0xF); 1316 } 1317 1318 /* Set our MAC address */ 1319 sp[0] = ((u_int16_t *)sc->arpcom.ac_enaddr)[0]; 1320 sp[1] = ((u_int16_t *)sc->arpcom.ac_enaddr)[1]; 1321 sp[2] = ((u_int16_t *)sc->arpcom.ac_enaddr)[2]; 1322 1323 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_TX_ON); 1324 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_ON); 1325 ifp->if_flags |= IFF_RUNNING; 1326 sframe->dc_status = DC_TXSTAT_OWN; 1327 CSR_WRITE_4(sc, DC_TXSTART, 0xFFFFFFFF); 1328 1329 /* 1330 * Wait some time... 1331 */ 1332 DELAY(1000); 1333 1334 ifp->if_timer = 5; 1335 } 1336 1337 static void 1338 dc_setfilt(struct dc_softc *sc) 1339 { 1340 1341 if (DC_IS_INTEL(sc) || DC_IS_MACRONIX(sc) || DC_IS_PNIC(sc) || 1342 DC_IS_PNICII(sc) || DC_IS_DAVICOM(sc) || DC_IS_CONEXANT(sc)) 1343 dc_setfilt_21143(sc); 1344 1345 if (DC_IS_ASIX(sc)) 1346 dc_setfilt_asix(sc); 1347 1348 if (DC_IS_ADMTEK(sc)) 1349 dc_setfilt_admtek(sc); 1350 1351 if (DC_IS_XIRCOM(sc)) 1352 dc_setfilt_xircom(sc); 1353 } 1354 1355 /* 1356 * In order to fiddle with the 'full-duplex' and '100Mbps' bits in 1357 * the netconfig register, we first have to put the transmit and/or 1358 * receive logic in the idle state. 1359 */ 1360 static void 1361 dc_setcfg(struct dc_softc *sc, int media) 1362 { 1363 int i, restart = 0, watchdogreg; 1364 u_int32_t isr; 1365 1366 if (IFM_SUBTYPE(media) == IFM_NONE) 1367 return; 1368 1369 if (CSR_READ_4(sc, DC_NETCFG) & (DC_NETCFG_TX_ON | DC_NETCFG_RX_ON)) { 1370 restart = 1; 1371 DC_CLRBIT(sc, DC_NETCFG, (DC_NETCFG_TX_ON | DC_NETCFG_RX_ON)); 1372 1373 for (i = 0; i < DC_TIMEOUT; i++) { 1374 isr = CSR_READ_4(sc, DC_ISR); 1375 if (isr & DC_ISR_TX_IDLE && 1376 ((isr & DC_ISR_RX_STATE) == DC_RXSTATE_STOPPED || 1377 (isr & DC_ISR_RX_STATE) == DC_RXSTATE_WAIT)) 1378 break; 1379 DELAY(10); 1380 } 1381 1382 if (i == DC_TIMEOUT) 1383 printf("dc%d: failed to force tx and " 1384 "rx to idle state\n", sc->dc_unit); 1385 } 1386 1387 if (IFM_SUBTYPE(media) == IFM_100_TX) { 1388 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_SPEEDSEL); 1389 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_HEARTBEAT); 1390 if (sc->dc_pmode == DC_PMODE_MII) { 1391 if (DC_IS_INTEL(sc)) { 1392 /* There's a write enable bit here that reads as 1. */ 1393 watchdogreg = CSR_READ_4(sc, DC_WATCHDOG); 1394 watchdogreg &= ~DC_WDOG_CTLWREN; 1395 watchdogreg |= DC_WDOG_JABBERDIS; 1396 CSR_WRITE_4(sc, DC_WATCHDOG, watchdogreg); 1397 } else { 1398 DC_SETBIT(sc, DC_WATCHDOG, DC_WDOG_JABBERDIS); 1399 } 1400 DC_CLRBIT(sc, DC_NETCFG, (DC_NETCFG_PCS | 1401 DC_NETCFG_PORTSEL | DC_NETCFG_SCRAMBLER)); 1402 if (sc->dc_type == DC_TYPE_98713) 1403 DC_SETBIT(sc, DC_NETCFG, (DC_NETCFG_PCS | 1404 DC_NETCFG_SCRAMBLER)); 1405 if (!DC_IS_DAVICOM(sc)) 1406 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL); 1407 DC_CLRBIT(sc, DC_10BTCTRL, 0xFFFF); 1408 if (DC_IS_INTEL(sc)) 1409 dc_apply_fixup(sc, IFM_AUTO); 1410 } else { 1411 if (DC_IS_PNIC(sc)) { 1412 DC_PN_GPIO_SETBIT(sc, DC_PN_GPIO_SPEEDSEL); 1413 DC_PN_GPIO_SETBIT(sc, DC_PN_GPIO_100TX_LOOP); 1414 DC_SETBIT(sc, DC_PN_NWAY, DC_PN_NWAY_SPEEDSEL); 1415 } 1416 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL); 1417 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PCS); 1418 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_SCRAMBLER); 1419 if (DC_IS_INTEL(sc)) 1420 dc_apply_fixup(sc, 1421 (media & IFM_GMASK) == IFM_FDX ? 1422 IFM_100_TX | IFM_FDX : IFM_100_TX); 1423 } 1424 } 1425 1426 if (IFM_SUBTYPE(media) == IFM_10_T) { 1427 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_SPEEDSEL); 1428 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_HEARTBEAT); 1429 if (sc->dc_pmode == DC_PMODE_MII) { 1430 /* There's a write enable bit here that reads as 1. */ 1431 if (DC_IS_INTEL(sc)) { 1432 watchdogreg = CSR_READ_4(sc, DC_WATCHDOG); 1433 watchdogreg &= ~DC_WDOG_CTLWREN; 1434 watchdogreg |= DC_WDOG_JABBERDIS; 1435 CSR_WRITE_4(sc, DC_WATCHDOG, watchdogreg); 1436 } else { 1437 DC_SETBIT(sc, DC_WATCHDOG, DC_WDOG_JABBERDIS); 1438 } 1439 DC_CLRBIT(sc, DC_NETCFG, (DC_NETCFG_PCS | 1440 DC_NETCFG_PORTSEL | DC_NETCFG_SCRAMBLER)); 1441 if (sc->dc_type == DC_TYPE_98713) 1442 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PCS); 1443 if (!DC_IS_DAVICOM(sc)) 1444 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL); 1445 DC_CLRBIT(sc, DC_10BTCTRL, 0xFFFF); 1446 if (DC_IS_INTEL(sc)) 1447 dc_apply_fixup(sc, IFM_AUTO); 1448 } else { 1449 if (DC_IS_PNIC(sc)) { 1450 DC_PN_GPIO_CLRBIT(sc, DC_PN_GPIO_SPEEDSEL); 1451 DC_PN_GPIO_SETBIT(sc, DC_PN_GPIO_100TX_LOOP); 1452 DC_CLRBIT(sc, DC_PN_NWAY, DC_PN_NWAY_SPEEDSEL); 1453 } 1454 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL); 1455 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_PCS); 1456 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_SCRAMBLER); 1457 if (DC_IS_INTEL(sc)) { 1458 DC_CLRBIT(sc, DC_SIARESET, DC_SIA_RESET); 1459 DC_CLRBIT(sc, DC_10BTCTRL, 0xFFFF); 1460 if ((media & IFM_GMASK) == IFM_FDX) 1461 DC_SETBIT(sc, DC_10BTCTRL, 0x7F3D); 1462 else 1463 DC_SETBIT(sc, DC_10BTCTRL, 0x7F3F); 1464 DC_SETBIT(sc, DC_SIARESET, DC_SIA_RESET); 1465 DC_CLRBIT(sc, DC_10BTCTRL, 1466 DC_TCTL_AUTONEGENBL); 1467 dc_apply_fixup(sc, 1468 (media & IFM_GMASK) == IFM_FDX ? 1469 IFM_10_T | IFM_FDX : IFM_10_T); 1470 DELAY(20000); 1471 } 1472 } 1473 } 1474 1475 /* 1476 * If this is a Davicom DM9102A card with a DM9801 HomePNA 1477 * PHY and we want HomePNA mode, set the portsel bit to turn 1478 * on the external MII port. 1479 */ 1480 if (DC_IS_DAVICOM(sc)) { 1481 if (IFM_SUBTYPE(media) == IFM_HPNA_1) { 1482 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL); 1483 sc->dc_link = 1; 1484 } else { 1485 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL); 1486 } 1487 } 1488 1489 if ((media & IFM_GMASK) == IFM_FDX) { 1490 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_FULLDUPLEX); 1491 if (sc->dc_pmode == DC_PMODE_SYM && DC_IS_PNIC(sc)) 1492 DC_SETBIT(sc, DC_PN_NWAY, DC_PN_NWAY_DUPLEX); 1493 } else { 1494 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_FULLDUPLEX); 1495 if (sc->dc_pmode == DC_PMODE_SYM && DC_IS_PNIC(sc)) 1496 DC_CLRBIT(sc, DC_PN_NWAY, DC_PN_NWAY_DUPLEX); 1497 } 1498 1499 if (restart) 1500 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_TX_ON | DC_NETCFG_RX_ON); 1501 } 1502 1503 static void 1504 dc_reset(struct dc_softc *sc) 1505 { 1506 int i; 1507 1508 DC_SETBIT(sc, DC_BUSCTL, DC_BUSCTL_RESET); 1509 1510 for (i = 0; i < DC_TIMEOUT; i++) { 1511 DELAY(10); 1512 if (!(CSR_READ_4(sc, DC_BUSCTL) & DC_BUSCTL_RESET)) 1513 break; 1514 } 1515 1516 if (DC_IS_ASIX(sc) || DC_IS_ADMTEK(sc) || DC_IS_CONEXANT(sc) || 1517 DC_IS_XIRCOM(sc) || DC_IS_INTEL(sc)) { 1518 DELAY(10000); 1519 DC_CLRBIT(sc, DC_BUSCTL, DC_BUSCTL_RESET); 1520 i = 0; 1521 } 1522 1523 if (i == DC_TIMEOUT) 1524 printf("dc%d: reset never completed!\n", sc->dc_unit); 1525 1526 /* Wait a little while for the chip to get its brains in order. */ 1527 DELAY(1000); 1528 1529 CSR_WRITE_4(sc, DC_IMR, 0x00000000); 1530 CSR_WRITE_4(sc, DC_BUSCTL, 0x00000000); 1531 CSR_WRITE_4(sc, DC_NETCFG, 0x00000000); 1532 1533 /* 1534 * Bring the SIA out of reset. In some cases, it looks 1535 * like failing to unreset the SIA soon enough gets it 1536 * into a state where it will never come out of reset 1537 * until we reset the whole chip again. 1538 */ 1539 if (DC_IS_INTEL(sc)) { 1540 DC_SETBIT(sc, DC_SIARESET, DC_SIA_RESET); 1541 CSR_WRITE_4(sc, DC_10BTCTRL, 0); 1542 CSR_WRITE_4(sc, DC_WATCHDOG, 0); 1543 } 1544 } 1545 1546 static struct dc_type * 1547 dc_devtype(device_t dev) 1548 { 1549 struct dc_type *t; 1550 u_int32_t rev; 1551 1552 t = dc_devs; 1553 1554 while (t->dc_name != NULL) { 1555 if ((pci_get_vendor(dev) == t->dc_vid) && 1556 (pci_get_device(dev) == t->dc_did)) { 1557 /* Check the PCI revision */ 1558 rev = pci_read_config(dev, DC_PCI_CFRV, 4) & 0xFF; 1559 if (t->dc_did == DC_DEVICEID_98713 && 1560 rev >= DC_REVISION_98713A) 1561 t++; 1562 if (t->dc_did == DC_DEVICEID_98713_CP && 1563 rev >= DC_REVISION_98713A) 1564 t++; 1565 if (t->dc_did == DC_DEVICEID_987x5 && 1566 rev >= DC_REVISION_98715AEC_C) 1567 t++; 1568 if (t->dc_did == DC_DEVICEID_987x5 && 1569 rev >= DC_REVISION_98725) 1570 t++; 1571 if (t->dc_did == DC_DEVICEID_AX88140A && 1572 rev >= DC_REVISION_88141) 1573 t++; 1574 if (t->dc_did == DC_DEVICEID_82C168 && 1575 rev >= DC_REVISION_82C169) 1576 t++; 1577 if (t->dc_did == DC_DEVICEID_DM9102 && 1578 rev >= DC_REVISION_DM9102A) 1579 t++; 1580 return (t); 1581 } 1582 t++; 1583 } 1584 1585 return (NULL); 1586 } 1587 1588 /* 1589 * Probe for a 21143 or clone chip. Check the PCI vendor and device 1590 * IDs against our list and return a device name if we find a match. 1591 * We do a little bit of extra work to identify the exact type of 1592 * chip. The MX98713 and MX98713A have the same PCI vendor/device ID, 1593 * but different revision IDs. The same is true for 98715/98715A 1594 * chips and the 98725, as well as the ASIX and ADMtek chips. In some 1595 * cases, the exact chip revision affects driver behavior. 1596 */ 1597 static int 1598 dc_probe(device_t dev) 1599 { 1600 struct dc_type *t; 1601 1602 t = dc_devtype(dev); 1603 1604 if (t != NULL) { 1605 device_set_desc(dev, t->dc_name); 1606 return (0); 1607 } 1608 1609 return (ENXIO); 1610 } 1611 1612 static void 1613 dc_acpi(device_t dev) 1614 { 1615 int unit; 1616 u_int32_t iobase, membase, irq; 1617 1618 unit = device_get_unit(dev); 1619 1620 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) { 1621 /* Save important PCI config data. */ 1622 iobase = pci_read_config(dev, DC_PCI_CFBIO, 4); 1623 membase = pci_read_config(dev, DC_PCI_CFBMA, 4); 1624 irq = pci_read_config(dev, DC_PCI_CFIT, 4); 1625 1626 /* Reset the power state. */ 1627 printf("dc%d: chip is in D%d power mode " 1628 "-- setting to D0\n", unit, 1629 pci_get_powerstate(dev)); 1630 pci_set_powerstate(dev, PCI_POWERSTATE_D0); 1631 1632 /* Restore PCI config data. */ 1633 pci_write_config(dev, DC_PCI_CFBIO, iobase, 4); 1634 pci_write_config(dev, DC_PCI_CFBMA, membase, 4); 1635 pci_write_config(dev, DC_PCI_CFIT, irq, 4); 1636 } 1637 } 1638 1639 static void 1640 dc_apply_fixup(struct dc_softc *sc, int media) 1641 { 1642 struct dc_mediainfo *m; 1643 u_int8_t *p; 1644 int i; 1645 u_int32_t reg; 1646 1647 m = sc->dc_mi; 1648 1649 while (m != NULL) { 1650 if (m->dc_media == media) 1651 break; 1652 m = m->dc_next; 1653 } 1654 1655 if (m == NULL) 1656 return; 1657 1658 for (i = 0, p = m->dc_reset_ptr; i < m->dc_reset_len; i++, p += 2) { 1659 reg = (p[0] | (p[1] << 8)) << 16; 1660 CSR_WRITE_4(sc, DC_WATCHDOG, reg); 1661 } 1662 1663 for (i = 0, p = m->dc_gp_ptr; i < m->dc_gp_len; i++, p += 2) { 1664 reg = (p[0] | (p[1] << 8)) << 16; 1665 CSR_WRITE_4(sc, DC_WATCHDOG, reg); 1666 } 1667 } 1668 1669 static void 1670 dc_decode_leaf_sia(struct dc_softc *sc, struct dc_eblock_sia *l) 1671 { 1672 struct dc_mediainfo *m; 1673 1674 m = malloc(sizeof(struct dc_mediainfo), M_DEVBUF, M_NOWAIT | M_ZERO); 1675 if (l->dc_sia_code == DC_SIA_CODE_10BT) 1676 m->dc_media = IFM_10_T; 1677 1678 if (l->dc_sia_code == DC_SIA_CODE_10BT_FDX) 1679 m->dc_media = IFM_10_T | IFM_FDX; 1680 1681 if (l->dc_sia_code == DC_SIA_CODE_10B2) 1682 m->dc_media = IFM_10_2; 1683 1684 if (l->dc_sia_code == DC_SIA_CODE_10B5) 1685 m->dc_media = IFM_10_5; 1686 1687 m->dc_gp_len = 2; 1688 m->dc_gp_ptr = (u_int8_t *)&l->dc_sia_gpio_ctl; 1689 1690 m->dc_next = sc->dc_mi; 1691 sc->dc_mi = m; 1692 1693 sc->dc_pmode = DC_PMODE_SIA; 1694 } 1695 1696 static void 1697 dc_decode_leaf_sym(struct dc_softc *sc, struct dc_eblock_sym *l) 1698 { 1699 struct dc_mediainfo *m; 1700 1701 m = malloc(sizeof(struct dc_mediainfo), M_DEVBUF, M_NOWAIT | M_ZERO); 1702 if (l->dc_sym_code == DC_SYM_CODE_100BT) 1703 m->dc_media = IFM_100_TX; 1704 1705 if (l->dc_sym_code == DC_SYM_CODE_100BT_FDX) 1706 m->dc_media = IFM_100_TX | IFM_FDX; 1707 1708 m->dc_gp_len = 2; 1709 m->dc_gp_ptr = (u_int8_t *)&l->dc_sym_gpio_ctl; 1710 1711 m->dc_next = sc->dc_mi; 1712 sc->dc_mi = m; 1713 1714 sc->dc_pmode = DC_PMODE_SYM; 1715 } 1716 1717 static void 1718 dc_decode_leaf_mii(struct dc_softc *sc, struct dc_eblock_mii *l) 1719 { 1720 struct dc_mediainfo *m; 1721 u_int8_t *p; 1722 1723 m = malloc(sizeof(struct dc_mediainfo), M_DEVBUF, M_NOWAIT | M_ZERO); 1724 /* We abuse IFM_AUTO to represent MII. */ 1725 m->dc_media = IFM_AUTO; 1726 m->dc_gp_len = l->dc_gpr_len; 1727 1728 p = (u_int8_t *)l; 1729 p += sizeof(struct dc_eblock_mii); 1730 m->dc_gp_ptr = p; 1731 p += 2 * l->dc_gpr_len; 1732 m->dc_reset_len = *p; 1733 p++; 1734 m->dc_reset_ptr = p; 1735 1736 m->dc_next = sc->dc_mi; 1737 sc->dc_mi = m; 1738 } 1739 1740 static void 1741 dc_read_srom(struct dc_softc *sc, int bits) 1742 { 1743 int size; 1744 1745 size = 2 << bits; 1746 sc->dc_srom = malloc(size, M_DEVBUF, M_NOWAIT); 1747 dc_read_eeprom(sc, (caddr_t)sc->dc_srom, 0, (size / 2), 0); 1748 } 1749 1750 static void 1751 dc_parse_21143_srom(struct dc_softc *sc) 1752 { 1753 struct dc_leaf_hdr *lhdr; 1754 struct dc_eblock_hdr *hdr; 1755 int have_mii, i, loff; 1756 char *ptr; 1757 1758 have_mii = 0; 1759 loff = sc->dc_srom[27]; 1760 lhdr = (struct dc_leaf_hdr *)&(sc->dc_srom[loff]); 1761 1762 ptr = (char *)lhdr; 1763 ptr += sizeof(struct dc_leaf_hdr) - 1; 1764 /* 1765 * Look if we got a MII media block. 1766 */ 1767 for (i = 0; i < lhdr->dc_mcnt; i++) { 1768 hdr = (struct dc_eblock_hdr *)ptr; 1769 if (hdr->dc_type == DC_EBLOCK_MII) 1770 have_mii++; 1771 1772 ptr += (hdr->dc_len & 0x7F); 1773 ptr++; 1774 } 1775 1776 /* 1777 * Do the same thing again. Only use SIA and SYM media 1778 * blocks if no MII media block is available. 1779 */ 1780 ptr = (char *)lhdr; 1781 ptr += sizeof(struct dc_leaf_hdr) - 1; 1782 for (i = 0; i < lhdr->dc_mcnt; i++) { 1783 hdr = (struct dc_eblock_hdr *)ptr; 1784 switch (hdr->dc_type) { 1785 case DC_EBLOCK_MII: 1786 dc_decode_leaf_mii(sc, (struct dc_eblock_mii *)hdr); 1787 break; 1788 case DC_EBLOCK_SIA: 1789 if (! have_mii) 1790 dc_decode_leaf_sia(sc, 1791 (struct dc_eblock_sia *)hdr); 1792 break; 1793 case DC_EBLOCK_SYM: 1794 if (! have_mii) 1795 dc_decode_leaf_sym(sc, 1796 (struct dc_eblock_sym *)hdr); 1797 break; 1798 default: 1799 /* Don't care. Yet. */ 1800 break; 1801 } 1802 ptr += (hdr->dc_len & 0x7F); 1803 ptr++; 1804 } 1805 } 1806 1807 /* 1808 * Attach the interface. Allocate softc structures, do ifmedia 1809 * setup and ethernet/BPF attach. 1810 */ 1811 static int 1812 dc_attach(device_t dev) 1813 { 1814 int tmp = 0; 1815 u_char eaddr[ETHER_ADDR_LEN]; 1816 u_int32_t command; 1817 struct dc_softc *sc; 1818 struct ifnet *ifp; 1819 u_int32_t revision; 1820 int unit, error = 0, rid, mac_offset; 1821 u_int8_t *mac; 1822 1823 sc = device_get_softc(dev); 1824 unit = device_get_unit(dev); 1825 1826 mtx_init(&sc->dc_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 1827 MTX_DEF | MTX_RECURSE); 1828 1829 /* 1830 * Handle power management nonsense. 1831 */ 1832 dc_acpi(dev); 1833 1834 /* 1835 * Map control/status registers. 1836 */ 1837 pci_enable_busmaster(dev); 1838 1839 rid = DC_RID; 1840 sc->dc_res = bus_alloc_resource(dev, DC_RES, &rid, 1841 0, ~0, 1, RF_ACTIVE); 1842 1843 if (sc->dc_res == NULL) { 1844 printf("dc%d: couldn't map ports/memory\n", unit); 1845 error = ENXIO; 1846 goto fail; 1847 } 1848 1849 sc->dc_btag = rman_get_bustag(sc->dc_res); 1850 sc->dc_bhandle = rman_get_bushandle(sc->dc_res); 1851 1852 /* Allocate interrupt. */ 1853 rid = 0; 1854 sc->dc_irq = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, 0, ~0, 1, 1855 RF_SHAREABLE | RF_ACTIVE); 1856 1857 if (sc->dc_irq == NULL) { 1858 printf("dc%d: couldn't map interrupt\n", unit); 1859 error = ENXIO; 1860 goto fail; 1861 } 1862 1863 /* Need this info to decide on a chip type. */ 1864 sc->dc_info = dc_devtype(dev); 1865 revision = pci_read_config(dev, DC_PCI_CFRV, 4) & 0x000000FF; 1866 1867 /* Get the eeprom width, but PNIC and XIRCOM have diff eeprom */ 1868 if (sc->dc_info->dc_did != DC_DEVICEID_82C168 && 1869 sc->dc_info->dc_did != DC_DEVICEID_X3201) 1870 dc_eeprom_width(sc); 1871 1872 switch (sc->dc_info->dc_did) { 1873 case DC_DEVICEID_21143: 1874 sc->dc_type = DC_TYPE_21143; 1875 sc->dc_flags |= DC_TX_POLL | DC_TX_USE_TX_INTR; 1876 sc->dc_flags |= DC_REDUCED_MII_POLL; 1877 /* Save EEPROM contents so we can parse them later. */ 1878 dc_read_srom(sc, sc->dc_romwidth); 1879 break; 1880 case DC_DEVICEID_DM9009: 1881 case DC_DEVICEID_DM9100: 1882 case DC_DEVICEID_DM9102: 1883 sc->dc_type = DC_TYPE_DM9102; 1884 sc->dc_flags |= DC_TX_COALESCE | DC_TX_INTR_ALWAYS; 1885 sc->dc_flags |= DC_REDUCED_MII_POLL | DC_TX_STORENFWD; 1886 sc->dc_pmode = DC_PMODE_MII; 1887 /* Increase the latency timer value. */ 1888 command = pci_read_config(dev, DC_PCI_CFLT, 4); 1889 command &= 0xFFFF00FF; 1890 command |= 0x00008000; 1891 pci_write_config(dev, DC_PCI_CFLT, command, 4); 1892 break; 1893 case DC_DEVICEID_AL981: 1894 sc->dc_type = DC_TYPE_AL981; 1895 sc->dc_flags |= DC_TX_USE_TX_INTR; 1896 sc->dc_flags |= DC_TX_ADMTEK_WAR; 1897 sc->dc_pmode = DC_PMODE_MII; 1898 dc_read_srom(sc, sc->dc_romwidth); 1899 break; 1900 case DC_DEVICEID_AN985: 1901 case DC_DEVICEID_FE2500: 1902 case DC_DEVICEID_EN2242: 1903 case DC_DEVICEID_HAWKING_PN672TX: 1904 case DC_DEVICEID_3CSOHOB: 1905 sc->dc_type = DC_TYPE_AN985; 1906 sc->dc_flags |= DC_64BIT_HASH; 1907 sc->dc_flags |= DC_TX_USE_TX_INTR; 1908 sc->dc_flags |= DC_TX_ADMTEK_WAR; 1909 sc->dc_pmode = DC_PMODE_MII; 1910 dc_read_srom(sc, sc->dc_romwidth); 1911 break; 1912 case DC_DEVICEID_98713: 1913 case DC_DEVICEID_98713_CP: 1914 if (revision < DC_REVISION_98713A) { 1915 sc->dc_type = DC_TYPE_98713; 1916 } 1917 if (revision >= DC_REVISION_98713A) { 1918 sc->dc_type = DC_TYPE_98713A; 1919 sc->dc_flags |= DC_21143_NWAY; 1920 } 1921 sc->dc_flags |= DC_REDUCED_MII_POLL; 1922 sc->dc_flags |= DC_TX_POLL | DC_TX_USE_TX_INTR; 1923 break; 1924 case DC_DEVICEID_987x5: 1925 case DC_DEVICEID_EN1217: 1926 /* 1927 * Macronix MX98715AEC-C/D/E parts have only a 1928 * 128-bit hash table. We need to deal with these 1929 * in the same manner as the PNIC II so that we 1930 * get the right number of bits out of the 1931 * CRC routine. 1932 */ 1933 if (revision >= DC_REVISION_98715AEC_C && 1934 revision < DC_REVISION_98725) 1935 sc->dc_flags |= DC_128BIT_HASH; 1936 sc->dc_type = DC_TYPE_987x5; 1937 sc->dc_flags |= DC_TX_POLL | DC_TX_USE_TX_INTR; 1938 sc->dc_flags |= DC_REDUCED_MII_POLL | DC_21143_NWAY; 1939 break; 1940 case DC_DEVICEID_98727: 1941 sc->dc_type = DC_TYPE_987x5; 1942 sc->dc_flags |= DC_TX_POLL | DC_TX_USE_TX_INTR; 1943 sc->dc_flags |= DC_REDUCED_MII_POLL | DC_21143_NWAY; 1944 break; 1945 case DC_DEVICEID_82C115: 1946 sc->dc_type = DC_TYPE_PNICII; 1947 sc->dc_flags |= DC_TX_POLL | DC_TX_USE_TX_INTR | DC_128BIT_HASH; 1948 sc->dc_flags |= DC_REDUCED_MII_POLL | DC_21143_NWAY; 1949 break; 1950 case DC_DEVICEID_82C168: 1951 sc->dc_type = DC_TYPE_PNIC; 1952 sc->dc_flags |= DC_TX_STORENFWD | DC_TX_INTR_ALWAYS; 1953 sc->dc_flags |= DC_PNIC_RX_BUG_WAR; 1954 sc->dc_pnic_rx_buf = malloc(DC_RXLEN * 5, M_DEVBUF, M_NOWAIT); 1955 if (revision < DC_REVISION_82C169) 1956 sc->dc_pmode = DC_PMODE_SYM; 1957 break; 1958 case DC_DEVICEID_AX88140A: 1959 sc->dc_type = DC_TYPE_ASIX; 1960 sc->dc_flags |= DC_TX_USE_TX_INTR | DC_TX_INTR_FIRSTFRAG; 1961 sc->dc_flags |= DC_REDUCED_MII_POLL; 1962 sc->dc_pmode = DC_PMODE_MII; 1963 break; 1964 case DC_DEVICEID_X3201: 1965 sc->dc_type = DC_TYPE_XIRCOM; 1966 sc->dc_flags |= DC_TX_INTR_ALWAYS | DC_TX_COALESCE | 1967 DC_TX_ALIGN; 1968 /* 1969 * We don't actually need to coalesce, but we're doing 1970 * it to obtain a double word aligned buffer. 1971 * The DC_TX_COALESCE flag is required. 1972 */ 1973 sc->dc_pmode = DC_PMODE_MII; 1974 break; 1975 case DC_DEVICEID_RS7112: 1976 sc->dc_type = DC_TYPE_CONEXANT; 1977 sc->dc_flags |= DC_TX_INTR_ALWAYS; 1978 sc->dc_flags |= DC_REDUCED_MII_POLL; 1979 sc->dc_pmode = DC_PMODE_MII; 1980 dc_read_srom(sc, sc->dc_romwidth); 1981 break; 1982 default: 1983 printf("dc%d: unknown device: %x\n", sc->dc_unit, 1984 sc->dc_info->dc_did); 1985 break; 1986 } 1987 1988 /* Save the cache line size. */ 1989 if (DC_IS_DAVICOM(sc)) 1990 sc->dc_cachesize = 0; 1991 else 1992 sc->dc_cachesize = pci_read_config(dev, 1993 DC_PCI_CFLT, 4) & 0xFF; 1994 1995 /* Reset the adapter. */ 1996 dc_reset(sc); 1997 1998 /* Take 21143 out of snooze mode */ 1999 if (DC_IS_INTEL(sc) || DC_IS_XIRCOM(sc)) { 2000 command = pci_read_config(dev, DC_PCI_CFDD, 4); 2001 command &= ~(DC_CFDD_SNOOZE_MODE | DC_CFDD_SLEEP_MODE); 2002 pci_write_config(dev, DC_PCI_CFDD, command, 4); 2003 } 2004 2005 /* 2006 * Try to learn something about the supported media. 2007 * We know that ASIX and ADMtek and Davicom devices 2008 * will *always* be using MII media, so that's a no-brainer. 2009 * The tricky ones are the Macronix/PNIC II and the 2010 * Intel 21143. 2011 */ 2012 if (DC_IS_INTEL(sc)) 2013 dc_parse_21143_srom(sc); 2014 else if (DC_IS_MACRONIX(sc) || DC_IS_PNICII(sc)) { 2015 if (sc->dc_type == DC_TYPE_98713) 2016 sc->dc_pmode = DC_PMODE_MII; 2017 else 2018 sc->dc_pmode = DC_PMODE_SYM; 2019 } else if (!sc->dc_pmode) 2020 sc->dc_pmode = DC_PMODE_MII; 2021 2022 /* 2023 * Get station address from the EEPROM. 2024 */ 2025 switch(sc->dc_type) { 2026 case DC_TYPE_98713: 2027 case DC_TYPE_98713A: 2028 case DC_TYPE_987x5: 2029 case DC_TYPE_PNICII: 2030 dc_read_eeprom(sc, (caddr_t)&mac_offset, 2031 (DC_EE_NODEADDR_OFFSET / 2), 1, 0); 2032 dc_read_eeprom(sc, (caddr_t)&eaddr, (mac_offset / 2), 3, 0); 2033 break; 2034 case DC_TYPE_PNIC: 2035 dc_read_eeprom(sc, (caddr_t)&eaddr, 0, 3, 1); 2036 break; 2037 case DC_TYPE_DM9102: 2038 case DC_TYPE_21143: 2039 case DC_TYPE_ASIX: 2040 dc_read_eeprom(sc, (caddr_t)&eaddr, DC_EE_NODEADDR, 3, 0); 2041 break; 2042 case DC_TYPE_AL981: 2043 case DC_TYPE_AN985: 2044 bcopy(sc->dc_srom + DC_AL_EE_NODEADDR, &eaddr, 2045 ETHER_ADDR_LEN); 2046 dc_read_eeprom(sc, (caddr_t)&eaddr, DC_AL_EE_NODEADDR, 3, 0); 2047 break; 2048 case DC_TYPE_CONEXANT: 2049 bcopy(sc->dc_srom + DC_CONEXANT_EE_NODEADDR, &eaddr, 2050 ETHER_ADDR_LEN); 2051 break; 2052 case DC_TYPE_XIRCOM: 2053 /* The MAC comes from the CIS. */ 2054 mac = pci_get_ether(dev); 2055 if (!mac) { 2056 device_printf(dev, "No station address in CIS!\n"); 2057 error = ENXIO; 2058 goto fail; 2059 } 2060 bcopy(mac, eaddr, ETHER_ADDR_LEN); 2061 break; 2062 default: 2063 dc_read_eeprom(sc, (caddr_t)&eaddr, DC_EE_NODEADDR, 3, 0); 2064 break; 2065 } 2066 2067 /* 2068 * A 21143 or clone chip was detected. Inform the world. 2069 */ 2070 printf("dc%d: Ethernet address: %6D\n", unit, eaddr, ":"); 2071 2072 sc->dc_unit = unit; 2073 bcopy(eaddr, &sc->arpcom.ac_enaddr, ETHER_ADDR_LEN); 2074 2075 sc->dc_ldata = contigmalloc(sizeof(struct dc_list_data), M_DEVBUF, 2076 M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0); 2077 2078 if (sc->dc_ldata == NULL) { 2079 printf("dc%d: no memory for list buffers!\n", unit); 2080 error = ENXIO; 2081 goto fail; 2082 } 2083 2084 bzero(sc->dc_ldata, sizeof(struct dc_list_data)); 2085 2086 ifp = &sc->arpcom.ac_if; 2087 ifp->if_softc = sc; 2088 ifp->if_unit = unit; 2089 ifp->if_name = "dc"; 2090 /* XXX: bleah, MTU gets overwritten in ether_ifattach() */ 2091 ifp->if_mtu = ETHERMTU; 2092 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 2093 ifp->if_ioctl = dc_ioctl; 2094 ifp->if_start = dc_start; 2095 ifp->if_watchdog = dc_watchdog; 2096 ifp->if_init = dc_init; 2097 ifp->if_baudrate = 10000000; 2098 ifp->if_snd.ifq_maxlen = DC_TX_LIST_CNT - 1; 2099 2100 /* 2101 * Do MII setup. If this is a 21143, check for a PHY on the 2102 * MII bus after applying any necessary fixups to twiddle the 2103 * GPIO bits. If we don't end up finding a PHY, restore the 2104 * old selection (SIA only or SIA/SYM) and attach the dcphy 2105 * driver instead. 2106 */ 2107 if (DC_IS_INTEL(sc)) { 2108 dc_apply_fixup(sc, IFM_AUTO); 2109 tmp = sc->dc_pmode; 2110 sc->dc_pmode = DC_PMODE_MII; 2111 } 2112 2113 error = mii_phy_probe(dev, &sc->dc_miibus, 2114 dc_ifmedia_upd, dc_ifmedia_sts); 2115 2116 if (error && DC_IS_INTEL(sc)) { 2117 sc->dc_pmode = tmp; 2118 if (sc->dc_pmode != DC_PMODE_SIA) 2119 sc->dc_pmode = DC_PMODE_SYM; 2120 sc->dc_flags |= DC_21143_NWAY; 2121 mii_phy_probe(dev, &sc->dc_miibus, 2122 dc_ifmedia_upd, dc_ifmedia_sts); 2123 /* 2124 * For non-MII cards, we need to have the 21143 2125 * drive the LEDs. Except there are some systems 2126 * like the NEC VersaPro NoteBook PC which have no 2127 * LEDs, and twiddling these bits has adverse effects 2128 * on them. (I.e. you suddenly can't get a link.) 2129 */ 2130 if (pci_read_config(dev, DC_PCI_CSID, 4) != 0x80281033) 2131 sc->dc_flags |= DC_TULIP_LEDS; 2132 error = 0; 2133 } 2134 2135 if (error) { 2136 printf("dc%d: MII without any PHY!\n", sc->dc_unit); 2137 goto fail; 2138 } 2139 2140 if (DC_IS_XIRCOM(sc)) { 2141 /* 2142 * setup General Purpose Port mode and data so the tulip 2143 * can talk to the MII. 2144 */ 2145 CSR_WRITE_4(sc, DC_SIAGP, DC_SIAGP_WRITE_EN | DC_SIAGP_INT1_EN | 2146 DC_SIAGP_MD_GP2_OUTPUT | DC_SIAGP_MD_GP0_OUTPUT); 2147 DELAY(10); 2148 CSR_WRITE_4(sc, DC_SIAGP, DC_SIAGP_INT1_EN | 2149 DC_SIAGP_MD_GP2_OUTPUT | DC_SIAGP_MD_GP0_OUTPUT); 2150 DELAY(10); 2151 } 2152 2153 if (DC_IS_ADMTEK(sc)) { 2154 /* 2155 * Set automatic TX underrun recovery for the ADMtek chips 2156 */ 2157 DC_SETBIT(sc, DC_AL_CR, DC_AL_CR_ATUR); 2158 } 2159 2160 /* 2161 * Tell the upper layer(s) we support long frames. 2162 */ 2163 ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header); 2164 ifp->if_capabilities |= IFCAP_VLAN_MTU; 2165 2166 callout_init(&sc->dc_stat_ch, IS_MPSAFE); 2167 2168 #ifdef SRM_MEDIA 2169 sc->dc_srm_media = 0; 2170 2171 /* Remember the SRM console media setting */ 2172 if (DC_IS_INTEL(sc)) { 2173 command = pci_read_config(dev, DC_PCI_CFDD, 4); 2174 command &= ~(DC_CFDD_SNOOZE_MODE | DC_CFDD_SLEEP_MODE); 2175 switch ((command >> 8) & 0xff) { 2176 case 3: 2177 sc->dc_srm_media = IFM_10_T; 2178 break; 2179 case 4: 2180 sc->dc_srm_media = IFM_10_T | IFM_FDX; 2181 break; 2182 case 5: 2183 sc->dc_srm_media = IFM_100_TX; 2184 break; 2185 case 6: 2186 sc->dc_srm_media = IFM_100_TX | IFM_FDX; 2187 break; 2188 } 2189 if (sc->dc_srm_media) 2190 sc->dc_srm_media |= IFM_ACTIVE | IFM_ETHER; 2191 } 2192 #endif 2193 2194 /* 2195 * Call MI attach routine. 2196 */ 2197 ether_ifattach(ifp, eaddr); 2198 2199 /* Hook interrupt last to avoid having to lock softc */ 2200 error = bus_setup_intr(dev, sc->dc_irq, INTR_TYPE_NET | 2201 (IS_MPSAFE ? INTR_MPSAFE : 0), 2202 dc_intr, sc, &sc->dc_intrhand); 2203 2204 if (error) { 2205 printf("dc%d: couldn't set up irq\n", unit); 2206 ether_ifdetach(ifp); 2207 goto fail; 2208 } 2209 2210 fail: 2211 if (error) 2212 dc_detach(dev); 2213 return (error); 2214 } 2215 2216 /* 2217 * Shutdown hardware and free up resources. This can be called any 2218 * time after the mutex has been initialized. It is called in both 2219 * the error case in attach and the normal detach case so it needs 2220 * to be careful about only freeing resources that have actually been 2221 * allocated. 2222 */ 2223 static int 2224 dc_detach(device_t dev) 2225 { 2226 struct dc_softc *sc; 2227 struct ifnet *ifp; 2228 struct dc_mediainfo *m; 2229 2230 sc = device_get_softc(dev); 2231 KASSERT(mtx_initialized(&sc->dc_mtx), ("dc mutex not initialized")); 2232 DC_LOCK(sc); 2233 2234 ifp = &sc->arpcom.ac_if; 2235 2236 /* These should only be active if attach succeeded */ 2237 if (device_is_attached(dev)) { 2238 dc_stop(sc); 2239 ether_ifdetach(ifp); 2240 } 2241 if (sc->dc_miibus) 2242 device_delete_child(dev, sc->dc_miibus); 2243 bus_generic_detach(dev); 2244 2245 if (sc->dc_intrhand) 2246 bus_teardown_intr(dev, sc->dc_irq, sc->dc_intrhand); 2247 if (sc->dc_irq) 2248 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->dc_irq); 2249 if (sc->dc_res) 2250 bus_release_resource(dev, DC_RES, DC_RID, sc->dc_res); 2251 2252 if (sc->dc_ldata) 2253 contigfree(sc->dc_ldata, sizeof(struct dc_list_data), M_DEVBUF); 2254 free(sc->dc_pnic_rx_buf, M_DEVBUF); 2255 2256 while (sc->dc_mi != NULL) { 2257 m = sc->dc_mi->dc_next; 2258 free(sc->dc_mi, M_DEVBUF); 2259 sc->dc_mi = m; 2260 } 2261 free(sc->dc_srom, M_DEVBUF); 2262 2263 DC_UNLOCK(sc); 2264 mtx_destroy(&sc->dc_mtx); 2265 2266 return (0); 2267 } 2268 2269 /* 2270 * Initialize the transmit descriptors. 2271 */ 2272 static int 2273 dc_list_tx_init(struct dc_softc *sc) 2274 { 2275 struct dc_chain_data *cd; 2276 struct dc_list_data *ld; 2277 int i, nexti; 2278 2279 cd = &sc->dc_cdata; 2280 ld = sc->dc_ldata; 2281 for (i = 0; i < DC_TX_LIST_CNT; i++) { 2282 nexti = (i == (DC_TX_LIST_CNT - 1)) ? 0 : i+1; 2283 ld->dc_tx_list[i].dc_next = vtophys(&ld->dc_tx_list[nexti]); 2284 cd->dc_tx_chain[i] = NULL; 2285 ld->dc_tx_list[i].dc_data = 0; 2286 ld->dc_tx_list[i].dc_ctl = 0; 2287 } 2288 2289 cd->dc_tx_prod = cd->dc_tx_cons = cd->dc_tx_cnt = 0; 2290 2291 return (0); 2292 } 2293 2294 2295 /* 2296 * Initialize the RX descriptors and allocate mbufs for them. Note that 2297 * we arrange the descriptors in a closed ring, so that the last descriptor 2298 * points back to the first. 2299 */ 2300 static int 2301 dc_list_rx_init(struct dc_softc *sc) 2302 { 2303 struct dc_chain_data *cd; 2304 struct dc_list_data *ld; 2305 int i, nexti; 2306 2307 cd = &sc->dc_cdata; 2308 ld = sc->dc_ldata; 2309 2310 for (i = 0; i < DC_RX_LIST_CNT; i++) { 2311 if (dc_newbuf(sc, i, NULL) == ENOBUFS) 2312 return (ENOBUFS); 2313 nexti = (i == (DC_RX_LIST_CNT - 1)) ? 0 : i+1; 2314 ld->dc_rx_list[i].dc_next = vtophys(&ld->dc_rx_list[nexti]); 2315 } 2316 2317 cd->dc_rx_prod = 0; 2318 2319 return (0); 2320 } 2321 2322 /* 2323 * Initialize an RX descriptor and attach an MBUF cluster. 2324 */ 2325 static int 2326 dc_newbuf(struct dc_softc *sc, int i, struct mbuf *m) 2327 { 2328 struct mbuf *m_new = NULL; 2329 struct dc_desc *c; 2330 2331 c = &sc->dc_ldata->dc_rx_list[i]; 2332 2333 if (m == NULL) { 2334 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 2335 if (m_new == NULL) 2336 return (ENOBUFS); 2337 2338 MCLGET(m_new, M_DONTWAIT); 2339 if (!(m_new->m_flags & M_EXT)) { 2340 m_freem(m_new); 2341 return (ENOBUFS); 2342 } 2343 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 2344 } else { 2345 m_new = m; 2346 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 2347 m_new->m_data = m_new->m_ext.ext_buf; 2348 } 2349 2350 m_adj(m_new, sizeof(u_int64_t)); 2351 2352 /* 2353 * If this is a PNIC chip, zero the buffer. This is part 2354 * of the workaround for the receive bug in the 82c168 and 2355 * 82c169 chips. 2356 */ 2357 if (sc->dc_flags & DC_PNIC_RX_BUG_WAR) 2358 bzero(mtod(m_new, char *), m_new->m_len); 2359 2360 sc->dc_cdata.dc_rx_chain[i] = m_new; 2361 c->dc_data = vtophys(mtod(m_new, caddr_t)); 2362 c->dc_ctl = DC_RXCTL_RLINK | DC_RXLEN; 2363 c->dc_status = DC_RXSTAT_OWN; 2364 2365 return (0); 2366 } 2367 2368 /* 2369 * Grrrrr. 2370 * The PNIC chip has a terrible bug in it that manifests itself during 2371 * periods of heavy activity. The exact mode of failure if difficult to 2372 * pinpoint: sometimes it only happens in promiscuous mode, sometimes it 2373 * will happen on slow machines. The bug is that sometimes instead of 2374 * uploading one complete frame during reception, it uploads what looks 2375 * like the entire contents of its FIFO memory. The frame we want is at 2376 * the end of the whole mess, but we never know exactly how much data has 2377 * been uploaded, so salvaging the frame is hard. 2378 * 2379 * There is only one way to do it reliably, and it's disgusting. 2380 * Here's what we know: 2381 * 2382 * - We know there will always be somewhere between one and three extra 2383 * descriptors uploaded. 2384 * 2385 * - We know the desired received frame will always be at the end of the 2386 * total data upload. 2387 * 2388 * - We know the size of the desired received frame because it will be 2389 * provided in the length field of the status word in the last descriptor. 2390 * 2391 * Here's what we do: 2392 * 2393 * - When we allocate buffers for the receive ring, we bzero() them. 2394 * This means that we know that the buffer contents should be all 2395 * zeros, except for data uploaded by the chip. 2396 * 2397 * - We also force the PNIC chip to upload frames that include the 2398 * ethernet CRC at the end. 2399 * 2400 * - We gather all of the bogus frame data into a single buffer. 2401 * 2402 * - We then position a pointer at the end of this buffer and scan 2403 * backwards until we encounter the first non-zero byte of data. 2404 * This is the end of the received frame. We know we will encounter 2405 * some data at the end of the frame because the CRC will always be 2406 * there, so even if the sender transmits a packet of all zeros, 2407 * we won't be fooled. 2408 * 2409 * - We know the size of the actual received frame, so we subtract 2410 * that value from the current pointer location. This brings us 2411 * to the start of the actual received packet. 2412 * 2413 * - We copy this into an mbuf and pass it on, along with the actual 2414 * frame length. 2415 * 2416 * The performance hit is tremendous, but it beats dropping frames all 2417 * the time. 2418 */ 2419 2420 #define DC_WHOLEFRAME (DC_RXSTAT_FIRSTFRAG | DC_RXSTAT_LASTFRAG) 2421 static void 2422 dc_pnic_rx_bug_war(struct dc_softc *sc, int idx) 2423 { 2424 struct dc_desc *cur_rx; 2425 struct dc_desc *c = NULL; 2426 struct mbuf *m = NULL; 2427 unsigned char *ptr; 2428 int i, total_len; 2429 u_int32_t rxstat = 0; 2430 2431 i = sc->dc_pnic_rx_bug_save; 2432 cur_rx = &sc->dc_ldata->dc_rx_list[idx]; 2433 ptr = sc->dc_pnic_rx_buf; 2434 bzero(ptr, DC_RXLEN * 5); 2435 2436 /* Copy all the bytes from the bogus buffers. */ 2437 while (1) { 2438 c = &sc->dc_ldata->dc_rx_list[i]; 2439 rxstat = c->dc_status; 2440 m = sc->dc_cdata.dc_rx_chain[i]; 2441 bcopy(mtod(m, char *), ptr, DC_RXLEN); 2442 ptr += DC_RXLEN; 2443 /* If this is the last buffer, break out. */ 2444 if (i == idx || rxstat & DC_RXSTAT_LASTFRAG) 2445 break; 2446 dc_newbuf(sc, i, m); 2447 DC_INC(i, DC_RX_LIST_CNT); 2448 } 2449 2450 /* Find the length of the actual receive frame. */ 2451 total_len = DC_RXBYTES(rxstat); 2452 2453 /* Scan backwards until we hit a non-zero byte. */ 2454 while (*ptr == 0x00) 2455 ptr--; 2456 2457 /* Round off. */ 2458 if ((uintptr_t)(ptr) & 0x3) 2459 ptr -= 1; 2460 2461 /* Now find the start of the frame. */ 2462 ptr -= total_len; 2463 if (ptr < sc->dc_pnic_rx_buf) 2464 ptr = sc->dc_pnic_rx_buf; 2465 2466 /* 2467 * Now copy the salvaged frame to the last mbuf and fake up 2468 * the status word to make it look like a successful 2469 * frame reception. 2470 */ 2471 dc_newbuf(sc, i, m); 2472 bcopy(ptr, mtod(m, char *), total_len); 2473 cur_rx->dc_status = rxstat | DC_RXSTAT_FIRSTFRAG; 2474 } 2475 2476 /* 2477 * This routine searches the RX ring for dirty descriptors in the 2478 * event that the rxeof routine falls out of sync with the chip's 2479 * current descriptor pointer. This may happen sometimes as a result 2480 * of a "no RX buffer available" condition that happens when the chip 2481 * consumes all of the RX buffers before the driver has a chance to 2482 * process the RX ring. This routine may need to be called more than 2483 * once to bring the driver back in sync with the chip, however we 2484 * should still be getting RX DONE interrupts to drive the search 2485 * for new packets in the RX ring, so we should catch up eventually. 2486 */ 2487 static int 2488 dc_rx_resync(struct dc_softc *sc) 2489 { 2490 struct dc_desc *cur_rx; 2491 int i, pos; 2492 2493 pos = sc->dc_cdata.dc_rx_prod; 2494 2495 for (i = 0; i < DC_RX_LIST_CNT; i++) { 2496 cur_rx = &sc->dc_ldata->dc_rx_list[pos]; 2497 if (!(cur_rx->dc_status & DC_RXSTAT_OWN)) 2498 break; 2499 DC_INC(pos, DC_RX_LIST_CNT); 2500 } 2501 2502 /* If the ring really is empty, then just return. */ 2503 if (i == DC_RX_LIST_CNT) 2504 return (0); 2505 2506 /* We've fallen behing the chip: catch it. */ 2507 sc->dc_cdata.dc_rx_prod = pos; 2508 2509 return (EAGAIN); 2510 } 2511 2512 /* 2513 * A frame has been uploaded: pass the resulting mbuf chain up to 2514 * the higher level protocols. 2515 */ 2516 static void 2517 dc_rxeof(struct dc_softc *sc) 2518 { 2519 struct mbuf *m; 2520 struct ifnet *ifp; 2521 struct dc_desc *cur_rx; 2522 int i, total_len = 0; 2523 u_int32_t rxstat; 2524 2525 ifp = &sc->arpcom.ac_if; 2526 i = sc->dc_cdata.dc_rx_prod; 2527 2528 while (!(sc->dc_ldata->dc_rx_list[i].dc_status & DC_RXSTAT_OWN)) { 2529 #ifdef DEVICE_POLLING 2530 if (ifp->if_flags & IFF_POLLING) { 2531 if (sc->rxcycles <= 0) 2532 break; 2533 sc->rxcycles--; 2534 } 2535 #endif 2536 cur_rx = &sc->dc_ldata->dc_rx_list[i]; 2537 rxstat = cur_rx->dc_status; 2538 m = sc->dc_cdata.dc_rx_chain[i]; 2539 total_len = DC_RXBYTES(rxstat); 2540 2541 if (sc->dc_flags & DC_PNIC_RX_BUG_WAR) { 2542 if ((rxstat & DC_WHOLEFRAME) != DC_WHOLEFRAME) { 2543 if (rxstat & DC_RXSTAT_FIRSTFRAG) 2544 sc->dc_pnic_rx_bug_save = i; 2545 if ((rxstat & DC_RXSTAT_LASTFRAG) == 0) { 2546 DC_INC(i, DC_RX_LIST_CNT); 2547 continue; 2548 } 2549 dc_pnic_rx_bug_war(sc, i); 2550 rxstat = cur_rx->dc_status; 2551 total_len = DC_RXBYTES(rxstat); 2552 } 2553 } 2554 2555 sc->dc_cdata.dc_rx_chain[i] = NULL; 2556 2557 /* 2558 * If an error occurs, update stats, clear the 2559 * status word and leave the mbuf cluster in place: 2560 * it should simply get re-used next time this descriptor 2561 * comes up in the ring. However, don't report long 2562 * frames as errors since they could be vlans. 2563 */ 2564 if ((rxstat & DC_RXSTAT_RXERR)) { 2565 if (!(rxstat & DC_RXSTAT_GIANT) || 2566 (rxstat & (DC_RXSTAT_CRCERR | DC_RXSTAT_DRIBBLE | 2567 DC_RXSTAT_MIIERE | DC_RXSTAT_COLLSEEN | 2568 DC_RXSTAT_RUNT | DC_RXSTAT_DE))) { 2569 ifp->if_ierrors++; 2570 if (rxstat & DC_RXSTAT_COLLSEEN) 2571 ifp->if_collisions++; 2572 dc_newbuf(sc, i, m); 2573 if (rxstat & DC_RXSTAT_CRCERR) { 2574 DC_INC(i, DC_RX_LIST_CNT); 2575 continue; 2576 } else { 2577 dc_init(sc); 2578 return; 2579 } 2580 } 2581 } 2582 2583 /* No errors; receive the packet. */ 2584 total_len -= ETHER_CRC_LEN; 2585 #ifdef __i386__ 2586 /* 2587 * On the x86 we do not have alignment problems, so try to 2588 * allocate a new buffer for the receive ring, and pass up 2589 * the one where the packet is already, saving the expensive 2590 * copy done in m_devget(). 2591 * If we are on an architecture with alignment problems, or 2592 * if the allocation fails, then use m_devget and leave the 2593 * existing buffer in the receive ring. 2594 */ 2595 if (dc_quick && dc_newbuf(sc, i, NULL) == 0) { 2596 m->m_pkthdr.rcvif = ifp; 2597 m->m_pkthdr.len = m->m_len = total_len; 2598 DC_INC(i, DC_RX_LIST_CNT); 2599 } else 2600 #endif 2601 { 2602 struct mbuf *m0; 2603 2604 m0 = m_devget(mtod(m, char *), total_len, 2605 ETHER_ALIGN, ifp, NULL); 2606 dc_newbuf(sc, i, m); 2607 DC_INC(i, DC_RX_LIST_CNT); 2608 if (m0 == NULL) { 2609 ifp->if_ierrors++; 2610 continue; 2611 } 2612 m = m0; 2613 } 2614 2615 ifp->if_ipackets++; 2616 (*ifp->if_input)(ifp, m); 2617 } 2618 2619 sc->dc_cdata.dc_rx_prod = i; 2620 } 2621 2622 /* 2623 * A frame was downloaded to the chip. It's safe for us to clean up 2624 * the list buffers. 2625 */ 2626 2627 static void 2628 dc_txeof(struct dc_softc *sc) 2629 { 2630 struct dc_desc *cur_tx = NULL; 2631 struct ifnet *ifp; 2632 int idx; 2633 u_int32_t txstat; 2634 2635 ifp = &sc->arpcom.ac_if; 2636 2637 /* 2638 * Go through our tx list and free mbufs for those 2639 * frames that have been transmitted. 2640 */ 2641 idx = sc->dc_cdata.dc_tx_cons; 2642 while (idx != sc->dc_cdata.dc_tx_prod) { 2643 2644 cur_tx = &sc->dc_ldata->dc_tx_list[idx]; 2645 txstat = cur_tx->dc_status; 2646 2647 if (txstat & DC_TXSTAT_OWN) 2648 break; 2649 2650 if (!(cur_tx->dc_ctl & DC_TXCTL_LASTFRAG) || 2651 cur_tx->dc_ctl & DC_TXCTL_SETUP) { 2652 if (cur_tx->dc_ctl & DC_TXCTL_SETUP) { 2653 /* 2654 * Yes, the PNIC is so brain damaged 2655 * that it will sometimes generate a TX 2656 * underrun error while DMAing the RX 2657 * filter setup frame. If we detect this, 2658 * we have to send the setup frame again, 2659 * or else the filter won't be programmed 2660 * correctly. 2661 */ 2662 if (DC_IS_PNIC(sc)) { 2663 if (txstat & DC_TXSTAT_ERRSUM) 2664 dc_setfilt(sc); 2665 } 2666 sc->dc_cdata.dc_tx_chain[idx] = NULL; 2667 } 2668 sc->dc_cdata.dc_tx_cnt--; 2669 DC_INC(idx, DC_TX_LIST_CNT); 2670 continue; 2671 } 2672 2673 if (DC_IS_XIRCOM(sc) || DC_IS_CONEXANT(sc)) { 2674 /* 2675 * XXX: Why does my Xircom taunt me so? 2676 * For some reason it likes setting the CARRLOST flag 2677 * even when the carrier is there. wtf?!? 2678 * Who knows, but Conexant chips have the 2679 * same problem. Maybe they took lessons 2680 * from Xircom. 2681 */ 2682 if (/*sc->dc_type == DC_TYPE_21143 &&*/ 2683 sc->dc_pmode == DC_PMODE_MII && 2684 ((txstat & 0xFFFF) & ~(DC_TXSTAT_ERRSUM | 2685 DC_TXSTAT_NOCARRIER))) 2686 txstat &= ~DC_TXSTAT_ERRSUM; 2687 } else { 2688 if (/*sc->dc_type == DC_TYPE_21143 &&*/ 2689 sc->dc_pmode == DC_PMODE_MII && 2690 ((txstat & 0xFFFF) & ~(DC_TXSTAT_ERRSUM | 2691 DC_TXSTAT_NOCARRIER | DC_TXSTAT_CARRLOST))) 2692 txstat &= ~DC_TXSTAT_ERRSUM; 2693 } 2694 2695 if (txstat & DC_TXSTAT_ERRSUM) { 2696 ifp->if_oerrors++; 2697 if (txstat & DC_TXSTAT_EXCESSCOLL) 2698 ifp->if_collisions++; 2699 if (txstat & DC_TXSTAT_LATECOLL) 2700 ifp->if_collisions++; 2701 if (!(txstat & DC_TXSTAT_UNDERRUN)) { 2702 dc_init(sc); 2703 return; 2704 } 2705 } 2706 2707 ifp->if_collisions += (txstat & DC_TXSTAT_COLLCNT) >> 3; 2708 2709 ifp->if_opackets++; 2710 if (sc->dc_cdata.dc_tx_chain[idx] != NULL) { 2711 m_freem(sc->dc_cdata.dc_tx_chain[idx]); 2712 sc->dc_cdata.dc_tx_chain[idx] = NULL; 2713 } 2714 2715 sc->dc_cdata.dc_tx_cnt--; 2716 DC_INC(idx, DC_TX_LIST_CNT); 2717 } 2718 2719 if (idx != sc->dc_cdata.dc_tx_cons) { 2720 /* Some buffers have been freed. */ 2721 sc->dc_cdata.dc_tx_cons = idx; 2722 ifp->if_flags &= ~IFF_OACTIVE; 2723 } 2724 ifp->if_timer = (sc->dc_cdata.dc_tx_cnt == 0) ? 0 : 5; 2725 } 2726 2727 static void 2728 dc_tick(void *xsc) 2729 { 2730 struct dc_softc *sc; 2731 struct mii_data *mii; 2732 struct ifnet *ifp; 2733 u_int32_t r; 2734 2735 sc = xsc; 2736 DC_LOCK(sc); 2737 ifp = &sc->arpcom.ac_if; 2738 mii = device_get_softc(sc->dc_miibus); 2739 2740 if (sc->dc_flags & DC_REDUCED_MII_POLL) { 2741 if (sc->dc_flags & DC_21143_NWAY) { 2742 r = CSR_READ_4(sc, DC_10BTSTAT); 2743 if (IFM_SUBTYPE(mii->mii_media_active) == 2744 IFM_100_TX && (r & DC_TSTAT_LS100)) { 2745 sc->dc_link = 0; 2746 mii_mediachg(mii); 2747 } 2748 if (IFM_SUBTYPE(mii->mii_media_active) == 2749 IFM_10_T && (r & DC_TSTAT_LS10)) { 2750 sc->dc_link = 0; 2751 mii_mediachg(mii); 2752 } 2753 if (sc->dc_link == 0) 2754 mii_tick(mii); 2755 } else { 2756 r = CSR_READ_4(sc, DC_ISR); 2757 if ((r & DC_ISR_RX_STATE) == DC_RXSTATE_WAIT && 2758 sc->dc_cdata.dc_tx_cnt == 0) { 2759 mii_tick(mii); 2760 if (!(mii->mii_media_status & IFM_ACTIVE)) 2761 sc->dc_link = 0; 2762 } 2763 } 2764 } else 2765 mii_tick(mii); 2766 2767 /* 2768 * When the init routine completes, we expect to be able to send 2769 * packets right away, and in fact the network code will send a 2770 * gratuitous ARP the moment the init routine marks the interface 2771 * as running. However, even though the MAC may have been initialized, 2772 * there may be a delay of a few seconds before the PHY completes 2773 * autonegotiation and the link is brought up. Any transmissions 2774 * made during that delay will be lost. Dealing with this is tricky: 2775 * we can't just pause in the init routine while waiting for the 2776 * PHY to come ready since that would bring the whole system to 2777 * a screeching halt for several seconds. 2778 * 2779 * What we do here is prevent the TX start routine from sending 2780 * any packets until a link has been established. After the 2781 * interface has been initialized, the tick routine will poll 2782 * the state of the PHY until the IFM_ACTIVE flag is set. Until 2783 * that time, packets will stay in the send queue, and once the 2784 * link comes up, they will be flushed out to the wire. 2785 */ 2786 if (!sc->dc_link && mii->mii_media_status & IFM_ACTIVE && 2787 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) { 2788 sc->dc_link++; 2789 if (ifp->if_snd.ifq_head != NULL) 2790 dc_start(ifp); 2791 } 2792 2793 if (sc->dc_flags & DC_21143_NWAY && !sc->dc_link) 2794 callout_reset(&sc->dc_stat_ch, hz/10, dc_tick, sc); 2795 else 2796 callout_reset(&sc->dc_stat_ch, hz, dc_tick, sc); 2797 2798 DC_UNLOCK(sc); 2799 } 2800 2801 /* 2802 * A transmit underrun has occurred. Back off the transmit threshold, 2803 * or switch to store and forward mode if we have to. 2804 */ 2805 static void 2806 dc_tx_underrun(struct dc_softc *sc) 2807 { 2808 u_int32_t isr; 2809 int i; 2810 2811 if (DC_IS_DAVICOM(sc)) 2812 dc_init(sc); 2813 2814 if (DC_IS_INTEL(sc)) { 2815 /* 2816 * The real 21143 requires that the transmitter be idle 2817 * in order to change the transmit threshold or store 2818 * and forward state. 2819 */ 2820 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_TX_ON); 2821 2822 for (i = 0; i < DC_TIMEOUT; i++) { 2823 isr = CSR_READ_4(sc, DC_ISR); 2824 if (isr & DC_ISR_TX_IDLE) 2825 break; 2826 DELAY(10); 2827 } 2828 if (i == DC_TIMEOUT) { 2829 printf("dc%d: failed to force tx to idle state\n", 2830 sc->dc_unit); 2831 dc_init(sc); 2832 } 2833 } 2834 2835 printf("dc%d: TX underrun -- ", sc->dc_unit); 2836 sc->dc_txthresh += DC_TXTHRESH_INC; 2837 if (sc->dc_txthresh > DC_TXTHRESH_MAX) { 2838 printf("using store and forward mode\n"); 2839 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_STORENFWD); 2840 } else { 2841 printf("increasing TX threshold\n"); 2842 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_TX_THRESH); 2843 DC_SETBIT(sc, DC_NETCFG, sc->dc_txthresh); 2844 } 2845 2846 if (DC_IS_INTEL(sc)) 2847 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_TX_ON); 2848 } 2849 2850 #ifdef DEVICE_POLLING 2851 static poll_handler_t dc_poll; 2852 2853 static void 2854 dc_poll(struct ifnet *ifp, enum poll_cmd cmd, int count) 2855 { 2856 struct dc_softc *sc = ifp->if_softc; 2857 2858 if (cmd == POLL_DEREGISTER) { /* final call, enable interrupts */ 2859 /* Re-enable interrupts. */ 2860 CSR_WRITE_4(sc, DC_IMR, DC_INTRS); 2861 return; 2862 } 2863 sc->rxcycles = count; 2864 dc_rxeof(sc); 2865 dc_txeof(sc); 2866 if (ifp->if_snd.ifq_head != NULL && !(ifp->if_flags & IFF_OACTIVE)) 2867 dc_start(ifp); 2868 2869 if (cmd == POLL_AND_CHECK_STATUS) { /* also check status register */ 2870 u_int32_t status; 2871 2872 status = CSR_READ_4(sc, DC_ISR); 2873 status &= (DC_ISR_RX_WATDOGTIMEO | DC_ISR_RX_NOBUF | 2874 DC_ISR_TX_NOBUF | DC_ISR_TX_IDLE | DC_ISR_TX_UNDERRUN | 2875 DC_ISR_BUS_ERR); 2876 if (!status) 2877 return; 2878 /* ack what we have */ 2879 CSR_WRITE_4(sc, DC_ISR, status); 2880 2881 if (status & (DC_ISR_RX_WATDOGTIMEO | DC_ISR_RX_NOBUF)) { 2882 u_int32_t r = CSR_READ_4(sc, DC_FRAMESDISCARDED); 2883 ifp->if_ierrors += (r & 0xffff) + ((r >> 17) & 0x7ff); 2884 2885 if (dc_rx_resync(sc)) 2886 dc_rxeof(sc); 2887 } 2888 /* restart transmit unit if necessary */ 2889 if (status & DC_ISR_TX_IDLE && sc->dc_cdata.dc_tx_cnt) 2890 CSR_WRITE_4(sc, DC_TXSTART, 0xFFFFFFFF); 2891 2892 if (status & DC_ISR_TX_UNDERRUN) 2893 dc_tx_underrun(sc); 2894 2895 if (status & DC_ISR_BUS_ERR) { 2896 printf("dc_poll: dc%d bus error\n", sc->dc_unit); 2897 dc_reset(sc); 2898 dc_init(sc); 2899 } 2900 } 2901 } 2902 #endif /* DEVICE_POLLING */ 2903 2904 static void 2905 dc_intr(void *arg) 2906 { 2907 struct dc_softc *sc; 2908 struct ifnet *ifp; 2909 u_int32_t status; 2910 2911 sc = arg; 2912 2913 if (sc->suspended) 2914 return; 2915 2916 if ((CSR_READ_4(sc, DC_ISR) & DC_INTRS) == 0) 2917 return; 2918 2919 DC_LOCK(sc); 2920 ifp = &sc->arpcom.ac_if; 2921 #ifdef DEVICE_POLLING 2922 if (ifp->if_flags & IFF_POLLING) 2923 goto done; 2924 if (ether_poll_register(dc_poll, ifp)) { /* ok, disable interrupts */ 2925 CSR_WRITE_4(sc, DC_IMR, 0x00000000); 2926 goto done; 2927 } 2928 #endif 2929 2930 /* Suppress unwanted interrupts */ 2931 if (!(ifp->if_flags & IFF_UP)) { 2932 if (CSR_READ_4(sc, DC_ISR) & DC_INTRS) 2933 dc_stop(sc); 2934 DC_UNLOCK(sc); 2935 return; 2936 } 2937 2938 /* Disable interrupts. */ 2939 CSR_WRITE_4(sc, DC_IMR, 0x00000000); 2940 2941 while (((status = CSR_READ_4(sc, DC_ISR)) & DC_INTRS) 2942 && status != 0xFFFFFFFF) { 2943 2944 CSR_WRITE_4(sc, DC_ISR, status); 2945 2946 if (status & DC_ISR_RX_OK) { 2947 int curpkts; 2948 curpkts = ifp->if_ipackets; 2949 dc_rxeof(sc); 2950 if (curpkts == ifp->if_ipackets) { 2951 while (dc_rx_resync(sc)) 2952 dc_rxeof(sc); 2953 } 2954 } 2955 2956 if (status & (DC_ISR_TX_OK | DC_ISR_TX_NOBUF)) 2957 dc_txeof(sc); 2958 2959 if (status & DC_ISR_TX_IDLE) { 2960 dc_txeof(sc); 2961 if (sc->dc_cdata.dc_tx_cnt) { 2962 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_TX_ON); 2963 CSR_WRITE_4(sc, DC_TXSTART, 0xFFFFFFFF); 2964 } 2965 } 2966 2967 if (status & DC_ISR_TX_UNDERRUN) 2968 dc_tx_underrun(sc); 2969 2970 if ((status & DC_ISR_RX_WATDOGTIMEO) 2971 || (status & DC_ISR_RX_NOBUF)) { 2972 int curpkts; 2973 curpkts = ifp->if_ipackets; 2974 dc_rxeof(sc); 2975 if (curpkts == ifp->if_ipackets) { 2976 while (dc_rx_resync(sc)) 2977 dc_rxeof(sc); 2978 } 2979 } 2980 2981 if (status & DC_ISR_BUS_ERR) { 2982 dc_reset(sc); 2983 dc_init(sc); 2984 } 2985 } 2986 2987 /* Re-enable interrupts. */ 2988 CSR_WRITE_4(sc, DC_IMR, DC_INTRS); 2989 2990 if (ifp->if_snd.ifq_head != NULL) 2991 dc_start(ifp); 2992 2993 #ifdef DEVICE_POLLING 2994 done: 2995 #endif 2996 2997 DC_UNLOCK(sc); 2998 } 2999 3000 /* 3001 * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data 3002 * pointers to the fragment pointers. 3003 */ 3004 static int 3005 dc_encap(struct dc_softc *sc, struct mbuf *m_head, u_int32_t *txidx) 3006 { 3007 struct dc_desc *f = NULL; 3008 struct mbuf *m; 3009 int frag, cur, cnt = 0, chainlen = 0; 3010 3011 /* 3012 * If there's no way we can send any packets, return now. 3013 */ 3014 if (DC_TX_LIST_CNT - sc->dc_cdata.dc_tx_cnt < 6) 3015 return (ENOBUFS); 3016 3017 /* 3018 * Count the number of frags in this chain to see if 3019 * we need to m_defrag. Since the descriptor list is shared 3020 * by all packets, we'll m_defrag long chains so that they 3021 * do not use up the entire list, even if they would fit. 3022 */ 3023 3024 for (m = m_head; m != NULL; m = m->m_next) 3025 chainlen++; 3026 3027 if ((chainlen > DC_TX_LIST_CNT / 4) || 3028 ((DC_TX_LIST_CNT - (chainlen + sc->dc_cdata.dc_tx_cnt)) < 6)) { 3029 m = m_defrag(m_head, M_DONTWAIT); 3030 if (m == NULL) 3031 return (ENOBUFS); 3032 m_head = m; 3033 } 3034 3035 /* 3036 * Start packing the mbufs in this chain into 3037 * the fragment pointers. Stop when we run out 3038 * of fragments or hit the end of the mbuf chain. 3039 */ 3040 m = m_head; 3041 cur = frag = *txidx; 3042 3043 for (m = m_head; m != NULL; m = m->m_next) { 3044 if (m->m_len != 0) { 3045 if (sc->dc_flags & DC_TX_ADMTEK_WAR) { 3046 if (*txidx != sc->dc_cdata.dc_tx_prod && 3047 frag == (DC_TX_LIST_CNT - 1)) 3048 return (ENOBUFS); 3049 } 3050 if ((DC_TX_LIST_CNT - 3051 (sc->dc_cdata.dc_tx_cnt + cnt)) < 5) 3052 return (ENOBUFS); 3053 3054 f = &sc->dc_ldata->dc_tx_list[frag]; 3055 f->dc_ctl = DC_TXCTL_TLINK | m->m_len; 3056 if (cnt == 0) { 3057 f->dc_status = 0; 3058 f->dc_ctl |= DC_TXCTL_FIRSTFRAG; 3059 } else 3060 f->dc_status = DC_TXSTAT_OWN; 3061 f->dc_data = vtophys(mtod(m, vm_offset_t)); 3062 cur = frag; 3063 DC_INC(frag, DC_TX_LIST_CNT); 3064 cnt++; 3065 } 3066 } 3067 3068 if (m != NULL) 3069 return (ENOBUFS); 3070 3071 sc->dc_cdata.dc_tx_cnt += cnt; 3072 sc->dc_cdata.dc_tx_chain[cur] = m_head; 3073 sc->dc_ldata->dc_tx_list[cur].dc_ctl |= DC_TXCTL_LASTFRAG; 3074 if (sc->dc_flags & DC_TX_INTR_FIRSTFRAG) 3075 sc->dc_ldata->dc_tx_list[*txidx].dc_ctl |= DC_TXCTL_FINT; 3076 if (sc->dc_flags & DC_TX_INTR_ALWAYS) 3077 sc->dc_ldata->dc_tx_list[cur].dc_ctl |= DC_TXCTL_FINT; 3078 if (sc->dc_flags & DC_TX_USE_TX_INTR && sc->dc_cdata.dc_tx_cnt > 64) 3079 sc->dc_ldata->dc_tx_list[cur].dc_ctl |= DC_TXCTL_FINT; 3080 sc->dc_ldata->dc_tx_list[*txidx].dc_status = DC_TXSTAT_OWN; 3081 *txidx = frag; 3082 3083 return (0); 3084 } 3085 3086 /* 3087 * Main transmit routine. To avoid having to do mbuf copies, we put pointers 3088 * to the mbuf data regions directly in the transmit lists. We also save a 3089 * copy of the pointers since the transmit list fragment pointers are 3090 * physical addresses. 3091 */ 3092 3093 static void 3094 dc_start(struct ifnet *ifp) 3095 { 3096 struct dc_softc *sc; 3097 struct mbuf *m_head = NULL, *m; 3098 int idx; 3099 3100 sc = ifp->if_softc; 3101 3102 DC_LOCK(sc); 3103 3104 if (!sc->dc_link && ifp->if_snd.ifq_len < 10) { 3105 DC_UNLOCK(sc); 3106 return; 3107 } 3108 3109 if (ifp->if_flags & IFF_OACTIVE) { 3110 DC_UNLOCK(sc); 3111 return; 3112 } 3113 3114 idx = sc->dc_cdata.dc_tx_prod; 3115 3116 while (sc->dc_cdata.dc_tx_chain[idx] == NULL) { 3117 IF_DEQUEUE(&ifp->if_snd, m_head); 3118 if (m_head == NULL) 3119 break; 3120 3121 if (sc->dc_flags & DC_TX_COALESCE && 3122 (m_head->m_next != NULL || 3123 sc->dc_flags & DC_TX_ALIGN)) { 3124 m = m_defrag(m_head, M_DONTWAIT); 3125 if (m == NULL) { 3126 IF_PREPEND(&ifp->if_snd, m_head); 3127 ifp->if_flags |= IFF_OACTIVE; 3128 break; 3129 } else { 3130 m_head = m; 3131 } 3132 } 3133 3134 if (dc_encap(sc, m_head, &idx)) { 3135 IF_PREPEND(&ifp->if_snd, m_head); 3136 ifp->if_flags |= IFF_OACTIVE; 3137 break; 3138 } 3139 3140 /* 3141 * If there's a BPF listener, bounce a copy of this frame 3142 * to him. 3143 */ 3144 BPF_MTAP(ifp, m_head); 3145 3146 if (sc->dc_flags & DC_TX_ONE) { 3147 ifp->if_flags |= IFF_OACTIVE; 3148 break; 3149 } 3150 } 3151 3152 /* Transmit */ 3153 sc->dc_cdata.dc_tx_prod = idx; 3154 if (!(sc->dc_flags & DC_TX_POLL)) 3155 CSR_WRITE_4(sc, DC_TXSTART, 0xFFFFFFFF); 3156 3157 /* 3158 * Set a timeout in case the chip goes out to lunch. 3159 */ 3160 ifp->if_timer = 5; 3161 3162 DC_UNLOCK(sc); 3163 } 3164 3165 static void 3166 dc_init(void *xsc) 3167 { 3168 struct dc_softc *sc = xsc; 3169 struct ifnet *ifp = &sc->arpcom.ac_if; 3170 struct mii_data *mii; 3171 3172 DC_LOCK(sc); 3173 3174 mii = device_get_softc(sc->dc_miibus); 3175 3176 /* 3177 * Cancel pending I/O and free all RX/TX buffers. 3178 */ 3179 dc_stop(sc); 3180 dc_reset(sc); 3181 3182 /* 3183 * Set cache alignment and burst length. 3184 */ 3185 if (DC_IS_ASIX(sc) || DC_IS_DAVICOM(sc)) 3186 CSR_WRITE_4(sc, DC_BUSCTL, 0); 3187 else 3188 CSR_WRITE_4(sc, DC_BUSCTL, DC_BUSCTL_MRME | DC_BUSCTL_MRLE); 3189 /* 3190 * Evenly share the bus between receive and transmit process. 3191 */ 3192 if (DC_IS_INTEL(sc)) 3193 DC_SETBIT(sc, DC_BUSCTL, DC_BUSCTL_ARBITRATION); 3194 if (DC_IS_DAVICOM(sc) || DC_IS_INTEL(sc)) { 3195 DC_SETBIT(sc, DC_BUSCTL, DC_BURSTLEN_USECA); 3196 } else { 3197 DC_SETBIT(sc, DC_BUSCTL, DC_BURSTLEN_16LONG); 3198 } 3199 if (sc->dc_flags & DC_TX_POLL) 3200 DC_SETBIT(sc, DC_BUSCTL, DC_TXPOLL_1); 3201 switch(sc->dc_cachesize) { 3202 case 32: 3203 DC_SETBIT(sc, DC_BUSCTL, DC_CACHEALIGN_32LONG); 3204 break; 3205 case 16: 3206 DC_SETBIT(sc, DC_BUSCTL, DC_CACHEALIGN_16LONG); 3207 break; 3208 case 8: 3209 DC_SETBIT(sc, DC_BUSCTL, DC_CACHEALIGN_8LONG); 3210 break; 3211 case 0: 3212 default: 3213 DC_SETBIT(sc, DC_BUSCTL, DC_CACHEALIGN_NONE); 3214 break; 3215 } 3216 3217 if (sc->dc_flags & DC_TX_STORENFWD) 3218 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_STORENFWD); 3219 else { 3220 if (sc->dc_txthresh > DC_TXTHRESH_MAX) { 3221 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_STORENFWD); 3222 } else { 3223 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_STORENFWD); 3224 DC_SETBIT(sc, DC_NETCFG, sc->dc_txthresh); 3225 } 3226 } 3227 3228 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_NO_RXCRC); 3229 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_TX_BACKOFF); 3230 3231 if (DC_IS_MACRONIX(sc) || DC_IS_PNICII(sc)) { 3232 /* 3233 * The app notes for the 98713 and 98715A say that 3234 * in order to have the chips operate properly, a magic 3235 * number must be written to CSR16. Macronix does not 3236 * document the meaning of these bits so there's no way 3237 * to know exactly what they do. The 98713 has a magic 3238 * number all its own; the rest all use a different one. 3239 */ 3240 DC_CLRBIT(sc, DC_MX_MAGICPACKET, 0xFFFF0000); 3241 if (sc->dc_type == DC_TYPE_98713) 3242 DC_SETBIT(sc, DC_MX_MAGICPACKET, DC_MX_MAGIC_98713); 3243 else 3244 DC_SETBIT(sc, DC_MX_MAGICPACKET, DC_MX_MAGIC_98715); 3245 } 3246 3247 if (DC_IS_XIRCOM(sc)) { 3248 /* 3249 * setup General Purpose Port mode and data so the tulip 3250 * can talk to the MII. 3251 */ 3252 CSR_WRITE_4(sc, DC_SIAGP, DC_SIAGP_WRITE_EN | DC_SIAGP_INT1_EN | 3253 DC_SIAGP_MD_GP2_OUTPUT | DC_SIAGP_MD_GP0_OUTPUT); 3254 DELAY(10); 3255 CSR_WRITE_4(sc, DC_SIAGP, DC_SIAGP_INT1_EN | 3256 DC_SIAGP_MD_GP2_OUTPUT | DC_SIAGP_MD_GP0_OUTPUT); 3257 DELAY(10); 3258 } 3259 3260 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_TX_THRESH); 3261 DC_SETBIT(sc, DC_NETCFG, DC_TXTHRESH_MIN); 3262 3263 /* Init circular RX list. */ 3264 if (dc_list_rx_init(sc) == ENOBUFS) { 3265 printf("dc%d: initialization failed: no " 3266 "memory for rx buffers\n", sc->dc_unit); 3267 dc_stop(sc); 3268 DC_UNLOCK(sc); 3269 return; 3270 } 3271 3272 /* 3273 * Init tx descriptors. 3274 */ 3275 dc_list_tx_init(sc); 3276 3277 /* 3278 * Load the address of the RX list. 3279 */ 3280 CSR_WRITE_4(sc, DC_RXADDR, vtophys(&sc->dc_ldata->dc_rx_list[0])); 3281 CSR_WRITE_4(sc, DC_TXADDR, vtophys(&sc->dc_ldata->dc_tx_list[0])); 3282 3283 /* 3284 * Enable interrupts. 3285 */ 3286 #ifdef DEVICE_POLLING 3287 /* 3288 * ... but only if we are not polling, and make sure they are off in 3289 * the case of polling. Some cards (e.g. fxp) turn interrupts on 3290 * after a reset. 3291 */ 3292 if (ifp->if_flags & IFF_POLLING) 3293 CSR_WRITE_4(sc, DC_IMR, 0x00000000); 3294 else 3295 #endif 3296 CSR_WRITE_4(sc, DC_IMR, DC_INTRS); 3297 CSR_WRITE_4(sc, DC_ISR, 0xFFFFFFFF); 3298 3299 /* Enable transmitter. */ 3300 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_TX_ON); 3301 3302 /* 3303 * If this is an Intel 21143 and we're not using the 3304 * MII port, program the LED control pins so we get 3305 * link and activity indications. 3306 */ 3307 if (sc->dc_flags & DC_TULIP_LEDS) { 3308 CSR_WRITE_4(sc, DC_WATCHDOG, 3309 DC_WDOG_CTLWREN | DC_WDOG_LINK | DC_WDOG_ACTIVITY); 3310 CSR_WRITE_4(sc, DC_WATCHDOG, 0); 3311 } 3312 3313 /* 3314 * Load the RX/multicast filter. We do this sort of late 3315 * because the filter programming scheme on the 21143 and 3316 * some clones requires DMAing a setup frame via the TX 3317 * engine, and we need the transmitter enabled for that. 3318 */ 3319 dc_setfilt(sc); 3320 3321 /* Enable receiver. */ 3322 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_ON); 3323 CSR_WRITE_4(sc, DC_RXSTART, 0xFFFFFFFF); 3324 3325 mii_mediachg(mii); 3326 dc_setcfg(sc, sc->dc_if_media); 3327 3328 ifp->if_flags |= IFF_RUNNING; 3329 ifp->if_flags &= ~IFF_OACTIVE; 3330 3331 /* Don't start the ticker if this is a homePNA link. */ 3332 if (IFM_SUBTYPE(mii->mii_media.ifm_media) == IFM_HPNA_1) 3333 sc->dc_link = 1; 3334 else { 3335 if (sc->dc_flags & DC_21143_NWAY) 3336 callout_reset(&sc->dc_stat_ch, hz/10, dc_tick, sc); 3337 else 3338 callout_reset(&sc->dc_stat_ch, hz, dc_tick, sc); 3339 } 3340 3341 #ifdef SRM_MEDIA 3342 if(sc->dc_srm_media) { 3343 struct ifreq ifr; 3344 3345 ifr.ifr_media = sc->dc_srm_media; 3346 ifmedia_ioctl(ifp, &ifr, &mii->mii_media, SIOCSIFMEDIA); 3347 sc->dc_srm_media = 0; 3348 } 3349 #endif 3350 DC_UNLOCK(sc); 3351 } 3352 3353 /* 3354 * Set media options. 3355 */ 3356 static int 3357 dc_ifmedia_upd(struct ifnet *ifp) 3358 { 3359 struct dc_softc *sc; 3360 struct mii_data *mii; 3361 struct ifmedia *ifm; 3362 3363 sc = ifp->if_softc; 3364 mii = device_get_softc(sc->dc_miibus); 3365 mii_mediachg(mii); 3366 ifm = &mii->mii_media; 3367 3368 if (DC_IS_DAVICOM(sc) && 3369 IFM_SUBTYPE(ifm->ifm_media) == IFM_HPNA_1) 3370 dc_setcfg(sc, ifm->ifm_media); 3371 else 3372 sc->dc_link = 0; 3373 3374 return (0); 3375 } 3376 3377 /* 3378 * Report current media status. 3379 */ 3380 static void 3381 dc_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 3382 { 3383 struct dc_softc *sc; 3384 struct mii_data *mii; 3385 struct ifmedia *ifm; 3386 3387 sc = ifp->if_softc; 3388 mii = device_get_softc(sc->dc_miibus); 3389 mii_pollstat(mii); 3390 ifm = &mii->mii_media; 3391 if (DC_IS_DAVICOM(sc)) { 3392 if (IFM_SUBTYPE(ifm->ifm_media) == IFM_HPNA_1) { 3393 ifmr->ifm_active = ifm->ifm_media; 3394 ifmr->ifm_status = 0; 3395 return; 3396 } 3397 } 3398 ifmr->ifm_active = mii->mii_media_active; 3399 ifmr->ifm_status = mii->mii_media_status; 3400 } 3401 3402 static int 3403 dc_ioctl(struct ifnet *ifp, u_long command, caddr_t data) 3404 { 3405 struct dc_softc *sc = ifp->if_softc; 3406 struct ifreq *ifr = (struct ifreq *)data; 3407 struct mii_data *mii; 3408 int error = 0; 3409 3410 DC_LOCK(sc); 3411 3412 switch (command) { 3413 case SIOCSIFFLAGS: 3414 if (ifp->if_flags & IFF_UP) { 3415 int need_setfilt = (ifp->if_flags ^ sc->dc_if_flags) & 3416 (IFF_PROMISC | IFF_ALLMULTI); 3417 3418 if (ifp->if_flags & IFF_RUNNING) { 3419 if (need_setfilt) 3420 dc_setfilt(sc); 3421 } else { 3422 sc->dc_txthresh = 0; 3423 dc_init(sc); 3424 } 3425 } else { 3426 if (ifp->if_flags & IFF_RUNNING) 3427 dc_stop(sc); 3428 } 3429 sc->dc_if_flags = ifp->if_flags; 3430 error = 0; 3431 break; 3432 case SIOCADDMULTI: 3433 case SIOCDELMULTI: 3434 dc_setfilt(sc); 3435 error = 0; 3436 break; 3437 case SIOCGIFMEDIA: 3438 case SIOCSIFMEDIA: 3439 mii = device_get_softc(sc->dc_miibus); 3440 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 3441 #ifdef SRM_MEDIA 3442 if (sc->dc_srm_media) 3443 sc->dc_srm_media = 0; 3444 #endif 3445 break; 3446 default: 3447 error = ether_ioctl(ifp, command, data); 3448 break; 3449 } 3450 3451 DC_UNLOCK(sc); 3452 3453 return (error); 3454 } 3455 3456 static void 3457 dc_watchdog(struct ifnet *ifp) 3458 { 3459 struct dc_softc *sc; 3460 3461 sc = ifp->if_softc; 3462 3463 DC_LOCK(sc); 3464 3465 ifp->if_oerrors++; 3466 printf("dc%d: watchdog timeout\n", sc->dc_unit); 3467 3468 dc_stop(sc); 3469 dc_reset(sc); 3470 dc_init(sc); 3471 3472 if (ifp->if_snd.ifq_head != NULL) 3473 dc_start(ifp); 3474 3475 DC_UNLOCK(sc); 3476 } 3477 3478 /* 3479 * Stop the adapter and free any mbufs allocated to the 3480 * RX and TX lists. 3481 */ 3482 static void 3483 dc_stop(struct dc_softc *sc) 3484 { 3485 int i; 3486 struct ifnet *ifp; 3487 3488 DC_LOCK(sc); 3489 3490 ifp = &sc->arpcom.ac_if; 3491 ifp->if_timer = 0; 3492 3493 callout_stop(&sc->dc_stat_ch); 3494 3495 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 3496 #ifdef DEVICE_POLLING 3497 ether_poll_deregister(ifp); 3498 #endif 3499 3500 DC_CLRBIT(sc, DC_NETCFG, (DC_NETCFG_RX_ON | DC_NETCFG_TX_ON)); 3501 CSR_WRITE_4(sc, DC_IMR, 0x00000000); 3502 CSR_WRITE_4(sc, DC_TXADDR, 0x00000000); 3503 CSR_WRITE_4(sc, DC_RXADDR, 0x00000000); 3504 sc->dc_link = 0; 3505 3506 /* 3507 * Free data in the RX lists. 3508 */ 3509 for (i = 0; i < DC_RX_LIST_CNT; i++) { 3510 if (sc->dc_cdata.dc_rx_chain[i] != NULL) { 3511 m_freem(sc->dc_cdata.dc_rx_chain[i]); 3512 sc->dc_cdata.dc_rx_chain[i] = NULL; 3513 } 3514 } 3515 bzero(&sc->dc_ldata->dc_rx_list, sizeof(sc->dc_ldata->dc_rx_list)); 3516 3517 /* 3518 * Free the TX list buffers. 3519 */ 3520 for (i = 0; i < DC_TX_LIST_CNT; i++) { 3521 if (sc->dc_cdata.dc_tx_chain[i] != NULL) { 3522 if (sc->dc_ldata->dc_tx_list[i].dc_ctl & 3523 DC_TXCTL_SETUP) { 3524 sc->dc_cdata.dc_tx_chain[i] = NULL; 3525 continue; 3526 } 3527 m_freem(sc->dc_cdata.dc_tx_chain[i]); 3528 sc->dc_cdata.dc_tx_chain[i] = NULL; 3529 } 3530 } 3531 3532 bzero(&sc->dc_ldata->dc_tx_list, sizeof(sc->dc_ldata->dc_tx_list)); 3533 3534 DC_UNLOCK(sc); 3535 } 3536 3537 /* 3538 * Device suspend routine. Stop the interface and save some PCI 3539 * settings in case the BIOS doesn't restore them properly on 3540 * resume. 3541 */ 3542 static int 3543 dc_suspend(device_t dev) 3544 { 3545 struct dc_softc *sc; 3546 int i, s; 3547 3548 s = splimp(); 3549 3550 sc = device_get_softc(dev); 3551 3552 dc_stop(sc); 3553 3554 for (i = 0; i < 5; i++) 3555 sc->saved_maps[i] = pci_read_config(dev, PCIR_MAPS + i * 4, 4); 3556 sc->saved_biosaddr = pci_read_config(dev, PCIR_BIOS, 4); 3557 sc->saved_intline = pci_read_config(dev, PCIR_INTLINE, 1); 3558 sc->saved_cachelnsz = pci_read_config(dev, PCIR_CACHELNSZ, 1); 3559 sc->saved_lattimer = pci_read_config(dev, PCIR_LATTIMER, 1); 3560 3561 sc->suspended = 1; 3562 3563 splx(s); 3564 return (0); 3565 } 3566 3567 /* 3568 * Device resume routine. Restore some PCI settings in case the BIOS 3569 * doesn't, re-enable busmastering, and restart the interface if 3570 * appropriate. 3571 */ 3572 static int 3573 dc_resume(device_t dev) 3574 { 3575 struct dc_softc *sc; 3576 struct ifnet *ifp; 3577 int i, s; 3578 3579 s = splimp(); 3580 3581 sc = device_get_softc(dev); 3582 ifp = &sc->arpcom.ac_if; 3583 3584 dc_acpi(dev); 3585 3586 /* better way to do this? */ 3587 for (i = 0; i < 5; i++) 3588 pci_write_config(dev, PCIR_MAPS + i * 4, sc->saved_maps[i], 4); 3589 pci_write_config(dev, PCIR_BIOS, sc->saved_biosaddr, 4); 3590 pci_write_config(dev, PCIR_INTLINE, sc->saved_intline, 1); 3591 pci_write_config(dev, PCIR_CACHELNSZ, sc->saved_cachelnsz, 1); 3592 pci_write_config(dev, PCIR_LATTIMER, sc->saved_lattimer, 1); 3593 3594 /* reenable busmastering */ 3595 pci_enable_busmaster(dev); 3596 pci_enable_io(dev, DC_RES); 3597 3598 /* reinitialize interface if necessary */ 3599 if (ifp->if_flags & IFF_UP) 3600 dc_init(sc); 3601 3602 sc->suspended = 0; 3603 3604 splx(s); 3605 return (0); 3606 } 3607 3608 /* 3609 * Stop all chip I/O so that the kernel's probe routines don't 3610 * get confused by errant DMAs when rebooting. 3611 */ 3612 static void 3613 dc_shutdown(device_t dev) 3614 { 3615 struct dc_softc *sc; 3616 3617 sc = device_get_softc(dev); 3618 3619 dc_stop(sc); 3620 } 3621