1 /*- 2 * Copyright (c) 1997, 1998, 1999 3 * Bill Paul <wpaul@ee.columbia.edu>. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 3. All advertising materials mentioning features or use of this software 14 * must display the following acknowledgement: 15 * This product includes software developed by Bill Paul. 16 * 4. Neither the name of the author nor the names of any co-contributors 17 * may be used to endorse or promote products derived from this software 18 * without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30 * THE POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33 #include <sys/cdefs.h> 34 __FBSDID("$FreeBSD$"); 35 36 /* 37 * DEC "tulip" clone ethernet driver. Supports the DEC/Intel 21143 38 * series chips and several workalikes including the following: 39 * 40 * Macronix 98713/98715/98725/98727/98732 PMAC (www.macronix.com) 41 * Macronix/Lite-On 82c115 PNIC II (www.macronix.com) 42 * Lite-On 82c168/82c169 PNIC (www.litecom.com) 43 * ASIX Electronics AX88140A (www.asix.com.tw) 44 * ASIX Electronics AX88141 (www.asix.com.tw) 45 * ADMtek AL981 (www.admtek.com.tw) 46 * ADMtek AN985 (www.admtek.com.tw) 47 * Netgear FA511 (www.netgear.com) Appears to be rebadged ADMTek AN985 48 * Davicom DM9100, DM9102, DM9102A (www.davicom8.com) 49 * Accton EN1217 (www.accton.com) 50 * Xircom X3201 (www.xircom.com) 51 * Abocom FE2500 52 * Conexant LANfinity (www.conexant.com) 53 * 3Com OfficeConnect 10/100B 3CSOHO100B (www.3com.com) 54 * 55 * Datasheets for the 21143 are available at developer.intel.com. 56 * Datasheets for the clone parts can be found at their respective sites. 57 * (Except for the PNIC; see www.freebsd.org/~wpaul/PNIC/pnic.ps.gz.) 58 * The PNIC II is essentially a Macronix 98715A chip; the only difference 59 * worth noting is that its multicast hash table is only 128 bits wide 60 * instead of 512. 61 * 62 * Written by Bill Paul <wpaul@ee.columbia.edu> 63 * Electrical Engineering Department 64 * Columbia University, New York City 65 */ 66 /* 67 * The Intel 21143 is the successor to the DEC 21140. It is basically 68 * the same as the 21140 but with a few new features. The 21143 supports 69 * three kinds of media attachments: 70 * 71 * o MII port, for 10Mbps and 100Mbps support and NWAY 72 * autonegotiation provided by an external PHY. 73 * o SYM port, for symbol mode 100Mbps support. 74 * o 10baseT port. 75 * o AUI/BNC port. 76 * 77 * The 100Mbps SYM port and 10baseT port can be used together in 78 * combination with the internal NWAY support to create a 10/100 79 * autosensing configuration. 80 * 81 * Note that not all tulip workalikes are handled in this driver: we only 82 * deal with those which are relatively well behaved. The Winbond is 83 * handled separately due to its different register offsets and the 84 * special handling needed for its various bugs. The PNIC is handled 85 * here, but I'm not thrilled about it. 86 * 87 * All of the workalike chips use some form of MII transceiver support 88 * with the exception of the Macronix chips, which also have a SYM port. 89 * The ASIX AX88140A is also documented to have a SYM port, but all 90 * the cards I've seen use an MII transceiver, probably because the 91 * AX88140A doesn't support internal NWAY. 92 */ 93 94 #include <sys/param.h> 95 #include <sys/endian.h> 96 #include <sys/systm.h> 97 #include <sys/sockio.h> 98 #include <sys/mbuf.h> 99 #include <sys/malloc.h> 100 #include <sys/kernel.h> 101 #include <sys/module.h> 102 #include <sys/socket.h> 103 #include <sys/sysctl.h> 104 105 #include <net/if.h> 106 #include <net/if_arp.h> 107 #include <net/ethernet.h> 108 #include <net/if_dl.h> 109 #include <net/if_media.h> 110 #include <net/if_types.h> 111 #include <net/if_vlan_var.h> 112 113 #include <net/bpf.h> 114 115 #include <machine/bus.h> 116 #include <machine/resource.h> 117 #include <sys/bus.h> 118 #include <sys/rman.h> 119 120 #include <dev/mii/mii.h> 121 #include <dev/mii/miivar.h> 122 123 #include <dev/pci/pcireg.h> 124 #include <dev/pci/pcivar.h> 125 126 #define DC_USEIOSPACE 127 #ifdef __alpha__ 128 #define SRM_MEDIA 129 #endif 130 131 #include <pci/if_dcreg.h> 132 133 #ifdef __sparc64__ 134 #include <dev/ofw/openfirm.h> 135 #include <machine/ofw_machdep.h> 136 #endif 137 138 MODULE_DEPEND(dc, pci, 1, 1, 1); 139 MODULE_DEPEND(dc, ether, 1, 1, 1); 140 MODULE_DEPEND(dc, miibus, 1, 1, 1); 141 142 /* 143 * "device miibus" is required in kernel config. See GENERIC if you get 144 * errors here. 145 */ 146 #include "miibus_if.h" 147 148 /* 149 * Various supported device vendors/types and their names. 150 */ 151 static struct dc_type dc_devs[] = { 152 { DC_VENDORID_DEC, DC_DEVICEID_21143, 153 "Intel 21143 10/100BaseTX" }, 154 { DC_VENDORID_DAVICOM, DC_DEVICEID_DM9009, 155 "Davicom DM9009 10/100BaseTX" }, 156 { DC_VENDORID_DAVICOM, DC_DEVICEID_DM9100, 157 "Davicom DM9100 10/100BaseTX" }, 158 { DC_VENDORID_DAVICOM, DC_DEVICEID_DM9102, 159 "Davicom DM9102 10/100BaseTX" }, 160 { DC_VENDORID_DAVICOM, DC_DEVICEID_DM9102, 161 "Davicom DM9102A 10/100BaseTX" }, 162 { DC_VENDORID_ADMTEK, DC_DEVICEID_AL981, 163 "ADMtek AL981 10/100BaseTX" }, 164 { DC_VENDORID_ADMTEK, DC_DEVICEID_AN985, 165 "ADMtek AN985 10/100BaseTX" }, 166 { DC_VENDORID_ADMTEK, DC_DEVICEID_ADM9511, 167 "ADMtek ADM9511 10/100BaseTX" }, 168 { DC_VENDORID_ADMTEK, DC_DEVICEID_ADM9513, 169 "ADMtek ADM9513 10/100BaseTX" }, 170 { DC_VENDORID_ADMTEK, DC_DEVICEID_FA511, 171 "Netgear FA511 10/100BaseTX" }, 172 { DC_VENDORID_ASIX, DC_DEVICEID_AX88140A, 173 "ASIX AX88140A 10/100BaseTX" }, 174 { DC_VENDORID_ASIX, DC_DEVICEID_AX88140A, 175 "ASIX AX88141 10/100BaseTX" }, 176 { DC_VENDORID_MX, DC_DEVICEID_98713, 177 "Macronix 98713 10/100BaseTX" }, 178 { DC_VENDORID_MX, DC_DEVICEID_98713, 179 "Macronix 98713A 10/100BaseTX" }, 180 { DC_VENDORID_CP, DC_DEVICEID_98713_CP, 181 "Compex RL100-TX 10/100BaseTX" }, 182 { DC_VENDORID_CP, DC_DEVICEID_98713_CP, 183 "Compex RL100-TX 10/100BaseTX" }, 184 { DC_VENDORID_MX, DC_DEVICEID_987x5, 185 "Macronix 98715/98715A 10/100BaseTX" }, 186 { DC_VENDORID_MX, DC_DEVICEID_987x5, 187 "Macronix 98715AEC-C 10/100BaseTX" }, 188 { DC_VENDORID_MX, DC_DEVICEID_987x5, 189 "Macronix 98725 10/100BaseTX" }, 190 { DC_VENDORID_MX, DC_DEVICEID_98727, 191 "Macronix 98727/98732 10/100BaseTX" }, 192 { DC_VENDORID_LO, DC_DEVICEID_82C115, 193 "LC82C115 PNIC II 10/100BaseTX" }, 194 { DC_VENDORID_LO, DC_DEVICEID_82C168, 195 "82c168 PNIC 10/100BaseTX" }, 196 { DC_VENDORID_LO, DC_DEVICEID_82C168, 197 "82c169 PNIC 10/100BaseTX" }, 198 { DC_VENDORID_ACCTON, DC_DEVICEID_EN1217, 199 "Accton EN1217 10/100BaseTX" }, 200 { DC_VENDORID_ACCTON, DC_DEVICEID_EN2242, 201 "Accton EN2242 MiniPCI 10/100BaseTX" }, 202 { DC_VENDORID_XIRCOM, DC_DEVICEID_X3201, 203 "Xircom X3201 10/100BaseTX" }, 204 { DC_VENDORID_ABOCOM, DC_DEVICEID_FE2500, 205 "Abocom FE2500 10/100BaseTX" }, 206 { DC_VENDORID_ABOCOM, DC_DEVICEID_FE2500MX, 207 "Abocom FE2500MX 10/100BaseTX" }, 208 { DC_VENDORID_CONEXANT, DC_DEVICEID_RS7112, 209 "Conexant LANfinity MiniPCI 10/100BaseTX" }, 210 { DC_VENDORID_HAWKING, DC_DEVICEID_HAWKING_PN672TX, 211 "Hawking CB102 CardBus 10/100" }, 212 { DC_VENDORID_PLANEX, DC_DEVICEID_FNW3602T, 213 "PlaneX FNW-3602-T CardBus 10/100" }, 214 { DC_VENDORID_3COM, DC_DEVICEID_3CSOHOB, 215 "3Com OfficeConnect 10/100B" }, 216 { DC_VENDORID_MICROSOFT, DC_DEVICEID_MSMN120, 217 "Microsoft MN-120 CardBus 10/100" }, 218 { DC_VENDORID_MICROSOFT, DC_DEVICEID_MSMN130, 219 "Microsoft MN-130 10/100" }, 220 { DC_VENDORID_MICROSOFT, DC_DEVICEID_MSMN130_FAKE, 221 "Microsoft MN-130 10/100" }, 222 { 0, 0, NULL } 223 }; 224 225 static int dc_probe(device_t); 226 static int dc_attach(device_t); 227 static int dc_detach(device_t); 228 static int dc_suspend(device_t); 229 static int dc_resume(device_t); 230 static struct dc_type *dc_devtype(device_t); 231 static int dc_newbuf(struct dc_softc *, int, int); 232 static int dc_encap(struct dc_softc *, struct mbuf **); 233 static void dc_pnic_rx_bug_war(struct dc_softc *, int); 234 static int dc_rx_resync(struct dc_softc *); 235 static void dc_rxeof(struct dc_softc *); 236 static void dc_txeof(struct dc_softc *); 237 static void dc_tick(void *); 238 static void dc_tx_underrun(struct dc_softc *); 239 static void dc_intr(void *); 240 static void dc_start(struct ifnet *); 241 static void dc_start_locked(struct ifnet *); 242 static int dc_ioctl(struct ifnet *, u_long, caddr_t); 243 static void dc_init(void *); 244 static void dc_init_locked(struct dc_softc *); 245 static void dc_stop(struct dc_softc *); 246 static void dc_watchdog(struct ifnet *); 247 static void dc_shutdown(device_t); 248 static int dc_ifmedia_upd(struct ifnet *); 249 static void dc_ifmedia_sts(struct ifnet *, struct ifmediareq *); 250 251 static void dc_delay(struct dc_softc *); 252 static void dc_eeprom_idle(struct dc_softc *); 253 static void dc_eeprom_putbyte(struct dc_softc *, int); 254 static void dc_eeprom_getword(struct dc_softc *, int, u_int16_t *); 255 static void dc_eeprom_getword_pnic(struct dc_softc *, int, u_int16_t *); 256 static void dc_eeprom_getword_xircom(struct dc_softc *, int, u_int16_t *); 257 static void dc_eeprom_width(struct dc_softc *); 258 static void dc_read_eeprom(struct dc_softc *, caddr_t, int, int, int); 259 260 static void dc_mii_writebit(struct dc_softc *, int); 261 static int dc_mii_readbit(struct dc_softc *); 262 static void dc_mii_sync(struct dc_softc *); 263 static void dc_mii_send(struct dc_softc *, u_int32_t, int); 264 static int dc_mii_readreg(struct dc_softc *, struct dc_mii_frame *); 265 static int dc_mii_writereg(struct dc_softc *, struct dc_mii_frame *); 266 static int dc_miibus_readreg(device_t, int, int); 267 static int dc_miibus_writereg(device_t, int, int, int); 268 static void dc_miibus_statchg(device_t); 269 static void dc_miibus_mediainit(device_t); 270 271 static void dc_setcfg(struct dc_softc *, int); 272 static uint32_t dc_mchash_le(struct dc_softc *, const uint8_t *); 273 static uint32_t dc_mchash_be(const uint8_t *); 274 static void dc_setfilt_21143(struct dc_softc *); 275 static void dc_setfilt_asix(struct dc_softc *); 276 static void dc_setfilt_admtek(struct dc_softc *); 277 static void dc_setfilt_xircom(struct dc_softc *); 278 279 static void dc_setfilt(struct dc_softc *); 280 281 static void dc_reset(struct dc_softc *); 282 static int dc_list_rx_init(struct dc_softc *); 283 static int dc_list_tx_init(struct dc_softc *); 284 285 static void dc_read_srom(struct dc_softc *, int); 286 static void dc_parse_21143_srom(struct dc_softc *); 287 static void dc_decode_leaf_sia(struct dc_softc *, struct dc_eblock_sia *); 288 static void dc_decode_leaf_mii(struct dc_softc *, struct dc_eblock_mii *); 289 static void dc_decode_leaf_sym(struct dc_softc *, struct dc_eblock_sym *); 290 static void dc_apply_fixup(struct dc_softc *, int); 291 292 static void dc_dma_map_txbuf(void *, bus_dma_segment_t *, int, bus_size_t, int); 293 static void dc_dma_map_rxbuf(void *, bus_dma_segment_t *, int, bus_size_t, int); 294 295 #ifdef DC_USEIOSPACE 296 #define DC_RES SYS_RES_IOPORT 297 #define DC_RID DC_PCI_CFBIO 298 #else 299 #define DC_RES SYS_RES_MEMORY 300 #define DC_RID DC_PCI_CFBMA 301 #endif 302 303 static device_method_t dc_methods[] = { 304 /* Device interface */ 305 DEVMETHOD(device_probe, dc_probe), 306 DEVMETHOD(device_attach, dc_attach), 307 DEVMETHOD(device_detach, dc_detach), 308 DEVMETHOD(device_suspend, dc_suspend), 309 DEVMETHOD(device_resume, dc_resume), 310 DEVMETHOD(device_shutdown, dc_shutdown), 311 312 /* bus interface */ 313 DEVMETHOD(bus_print_child, bus_generic_print_child), 314 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 315 316 /* MII interface */ 317 DEVMETHOD(miibus_readreg, dc_miibus_readreg), 318 DEVMETHOD(miibus_writereg, dc_miibus_writereg), 319 DEVMETHOD(miibus_statchg, dc_miibus_statchg), 320 DEVMETHOD(miibus_mediainit, dc_miibus_mediainit), 321 322 { 0, 0 } 323 }; 324 325 static driver_t dc_driver = { 326 "dc", 327 dc_methods, 328 sizeof(struct dc_softc) 329 }; 330 331 static devclass_t dc_devclass; 332 #ifdef __i386__ 333 static int dc_quick = 1; 334 SYSCTL_INT(_hw, OID_AUTO, dc_quick, CTLFLAG_RW, &dc_quick, 0, 335 "do not m_devget() in dc driver"); 336 #endif 337 338 DRIVER_MODULE(dc, cardbus, dc_driver, dc_devclass, 0, 0); 339 DRIVER_MODULE(dc, pci, dc_driver, dc_devclass, 0, 0); 340 DRIVER_MODULE(miibus, dc, miibus_driver, miibus_devclass, 0, 0); 341 342 #define DC_SETBIT(sc, reg, x) \ 343 CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) | (x)) 344 345 #define DC_CLRBIT(sc, reg, x) \ 346 CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) & ~(x)) 347 348 #define SIO_SET(x) DC_SETBIT(sc, DC_SIO, (x)) 349 #define SIO_CLR(x) DC_CLRBIT(sc, DC_SIO, (x)) 350 351 static void 352 dc_delay(struct dc_softc *sc) 353 { 354 int idx; 355 356 for (idx = (300 / 33) + 1; idx > 0; idx--) 357 CSR_READ_4(sc, DC_BUSCTL); 358 } 359 360 static void 361 dc_eeprom_width(struct dc_softc *sc) 362 { 363 int i; 364 365 /* Force EEPROM to idle state. */ 366 dc_eeprom_idle(sc); 367 368 /* Enter EEPROM access mode. */ 369 CSR_WRITE_4(sc, DC_SIO, DC_SIO_EESEL); 370 dc_delay(sc); 371 DC_SETBIT(sc, DC_SIO, DC_SIO_ROMCTL_READ); 372 dc_delay(sc); 373 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); 374 dc_delay(sc); 375 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CS); 376 dc_delay(sc); 377 378 for (i = 3; i--;) { 379 if (6 & (1 << i)) 380 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_DATAIN); 381 else 382 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_DATAIN); 383 dc_delay(sc); 384 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CLK); 385 dc_delay(sc); 386 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); 387 dc_delay(sc); 388 } 389 390 for (i = 1; i <= 12; i++) { 391 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CLK); 392 dc_delay(sc); 393 if (!(CSR_READ_4(sc, DC_SIO) & DC_SIO_EE_DATAOUT)) { 394 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); 395 dc_delay(sc); 396 break; 397 } 398 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); 399 dc_delay(sc); 400 } 401 402 /* Turn off EEPROM access mode. */ 403 dc_eeprom_idle(sc); 404 405 if (i < 4 || i > 12) 406 sc->dc_romwidth = 6; 407 else 408 sc->dc_romwidth = i; 409 410 /* Enter EEPROM access mode. */ 411 CSR_WRITE_4(sc, DC_SIO, DC_SIO_EESEL); 412 dc_delay(sc); 413 DC_SETBIT(sc, DC_SIO, DC_SIO_ROMCTL_READ); 414 dc_delay(sc); 415 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); 416 dc_delay(sc); 417 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CS); 418 dc_delay(sc); 419 420 /* Turn off EEPROM access mode. */ 421 dc_eeprom_idle(sc); 422 } 423 424 static void 425 dc_eeprom_idle(struct dc_softc *sc) 426 { 427 int i; 428 429 CSR_WRITE_4(sc, DC_SIO, DC_SIO_EESEL); 430 dc_delay(sc); 431 DC_SETBIT(sc, DC_SIO, DC_SIO_ROMCTL_READ); 432 dc_delay(sc); 433 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); 434 dc_delay(sc); 435 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CS); 436 dc_delay(sc); 437 438 for (i = 0; i < 25; i++) { 439 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); 440 dc_delay(sc); 441 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CLK); 442 dc_delay(sc); 443 } 444 445 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); 446 dc_delay(sc); 447 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CS); 448 dc_delay(sc); 449 CSR_WRITE_4(sc, DC_SIO, 0x00000000); 450 } 451 452 /* 453 * Send a read command and address to the EEPROM, check for ACK. 454 */ 455 static void 456 dc_eeprom_putbyte(struct dc_softc *sc, int addr) 457 { 458 int d, i; 459 460 d = DC_EECMD_READ >> 6; 461 for (i = 3; i--; ) { 462 if (d & (1 << i)) 463 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_DATAIN); 464 else 465 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_DATAIN); 466 dc_delay(sc); 467 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CLK); 468 dc_delay(sc); 469 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); 470 dc_delay(sc); 471 } 472 473 /* 474 * Feed in each bit and strobe the clock. 475 */ 476 for (i = sc->dc_romwidth; i--;) { 477 if (addr & (1 << i)) { 478 SIO_SET(DC_SIO_EE_DATAIN); 479 } else { 480 SIO_CLR(DC_SIO_EE_DATAIN); 481 } 482 dc_delay(sc); 483 SIO_SET(DC_SIO_EE_CLK); 484 dc_delay(sc); 485 SIO_CLR(DC_SIO_EE_CLK); 486 dc_delay(sc); 487 } 488 } 489 490 /* 491 * Read a word of data stored in the EEPROM at address 'addr.' 492 * The PNIC 82c168/82c169 has its own non-standard way to read 493 * the EEPROM. 494 */ 495 static void 496 dc_eeprom_getword_pnic(struct dc_softc *sc, int addr, u_int16_t *dest) 497 { 498 int i; 499 u_int32_t r; 500 501 CSR_WRITE_4(sc, DC_PN_SIOCTL, DC_PN_EEOPCODE_READ | addr); 502 503 for (i = 0; i < DC_TIMEOUT; i++) { 504 DELAY(1); 505 r = CSR_READ_4(sc, DC_SIO); 506 if (!(r & DC_PN_SIOCTL_BUSY)) { 507 *dest = (u_int16_t)(r & 0xFFFF); 508 return; 509 } 510 } 511 } 512 513 /* 514 * Read a word of data stored in the EEPROM at address 'addr.' 515 * The Xircom X3201 has its own non-standard way to read 516 * the EEPROM, too. 517 */ 518 static void 519 dc_eeprom_getword_xircom(struct dc_softc *sc, int addr, u_int16_t *dest) 520 { 521 522 SIO_SET(DC_SIO_ROMSEL | DC_SIO_ROMCTL_READ); 523 524 addr *= 2; 525 CSR_WRITE_4(sc, DC_ROM, addr | 0x160); 526 *dest = (u_int16_t)CSR_READ_4(sc, DC_SIO) & 0xff; 527 addr += 1; 528 CSR_WRITE_4(sc, DC_ROM, addr | 0x160); 529 *dest |= ((u_int16_t)CSR_READ_4(sc, DC_SIO) & 0xff) << 8; 530 531 SIO_CLR(DC_SIO_ROMSEL | DC_SIO_ROMCTL_READ); 532 } 533 534 /* 535 * Read a word of data stored in the EEPROM at address 'addr.' 536 */ 537 static void 538 dc_eeprom_getword(struct dc_softc *sc, int addr, u_int16_t *dest) 539 { 540 int i; 541 u_int16_t word = 0; 542 543 /* Force EEPROM to idle state. */ 544 dc_eeprom_idle(sc); 545 546 /* Enter EEPROM access mode. */ 547 CSR_WRITE_4(sc, DC_SIO, DC_SIO_EESEL); 548 dc_delay(sc); 549 DC_SETBIT(sc, DC_SIO, DC_SIO_ROMCTL_READ); 550 dc_delay(sc); 551 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); 552 dc_delay(sc); 553 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CS); 554 dc_delay(sc); 555 556 /* 557 * Send address of word we want to read. 558 */ 559 dc_eeprom_putbyte(sc, addr); 560 561 /* 562 * Start reading bits from EEPROM. 563 */ 564 for (i = 0x8000; i; i >>= 1) { 565 SIO_SET(DC_SIO_EE_CLK); 566 dc_delay(sc); 567 if (CSR_READ_4(sc, DC_SIO) & DC_SIO_EE_DATAOUT) 568 word |= i; 569 dc_delay(sc); 570 SIO_CLR(DC_SIO_EE_CLK); 571 dc_delay(sc); 572 } 573 574 /* Turn off EEPROM access mode. */ 575 dc_eeprom_idle(sc); 576 577 *dest = word; 578 } 579 580 /* 581 * Read a sequence of words from the EEPROM. 582 */ 583 static void 584 dc_read_eeprom(struct dc_softc *sc, caddr_t dest, int off, int cnt, int be) 585 { 586 int i; 587 u_int16_t word = 0, *ptr; 588 589 for (i = 0; i < cnt; i++) { 590 if (DC_IS_PNIC(sc)) 591 dc_eeprom_getword_pnic(sc, off + i, &word); 592 else if (DC_IS_XIRCOM(sc)) 593 dc_eeprom_getword_xircom(sc, off + i, &word); 594 else 595 dc_eeprom_getword(sc, off + i, &word); 596 ptr = (u_int16_t *)(dest + (i * 2)); 597 if (be) 598 *ptr = be16toh(word); 599 else 600 *ptr = le16toh(word); 601 } 602 } 603 604 /* 605 * The following two routines are taken from the Macronix 98713 606 * Application Notes pp.19-21. 607 */ 608 /* 609 * Write a bit to the MII bus. 610 */ 611 static void 612 dc_mii_writebit(struct dc_softc *sc, int bit) 613 { 614 615 if (bit) 616 CSR_WRITE_4(sc, DC_SIO, 617 DC_SIO_ROMCTL_WRITE | DC_SIO_MII_DATAOUT); 618 else 619 CSR_WRITE_4(sc, DC_SIO, DC_SIO_ROMCTL_WRITE); 620 621 DC_SETBIT(sc, DC_SIO, DC_SIO_MII_CLK); 622 DC_CLRBIT(sc, DC_SIO, DC_SIO_MII_CLK); 623 } 624 625 /* 626 * Read a bit from the MII bus. 627 */ 628 static int 629 dc_mii_readbit(struct dc_softc *sc) 630 { 631 632 CSR_WRITE_4(sc, DC_SIO, DC_SIO_ROMCTL_READ | DC_SIO_MII_DIR); 633 CSR_READ_4(sc, DC_SIO); 634 DC_SETBIT(sc, DC_SIO, DC_SIO_MII_CLK); 635 DC_CLRBIT(sc, DC_SIO, DC_SIO_MII_CLK); 636 if (CSR_READ_4(sc, DC_SIO) & DC_SIO_MII_DATAIN) 637 return (1); 638 639 return (0); 640 } 641 642 /* 643 * Sync the PHYs by setting data bit and strobing the clock 32 times. 644 */ 645 static void 646 dc_mii_sync(struct dc_softc *sc) 647 { 648 int i; 649 650 CSR_WRITE_4(sc, DC_SIO, DC_SIO_ROMCTL_WRITE); 651 652 for (i = 0; i < 32; i++) 653 dc_mii_writebit(sc, 1); 654 } 655 656 /* 657 * Clock a series of bits through the MII. 658 */ 659 static void 660 dc_mii_send(struct dc_softc *sc, u_int32_t bits, int cnt) 661 { 662 int i; 663 664 for (i = (0x1 << (cnt - 1)); i; i >>= 1) 665 dc_mii_writebit(sc, bits & i); 666 } 667 668 /* 669 * Read an PHY register through the MII. 670 */ 671 static int 672 dc_mii_readreg(struct dc_softc *sc, struct dc_mii_frame *frame) 673 { 674 int i, ack; 675 676 /* 677 * Set up frame for RX. 678 */ 679 frame->mii_stdelim = DC_MII_STARTDELIM; 680 frame->mii_opcode = DC_MII_READOP; 681 frame->mii_turnaround = 0; 682 frame->mii_data = 0; 683 684 /* 685 * Sync the PHYs. 686 */ 687 dc_mii_sync(sc); 688 689 /* 690 * Send command/address info. 691 */ 692 dc_mii_send(sc, frame->mii_stdelim, 2); 693 dc_mii_send(sc, frame->mii_opcode, 2); 694 dc_mii_send(sc, frame->mii_phyaddr, 5); 695 dc_mii_send(sc, frame->mii_regaddr, 5); 696 697 #ifdef notdef 698 /* Idle bit */ 699 dc_mii_writebit(sc, 1); 700 dc_mii_writebit(sc, 0); 701 #endif 702 703 /* Check for ack. */ 704 ack = dc_mii_readbit(sc); 705 706 /* 707 * Now try reading data bits. If the ack failed, we still 708 * need to clock through 16 cycles to keep the PHY(s) in sync. 709 */ 710 if (ack) { 711 for (i = 0; i < 16; i++) 712 dc_mii_readbit(sc); 713 goto fail; 714 } 715 716 for (i = 0x8000; i; i >>= 1) { 717 if (!ack) { 718 if (dc_mii_readbit(sc)) 719 frame->mii_data |= i; 720 } 721 } 722 723 fail: 724 725 dc_mii_writebit(sc, 0); 726 dc_mii_writebit(sc, 0); 727 728 if (ack) 729 return (1); 730 return (0); 731 } 732 733 /* 734 * Write to a PHY register through the MII. 735 */ 736 static int 737 dc_mii_writereg(struct dc_softc *sc, struct dc_mii_frame *frame) 738 { 739 740 /* 741 * Set up frame for TX. 742 */ 743 744 frame->mii_stdelim = DC_MII_STARTDELIM; 745 frame->mii_opcode = DC_MII_WRITEOP; 746 frame->mii_turnaround = DC_MII_TURNAROUND; 747 748 /* 749 * Sync the PHYs. 750 */ 751 dc_mii_sync(sc); 752 753 dc_mii_send(sc, frame->mii_stdelim, 2); 754 dc_mii_send(sc, frame->mii_opcode, 2); 755 dc_mii_send(sc, frame->mii_phyaddr, 5); 756 dc_mii_send(sc, frame->mii_regaddr, 5); 757 dc_mii_send(sc, frame->mii_turnaround, 2); 758 dc_mii_send(sc, frame->mii_data, 16); 759 760 /* Idle bit. */ 761 dc_mii_writebit(sc, 0); 762 dc_mii_writebit(sc, 0); 763 764 return (0); 765 } 766 767 static int 768 dc_miibus_readreg(device_t dev, int phy, int reg) 769 { 770 struct dc_mii_frame frame; 771 struct dc_softc *sc; 772 int i, rval, phy_reg = 0; 773 774 sc = device_get_softc(dev); 775 bzero(&frame, sizeof(frame)); 776 777 /* 778 * Note: both the AL981 and AN985 have internal PHYs, 779 * however the AL981 provides direct access to the PHY 780 * registers while the AN985 uses a serial MII interface. 781 * The AN985's MII interface is also buggy in that you 782 * can read from any MII address (0 to 31), but only address 1 783 * behaves normally. To deal with both cases, we pretend 784 * that the PHY is at MII address 1. 785 */ 786 if (DC_IS_ADMTEK(sc) && phy != DC_ADMTEK_PHYADDR) 787 return (0); 788 789 /* 790 * Note: the ukphy probes of the RS7112 report a PHY at 791 * MII address 0 (possibly HomePNA?) and 1 (ethernet) 792 * so we only respond to correct one. 793 */ 794 if (DC_IS_CONEXANT(sc) && phy != DC_CONEXANT_PHYADDR) 795 return (0); 796 797 if (sc->dc_pmode != DC_PMODE_MII) { 798 if (phy == (MII_NPHY - 1)) { 799 switch (reg) { 800 case MII_BMSR: 801 /* 802 * Fake something to make the probe 803 * code think there's a PHY here. 804 */ 805 return (BMSR_MEDIAMASK); 806 break; 807 case MII_PHYIDR1: 808 if (DC_IS_PNIC(sc)) 809 return (DC_VENDORID_LO); 810 return (DC_VENDORID_DEC); 811 break; 812 case MII_PHYIDR2: 813 if (DC_IS_PNIC(sc)) 814 return (DC_DEVICEID_82C168); 815 return (DC_DEVICEID_21143); 816 break; 817 default: 818 return (0); 819 break; 820 } 821 } else 822 return (0); 823 } 824 825 if (DC_IS_PNIC(sc)) { 826 CSR_WRITE_4(sc, DC_PN_MII, DC_PN_MIIOPCODE_READ | 827 (phy << 23) | (reg << 18)); 828 for (i = 0; i < DC_TIMEOUT; i++) { 829 DELAY(1); 830 rval = CSR_READ_4(sc, DC_PN_MII); 831 if (!(rval & DC_PN_MII_BUSY)) { 832 rval &= 0xFFFF; 833 return (rval == 0xFFFF ? 0 : rval); 834 } 835 } 836 return (0); 837 } 838 839 if (DC_IS_COMET(sc)) { 840 switch (reg) { 841 case MII_BMCR: 842 phy_reg = DC_AL_BMCR; 843 break; 844 case MII_BMSR: 845 phy_reg = DC_AL_BMSR; 846 break; 847 case MII_PHYIDR1: 848 phy_reg = DC_AL_VENID; 849 break; 850 case MII_PHYIDR2: 851 phy_reg = DC_AL_DEVID; 852 break; 853 case MII_ANAR: 854 phy_reg = DC_AL_ANAR; 855 break; 856 case MII_ANLPAR: 857 phy_reg = DC_AL_LPAR; 858 break; 859 case MII_ANER: 860 phy_reg = DC_AL_ANER; 861 break; 862 default: 863 device_printf(dev, "phy_read: bad phy register %x\n", 864 reg); 865 return (0); 866 break; 867 } 868 869 rval = CSR_READ_4(sc, phy_reg) & 0x0000FFFF; 870 871 if (rval == 0xFFFF) 872 return (0); 873 return (rval); 874 } 875 876 frame.mii_phyaddr = phy; 877 frame.mii_regaddr = reg; 878 if (sc->dc_type == DC_TYPE_98713) { 879 phy_reg = CSR_READ_4(sc, DC_NETCFG); 880 CSR_WRITE_4(sc, DC_NETCFG, phy_reg & ~DC_NETCFG_PORTSEL); 881 } 882 dc_mii_readreg(sc, &frame); 883 if (sc->dc_type == DC_TYPE_98713) 884 CSR_WRITE_4(sc, DC_NETCFG, phy_reg); 885 886 return (frame.mii_data); 887 } 888 889 static int 890 dc_miibus_writereg(device_t dev, int phy, int reg, int data) 891 { 892 struct dc_softc *sc; 893 struct dc_mii_frame frame; 894 int i, phy_reg = 0; 895 896 sc = device_get_softc(dev); 897 bzero(&frame, sizeof(frame)); 898 899 if (DC_IS_ADMTEK(sc) && phy != DC_ADMTEK_PHYADDR) 900 return (0); 901 902 if (DC_IS_CONEXANT(sc) && phy != DC_CONEXANT_PHYADDR) 903 return (0); 904 905 if (DC_IS_PNIC(sc)) { 906 CSR_WRITE_4(sc, DC_PN_MII, DC_PN_MIIOPCODE_WRITE | 907 (phy << 23) | (reg << 10) | data); 908 for (i = 0; i < DC_TIMEOUT; i++) { 909 if (!(CSR_READ_4(sc, DC_PN_MII) & DC_PN_MII_BUSY)) 910 break; 911 } 912 return (0); 913 } 914 915 if (DC_IS_COMET(sc)) { 916 switch (reg) { 917 case MII_BMCR: 918 phy_reg = DC_AL_BMCR; 919 break; 920 case MII_BMSR: 921 phy_reg = DC_AL_BMSR; 922 break; 923 case MII_PHYIDR1: 924 phy_reg = DC_AL_VENID; 925 break; 926 case MII_PHYIDR2: 927 phy_reg = DC_AL_DEVID; 928 break; 929 case MII_ANAR: 930 phy_reg = DC_AL_ANAR; 931 break; 932 case MII_ANLPAR: 933 phy_reg = DC_AL_LPAR; 934 break; 935 case MII_ANER: 936 phy_reg = DC_AL_ANER; 937 break; 938 default: 939 device_printf(dev, "phy_write: bad phy register %x\n", 940 reg); 941 return (0); 942 break; 943 } 944 945 CSR_WRITE_4(sc, phy_reg, data); 946 return (0); 947 } 948 949 frame.mii_phyaddr = phy; 950 frame.mii_regaddr = reg; 951 frame.mii_data = data; 952 953 if (sc->dc_type == DC_TYPE_98713) { 954 phy_reg = CSR_READ_4(sc, DC_NETCFG); 955 CSR_WRITE_4(sc, DC_NETCFG, phy_reg & ~DC_NETCFG_PORTSEL); 956 } 957 dc_mii_writereg(sc, &frame); 958 if (sc->dc_type == DC_TYPE_98713) 959 CSR_WRITE_4(sc, DC_NETCFG, phy_reg); 960 961 return (0); 962 } 963 964 static void 965 dc_miibus_statchg(device_t dev) 966 { 967 struct dc_softc *sc; 968 struct mii_data *mii; 969 struct ifmedia *ifm; 970 971 sc = device_get_softc(dev); 972 if (DC_IS_ADMTEK(sc)) 973 return; 974 975 mii = device_get_softc(sc->dc_miibus); 976 ifm = &mii->mii_media; 977 if (DC_IS_DAVICOM(sc) && 978 IFM_SUBTYPE(ifm->ifm_media) == IFM_HPNA_1) { 979 dc_setcfg(sc, ifm->ifm_media); 980 sc->dc_if_media = ifm->ifm_media; 981 } else { 982 dc_setcfg(sc, mii->mii_media_active); 983 sc->dc_if_media = mii->mii_media_active; 984 } 985 } 986 987 /* 988 * Special support for DM9102A cards with HomePNA PHYs. Note: 989 * with the Davicom DM9102A/DM9801 eval board that I have, it seems 990 * to be impossible to talk to the management interface of the DM9801 991 * PHY (its MDIO pin is not connected to anything). Consequently, 992 * the driver has to just 'know' about the additional mode and deal 993 * with it itself. *sigh* 994 */ 995 static void 996 dc_miibus_mediainit(device_t dev) 997 { 998 struct dc_softc *sc; 999 struct mii_data *mii; 1000 struct ifmedia *ifm; 1001 int rev; 1002 1003 rev = pci_read_config(dev, DC_PCI_CFRV, 4) & 0xFF; 1004 1005 sc = device_get_softc(dev); 1006 mii = device_get_softc(sc->dc_miibus); 1007 ifm = &mii->mii_media; 1008 1009 if (DC_IS_DAVICOM(sc) && rev >= DC_REVISION_DM9102A) 1010 ifmedia_add(ifm, IFM_ETHER | IFM_HPNA_1, 0, NULL); 1011 } 1012 1013 #define DC_BITS_512 9 1014 #define DC_BITS_128 7 1015 #define DC_BITS_64 6 1016 1017 static uint32_t 1018 dc_mchash_le(struct dc_softc *sc, const uint8_t *addr) 1019 { 1020 uint32_t crc; 1021 1022 /* Compute CRC for the address value. */ 1023 crc = ether_crc32_le(addr, ETHER_ADDR_LEN); 1024 1025 /* 1026 * The hash table on the PNIC II and the MX98715AEC-C/D/E 1027 * chips is only 128 bits wide. 1028 */ 1029 if (sc->dc_flags & DC_128BIT_HASH) 1030 return (crc & ((1 << DC_BITS_128) - 1)); 1031 1032 /* The hash table on the MX98715BEC is only 64 bits wide. */ 1033 if (sc->dc_flags & DC_64BIT_HASH) 1034 return (crc & ((1 << DC_BITS_64) - 1)); 1035 1036 /* Xircom's hash filtering table is different (read: weird) */ 1037 /* Xircom uses the LEAST significant bits */ 1038 if (DC_IS_XIRCOM(sc)) { 1039 if ((crc & 0x180) == 0x180) 1040 return ((crc & 0x0F) + (crc & 0x70) * 3 + (14 << 4)); 1041 else 1042 return ((crc & 0x1F) + ((crc >> 1) & 0xF0) * 3 + 1043 (12 << 4)); 1044 } 1045 1046 return (crc & ((1 << DC_BITS_512) - 1)); 1047 } 1048 1049 /* 1050 * Calculate CRC of a multicast group address, return the lower 6 bits. 1051 */ 1052 static uint32_t 1053 dc_mchash_be(const uint8_t *addr) 1054 { 1055 uint32_t crc; 1056 1057 /* Compute CRC for the address value. */ 1058 crc = ether_crc32_be(addr, ETHER_ADDR_LEN); 1059 1060 /* Return the filter bit position. */ 1061 return ((crc >> 26) & 0x0000003F); 1062 } 1063 1064 /* 1065 * 21143-style RX filter setup routine. Filter programming is done by 1066 * downloading a special setup frame into the TX engine. 21143, Macronix, 1067 * PNIC, PNIC II and Davicom chips are programmed this way. 1068 * 1069 * We always program the chip using 'hash perfect' mode, i.e. one perfect 1070 * address (our node address) and a 512-bit hash filter for multicast 1071 * frames. We also sneak the broadcast address into the hash filter since 1072 * we need that too. 1073 */ 1074 static void 1075 dc_setfilt_21143(struct dc_softc *sc) 1076 { 1077 struct dc_desc *sframe; 1078 u_int32_t h, *sp; 1079 struct ifmultiaddr *ifma; 1080 struct ifnet *ifp; 1081 int i; 1082 1083 ifp = sc->dc_ifp; 1084 1085 i = sc->dc_cdata.dc_tx_prod; 1086 DC_INC(sc->dc_cdata.dc_tx_prod, DC_TX_LIST_CNT); 1087 sc->dc_cdata.dc_tx_cnt++; 1088 sframe = &sc->dc_ldata->dc_tx_list[i]; 1089 sp = sc->dc_cdata.dc_sbuf; 1090 bzero(sp, DC_SFRAME_LEN); 1091 1092 sframe->dc_data = htole32(sc->dc_saddr); 1093 sframe->dc_ctl = htole32(DC_SFRAME_LEN | DC_TXCTL_SETUP | 1094 DC_TXCTL_TLINK | DC_FILTER_HASHPERF | DC_TXCTL_FINT); 1095 1096 sc->dc_cdata.dc_tx_chain[i] = (struct mbuf *)sc->dc_cdata.dc_sbuf; 1097 1098 /* If we want promiscuous mode, set the allframes bit. */ 1099 if (ifp->if_flags & IFF_PROMISC) 1100 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC); 1101 else 1102 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC); 1103 1104 if (ifp->if_flags & IFF_ALLMULTI) 1105 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI); 1106 else 1107 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI); 1108 1109 IF_ADDR_LOCK(ifp); 1110 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 1111 if (ifma->ifma_addr->sa_family != AF_LINK) 1112 continue; 1113 h = dc_mchash_le(sc, 1114 LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 1115 sp[h >> 4] |= htole32(1 << (h & 0xF)); 1116 } 1117 IF_ADDR_UNLOCK(ifp); 1118 1119 if (ifp->if_flags & IFF_BROADCAST) { 1120 h = dc_mchash_le(sc, ifp->if_broadcastaddr); 1121 sp[h >> 4] |= htole32(1 << (h & 0xF)); 1122 } 1123 1124 /* Set our MAC address */ 1125 sp[39] = DC_SP_MAC(((u_int16_t *)IFP2ENADDR(sc->dc_ifp))[0]); 1126 sp[40] = DC_SP_MAC(((u_int16_t *)IFP2ENADDR(sc->dc_ifp))[1]); 1127 sp[41] = DC_SP_MAC(((u_int16_t *)IFP2ENADDR(sc->dc_ifp))[2]); 1128 1129 sframe->dc_status = htole32(DC_TXSTAT_OWN); 1130 CSR_WRITE_4(sc, DC_TXSTART, 0xFFFFFFFF); 1131 1132 /* 1133 * The PNIC takes an exceedingly long time to process its 1134 * setup frame; wait 10ms after posting the setup frame 1135 * before proceeding, just so it has time to swallow its 1136 * medicine. 1137 */ 1138 DELAY(10000); 1139 1140 ifp->if_timer = 5; 1141 } 1142 1143 static void 1144 dc_setfilt_admtek(struct dc_softc *sc) 1145 { 1146 struct ifnet *ifp; 1147 struct ifmultiaddr *ifma; 1148 int h = 0; 1149 u_int32_t hashes[2] = { 0, 0 }; 1150 1151 ifp = sc->dc_ifp; 1152 1153 /* Init our MAC address. */ 1154 CSR_WRITE_4(sc, DC_AL_PAR0, *(u_int32_t *)(&IFP2ENADDR(sc->dc_ifp)[0])); 1155 CSR_WRITE_4(sc, DC_AL_PAR1, *(u_int32_t *)(&IFP2ENADDR(sc->dc_ifp)[4])); 1156 1157 /* If we want promiscuous mode, set the allframes bit. */ 1158 if (ifp->if_flags & IFF_PROMISC) 1159 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC); 1160 else 1161 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC); 1162 1163 if (ifp->if_flags & IFF_ALLMULTI) 1164 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI); 1165 else 1166 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI); 1167 1168 /* First, zot all the existing hash bits. */ 1169 CSR_WRITE_4(sc, DC_AL_MAR0, 0); 1170 CSR_WRITE_4(sc, DC_AL_MAR1, 0); 1171 1172 /* 1173 * If we're already in promisc or allmulti mode, we 1174 * don't have to bother programming the multicast filter. 1175 */ 1176 if (ifp->if_flags & (IFF_PROMISC | IFF_ALLMULTI)) 1177 return; 1178 1179 /* Now program new ones. */ 1180 IF_ADDR_LOCK(ifp); 1181 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 1182 if (ifma->ifma_addr->sa_family != AF_LINK) 1183 continue; 1184 if (DC_IS_CENTAUR(sc)) 1185 h = dc_mchash_le(sc, 1186 LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 1187 else 1188 h = dc_mchash_be( 1189 LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 1190 if (h < 32) 1191 hashes[0] |= (1 << h); 1192 else 1193 hashes[1] |= (1 << (h - 32)); 1194 } 1195 IF_ADDR_UNLOCK(ifp); 1196 1197 CSR_WRITE_4(sc, DC_AL_MAR0, hashes[0]); 1198 CSR_WRITE_4(sc, DC_AL_MAR1, hashes[1]); 1199 } 1200 1201 static void 1202 dc_setfilt_asix(struct dc_softc *sc) 1203 { 1204 struct ifnet *ifp; 1205 struct ifmultiaddr *ifma; 1206 int h = 0; 1207 u_int32_t hashes[2] = { 0, 0 }; 1208 1209 ifp = sc->dc_ifp; 1210 1211 /* Init our MAC address */ 1212 CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_PAR0); 1213 CSR_WRITE_4(sc, DC_AX_FILTDATA, 1214 *(u_int32_t *)(&IFP2ENADDR(sc->dc_ifp)[0])); 1215 CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_PAR1); 1216 CSR_WRITE_4(sc, DC_AX_FILTDATA, 1217 *(u_int32_t *)(&IFP2ENADDR(sc->dc_ifp)[4])); 1218 1219 /* If we want promiscuous mode, set the allframes bit. */ 1220 if (ifp->if_flags & IFF_PROMISC) 1221 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC); 1222 else 1223 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC); 1224 1225 if (ifp->if_flags & IFF_ALLMULTI) 1226 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI); 1227 else 1228 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI); 1229 1230 /* 1231 * The ASIX chip has a special bit to enable reception 1232 * of broadcast frames. 1233 */ 1234 if (ifp->if_flags & IFF_BROADCAST) 1235 DC_SETBIT(sc, DC_NETCFG, DC_AX_NETCFG_RX_BROAD); 1236 else 1237 DC_CLRBIT(sc, DC_NETCFG, DC_AX_NETCFG_RX_BROAD); 1238 1239 /* first, zot all the existing hash bits */ 1240 CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_MAR0); 1241 CSR_WRITE_4(sc, DC_AX_FILTDATA, 0); 1242 CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_MAR1); 1243 CSR_WRITE_4(sc, DC_AX_FILTDATA, 0); 1244 1245 /* 1246 * If we're already in promisc or allmulti mode, we 1247 * don't have to bother programming the multicast filter. 1248 */ 1249 if (ifp->if_flags & (IFF_PROMISC | IFF_ALLMULTI)) 1250 return; 1251 1252 /* now program new ones */ 1253 IF_ADDR_LOCK(ifp); 1254 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 1255 if (ifma->ifma_addr->sa_family != AF_LINK) 1256 continue; 1257 h = dc_mchash_be(LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 1258 if (h < 32) 1259 hashes[0] |= (1 << h); 1260 else 1261 hashes[1] |= (1 << (h - 32)); 1262 } 1263 IF_ADDR_UNLOCK(ifp); 1264 1265 CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_MAR0); 1266 CSR_WRITE_4(sc, DC_AX_FILTDATA, hashes[0]); 1267 CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_MAR1); 1268 CSR_WRITE_4(sc, DC_AX_FILTDATA, hashes[1]); 1269 } 1270 1271 static void 1272 dc_setfilt_xircom(struct dc_softc *sc) 1273 { 1274 struct ifnet *ifp; 1275 struct ifmultiaddr *ifma; 1276 struct dc_desc *sframe; 1277 u_int32_t h, *sp; 1278 int i; 1279 1280 ifp = sc->dc_ifp; 1281 DC_CLRBIT(sc, DC_NETCFG, (DC_NETCFG_TX_ON | DC_NETCFG_RX_ON)); 1282 1283 i = sc->dc_cdata.dc_tx_prod; 1284 DC_INC(sc->dc_cdata.dc_tx_prod, DC_TX_LIST_CNT); 1285 sc->dc_cdata.dc_tx_cnt++; 1286 sframe = &sc->dc_ldata->dc_tx_list[i]; 1287 sp = sc->dc_cdata.dc_sbuf; 1288 bzero(sp, DC_SFRAME_LEN); 1289 1290 sframe->dc_data = htole32(sc->dc_saddr); 1291 sframe->dc_ctl = htole32(DC_SFRAME_LEN | DC_TXCTL_SETUP | 1292 DC_TXCTL_TLINK | DC_FILTER_HASHPERF | DC_TXCTL_FINT); 1293 1294 sc->dc_cdata.dc_tx_chain[i] = (struct mbuf *)sc->dc_cdata.dc_sbuf; 1295 1296 /* If we want promiscuous mode, set the allframes bit. */ 1297 if (ifp->if_flags & IFF_PROMISC) 1298 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC); 1299 else 1300 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC); 1301 1302 if (ifp->if_flags & IFF_ALLMULTI) 1303 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI); 1304 else 1305 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI); 1306 1307 IF_ADDR_LOCK(ifp); 1308 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 1309 if (ifma->ifma_addr->sa_family != AF_LINK) 1310 continue; 1311 h = dc_mchash_le(sc, 1312 LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 1313 sp[h >> 4] |= htole32(1 << (h & 0xF)); 1314 } 1315 IF_ADDR_UNLOCK(ifp); 1316 1317 if (ifp->if_flags & IFF_BROADCAST) { 1318 h = dc_mchash_le(sc, ifp->if_broadcastaddr); 1319 sp[h >> 4] |= htole32(1 << (h & 0xF)); 1320 } 1321 1322 /* Set our MAC address */ 1323 sp[0] = DC_SP_MAC(((u_int16_t *)IFP2ENADDR(sc->dc_ifp))[0]); 1324 sp[1] = DC_SP_MAC(((u_int16_t *)IFP2ENADDR(sc->dc_ifp))[1]); 1325 sp[2] = DC_SP_MAC(((u_int16_t *)IFP2ENADDR(sc->dc_ifp))[2]); 1326 1327 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_TX_ON); 1328 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_ON); 1329 ifp->if_drv_flags |= IFF_DRV_RUNNING; 1330 sframe->dc_status = htole32(DC_TXSTAT_OWN); 1331 CSR_WRITE_4(sc, DC_TXSTART, 0xFFFFFFFF); 1332 1333 /* 1334 * Wait some time... 1335 */ 1336 DELAY(1000); 1337 1338 ifp->if_timer = 5; 1339 } 1340 1341 static void 1342 dc_setfilt(struct dc_softc *sc) 1343 { 1344 1345 if (DC_IS_INTEL(sc) || DC_IS_MACRONIX(sc) || DC_IS_PNIC(sc) || 1346 DC_IS_PNICII(sc) || DC_IS_DAVICOM(sc) || DC_IS_CONEXANT(sc)) 1347 dc_setfilt_21143(sc); 1348 1349 if (DC_IS_ASIX(sc)) 1350 dc_setfilt_asix(sc); 1351 1352 if (DC_IS_ADMTEK(sc)) 1353 dc_setfilt_admtek(sc); 1354 1355 if (DC_IS_XIRCOM(sc)) 1356 dc_setfilt_xircom(sc); 1357 } 1358 1359 /* 1360 * In order to fiddle with the 'full-duplex' and '100Mbps' bits in 1361 * the netconfig register, we first have to put the transmit and/or 1362 * receive logic in the idle state. 1363 */ 1364 static void 1365 dc_setcfg(struct dc_softc *sc, int media) 1366 { 1367 int i, restart = 0, watchdogreg; 1368 u_int32_t isr; 1369 1370 if (IFM_SUBTYPE(media) == IFM_NONE) 1371 return; 1372 1373 if (CSR_READ_4(sc, DC_NETCFG) & (DC_NETCFG_TX_ON | DC_NETCFG_RX_ON)) { 1374 restart = 1; 1375 DC_CLRBIT(sc, DC_NETCFG, (DC_NETCFG_TX_ON | DC_NETCFG_RX_ON)); 1376 1377 for (i = 0; i < DC_TIMEOUT; i++) { 1378 isr = CSR_READ_4(sc, DC_ISR); 1379 if (isr & DC_ISR_TX_IDLE && 1380 ((isr & DC_ISR_RX_STATE) == DC_RXSTATE_STOPPED || 1381 (isr & DC_ISR_RX_STATE) == DC_RXSTATE_WAIT)) 1382 break; 1383 DELAY(10); 1384 } 1385 1386 if (i == DC_TIMEOUT) 1387 if_printf(sc->dc_ifp, 1388 "failed to force tx and rx to idle state\n"); 1389 } 1390 1391 if (IFM_SUBTYPE(media) == IFM_100_TX) { 1392 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_SPEEDSEL); 1393 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_HEARTBEAT); 1394 if (sc->dc_pmode == DC_PMODE_MII) { 1395 if (DC_IS_INTEL(sc)) { 1396 /* There's a write enable bit here that reads as 1. */ 1397 watchdogreg = CSR_READ_4(sc, DC_WATCHDOG); 1398 watchdogreg &= ~DC_WDOG_CTLWREN; 1399 watchdogreg |= DC_WDOG_JABBERDIS; 1400 CSR_WRITE_4(sc, DC_WATCHDOG, watchdogreg); 1401 } else { 1402 DC_SETBIT(sc, DC_WATCHDOG, DC_WDOG_JABBERDIS); 1403 } 1404 DC_CLRBIT(sc, DC_NETCFG, (DC_NETCFG_PCS | 1405 DC_NETCFG_PORTSEL | DC_NETCFG_SCRAMBLER)); 1406 if (sc->dc_type == DC_TYPE_98713) 1407 DC_SETBIT(sc, DC_NETCFG, (DC_NETCFG_PCS | 1408 DC_NETCFG_SCRAMBLER)); 1409 if (!DC_IS_DAVICOM(sc)) 1410 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL); 1411 DC_CLRBIT(sc, DC_10BTCTRL, 0xFFFF); 1412 if (DC_IS_INTEL(sc)) 1413 dc_apply_fixup(sc, IFM_AUTO); 1414 } else { 1415 if (DC_IS_PNIC(sc)) { 1416 DC_PN_GPIO_SETBIT(sc, DC_PN_GPIO_SPEEDSEL); 1417 DC_PN_GPIO_SETBIT(sc, DC_PN_GPIO_100TX_LOOP); 1418 DC_SETBIT(sc, DC_PN_NWAY, DC_PN_NWAY_SPEEDSEL); 1419 } 1420 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL); 1421 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PCS); 1422 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_SCRAMBLER); 1423 if (DC_IS_INTEL(sc)) 1424 dc_apply_fixup(sc, 1425 (media & IFM_GMASK) == IFM_FDX ? 1426 IFM_100_TX | IFM_FDX : IFM_100_TX); 1427 } 1428 } 1429 1430 if (IFM_SUBTYPE(media) == IFM_10_T) { 1431 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_SPEEDSEL); 1432 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_HEARTBEAT); 1433 if (sc->dc_pmode == DC_PMODE_MII) { 1434 /* There's a write enable bit here that reads as 1. */ 1435 if (DC_IS_INTEL(sc)) { 1436 watchdogreg = CSR_READ_4(sc, DC_WATCHDOG); 1437 watchdogreg &= ~DC_WDOG_CTLWREN; 1438 watchdogreg |= DC_WDOG_JABBERDIS; 1439 CSR_WRITE_4(sc, DC_WATCHDOG, watchdogreg); 1440 } else { 1441 DC_SETBIT(sc, DC_WATCHDOG, DC_WDOG_JABBERDIS); 1442 } 1443 DC_CLRBIT(sc, DC_NETCFG, (DC_NETCFG_PCS | 1444 DC_NETCFG_PORTSEL | DC_NETCFG_SCRAMBLER)); 1445 if (sc->dc_type == DC_TYPE_98713) 1446 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PCS); 1447 if (!DC_IS_DAVICOM(sc)) 1448 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL); 1449 DC_CLRBIT(sc, DC_10BTCTRL, 0xFFFF); 1450 if (DC_IS_INTEL(sc)) 1451 dc_apply_fixup(sc, IFM_AUTO); 1452 } else { 1453 if (DC_IS_PNIC(sc)) { 1454 DC_PN_GPIO_CLRBIT(sc, DC_PN_GPIO_SPEEDSEL); 1455 DC_PN_GPIO_SETBIT(sc, DC_PN_GPIO_100TX_LOOP); 1456 DC_CLRBIT(sc, DC_PN_NWAY, DC_PN_NWAY_SPEEDSEL); 1457 } 1458 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL); 1459 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_PCS); 1460 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_SCRAMBLER); 1461 if (DC_IS_INTEL(sc)) { 1462 DC_CLRBIT(sc, DC_SIARESET, DC_SIA_RESET); 1463 DC_CLRBIT(sc, DC_10BTCTRL, 0xFFFF); 1464 if ((media & IFM_GMASK) == IFM_FDX) 1465 DC_SETBIT(sc, DC_10BTCTRL, 0x7F3D); 1466 else 1467 DC_SETBIT(sc, DC_10BTCTRL, 0x7F3F); 1468 DC_SETBIT(sc, DC_SIARESET, DC_SIA_RESET); 1469 DC_CLRBIT(sc, DC_10BTCTRL, 1470 DC_TCTL_AUTONEGENBL); 1471 dc_apply_fixup(sc, 1472 (media & IFM_GMASK) == IFM_FDX ? 1473 IFM_10_T | IFM_FDX : IFM_10_T); 1474 DELAY(20000); 1475 } 1476 } 1477 } 1478 1479 /* 1480 * If this is a Davicom DM9102A card with a DM9801 HomePNA 1481 * PHY and we want HomePNA mode, set the portsel bit to turn 1482 * on the external MII port. 1483 */ 1484 if (DC_IS_DAVICOM(sc)) { 1485 if (IFM_SUBTYPE(media) == IFM_HPNA_1) { 1486 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL); 1487 sc->dc_link = 1; 1488 } else { 1489 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL); 1490 } 1491 } 1492 1493 if ((media & IFM_GMASK) == IFM_FDX) { 1494 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_FULLDUPLEX); 1495 if (sc->dc_pmode == DC_PMODE_SYM && DC_IS_PNIC(sc)) 1496 DC_SETBIT(sc, DC_PN_NWAY, DC_PN_NWAY_DUPLEX); 1497 } else { 1498 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_FULLDUPLEX); 1499 if (sc->dc_pmode == DC_PMODE_SYM && DC_IS_PNIC(sc)) 1500 DC_CLRBIT(sc, DC_PN_NWAY, DC_PN_NWAY_DUPLEX); 1501 } 1502 1503 if (restart) 1504 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_TX_ON | DC_NETCFG_RX_ON); 1505 } 1506 1507 static void 1508 dc_reset(struct dc_softc *sc) 1509 { 1510 int i; 1511 1512 DC_SETBIT(sc, DC_BUSCTL, DC_BUSCTL_RESET); 1513 1514 for (i = 0; i < DC_TIMEOUT; i++) { 1515 DELAY(10); 1516 if (!(CSR_READ_4(sc, DC_BUSCTL) & DC_BUSCTL_RESET)) 1517 break; 1518 } 1519 1520 if (DC_IS_ASIX(sc) || DC_IS_ADMTEK(sc) || DC_IS_CONEXANT(sc) || 1521 DC_IS_XIRCOM(sc) || DC_IS_INTEL(sc)) { 1522 DELAY(10000); 1523 DC_CLRBIT(sc, DC_BUSCTL, DC_BUSCTL_RESET); 1524 i = 0; 1525 } 1526 1527 if (i == DC_TIMEOUT) 1528 if_printf(sc->dc_ifp, "reset never completed!\n"); 1529 1530 /* Wait a little while for the chip to get its brains in order. */ 1531 DELAY(1000); 1532 1533 CSR_WRITE_4(sc, DC_IMR, 0x00000000); 1534 CSR_WRITE_4(sc, DC_BUSCTL, 0x00000000); 1535 CSR_WRITE_4(sc, DC_NETCFG, 0x00000000); 1536 1537 /* 1538 * Bring the SIA out of reset. In some cases, it looks 1539 * like failing to unreset the SIA soon enough gets it 1540 * into a state where it will never come out of reset 1541 * until we reset the whole chip again. 1542 */ 1543 if (DC_IS_INTEL(sc)) { 1544 DC_SETBIT(sc, DC_SIARESET, DC_SIA_RESET); 1545 CSR_WRITE_4(sc, DC_10BTCTRL, 0); 1546 CSR_WRITE_4(sc, DC_WATCHDOG, 0); 1547 } 1548 } 1549 1550 static struct dc_type * 1551 dc_devtype(device_t dev) 1552 { 1553 struct dc_type *t; 1554 u_int32_t rev; 1555 1556 t = dc_devs; 1557 1558 while (t->dc_name != NULL) { 1559 if ((pci_get_vendor(dev) == t->dc_vid) && 1560 (pci_get_device(dev) == t->dc_did)) { 1561 /* Check the PCI revision */ 1562 rev = pci_read_config(dev, DC_PCI_CFRV, 4) & 0xFF; 1563 if (t->dc_did == DC_DEVICEID_98713 && 1564 rev >= DC_REVISION_98713A) 1565 t++; 1566 if (t->dc_did == DC_DEVICEID_98713_CP && 1567 rev >= DC_REVISION_98713A) 1568 t++; 1569 if (t->dc_did == DC_DEVICEID_987x5 && 1570 rev >= DC_REVISION_98715AEC_C) 1571 t++; 1572 if (t->dc_did == DC_DEVICEID_987x5 && 1573 rev >= DC_REVISION_98725) 1574 t++; 1575 if (t->dc_did == DC_DEVICEID_AX88140A && 1576 rev >= DC_REVISION_88141) 1577 t++; 1578 if (t->dc_did == DC_DEVICEID_82C168 && 1579 rev >= DC_REVISION_82C169) 1580 t++; 1581 if (t->dc_did == DC_DEVICEID_DM9102 && 1582 rev >= DC_REVISION_DM9102A) 1583 t++; 1584 /* 1585 * The Microsoft MN-130 has a device ID of 0x0002, 1586 * which happens to be the same as the PNIC 82c168. 1587 * To keep dc_attach() from getting confused, we 1588 * pretend its ID is something different. 1589 * XXX: ideally, dc_attach() should be checking 1590 * vendorid+deviceid together to avoid such 1591 * collisions. 1592 */ 1593 if (t->dc_vid == DC_VENDORID_MICROSOFT && 1594 t->dc_did == DC_DEVICEID_MSMN130) 1595 t++; 1596 return (t); 1597 } 1598 t++; 1599 } 1600 1601 return (NULL); 1602 } 1603 1604 /* 1605 * Probe for a 21143 or clone chip. Check the PCI vendor and device 1606 * IDs against our list and return a device name if we find a match. 1607 * We do a little bit of extra work to identify the exact type of 1608 * chip. The MX98713 and MX98713A have the same PCI vendor/device ID, 1609 * but different revision IDs. The same is true for 98715/98715A 1610 * chips and the 98725, as well as the ASIX and ADMtek chips. In some 1611 * cases, the exact chip revision affects driver behavior. 1612 */ 1613 static int 1614 dc_probe(device_t dev) 1615 { 1616 struct dc_type *t; 1617 1618 t = dc_devtype(dev); 1619 1620 if (t != NULL) { 1621 device_set_desc(dev, t->dc_name); 1622 return (BUS_PROBE_DEFAULT); 1623 } 1624 1625 return (ENXIO); 1626 } 1627 1628 static void 1629 dc_apply_fixup(struct dc_softc *sc, int media) 1630 { 1631 struct dc_mediainfo *m; 1632 u_int8_t *p; 1633 int i; 1634 u_int32_t reg; 1635 1636 m = sc->dc_mi; 1637 1638 while (m != NULL) { 1639 if (m->dc_media == media) 1640 break; 1641 m = m->dc_next; 1642 } 1643 1644 if (m == NULL) 1645 return; 1646 1647 for (i = 0, p = m->dc_reset_ptr; i < m->dc_reset_len; i++, p += 2) { 1648 reg = (p[0] | (p[1] << 8)) << 16; 1649 CSR_WRITE_4(sc, DC_WATCHDOG, reg); 1650 } 1651 1652 for (i = 0, p = m->dc_gp_ptr; i < m->dc_gp_len; i++, p += 2) { 1653 reg = (p[0] | (p[1] << 8)) << 16; 1654 CSR_WRITE_4(sc, DC_WATCHDOG, reg); 1655 } 1656 } 1657 1658 static void 1659 dc_decode_leaf_sia(struct dc_softc *sc, struct dc_eblock_sia *l) 1660 { 1661 struct dc_mediainfo *m; 1662 1663 m = malloc(sizeof(struct dc_mediainfo), M_DEVBUF, M_NOWAIT | M_ZERO); 1664 switch (l->dc_sia_code & ~DC_SIA_CODE_EXT) { 1665 case DC_SIA_CODE_10BT: 1666 m->dc_media = IFM_10_T; 1667 break; 1668 case DC_SIA_CODE_10BT_FDX: 1669 m->dc_media = IFM_10_T | IFM_FDX; 1670 break; 1671 case DC_SIA_CODE_10B2: 1672 m->dc_media = IFM_10_2; 1673 break; 1674 case DC_SIA_CODE_10B5: 1675 m->dc_media = IFM_10_5; 1676 break; 1677 default: 1678 break; 1679 } 1680 1681 /* 1682 * We need to ignore CSR13, CSR14, CSR15 for SIA mode. 1683 * Things apparently already work for cards that do 1684 * supply Media Specific Data. 1685 */ 1686 if (l->dc_sia_code & DC_SIA_CODE_EXT) { 1687 m->dc_gp_len = 2; 1688 m->dc_gp_ptr = 1689 (u_int8_t *)&l->dc_un.dc_sia_ext.dc_sia_gpio_ctl; 1690 } else { 1691 m->dc_gp_len = 2; 1692 m->dc_gp_ptr = 1693 (u_int8_t *)&l->dc_un.dc_sia_noext.dc_sia_gpio_ctl; 1694 } 1695 1696 m->dc_next = sc->dc_mi; 1697 sc->dc_mi = m; 1698 1699 sc->dc_pmode = DC_PMODE_SIA; 1700 } 1701 1702 static void 1703 dc_decode_leaf_sym(struct dc_softc *sc, struct dc_eblock_sym *l) 1704 { 1705 struct dc_mediainfo *m; 1706 1707 m = malloc(sizeof(struct dc_mediainfo), M_DEVBUF, M_NOWAIT | M_ZERO); 1708 if (l->dc_sym_code == DC_SYM_CODE_100BT) 1709 m->dc_media = IFM_100_TX; 1710 1711 if (l->dc_sym_code == DC_SYM_CODE_100BT_FDX) 1712 m->dc_media = IFM_100_TX | IFM_FDX; 1713 1714 m->dc_gp_len = 2; 1715 m->dc_gp_ptr = (u_int8_t *)&l->dc_sym_gpio_ctl; 1716 1717 m->dc_next = sc->dc_mi; 1718 sc->dc_mi = m; 1719 1720 sc->dc_pmode = DC_PMODE_SYM; 1721 } 1722 1723 static void 1724 dc_decode_leaf_mii(struct dc_softc *sc, struct dc_eblock_mii *l) 1725 { 1726 struct dc_mediainfo *m; 1727 u_int8_t *p; 1728 1729 m = malloc(sizeof(struct dc_mediainfo), M_DEVBUF, M_NOWAIT | M_ZERO); 1730 /* We abuse IFM_AUTO to represent MII. */ 1731 m->dc_media = IFM_AUTO; 1732 m->dc_gp_len = l->dc_gpr_len; 1733 1734 p = (u_int8_t *)l; 1735 p += sizeof(struct dc_eblock_mii); 1736 m->dc_gp_ptr = p; 1737 p += 2 * l->dc_gpr_len; 1738 m->dc_reset_len = *p; 1739 p++; 1740 m->dc_reset_ptr = p; 1741 1742 m->dc_next = sc->dc_mi; 1743 sc->dc_mi = m; 1744 } 1745 1746 static void 1747 dc_read_srom(struct dc_softc *sc, int bits) 1748 { 1749 int size; 1750 1751 size = 2 << bits; 1752 sc->dc_srom = malloc(size, M_DEVBUF, M_NOWAIT); 1753 dc_read_eeprom(sc, (caddr_t)sc->dc_srom, 0, (size / 2), 0); 1754 } 1755 1756 static void 1757 dc_parse_21143_srom(struct dc_softc *sc) 1758 { 1759 struct dc_leaf_hdr *lhdr; 1760 struct dc_eblock_hdr *hdr; 1761 int have_mii, i, loff; 1762 char *ptr; 1763 1764 have_mii = 0; 1765 loff = sc->dc_srom[27]; 1766 lhdr = (struct dc_leaf_hdr *)&(sc->dc_srom[loff]); 1767 1768 ptr = (char *)lhdr; 1769 ptr += sizeof(struct dc_leaf_hdr) - 1; 1770 /* 1771 * Look if we got a MII media block. 1772 */ 1773 for (i = 0; i < lhdr->dc_mcnt; i++) { 1774 hdr = (struct dc_eblock_hdr *)ptr; 1775 if (hdr->dc_type == DC_EBLOCK_MII) 1776 have_mii++; 1777 1778 ptr += (hdr->dc_len & 0x7F); 1779 ptr++; 1780 } 1781 1782 /* 1783 * Do the same thing again. Only use SIA and SYM media 1784 * blocks if no MII media block is available. 1785 */ 1786 ptr = (char *)lhdr; 1787 ptr += sizeof(struct dc_leaf_hdr) - 1; 1788 for (i = 0; i < lhdr->dc_mcnt; i++) { 1789 hdr = (struct dc_eblock_hdr *)ptr; 1790 switch (hdr->dc_type) { 1791 case DC_EBLOCK_MII: 1792 dc_decode_leaf_mii(sc, (struct dc_eblock_mii *)hdr); 1793 break; 1794 case DC_EBLOCK_SIA: 1795 if (! have_mii) 1796 dc_decode_leaf_sia(sc, 1797 (struct dc_eblock_sia *)hdr); 1798 break; 1799 case DC_EBLOCK_SYM: 1800 if (! have_mii) 1801 dc_decode_leaf_sym(sc, 1802 (struct dc_eblock_sym *)hdr); 1803 break; 1804 default: 1805 /* Don't care. Yet. */ 1806 break; 1807 } 1808 ptr += (hdr->dc_len & 0x7F); 1809 ptr++; 1810 } 1811 } 1812 1813 static void 1814 dc_dma_map_addr(void *arg, bus_dma_segment_t *segs, int nseg, int error) 1815 { 1816 u_int32_t *paddr; 1817 1818 KASSERT(nseg == 1, ("wrong number of segments, should be 1")); 1819 paddr = arg; 1820 *paddr = segs->ds_addr; 1821 } 1822 1823 /* 1824 * Attach the interface. Allocate softc structures, do ifmedia 1825 * setup and ethernet/BPF attach. 1826 */ 1827 static int 1828 dc_attach(device_t dev) 1829 { 1830 int tmp = 0; 1831 u_char eaddr[ETHER_ADDR_LEN]; 1832 u_int32_t command; 1833 struct dc_softc *sc; 1834 struct ifnet *ifp; 1835 u_int32_t revision; 1836 int error = 0, rid, mac_offset; 1837 int i; 1838 u_int8_t *mac; 1839 1840 sc = device_get_softc(dev); 1841 1842 mtx_init(&sc->dc_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 1843 MTX_DEF); 1844 1845 /* 1846 * Map control/status registers. 1847 */ 1848 pci_enable_busmaster(dev); 1849 1850 rid = DC_RID; 1851 sc->dc_res = bus_alloc_resource_any(dev, DC_RES, &rid, RF_ACTIVE); 1852 1853 if (sc->dc_res == NULL) { 1854 device_printf(dev, "couldn't map ports/memory\n"); 1855 error = ENXIO; 1856 goto fail; 1857 } 1858 1859 sc->dc_btag = rman_get_bustag(sc->dc_res); 1860 sc->dc_bhandle = rman_get_bushandle(sc->dc_res); 1861 1862 /* Allocate interrupt. */ 1863 rid = 0; 1864 sc->dc_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 1865 RF_SHAREABLE | RF_ACTIVE); 1866 1867 if (sc->dc_irq == NULL) { 1868 device_printf(dev, "couldn't map interrupt\n"); 1869 error = ENXIO; 1870 goto fail; 1871 } 1872 1873 /* Need this info to decide on a chip type. */ 1874 sc->dc_info = dc_devtype(dev); 1875 revision = pci_read_config(dev, DC_PCI_CFRV, 4) & 0x000000FF; 1876 1877 /* Get the eeprom width, but PNIC and XIRCOM have diff eeprom */ 1878 if (sc->dc_info->dc_did != DC_DEVICEID_82C168 && 1879 sc->dc_info->dc_did != DC_DEVICEID_X3201) 1880 dc_eeprom_width(sc); 1881 1882 switch (sc->dc_info->dc_did) { 1883 case DC_DEVICEID_21143: 1884 sc->dc_type = DC_TYPE_21143; 1885 sc->dc_flags |= DC_TX_POLL | DC_TX_USE_TX_INTR; 1886 sc->dc_flags |= DC_REDUCED_MII_POLL; 1887 /* Save EEPROM contents so we can parse them later. */ 1888 dc_read_srom(sc, sc->dc_romwidth); 1889 break; 1890 case DC_DEVICEID_DM9009: 1891 case DC_DEVICEID_DM9100: 1892 case DC_DEVICEID_DM9102: 1893 sc->dc_type = DC_TYPE_DM9102; 1894 sc->dc_flags |= DC_TX_COALESCE | DC_TX_INTR_ALWAYS; 1895 sc->dc_flags |= DC_REDUCED_MII_POLL | DC_TX_STORENFWD; 1896 sc->dc_flags |= DC_TX_ALIGN; 1897 sc->dc_pmode = DC_PMODE_MII; 1898 /* Increase the latency timer value. */ 1899 command = pci_read_config(dev, DC_PCI_CFLT, 4); 1900 command &= 0xFFFF00FF; 1901 command |= 0x00008000; 1902 pci_write_config(dev, DC_PCI_CFLT, command, 4); 1903 break; 1904 case DC_DEVICEID_AL981: 1905 sc->dc_type = DC_TYPE_AL981; 1906 sc->dc_flags |= DC_TX_USE_TX_INTR; 1907 sc->dc_flags |= DC_TX_ADMTEK_WAR; 1908 sc->dc_pmode = DC_PMODE_MII; 1909 dc_read_srom(sc, sc->dc_romwidth); 1910 break; 1911 case DC_DEVICEID_AN985: 1912 case DC_DEVICEID_ADM9511: 1913 case DC_DEVICEID_ADM9513: 1914 case DC_DEVICEID_FA511: 1915 case DC_DEVICEID_FE2500: 1916 case DC_DEVICEID_EN2242: 1917 case DC_DEVICEID_HAWKING_PN672TX: 1918 case DC_DEVICEID_3CSOHOB: 1919 case DC_DEVICEID_MSMN120: 1920 case DC_DEVICEID_MSMN130_FAKE: /* XXX avoid collision with PNIC*/ 1921 sc->dc_type = DC_TYPE_AN985; 1922 sc->dc_flags |= DC_64BIT_HASH; 1923 sc->dc_flags |= DC_TX_USE_TX_INTR; 1924 sc->dc_flags |= DC_TX_ADMTEK_WAR; 1925 sc->dc_pmode = DC_PMODE_MII; 1926 /* Don't read SROM for - auto-loaded on reset */ 1927 break; 1928 case DC_DEVICEID_98713: 1929 case DC_DEVICEID_98713_CP: 1930 if (revision < DC_REVISION_98713A) { 1931 sc->dc_type = DC_TYPE_98713; 1932 } 1933 if (revision >= DC_REVISION_98713A) { 1934 sc->dc_type = DC_TYPE_98713A; 1935 sc->dc_flags |= DC_21143_NWAY; 1936 } 1937 sc->dc_flags |= DC_REDUCED_MII_POLL; 1938 sc->dc_flags |= DC_TX_POLL | DC_TX_USE_TX_INTR; 1939 break; 1940 case DC_DEVICEID_987x5: 1941 case DC_DEVICEID_EN1217: 1942 /* 1943 * Macronix MX98715AEC-C/D/E parts have only a 1944 * 128-bit hash table. We need to deal with these 1945 * in the same manner as the PNIC II so that we 1946 * get the right number of bits out of the 1947 * CRC routine. 1948 */ 1949 if (revision >= DC_REVISION_98715AEC_C && 1950 revision < DC_REVISION_98725) 1951 sc->dc_flags |= DC_128BIT_HASH; 1952 sc->dc_type = DC_TYPE_987x5; 1953 sc->dc_flags |= DC_TX_POLL | DC_TX_USE_TX_INTR; 1954 sc->dc_flags |= DC_REDUCED_MII_POLL | DC_21143_NWAY; 1955 break; 1956 case DC_DEVICEID_98727: 1957 sc->dc_type = DC_TYPE_987x5; 1958 sc->dc_flags |= DC_TX_POLL | DC_TX_USE_TX_INTR; 1959 sc->dc_flags |= DC_REDUCED_MII_POLL | DC_21143_NWAY; 1960 break; 1961 case DC_DEVICEID_82C115: 1962 sc->dc_type = DC_TYPE_PNICII; 1963 sc->dc_flags |= DC_TX_POLL | DC_TX_USE_TX_INTR | DC_128BIT_HASH; 1964 sc->dc_flags |= DC_REDUCED_MII_POLL | DC_21143_NWAY; 1965 break; 1966 case DC_DEVICEID_82C168: 1967 sc->dc_type = DC_TYPE_PNIC; 1968 sc->dc_flags |= DC_TX_STORENFWD | DC_TX_INTR_ALWAYS; 1969 sc->dc_flags |= DC_PNIC_RX_BUG_WAR; 1970 sc->dc_pnic_rx_buf = malloc(DC_RXLEN * 5, M_DEVBUF, M_NOWAIT); 1971 if (revision < DC_REVISION_82C169) 1972 sc->dc_pmode = DC_PMODE_SYM; 1973 break; 1974 case DC_DEVICEID_AX88140A: 1975 sc->dc_type = DC_TYPE_ASIX; 1976 sc->dc_flags |= DC_TX_USE_TX_INTR | DC_TX_INTR_FIRSTFRAG; 1977 sc->dc_flags |= DC_REDUCED_MII_POLL; 1978 sc->dc_pmode = DC_PMODE_MII; 1979 break; 1980 case DC_DEVICEID_X3201: 1981 sc->dc_type = DC_TYPE_XIRCOM; 1982 sc->dc_flags |= DC_TX_INTR_ALWAYS | DC_TX_COALESCE | 1983 DC_TX_ALIGN; 1984 /* 1985 * We don't actually need to coalesce, but we're doing 1986 * it to obtain a double word aligned buffer. 1987 * The DC_TX_COALESCE flag is required. 1988 */ 1989 sc->dc_pmode = DC_PMODE_MII; 1990 break; 1991 case DC_DEVICEID_RS7112: 1992 sc->dc_type = DC_TYPE_CONEXANT; 1993 sc->dc_flags |= DC_TX_INTR_ALWAYS; 1994 sc->dc_flags |= DC_REDUCED_MII_POLL; 1995 sc->dc_pmode = DC_PMODE_MII; 1996 dc_read_srom(sc, sc->dc_romwidth); 1997 break; 1998 default: 1999 device_printf(dev, "unknown device: %x\n", sc->dc_info->dc_did); 2000 break; 2001 } 2002 2003 /* Save the cache line size. */ 2004 if (DC_IS_DAVICOM(sc)) 2005 sc->dc_cachesize = 0; 2006 else 2007 sc->dc_cachesize = pci_read_config(dev, 2008 DC_PCI_CFLT, 4) & 0xFF; 2009 2010 /* Reset the adapter. */ 2011 dc_reset(sc); 2012 2013 /* Take 21143 out of snooze mode */ 2014 if (DC_IS_INTEL(sc) || DC_IS_XIRCOM(sc)) { 2015 command = pci_read_config(dev, DC_PCI_CFDD, 4); 2016 command &= ~(DC_CFDD_SNOOZE_MODE | DC_CFDD_SLEEP_MODE); 2017 pci_write_config(dev, DC_PCI_CFDD, command, 4); 2018 } 2019 2020 /* 2021 * Try to learn something about the supported media. 2022 * We know that ASIX and ADMtek and Davicom devices 2023 * will *always* be using MII media, so that's a no-brainer. 2024 * The tricky ones are the Macronix/PNIC II and the 2025 * Intel 21143. 2026 */ 2027 if (DC_IS_INTEL(sc)) 2028 dc_parse_21143_srom(sc); 2029 else if (DC_IS_MACRONIX(sc) || DC_IS_PNICII(sc)) { 2030 if (sc->dc_type == DC_TYPE_98713) 2031 sc->dc_pmode = DC_PMODE_MII; 2032 else 2033 sc->dc_pmode = DC_PMODE_SYM; 2034 } else if (!sc->dc_pmode) 2035 sc->dc_pmode = DC_PMODE_MII; 2036 2037 /* 2038 * Get station address from the EEPROM. 2039 */ 2040 switch(sc->dc_type) { 2041 case DC_TYPE_98713: 2042 case DC_TYPE_98713A: 2043 case DC_TYPE_987x5: 2044 case DC_TYPE_PNICII: 2045 dc_read_eeprom(sc, (caddr_t)&mac_offset, 2046 (DC_EE_NODEADDR_OFFSET / 2), 1, 0); 2047 dc_read_eeprom(sc, (caddr_t)&eaddr, (mac_offset / 2), 3, 0); 2048 break; 2049 case DC_TYPE_PNIC: 2050 dc_read_eeprom(sc, (caddr_t)&eaddr, 0, 3, 1); 2051 break; 2052 case DC_TYPE_DM9102: 2053 dc_read_eeprom(sc, (caddr_t)&eaddr, DC_EE_NODEADDR, 3, 0); 2054 #ifdef __sparc64__ 2055 /* 2056 * If this is an onboard dc(4) the station address read from 2057 * the EEPROM is all zero and we have to get it from the fcode. 2058 */ 2059 for (i = 0; i < ETHER_ADDR_LEN; i++) 2060 if (eaddr[i] != 0x00) 2061 break; 2062 if (i >= ETHER_ADDR_LEN) 2063 OF_getetheraddr(dev, eaddr); 2064 #endif 2065 break; 2066 case DC_TYPE_21143: 2067 case DC_TYPE_ASIX: 2068 dc_read_eeprom(sc, (caddr_t)&eaddr, DC_EE_NODEADDR, 3, 0); 2069 break; 2070 case DC_TYPE_AL981: 2071 case DC_TYPE_AN985: 2072 *(u_int32_t *)(&eaddr[0]) = CSR_READ_4(sc, DC_AL_PAR0); 2073 *(u_int16_t *)(&eaddr[4]) = CSR_READ_4(sc, DC_AL_PAR1); 2074 break; 2075 case DC_TYPE_CONEXANT: 2076 bcopy(sc->dc_srom + DC_CONEXANT_EE_NODEADDR, &eaddr, 2077 ETHER_ADDR_LEN); 2078 break; 2079 case DC_TYPE_XIRCOM: 2080 /* The MAC comes from the CIS. */ 2081 mac = pci_get_ether(dev); 2082 if (!mac) { 2083 device_printf(dev, "No station address in CIS!\n"); 2084 error = ENXIO; 2085 goto fail; 2086 } 2087 bcopy(mac, eaddr, ETHER_ADDR_LEN); 2088 break; 2089 default: 2090 dc_read_eeprom(sc, (caddr_t)&eaddr, DC_EE_NODEADDR, 3, 0); 2091 break; 2092 } 2093 2094 /* Allocate a busdma tag and DMA safe memory for TX/RX descriptors. */ 2095 error = bus_dma_tag_create(NULL, PAGE_SIZE, 0, BUS_SPACE_MAXADDR_32BIT, 2096 BUS_SPACE_MAXADDR, NULL, NULL, sizeof(struct dc_list_data), 1, 2097 sizeof(struct dc_list_data), 0, NULL, NULL, &sc->dc_ltag); 2098 if (error) { 2099 device_printf(dev, "failed to allocate busdma tag\n"); 2100 error = ENXIO; 2101 goto fail; 2102 } 2103 error = bus_dmamem_alloc(sc->dc_ltag, (void **)&sc->dc_ldata, 2104 BUS_DMA_NOWAIT | BUS_DMA_ZERO, &sc->dc_lmap); 2105 if (error) { 2106 device_printf(dev, "failed to allocate DMA safe memory\n"); 2107 error = ENXIO; 2108 goto fail; 2109 } 2110 error = bus_dmamap_load(sc->dc_ltag, sc->dc_lmap, sc->dc_ldata, 2111 sizeof(struct dc_list_data), dc_dma_map_addr, &sc->dc_laddr, 2112 BUS_DMA_NOWAIT); 2113 if (error) { 2114 device_printf(dev, "cannot get address of the descriptors\n"); 2115 error = ENXIO; 2116 goto fail; 2117 } 2118 2119 /* 2120 * Allocate a busdma tag and DMA safe memory for the multicast 2121 * setup frame. 2122 */ 2123 error = bus_dma_tag_create(NULL, PAGE_SIZE, 0, BUS_SPACE_MAXADDR_32BIT, 2124 BUS_SPACE_MAXADDR, NULL, NULL, DC_SFRAME_LEN + DC_MIN_FRAMELEN, 1, 2125 DC_SFRAME_LEN + DC_MIN_FRAMELEN, 0, NULL, NULL, &sc->dc_stag); 2126 if (error) { 2127 device_printf(dev, "failed to allocate busdma tag\n"); 2128 error = ENXIO; 2129 goto fail; 2130 } 2131 error = bus_dmamem_alloc(sc->dc_stag, (void **)&sc->dc_cdata.dc_sbuf, 2132 BUS_DMA_NOWAIT, &sc->dc_smap); 2133 if (error) { 2134 device_printf(dev, "failed to allocate DMA safe memory\n"); 2135 error = ENXIO; 2136 goto fail; 2137 } 2138 error = bus_dmamap_load(sc->dc_stag, sc->dc_smap, sc->dc_cdata.dc_sbuf, 2139 DC_SFRAME_LEN, dc_dma_map_addr, &sc->dc_saddr, BUS_DMA_NOWAIT); 2140 if (error) { 2141 device_printf(dev, "cannot get address of the descriptors\n"); 2142 error = ENXIO; 2143 goto fail; 2144 } 2145 2146 /* Allocate a busdma tag for mbufs. */ 2147 error = bus_dma_tag_create(NULL, 1, 0, BUS_SPACE_MAXADDR_32BIT, 2148 BUS_SPACE_MAXADDR, NULL, NULL, MCLBYTES, DC_TX_LIST_CNT, MCLBYTES, 2149 0, NULL, NULL, &sc->dc_mtag); 2150 if (error) { 2151 device_printf(dev, "failed to allocate busdma tag\n"); 2152 error = ENXIO; 2153 goto fail; 2154 } 2155 2156 /* Create the TX/RX busdma maps. */ 2157 for (i = 0; i < DC_TX_LIST_CNT; i++) { 2158 error = bus_dmamap_create(sc->dc_mtag, 0, 2159 &sc->dc_cdata.dc_tx_map[i]); 2160 if (error) { 2161 device_printf(dev, "failed to init TX ring\n"); 2162 error = ENXIO; 2163 goto fail; 2164 } 2165 } 2166 for (i = 0; i < DC_RX_LIST_CNT; i++) { 2167 error = bus_dmamap_create(sc->dc_mtag, 0, 2168 &sc->dc_cdata.dc_rx_map[i]); 2169 if (error) { 2170 device_printf(dev, "failed to init RX ring\n"); 2171 error = ENXIO; 2172 goto fail; 2173 } 2174 } 2175 error = bus_dmamap_create(sc->dc_mtag, 0, &sc->dc_sparemap); 2176 if (error) { 2177 device_printf(dev, "failed to init RX ring\n"); 2178 error = ENXIO; 2179 goto fail; 2180 } 2181 2182 ifp = sc->dc_ifp = if_alloc(IFT_ETHER); 2183 if (ifp == NULL) { 2184 device_printf(dev, "can not if_alloc()\n"); 2185 error = ENOSPC; 2186 goto fail; 2187 } 2188 ifp->if_softc = sc; 2189 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 2190 /* XXX: bleah, MTU gets overwritten in ether_ifattach() */ 2191 ifp->if_mtu = ETHERMTU; 2192 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 2193 ifp->if_ioctl = dc_ioctl; 2194 ifp->if_start = dc_start; 2195 ifp->if_watchdog = dc_watchdog; 2196 ifp->if_init = dc_init; 2197 ifp->if_baudrate = 10000000; 2198 IFQ_SET_MAXLEN(&ifp->if_snd, DC_TX_LIST_CNT - 1); 2199 ifp->if_snd.ifq_drv_maxlen = DC_TX_LIST_CNT - 1; 2200 IFQ_SET_READY(&ifp->if_snd); 2201 2202 /* 2203 * Do MII setup. If this is a 21143, check for a PHY on the 2204 * MII bus after applying any necessary fixups to twiddle the 2205 * GPIO bits. If we don't end up finding a PHY, restore the 2206 * old selection (SIA only or SIA/SYM) and attach the dcphy 2207 * driver instead. 2208 */ 2209 if (DC_IS_INTEL(sc)) { 2210 dc_apply_fixup(sc, IFM_AUTO); 2211 tmp = sc->dc_pmode; 2212 sc->dc_pmode = DC_PMODE_MII; 2213 } 2214 2215 /* 2216 * Setup General Purpose port mode and data so the tulip can talk 2217 * to the MII. This needs to be done before mii_phy_probe so that 2218 * we can actually see them. 2219 */ 2220 if (DC_IS_XIRCOM(sc)) { 2221 CSR_WRITE_4(sc, DC_SIAGP, DC_SIAGP_WRITE_EN | DC_SIAGP_INT1_EN | 2222 DC_SIAGP_MD_GP2_OUTPUT | DC_SIAGP_MD_GP0_OUTPUT); 2223 DELAY(10); 2224 CSR_WRITE_4(sc, DC_SIAGP, DC_SIAGP_INT1_EN | 2225 DC_SIAGP_MD_GP2_OUTPUT | DC_SIAGP_MD_GP0_OUTPUT); 2226 DELAY(10); 2227 } 2228 2229 error = mii_phy_probe(dev, &sc->dc_miibus, 2230 dc_ifmedia_upd, dc_ifmedia_sts); 2231 2232 if (error && DC_IS_INTEL(sc)) { 2233 sc->dc_pmode = tmp; 2234 if (sc->dc_pmode != DC_PMODE_SIA) 2235 sc->dc_pmode = DC_PMODE_SYM; 2236 sc->dc_flags |= DC_21143_NWAY; 2237 mii_phy_probe(dev, &sc->dc_miibus, 2238 dc_ifmedia_upd, dc_ifmedia_sts); 2239 /* 2240 * For non-MII cards, we need to have the 21143 2241 * drive the LEDs. Except there are some systems 2242 * like the NEC VersaPro NoteBook PC which have no 2243 * LEDs, and twiddling these bits has adverse effects 2244 * on them. (I.e. you suddenly can't get a link.) 2245 */ 2246 if (pci_read_config(dev, DC_PCI_CSID, 4) != 0x80281033) 2247 sc->dc_flags |= DC_TULIP_LEDS; 2248 error = 0; 2249 } 2250 2251 if (error) { 2252 device_printf(dev, "MII without any PHY!\n"); 2253 goto fail; 2254 } 2255 2256 if (DC_IS_ADMTEK(sc)) { 2257 /* 2258 * Set automatic TX underrun recovery for the ADMtek chips 2259 */ 2260 DC_SETBIT(sc, DC_AL_CR, DC_AL_CR_ATUR); 2261 } 2262 2263 /* 2264 * Tell the upper layer(s) we support long frames. 2265 */ 2266 ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header); 2267 ifp->if_capabilities |= IFCAP_VLAN_MTU; 2268 #ifdef DEVICE_POLLING 2269 ifp->if_capabilities |= IFCAP_POLLING; 2270 #endif 2271 ifp->if_capenable = ifp->if_capabilities; 2272 2273 callout_init_mtx(&sc->dc_stat_ch, &sc->dc_mtx, 0); 2274 2275 #ifdef SRM_MEDIA 2276 sc->dc_srm_media = 0; 2277 2278 /* Remember the SRM console media setting */ 2279 if (DC_IS_INTEL(sc)) { 2280 command = pci_read_config(dev, DC_PCI_CFDD, 4); 2281 command &= ~(DC_CFDD_SNOOZE_MODE | DC_CFDD_SLEEP_MODE); 2282 switch ((command >> 8) & 0xff) { 2283 case 3: 2284 sc->dc_srm_media = IFM_10_T; 2285 break; 2286 case 4: 2287 sc->dc_srm_media = IFM_10_T | IFM_FDX; 2288 break; 2289 case 5: 2290 sc->dc_srm_media = IFM_100_TX; 2291 break; 2292 case 6: 2293 sc->dc_srm_media = IFM_100_TX | IFM_FDX; 2294 break; 2295 } 2296 if (sc->dc_srm_media) 2297 sc->dc_srm_media |= IFM_ACTIVE | IFM_ETHER; 2298 } 2299 #endif 2300 2301 /* 2302 * Call MI attach routine. 2303 */ 2304 ether_ifattach(ifp, eaddr); 2305 2306 /* Hook interrupt last to avoid having to lock softc */ 2307 error = bus_setup_intr(dev, sc->dc_irq, INTR_TYPE_NET | INTR_MPSAFE, 2308 dc_intr, sc, &sc->dc_intrhand); 2309 2310 if (error) { 2311 device_printf(dev, "couldn't set up irq\n"); 2312 ether_ifdetach(ifp); 2313 goto fail; 2314 } 2315 2316 fail: 2317 if (error) 2318 dc_detach(dev); 2319 return (error); 2320 } 2321 2322 /* 2323 * Shutdown hardware and free up resources. This can be called any 2324 * time after the mutex has been initialized. It is called in both 2325 * the error case in attach and the normal detach case so it needs 2326 * to be careful about only freeing resources that have actually been 2327 * allocated. 2328 */ 2329 static int 2330 dc_detach(device_t dev) 2331 { 2332 struct dc_softc *sc; 2333 struct ifnet *ifp; 2334 struct dc_mediainfo *m; 2335 int i; 2336 2337 sc = device_get_softc(dev); 2338 KASSERT(mtx_initialized(&sc->dc_mtx), ("dc mutex not initialized")); 2339 2340 ifp = sc->dc_ifp; 2341 2342 /* These should only be active if attach succeeded */ 2343 if (device_is_attached(dev)) { 2344 DC_LOCK(sc); 2345 dc_stop(sc); 2346 DC_UNLOCK(sc); 2347 callout_drain(&sc->dc_stat_ch); 2348 ether_ifdetach(ifp); 2349 } 2350 if (ifp) 2351 if_free(ifp); 2352 if (sc->dc_miibus) 2353 device_delete_child(dev, sc->dc_miibus); 2354 bus_generic_detach(dev); 2355 2356 if (sc->dc_intrhand) 2357 bus_teardown_intr(dev, sc->dc_irq, sc->dc_intrhand); 2358 if (sc->dc_irq) 2359 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->dc_irq); 2360 if (sc->dc_res) 2361 bus_release_resource(dev, DC_RES, DC_RID, sc->dc_res); 2362 2363 if (sc->dc_cdata.dc_sbuf != NULL) 2364 bus_dmamem_free(sc->dc_stag, sc->dc_cdata.dc_sbuf, sc->dc_smap); 2365 if (sc->dc_ldata != NULL) 2366 bus_dmamem_free(sc->dc_ltag, sc->dc_ldata, sc->dc_lmap); 2367 if (sc->dc_mtag) { 2368 for (i = 0; i < DC_TX_LIST_CNT; i++) 2369 if (sc->dc_cdata.dc_tx_map[i] != NULL) 2370 bus_dmamap_destroy(sc->dc_mtag, 2371 sc->dc_cdata.dc_tx_map[i]); 2372 for (i = 0; i < DC_RX_LIST_CNT; i++) 2373 if (sc->dc_cdata.dc_rx_map[i] != NULL) 2374 bus_dmamap_destroy(sc->dc_mtag, 2375 sc->dc_cdata.dc_rx_map[i]); 2376 bus_dmamap_destroy(sc->dc_mtag, sc->dc_sparemap); 2377 } 2378 if (sc->dc_stag) 2379 bus_dma_tag_destroy(sc->dc_stag); 2380 if (sc->dc_mtag) 2381 bus_dma_tag_destroy(sc->dc_mtag); 2382 if (sc->dc_ltag) 2383 bus_dma_tag_destroy(sc->dc_ltag); 2384 2385 free(sc->dc_pnic_rx_buf, M_DEVBUF); 2386 2387 while (sc->dc_mi != NULL) { 2388 m = sc->dc_mi->dc_next; 2389 free(sc->dc_mi, M_DEVBUF); 2390 sc->dc_mi = m; 2391 } 2392 free(sc->dc_srom, M_DEVBUF); 2393 2394 mtx_destroy(&sc->dc_mtx); 2395 2396 return (0); 2397 } 2398 2399 /* 2400 * Initialize the transmit descriptors. 2401 */ 2402 static int 2403 dc_list_tx_init(struct dc_softc *sc) 2404 { 2405 struct dc_chain_data *cd; 2406 struct dc_list_data *ld; 2407 int i, nexti; 2408 2409 cd = &sc->dc_cdata; 2410 ld = sc->dc_ldata; 2411 for (i = 0; i < DC_TX_LIST_CNT; i++) { 2412 if (i == DC_TX_LIST_CNT - 1) 2413 nexti = 0; 2414 else 2415 nexti = i + 1; 2416 ld->dc_tx_list[i].dc_next = htole32(DC_TXDESC(sc, nexti)); 2417 cd->dc_tx_chain[i] = NULL; 2418 ld->dc_tx_list[i].dc_data = 0; 2419 ld->dc_tx_list[i].dc_ctl = 0; 2420 } 2421 2422 cd->dc_tx_prod = cd->dc_tx_cons = cd->dc_tx_cnt = 0; 2423 bus_dmamap_sync(sc->dc_ltag, sc->dc_lmap, 2424 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2425 return (0); 2426 } 2427 2428 2429 /* 2430 * Initialize the RX descriptors and allocate mbufs for them. Note that 2431 * we arrange the descriptors in a closed ring, so that the last descriptor 2432 * points back to the first. 2433 */ 2434 static int 2435 dc_list_rx_init(struct dc_softc *sc) 2436 { 2437 struct dc_chain_data *cd; 2438 struct dc_list_data *ld; 2439 int i, nexti; 2440 2441 cd = &sc->dc_cdata; 2442 ld = sc->dc_ldata; 2443 2444 for (i = 0; i < DC_RX_LIST_CNT; i++) { 2445 if (dc_newbuf(sc, i, 1) != 0) 2446 return (ENOBUFS); 2447 if (i == DC_RX_LIST_CNT - 1) 2448 nexti = 0; 2449 else 2450 nexti = i + 1; 2451 ld->dc_rx_list[i].dc_next = htole32(DC_RXDESC(sc, nexti)); 2452 } 2453 2454 cd->dc_rx_prod = 0; 2455 bus_dmamap_sync(sc->dc_ltag, sc->dc_lmap, 2456 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2457 return (0); 2458 } 2459 2460 static void 2461 dc_dma_map_rxbuf(arg, segs, nseg, mapsize, error) 2462 void *arg; 2463 bus_dma_segment_t *segs; 2464 int nseg; 2465 bus_size_t mapsize; 2466 int error; 2467 { 2468 struct dc_softc *sc; 2469 struct dc_desc *c; 2470 2471 sc = arg; 2472 c = &sc->dc_ldata->dc_rx_list[sc->dc_cdata.dc_rx_cur]; 2473 if (error) { 2474 sc->dc_cdata.dc_rx_err = error; 2475 return; 2476 } 2477 2478 KASSERT(nseg == 1, ("wrong number of segments, should be 1")); 2479 sc->dc_cdata.dc_rx_err = 0; 2480 c->dc_data = htole32(segs->ds_addr); 2481 } 2482 2483 /* 2484 * Initialize an RX descriptor and attach an MBUF cluster. 2485 */ 2486 static int 2487 dc_newbuf(struct dc_softc *sc, int i, int alloc) 2488 { 2489 struct mbuf *m_new; 2490 bus_dmamap_t tmp; 2491 int error; 2492 2493 if (alloc) { 2494 m_new = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR); 2495 if (m_new == NULL) 2496 return (ENOBUFS); 2497 } else { 2498 m_new = sc->dc_cdata.dc_rx_chain[i]; 2499 m_new->m_data = m_new->m_ext.ext_buf; 2500 } 2501 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 2502 m_adj(m_new, sizeof(u_int64_t)); 2503 2504 /* 2505 * If this is a PNIC chip, zero the buffer. This is part 2506 * of the workaround for the receive bug in the 82c168 and 2507 * 82c169 chips. 2508 */ 2509 if (sc->dc_flags & DC_PNIC_RX_BUG_WAR) 2510 bzero(mtod(m_new, char *), m_new->m_len); 2511 2512 /* No need to remap the mbuf if we're reusing it. */ 2513 if (alloc) { 2514 sc->dc_cdata.dc_rx_cur = i; 2515 error = bus_dmamap_load_mbuf(sc->dc_mtag, sc->dc_sparemap, 2516 m_new, dc_dma_map_rxbuf, sc, 0); 2517 if (error) { 2518 m_freem(m_new); 2519 return (error); 2520 } 2521 if (sc->dc_cdata.dc_rx_err != 0) { 2522 m_freem(m_new); 2523 return (sc->dc_cdata.dc_rx_err); 2524 } 2525 bus_dmamap_unload(sc->dc_mtag, sc->dc_cdata.dc_rx_map[i]); 2526 tmp = sc->dc_cdata.dc_rx_map[i]; 2527 sc->dc_cdata.dc_rx_map[i] = sc->dc_sparemap; 2528 sc->dc_sparemap = tmp; 2529 sc->dc_cdata.dc_rx_chain[i] = m_new; 2530 } 2531 2532 sc->dc_ldata->dc_rx_list[i].dc_ctl = htole32(DC_RXCTL_RLINK | DC_RXLEN); 2533 sc->dc_ldata->dc_rx_list[i].dc_status = htole32(DC_RXSTAT_OWN); 2534 bus_dmamap_sync(sc->dc_mtag, sc->dc_cdata.dc_rx_map[i], 2535 BUS_DMASYNC_PREREAD); 2536 bus_dmamap_sync(sc->dc_ltag, sc->dc_lmap, 2537 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2538 return (0); 2539 } 2540 2541 /* 2542 * Grrrrr. 2543 * The PNIC chip has a terrible bug in it that manifests itself during 2544 * periods of heavy activity. The exact mode of failure if difficult to 2545 * pinpoint: sometimes it only happens in promiscuous mode, sometimes it 2546 * will happen on slow machines. The bug is that sometimes instead of 2547 * uploading one complete frame during reception, it uploads what looks 2548 * like the entire contents of its FIFO memory. The frame we want is at 2549 * the end of the whole mess, but we never know exactly how much data has 2550 * been uploaded, so salvaging the frame is hard. 2551 * 2552 * There is only one way to do it reliably, and it's disgusting. 2553 * Here's what we know: 2554 * 2555 * - We know there will always be somewhere between one and three extra 2556 * descriptors uploaded. 2557 * 2558 * - We know the desired received frame will always be at the end of the 2559 * total data upload. 2560 * 2561 * - We know the size of the desired received frame because it will be 2562 * provided in the length field of the status word in the last descriptor. 2563 * 2564 * Here's what we do: 2565 * 2566 * - When we allocate buffers for the receive ring, we bzero() them. 2567 * This means that we know that the buffer contents should be all 2568 * zeros, except for data uploaded by the chip. 2569 * 2570 * - We also force the PNIC chip to upload frames that include the 2571 * ethernet CRC at the end. 2572 * 2573 * - We gather all of the bogus frame data into a single buffer. 2574 * 2575 * - We then position a pointer at the end of this buffer and scan 2576 * backwards until we encounter the first non-zero byte of data. 2577 * This is the end of the received frame. We know we will encounter 2578 * some data at the end of the frame because the CRC will always be 2579 * there, so even if the sender transmits a packet of all zeros, 2580 * we won't be fooled. 2581 * 2582 * - We know the size of the actual received frame, so we subtract 2583 * that value from the current pointer location. This brings us 2584 * to the start of the actual received packet. 2585 * 2586 * - We copy this into an mbuf and pass it on, along with the actual 2587 * frame length. 2588 * 2589 * The performance hit is tremendous, but it beats dropping frames all 2590 * the time. 2591 */ 2592 2593 #define DC_WHOLEFRAME (DC_RXSTAT_FIRSTFRAG | DC_RXSTAT_LASTFRAG) 2594 static void 2595 dc_pnic_rx_bug_war(struct dc_softc *sc, int idx) 2596 { 2597 struct dc_desc *cur_rx; 2598 struct dc_desc *c = NULL; 2599 struct mbuf *m = NULL; 2600 unsigned char *ptr; 2601 int i, total_len; 2602 u_int32_t rxstat = 0; 2603 2604 i = sc->dc_pnic_rx_bug_save; 2605 cur_rx = &sc->dc_ldata->dc_rx_list[idx]; 2606 ptr = sc->dc_pnic_rx_buf; 2607 bzero(ptr, DC_RXLEN * 5); 2608 2609 /* Copy all the bytes from the bogus buffers. */ 2610 while (1) { 2611 c = &sc->dc_ldata->dc_rx_list[i]; 2612 rxstat = le32toh(c->dc_status); 2613 m = sc->dc_cdata.dc_rx_chain[i]; 2614 bcopy(mtod(m, char *), ptr, DC_RXLEN); 2615 ptr += DC_RXLEN; 2616 /* If this is the last buffer, break out. */ 2617 if (i == idx || rxstat & DC_RXSTAT_LASTFRAG) 2618 break; 2619 dc_newbuf(sc, i, 0); 2620 DC_INC(i, DC_RX_LIST_CNT); 2621 } 2622 2623 /* Find the length of the actual receive frame. */ 2624 total_len = DC_RXBYTES(rxstat); 2625 2626 /* Scan backwards until we hit a non-zero byte. */ 2627 while (*ptr == 0x00) 2628 ptr--; 2629 2630 /* Round off. */ 2631 if ((uintptr_t)(ptr) & 0x3) 2632 ptr -= 1; 2633 2634 /* Now find the start of the frame. */ 2635 ptr -= total_len; 2636 if (ptr < sc->dc_pnic_rx_buf) 2637 ptr = sc->dc_pnic_rx_buf; 2638 2639 /* 2640 * Now copy the salvaged frame to the last mbuf and fake up 2641 * the status word to make it look like a successful 2642 * frame reception. 2643 */ 2644 dc_newbuf(sc, i, 0); 2645 bcopy(ptr, mtod(m, char *), total_len); 2646 cur_rx->dc_status = htole32(rxstat | DC_RXSTAT_FIRSTFRAG); 2647 } 2648 2649 /* 2650 * This routine searches the RX ring for dirty descriptors in the 2651 * event that the rxeof routine falls out of sync with the chip's 2652 * current descriptor pointer. This may happen sometimes as a result 2653 * of a "no RX buffer available" condition that happens when the chip 2654 * consumes all of the RX buffers before the driver has a chance to 2655 * process the RX ring. This routine may need to be called more than 2656 * once to bring the driver back in sync with the chip, however we 2657 * should still be getting RX DONE interrupts to drive the search 2658 * for new packets in the RX ring, so we should catch up eventually. 2659 */ 2660 static int 2661 dc_rx_resync(struct dc_softc *sc) 2662 { 2663 struct dc_desc *cur_rx; 2664 int i, pos; 2665 2666 pos = sc->dc_cdata.dc_rx_prod; 2667 2668 for (i = 0; i < DC_RX_LIST_CNT; i++) { 2669 cur_rx = &sc->dc_ldata->dc_rx_list[pos]; 2670 if (!(le32toh(cur_rx->dc_status) & DC_RXSTAT_OWN)) 2671 break; 2672 DC_INC(pos, DC_RX_LIST_CNT); 2673 } 2674 2675 /* If the ring really is empty, then just return. */ 2676 if (i == DC_RX_LIST_CNT) 2677 return (0); 2678 2679 /* We've fallen behing the chip: catch it. */ 2680 sc->dc_cdata.dc_rx_prod = pos; 2681 2682 return (EAGAIN); 2683 } 2684 2685 /* 2686 * A frame has been uploaded: pass the resulting mbuf chain up to 2687 * the higher level protocols. 2688 */ 2689 static void 2690 dc_rxeof(struct dc_softc *sc) 2691 { 2692 struct mbuf *m; 2693 struct ifnet *ifp; 2694 struct dc_desc *cur_rx; 2695 int i, total_len = 0; 2696 u_int32_t rxstat; 2697 2698 DC_LOCK_ASSERT(sc); 2699 2700 ifp = sc->dc_ifp; 2701 i = sc->dc_cdata.dc_rx_prod; 2702 2703 bus_dmamap_sync(sc->dc_ltag, sc->dc_lmap, BUS_DMASYNC_POSTREAD); 2704 while (!(le32toh(sc->dc_ldata->dc_rx_list[i].dc_status) & 2705 DC_RXSTAT_OWN)) { 2706 #ifdef DEVICE_POLLING 2707 if (ifp->if_flags & IFF_POLLING) { 2708 if (sc->rxcycles <= 0) 2709 break; 2710 sc->rxcycles--; 2711 } 2712 #endif 2713 cur_rx = &sc->dc_ldata->dc_rx_list[i]; 2714 rxstat = le32toh(cur_rx->dc_status); 2715 m = sc->dc_cdata.dc_rx_chain[i]; 2716 bus_dmamap_sync(sc->dc_mtag, sc->dc_cdata.dc_rx_map[i], 2717 BUS_DMASYNC_POSTREAD); 2718 total_len = DC_RXBYTES(rxstat); 2719 2720 if (sc->dc_flags & DC_PNIC_RX_BUG_WAR) { 2721 if ((rxstat & DC_WHOLEFRAME) != DC_WHOLEFRAME) { 2722 if (rxstat & DC_RXSTAT_FIRSTFRAG) 2723 sc->dc_pnic_rx_bug_save = i; 2724 if ((rxstat & DC_RXSTAT_LASTFRAG) == 0) { 2725 DC_INC(i, DC_RX_LIST_CNT); 2726 continue; 2727 } 2728 dc_pnic_rx_bug_war(sc, i); 2729 rxstat = le32toh(cur_rx->dc_status); 2730 total_len = DC_RXBYTES(rxstat); 2731 } 2732 } 2733 2734 /* 2735 * If an error occurs, update stats, clear the 2736 * status word and leave the mbuf cluster in place: 2737 * it should simply get re-used next time this descriptor 2738 * comes up in the ring. However, don't report long 2739 * frames as errors since they could be vlans. 2740 */ 2741 if ((rxstat & DC_RXSTAT_RXERR)) { 2742 if (!(rxstat & DC_RXSTAT_GIANT) || 2743 (rxstat & (DC_RXSTAT_CRCERR | DC_RXSTAT_DRIBBLE | 2744 DC_RXSTAT_MIIERE | DC_RXSTAT_COLLSEEN | 2745 DC_RXSTAT_RUNT | DC_RXSTAT_DE))) { 2746 ifp->if_ierrors++; 2747 if (rxstat & DC_RXSTAT_COLLSEEN) 2748 ifp->if_collisions++; 2749 dc_newbuf(sc, i, 0); 2750 if (rxstat & DC_RXSTAT_CRCERR) { 2751 DC_INC(i, DC_RX_LIST_CNT); 2752 continue; 2753 } else { 2754 dc_init_locked(sc); 2755 return; 2756 } 2757 } 2758 } 2759 2760 /* No errors; receive the packet. */ 2761 total_len -= ETHER_CRC_LEN; 2762 #ifdef __i386__ 2763 /* 2764 * On the x86 we do not have alignment problems, so try to 2765 * allocate a new buffer for the receive ring, and pass up 2766 * the one where the packet is already, saving the expensive 2767 * copy done in m_devget(). 2768 * If we are on an architecture with alignment problems, or 2769 * if the allocation fails, then use m_devget and leave the 2770 * existing buffer in the receive ring. 2771 */ 2772 if (dc_quick && dc_newbuf(sc, i, 1) == 0) { 2773 m->m_pkthdr.rcvif = ifp; 2774 m->m_pkthdr.len = m->m_len = total_len; 2775 DC_INC(i, DC_RX_LIST_CNT); 2776 } else 2777 #endif 2778 { 2779 struct mbuf *m0; 2780 2781 m0 = m_devget(mtod(m, char *), total_len, 2782 ETHER_ALIGN, ifp, NULL); 2783 dc_newbuf(sc, i, 0); 2784 DC_INC(i, DC_RX_LIST_CNT); 2785 if (m0 == NULL) { 2786 ifp->if_ierrors++; 2787 continue; 2788 } 2789 m = m0; 2790 } 2791 2792 ifp->if_ipackets++; 2793 DC_UNLOCK(sc); 2794 (*ifp->if_input)(ifp, m); 2795 DC_LOCK(sc); 2796 } 2797 2798 sc->dc_cdata.dc_rx_prod = i; 2799 } 2800 2801 /* 2802 * A frame was downloaded to the chip. It's safe for us to clean up 2803 * the list buffers. 2804 */ 2805 2806 static void 2807 dc_txeof(struct dc_softc *sc) 2808 { 2809 struct dc_desc *cur_tx = NULL; 2810 struct ifnet *ifp; 2811 int idx; 2812 u_int32_t ctl, txstat; 2813 2814 ifp = sc->dc_ifp; 2815 2816 /* 2817 * Go through our tx list and free mbufs for those 2818 * frames that have been transmitted. 2819 */ 2820 bus_dmamap_sync(sc->dc_ltag, sc->dc_lmap, BUS_DMASYNC_POSTREAD); 2821 idx = sc->dc_cdata.dc_tx_cons; 2822 while (idx != sc->dc_cdata.dc_tx_prod) { 2823 2824 cur_tx = &sc->dc_ldata->dc_tx_list[idx]; 2825 txstat = le32toh(cur_tx->dc_status); 2826 ctl = le32toh(cur_tx->dc_ctl); 2827 2828 if (txstat & DC_TXSTAT_OWN) 2829 break; 2830 2831 if (!(ctl & DC_TXCTL_LASTFRAG) || ctl & DC_TXCTL_SETUP) { 2832 if (ctl & DC_TXCTL_SETUP) { 2833 /* 2834 * Yes, the PNIC is so brain damaged 2835 * that it will sometimes generate a TX 2836 * underrun error while DMAing the RX 2837 * filter setup frame. If we detect this, 2838 * we have to send the setup frame again, 2839 * or else the filter won't be programmed 2840 * correctly. 2841 */ 2842 if (DC_IS_PNIC(sc)) { 2843 if (txstat & DC_TXSTAT_ERRSUM) 2844 dc_setfilt(sc); 2845 } 2846 sc->dc_cdata.dc_tx_chain[idx] = NULL; 2847 } 2848 sc->dc_cdata.dc_tx_cnt--; 2849 DC_INC(idx, DC_TX_LIST_CNT); 2850 continue; 2851 } 2852 2853 if (DC_IS_XIRCOM(sc) || DC_IS_CONEXANT(sc)) { 2854 /* 2855 * XXX: Why does my Xircom taunt me so? 2856 * For some reason it likes setting the CARRLOST flag 2857 * even when the carrier is there. wtf?!? 2858 * Who knows, but Conexant chips have the 2859 * same problem. Maybe they took lessons 2860 * from Xircom. 2861 */ 2862 if (/*sc->dc_type == DC_TYPE_21143 &&*/ 2863 sc->dc_pmode == DC_PMODE_MII && 2864 ((txstat & 0xFFFF) & ~(DC_TXSTAT_ERRSUM | 2865 DC_TXSTAT_NOCARRIER))) 2866 txstat &= ~DC_TXSTAT_ERRSUM; 2867 } else { 2868 if (/*sc->dc_type == DC_TYPE_21143 &&*/ 2869 sc->dc_pmode == DC_PMODE_MII && 2870 ((txstat & 0xFFFF) & ~(DC_TXSTAT_ERRSUM | 2871 DC_TXSTAT_NOCARRIER | DC_TXSTAT_CARRLOST))) 2872 txstat &= ~DC_TXSTAT_ERRSUM; 2873 } 2874 2875 if (txstat & DC_TXSTAT_ERRSUM) { 2876 ifp->if_oerrors++; 2877 if (txstat & DC_TXSTAT_EXCESSCOLL) 2878 ifp->if_collisions++; 2879 if (txstat & DC_TXSTAT_LATECOLL) 2880 ifp->if_collisions++; 2881 if (!(txstat & DC_TXSTAT_UNDERRUN)) { 2882 dc_init_locked(sc); 2883 return; 2884 } 2885 } 2886 2887 ifp->if_collisions += (txstat & DC_TXSTAT_COLLCNT) >> 3; 2888 2889 ifp->if_opackets++; 2890 if (sc->dc_cdata.dc_tx_chain[idx] != NULL) { 2891 bus_dmamap_sync(sc->dc_mtag, 2892 sc->dc_cdata.dc_tx_map[idx], 2893 BUS_DMASYNC_POSTWRITE); 2894 bus_dmamap_unload(sc->dc_mtag, 2895 sc->dc_cdata.dc_tx_map[idx]); 2896 m_freem(sc->dc_cdata.dc_tx_chain[idx]); 2897 sc->dc_cdata.dc_tx_chain[idx] = NULL; 2898 } 2899 2900 sc->dc_cdata.dc_tx_cnt--; 2901 DC_INC(idx, DC_TX_LIST_CNT); 2902 } 2903 2904 if (idx != sc->dc_cdata.dc_tx_cons) { 2905 /* Some buffers have been freed. */ 2906 sc->dc_cdata.dc_tx_cons = idx; 2907 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 2908 } 2909 ifp->if_timer = (sc->dc_cdata.dc_tx_cnt == 0) ? 0 : 5; 2910 } 2911 2912 static void 2913 dc_tick(void *xsc) 2914 { 2915 struct dc_softc *sc; 2916 struct mii_data *mii; 2917 struct ifnet *ifp; 2918 u_int32_t r; 2919 2920 sc = xsc; 2921 DC_LOCK_ASSERT(sc); 2922 ifp = sc->dc_ifp; 2923 mii = device_get_softc(sc->dc_miibus); 2924 2925 if (sc->dc_flags & DC_REDUCED_MII_POLL) { 2926 if (sc->dc_flags & DC_21143_NWAY) { 2927 r = CSR_READ_4(sc, DC_10BTSTAT); 2928 if (IFM_SUBTYPE(mii->mii_media_active) == 2929 IFM_100_TX && (r & DC_TSTAT_LS100)) { 2930 sc->dc_link = 0; 2931 mii_mediachg(mii); 2932 } 2933 if (IFM_SUBTYPE(mii->mii_media_active) == 2934 IFM_10_T && (r & DC_TSTAT_LS10)) { 2935 sc->dc_link = 0; 2936 mii_mediachg(mii); 2937 } 2938 if (sc->dc_link == 0) 2939 mii_tick(mii); 2940 } else { 2941 r = CSR_READ_4(sc, DC_ISR); 2942 if ((r & DC_ISR_RX_STATE) == DC_RXSTATE_WAIT && 2943 sc->dc_cdata.dc_tx_cnt == 0) { 2944 mii_tick(mii); 2945 if (!(mii->mii_media_status & IFM_ACTIVE)) 2946 sc->dc_link = 0; 2947 } 2948 } 2949 } else 2950 mii_tick(mii); 2951 2952 /* 2953 * When the init routine completes, we expect to be able to send 2954 * packets right away, and in fact the network code will send a 2955 * gratuitous ARP the moment the init routine marks the interface 2956 * as running. However, even though the MAC may have been initialized, 2957 * there may be a delay of a few seconds before the PHY completes 2958 * autonegotiation and the link is brought up. Any transmissions 2959 * made during that delay will be lost. Dealing with this is tricky: 2960 * we can't just pause in the init routine while waiting for the 2961 * PHY to come ready since that would bring the whole system to 2962 * a screeching halt for several seconds. 2963 * 2964 * What we do here is prevent the TX start routine from sending 2965 * any packets until a link has been established. After the 2966 * interface has been initialized, the tick routine will poll 2967 * the state of the PHY until the IFM_ACTIVE flag is set. Until 2968 * that time, packets will stay in the send queue, and once the 2969 * link comes up, they will be flushed out to the wire. 2970 */ 2971 if (!sc->dc_link && mii->mii_media_status & IFM_ACTIVE && 2972 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) { 2973 sc->dc_link++; 2974 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 2975 dc_start_locked(ifp); 2976 } 2977 2978 if (sc->dc_flags & DC_21143_NWAY && !sc->dc_link) 2979 callout_reset(&sc->dc_stat_ch, hz/10, dc_tick, sc); 2980 else 2981 callout_reset(&sc->dc_stat_ch, hz, dc_tick, sc); 2982 } 2983 2984 /* 2985 * A transmit underrun has occurred. Back off the transmit threshold, 2986 * or switch to store and forward mode if we have to. 2987 */ 2988 static void 2989 dc_tx_underrun(struct dc_softc *sc) 2990 { 2991 u_int32_t isr; 2992 int i; 2993 2994 if (DC_IS_DAVICOM(sc)) 2995 dc_init_locked(sc); 2996 2997 if (DC_IS_INTEL(sc)) { 2998 /* 2999 * The real 21143 requires that the transmitter be idle 3000 * in order to change the transmit threshold or store 3001 * and forward state. 3002 */ 3003 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_TX_ON); 3004 3005 for (i = 0; i < DC_TIMEOUT; i++) { 3006 isr = CSR_READ_4(sc, DC_ISR); 3007 if (isr & DC_ISR_TX_IDLE) 3008 break; 3009 DELAY(10); 3010 } 3011 if (i == DC_TIMEOUT) { 3012 if_printf(sc->dc_ifp, 3013 "failed to force tx to idle state\n"); 3014 dc_init_locked(sc); 3015 } 3016 } 3017 3018 if_printf(sc->dc_ifp, "TX underrun -- "); 3019 sc->dc_txthresh += DC_TXTHRESH_INC; 3020 if (sc->dc_txthresh > DC_TXTHRESH_MAX) { 3021 printf("using store and forward mode\n"); 3022 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_STORENFWD); 3023 } else { 3024 printf("increasing TX threshold\n"); 3025 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_TX_THRESH); 3026 DC_SETBIT(sc, DC_NETCFG, sc->dc_txthresh); 3027 } 3028 3029 if (DC_IS_INTEL(sc)) 3030 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_TX_ON); 3031 } 3032 3033 #ifdef DEVICE_POLLING 3034 static poll_handler_t dc_poll; 3035 3036 static void 3037 dc_poll(struct ifnet *ifp, enum poll_cmd cmd, int count) 3038 { 3039 struct dc_softc *sc = ifp->if_softc; 3040 3041 if (!(ifp->if_capenable & IFCAP_POLLING)) { 3042 ether_poll_deregister(ifp); 3043 cmd = POLL_DEREGISTER; 3044 } 3045 if (cmd == POLL_DEREGISTER) { /* final call, enable interrupts */ 3046 /* Re-enable interrupts. */ 3047 CSR_WRITE_4(sc, DC_IMR, DC_INTRS); 3048 return; 3049 } 3050 DC_LOCK(sc); 3051 sc->rxcycles = count; 3052 dc_rxeof(sc); 3053 dc_txeof(sc); 3054 if (!IFQ_IS_EMPTY(&ifp->if_snd) && 3055 !(ifp->if_drv_flags & IFF_DRV_OACTIVE)) 3056 dc_start_locked(ifp); 3057 3058 if (cmd == POLL_AND_CHECK_STATUS) { /* also check status register */ 3059 u_int32_t status; 3060 3061 status = CSR_READ_4(sc, DC_ISR); 3062 status &= (DC_ISR_RX_WATDOGTIMEO | DC_ISR_RX_NOBUF | 3063 DC_ISR_TX_NOBUF | DC_ISR_TX_IDLE | DC_ISR_TX_UNDERRUN | 3064 DC_ISR_BUS_ERR); 3065 if (!status) { 3066 DC_UNLOCK(sc); 3067 return; 3068 } 3069 /* ack what we have */ 3070 CSR_WRITE_4(sc, DC_ISR, status); 3071 3072 if (status & (DC_ISR_RX_WATDOGTIMEO | DC_ISR_RX_NOBUF)) { 3073 u_int32_t r = CSR_READ_4(sc, DC_FRAMESDISCARDED); 3074 ifp->if_ierrors += (r & 0xffff) + ((r >> 17) & 0x7ff); 3075 3076 if (dc_rx_resync(sc)) 3077 dc_rxeof(sc); 3078 } 3079 /* restart transmit unit if necessary */ 3080 if (status & DC_ISR_TX_IDLE && sc->dc_cdata.dc_tx_cnt) 3081 CSR_WRITE_4(sc, DC_TXSTART, 0xFFFFFFFF); 3082 3083 if (status & DC_ISR_TX_UNDERRUN) 3084 dc_tx_underrun(sc); 3085 3086 if (status & DC_ISR_BUS_ERR) { 3087 if_printf(ifp, "dc_poll: bus error\n"); 3088 dc_reset(sc); 3089 dc_init_locked(sc); 3090 } 3091 } 3092 DC_UNLOCK(sc); 3093 } 3094 #endif /* DEVICE_POLLING */ 3095 3096 static void 3097 dc_intr(void *arg) 3098 { 3099 struct dc_softc *sc; 3100 struct ifnet *ifp; 3101 u_int32_t status; 3102 3103 sc = arg; 3104 3105 if (sc->suspended) 3106 return; 3107 3108 if ((CSR_READ_4(sc, DC_ISR) & DC_INTRS) == 0) 3109 return; 3110 3111 DC_LOCK(sc); 3112 ifp = sc->dc_ifp; 3113 #ifdef DEVICE_POLLING 3114 if (ifp->if_flags & IFF_POLLING) 3115 goto done; 3116 if ((ifp->if_capenable & IFCAP_POLLING) && 3117 ether_poll_register(dc_poll, ifp)) { /* ok, disable interrupts */ 3118 CSR_WRITE_4(sc, DC_IMR, 0x00000000); 3119 goto done; 3120 } 3121 #endif 3122 3123 /* Suppress unwanted interrupts */ 3124 if (!(ifp->if_flags & IFF_UP)) { 3125 if (CSR_READ_4(sc, DC_ISR) & DC_INTRS) 3126 dc_stop(sc); 3127 DC_UNLOCK(sc); 3128 return; 3129 } 3130 3131 /* Disable interrupts. */ 3132 CSR_WRITE_4(sc, DC_IMR, 0x00000000); 3133 3134 while (((status = CSR_READ_4(sc, DC_ISR)) & DC_INTRS) 3135 && status != 0xFFFFFFFF) { 3136 3137 CSR_WRITE_4(sc, DC_ISR, status); 3138 3139 if (status & DC_ISR_RX_OK) { 3140 int curpkts; 3141 curpkts = ifp->if_ipackets; 3142 dc_rxeof(sc); 3143 if (curpkts == ifp->if_ipackets) { 3144 while (dc_rx_resync(sc)) 3145 dc_rxeof(sc); 3146 } 3147 } 3148 3149 if (status & (DC_ISR_TX_OK | DC_ISR_TX_NOBUF)) 3150 dc_txeof(sc); 3151 3152 if (status & DC_ISR_TX_IDLE) { 3153 dc_txeof(sc); 3154 if (sc->dc_cdata.dc_tx_cnt) { 3155 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_TX_ON); 3156 CSR_WRITE_4(sc, DC_TXSTART, 0xFFFFFFFF); 3157 } 3158 } 3159 3160 if (status & DC_ISR_TX_UNDERRUN) 3161 dc_tx_underrun(sc); 3162 3163 if ((status & DC_ISR_RX_WATDOGTIMEO) 3164 || (status & DC_ISR_RX_NOBUF)) { 3165 int curpkts; 3166 curpkts = ifp->if_ipackets; 3167 dc_rxeof(sc); 3168 if (curpkts == ifp->if_ipackets) { 3169 while (dc_rx_resync(sc)) 3170 dc_rxeof(sc); 3171 } 3172 } 3173 3174 if (status & DC_ISR_BUS_ERR) { 3175 dc_reset(sc); 3176 dc_init_locked(sc); 3177 } 3178 } 3179 3180 /* Re-enable interrupts. */ 3181 CSR_WRITE_4(sc, DC_IMR, DC_INTRS); 3182 3183 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 3184 dc_start_locked(ifp); 3185 3186 #ifdef DEVICE_POLLING 3187 done: 3188 #endif 3189 3190 DC_UNLOCK(sc); 3191 } 3192 3193 static void 3194 dc_dma_map_txbuf(arg, segs, nseg, mapsize, error) 3195 void *arg; 3196 bus_dma_segment_t *segs; 3197 int nseg; 3198 bus_size_t mapsize; 3199 int error; 3200 { 3201 struct dc_softc *sc; 3202 struct dc_desc *f; 3203 int cur, first, frag, i; 3204 3205 sc = arg; 3206 if (error) { 3207 sc->dc_cdata.dc_tx_err = error; 3208 return; 3209 } 3210 3211 first = cur = frag = sc->dc_cdata.dc_tx_prod; 3212 for (i = 0; i < nseg; i++) { 3213 if ((sc->dc_flags & DC_TX_ADMTEK_WAR) && 3214 (frag == (DC_TX_LIST_CNT - 1)) && 3215 (first != sc->dc_cdata.dc_tx_first)) { 3216 bus_dmamap_unload(sc->dc_mtag, 3217 sc->dc_cdata.dc_tx_map[first]); 3218 sc->dc_cdata.dc_tx_err = ENOBUFS; 3219 return; 3220 } 3221 3222 f = &sc->dc_ldata->dc_tx_list[frag]; 3223 f->dc_ctl = htole32(DC_TXCTL_TLINK | segs[i].ds_len); 3224 if (i == 0) { 3225 f->dc_status = 0; 3226 f->dc_ctl |= htole32(DC_TXCTL_FIRSTFRAG); 3227 } else 3228 f->dc_status = htole32(DC_TXSTAT_OWN); 3229 f->dc_data = htole32(segs[i].ds_addr); 3230 cur = frag; 3231 DC_INC(frag, DC_TX_LIST_CNT); 3232 } 3233 3234 sc->dc_cdata.dc_tx_err = 0; 3235 sc->dc_cdata.dc_tx_prod = frag; 3236 sc->dc_cdata.dc_tx_cnt += nseg; 3237 sc->dc_ldata->dc_tx_list[cur].dc_ctl |= htole32(DC_TXCTL_LASTFRAG); 3238 sc->dc_cdata.dc_tx_chain[cur] = sc->dc_cdata.dc_tx_mapping; 3239 if (sc->dc_flags & DC_TX_INTR_FIRSTFRAG) 3240 sc->dc_ldata->dc_tx_list[first].dc_ctl |= 3241 htole32(DC_TXCTL_FINT); 3242 if (sc->dc_flags & DC_TX_INTR_ALWAYS) 3243 sc->dc_ldata->dc_tx_list[cur].dc_ctl |= htole32(DC_TXCTL_FINT); 3244 if (sc->dc_flags & DC_TX_USE_TX_INTR && sc->dc_cdata.dc_tx_cnt > 64) 3245 sc->dc_ldata->dc_tx_list[cur].dc_ctl |= htole32(DC_TXCTL_FINT); 3246 sc->dc_ldata->dc_tx_list[first].dc_status = htole32(DC_TXSTAT_OWN); 3247 } 3248 3249 /* 3250 * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data 3251 * pointers to the fragment pointers. 3252 */ 3253 static int 3254 dc_encap(struct dc_softc *sc, struct mbuf **m_head) 3255 { 3256 struct mbuf *m; 3257 int error, idx, chainlen = 0; 3258 3259 /* 3260 * If there's no way we can send any packets, return now. 3261 */ 3262 if (DC_TX_LIST_CNT - sc->dc_cdata.dc_tx_cnt < 6) 3263 return (ENOBUFS); 3264 3265 /* 3266 * Count the number of frags in this chain to see if 3267 * we need to m_defrag. Since the descriptor list is shared 3268 * by all packets, we'll m_defrag long chains so that they 3269 * do not use up the entire list, even if they would fit. 3270 */ 3271 for (m = *m_head; m != NULL; m = m->m_next) 3272 chainlen++; 3273 3274 if ((chainlen > DC_TX_LIST_CNT / 4) || 3275 ((DC_TX_LIST_CNT - (chainlen + sc->dc_cdata.dc_tx_cnt)) < 6)) { 3276 m = m_defrag(*m_head, M_DONTWAIT); 3277 if (m == NULL) 3278 return (ENOBUFS); 3279 *m_head = m; 3280 } 3281 3282 /* 3283 * Start packing the mbufs in this chain into 3284 * the fragment pointers. Stop when we run out 3285 * of fragments or hit the end of the mbuf chain. 3286 */ 3287 idx = sc->dc_cdata.dc_tx_prod; 3288 sc->dc_cdata.dc_tx_mapping = *m_head; 3289 error = bus_dmamap_load_mbuf(sc->dc_mtag, sc->dc_cdata.dc_tx_map[idx], 3290 *m_head, dc_dma_map_txbuf, sc, 0); 3291 if (error) 3292 return (error); 3293 if (sc->dc_cdata.dc_tx_err != 0) 3294 return (sc->dc_cdata.dc_tx_err); 3295 bus_dmamap_sync(sc->dc_mtag, sc->dc_cdata.dc_tx_map[idx], 3296 BUS_DMASYNC_PREWRITE); 3297 bus_dmamap_sync(sc->dc_ltag, sc->dc_lmap, 3298 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3299 return (0); 3300 } 3301 3302 /* 3303 * Main transmit routine. To avoid having to do mbuf copies, we put pointers 3304 * to the mbuf data regions directly in the transmit lists. We also save a 3305 * copy of the pointers since the transmit list fragment pointers are 3306 * physical addresses. 3307 */ 3308 3309 static void 3310 dc_start(struct ifnet *ifp) 3311 { 3312 struct dc_softc *sc; 3313 3314 sc = ifp->if_softc; 3315 DC_LOCK(sc); 3316 dc_start_locked(ifp); 3317 DC_UNLOCK(sc); 3318 } 3319 3320 static void 3321 dc_start_locked(struct ifnet *ifp) 3322 { 3323 struct dc_softc *sc; 3324 struct mbuf *m_head = NULL, *m; 3325 unsigned int queued = 0; 3326 int idx; 3327 3328 sc = ifp->if_softc; 3329 3330 DC_LOCK_ASSERT(sc); 3331 3332 if (!sc->dc_link && ifp->if_snd.ifq_len < 10) 3333 return; 3334 3335 if (ifp->if_drv_flags & IFF_DRV_OACTIVE) 3336 return; 3337 3338 idx = sc->dc_cdata.dc_tx_first = sc->dc_cdata.dc_tx_prod; 3339 3340 while (sc->dc_cdata.dc_tx_chain[idx] == NULL) { 3341 IFQ_DRV_DEQUEUE(&ifp->if_snd, m_head); 3342 if (m_head == NULL) 3343 break; 3344 3345 if (sc->dc_flags & DC_TX_COALESCE && 3346 (m_head->m_next != NULL || 3347 sc->dc_flags & DC_TX_ALIGN)) { 3348 m = m_defrag(m_head, M_DONTWAIT); 3349 if (m == NULL) { 3350 IFQ_DRV_PREPEND(&ifp->if_snd, m_head); 3351 ifp->if_drv_flags |= IFF_DRV_OACTIVE; 3352 break; 3353 } else { 3354 m_head = m; 3355 } 3356 } 3357 3358 if (dc_encap(sc, &m_head)) { 3359 IFQ_DRV_PREPEND(&ifp->if_snd, m_head); 3360 ifp->if_drv_flags |= IFF_DRV_OACTIVE; 3361 break; 3362 } 3363 idx = sc->dc_cdata.dc_tx_prod; 3364 3365 queued++; 3366 /* 3367 * If there's a BPF listener, bounce a copy of this frame 3368 * to him. 3369 */ 3370 BPF_MTAP(ifp, m_head); 3371 3372 if (sc->dc_flags & DC_TX_ONE) { 3373 ifp->if_drv_flags |= IFF_DRV_OACTIVE; 3374 break; 3375 } 3376 } 3377 3378 if (queued > 0) { 3379 /* Transmit */ 3380 if (!(sc->dc_flags & DC_TX_POLL)) 3381 CSR_WRITE_4(sc, DC_TXSTART, 0xFFFFFFFF); 3382 3383 /* 3384 * Set a timeout in case the chip goes out to lunch. 3385 */ 3386 ifp->if_timer = 5; 3387 } 3388 } 3389 3390 static void 3391 dc_init(void *xsc) 3392 { 3393 struct dc_softc *sc = xsc; 3394 3395 DC_LOCK(sc); 3396 dc_init_locked(sc); 3397 #ifdef SRM_MEDIA 3398 if(sc->dc_srm_media) { 3399 struct ifreq ifr; 3400 struct mii_data *mii; 3401 3402 ifr.ifr_media = sc->dc_srm_media; 3403 sc->dc_srm_media = 0; 3404 DC_UNLOCK(sc); 3405 mii = device_get_softc(sc->dc_miibus); 3406 ifmedia_ioctl(sc->dc_ifp, &ifr, &mii->mii_media, SIOCSIFMEDIA); 3407 } else 3408 #endif 3409 DC_UNLOCK(sc); 3410 } 3411 3412 static void 3413 dc_init_locked(struct dc_softc *sc) 3414 { 3415 struct ifnet *ifp = sc->dc_ifp; 3416 struct mii_data *mii; 3417 3418 DC_LOCK_ASSERT(sc); 3419 3420 mii = device_get_softc(sc->dc_miibus); 3421 3422 /* 3423 * Cancel pending I/O and free all RX/TX buffers. 3424 */ 3425 dc_stop(sc); 3426 dc_reset(sc); 3427 3428 /* 3429 * Set cache alignment and burst length. 3430 */ 3431 if (DC_IS_ASIX(sc) || DC_IS_DAVICOM(sc)) 3432 CSR_WRITE_4(sc, DC_BUSCTL, 0); 3433 else 3434 CSR_WRITE_4(sc, DC_BUSCTL, DC_BUSCTL_MRME | DC_BUSCTL_MRLE); 3435 /* 3436 * Evenly share the bus between receive and transmit process. 3437 */ 3438 if (DC_IS_INTEL(sc)) 3439 DC_SETBIT(sc, DC_BUSCTL, DC_BUSCTL_ARBITRATION); 3440 if (DC_IS_DAVICOM(sc) || DC_IS_INTEL(sc)) { 3441 DC_SETBIT(sc, DC_BUSCTL, DC_BURSTLEN_USECA); 3442 } else { 3443 DC_SETBIT(sc, DC_BUSCTL, DC_BURSTLEN_16LONG); 3444 } 3445 if (sc->dc_flags & DC_TX_POLL) 3446 DC_SETBIT(sc, DC_BUSCTL, DC_TXPOLL_1); 3447 switch(sc->dc_cachesize) { 3448 case 32: 3449 DC_SETBIT(sc, DC_BUSCTL, DC_CACHEALIGN_32LONG); 3450 break; 3451 case 16: 3452 DC_SETBIT(sc, DC_BUSCTL, DC_CACHEALIGN_16LONG); 3453 break; 3454 case 8: 3455 DC_SETBIT(sc, DC_BUSCTL, DC_CACHEALIGN_8LONG); 3456 break; 3457 case 0: 3458 default: 3459 DC_SETBIT(sc, DC_BUSCTL, DC_CACHEALIGN_NONE); 3460 break; 3461 } 3462 3463 if (sc->dc_flags & DC_TX_STORENFWD) 3464 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_STORENFWD); 3465 else { 3466 if (sc->dc_txthresh > DC_TXTHRESH_MAX) { 3467 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_STORENFWD); 3468 } else { 3469 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_STORENFWD); 3470 DC_SETBIT(sc, DC_NETCFG, sc->dc_txthresh); 3471 } 3472 } 3473 3474 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_NO_RXCRC); 3475 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_TX_BACKOFF); 3476 3477 if (DC_IS_MACRONIX(sc) || DC_IS_PNICII(sc)) { 3478 /* 3479 * The app notes for the 98713 and 98715A say that 3480 * in order to have the chips operate properly, a magic 3481 * number must be written to CSR16. Macronix does not 3482 * document the meaning of these bits so there's no way 3483 * to know exactly what they do. The 98713 has a magic 3484 * number all its own; the rest all use a different one. 3485 */ 3486 DC_CLRBIT(sc, DC_MX_MAGICPACKET, 0xFFFF0000); 3487 if (sc->dc_type == DC_TYPE_98713) 3488 DC_SETBIT(sc, DC_MX_MAGICPACKET, DC_MX_MAGIC_98713); 3489 else 3490 DC_SETBIT(sc, DC_MX_MAGICPACKET, DC_MX_MAGIC_98715); 3491 } 3492 3493 if (DC_IS_XIRCOM(sc)) { 3494 /* 3495 * setup General Purpose Port mode and data so the tulip 3496 * can talk to the MII. 3497 */ 3498 CSR_WRITE_4(sc, DC_SIAGP, DC_SIAGP_WRITE_EN | DC_SIAGP_INT1_EN | 3499 DC_SIAGP_MD_GP2_OUTPUT | DC_SIAGP_MD_GP0_OUTPUT); 3500 DELAY(10); 3501 CSR_WRITE_4(sc, DC_SIAGP, DC_SIAGP_INT1_EN | 3502 DC_SIAGP_MD_GP2_OUTPUT | DC_SIAGP_MD_GP0_OUTPUT); 3503 DELAY(10); 3504 } 3505 3506 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_TX_THRESH); 3507 DC_SETBIT(sc, DC_NETCFG, DC_TXTHRESH_MIN); 3508 3509 /* Init circular RX list. */ 3510 if (dc_list_rx_init(sc) == ENOBUFS) { 3511 if_printf(ifp, 3512 "initialization failed: no memory for rx buffers\n"); 3513 dc_stop(sc); 3514 return; 3515 } 3516 3517 /* 3518 * Init TX descriptors. 3519 */ 3520 dc_list_tx_init(sc); 3521 3522 /* 3523 * Load the address of the RX list. 3524 */ 3525 CSR_WRITE_4(sc, DC_RXADDR, DC_RXDESC(sc, 0)); 3526 CSR_WRITE_4(sc, DC_TXADDR, DC_TXDESC(sc, 0)); 3527 3528 /* 3529 * Enable interrupts. 3530 */ 3531 #ifdef DEVICE_POLLING 3532 /* 3533 * ... but only if we are not polling, and make sure they are off in 3534 * the case of polling. Some cards (e.g. fxp) turn interrupts on 3535 * after a reset. 3536 */ 3537 if (ifp->if_flags & IFF_POLLING) 3538 CSR_WRITE_4(sc, DC_IMR, 0x00000000); 3539 else 3540 #endif 3541 CSR_WRITE_4(sc, DC_IMR, DC_INTRS); 3542 CSR_WRITE_4(sc, DC_ISR, 0xFFFFFFFF); 3543 3544 /* Enable transmitter. */ 3545 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_TX_ON); 3546 3547 /* 3548 * If this is an Intel 21143 and we're not using the 3549 * MII port, program the LED control pins so we get 3550 * link and activity indications. 3551 */ 3552 if (sc->dc_flags & DC_TULIP_LEDS) { 3553 CSR_WRITE_4(sc, DC_WATCHDOG, 3554 DC_WDOG_CTLWREN | DC_WDOG_LINK | DC_WDOG_ACTIVITY); 3555 CSR_WRITE_4(sc, DC_WATCHDOG, 0); 3556 } 3557 3558 /* 3559 * Load the RX/multicast filter. We do this sort of late 3560 * because the filter programming scheme on the 21143 and 3561 * some clones requires DMAing a setup frame via the TX 3562 * engine, and we need the transmitter enabled for that. 3563 */ 3564 dc_setfilt(sc); 3565 3566 /* Enable receiver. */ 3567 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_ON); 3568 CSR_WRITE_4(sc, DC_RXSTART, 0xFFFFFFFF); 3569 3570 mii_mediachg(mii); 3571 dc_setcfg(sc, sc->dc_if_media); 3572 3573 ifp->if_drv_flags |= IFF_DRV_RUNNING; 3574 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 3575 3576 /* Don't start the ticker if this is a homePNA link. */ 3577 if (IFM_SUBTYPE(mii->mii_media.ifm_media) == IFM_HPNA_1) 3578 sc->dc_link = 1; 3579 else { 3580 if (sc->dc_flags & DC_21143_NWAY) 3581 callout_reset(&sc->dc_stat_ch, hz/10, dc_tick, sc); 3582 else 3583 callout_reset(&sc->dc_stat_ch, hz, dc_tick, sc); 3584 } 3585 } 3586 3587 /* 3588 * Set media options. 3589 */ 3590 static int 3591 dc_ifmedia_upd(struct ifnet *ifp) 3592 { 3593 struct dc_softc *sc; 3594 struct mii_data *mii; 3595 struct ifmedia *ifm; 3596 3597 sc = ifp->if_softc; 3598 mii = device_get_softc(sc->dc_miibus); 3599 DC_LOCK(sc); 3600 mii_mediachg(mii); 3601 ifm = &mii->mii_media; 3602 3603 if (DC_IS_DAVICOM(sc) && 3604 IFM_SUBTYPE(ifm->ifm_media) == IFM_HPNA_1) 3605 dc_setcfg(sc, ifm->ifm_media); 3606 else 3607 sc->dc_link = 0; 3608 DC_UNLOCK(sc); 3609 3610 return (0); 3611 } 3612 3613 /* 3614 * Report current media status. 3615 */ 3616 static void 3617 dc_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 3618 { 3619 struct dc_softc *sc; 3620 struct mii_data *mii; 3621 struct ifmedia *ifm; 3622 3623 sc = ifp->if_softc; 3624 mii = device_get_softc(sc->dc_miibus); 3625 DC_LOCK(sc); 3626 mii_pollstat(mii); 3627 ifm = &mii->mii_media; 3628 if (DC_IS_DAVICOM(sc)) { 3629 if (IFM_SUBTYPE(ifm->ifm_media) == IFM_HPNA_1) { 3630 ifmr->ifm_active = ifm->ifm_media; 3631 ifmr->ifm_status = 0; 3632 return; 3633 } 3634 } 3635 ifmr->ifm_active = mii->mii_media_active; 3636 ifmr->ifm_status = mii->mii_media_status; 3637 DC_UNLOCK(sc); 3638 } 3639 3640 static int 3641 dc_ioctl(struct ifnet *ifp, u_long command, caddr_t data) 3642 { 3643 struct dc_softc *sc = ifp->if_softc; 3644 struct ifreq *ifr = (struct ifreq *)data; 3645 struct mii_data *mii; 3646 int error = 0; 3647 3648 switch (command) { 3649 case SIOCSIFFLAGS: 3650 DC_LOCK(sc); 3651 if (ifp->if_flags & IFF_UP) { 3652 int need_setfilt = (ifp->if_flags ^ sc->dc_if_flags) & 3653 (IFF_PROMISC | IFF_ALLMULTI); 3654 3655 if (ifp->if_drv_flags & IFF_DRV_RUNNING) { 3656 if (need_setfilt) 3657 dc_setfilt(sc); 3658 } else { 3659 sc->dc_txthresh = 0; 3660 dc_init_locked(sc); 3661 } 3662 } else { 3663 if (ifp->if_drv_flags & IFF_DRV_RUNNING) 3664 dc_stop(sc); 3665 } 3666 sc->dc_if_flags = ifp->if_flags; 3667 DC_UNLOCK(sc); 3668 error = 0; 3669 break; 3670 case SIOCADDMULTI: 3671 case SIOCDELMULTI: 3672 DC_LOCK(sc); 3673 dc_setfilt(sc); 3674 DC_UNLOCK(sc); 3675 error = 0; 3676 break; 3677 case SIOCGIFMEDIA: 3678 case SIOCSIFMEDIA: 3679 mii = device_get_softc(sc->dc_miibus); 3680 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 3681 #ifdef SRM_MEDIA 3682 DC_LOCK(sc); 3683 if (sc->dc_srm_media) 3684 sc->dc_srm_media = 0; 3685 DC_UNLOCK(sc); 3686 #endif 3687 break; 3688 case SIOCSIFCAP: 3689 DC_LOCK(sc); 3690 ifp->if_capenable &= ~IFCAP_POLLING; 3691 ifp->if_capenable |= ifr->ifr_reqcap & IFCAP_POLLING; 3692 DC_UNLOCK(sc); 3693 break; 3694 default: 3695 error = ether_ioctl(ifp, command, data); 3696 break; 3697 } 3698 3699 return (error); 3700 } 3701 3702 static void 3703 dc_watchdog(struct ifnet *ifp) 3704 { 3705 struct dc_softc *sc; 3706 3707 sc = ifp->if_softc; 3708 3709 DC_LOCK(sc); 3710 3711 ifp->if_oerrors++; 3712 if_printf(ifp, "watchdog timeout\n"); 3713 3714 dc_stop(sc); 3715 dc_reset(sc); 3716 dc_init_locked(sc); 3717 3718 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 3719 dc_start_locked(ifp); 3720 3721 DC_UNLOCK(sc); 3722 } 3723 3724 /* 3725 * Stop the adapter and free any mbufs allocated to the 3726 * RX and TX lists. 3727 */ 3728 static void 3729 dc_stop(struct dc_softc *sc) 3730 { 3731 struct ifnet *ifp; 3732 struct dc_list_data *ld; 3733 struct dc_chain_data *cd; 3734 int i; 3735 u_int32_t ctl; 3736 3737 DC_LOCK_ASSERT(sc); 3738 3739 ifp = sc->dc_ifp; 3740 ifp->if_timer = 0; 3741 ld = sc->dc_ldata; 3742 cd = &sc->dc_cdata; 3743 3744 callout_stop(&sc->dc_stat_ch); 3745 3746 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE); 3747 #ifdef DEVICE_POLLING 3748 ether_poll_deregister(ifp); 3749 #endif 3750 3751 DC_CLRBIT(sc, DC_NETCFG, (DC_NETCFG_RX_ON | DC_NETCFG_TX_ON)); 3752 CSR_WRITE_4(sc, DC_IMR, 0x00000000); 3753 CSR_WRITE_4(sc, DC_TXADDR, 0x00000000); 3754 CSR_WRITE_4(sc, DC_RXADDR, 0x00000000); 3755 sc->dc_link = 0; 3756 3757 /* 3758 * Free data in the RX lists. 3759 */ 3760 for (i = 0; i < DC_RX_LIST_CNT; i++) { 3761 if (cd->dc_rx_chain[i] != NULL) { 3762 m_freem(cd->dc_rx_chain[i]); 3763 cd->dc_rx_chain[i] = NULL; 3764 } 3765 } 3766 bzero(&ld->dc_rx_list, sizeof(ld->dc_rx_list)); 3767 3768 /* 3769 * Free the TX list buffers. 3770 */ 3771 for (i = 0; i < DC_TX_LIST_CNT; i++) { 3772 if (cd->dc_tx_chain[i] != NULL) { 3773 ctl = le32toh(ld->dc_tx_list[i].dc_ctl); 3774 if ((ctl & DC_TXCTL_SETUP) || 3775 !(ctl & DC_TXCTL_LASTFRAG)) { 3776 cd->dc_tx_chain[i] = NULL; 3777 continue; 3778 } 3779 bus_dmamap_unload(sc->dc_mtag, cd->dc_tx_map[i]); 3780 m_freem(cd->dc_tx_chain[i]); 3781 cd->dc_tx_chain[i] = NULL; 3782 } 3783 } 3784 bzero(&ld->dc_tx_list, sizeof(ld->dc_tx_list)); 3785 } 3786 3787 /* 3788 * Device suspend routine. Stop the interface and save some PCI 3789 * settings in case the BIOS doesn't restore them properly on 3790 * resume. 3791 */ 3792 static int 3793 dc_suspend(device_t dev) 3794 { 3795 struct dc_softc *sc; 3796 3797 sc = device_get_softc(dev); 3798 DC_LOCK(sc); 3799 dc_stop(sc); 3800 sc->suspended = 1; 3801 DC_UNLOCK(sc); 3802 3803 return (0); 3804 } 3805 3806 /* 3807 * Device resume routine. Restore some PCI settings in case the BIOS 3808 * doesn't, re-enable busmastering, and restart the interface if 3809 * appropriate. 3810 */ 3811 static int 3812 dc_resume(device_t dev) 3813 { 3814 struct dc_softc *sc; 3815 struct ifnet *ifp; 3816 3817 sc = device_get_softc(dev); 3818 ifp = sc->dc_ifp; 3819 3820 /* reinitialize interface if necessary */ 3821 DC_LOCK(sc); 3822 if (ifp->if_flags & IFF_UP) 3823 dc_init_locked(sc); 3824 3825 sc->suspended = 0; 3826 DC_UNLOCK(sc); 3827 3828 return (0); 3829 } 3830 3831 /* 3832 * Stop all chip I/O so that the kernel's probe routines don't 3833 * get confused by errant DMAs when rebooting. 3834 */ 3835 static void 3836 dc_shutdown(device_t dev) 3837 { 3838 struct dc_softc *sc; 3839 3840 sc = device_get_softc(dev); 3841 3842 DC_LOCK(sc); 3843 dc_stop(sc); 3844 DC_UNLOCK(sc); 3845 } 3846