1 /* 2 * Copyright (c) 1997, 1998, 1999 3 * Bill Paul <wpaul@ee.columbia.edu>. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 3. All advertising materials mentioning features or use of this software 14 * must display the following acknowledgement: 15 * This product includes software developed by Bill Paul. 16 * 4. Neither the name of the author nor the names of any co-contributors 17 * may be used to endorse or promote products derived from this software 18 * without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30 * THE POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33 #include <sys/cdefs.h> 34 __FBSDID("$FreeBSD$"); 35 36 /* 37 * DEC "tulip" clone ethernet driver. Supports the DEC/Intel 21143 38 * series chips and several workalikes including the following: 39 * 40 * Macronix 98713/98715/98725/98727/98732 PMAC (www.macronix.com) 41 * Macronix/Lite-On 82c115 PNIC II (www.macronix.com) 42 * Lite-On 82c168/82c169 PNIC (www.litecom.com) 43 * ASIX Electronics AX88140A (www.asix.com.tw) 44 * ASIX Electronics AX88141 (www.asix.com.tw) 45 * ADMtek AL981 (www.admtek.com.tw) 46 * ADMtek AN985 (www.admtek.com.tw) 47 * Netgear FA511 (www.netgear.com) Appears to be rebadged ADMTek AN985 48 * Davicom DM9100, DM9102, DM9102A (www.davicom8.com) 49 * Accton EN1217 (www.accton.com) 50 * Xircom X3201 (www.xircom.com) 51 * Abocom FE2500 52 * Conexant LANfinity (www.conexant.com) 53 * 3Com OfficeConnect 10/100B 3CSOHO100B (www.3com.com) 54 * 55 * Datasheets for the 21143 are available at developer.intel.com. 56 * Datasheets for the clone parts can be found at their respective sites. 57 * (Except for the PNIC; see www.freebsd.org/~wpaul/PNIC/pnic.ps.gz.) 58 * The PNIC II is essentially a Macronix 98715A chip; the only difference 59 * worth noting is that its multicast hash table is only 128 bits wide 60 * instead of 512. 61 * 62 * Written by Bill Paul <wpaul@ee.columbia.edu> 63 * Electrical Engineering Department 64 * Columbia University, New York City 65 */ 66 /* 67 * The Intel 21143 is the successor to the DEC 21140. It is basically 68 * the same as the 21140 but with a few new features. The 21143 supports 69 * three kinds of media attachments: 70 * 71 * o MII port, for 10Mbps and 100Mbps support and NWAY 72 * autonegotiation provided by an external PHY. 73 * o SYM port, for symbol mode 100Mbps support. 74 * o 10baseT port. 75 * o AUI/BNC port. 76 * 77 * The 100Mbps SYM port and 10baseT port can be used together in 78 * combination with the internal NWAY support to create a 10/100 79 * autosensing configuration. 80 * 81 * Note that not all tulip workalikes are handled in this driver: we only 82 * deal with those which are relatively well behaved. The Winbond is 83 * handled separately due to its different register offsets and the 84 * special handling needed for its various bugs. The PNIC is handled 85 * here, but I'm not thrilled about it. 86 * 87 * All of the workalike chips use some form of MII transceiver support 88 * with the exception of the Macronix chips, which also have a SYM port. 89 * The ASIX AX88140A is also documented to have a SYM port, but all 90 * the cards I've seen use an MII transceiver, probably because the 91 * AX88140A doesn't support internal NWAY. 92 */ 93 94 #include <sys/param.h> 95 #include <sys/endian.h> 96 #include <sys/systm.h> 97 #include <sys/sockio.h> 98 #include <sys/mbuf.h> 99 #include <sys/malloc.h> 100 #include <sys/kernel.h> 101 #include <sys/socket.h> 102 #include <sys/sysctl.h> 103 104 #include <net/if.h> 105 #include <net/if_arp.h> 106 #include <net/ethernet.h> 107 #include <net/if_dl.h> 108 #include <net/if_media.h> 109 #include <net/if_types.h> 110 #include <net/if_vlan_var.h> 111 112 #include <net/bpf.h> 113 114 #include <machine/bus_pio.h> 115 #include <machine/bus_memio.h> 116 #include <machine/bus.h> 117 #include <machine/resource.h> 118 #include <sys/bus.h> 119 #include <sys/rman.h> 120 121 #include <dev/mii/mii.h> 122 #include <dev/mii/miivar.h> 123 124 #include <dev/pci/pcireg.h> 125 #include <dev/pci/pcivar.h> 126 127 #define DC_USEIOSPACE 128 #ifdef __alpha__ 129 #define SRM_MEDIA 130 #endif 131 132 #include <pci/if_dcreg.h> 133 134 MODULE_DEPEND(dc, pci, 1, 1, 1); 135 MODULE_DEPEND(dc, ether, 1, 1, 1); 136 MODULE_DEPEND(dc, miibus, 1, 1, 1); 137 138 /* "controller miibus0" required. See GENERIC if you get errors here. */ 139 #include "miibus_if.h" 140 141 /* 142 * Various supported device vendors/types and their names. 143 */ 144 static struct dc_type dc_devs[] = { 145 { DC_VENDORID_DEC, DC_DEVICEID_21143, 146 "Intel 21143 10/100BaseTX" }, 147 { DC_VENDORID_DAVICOM, DC_DEVICEID_DM9009, 148 "Davicom DM9009 10/100BaseTX" }, 149 { DC_VENDORID_DAVICOM, DC_DEVICEID_DM9100, 150 "Davicom DM9100 10/100BaseTX" }, 151 { DC_VENDORID_DAVICOM, DC_DEVICEID_DM9102, 152 "Davicom DM9102 10/100BaseTX" }, 153 { DC_VENDORID_DAVICOM, DC_DEVICEID_DM9102, 154 "Davicom DM9102A 10/100BaseTX" }, 155 { DC_VENDORID_ADMTEK, DC_DEVICEID_AL981, 156 "ADMtek AL981 10/100BaseTX" }, 157 { DC_VENDORID_ADMTEK, DC_DEVICEID_AN985, 158 "ADMtek AN985 10/100BaseTX" }, 159 { DC_VENDORID_ADMTEK, DC_DEVICEID_ADM9511, 160 "ADMtek ADM9511 10/100BaseTX" }, 161 { DC_VENDORID_ADMTEK, DC_DEVICEID_ADM9513, 162 "ADMtek ADM9513 10/100BaseTX" }, 163 { DC_VENDORID_ADMTEK, DC_DEVICEID_FA511, 164 "Netgear FA511 10/100BaseTX" }, 165 { DC_VENDORID_ASIX, DC_DEVICEID_AX88140A, 166 "ASIX AX88140A 10/100BaseTX" }, 167 { DC_VENDORID_ASIX, DC_DEVICEID_AX88140A, 168 "ASIX AX88141 10/100BaseTX" }, 169 { DC_VENDORID_MX, DC_DEVICEID_98713, 170 "Macronix 98713 10/100BaseTX" }, 171 { DC_VENDORID_MX, DC_DEVICEID_98713, 172 "Macronix 98713A 10/100BaseTX" }, 173 { DC_VENDORID_CP, DC_DEVICEID_98713_CP, 174 "Compex RL100-TX 10/100BaseTX" }, 175 { DC_VENDORID_CP, DC_DEVICEID_98713_CP, 176 "Compex RL100-TX 10/100BaseTX" }, 177 { DC_VENDORID_MX, DC_DEVICEID_987x5, 178 "Macronix 98715/98715A 10/100BaseTX" }, 179 { DC_VENDORID_MX, DC_DEVICEID_987x5, 180 "Macronix 98715AEC-C 10/100BaseTX" }, 181 { DC_VENDORID_MX, DC_DEVICEID_987x5, 182 "Macronix 98725 10/100BaseTX" }, 183 { DC_VENDORID_MX, DC_DEVICEID_98727, 184 "Macronix 98727/98732 10/100BaseTX" }, 185 { DC_VENDORID_LO, DC_DEVICEID_82C115, 186 "LC82C115 PNIC II 10/100BaseTX" }, 187 { DC_VENDORID_LO, DC_DEVICEID_82C168, 188 "82c168 PNIC 10/100BaseTX" }, 189 { DC_VENDORID_LO, DC_DEVICEID_82C168, 190 "82c169 PNIC 10/100BaseTX" }, 191 { DC_VENDORID_ACCTON, DC_DEVICEID_EN1217, 192 "Accton EN1217 10/100BaseTX" }, 193 { DC_VENDORID_ACCTON, DC_DEVICEID_EN2242, 194 "Accton EN2242 MiniPCI 10/100BaseTX" }, 195 { DC_VENDORID_XIRCOM, DC_DEVICEID_X3201, 196 "Xircom X3201 10/100BaseTX" }, 197 { DC_VENDORID_ABOCOM, DC_DEVICEID_FE2500, 198 "Abocom FE2500 10/100BaseTX" }, 199 { DC_VENDORID_CONEXANT, DC_DEVICEID_RS7112, 200 "Conexant LANfinity MiniPCI 10/100BaseTX" }, 201 { DC_VENDORID_HAWKING, DC_DEVICEID_HAWKING_PN672TX, 202 "Hawking CB102 CardBus 10/100" }, 203 { DC_VENDORID_PLANEX, DC_DEVICEID_FNW3602T, 204 "PlaneX FNW-3602-T CardBus 10/100" }, 205 { DC_VENDORID_3COM, DC_DEVICEID_3CSOHOB, 206 "3Com OfficeConnect 10/100B" }, 207 { DC_VENDORID_MICROSOFT, DC_DEVICEID_MSMN120, 208 "Microsoft MN-120 CardBus 10/100" }, 209 { DC_VENDORID_MICROSOFT, DC_DEVICEID_MSMN130, 210 "Microsoft MN-130 10/100" }, 211 { DC_VENDORID_MICROSOFT, DC_DEVICEID_MSMN130_FAKE, 212 "Microsoft MN-130 10/100" }, 213 { 0, 0, NULL } 214 }; 215 216 static int dc_probe (device_t); 217 static int dc_attach (device_t); 218 static int dc_detach (device_t); 219 static int dc_suspend (device_t); 220 static int dc_resume (device_t); 221 #ifndef BURN_BRIDGES 222 static void dc_acpi (device_t); 223 #endif 224 static struct dc_type *dc_devtype (device_t); 225 static int dc_newbuf (struct dc_softc *, int, int); 226 static int dc_encap (struct dc_softc *, struct mbuf **); 227 static void dc_pnic_rx_bug_war (struct dc_softc *, int); 228 static int dc_rx_resync (struct dc_softc *); 229 static void dc_rxeof (struct dc_softc *); 230 static void dc_txeof (struct dc_softc *); 231 static void dc_tick (void *); 232 static void dc_tx_underrun (struct dc_softc *); 233 static void dc_intr (void *); 234 static void dc_start (struct ifnet *); 235 static int dc_ioctl (struct ifnet *, u_long, caddr_t); 236 static void dc_init (void *); 237 static void dc_stop (struct dc_softc *); 238 static void dc_watchdog (struct ifnet *); 239 static void dc_shutdown (device_t); 240 static int dc_ifmedia_upd (struct ifnet *); 241 static void dc_ifmedia_sts (struct ifnet *, struct ifmediareq *); 242 243 static void dc_delay (struct dc_softc *); 244 static void dc_eeprom_idle (struct dc_softc *); 245 static void dc_eeprom_putbyte (struct dc_softc *, int); 246 static void dc_eeprom_getword (struct dc_softc *, int, u_int16_t *); 247 static void dc_eeprom_getword_pnic 248 (struct dc_softc *, int, u_int16_t *); 249 static void dc_eeprom_getword_xircom 250 (struct dc_softc *, int, u_int16_t *); 251 static void dc_eeprom_width (struct dc_softc *); 252 static void dc_read_eeprom (struct dc_softc *, caddr_t, int, int, int); 253 254 static void dc_mii_writebit (struct dc_softc *, int); 255 static int dc_mii_readbit (struct dc_softc *); 256 static void dc_mii_sync (struct dc_softc *); 257 static void dc_mii_send (struct dc_softc *, u_int32_t, int); 258 static int dc_mii_readreg (struct dc_softc *, struct dc_mii_frame *); 259 static int dc_mii_writereg (struct dc_softc *, struct dc_mii_frame *); 260 static int dc_miibus_readreg (device_t, int, int); 261 static int dc_miibus_writereg (device_t, int, int, int); 262 static void dc_miibus_statchg (device_t); 263 static void dc_miibus_mediainit (device_t); 264 265 static void dc_setcfg (struct dc_softc *, int); 266 static uint32_t dc_mchash_le (struct dc_softc *, const uint8_t *); 267 static uint32_t dc_mchash_be (const uint8_t *); 268 static void dc_setfilt_21143 (struct dc_softc *); 269 static void dc_setfilt_asix (struct dc_softc *); 270 static void dc_setfilt_admtek (struct dc_softc *); 271 static void dc_setfilt_xircom (struct dc_softc *); 272 273 static void dc_setfilt (struct dc_softc *); 274 275 static void dc_reset (struct dc_softc *); 276 static int dc_list_rx_init (struct dc_softc *); 277 static int dc_list_tx_init (struct dc_softc *); 278 279 static void dc_read_srom (struct dc_softc *, int); 280 static void dc_parse_21143_srom (struct dc_softc *); 281 static void dc_decode_leaf_sia (struct dc_softc *, struct dc_eblock_sia *); 282 static void dc_decode_leaf_mii (struct dc_softc *, struct dc_eblock_mii *); 283 static void dc_decode_leaf_sym (struct dc_softc *, struct dc_eblock_sym *); 284 static void dc_apply_fixup (struct dc_softc *, int); 285 286 static void dc_dma_map_txbuf (void *, bus_dma_segment_t *, int, bus_size_t, 287 int); 288 static void dc_dma_map_rxbuf (void *, bus_dma_segment_t *, int, bus_size_t, 289 int); 290 291 #ifdef DC_USEIOSPACE 292 #define DC_RES SYS_RES_IOPORT 293 #define DC_RID DC_PCI_CFBIO 294 #else 295 #define DC_RES SYS_RES_MEMORY 296 #define DC_RID DC_PCI_CFBMA 297 #endif 298 299 static device_method_t dc_methods[] = { 300 /* Device interface */ 301 DEVMETHOD(device_probe, dc_probe), 302 DEVMETHOD(device_attach, dc_attach), 303 DEVMETHOD(device_detach, dc_detach), 304 DEVMETHOD(device_suspend, dc_suspend), 305 DEVMETHOD(device_resume, dc_resume), 306 DEVMETHOD(device_shutdown, dc_shutdown), 307 308 /* bus interface */ 309 DEVMETHOD(bus_print_child, bus_generic_print_child), 310 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 311 312 /* MII interface */ 313 DEVMETHOD(miibus_readreg, dc_miibus_readreg), 314 DEVMETHOD(miibus_writereg, dc_miibus_writereg), 315 DEVMETHOD(miibus_statchg, dc_miibus_statchg), 316 DEVMETHOD(miibus_mediainit, dc_miibus_mediainit), 317 318 { 0, 0 } 319 }; 320 321 static driver_t dc_driver = { 322 "dc", 323 dc_methods, 324 sizeof(struct dc_softc) 325 }; 326 327 static devclass_t dc_devclass; 328 #ifdef __i386__ 329 static int dc_quick = 1; 330 SYSCTL_INT(_hw, OID_AUTO, dc_quick, CTLFLAG_RW, &dc_quick, 0, 331 "do not m_devget() in dc driver"); 332 #endif 333 334 DRIVER_MODULE(dc, pci, dc_driver, dc_devclass, 0, 0); 335 DRIVER_MODULE(miibus, dc, miibus_driver, miibus_devclass, 0, 0); 336 337 #define DC_SETBIT(sc, reg, x) \ 338 CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) | (x)) 339 340 #define DC_CLRBIT(sc, reg, x) \ 341 CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) & ~(x)) 342 343 #define SIO_SET(x) DC_SETBIT(sc, DC_SIO, (x)) 344 #define SIO_CLR(x) DC_CLRBIT(sc, DC_SIO, (x)) 345 346 #define IS_MPSAFE 0 347 348 static void 349 dc_delay(struct dc_softc *sc) 350 { 351 int idx; 352 353 for (idx = (300 / 33) + 1; idx > 0; idx--) 354 CSR_READ_4(sc, DC_BUSCTL); 355 } 356 357 static void 358 dc_eeprom_width(struct dc_softc *sc) 359 { 360 int i; 361 362 /* Force EEPROM to idle state. */ 363 dc_eeprom_idle(sc); 364 365 /* Enter EEPROM access mode. */ 366 CSR_WRITE_4(sc, DC_SIO, DC_SIO_EESEL); 367 dc_delay(sc); 368 DC_SETBIT(sc, DC_SIO, DC_SIO_ROMCTL_READ); 369 dc_delay(sc); 370 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); 371 dc_delay(sc); 372 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CS); 373 dc_delay(sc); 374 375 for (i = 3; i--;) { 376 if (6 & (1 << i)) 377 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_DATAIN); 378 else 379 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_DATAIN); 380 dc_delay(sc); 381 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CLK); 382 dc_delay(sc); 383 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); 384 dc_delay(sc); 385 } 386 387 for (i = 1; i <= 12; i++) { 388 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CLK); 389 dc_delay(sc); 390 if (!(CSR_READ_4(sc, DC_SIO) & DC_SIO_EE_DATAOUT)) { 391 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); 392 dc_delay(sc); 393 break; 394 } 395 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); 396 dc_delay(sc); 397 } 398 399 /* Turn off EEPROM access mode. */ 400 dc_eeprom_idle(sc); 401 402 if (i < 4 || i > 12) 403 sc->dc_romwidth = 6; 404 else 405 sc->dc_romwidth = i; 406 407 /* Enter EEPROM access mode. */ 408 CSR_WRITE_4(sc, DC_SIO, DC_SIO_EESEL); 409 dc_delay(sc); 410 DC_SETBIT(sc, DC_SIO, DC_SIO_ROMCTL_READ); 411 dc_delay(sc); 412 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); 413 dc_delay(sc); 414 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CS); 415 dc_delay(sc); 416 417 /* Turn off EEPROM access mode. */ 418 dc_eeprom_idle(sc); 419 } 420 421 static void 422 dc_eeprom_idle(struct dc_softc *sc) 423 { 424 int i; 425 426 CSR_WRITE_4(sc, DC_SIO, DC_SIO_EESEL); 427 dc_delay(sc); 428 DC_SETBIT(sc, DC_SIO, DC_SIO_ROMCTL_READ); 429 dc_delay(sc); 430 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); 431 dc_delay(sc); 432 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CS); 433 dc_delay(sc); 434 435 for (i = 0; i < 25; i++) { 436 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); 437 dc_delay(sc); 438 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CLK); 439 dc_delay(sc); 440 } 441 442 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); 443 dc_delay(sc); 444 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CS); 445 dc_delay(sc); 446 CSR_WRITE_4(sc, DC_SIO, 0x00000000); 447 } 448 449 /* 450 * Send a read command and address to the EEPROM, check for ACK. 451 */ 452 static void 453 dc_eeprom_putbyte(struct dc_softc *sc, int addr) 454 { 455 int d, i; 456 457 d = DC_EECMD_READ >> 6; 458 for (i = 3; i--; ) { 459 if (d & (1 << i)) 460 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_DATAIN); 461 else 462 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_DATAIN); 463 dc_delay(sc); 464 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CLK); 465 dc_delay(sc); 466 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); 467 dc_delay(sc); 468 } 469 470 /* 471 * Feed in each bit and strobe the clock. 472 */ 473 for (i = sc->dc_romwidth; i--;) { 474 if (addr & (1 << i)) { 475 SIO_SET(DC_SIO_EE_DATAIN); 476 } else { 477 SIO_CLR(DC_SIO_EE_DATAIN); 478 } 479 dc_delay(sc); 480 SIO_SET(DC_SIO_EE_CLK); 481 dc_delay(sc); 482 SIO_CLR(DC_SIO_EE_CLK); 483 dc_delay(sc); 484 } 485 } 486 487 /* 488 * Read a word of data stored in the EEPROM at address 'addr.' 489 * The PNIC 82c168/82c169 has its own non-standard way to read 490 * the EEPROM. 491 */ 492 static void 493 dc_eeprom_getword_pnic(struct dc_softc *sc, int addr, u_int16_t *dest) 494 { 495 int i; 496 u_int32_t r; 497 498 CSR_WRITE_4(sc, DC_PN_SIOCTL, DC_PN_EEOPCODE_READ | addr); 499 500 for (i = 0; i < DC_TIMEOUT; i++) { 501 DELAY(1); 502 r = CSR_READ_4(sc, DC_SIO); 503 if (!(r & DC_PN_SIOCTL_BUSY)) { 504 *dest = (u_int16_t)(r & 0xFFFF); 505 return; 506 } 507 } 508 } 509 510 /* 511 * Read a word of data stored in the EEPROM at address 'addr.' 512 * The Xircom X3201 has its own non-standard way to read 513 * the EEPROM, too. 514 */ 515 static void 516 dc_eeprom_getword_xircom(struct dc_softc *sc, int addr, u_int16_t *dest) 517 { 518 519 SIO_SET(DC_SIO_ROMSEL | DC_SIO_ROMCTL_READ); 520 521 addr *= 2; 522 CSR_WRITE_4(sc, DC_ROM, addr | 0x160); 523 *dest = (u_int16_t)CSR_READ_4(sc, DC_SIO) & 0xff; 524 addr += 1; 525 CSR_WRITE_4(sc, DC_ROM, addr | 0x160); 526 *dest |= ((u_int16_t)CSR_READ_4(sc, DC_SIO) & 0xff) << 8; 527 528 SIO_CLR(DC_SIO_ROMSEL | DC_SIO_ROMCTL_READ); 529 } 530 531 /* 532 * Read a word of data stored in the EEPROM at address 'addr.' 533 */ 534 static void 535 dc_eeprom_getword(struct dc_softc *sc, int addr, u_int16_t *dest) 536 { 537 int i; 538 u_int16_t word = 0; 539 540 /* Force EEPROM to idle state. */ 541 dc_eeprom_idle(sc); 542 543 /* Enter EEPROM access mode. */ 544 CSR_WRITE_4(sc, DC_SIO, DC_SIO_EESEL); 545 dc_delay(sc); 546 DC_SETBIT(sc, DC_SIO, DC_SIO_ROMCTL_READ); 547 dc_delay(sc); 548 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); 549 dc_delay(sc); 550 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CS); 551 dc_delay(sc); 552 553 /* 554 * Send address of word we want to read. 555 */ 556 dc_eeprom_putbyte(sc, addr); 557 558 /* 559 * Start reading bits from EEPROM. 560 */ 561 for (i = 0x8000; i; i >>= 1) { 562 SIO_SET(DC_SIO_EE_CLK); 563 dc_delay(sc); 564 if (CSR_READ_4(sc, DC_SIO) & DC_SIO_EE_DATAOUT) 565 word |= i; 566 dc_delay(sc); 567 SIO_CLR(DC_SIO_EE_CLK); 568 dc_delay(sc); 569 } 570 571 /* Turn off EEPROM access mode. */ 572 dc_eeprom_idle(sc); 573 574 *dest = word; 575 } 576 577 /* 578 * Read a sequence of words from the EEPROM. 579 */ 580 static void 581 dc_read_eeprom(struct dc_softc *sc, caddr_t dest, int off, int cnt, int swap) 582 { 583 int i; 584 u_int16_t word = 0, *ptr; 585 586 for (i = 0; i < cnt; i++) { 587 if (DC_IS_PNIC(sc)) 588 dc_eeprom_getword_pnic(sc, off + i, &word); 589 else if (DC_IS_XIRCOM(sc)) 590 dc_eeprom_getword_xircom(sc, off + i, &word); 591 else 592 dc_eeprom_getword(sc, off + i, &word); 593 ptr = (u_int16_t *)(dest + (i * 2)); 594 if (swap) 595 *ptr = ntohs(word); 596 else 597 *ptr = word; 598 } 599 } 600 601 /* 602 * The following two routines are taken from the Macronix 98713 603 * Application Notes pp.19-21. 604 */ 605 /* 606 * Write a bit to the MII bus. 607 */ 608 static void 609 dc_mii_writebit(struct dc_softc *sc, int bit) 610 { 611 612 if (bit) 613 CSR_WRITE_4(sc, DC_SIO, 614 DC_SIO_ROMCTL_WRITE | DC_SIO_MII_DATAOUT); 615 else 616 CSR_WRITE_4(sc, DC_SIO, DC_SIO_ROMCTL_WRITE); 617 618 DC_SETBIT(sc, DC_SIO, DC_SIO_MII_CLK); 619 DC_CLRBIT(sc, DC_SIO, DC_SIO_MII_CLK); 620 } 621 622 /* 623 * Read a bit from the MII bus. 624 */ 625 static int 626 dc_mii_readbit(struct dc_softc *sc) 627 { 628 629 CSR_WRITE_4(sc, DC_SIO, DC_SIO_ROMCTL_READ | DC_SIO_MII_DIR); 630 CSR_READ_4(sc, DC_SIO); 631 DC_SETBIT(sc, DC_SIO, DC_SIO_MII_CLK); 632 DC_CLRBIT(sc, DC_SIO, DC_SIO_MII_CLK); 633 if (CSR_READ_4(sc, DC_SIO) & DC_SIO_MII_DATAIN) 634 return (1); 635 636 return (0); 637 } 638 639 /* 640 * Sync the PHYs by setting data bit and strobing the clock 32 times. 641 */ 642 static void 643 dc_mii_sync(struct dc_softc *sc) 644 { 645 int i; 646 647 CSR_WRITE_4(sc, DC_SIO, DC_SIO_ROMCTL_WRITE); 648 649 for (i = 0; i < 32; i++) 650 dc_mii_writebit(sc, 1); 651 } 652 653 /* 654 * Clock a series of bits through the MII. 655 */ 656 static void 657 dc_mii_send(struct dc_softc *sc, u_int32_t bits, int cnt) 658 { 659 int i; 660 661 for (i = (0x1 << (cnt - 1)); i; i >>= 1) 662 dc_mii_writebit(sc, bits & i); 663 } 664 665 /* 666 * Read an PHY register through the MII. 667 */ 668 static int 669 dc_mii_readreg(struct dc_softc *sc, struct dc_mii_frame *frame) 670 { 671 int i, ack; 672 673 DC_LOCK(sc); 674 675 /* 676 * Set up frame for RX. 677 */ 678 frame->mii_stdelim = DC_MII_STARTDELIM; 679 frame->mii_opcode = DC_MII_READOP; 680 frame->mii_turnaround = 0; 681 frame->mii_data = 0; 682 683 /* 684 * Sync the PHYs. 685 */ 686 dc_mii_sync(sc); 687 688 /* 689 * Send command/address info. 690 */ 691 dc_mii_send(sc, frame->mii_stdelim, 2); 692 dc_mii_send(sc, frame->mii_opcode, 2); 693 dc_mii_send(sc, frame->mii_phyaddr, 5); 694 dc_mii_send(sc, frame->mii_regaddr, 5); 695 696 #ifdef notdef 697 /* Idle bit */ 698 dc_mii_writebit(sc, 1); 699 dc_mii_writebit(sc, 0); 700 #endif 701 702 /* Check for ack. */ 703 ack = dc_mii_readbit(sc); 704 705 /* 706 * Now try reading data bits. If the ack failed, we still 707 * need to clock through 16 cycles to keep the PHY(s) in sync. 708 */ 709 if (ack) { 710 for (i = 0; i < 16; i++) 711 dc_mii_readbit(sc); 712 goto fail; 713 } 714 715 for (i = 0x8000; i; i >>= 1) { 716 if (!ack) { 717 if (dc_mii_readbit(sc)) 718 frame->mii_data |= i; 719 } 720 } 721 722 fail: 723 724 dc_mii_writebit(sc, 0); 725 dc_mii_writebit(sc, 0); 726 727 DC_UNLOCK(sc); 728 729 if (ack) 730 return (1); 731 return (0); 732 } 733 734 /* 735 * Write to a PHY register through the MII. 736 */ 737 static int 738 dc_mii_writereg(struct dc_softc *sc, struct dc_mii_frame *frame) 739 { 740 741 DC_LOCK(sc); 742 /* 743 * Set up frame for TX. 744 */ 745 746 frame->mii_stdelim = DC_MII_STARTDELIM; 747 frame->mii_opcode = DC_MII_WRITEOP; 748 frame->mii_turnaround = DC_MII_TURNAROUND; 749 750 /* 751 * Sync the PHYs. 752 */ 753 dc_mii_sync(sc); 754 755 dc_mii_send(sc, frame->mii_stdelim, 2); 756 dc_mii_send(sc, frame->mii_opcode, 2); 757 dc_mii_send(sc, frame->mii_phyaddr, 5); 758 dc_mii_send(sc, frame->mii_regaddr, 5); 759 dc_mii_send(sc, frame->mii_turnaround, 2); 760 dc_mii_send(sc, frame->mii_data, 16); 761 762 /* Idle bit. */ 763 dc_mii_writebit(sc, 0); 764 dc_mii_writebit(sc, 0); 765 766 DC_UNLOCK(sc); 767 768 return (0); 769 } 770 771 static int 772 dc_miibus_readreg(device_t dev, int phy, int reg) 773 { 774 struct dc_mii_frame frame; 775 struct dc_softc *sc; 776 int i, rval, phy_reg = 0; 777 778 sc = device_get_softc(dev); 779 bzero(&frame, sizeof(frame)); 780 781 /* 782 * Note: both the AL981 and AN985 have internal PHYs, 783 * however the AL981 provides direct access to the PHY 784 * registers while the AN985 uses a serial MII interface. 785 * The AN985's MII interface is also buggy in that you 786 * can read from any MII address (0 to 31), but only address 1 787 * behaves normally. To deal with both cases, we pretend 788 * that the PHY is at MII address 1. 789 */ 790 if (DC_IS_ADMTEK(sc) && phy != DC_ADMTEK_PHYADDR) 791 return (0); 792 793 /* 794 * Note: the ukphy probes of the RS7112 report a PHY at 795 * MII address 0 (possibly HomePNA?) and 1 (ethernet) 796 * so we only respond to correct one. 797 */ 798 if (DC_IS_CONEXANT(sc) && phy != DC_CONEXANT_PHYADDR) 799 return (0); 800 801 if (sc->dc_pmode != DC_PMODE_MII) { 802 if (phy == (MII_NPHY - 1)) { 803 switch (reg) { 804 case MII_BMSR: 805 /* 806 * Fake something to make the probe 807 * code think there's a PHY here. 808 */ 809 return (BMSR_MEDIAMASK); 810 break; 811 case MII_PHYIDR1: 812 if (DC_IS_PNIC(sc)) 813 return (DC_VENDORID_LO); 814 return (DC_VENDORID_DEC); 815 break; 816 case MII_PHYIDR2: 817 if (DC_IS_PNIC(sc)) 818 return (DC_DEVICEID_82C168); 819 return (DC_DEVICEID_21143); 820 break; 821 default: 822 return (0); 823 break; 824 } 825 } else 826 return (0); 827 } 828 829 if (DC_IS_PNIC(sc)) { 830 CSR_WRITE_4(sc, DC_PN_MII, DC_PN_MIIOPCODE_READ | 831 (phy << 23) | (reg << 18)); 832 for (i = 0; i < DC_TIMEOUT; i++) { 833 DELAY(1); 834 rval = CSR_READ_4(sc, DC_PN_MII); 835 if (!(rval & DC_PN_MII_BUSY)) { 836 rval &= 0xFFFF; 837 return (rval == 0xFFFF ? 0 : rval); 838 } 839 } 840 return (0); 841 } 842 843 if (DC_IS_COMET(sc)) { 844 switch (reg) { 845 case MII_BMCR: 846 phy_reg = DC_AL_BMCR; 847 break; 848 case MII_BMSR: 849 phy_reg = DC_AL_BMSR; 850 break; 851 case MII_PHYIDR1: 852 phy_reg = DC_AL_VENID; 853 break; 854 case MII_PHYIDR2: 855 phy_reg = DC_AL_DEVID; 856 break; 857 case MII_ANAR: 858 phy_reg = DC_AL_ANAR; 859 break; 860 case MII_ANLPAR: 861 phy_reg = DC_AL_LPAR; 862 break; 863 case MII_ANER: 864 phy_reg = DC_AL_ANER; 865 break; 866 default: 867 printf("dc%d: phy_read: bad phy register %x\n", 868 sc->dc_unit, reg); 869 return (0); 870 break; 871 } 872 873 rval = CSR_READ_4(sc, phy_reg) & 0x0000FFFF; 874 875 if (rval == 0xFFFF) 876 return (0); 877 return (rval); 878 } 879 880 frame.mii_phyaddr = phy; 881 frame.mii_regaddr = reg; 882 if (sc->dc_type == DC_TYPE_98713) { 883 phy_reg = CSR_READ_4(sc, DC_NETCFG); 884 CSR_WRITE_4(sc, DC_NETCFG, phy_reg & ~DC_NETCFG_PORTSEL); 885 } 886 dc_mii_readreg(sc, &frame); 887 if (sc->dc_type == DC_TYPE_98713) 888 CSR_WRITE_4(sc, DC_NETCFG, phy_reg); 889 890 return (frame.mii_data); 891 } 892 893 static int 894 dc_miibus_writereg(device_t dev, int phy, int reg, int data) 895 { 896 struct dc_softc *sc; 897 struct dc_mii_frame frame; 898 int i, phy_reg = 0; 899 900 sc = device_get_softc(dev); 901 bzero(&frame, sizeof(frame)); 902 903 if (DC_IS_ADMTEK(sc) && phy != DC_ADMTEK_PHYADDR) 904 return (0); 905 906 if (DC_IS_CONEXANT(sc) && phy != DC_CONEXANT_PHYADDR) 907 return (0); 908 909 if (DC_IS_PNIC(sc)) { 910 CSR_WRITE_4(sc, DC_PN_MII, DC_PN_MIIOPCODE_WRITE | 911 (phy << 23) | (reg << 10) | data); 912 for (i = 0; i < DC_TIMEOUT; i++) { 913 if (!(CSR_READ_4(sc, DC_PN_MII) & DC_PN_MII_BUSY)) 914 break; 915 } 916 return (0); 917 } 918 919 if (DC_IS_COMET(sc)) { 920 switch (reg) { 921 case MII_BMCR: 922 phy_reg = DC_AL_BMCR; 923 break; 924 case MII_BMSR: 925 phy_reg = DC_AL_BMSR; 926 break; 927 case MII_PHYIDR1: 928 phy_reg = DC_AL_VENID; 929 break; 930 case MII_PHYIDR2: 931 phy_reg = DC_AL_DEVID; 932 break; 933 case MII_ANAR: 934 phy_reg = DC_AL_ANAR; 935 break; 936 case MII_ANLPAR: 937 phy_reg = DC_AL_LPAR; 938 break; 939 case MII_ANER: 940 phy_reg = DC_AL_ANER; 941 break; 942 default: 943 printf("dc%d: phy_write: bad phy register %x\n", 944 sc->dc_unit, reg); 945 return (0); 946 break; 947 } 948 949 CSR_WRITE_4(sc, phy_reg, data); 950 return (0); 951 } 952 953 frame.mii_phyaddr = phy; 954 frame.mii_regaddr = reg; 955 frame.mii_data = data; 956 957 if (sc->dc_type == DC_TYPE_98713) { 958 phy_reg = CSR_READ_4(sc, DC_NETCFG); 959 CSR_WRITE_4(sc, DC_NETCFG, phy_reg & ~DC_NETCFG_PORTSEL); 960 } 961 dc_mii_writereg(sc, &frame); 962 if (sc->dc_type == DC_TYPE_98713) 963 CSR_WRITE_4(sc, DC_NETCFG, phy_reg); 964 965 return (0); 966 } 967 968 static void 969 dc_miibus_statchg(device_t dev) 970 { 971 struct dc_softc *sc; 972 struct mii_data *mii; 973 struct ifmedia *ifm; 974 975 sc = device_get_softc(dev); 976 if (DC_IS_ADMTEK(sc)) 977 return; 978 979 mii = device_get_softc(sc->dc_miibus); 980 ifm = &mii->mii_media; 981 if (DC_IS_DAVICOM(sc) && 982 IFM_SUBTYPE(ifm->ifm_media) == IFM_HPNA_1) { 983 dc_setcfg(sc, ifm->ifm_media); 984 sc->dc_if_media = ifm->ifm_media; 985 } else { 986 dc_setcfg(sc, mii->mii_media_active); 987 sc->dc_if_media = mii->mii_media_active; 988 } 989 } 990 991 /* 992 * Special support for DM9102A cards with HomePNA PHYs. Note: 993 * with the Davicom DM9102A/DM9801 eval board that I have, it seems 994 * to be impossible to talk to the management interface of the DM9801 995 * PHY (its MDIO pin is not connected to anything). Consequently, 996 * the driver has to just 'know' about the additional mode and deal 997 * with it itself. *sigh* 998 */ 999 static void 1000 dc_miibus_mediainit(device_t dev) 1001 { 1002 struct dc_softc *sc; 1003 struct mii_data *mii; 1004 struct ifmedia *ifm; 1005 int rev; 1006 1007 rev = pci_read_config(dev, DC_PCI_CFRV, 4) & 0xFF; 1008 1009 sc = device_get_softc(dev); 1010 mii = device_get_softc(sc->dc_miibus); 1011 ifm = &mii->mii_media; 1012 1013 if (DC_IS_DAVICOM(sc) && rev >= DC_REVISION_DM9102A) 1014 ifmedia_add(ifm, IFM_ETHER | IFM_HPNA_1, 0, NULL); 1015 } 1016 1017 #define DC_POLY 0xEDB88320 1018 #define DC_BITS_512 9 1019 #define DC_BITS_128 7 1020 #define DC_BITS_64 6 1021 1022 static uint32_t 1023 dc_mchash_le(struct dc_softc *sc, const uint8_t *addr) 1024 { 1025 uint32_t crc; 1026 int idx, bit; 1027 uint8_t data; 1028 1029 /* Compute CRC for the address value. */ 1030 crc = 0xFFFFFFFF; /* initial value */ 1031 1032 for (idx = 0; idx < 6; idx++) { 1033 for (data = *addr++, bit = 0; bit < 8; bit++, data >>= 1) 1034 crc = (crc >> 1) ^ (((crc ^ data) & 1) ? DC_POLY : 0); 1035 } 1036 1037 /* 1038 * The hash table on the PNIC II and the MX98715AEC-C/D/E 1039 * chips is only 128 bits wide. 1040 */ 1041 if (sc->dc_flags & DC_128BIT_HASH) 1042 return (crc & ((1 << DC_BITS_128) - 1)); 1043 1044 /* The hash table on the MX98715BEC is only 64 bits wide. */ 1045 if (sc->dc_flags & DC_64BIT_HASH) 1046 return (crc & ((1 << DC_BITS_64) - 1)); 1047 1048 /* Xircom's hash filtering table is different (read: weird) */ 1049 /* Xircom uses the LEAST significant bits */ 1050 if (DC_IS_XIRCOM(sc)) { 1051 if ((crc & 0x180) == 0x180) 1052 return ((crc & 0x0F) + (crc & 0x70) * 3 + (14 << 4)); 1053 else 1054 return ((crc & 0x1F) + ((crc >> 1) & 0xF0) * 3 + 1055 (12 << 4)); 1056 } 1057 1058 return (crc & ((1 << DC_BITS_512) - 1)); 1059 } 1060 1061 /* 1062 * Calculate CRC of a multicast group address, return the lower 6 bits. 1063 */ 1064 static uint32_t 1065 dc_mchash_be(const uint8_t *addr) 1066 { 1067 uint32_t crc, carry; 1068 int idx, bit; 1069 uint8_t data; 1070 1071 /* Compute CRC for the address value. */ 1072 crc = 0xFFFFFFFF; /* initial value */ 1073 1074 for (idx = 0; idx < 6; idx++) { 1075 for (data = *addr++, bit = 0; bit < 8; bit++, data >>= 1) { 1076 carry = ((crc & 0x80000000) ? 1 : 0) ^ (data & 0x01); 1077 data >>= 1; 1078 crc <<= 1; 1079 if (carry) 1080 crc = (crc ^ 0x04c11db6) | carry; 1081 } 1082 } 1083 1084 /* Return the filter bit position. */ 1085 return ((crc >> 26) & 0x0000003F); 1086 } 1087 1088 /* 1089 * 21143-style RX filter setup routine. Filter programming is done by 1090 * downloading a special setup frame into the TX engine. 21143, Macronix, 1091 * PNIC, PNIC II and Davicom chips are programmed this way. 1092 * 1093 * We always program the chip using 'hash perfect' mode, i.e. one perfect 1094 * address (our node address) and a 512-bit hash filter for multicast 1095 * frames. We also sneak the broadcast address into the hash filter since 1096 * we need that too. 1097 */ 1098 static void 1099 dc_setfilt_21143(struct dc_softc *sc) 1100 { 1101 struct dc_desc *sframe; 1102 u_int32_t h, *sp; 1103 struct ifmultiaddr *ifma; 1104 struct ifnet *ifp; 1105 int i; 1106 1107 ifp = &sc->arpcom.ac_if; 1108 1109 i = sc->dc_cdata.dc_tx_prod; 1110 DC_INC(sc->dc_cdata.dc_tx_prod, DC_TX_LIST_CNT); 1111 sc->dc_cdata.dc_tx_cnt++; 1112 sframe = &sc->dc_ldata->dc_tx_list[i]; 1113 sp = sc->dc_cdata.dc_sbuf; 1114 bzero(sp, DC_SFRAME_LEN); 1115 1116 sframe->dc_data = htole32(sc->dc_saddr); 1117 sframe->dc_ctl = htole32(DC_SFRAME_LEN | DC_TXCTL_SETUP | 1118 DC_TXCTL_TLINK | DC_FILTER_HASHPERF | DC_TXCTL_FINT); 1119 1120 sc->dc_cdata.dc_tx_chain[i] = (struct mbuf *)sc->dc_cdata.dc_sbuf; 1121 1122 /* If we want promiscuous mode, set the allframes bit. */ 1123 if (ifp->if_flags & IFF_PROMISC) 1124 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC); 1125 else 1126 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC); 1127 1128 if (ifp->if_flags & IFF_ALLMULTI) 1129 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI); 1130 else 1131 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI); 1132 1133 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 1134 if (ifma->ifma_addr->sa_family != AF_LINK) 1135 continue; 1136 h = dc_mchash_le(sc, 1137 LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 1138 sp[h >> 4] |= htole32(1 << (h & 0xF)); 1139 } 1140 1141 if (ifp->if_flags & IFF_BROADCAST) { 1142 h = dc_mchash_le(sc, ifp->if_broadcastaddr); 1143 sp[h >> 4] |= htole32(1 << (h & 0xF)); 1144 } 1145 1146 /* Set our MAC address */ 1147 sp[39] = DC_SP_MAC(((u_int16_t *)sc->arpcom.ac_enaddr)[0]); 1148 sp[40] = DC_SP_MAC(((u_int16_t *)sc->arpcom.ac_enaddr)[1]); 1149 sp[41] = DC_SP_MAC(((u_int16_t *)sc->arpcom.ac_enaddr)[2]); 1150 1151 sframe->dc_status = htole32(DC_TXSTAT_OWN); 1152 CSR_WRITE_4(sc, DC_TXSTART, 0xFFFFFFFF); 1153 1154 /* 1155 * The PNIC takes an exceedingly long time to process its 1156 * setup frame; wait 10ms after posting the setup frame 1157 * before proceeding, just so it has time to swallow its 1158 * medicine. 1159 */ 1160 DELAY(10000); 1161 1162 ifp->if_timer = 5; 1163 } 1164 1165 static void 1166 dc_setfilt_admtek(struct dc_softc *sc) 1167 { 1168 struct ifnet *ifp; 1169 struct ifmultiaddr *ifma; 1170 int h = 0; 1171 u_int32_t hashes[2] = { 0, 0 }; 1172 1173 ifp = &sc->arpcom.ac_if; 1174 1175 /* Init our MAC address. */ 1176 CSR_WRITE_4(sc, DC_AL_PAR0, *(u_int32_t *)(&sc->arpcom.ac_enaddr[0])); 1177 CSR_WRITE_4(sc, DC_AL_PAR1, *(u_int32_t *)(&sc->arpcom.ac_enaddr[4])); 1178 1179 /* If we want promiscuous mode, set the allframes bit. */ 1180 if (ifp->if_flags & IFF_PROMISC) 1181 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC); 1182 else 1183 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC); 1184 1185 if (ifp->if_flags & IFF_ALLMULTI) 1186 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI); 1187 else 1188 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI); 1189 1190 /* First, zot all the existing hash bits. */ 1191 CSR_WRITE_4(sc, DC_AL_MAR0, 0); 1192 CSR_WRITE_4(sc, DC_AL_MAR1, 0); 1193 1194 /* 1195 * If we're already in promisc or allmulti mode, we 1196 * don't have to bother programming the multicast filter. 1197 */ 1198 if (ifp->if_flags & (IFF_PROMISC | IFF_ALLMULTI)) 1199 return; 1200 1201 /* Now program new ones. */ 1202 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 1203 if (ifma->ifma_addr->sa_family != AF_LINK) 1204 continue; 1205 if (DC_IS_CENTAUR(sc)) 1206 h = dc_mchash_le(sc, 1207 LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 1208 else 1209 h = dc_mchash_be( 1210 LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 1211 if (h < 32) 1212 hashes[0] |= (1 << h); 1213 else 1214 hashes[1] |= (1 << (h - 32)); 1215 } 1216 1217 CSR_WRITE_4(sc, DC_AL_MAR0, hashes[0]); 1218 CSR_WRITE_4(sc, DC_AL_MAR1, hashes[1]); 1219 } 1220 1221 static void 1222 dc_setfilt_asix(struct dc_softc *sc) 1223 { 1224 struct ifnet *ifp; 1225 struct ifmultiaddr *ifma; 1226 int h = 0; 1227 u_int32_t hashes[2] = { 0, 0 }; 1228 1229 ifp = &sc->arpcom.ac_if; 1230 1231 /* Init our MAC address */ 1232 CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_PAR0); 1233 CSR_WRITE_4(sc, DC_AX_FILTDATA, 1234 *(u_int32_t *)(&sc->arpcom.ac_enaddr[0])); 1235 CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_PAR1); 1236 CSR_WRITE_4(sc, DC_AX_FILTDATA, 1237 *(u_int32_t *)(&sc->arpcom.ac_enaddr[4])); 1238 1239 /* If we want promiscuous mode, set the allframes bit. */ 1240 if (ifp->if_flags & IFF_PROMISC) 1241 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC); 1242 else 1243 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC); 1244 1245 if (ifp->if_flags & IFF_ALLMULTI) 1246 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI); 1247 else 1248 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI); 1249 1250 /* 1251 * The ASIX chip has a special bit to enable reception 1252 * of broadcast frames. 1253 */ 1254 if (ifp->if_flags & IFF_BROADCAST) 1255 DC_SETBIT(sc, DC_NETCFG, DC_AX_NETCFG_RX_BROAD); 1256 else 1257 DC_CLRBIT(sc, DC_NETCFG, DC_AX_NETCFG_RX_BROAD); 1258 1259 /* first, zot all the existing hash bits */ 1260 CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_MAR0); 1261 CSR_WRITE_4(sc, DC_AX_FILTDATA, 0); 1262 CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_MAR1); 1263 CSR_WRITE_4(sc, DC_AX_FILTDATA, 0); 1264 1265 /* 1266 * If we're already in promisc or allmulti mode, we 1267 * don't have to bother programming the multicast filter. 1268 */ 1269 if (ifp->if_flags & (IFF_PROMISC | IFF_ALLMULTI)) 1270 return; 1271 1272 /* now program new ones */ 1273 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 1274 if (ifma->ifma_addr->sa_family != AF_LINK) 1275 continue; 1276 h = dc_mchash_be(LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 1277 if (h < 32) 1278 hashes[0] |= (1 << h); 1279 else 1280 hashes[1] |= (1 << (h - 32)); 1281 } 1282 1283 CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_MAR0); 1284 CSR_WRITE_4(sc, DC_AX_FILTDATA, hashes[0]); 1285 CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_MAR1); 1286 CSR_WRITE_4(sc, DC_AX_FILTDATA, hashes[1]); 1287 } 1288 1289 static void 1290 dc_setfilt_xircom(struct dc_softc *sc) 1291 { 1292 struct ifnet *ifp; 1293 struct ifmultiaddr *ifma; 1294 struct dc_desc *sframe; 1295 u_int32_t h, *sp; 1296 int i; 1297 1298 ifp = &sc->arpcom.ac_if; 1299 DC_CLRBIT(sc, DC_NETCFG, (DC_NETCFG_TX_ON | DC_NETCFG_RX_ON)); 1300 1301 i = sc->dc_cdata.dc_tx_prod; 1302 DC_INC(sc->dc_cdata.dc_tx_prod, DC_TX_LIST_CNT); 1303 sc->dc_cdata.dc_tx_cnt++; 1304 sframe = &sc->dc_ldata->dc_tx_list[i]; 1305 sp = sc->dc_cdata.dc_sbuf; 1306 bzero(sp, DC_SFRAME_LEN); 1307 1308 sframe->dc_data = htole32(sc->dc_saddr); 1309 sframe->dc_ctl = htole32(DC_SFRAME_LEN | DC_TXCTL_SETUP | 1310 DC_TXCTL_TLINK | DC_FILTER_HASHPERF | DC_TXCTL_FINT); 1311 1312 sc->dc_cdata.dc_tx_chain[i] = (struct mbuf *)sc->dc_cdata.dc_sbuf; 1313 1314 /* If we want promiscuous mode, set the allframes bit. */ 1315 if (ifp->if_flags & IFF_PROMISC) 1316 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC); 1317 else 1318 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC); 1319 1320 if (ifp->if_flags & IFF_ALLMULTI) 1321 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI); 1322 else 1323 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI); 1324 1325 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 1326 if (ifma->ifma_addr->sa_family != AF_LINK) 1327 continue; 1328 h = dc_mchash_le(sc, 1329 LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 1330 sp[h >> 4] |= htole32(1 << (h & 0xF)); 1331 } 1332 1333 if (ifp->if_flags & IFF_BROADCAST) { 1334 h = dc_mchash_le(sc, ifp->if_broadcastaddr); 1335 sp[h >> 4] |= htole32(1 << (h & 0xF)); 1336 } 1337 1338 /* Set our MAC address */ 1339 sp[0] = DC_SP_MAC(((u_int16_t *)sc->arpcom.ac_enaddr)[0]); 1340 sp[1] = DC_SP_MAC(((u_int16_t *)sc->arpcom.ac_enaddr)[1]); 1341 sp[2] = DC_SP_MAC(((u_int16_t *)sc->arpcom.ac_enaddr)[2]); 1342 1343 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_TX_ON); 1344 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_ON); 1345 ifp->if_flags |= IFF_RUNNING; 1346 sframe->dc_status = htole32(DC_TXSTAT_OWN); 1347 CSR_WRITE_4(sc, DC_TXSTART, 0xFFFFFFFF); 1348 1349 /* 1350 * Wait some time... 1351 */ 1352 DELAY(1000); 1353 1354 ifp->if_timer = 5; 1355 } 1356 1357 static void 1358 dc_setfilt(struct dc_softc *sc) 1359 { 1360 1361 if (DC_IS_INTEL(sc) || DC_IS_MACRONIX(sc) || DC_IS_PNIC(sc) || 1362 DC_IS_PNICII(sc) || DC_IS_DAVICOM(sc) || DC_IS_CONEXANT(sc)) 1363 dc_setfilt_21143(sc); 1364 1365 if (DC_IS_ASIX(sc)) 1366 dc_setfilt_asix(sc); 1367 1368 if (DC_IS_ADMTEK(sc)) 1369 dc_setfilt_admtek(sc); 1370 1371 if (DC_IS_XIRCOM(sc)) 1372 dc_setfilt_xircom(sc); 1373 } 1374 1375 /* 1376 * In order to fiddle with the 'full-duplex' and '100Mbps' bits in 1377 * the netconfig register, we first have to put the transmit and/or 1378 * receive logic in the idle state. 1379 */ 1380 static void 1381 dc_setcfg(struct dc_softc *sc, int media) 1382 { 1383 int i, restart = 0, watchdogreg; 1384 u_int32_t isr; 1385 1386 if (IFM_SUBTYPE(media) == IFM_NONE) 1387 return; 1388 1389 if (CSR_READ_4(sc, DC_NETCFG) & (DC_NETCFG_TX_ON | DC_NETCFG_RX_ON)) { 1390 restart = 1; 1391 DC_CLRBIT(sc, DC_NETCFG, (DC_NETCFG_TX_ON | DC_NETCFG_RX_ON)); 1392 1393 for (i = 0; i < DC_TIMEOUT; i++) { 1394 isr = CSR_READ_4(sc, DC_ISR); 1395 if (isr & DC_ISR_TX_IDLE && 1396 ((isr & DC_ISR_RX_STATE) == DC_RXSTATE_STOPPED || 1397 (isr & DC_ISR_RX_STATE) == DC_RXSTATE_WAIT)) 1398 break; 1399 DELAY(10); 1400 } 1401 1402 if (i == DC_TIMEOUT) 1403 printf("dc%d: failed to force tx and " 1404 "rx to idle state\n", sc->dc_unit); 1405 } 1406 1407 if (IFM_SUBTYPE(media) == IFM_100_TX) { 1408 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_SPEEDSEL); 1409 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_HEARTBEAT); 1410 if (sc->dc_pmode == DC_PMODE_MII) { 1411 if (DC_IS_INTEL(sc)) { 1412 /* There's a write enable bit here that reads as 1. */ 1413 watchdogreg = CSR_READ_4(sc, DC_WATCHDOG); 1414 watchdogreg &= ~DC_WDOG_CTLWREN; 1415 watchdogreg |= DC_WDOG_JABBERDIS; 1416 CSR_WRITE_4(sc, DC_WATCHDOG, watchdogreg); 1417 } else { 1418 DC_SETBIT(sc, DC_WATCHDOG, DC_WDOG_JABBERDIS); 1419 } 1420 DC_CLRBIT(sc, DC_NETCFG, (DC_NETCFG_PCS | 1421 DC_NETCFG_PORTSEL | DC_NETCFG_SCRAMBLER)); 1422 if (sc->dc_type == DC_TYPE_98713) 1423 DC_SETBIT(sc, DC_NETCFG, (DC_NETCFG_PCS | 1424 DC_NETCFG_SCRAMBLER)); 1425 if (!DC_IS_DAVICOM(sc)) 1426 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL); 1427 DC_CLRBIT(sc, DC_10BTCTRL, 0xFFFF); 1428 if (DC_IS_INTEL(sc)) 1429 dc_apply_fixup(sc, IFM_AUTO); 1430 } else { 1431 if (DC_IS_PNIC(sc)) { 1432 DC_PN_GPIO_SETBIT(sc, DC_PN_GPIO_SPEEDSEL); 1433 DC_PN_GPIO_SETBIT(sc, DC_PN_GPIO_100TX_LOOP); 1434 DC_SETBIT(sc, DC_PN_NWAY, DC_PN_NWAY_SPEEDSEL); 1435 } 1436 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL); 1437 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PCS); 1438 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_SCRAMBLER); 1439 if (DC_IS_INTEL(sc)) 1440 dc_apply_fixup(sc, 1441 (media & IFM_GMASK) == IFM_FDX ? 1442 IFM_100_TX | IFM_FDX : IFM_100_TX); 1443 } 1444 } 1445 1446 if (IFM_SUBTYPE(media) == IFM_10_T) { 1447 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_SPEEDSEL); 1448 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_HEARTBEAT); 1449 if (sc->dc_pmode == DC_PMODE_MII) { 1450 /* There's a write enable bit here that reads as 1. */ 1451 if (DC_IS_INTEL(sc)) { 1452 watchdogreg = CSR_READ_4(sc, DC_WATCHDOG); 1453 watchdogreg &= ~DC_WDOG_CTLWREN; 1454 watchdogreg |= DC_WDOG_JABBERDIS; 1455 CSR_WRITE_4(sc, DC_WATCHDOG, watchdogreg); 1456 } else { 1457 DC_SETBIT(sc, DC_WATCHDOG, DC_WDOG_JABBERDIS); 1458 } 1459 DC_CLRBIT(sc, DC_NETCFG, (DC_NETCFG_PCS | 1460 DC_NETCFG_PORTSEL | DC_NETCFG_SCRAMBLER)); 1461 if (sc->dc_type == DC_TYPE_98713) 1462 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PCS); 1463 if (!DC_IS_DAVICOM(sc)) 1464 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL); 1465 DC_CLRBIT(sc, DC_10BTCTRL, 0xFFFF); 1466 if (DC_IS_INTEL(sc)) 1467 dc_apply_fixup(sc, IFM_AUTO); 1468 } else { 1469 if (DC_IS_PNIC(sc)) { 1470 DC_PN_GPIO_CLRBIT(sc, DC_PN_GPIO_SPEEDSEL); 1471 DC_PN_GPIO_SETBIT(sc, DC_PN_GPIO_100TX_LOOP); 1472 DC_CLRBIT(sc, DC_PN_NWAY, DC_PN_NWAY_SPEEDSEL); 1473 } 1474 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL); 1475 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_PCS); 1476 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_SCRAMBLER); 1477 if (DC_IS_INTEL(sc)) { 1478 DC_CLRBIT(sc, DC_SIARESET, DC_SIA_RESET); 1479 DC_CLRBIT(sc, DC_10BTCTRL, 0xFFFF); 1480 if ((media & IFM_GMASK) == IFM_FDX) 1481 DC_SETBIT(sc, DC_10BTCTRL, 0x7F3D); 1482 else 1483 DC_SETBIT(sc, DC_10BTCTRL, 0x7F3F); 1484 DC_SETBIT(sc, DC_SIARESET, DC_SIA_RESET); 1485 DC_CLRBIT(sc, DC_10BTCTRL, 1486 DC_TCTL_AUTONEGENBL); 1487 dc_apply_fixup(sc, 1488 (media & IFM_GMASK) == IFM_FDX ? 1489 IFM_10_T | IFM_FDX : IFM_10_T); 1490 DELAY(20000); 1491 } 1492 } 1493 } 1494 1495 /* 1496 * If this is a Davicom DM9102A card with a DM9801 HomePNA 1497 * PHY and we want HomePNA mode, set the portsel bit to turn 1498 * on the external MII port. 1499 */ 1500 if (DC_IS_DAVICOM(sc)) { 1501 if (IFM_SUBTYPE(media) == IFM_HPNA_1) { 1502 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL); 1503 sc->dc_link = 1; 1504 } else { 1505 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL); 1506 } 1507 } 1508 1509 if ((media & IFM_GMASK) == IFM_FDX) { 1510 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_FULLDUPLEX); 1511 if (sc->dc_pmode == DC_PMODE_SYM && DC_IS_PNIC(sc)) 1512 DC_SETBIT(sc, DC_PN_NWAY, DC_PN_NWAY_DUPLEX); 1513 } else { 1514 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_FULLDUPLEX); 1515 if (sc->dc_pmode == DC_PMODE_SYM && DC_IS_PNIC(sc)) 1516 DC_CLRBIT(sc, DC_PN_NWAY, DC_PN_NWAY_DUPLEX); 1517 } 1518 1519 if (restart) 1520 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_TX_ON | DC_NETCFG_RX_ON); 1521 } 1522 1523 static void 1524 dc_reset(struct dc_softc *sc) 1525 { 1526 int i; 1527 1528 DC_SETBIT(sc, DC_BUSCTL, DC_BUSCTL_RESET); 1529 1530 for (i = 0; i < DC_TIMEOUT; i++) { 1531 DELAY(10); 1532 if (!(CSR_READ_4(sc, DC_BUSCTL) & DC_BUSCTL_RESET)) 1533 break; 1534 } 1535 1536 if (DC_IS_ASIX(sc) || DC_IS_ADMTEK(sc) || DC_IS_CONEXANT(sc) || 1537 DC_IS_XIRCOM(sc) || DC_IS_INTEL(sc)) { 1538 DELAY(10000); 1539 DC_CLRBIT(sc, DC_BUSCTL, DC_BUSCTL_RESET); 1540 i = 0; 1541 } 1542 1543 if (i == DC_TIMEOUT) 1544 printf("dc%d: reset never completed!\n", sc->dc_unit); 1545 1546 /* Wait a little while for the chip to get its brains in order. */ 1547 DELAY(1000); 1548 1549 CSR_WRITE_4(sc, DC_IMR, 0x00000000); 1550 CSR_WRITE_4(sc, DC_BUSCTL, 0x00000000); 1551 CSR_WRITE_4(sc, DC_NETCFG, 0x00000000); 1552 1553 /* 1554 * Bring the SIA out of reset. In some cases, it looks 1555 * like failing to unreset the SIA soon enough gets it 1556 * into a state where it will never come out of reset 1557 * until we reset the whole chip again. 1558 */ 1559 if (DC_IS_INTEL(sc)) { 1560 DC_SETBIT(sc, DC_SIARESET, DC_SIA_RESET); 1561 CSR_WRITE_4(sc, DC_10BTCTRL, 0); 1562 CSR_WRITE_4(sc, DC_WATCHDOG, 0); 1563 } 1564 } 1565 1566 static struct dc_type * 1567 dc_devtype(device_t dev) 1568 { 1569 struct dc_type *t; 1570 u_int32_t rev; 1571 1572 t = dc_devs; 1573 1574 while (t->dc_name != NULL) { 1575 if ((pci_get_vendor(dev) == t->dc_vid) && 1576 (pci_get_device(dev) == t->dc_did)) { 1577 /* Check the PCI revision */ 1578 rev = pci_read_config(dev, DC_PCI_CFRV, 4) & 0xFF; 1579 if (t->dc_did == DC_DEVICEID_98713 && 1580 rev >= DC_REVISION_98713A) 1581 t++; 1582 if (t->dc_did == DC_DEVICEID_98713_CP && 1583 rev >= DC_REVISION_98713A) 1584 t++; 1585 if (t->dc_did == DC_DEVICEID_987x5 && 1586 rev >= DC_REVISION_98715AEC_C) 1587 t++; 1588 if (t->dc_did == DC_DEVICEID_987x5 && 1589 rev >= DC_REVISION_98725) 1590 t++; 1591 if (t->dc_did == DC_DEVICEID_AX88140A && 1592 rev >= DC_REVISION_88141) 1593 t++; 1594 if (t->dc_did == DC_DEVICEID_82C168 && 1595 rev >= DC_REVISION_82C169) 1596 t++; 1597 if (t->dc_did == DC_DEVICEID_DM9102 && 1598 rev >= DC_REVISION_DM9102A) 1599 t++; 1600 /* 1601 * The Microsoft MN-130 has a device ID of 0x0002, 1602 * which happens to be the same as the PNIC 82c168. 1603 * To keep dc_attach() from getting confused, we 1604 * pretend its ID is something different. 1605 * XXX: ideally, dc_attach() should be checking 1606 * vendorid+deviceid together to avoid such 1607 * collisions. 1608 */ 1609 if (t->dc_vid == DC_VENDORID_MICROSOFT && 1610 t->dc_did == DC_DEVICEID_MSMN130) 1611 t++; 1612 return (t); 1613 } 1614 t++; 1615 } 1616 1617 return (NULL); 1618 } 1619 1620 /* 1621 * Probe for a 21143 or clone chip. Check the PCI vendor and device 1622 * IDs against our list and return a device name if we find a match. 1623 * We do a little bit of extra work to identify the exact type of 1624 * chip. The MX98713 and MX98713A have the same PCI vendor/device ID, 1625 * but different revision IDs. The same is true for 98715/98715A 1626 * chips and the 98725, as well as the ASIX and ADMtek chips. In some 1627 * cases, the exact chip revision affects driver behavior. 1628 */ 1629 static int 1630 dc_probe(device_t dev) 1631 { 1632 struct dc_type *t; 1633 1634 t = dc_devtype(dev); 1635 1636 if (t != NULL) { 1637 device_set_desc(dev, t->dc_name); 1638 return (0); 1639 } 1640 1641 return (ENXIO); 1642 } 1643 1644 #ifndef BURN_BRIDGES 1645 static void 1646 dc_acpi(device_t dev) 1647 { 1648 int unit; 1649 u_int32_t iobase, membase, irq; 1650 1651 unit = device_get_unit(dev); 1652 1653 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) { 1654 /* Save important PCI config data. */ 1655 iobase = pci_read_config(dev, DC_PCI_CFBIO, 4); 1656 membase = pci_read_config(dev, DC_PCI_CFBMA, 4); 1657 irq = pci_read_config(dev, DC_PCI_CFIT, 4); 1658 1659 /* Reset the power state. */ 1660 printf("dc%d: chip is in D%d power mode " 1661 "-- setting to D0\n", unit, 1662 pci_get_powerstate(dev)); 1663 pci_set_powerstate(dev, PCI_POWERSTATE_D0); 1664 1665 /* Restore PCI config data. */ 1666 pci_write_config(dev, DC_PCI_CFBIO, iobase, 4); 1667 pci_write_config(dev, DC_PCI_CFBMA, membase, 4); 1668 pci_write_config(dev, DC_PCI_CFIT, irq, 4); 1669 } 1670 } 1671 #endif 1672 1673 static void 1674 dc_apply_fixup(struct dc_softc *sc, int media) 1675 { 1676 struct dc_mediainfo *m; 1677 u_int8_t *p; 1678 int i; 1679 u_int32_t reg; 1680 1681 m = sc->dc_mi; 1682 1683 while (m != NULL) { 1684 if (m->dc_media == media) 1685 break; 1686 m = m->dc_next; 1687 } 1688 1689 if (m == NULL) 1690 return; 1691 1692 for (i = 0, p = m->dc_reset_ptr; i < m->dc_reset_len; i++, p += 2) { 1693 reg = (p[0] | (p[1] << 8)) << 16; 1694 CSR_WRITE_4(sc, DC_WATCHDOG, reg); 1695 } 1696 1697 for (i = 0, p = m->dc_gp_ptr; i < m->dc_gp_len; i++, p += 2) { 1698 reg = (p[0] | (p[1] << 8)) << 16; 1699 CSR_WRITE_4(sc, DC_WATCHDOG, reg); 1700 } 1701 } 1702 1703 static void 1704 dc_decode_leaf_sia(struct dc_softc *sc, struct dc_eblock_sia *l) 1705 { 1706 struct dc_mediainfo *m; 1707 1708 m = malloc(sizeof(struct dc_mediainfo), M_DEVBUF, M_NOWAIT | M_ZERO); 1709 switch (l->dc_sia_code & ~DC_SIA_CODE_EXT) { 1710 case DC_SIA_CODE_10BT: 1711 m->dc_media = IFM_10_T; 1712 break; 1713 case DC_SIA_CODE_10BT_FDX: 1714 m->dc_media = IFM_10_T | IFM_FDX; 1715 break; 1716 case DC_SIA_CODE_10B2: 1717 m->dc_media = IFM_10_2; 1718 break; 1719 case DC_SIA_CODE_10B5: 1720 m->dc_media = IFM_10_5; 1721 break; 1722 default: 1723 break; 1724 } 1725 1726 /* 1727 * We need to ignore CSR13, CSR14, CSR15 for SIA mode. 1728 * Things apparently already work for cards that do 1729 * supply Media Specific Data. 1730 */ 1731 if (l->dc_sia_code & DC_SIA_CODE_EXT) { 1732 m->dc_gp_len = 2; 1733 m->dc_gp_ptr = 1734 (u_int8_t *)&l->dc_un.dc_sia_ext.dc_sia_gpio_ctl; 1735 } else { 1736 m->dc_gp_len = 2; 1737 m->dc_gp_ptr = 1738 (u_int8_t *)&l->dc_un.dc_sia_noext.dc_sia_gpio_ctl; 1739 } 1740 1741 m->dc_next = sc->dc_mi; 1742 sc->dc_mi = m; 1743 1744 sc->dc_pmode = DC_PMODE_SIA; 1745 } 1746 1747 static void 1748 dc_decode_leaf_sym(struct dc_softc *sc, struct dc_eblock_sym *l) 1749 { 1750 struct dc_mediainfo *m; 1751 1752 m = malloc(sizeof(struct dc_mediainfo), M_DEVBUF, M_NOWAIT | M_ZERO); 1753 if (l->dc_sym_code == DC_SYM_CODE_100BT) 1754 m->dc_media = IFM_100_TX; 1755 1756 if (l->dc_sym_code == DC_SYM_CODE_100BT_FDX) 1757 m->dc_media = IFM_100_TX | IFM_FDX; 1758 1759 m->dc_gp_len = 2; 1760 m->dc_gp_ptr = (u_int8_t *)&l->dc_sym_gpio_ctl; 1761 1762 m->dc_next = sc->dc_mi; 1763 sc->dc_mi = m; 1764 1765 sc->dc_pmode = DC_PMODE_SYM; 1766 } 1767 1768 static void 1769 dc_decode_leaf_mii(struct dc_softc *sc, struct dc_eblock_mii *l) 1770 { 1771 struct dc_mediainfo *m; 1772 u_int8_t *p; 1773 1774 m = malloc(sizeof(struct dc_mediainfo), M_DEVBUF, M_NOWAIT | M_ZERO); 1775 /* We abuse IFM_AUTO to represent MII. */ 1776 m->dc_media = IFM_AUTO; 1777 m->dc_gp_len = l->dc_gpr_len; 1778 1779 p = (u_int8_t *)l; 1780 p += sizeof(struct dc_eblock_mii); 1781 m->dc_gp_ptr = p; 1782 p += 2 * l->dc_gpr_len; 1783 m->dc_reset_len = *p; 1784 p++; 1785 m->dc_reset_ptr = p; 1786 1787 m->dc_next = sc->dc_mi; 1788 sc->dc_mi = m; 1789 } 1790 1791 static void 1792 dc_read_srom(struct dc_softc *sc, int bits) 1793 { 1794 int size; 1795 1796 size = 2 << bits; 1797 sc->dc_srom = malloc(size, M_DEVBUF, M_NOWAIT); 1798 dc_read_eeprom(sc, (caddr_t)sc->dc_srom, 0, (size / 2), 0); 1799 } 1800 1801 static void 1802 dc_parse_21143_srom(struct dc_softc *sc) 1803 { 1804 struct dc_leaf_hdr *lhdr; 1805 struct dc_eblock_hdr *hdr; 1806 int have_mii, i, loff; 1807 char *ptr; 1808 1809 have_mii = 0; 1810 loff = sc->dc_srom[27]; 1811 lhdr = (struct dc_leaf_hdr *)&(sc->dc_srom[loff]); 1812 1813 ptr = (char *)lhdr; 1814 ptr += sizeof(struct dc_leaf_hdr) - 1; 1815 /* 1816 * Look if we got a MII media block. 1817 */ 1818 for (i = 0; i < lhdr->dc_mcnt; i++) { 1819 hdr = (struct dc_eblock_hdr *)ptr; 1820 if (hdr->dc_type == DC_EBLOCK_MII) 1821 have_mii++; 1822 1823 ptr += (hdr->dc_len & 0x7F); 1824 ptr++; 1825 } 1826 1827 /* 1828 * Do the same thing again. Only use SIA and SYM media 1829 * blocks if no MII media block is available. 1830 */ 1831 ptr = (char *)lhdr; 1832 ptr += sizeof(struct dc_leaf_hdr) - 1; 1833 for (i = 0; i < lhdr->dc_mcnt; i++) { 1834 hdr = (struct dc_eblock_hdr *)ptr; 1835 switch (hdr->dc_type) { 1836 case DC_EBLOCK_MII: 1837 dc_decode_leaf_mii(sc, (struct dc_eblock_mii *)hdr); 1838 break; 1839 case DC_EBLOCK_SIA: 1840 if (! have_mii) 1841 dc_decode_leaf_sia(sc, 1842 (struct dc_eblock_sia *)hdr); 1843 break; 1844 case DC_EBLOCK_SYM: 1845 if (! have_mii) 1846 dc_decode_leaf_sym(sc, 1847 (struct dc_eblock_sym *)hdr); 1848 break; 1849 default: 1850 /* Don't care. Yet. */ 1851 break; 1852 } 1853 ptr += (hdr->dc_len & 0x7F); 1854 ptr++; 1855 } 1856 } 1857 1858 static void 1859 dc_dma_map_addr(void *arg, bus_dma_segment_t *segs, int nseg, int error) 1860 { 1861 u_int32_t *paddr; 1862 1863 KASSERT(nseg == 1, ("wrong number of segments, should be 1")); 1864 paddr = arg; 1865 *paddr = segs->ds_addr; 1866 } 1867 1868 /* 1869 * Attach the interface. Allocate softc structures, do ifmedia 1870 * setup and ethernet/BPF attach. 1871 */ 1872 static int 1873 dc_attach(device_t dev) 1874 { 1875 int tmp = 0; 1876 u_char eaddr[ETHER_ADDR_LEN]; 1877 u_int32_t command; 1878 struct dc_softc *sc; 1879 struct ifnet *ifp; 1880 u_int32_t revision; 1881 int unit, error = 0, rid, mac_offset; 1882 int i; 1883 u_int8_t *mac; 1884 1885 sc = device_get_softc(dev); 1886 unit = device_get_unit(dev); 1887 1888 mtx_init(&sc->dc_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 1889 MTX_DEF | MTX_RECURSE); 1890 #ifndef BURN_BRIDGES 1891 /* 1892 * Handle power management nonsense. 1893 */ 1894 dc_acpi(dev); 1895 #endif 1896 /* 1897 * Map control/status registers. 1898 */ 1899 pci_enable_busmaster(dev); 1900 1901 rid = DC_RID; 1902 sc->dc_res = bus_alloc_resource(dev, DC_RES, &rid, 1903 0, ~0, 1, RF_ACTIVE); 1904 1905 if (sc->dc_res == NULL) { 1906 printf("dc%d: couldn't map ports/memory\n", unit); 1907 error = ENXIO; 1908 goto fail; 1909 } 1910 1911 sc->dc_btag = rman_get_bustag(sc->dc_res); 1912 sc->dc_bhandle = rman_get_bushandle(sc->dc_res); 1913 1914 /* Allocate interrupt. */ 1915 rid = 0; 1916 sc->dc_irq = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, 0, ~0, 1, 1917 RF_SHAREABLE | RF_ACTIVE); 1918 1919 if (sc->dc_irq == NULL) { 1920 printf("dc%d: couldn't map interrupt\n", unit); 1921 error = ENXIO; 1922 goto fail; 1923 } 1924 1925 /* Need this info to decide on a chip type. */ 1926 sc->dc_info = dc_devtype(dev); 1927 revision = pci_read_config(dev, DC_PCI_CFRV, 4) & 0x000000FF; 1928 1929 /* Get the eeprom width, but PNIC and XIRCOM have diff eeprom */ 1930 if (sc->dc_info->dc_did != DC_DEVICEID_82C168 && 1931 sc->dc_info->dc_did != DC_DEVICEID_X3201) 1932 dc_eeprom_width(sc); 1933 1934 switch (sc->dc_info->dc_did) { 1935 case DC_DEVICEID_21143: 1936 sc->dc_type = DC_TYPE_21143; 1937 sc->dc_flags |= DC_TX_POLL | DC_TX_USE_TX_INTR; 1938 sc->dc_flags |= DC_REDUCED_MII_POLL; 1939 /* Save EEPROM contents so we can parse them later. */ 1940 dc_read_srom(sc, sc->dc_romwidth); 1941 break; 1942 case DC_DEVICEID_DM9009: 1943 case DC_DEVICEID_DM9100: 1944 case DC_DEVICEID_DM9102: 1945 sc->dc_type = DC_TYPE_DM9102; 1946 sc->dc_flags |= DC_TX_COALESCE | DC_TX_INTR_ALWAYS; 1947 sc->dc_flags |= DC_REDUCED_MII_POLL | DC_TX_STORENFWD; 1948 sc->dc_flags |= DC_TX_ALIGN; 1949 sc->dc_pmode = DC_PMODE_MII; 1950 /* Increase the latency timer value. */ 1951 command = pci_read_config(dev, DC_PCI_CFLT, 4); 1952 command &= 0xFFFF00FF; 1953 command |= 0x00008000; 1954 pci_write_config(dev, DC_PCI_CFLT, command, 4); 1955 break; 1956 case DC_DEVICEID_AL981: 1957 sc->dc_type = DC_TYPE_AL981; 1958 sc->dc_flags |= DC_TX_USE_TX_INTR; 1959 sc->dc_flags |= DC_TX_ADMTEK_WAR; 1960 sc->dc_pmode = DC_PMODE_MII; 1961 dc_read_srom(sc, sc->dc_romwidth); 1962 break; 1963 case DC_DEVICEID_AN985: 1964 case DC_DEVICEID_ADM9511: 1965 case DC_DEVICEID_ADM9513: 1966 case DC_DEVICEID_FA511: 1967 case DC_DEVICEID_FE2500: 1968 case DC_DEVICEID_EN2242: 1969 case DC_DEVICEID_HAWKING_PN672TX: 1970 case DC_DEVICEID_3CSOHOB: 1971 case DC_DEVICEID_MSMN120: 1972 case DC_DEVICEID_MSMN130_FAKE: /* XXX avoid collision with PNIC*/ 1973 sc->dc_type = DC_TYPE_AN985; 1974 sc->dc_flags |= DC_64BIT_HASH; 1975 sc->dc_flags |= DC_TX_USE_TX_INTR; 1976 sc->dc_flags |= DC_TX_ADMTEK_WAR; 1977 sc->dc_pmode = DC_PMODE_MII; 1978 /* Don't read SROM for - auto-loaded on reset */ 1979 break; 1980 case DC_DEVICEID_98713: 1981 case DC_DEVICEID_98713_CP: 1982 if (revision < DC_REVISION_98713A) { 1983 sc->dc_type = DC_TYPE_98713; 1984 } 1985 if (revision >= DC_REVISION_98713A) { 1986 sc->dc_type = DC_TYPE_98713A; 1987 sc->dc_flags |= DC_21143_NWAY; 1988 } 1989 sc->dc_flags |= DC_REDUCED_MII_POLL; 1990 sc->dc_flags |= DC_TX_POLL | DC_TX_USE_TX_INTR; 1991 break; 1992 case DC_DEVICEID_987x5: 1993 case DC_DEVICEID_EN1217: 1994 /* 1995 * Macronix MX98715AEC-C/D/E parts have only a 1996 * 128-bit hash table. We need to deal with these 1997 * in the same manner as the PNIC II so that we 1998 * get the right number of bits out of the 1999 * CRC routine. 2000 */ 2001 if (revision >= DC_REVISION_98715AEC_C && 2002 revision < DC_REVISION_98725) 2003 sc->dc_flags |= DC_128BIT_HASH; 2004 sc->dc_type = DC_TYPE_987x5; 2005 sc->dc_flags |= DC_TX_POLL | DC_TX_USE_TX_INTR; 2006 sc->dc_flags |= DC_REDUCED_MII_POLL | DC_21143_NWAY; 2007 break; 2008 case DC_DEVICEID_98727: 2009 sc->dc_type = DC_TYPE_987x5; 2010 sc->dc_flags |= DC_TX_POLL | DC_TX_USE_TX_INTR; 2011 sc->dc_flags |= DC_REDUCED_MII_POLL | DC_21143_NWAY; 2012 break; 2013 case DC_DEVICEID_82C115: 2014 sc->dc_type = DC_TYPE_PNICII; 2015 sc->dc_flags |= DC_TX_POLL | DC_TX_USE_TX_INTR | DC_128BIT_HASH; 2016 sc->dc_flags |= DC_REDUCED_MII_POLL | DC_21143_NWAY; 2017 break; 2018 case DC_DEVICEID_82C168: 2019 sc->dc_type = DC_TYPE_PNIC; 2020 sc->dc_flags |= DC_TX_STORENFWD | DC_TX_INTR_ALWAYS; 2021 sc->dc_flags |= DC_PNIC_RX_BUG_WAR; 2022 sc->dc_pnic_rx_buf = malloc(DC_RXLEN * 5, M_DEVBUF, M_NOWAIT); 2023 if (revision < DC_REVISION_82C169) 2024 sc->dc_pmode = DC_PMODE_SYM; 2025 break; 2026 case DC_DEVICEID_AX88140A: 2027 sc->dc_type = DC_TYPE_ASIX; 2028 sc->dc_flags |= DC_TX_USE_TX_INTR | DC_TX_INTR_FIRSTFRAG; 2029 sc->dc_flags |= DC_REDUCED_MII_POLL; 2030 sc->dc_pmode = DC_PMODE_MII; 2031 break; 2032 case DC_DEVICEID_X3201: 2033 sc->dc_type = DC_TYPE_XIRCOM; 2034 sc->dc_flags |= DC_TX_INTR_ALWAYS | DC_TX_COALESCE | 2035 DC_TX_ALIGN; 2036 /* 2037 * We don't actually need to coalesce, but we're doing 2038 * it to obtain a double word aligned buffer. 2039 * The DC_TX_COALESCE flag is required. 2040 */ 2041 sc->dc_pmode = DC_PMODE_MII; 2042 break; 2043 case DC_DEVICEID_RS7112: 2044 sc->dc_type = DC_TYPE_CONEXANT; 2045 sc->dc_flags |= DC_TX_INTR_ALWAYS; 2046 sc->dc_flags |= DC_REDUCED_MII_POLL; 2047 sc->dc_pmode = DC_PMODE_MII; 2048 dc_read_srom(sc, sc->dc_romwidth); 2049 break; 2050 default: 2051 printf("dc%d: unknown device: %x\n", sc->dc_unit, 2052 sc->dc_info->dc_did); 2053 break; 2054 } 2055 2056 /* Save the cache line size. */ 2057 if (DC_IS_DAVICOM(sc)) 2058 sc->dc_cachesize = 0; 2059 else 2060 sc->dc_cachesize = pci_read_config(dev, 2061 DC_PCI_CFLT, 4) & 0xFF; 2062 2063 /* Reset the adapter. */ 2064 dc_reset(sc); 2065 2066 /* Take 21143 out of snooze mode */ 2067 if (DC_IS_INTEL(sc) || DC_IS_XIRCOM(sc)) { 2068 command = pci_read_config(dev, DC_PCI_CFDD, 4); 2069 command &= ~(DC_CFDD_SNOOZE_MODE | DC_CFDD_SLEEP_MODE); 2070 pci_write_config(dev, DC_PCI_CFDD, command, 4); 2071 } 2072 2073 /* 2074 * Try to learn something about the supported media. 2075 * We know that ASIX and ADMtek and Davicom devices 2076 * will *always* be using MII media, so that's a no-brainer. 2077 * The tricky ones are the Macronix/PNIC II and the 2078 * Intel 21143. 2079 */ 2080 if (DC_IS_INTEL(sc)) 2081 dc_parse_21143_srom(sc); 2082 else if (DC_IS_MACRONIX(sc) || DC_IS_PNICII(sc)) { 2083 if (sc->dc_type == DC_TYPE_98713) 2084 sc->dc_pmode = DC_PMODE_MII; 2085 else 2086 sc->dc_pmode = DC_PMODE_SYM; 2087 } else if (!sc->dc_pmode) 2088 sc->dc_pmode = DC_PMODE_MII; 2089 2090 /* 2091 * Get station address from the EEPROM. 2092 */ 2093 switch(sc->dc_type) { 2094 case DC_TYPE_98713: 2095 case DC_TYPE_98713A: 2096 case DC_TYPE_987x5: 2097 case DC_TYPE_PNICII: 2098 dc_read_eeprom(sc, (caddr_t)&mac_offset, 2099 (DC_EE_NODEADDR_OFFSET / 2), 1, 0); 2100 dc_read_eeprom(sc, (caddr_t)&eaddr, (mac_offset / 2), 3, 0); 2101 break; 2102 case DC_TYPE_PNIC: 2103 dc_read_eeprom(sc, (caddr_t)&eaddr, 0, 3, 1); 2104 break; 2105 case DC_TYPE_DM9102: 2106 case DC_TYPE_21143: 2107 case DC_TYPE_ASIX: 2108 dc_read_eeprom(sc, (caddr_t)&eaddr, DC_EE_NODEADDR, 3, 0); 2109 break; 2110 case DC_TYPE_AL981: 2111 case DC_TYPE_AN985: 2112 *(u_int32_t *)(&eaddr[0]) = CSR_READ_4(sc, DC_AL_PAR0); 2113 *(u_int16_t *)(&eaddr[4]) = CSR_READ_4(sc, DC_AL_PAR1); 2114 break; 2115 case DC_TYPE_CONEXANT: 2116 bcopy(sc->dc_srom + DC_CONEXANT_EE_NODEADDR, &eaddr, 2117 ETHER_ADDR_LEN); 2118 break; 2119 case DC_TYPE_XIRCOM: 2120 /* The MAC comes from the CIS. */ 2121 mac = pci_get_ether(dev); 2122 if (!mac) { 2123 device_printf(dev, "No station address in CIS!\n"); 2124 error = ENXIO; 2125 goto fail; 2126 } 2127 bcopy(mac, eaddr, ETHER_ADDR_LEN); 2128 break; 2129 default: 2130 dc_read_eeprom(sc, (caddr_t)&eaddr, DC_EE_NODEADDR, 3, 0); 2131 break; 2132 } 2133 2134 /* 2135 * A 21143 or clone chip was detected. Inform the world. 2136 */ 2137 printf("dc%d: Ethernet address: %6D\n", unit, eaddr, ":"); 2138 2139 sc->dc_unit = unit; 2140 bcopy(eaddr, &sc->arpcom.ac_enaddr, ETHER_ADDR_LEN); 2141 2142 /* Allocate a busdma tag and DMA safe memory for TX/RX descriptors. */ 2143 error = bus_dma_tag_create(NULL, PAGE_SIZE, 0, BUS_SPACE_MAXADDR_32BIT, 2144 BUS_SPACE_MAXADDR, NULL, NULL, sizeof(struct dc_list_data), 1, 2145 sizeof(struct dc_list_data), 0, NULL, NULL, &sc->dc_ltag); 2146 if (error) { 2147 printf("dc%d: failed to allocate busdma tag\n", unit); 2148 error = ENXIO; 2149 goto fail; 2150 } 2151 error = bus_dmamem_alloc(sc->dc_ltag, (void **)&sc->dc_ldata, 2152 BUS_DMA_NOWAIT | BUS_DMA_ZERO, &sc->dc_lmap); 2153 if (error) { 2154 printf("dc%d: failed to allocate DMA safe memory\n", unit); 2155 error = ENXIO; 2156 goto fail; 2157 } 2158 error = bus_dmamap_load(sc->dc_ltag, sc->dc_lmap, sc->dc_ldata, 2159 sizeof(struct dc_list_data), dc_dma_map_addr, &sc->dc_laddr, 2160 BUS_DMA_NOWAIT); 2161 if (error) { 2162 printf("dc%d: cannot get address of the descriptors\n", unit); 2163 error = ENXIO; 2164 goto fail; 2165 } 2166 2167 /* 2168 * Allocate a busdma tag and DMA safe memory for the multicast 2169 * setup frame. 2170 */ 2171 error = bus_dma_tag_create(NULL, PAGE_SIZE, 0, BUS_SPACE_MAXADDR_32BIT, 2172 BUS_SPACE_MAXADDR, NULL, NULL, DC_SFRAME_LEN + DC_MIN_FRAMELEN, 1, 2173 DC_SFRAME_LEN + DC_MIN_FRAMELEN, 0, NULL, NULL, &sc->dc_stag); 2174 if (error) { 2175 printf("dc%d: failed to allocate busdma tag\n", unit); 2176 error = ENXIO; 2177 goto fail; 2178 } 2179 error = bus_dmamem_alloc(sc->dc_stag, (void **)&sc->dc_cdata.dc_sbuf, 2180 BUS_DMA_NOWAIT, &sc->dc_smap); 2181 if (error) { 2182 printf("dc%d: failed to allocate DMA safe memory\n", unit); 2183 error = ENXIO; 2184 goto fail; 2185 } 2186 error = bus_dmamap_load(sc->dc_stag, sc->dc_smap, sc->dc_cdata.dc_sbuf, 2187 DC_SFRAME_LEN, dc_dma_map_addr, &sc->dc_saddr, BUS_DMA_NOWAIT); 2188 if (error) { 2189 printf("dc%d: cannot get address of the descriptors\n", unit); 2190 error = ENXIO; 2191 goto fail; 2192 } 2193 2194 /* Allocate a busdma tag for mbufs. */ 2195 error = bus_dma_tag_create(NULL, PAGE_SIZE, 0, BUS_SPACE_MAXADDR_32BIT, 2196 BUS_SPACE_MAXADDR, NULL, NULL, MCLBYTES * DC_TX_LIST_CNT, 2197 DC_TX_LIST_CNT, MCLBYTES, 0, NULL, NULL, &sc->dc_mtag); 2198 if (error) { 2199 printf("dc%d: failed to allocate busdma tag\n", unit); 2200 error = ENXIO; 2201 goto fail; 2202 } 2203 2204 /* Create the TX/RX busdma maps. */ 2205 for (i = 0; i < DC_TX_LIST_CNT; i++) { 2206 error = bus_dmamap_create(sc->dc_mtag, 0, 2207 &sc->dc_cdata.dc_tx_map[i]); 2208 if (error) { 2209 printf("dc%d: failed to init TX ring\n", unit); 2210 error = ENXIO; 2211 goto fail; 2212 } 2213 } 2214 for (i = 0; i < DC_RX_LIST_CNT; i++) { 2215 error = bus_dmamap_create(sc->dc_mtag, 0, 2216 &sc->dc_cdata.dc_rx_map[i]); 2217 if (error) { 2218 printf("dc%d: failed to init RX ring\n", unit); 2219 error = ENXIO; 2220 goto fail; 2221 } 2222 } 2223 error = bus_dmamap_create(sc->dc_mtag, 0, &sc->dc_sparemap); 2224 if (error) { 2225 printf("dc%d: failed to init RX ring\n", unit); 2226 error = ENXIO; 2227 goto fail; 2228 } 2229 2230 ifp = &sc->arpcom.ac_if; 2231 ifp->if_softc = sc; 2232 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 2233 /* XXX: bleah, MTU gets overwritten in ether_ifattach() */ 2234 ifp->if_mtu = ETHERMTU; 2235 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 2236 ifp->if_ioctl = dc_ioctl; 2237 ifp->if_start = dc_start; 2238 ifp->if_watchdog = dc_watchdog; 2239 ifp->if_init = dc_init; 2240 ifp->if_baudrate = 10000000; 2241 ifp->if_snd.ifq_maxlen = DC_TX_LIST_CNT - 1; 2242 2243 /* 2244 * Do MII setup. If this is a 21143, check for a PHY on the 2245 * MII bus after applying any necessary fixups to twiddle the 2246 * GPIO bits. If we don't end up finding a PHY, restore the 2247 * old selection (SIA only or SIA/SYM) and attach the dcphy 2248 * driver instead. 2249 */ 2250 if (DC_IS_INTEL(sc)) { 2251 dc_apply_fixup(sc, IFM_AUTO); 2252 tmp = sc->dc_pmode; 2253 sc->dc_pmode = DC_PMODE_MII; 2254 } 2255 2256 error = mii_phy_probe(dev, &sc->dc_miibus, 2257 dc_ifmedia_upd, dc_ifmedia_sts); 2258 2259 if (error && DC_IS_INTEL(sc)) { 2260 sc->dc_pmode = tmp; 2261 if (sc->dc_pmode != DC_PMODE_SIA) 2262 sc->dc_pmode = DC_PMODE_SYM; 2263 sc->dc_flags |= DC_21143_NWAY; 2264 mii_phy_probe(dev, &sc->dc_miibus, 2265 dc_ifmedia_upd, dc_ifmedia_sts); 2266 /* 2267 * For non-MII cards, we need to have the 21143 2268 * drive the LEDs. Except there are some systems 2269 * like the NEC VersaPro NoteBook PC which have no 2270 * LEDs, and twiddling these bits has adverse effects 2271 * on them. (I.e. you suddenly can't get a link.) 2272 */ 2273 if (pci_read_config(dev, DC_PCI_CSID, 4) != 0x80281033) 2274 sc->dc_flags |= DC_TULIP_LEDS; 2275 error = 0; 2276 } 2277 2278 if (error) { 2279 printf("dc%d: MII without any PHY!\n", sc->dc_unit); 2280 goto fail; 2281 } 2282 2283 if (DC_IS_XIRCOM(sc)) { 2284 /* 2285 * setup General Purpose Port mode and data so the tulip 2286 * can talk to the MII. 2287 */ 2288 CSR_WRITE_4(sc, DC_SIAGP, DC_SIAGP_WRITE_EN | DC_SIAGP_INT1_EN | 2289 DC_SIAGP_MD_GP2_OUTPUT | DC_SIAGP_MD_GP0_OUTPUT); 2290 DELAY(10); 2291 CSR_WRITE_4(sc, DC_SIAGP, DC_SIAGP_INT1_EN | 2292 DC_SIAGP_MD_GP2_OUTPUT | DC_SIAGP_MD_GP0_OUTPUT); 2293 DELAY(10); 2294 } 2295 2296 if (DC_IS_ADMTEK(sc)) { 2297 /* 2298 * Set automatic TX underrun recovery for the ADMtek chips 2299 */ 2300 DC_SETBIT(sc, DC_AL_CR, DC_AL_CR_ATUR); 2301 } 2302 2303 /* 2304 * Tell the upper layer(s) we support long frames. 2305 */ 2306 ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header); 2307 ifp->if_capabilities |= IFCAP_VLAN_MTU; 2308 2309 callout_init(&sc->dc_stat_ch, IS_MPSAFE ? CALLOUT_MPSAFE : 0); 2310 2311 #ifdef SRM_MEDIA 2312 sc->dc_srm_media = 0; 2313 2314 /* Remember the SRM console media setting */ 2315 if (DC_IS_INTEL(sc)) { 2316 command = pci_read_config(dev, DC_PCI_CFDD, 4); 2317 command &= ~(DC_CFDD_SNOOZE_MODE | DC_CFDD_SLEEP_MODE); 2318 switch ((command >> 8) & 0xff) { 2319 case 3: 2320 sc->dc_srm_media = IFM_10_T; 2321 break; 2322 case 4: 2323 sc->dc_srm_media = IFM_10_T | IFM_FDX; 2324 break; 2325 case 5: 2326 sc->dc_srm_media = IFM_100_TX; 2327 break; 2328 case 6: 2329 sc->dc_srm_media = IFM_100_TX | IFM_FDX; 2330 break; 2331 } 2332 if (sc->dc_srm_media) 2333 sc->dc_srm_media |= IFM_ACTIVE | IFM_ETHER; 2334 } 2335 #endif 2336 2337 /* 2338 * Call MI attach routine. 2339 */ 2340 ether_ifattach(ifp, eaddr); 2341 2342 /* Hook interrupt last to avoid having to lock softc */ 2343 error = bus_setup_intr(dev, sc->dc_irq, INTR_TYPE_NET | 2344 (IS_MPSAFE ? INTR_MPSAFE : 0), 2345 dc_intr, sc, &sc->dc_intrhand); 2346 2347 if (error) { 2348 printf("dc%d: couldn't set up irq\n", unit); 2349 ether_ifdetach(ifp); 2350 goto fail; 2351 } 2352 2353 fail: 2354 if (error) 2355 dc_detach(dev); 2356 return (error); 2357 } 2358 2359 /* 2360 * Shutdown hardware and free up resources. This can be called any 2361 * time after the mutex has been initialized. It is called in both 2362 * the error case in attach and the normal detach case so it needs 2363 * to be careful about only freeing resources that have actually been 2364 * allocated. 2365 */ 2366 static int 2367 dc_detach(device_t dev) 2368 { 2369 struct dc_softc *sc; 2370 struct ifnet *ifp; 2371 struct dc_mediainfo *m; 2372 int i; 2373 2374 sc = device_get_softc(dev); 2375 KASSERT(mtx_initialized(&sc->dc_mtx), ("dc mutex not initialized")); 2376 DC_LOCK(sc); 2377 2378 ifp = &sc->arpcom.ac_if; 2379 2380 /* These should only be active if attach succeeded */ 2381 if (device_is_attached(dev)) { 2382 dc_stop(sc); 2383 ether_ifdetach(ifp); 2384 } 2385 if (sc->dc_miibus) 2386 device_delete_child(dev, sc->dc_miibus); 2387 bus_generic_detach(dev); 2388 2389 if (sc->dc_intrhand) 2390 bus_teardown_intr(dev, sc->dc_irq, sc->dc_intrhand); 2391 if (sc->dc_irq) 2392 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->dc_irq); 2393 if (sc->dc_res) 2394 bus_release_resource(dev, DC_RES, DC_RID, sc->dc_res); 2395 2396 if (sc->dc_cdata.dc_sbuf != NULL) 2397 bus_dmamem_free(sc->dc_stag, sc->dc_cdata.dc_sbuf, sc->dc_smap); 2398 if (sc->dc_ldata != NULL) 2399 bus_dmamem_free(sc->dc_ltag, sc->dc_ldata, sc->dc_lmap); 2400 for (i = 0; i < DC_TX_LIST_CNT; i++) 2401 bus_dmamap_destroy(sc->dc_mtag, sc->dc_cdata.dc_tx_map[i]); 2402 for (i = 0; i < DC_RX_LIST_CNT; i++) 2403 bus_dmamap_destroy(sc->dc_mtag, sc->dc_cdata.dc_rx_map[i]); 2404 bus_dmamap_destroy(sc->dc_mtag, sc->dc_sparemap); 2405 if (sc->dc_stag) 2406 bus_dma_tag_destroy(sc->dc_stag); 2407 if (sc->dc_mtag) 2408 bus_dma_tag_destroy(sc->dc_mtag); 2409 if (sc->dc_ltag) 2410 bus_dma_tag_destroy(sc->dc_ltag); 2411 2412 free(sc->dc_pnic_rx_buf, M_DEVBUF); 2413 2414 while (sc->dc_mi != NULL) { 2415 m = sc->dc_mi->dc_next; 2416 free(sc->dc_mi, M_DEVBUF); 2417 sc->dc_mi = m; 2418 } 2419 free(sc->dc_srom, M_DEVBUF); 2420 2421 DC_UNLOCK(sc); 2422 mtx_destroy(&sc->dc_mtx); 2423 2424 return (0); 2425 } 2426 2427 /* 2428 * Initialize the transmit descriptors. 2429 */ 2430 static int 2431 dc_list_tx_init(struct dc_softc *sc) 2432 { 2433 struct dc_chain_data *cd; 2434 struct dc_list_data *ld; 2435 int i, nexti; 2436 2437 cd = &sc->dc_cdata; 2438 ld = sc->dc_ldata; 2439 for (i = 0; i < DC_TX_LIST_CNT; i++) { 2440 if (i == DC_TX_LIST_CNT - 1) 2441 nexti = 0; 2442 else 2443 nexti = i + 1; 2444 ld->dc_tx_list[i].dc_next = htole32(DC_TXDESC(sc, nexti)); 2445 cd->dc_tx_chain[i] = NULL; 2446 ld->dc_tx_list[i].dc_data = 0; 2447 ld->dc_tx_list[i].dc_ctl = 0; 2448 } 2449 2450 cd->dc_tx_prod = cd->dc_tx_cons = cd->dc_tx_cnt = 0; 2451 bus_dmamap_sync(sc->dc_ltag, sc->dc_lmap, 2452 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2453 return (0); 2454 } 2455 2456 2457 /* 2458 * Initialize the RX descriptors and allocate mbufs for them. Note that 2459 * we arrange the descriptors in a closed ring, so that the last descriptor 2460 * points back to the first. 2461 */ 2462 static int 2463 dc_list_rx_init(struct dc_softc *sc) 2464 { 2465 struct dc_chain_data *cd; 2466 struct dc_list_data *ld; 2467 int i, nexti; 2468 2469 cd = &sc->dc_cdata; 2470 ld = sc->dc_ldata; 2471 2472 for (i = 0; i < DC_RX_LIST_CNT; i++) { 2473 if (dc_newbuf(sc, i, 1) != 0) 2474 return (ENOBUFS); 2475 if (i == DC_RX_LIST_CNT - 1) 2476 nexti = 0; 2477 else 2478 nexti = i + 1; 2479 ld->dc_rx_list[i].dc_next = htole32(DC_RXDESC(sc, nexti)); 2480 } 2481 2482 cd->dc_rx_prod = 0; 2483 bus_dmamap_sync(sc->dc_ltag, sc->dc_lmap, 2484 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2485 return (0); 2486 } 2487 2488 static void 2489 dc_dma_map_rxbuf(arg, segs, nseg, mapsize, error) 2490 void *arg; 2491 bus_dma_segment_t *segs; 2492 int nseg; 2493 bus_size_t mapsize; 2494 int error; 2495 { 2496 struct dc_softc *sc; 2497 struct dc_desc *c; 2498 2499 sc = arg; 2500 c = &sc->dc_ldata->dc_rx_list[sc->dc_cdata.dc_rx_cur]; 2501 if (error) { 2502 sc->dc_cdata.dc_rx_err = error; 2503 return; 2504 } 2505 2506 KASSERT(nseg == 1, ("wrong number of segments, should be 1")); 2507 sc->dc_cdata.dc_rx_err = 0; 2508 c->dc_data = htole32(segs->ds_addr); 2509 } 2510 2511 /* 2512 * Initialize an RX descriptor and attach an MBUF cluster. 2513 */ 2514 static int 2515 dc_newbuf(struct dc_softc *sc, int i, int alloc) 2516 { 2517 struct mbuf *m_new; 2518 bus_dmamap_t tmp; 2519 int error; 2520 2521 if (alloc) { 2522 m_new = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR); 2523 if (m_new == NULL) 2524 return (ENOBUFS); 2525 } else { 2526 m_new = sc->dc_cdata.dc_rx_chain[i]; 2527 m_new->m_data = m_new->m_ext.ext_buf; 2528 } 2529 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 2530 m_adj(m_new, sizeof(u_int64_t)); 2531 2532 /* 2533 * If this is a PNIC chip, zero the buffer. This is part 2534 * of the workaround for the receive bug in the 82c168 and 2535 * 82c169 chips. 2536 */ 2537 if (sc->dc_flags & DC_PNIC_RX_BUG_WAR) 2538 bzero(mtod(m_new, char *), m_new->m_len); 2539 2540 /* No need to remap the mbuf if we're reusing it. */ 2541 if (alloc) { 2542 sc->dc_cdata.dc_rx_cur = i; 2543 error = bus_dmamap_load_mbuf(sc->dc_mtag, sc->dc_sparemap, 2544 m_new, dc_dma_map_rxbuf, sc, 0); 2545 if (error) { 2546 m_freem(m_new); 2547 return (error); 2548 } 2549 if (sc->dc_cdata.dc_rx_err != 0) { 2550 m_freem(m_new); 2551 return (sc->dc_cdata.dc_rx_err); 2552 } 2553 bus_dmamap_unload(sc->dc_mtag, sc->dc_cdata.dc_rx_map[i]); 2554 tmp = sc->dc_cdata.dc_rx_map[i]; 2555 sc->dc_cdata.dc_rx_map[i] = sc->dc_sparemap; 2556 sc->dc_sparemap = tmp; 2557 sc->dc_cdata.dc_rx_chain[i] = m_new; 2558 } 2559 2560 sc->dc_ldata->dc_rx_list[i].dc_ctl = htole32(DC_RXCTL_RLINK | DC_RXLEN); 2561 sc->dc_ldata->dc_rx_list[i].dc_status = htole32(DC_RXSTAT_OWN); 2562 bus_dmamap_sync(sc->dc_mtag, sc->dc_cdata.dc_rx_map[i], 2563 BUS_DMASYNC_PREREAD); 2564 bus_dmamap_sync(sc->dc_ltag, sc->dc_lmap, 2565 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2566 return (0); 2567 } 2568 2569 /* 2570 * Grrrrr. 2571 * The PNIC chip has a terrible bug in it that manifests itself during 2572 * periods of heavy activity. The exact mode of failure if difficult to 2573 * pinpoint: sometimes it only happens in promiscuous mode, sometimes it 2574 * will happen on slow machines. The bug is that sometimes instead of 2575 * uploading one complete frame during reception, it uploads what looks 2576 * like the entire contents of its FIFO memory. The frame we want is at 2577 * the end of the whole mess, but we never know exactly how much data has 2578 * been uploaded, so salvaging the frame is hard. 2579 * 2580 * There is only one way to do it reliably, and it's disgusting. 2581 * Here's what we know: 2582 * 2583 * - We know there will always be somewhere between one and three extra 2584 * descriptors uploaded. 2585 * 2586 * - We know the desired received frame will always be at the end of the 2587 * total data upload. 2588 * 2589 * - We know the size of the desired received frame because it will be 2590 * provided in the length field of the status word in the last descriptor. 2591 * 2592 * Here's what we do: 2593 * 2594 * - When we allocate buffers for the receive ring, we bzero() them. 2595 * This means that we know that the buffer contents should be all 2596 * zeros, except for data uploaded by the chip. 2597 * 2598 * - We also force the PNIC chip to upload frames that include the 2599 * ethernet CRC at the end. 2600 * 2601 * - We gather all of the bogus frame data into a single buffer. 2602 * 2603 * - We then position a pointer at the end of this buffer and scan 2604 * backwards until we encounter the first non-zero byte of data. 2605 * This is the end of the received frame. We know we will encounter 2606 * some data at the end of the frame because the CRC will always be 2607 * there, so even if the sender transmits a packet of all zeros, 2608 * we won't be fooled. 2609 * 2610 * - We know the size of the actual received frame, so we subtract 2611 * that value from the current pointer location. This brings us 2612 * to the start of the actual received packet. 2613 * 2614 * - We copy this into an mbuf and pass it on, along with the actual 2615 * frame length. 2616 * 2617 * The performance hit is tremendous, but it beats dropping frames all 2618 * the time. 2619 */ 2620 2621 #define DC_WHOLEFRAME (DC_RXSTAT_FIRSTFRAG | DC_RXSTAT_LASTFRAG) 2622 static void 2623 dc_pnic_rx_bug_war(struct dc_softc *sc, int idx) 2624 { 2625 struct dc_desc *cur_rx; 2626 struct dc_desc *c = NULL; 2627 struct mbuf *m = NULL; 2628 unsigned char *ptr; 2629 int i, total_len; 2630 u_int32_t rxstat = 0; 2631 2632 i = sc->dc_pnic_rx_bug_save; 2633 cur_rx = &sc->dc_ldata->dc_rx_list[idx]; 2634 ptr = sc->dc_pnic_rx_buf; 2635 bzero(ptr, DC_RXLEN * 5); 2636 2637 /* Copy all the bytes from the bogus buffers. */ 2638 while (1) { 2639 c = &sc->dc_ldata->dc_rx_list[i]; 2640 rxstat = le32toh(c->dc_status); 2641 m = sc->dc_cdata.dc_rx_chain[i]; 2642 bcopy(mtod(m, char *), ptr, DC_RXLEN); 2643 ptr += DC_RXLEN; 2644 /* If this is the last buffer, break out. */ 2645 if (i == idx || rxstat & DC_RXSTAT_LASTFRAG) 2646 break; 2647 dc_newbuf(sc, i, 0); 2648 DC_INC(i, DC_RX_LIST_CNT); 2649 } 2650 2651 /* Find the length of the actual receive frame. */ 2652 total_len = DC_RXBYTES(rxstat); 2653 2654 /* Scan backwards until we hit a non-zero byte. */ 2655 while (*ptr == 0x00) 2656 ptr--; 2657 2658 /* Round off. */ 2659 if ((uintptr_t)(ptr) & 0x3) 2660 ptr -= 1; 2661 2662 /* Now find the start of the frame. */ 2663 ptr -= total_len; 2664 if (ptr < sc->dc_pnic_rx_buf) 2665 ptr = sc->dc_pnic_rx_buf; 2666 2667 /* 2668 * Now copy the salvaged frame to the last mbuf and fake up 2669 * the status word to make it look like a successful 2670 * frame reception. 2671 */ 2672 dc_newbuf(sc, i, 0); 2673 bcopy(ptr, mtod(m, char *), total_len); 2674 cur_rx->dc_status = htole32(rxstat | DC_RXSTAT_FIRSTFRAG); 2675 } 2676 2677 /* 2678 * This routine searches the RX ring for dirty descriptors in the 2679 * event that the rxeof routine falls out of sync with the chip's 2680 * current descriptor pointer. This may happen sometimes as a result 2681 * of a "no RX buffer available" condition that happens when the chip 2682 * consumes all of the RX buffers before the driver has a chance to 2683 * process the RX ring. This routine may need to be called more than 2684 * once to bring the driver back in sync with the chip, however we 2685 * should still be getting RX DONE interrupts to drive the search 2686 * for new packets in the RX ring, so we should catch up eventually. 2687 */ 2688 static int 2689 dc_rx_resync(struct dc_softc *sc) 2690 { 2691 struct dc_desc *cur_rx; 2692 int i, pos; 2693 2694 pos = sc->dc_cdata.dc_rx_prod; 2695 2696 for (i = 0; i < DC_RX_LIST_CNT; i++) { 2697 cur_rx = &sc->dc_ldata->dc_rx_list[pos]; 2698 if (!(le32toh(cur_rx->dc_status) & DC_RXSTAT_OWN)) 2699 break; 2700 DC_INC(pos, DC_RX_LIST_CNT); 2701 } 2702 2703 /* If the ring really is empty, then just return. */ 2704 if (i == DC_RX_LIST_CNT) 2705 return (0); 2706 2707 /* We've fallen behing the chip: catch it. */ 2708 sc->dc_cdata.dc_rx_prod = pos; 2709 2710 return (EAGAIN); 2711 } 2712 2713 /* 2714 * A frame has been uploaded: pass the resulting mbuf chain up to 2715 * the higher level protocols. 2716 */ 2717 static void 2718 dc_rxeof(struct dc_softc *sc) 2719 { 2720 struct mbuf *m; 2721 struct ifnet *ifp; 2722 struct dc_desc *cur_rx; 2723 int i, total_len = 0; 2724 u_int32_t rxstat; 2725 2726 DC_LOCK_ASSERT(sc); 2727 2728 ifp = &sc->arpcom.ac_if; 2729 i = sc->dc_cdata.dc_rx_prod; 2730 2731 bus_dmamap_sync(sc->dc_ltag, sc->dc_lmap, BUS_DMASYNC_POSTREAD); 2732 while (!(le32toh(sc->dc_ldata->dc_rx_list[i].dc_status) & 2733 DC_RXSTAT_OWN)) { 2734 #ifdef DEVICE_POLLING 2735 if (ifp->if_flags & IFF_POLLING) { 2736 if (sc->rxcycles <= 0) 2737 break; 2738 sc->rxcycles--; 2739 } 2740 #endif 2741 cur_rx = &sc->dc_ldata->dc_rx_list[i]; 2742 rxstat = le32toh(cur_rx->dc_status); 2743 m = sc->dc_cdata.dc_rx_chain[i]; 2744 bus_dmamap_sync(sc->dc_mtag, sc->dc_cdata.dc_rx_map[i], 2745 BUS_DMASYNC_POSTREAD); 2746 total_len = DC_RXBYTES(rxstat); 2747 2748 if (sc->dc_flags & DC_PNIC_RX_BUG_WAR) { 2749 if ((rxstat & DC_WHOLEFRAME) != DC_WHOLEFRAME) { 2750 if (rxstat & DC_RXSTAT_FIRSTFRAG) 2751 sc->dc_pnic_rx_bug_save = i; 2752 if ((rxstat & DC_RXSTAT_LASTFRAG) == 0) { 2753 DC_INC(i, DC_RX_LIST_CNT); 2754 continue; 2755 } 2756 dc_pnic_rx_bug_war(sc, i); 2757 rxstat = le32toh(cur_rx->dc_status); 2758 total_len = DC_RXBYTES(rxstat); 2759 } 2760 } 2761 2762 /* 2763 * If an error occurs, update stats, clear the 2764 * status word and leave the mbuf cluster in place: 2765 * it should simply get re-used next time this descriptor 2766 * comes up in the ring. However, don't report long 2767 * frames as errors since they could be vlans. 2768 */ 2769 if ((rxstat & DC_RXSTAT_RXERR)) { 2770 if (!(rxstat & DC_RXSTAT_GIANT) || 2771 (rxstat & (DC_RXSTAT_CRCERR | DC_RXSTAT_DRIBBLE | 2772 DC_RXSTAT_MIIERE | DC_RXSTAT_COLLSEEN | 2773 DC_RXSTAT_RUNT | DC_RXSTAT_DE))) { 2774 ifp->if_ierrors++; 2775 if (rxstat & DC_RXSTAT_COLLSEEN) 2776 ifp->if_collisions++; 2777 dc_newbuf(sc, i, 0); 2778 if (rxstat & DC_RXSTAT_CRCERR) { 2779 DC_INC(i, DC_RX_LIST_CNT); 2780 continue; 2781 } else { 2782 dc_init(sc); 2783 return; 2784 } 2785 } 2786 } 2787 2788 /* No errors; receive the packet. */ 2789 total_len -= ETHER_CRC_LEN; 2790 #ifdef __i386__ 2791 /* 2792 * On the x86 we do not have alignment problems, so try to 2793 * allocate a new buffer for the receive ring, and pass up 2794 * the one where the packet is already, saving the expensive 2795 * copy done in m_devget(). 2796 * If we are on an architecture with alignment problems, or 2797 * if the allocation fails, then use m_devget and leave the 2798 * existing buffer in the receive ring. 2799 */ 2800 if (dc_quick && dc_newbuf(sc, i, 1) == 0) { 2801 m->m_pkthdr.rcvif = ifp; 2802 m->m_pkthdr.len = m->m_len = total_len; 2803 DC_INC(i, DC_RX_LIST_CNT); 2804 } else 2805 #endif 2806 { 2807 struct mbuf *m0; 2808 2809 m0 = m_devget(mtod(m, char *), total_len, 2810 ETHER_ALIGN, ifp, NULL); 2811 dc_newbuf(sc, i, 0); 2812 DC_INC(i, DC_RX_LIST_CNT); 2813 if (m0 == NULL) { 2814 ifp->if_ierrors++; 2815 continue; 2816 } 2817 m = m0; 2818 } 2819 2820 ifp->if_ipackets++; 2821 DC_UNLOCK(sc); 2822 (*ifp->if_input)(ifp, m); 2823 DC_LOCK(sc); 2824 } 2825 2826 sc->dc_cdata.dc_rx_prod = i; 2827 } 2828 2829 /* 2830 * A frame was downloaded to the chip. It's safe for us to clean up 2831 * the list buffers. 2832 */ 2833 2834 static void 2835 dc_txeof(struct dc_softc *sc) 2836 { 2837 struct dc_desc *cur_tx = NULL; 2838 struct ifnet *ifp; 2839 int idx; 2840 u_int32_t ctl, txstat; 2841 2842 ifp = &sc->arpcom.ac_if; 2843 2844 /* 2845 * Go through our tx list and free mbufs for those 2846 * frames that have been transmitted. 2847 */ 2848 bus_dmamap_sync(sc->dc_ltag, sc->dc_lmap, BUS_DMASYNC_POSTREAD); 2849 idx = sc->dc_cdata.dc_tx_cons; 2850 while (idx != sc->dc_cdata.dc_tx_prod) { 2851 2852 cur_tx = &sc->dc_ldata->dc_tx_list[idx]; 2853 txstat = le32toh(cur_tx->dc_status); 2854 ctl = le32toh(cur_tx->dc_ctl); 2855 2856 if (txstat & DC_TXSTAT_OWN) 2857 break; 2858 2859 if (!(ctl & DC_TXCTL_FIRSTFRAG) || ctl & DC_TXCTL_SETUP) { 2860 if (ctl & DC_TXCTL_SETUP) { 2861 /* 2862 * Yes, the PNIC is so brain damaged 2863 * that it will sometimes generate a TX 2864 * underrun error while DMAing the RX 2865 * filter setup frame. If we detect this, 2866 * we have to send the setup frame again, 2867 * or else the filter won't be programmed 2868 * correctly. 2869 */ 2870 if (DC_IS_PNIC(sc)) { 2871 if (txstat & DC_TXSTAT_ERRSUM) 2872 dc_setfilt(sc); 2873 } 2874 sc->dc_cdata.dc_tx_chain[idx] = NULL; 2875 } 2876 sc->dc_cdata.dc_tx_cnt--; 2877 DC_INC(idx, DC_TX_LIST_CNT); 2878 continue; 2879 } 2880 2881 if (DC_IS_XIRCOM(sc) || DC_IS_CONEXANT(sc)) { 2882 /* 2883 * XXX: Why does my Xircom taunt me so? 2884 * For some reason it likes setting the CARRLOST flag 2885 * even when the carrier is there. wtf?!? 2886 * Who knows, but Conexant chips have the 2887 * same problem. Maybe they took lessons 2888 * from Xircom. 2889 */ 2890 if (/*sc->dc_type == DC_TYPE_21143 &&*/ 2891 sc->dc_pmode == DC_PMODE_MII && 2892 ((txstat & 0xFFFF) & ~(DC_TXSTAT_ERRSUM | 2893 DC_TXSTAT_NOCARRIER))) 2894 txstat &= ~DC_TXSTAT_ERRSUM; 2895 } else { 2896 if (/*sc->dc_type == DC_TYPE_21143 &&*/ 2897 sc->dc_pmode == DC_PMODE_MII && 2898 ((txstat & 0xFFFF) & ~(DC_TXSTAT_ERRSUM | 2899 DC_TXSTAT_NOCARRIER | DC_TXSTAT_CARRLOST))) 2900 txstat &= ~DC_TXSTAT_ERRSUM; 2901 } 2902 2903 if (txstat & DC_TXSTAT_ERRSUM) { 2904 ifp->if_oerrors++; 2905 if (txstat & DC_TXSTAT_EXCESSCOLL) 2906 ifp->if_collisions++; 2907 if (txstat & DC_TXSTAT_LATECOLL) 2908 ifp->if_collisions++; 2909 if (!(txstat & DC_TXSTAT_UNDERRUN)) { 2910 dc_init(sc); 2911 return; 2912 } 2913 } 2914 2915 ifp->if_collisions += (txstat & DC_TXSTAT_COLLCNT) >> 3; 2916 2917 ifp->if_opackets++; 2918 if (sc->dc_cdata.dc_tx_chain[idx] != NULL) { 2919 bus_dmamap_sync(sc->dc_mtag, 2920 sc->dc_cdata.dc_tx_map[idx], 2921 BUS_DMASYNC_POSTWRITE); 2922 bus_dmamap_unload(sc->dc_mtag, 2923 sc->dc_cdata.dc_tx_map[idx]); 2924 m_freem(sc->dc_cdata.dc_tx_chain[idx]); 2925 sc->dc_cdata.dc_tx_chain[idx] = NULL; 2926 } 2927 2928 sc->dc_cdata.dc_tx_cnt--; 2929 DC_INC(idx, DC_TX_LIST_CNT); 2930 } 2931 2932 if (idx != sc->dc_cdata.dc_tx_cons) { 2933 /* Some buffers have been freed. */ 2934 sc->dc_cdata.dc_tx_cons = idx; 2935 ifp->if_flags &= ~IFF_OACTIVE; 2936 } 2937 ifp->if_timer = (sc->dc_cdata.dc_tx_cnt == 0) ? 0 : 5; 2938 } 2939 2940 static void 2941 dc_tick(void *xsc) 2942 { 2943 struct dc_softc *sc; 2944 struct mii_data *mii; 2945 struct ifnet *ifp; 2946 u_int32_t r; 2947 2948 sc = xsc; 2949 DC_LOCK(sc); 2950 ifp = &sc->arpcom.ac_if; 2951 mii = device_get_softc(sc->dc_miibus); 2952 2953 if (sc->dc_flags & DC_REDUCED_MII_POLL) { 2954 if (sc->dc_flags & DC_21143_NWAY) { 2955 r = CSR_READ_4(sc, DC_10BTSTAT); 2956 if (IFM_SUBTYPE(mii->mii_media_active) == 2957 IFM_100_TX && (r & DC_TSTAT_LS100)) { 2958 sc->dc_link = 0; 2959 mii_mediachg(mii); 2960 } 2961 if (IFM_SUBTYPE(mii->mii_media_active) == 2962 IFM_10_T && (r & DC_TSTAT_LS10)) { 2963 sc->dc_link = 0; 2964 mii_mediachg(mii); 2965 } 2966 if (sc->dc_link == 0) 2967 mii_tick(mii); 2968 } else { 2969 r = CSR_READ_4(sc, DC_ISR); 2970 if ((r & DC_ISR_RX_STATE) == DC_RXSTATE_WAIT && 2971 sc->dc_cdata.dc_tx_cnt == 0) { 2972 mii_tick(mii); 2973 if (!(mii->mii_media_status & IFM_ACTIVE)) 2974 sc->dc_link = 0; 2975 } 2976 } 2977 } else 2978 mii_tick(mii); 2979 2980 /* 2981 * When the init routine completes, we expect to be able to send 2982 * packets right away, and in fact the network code will send a 2983 * gratuitous ARP the moment the init routine marks the interface 2984 * as running. However, even though the MAC may have been initialized, 2985 * there may be a delay of a few seconds before the PHY completes 2986 * autonegotiation and the link is brought up. Any transmissions 2987 * made during that delay will be lost. Dealing with this is tricky: 2988 * we can't just pause in the init routine while waiting for the 2989 * PHY to come ready since that would bring the whole system to 2990 * a screeching halt for several seconds. 2991 * 2992 * What we do here is prevent the TX start routine from sending 2993 * any packets until a link has been established. After the 2994 * interface has been initialized, the tick routine will poll 2995 * the state of the PHY until the IFM_ACTIVE flag is set. Until 2996 * that time, packets will stay in the send queue, and once the 2997 * link comes up, they will be flushed out to the wire. 2998 */ 2999 if (!sc->dc_link && mii->mii_media_status & IFM_ACTIVE && 3000 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) { 3001 sc->dc_link++; 3002 if (ifp->if_snd.ifq_head != NULL) 3003 dc_start(ifp); 3004 } 3005 3006 if (sc->dc_flags & DC_21143_NWAY && !sc->dc_link) 3007 callout_reset(&sc->dc_stat_ch, hz/10, dc_tick, sc); 3008 else 3009 callout_reset(&sc->dc_stat_ch, hz, dc_tick, sc); 3010 3011 DC_UNLOCK(sc); 3012 } 3013 3014 /* 3015 * A transmit underrun has occurred. Back off the transmit threshold, 3016 * or switch to store and forward mode if we have to. 3017 */ 3018 static void 3019 dc_tx_underrun(struct dc_softc *sc) 3020 { 3021 u_int32_t isr; 3022 int i; 3023 3024 if (DC_IS_DAVICOM(sc)) 3025 dc_init(sc); 3026 3027 if (DC_IS_INTEL(sc)) { 3028 /* 3029 * The real 21143 requires that the transmitter be idle 3030 * in order to change the transmit threshold or store 3031 * and forward state. 3032 */ 3033 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_TX_ON); 3034 3035 for (i = 0; i < DC_TIMEOUT; i++) { 3036 isr = CSR_READ_4(sc, DC_ISR); 3037 if (isr & DC_ISR_TX_IDLE) 3038 break; 3039 DELAY(10); 3040 } 3041 if (i == DC_TIMEOUT) { 3042 printf("dc%d: failed to force tx to idle state\n", 3043 sc->dc_unit); 3044 dc_init(sc); 3045 } 3046 } 3047 3048 printf("dc%d: TX underrun -- ", sc->dc_unit); 3049 sc->dc_txthresh += DC_TXTHRESH_INC; 3050 if (sc->dc_txthresh > DC_TXTHRESH_MAX) { 3051 printf("using store and forward mode\n"); 3052 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_STORENFWD); 3053 } else { 3054 printf("increasing TX threshold\n"); 3055 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_TX_THRESH); 3056 DC_SETBIT(sc, DC_NETCFG, sc->dc_txthresh); 3057 } 3058 3059 if (DC_IS_INTEL(sc)) 3060 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_TX_ON); 3061 } 3062 3063 #ifdef DEVICE_POLLING 3064 static poll_handler_t dc_poll; 3065 3066 static void 3067 dc_poll(struct ifnet *ifp, enum poll_cmd cmd, int count) 3068 { 3069 struct dc_softc *sc = ifp->if_softc; 3070 3071 if (cmd == POLL_DEREGISTER) { /* final call, enable interrupts */ 3072 /* Re-enable interrupts. */ 3073 CSR_WRITE_4(sc, DC_IMR, DC_INTRS); 3074 return; 3075 } 3076 DC_LOCK(sc); 3077 sc->rxcycles = count; 3078 dc_rxeof(sc); 3079 dc_txeof(sc); 3080 if (ifp->if_snd.ifq_head != NULL && !(ifp->if_flags & IFF_OACTIVE)) 3081 dc_start(ifp); 3082 3083 if (cmd == POLL_AND_CHECK_STATUS) { /* also check status register */ 3084 u_int32_t status; 3085 3086 status = CSR_READ_4(sc, DC_ISR); 3087 status &= (DC_ISR_RX_WATDOGTIMEO | DC_ISR_RX_NOBUF | 3088 DC_ISR_TX_NOBUF | DC_ISR_TX_IDLE | DC_ISR_TX_UNDERRUN | 3089 DC_ISR_BUS_ERR); 3090 if (!status) { 3091 DC_UNLOCK(sc); 3092 return; 3093 } 3094 /* ack what we have */ 3095 CSR_WRITE_4(sc, DC_ISR, status); 3096 3097 if (status & (DC_ISR_RX_WATDOGTIMEO | DC_ISR_RX_NOBUF)) { 3098 u_int32_t r = CSR_READ_4(sc, DC_FRAMESDISCARDED); 3099 ifp->if_ierrors += (r & 0xffff) + ((r >> 17) & 0x7ff); 3100 3101 if (dc_rx_resync(sc)) 3102 dc_rxeof(sc); 3103 } 3104 /* restart transmit unit if necessary */ 3105 if (status & DC_ISR_TX_IDLE && sc->dc_cdata.dc_tx_cnt) 3106 CSR_WRITE_4(sc, DC_TXSTART, 0xFFFFFFFF); 3107 3108 if (status & DC_ISR_TX_UNDERRUN) 3109 dc_tx_underrun(sc); 3110 3111 if (status & DC_ISR_BUS_ERR) { 3112 printf("dc_poll: dc%d bus error\n", sc->dc_unit); 3113 dc_reset(sc); 3114 dc_init(sc); 3115 } 3116 } 3117 DC_UNLOCK(sc); 3118 } 3119 #endif /* DEVICE_POLLING */ 3120 3121 static void 3122 dc_intr(void *arg) 3123 { 3124 struct dc_softc *sc; 3125 struct ifnet *ifp; 3126 u_int32_t status; 3127 3128 sc = arg; 3129 3130 if (sc->suspended) 3131 return; 3132 3133 if ((CSR_READ_4(sc, DC_ISR) & DC_INTRS) == 0) 3134 return; 3135 3136 DC_LOCK(sc); 3137 ifp = &sc->arpcom.ac_if; 3138 #ifdef DEVICE_POLLING 3139 if (ifp->if_flags & IFF_POLLING) 3140 goto done; 3141 if (ether_poll_register(dc_poll, ifp)) { /* ok, disable interrupts */ 3142 CSR_WRITE_4(sc, DC_IMR, 0x00000000); 3143 goto done; 3144 } 3145 #endif 3146 3147 /* Suppress unwanted interrupts */ 3148 if (!(ifp->if_flags & IFF_UP)) { 3149 if (CSR_READ_4(sc, DC_ISR) & DC_INTRS) 3150 dc_stop(sc); 3151 DC_UNLOCK(sc); 3152 return; 3153 } 3154 3155 /* Disable interrupts. */ 3156 CSR_WRITE_4(sc, DC_IMR, 0x00000000); 3157 3158 while (((status = CSR_READ_4(sc, DC_ISR)) & DC_INTRS) 3159 && status != 0xFFFFFFFF) { 3160 3161 CSR_WRITE_4(sc, DC_ISR, status); 3162 3163 if (status & DC_ISR_RX_OK) { 3164 int curpkts; 3165 curpkts = ifp->if_ipackets; 3166 dc_rxeof(sc); 3167 if (curpkts == ifp->if_ipackets) { 3168 while (dc_rx_resync(sc)) 3169 dc_rxeof(sc); 3170 } 3171 } 3172 3173 if (status & (DC_ISR_TX_OK | DC_ISR_TX_NOBUF)) 3174 dc_txeof(sc); 3175 3176 if (status & DC_ISR_TX_IDLE) { 3177 dc_txeof(sc); 3178 if (sc->dc_cdata.dc_tx_cnt) { 3179 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_TX_ON); 3180 CSR_WRITE_4(sc, DC_TXSTART, 0xFFFFFFFF); 3181 } 3182 } 3183 3184 if (status & DC_ISR_TX_UNDERRUN) 3185 dc_tx_underrun(sc); 3186 3187 if ((status & DC_ISR_RX_WATDOGTIMEO) 3188 || (status & DC_ISR_RX_NOBUF)) { 3189 int curpkts; 3190 curpkts = ifp->if_ipackets; 3191 dc_rxeof(sc); 3192 if (curpkts == ifp->if_ipackets) { 3193 while (dc_rx_resync(sc)) 3194 dc_rxeof(sc); 3195 } 3196 } 3197 3198 if (status & DC_ISR_BUS_ERR) { 3199 dc_reset(sc); 3200 dc_init(sc); 3201 } 3202 } 3203 3204 /* Re-enable interrupts. */ 3205 CSR_WRITE_4(sc, DC_IMR, DC_INTRS); 3206 3207 if (ifp->if_snd.ifq_head != NULL) 3208 dc_start(ifp); 3209 3210 #ifdef DEVICE_POLLING 3211 done: 3212 #endif 3213 3214 DC_UNLOCK(sc); 3215 } 3216 3217 static void 3218 dc_dma_map_txbuf(arg, segs, nseg, mapsize, error) 3219 void *arg; 3220 bus_dma_segment_t *segs; 3221 int nseg; 3222 bus_size_t mapsize; 3223 int error; 3224 { 3225 struct dc_softc *sc; 3226 struct dc_desc *f; 3227 int cur, first, frag, i; 3228 3229 sc = arg; 3230 if (error) { 3231 sc->dc_cdata.dc_tx_err = error; 3232 return; 3233 } 3234 3235 first = cur = frag = sc->dc_cdata.dc_tx_prod; 3236 for (i = 0; i < nseg; i++) { 3237 if ((sc->dc_flags & DC_TX_ADMTEK_WAR) && 3238 (frag == (DC_TX_LIST_CNT - 1)) && 3239 (first != sc->dc_cdata.dc_tx_first)) { 3240 bus_dmamap_unload(sc->dc_mtag, 3241 sc->dc_cdata.dc_tx_map[first]); 3242 sc->dc_cdata.dc_tx_err = ENOBUFS; 3243 return; 3244 } 3245 3246 f = &sc->dc_ldata->dc_tx_list[frag]; 3247 f->dc_ctl = htole32(DC_TXCTL_TLINK | segs[i].ds_len); 3248 if (i == 0) { 3249 f->dc_status = 0; 3250 f->dc_ctl |= htole32(DC_TXCTL_FIRSTFRAG); 3251 } else 3252 f->dc_status = htole32(DC_TXSTAT_OWN); 3253 f->dc_data = htole32(segs[i].ds_addr); 3254 cur = frag; 3255 DC_INC(frag, DC_TX_LIST_CNT); 3256 } 3257 3258 sc->dc_cdata.dc_tx_err = 0; 3259 sc->dc_cdata.dc_tx_prod = frag; 3260 sc->dc_cdata.dc_tx_cnt += nseg; 3261 sc->dc_ldata->dc_tx_list[cur].dc_ctl |= htole32(DC_TXCTL_LASTFRAG); 3262 if (sc->dc_flags & DC_TX_INTR_FIRSTFRAG) 3263 sc->dc_ldata->dc_tx_list[first].dc_ctl |= 3264 htole32(DC_TXCTL_FINT); 3265 if (sc->dc_flags & DC_TX_INTR_ALWAYS) 3266 sc->dc_ldata->dc_tx_list[cur].dc_ctl |= htole32(DC_TXCTL_FINT); 3267 if (sc->dc_flags & DC_TX_USE_TX_INTR && sc->dc_cdata.dc_tx_cnt > 64) 3268 sc->dc_ldata->dc_tx_list[cur].dc_ctl |= htole32(DC_TXCTL_FINT); 3269 sc->dc_ldata->dc_tx_list[first].dc_status = htole32(DC_TXSTAT_OWN); 3270 } 3271 3272 /* 3273 * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data 3274 * pointers to the fragment pointers. 3275 */ 3276 static int 3277 dc_encap(struct dc_softc *sc, struct mbuf **m_head) 3278 { 3279 struct mbuf *m; 3280 int error, idx, chainlen = 0; 3281 3282 /* 3283 * If there's no way we can send any packets, return now. 3284 */ 3285 if (DC_TX_LIST_CNT - sc->dc_cdata.dc_tx_cnt < 6) 3286 return (ENOBUFS); 3287 3288 /* 3289 * Count the number of frags in this chain to see if 3290 * we need to m_defrag. Since the descriptor list is shared 3291 * by all packets, we'll m_defrag long chains so that they 3292 * do not use up the entire list, even if they would fit. 3293 */ 3294 for (m = *m_head; m != NULL; m = m->m_next) 3295 chainlen++; 3296 3297 if ((chainlen > DC_TX_LIST_CNT / 4) || 3298 ((DC_TX_LIST_CNT - (chainlen + sc->dc_cdata.dc_tx_cnt)) < 6)) { 3299 m = m_defrag(*m_head, M_DONTWAIT); 3300 if (m == NULL) 3301 return (ENOBUFS); 3302 *m_head = m; 3303 } 3304 3305 /* 3306 * Start packing the mbufs in this chain into 3307 * the fragment pointers. Stop when we run out 3308 * of fragments or hit the end of the mbuf chain. 3309 */ 3310 idx = sc->dc_cdata.dc_tx_prod; 3311 error = bus_dmamap_load_mbuf(sc->dc_mtag, sc->dc_cdata.dc_tx_map[idx], 3312 *m_head, dc_dma_map_txbuf, sc, 0); 3313 if (error) 3314 return (error); 3315 if (sc->dc_cdata.dc_tx_err != 0) 3316 return (sc->dc_cdata.dc_tx_err); 3317 sc->dc_cdata.dc_tx_chain[idx] = *m_head; 3318 bus_dmamap_sync(sc->dc_mtag, sc->dc_cdata.dc_tx_map[idx], 3319 BUS_DMASYNC_PREWRITE); 3320 bus_dmamap_sync(sc->dc_ltag, sc->dc_lmap, 3321 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3322 return (0); 3323 } 3324 3325 /* 3326 * Main transmit routine. To avoid having to do mbuf copies, we put pointers 3327 * to the mbuf data regions directly in the transmit lists. We also save a 3328 * copy of the pointers since the transmit list fragment pointers are 3329 * physical addresses. 3330 */ 3331 3332 static void 3333 dc_start(struct ifnet *ifp) 3334 { 3335 struct dc_softc *sc; 3336 struct mbuf *m_head = NULL, *m; 3337 int idx; 3338 3339 sc = ifp->if_softc; 3340 3341 DC_LOCK(sc); 3342 3343 if (!sc->dc_link && ifp->if_snd.ifq_len < 10) { 3344 DC_UNLOCK(sc); 3345 return; 3346 } 3347 3348 if (ifp->if_flags & IFF_OACTIVE) { 3349 DC_UNLOCK(sc); 3350 return; 3351 } 3352 3353 idx = sc->dc_cdata.dc_tx_first = sc->dc_cdata.dc_tx_prod; 3354 3355 while (sc->dc_cdata.dc_tx_chain[idx] == NULL) { 3356 IF_DEQUEUE(&ifp->if_snd, m_head); 3357 if (m_head == NULL) 3358 break; 3359 3360 if (sc->dc_flags & DC_TX_COALESCE && 3361 (m_head->m_next != NULL || 3362 sc->dc_flags & DC_TX_ALIGN)) { 3363 m = m_defrag(m_head, M_DONTWAIT); 3364 if (m == NULL) { 3365 IF_PREPEND(&ifp->if_snd, m_head); 3366 ifp->if_flags |= IFF_OACTIVE; 3367 break; 3368 } else { 3369 m_head = m; 3370 } 3371 } 3372 3373 if (dc_encap(sc, &m_head)) { 3374 IF_PREPEND(&ifp->if_snd, m_head); 3375 ifp->if_flags |= IFF_OACTIVE; 3376 break; 3377 } 3378 idx = sc->dc_cdata.dc_tx_prod; 3379 3380 /* 3381 * If there's a BPF listener, bounce a copy of this frame 3382 * to him. 3383 */ 3384 BPF_MTAP(ifp, m_head); 3385 3386 if (sc->dc_flags & DC_TX_ONE) { 3387 ifp->if_flags |= IFF_OACTIVE; 3388 break; 3389 } 3390 } 3391 3392 /* Transmit */ 3393 if (!(sc->dc_flags & DC_TX_POLL)) 3394 CSR_WRITE_4(sc, DC_TXSTART, 0xFFFFFFFF); 3395 3396 /* 3397 * Set a timeout in case the chip goes out to lunch. 3398 */ 3399 ifp->if_timer = 5; 3400 3401 DC_UNLOCK(sc); 3402 } 3403 3404 static void 3405 dc_init(void *xsc) 3406 { 3407 struct dc_softc *sc = xsc; 3408 struct ifnet *ifp = &sc->arpcom.ac_if; 3409 struct mii_data *mii; 3410 3411 DC_LOCK(sc); 3412 3413 mii = device_get_softc(sc->dc_miibus); 3414 3415 /* 3416 * Cancel pending I/O and free all RX/TX buffers. 3417 */ 3418 dc_stop(sc); 3419 dc_reset(sc); 3420 3421 /* 3422 * Set cache alignment and burst length. 3423 */ 3424 if (DC_IS_ASIX(sc) || DC_IS_DAVICOM(sc)) 3425 CSR_WRITE_4(sc, DC_BUSCTL, 0); 3426 else 3427 CSR_WRITE_4(sc, DC_BUSCTL, DC_BUSCTL_MRME | DC_BUSCTL_MRLE); 3428 /* 3429 * Evenly share the bus between receive and transmit process. 3430 */ 3431 if (DC_IS_INTEL(sc)) 3432 DC_SETBIT(sc, DC_BUSCTL, DC_BUSCTL_ARBITRATION); 3433 if (DC_IS_DAVICOM(sc) || DC_IS_INTEL(sc)) { 3434 DC_SETBIT(sc, DC_BUSCTL, DC_BURSTLEN_USECA); 3435 } else { 3436 DC_SETBIT(sc, DC_BUSCTL, DC_BURSTLEN_16LONG); 3437 } 3438 if (sc->dc_flags & DC_TX_POLL) 3439 DC_SETBIT(sc, DC_BUSCTL, DC_TXPOLL_1); 3440 switch(sc->dc_cachesize) { 3441 case 32: 3442 DC_SETBIT(sc, DC_BUSCTL, DC_CACHEALIGN_32LONG); 3443 break; 3444 case 16: 3445 DC_SETBIT(sc, DC_BUSCTL, DC_CACHEALIGN_16LONG); 3446 break; 3447 case 8: 3448 DC_SETBIT(sc, DC_BUSCTL, DC_CACHEALIGN_8LONG); 3449 break; 3450 case 0: 3451 default: 3452 DC_SETBIT(sc, DC_BUSCTL, DC_CACHEALIGN_NONE); 3453 break; 3454 } 3455 3456 if (sc->dc_flags & DC_TX_STORENFWD) 3457 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_STORENFWD); 3458 else { 3459 if (sc->dc_txthresh > DC_TXTHRESH_MAX) { 3460 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_STORENFWD); 3461 } else { 3462 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_STORENFWD); 3463 DC_SETBIT(sc, DC_NETCFG, sc->dc_txthresh); 3464 } 3465 } 3466 3467 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_NO_RXCRC); 3468 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_TX_BACKOFF); 3469 3470 if (DC_IS_MACRONIX(sc) || DC_IS_PNICII(sc)) { 3471 /* 3472 * The app notes for the 98713 and 98715A say that 3473 * in order to have the chips operate properly, a magic 3474 * number must be written to CSR16. Macronix does not 3475 * document the meaning of these bits so there's no way 3476 * to know exactly what they do. The 98713 has a magic 3477 * number all its own; the rest all use a different one. 3478 */ 3479 DC_CLRBIT(sc, DC_MX_MAGICPACKET, 0xFFFF0000); 3480 if (sc->dc_type == DC_TYPE_98713) 3481 DC_SETBIT(sc, DC_MX_MAGICPACKET, DC_MX_MAGIC_98713); 3482 else 3483 DC_SETBIT(sc, DC_MX_MAGICPACKET, DC_MX_MAGIC_98715); 3484 } 3485 3486 if (DC_IS_XIRCOM(sc)) { 3487 /* 3488 * setup General Purpose Port mode and data so the tulip 3489 * can talk to the MII. 3490 */ 3491 CSR_WRITE_4(sc, DC_SIAGP, DC_SIAGP_WRITE_EN | DC_SIAGP_INT1_EN | 3492 DC_SIAGP_MD_GP2_OUTPUT | DC_SIAGP_MD_GP0_OUTPUT); 3493 DELAY(10); 3494 CSR_WRITE_4(sc, DC_SIAGP, DC_SIAGP_INT1_EN | 3495 DC_SIAGP_MD_GP2_OUTPUT | DC_SIAGP_MD_GP0_OUTPUT); 3496 DELAY(10); 3497 } 3498 3499 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_TX_THRESH); 3500 DC_SETBIT(sc, DC_NETCFG, DC_TXTHRESH_MIN); 3501 3502 /* Init circular RX list. */ 3503 if (dc_list_rx_init(sc) == ENOBUFS) { 3504 printf("dc%d: initialization failed: no " 3505 "memory for rx buffers\n", sc->dc_unit); 3506 dc_stop(sc); 3507 DC_UNLOCK(sc); 3508 return; 3509 } 3510 3511 /* 3512 * Init TX descriptors. 3513 */ 3514 dc_list_tx_init(sc); 3515 3516 /* 3517 * Load the address of the RX list. 3518 */ 3519 CSR_WRITE_4(sc, DC_RXADDR, DC_RXDESC(sc, 0)); 3520 CSR_WRITE_4(sc, DC_TXADDR, DC_TXDESC(sc, 0)); 3521 3522 /* 3523 * Enable interrupts. 3524 */ 3525 #ifdef DEVICE_POLLING 3526 /* 3527 * ... but only if we are not polling, and make sure they are off in 3528 * the case of polling. Some cards (e.g. fxp) turn interrupts on 3529 * after a reset. 3530 */ 3531 if (ifp->if_flags & IFF_POLLING) 3532 CSR_WRITE_4(sc, DC_IMR, 0x00000000); 3533 else 3534 #endif 3535 CSR_WRITE_4(sc, DC_IMR, DC_INTRS); 3536 CSR_WRITE_4(sc, DC_ISR, 0xFFFFFFFF); 3537 3538 /* Enable transmitter. */ 3539 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_TX_ON); 3540 3541 /* 3542 * If this is an Intel 21143 and we're not using the 3543 * MII port, program the LED control pins so we get 3544 * link and activity indications. 3545 */ 3546 if (sc->dc_flags & DC_TULIP_LEDS) { 3547 CSR_WRITE_4(sc, DC_WATCHDOG, 3548 DC_WDOG_CTLWREN | DC_WDOG_LINK | DC_WDOG_ACTIVITY); 3549 CSR_WRITE_4(sc, DC_WATCHDOG, 0); 3550 } 3551 3552 /* 3553 * Load the RX/multicast filter. We do this sort of late 3554 * because the filter programming scheme on the 21143 and 3555 * some clones requires DMAing a setup frame via the TX 3556 * engine, and we need the transmitter enabled for that. 3557 */ 3558 dc_setfilt(sc); 3559 3560 /* Enable receiver. */ 3561 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_ON); 3562 CSR_WRITE_4(sc, DC_RXSTART, 0xFFFFFFFF); 3563 3564 mii_mediachg(mii); 3565 dc_setcfg(sc, sc->dc_if_media); 3566 3567 ifp->if_flags |= IFF_RUNNING; 3568 ifp->if_flags &= ~IFF_OACTIVE; 3569 3570 /* Don't start the ticker if this is a homePNA link. */ 3571 if (IFM_SUBTYPE(mii->mii_media.ifm_media) == IFM_HPNA_1) 3572 sc->dc_link = 1; 3573 else { 3574 if (sc->dc_flags & DC_21143_NWAY) 3575 callout_reset(&sc->dc_stat_ch, hz/10, dc_tick, sc); 3576 else 3577 callout_reset(&sc->dc_stat_ch, hz, dc_tick, sc); 3578 } 3579 3580 #ifdef SRM_MEDIA 3581 if(sc->dc_srm_media) { 3582 struct ifreq ifr; 3583 3584 ifr.ifr_media = sc->dc_srm_media; 3585 ifmedia_ioctl(ifp, &ifr, &mii->mii_media, SIOCSIFMEDIA); 3586 sc->dc_srm_media = 0; 3587 } 3588 #endif 3589 DC_UNLOCK(sc); 3590 } 3591 3592 /* 3593 * Set media options. 3594 */ 3595 static int 3596 dc_ifmedia_upd(struct ifnet *ifp) 3597 { 3598 struct dc_softc *sc; 3599 struct mii_data *mii; 3600 struct ifmedia *ifm; 3601 3602 sc = ifp->if_softc; 3603 mii = device_get_softc(sc->dc_miibus); 3604 mii_mediachg(mii); 3605 ifm = &mii->mii_media; 3606 3607 if (DC_IS_DAVICOM(sc) && 3608 IFM_SUBTYPE(ifm->ifm_media) == IFM_HPNA_1) 3609 dc_setcfg(sc, ifm->ifm_media); 3610 else 3611 sc->dc_link = 0; 3612 3613 return (0); 3614 } 3615 3616 /* 3617 * Report current media status. 3618 */ 3619 static void 3620 dc_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 3621 { 3622 struct dc_softc *sc; 3623 struct mii_data *mii; 3624 struct ifmedia *ifm; 3625 3626 sc = ifp->if_softc; 3627 mii = device_get_softc(sc->dc_miibus); 3628 mii_pollstat(mii); 3629 ifm = &mii->mii_media; 3630 if (DC_IS_DAVICOM(sc)) { 3631 if (IFM_SUBTYPE(ifm->ifm_media) == IFM_HPNA_1) { 3632 ifmr->ifm_active = ifm->ifm_media; 3633 ifmr->ifm_status = 0; 3634 return; 3635 } 3636 } 3637 ifmr->ifm_active = mii->mii_media_active; 3638 ifmr->ifm_status = mii->mii_media_status; 3639 } 3640 3641 static int 3642 dc_ioctl(struct ifnet *ifp, u_long command, caddr_t data) 3643 { 3644 struct dc_softc *sc = ifp->if_softc; 3645 struct ifreq *ifr = (struct ifreq *)data; 3646 struct mii_data *mii; 3647 int error = 0; 3648 3649 DC_LOCK(sc); 3650 3651 switch (command) { 3652 case SIOCSIFFLAGS: 3653 if (ifp->if_flags & IFF_UP) { 3654 int need_setfilt = (ifp->if_flags ^ sc->dc_if_flags) & 3655 (IFF_PROMISC | IFF_ALLMULTI); 3656 3657 if (ifp->if_flags & IFF_RUNNING) { 3658 if (need_setfilt) 3659 dc_setfilt(sc); 3660 } else { 3661 sc->dc_txthresh = 0; 3662 dc_init(sc); 3663 } 3664 } else { 3665 if (ifp->if_flags & IFF_RUNNING) 3666 dc_stop(sc); 3667 } 3668 sc->dc_if_flags = ifp->if_flags; 3669 error = 0; 3670 break; 3671 case SIOCADDMULTI: 3672 case SIOCDELMULTI: 3673 dc_setfilt(sc); 3674 error = 0; 3675 break; 3676 case SIOCGIFMEDIA: 3677 case SIOCSIFMEDIA: 3678 mii = device_get_softc(sc->dc_miibus); 3679 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 3680 #ifdef SRM_MEDIA 3681 if (sc->dc_srm_media) 3682 sc->dc_srm_media = 0; 3683 #endif 3684 break; 3685 default: 3686 error = ether_ioctl(ifp, command, data); 3687 break; 3688 } 3689 3690 DC_UNLOCK(sc); 3691 3692 return (error); 3693 } 3694 3695 static void 3696 dc_watchdog(struct ifnet *ifp) 3697 { 3698 struct dc_softc *sc; 3699 3700 sc = ifp->if_softc; 3701 3702 DC_LOCK(sc); 3703 3704 ifp->if_oerrors++; 3705 printf("dc%d: watchdog timeout\n", sc->dc_unit); 3706 3707 dc_stop(sc); 3708 dc_reset(sc); 3709 dc_init(sc); 3710 3711 if (ifp->if_snd.ifq_head != NULL) 3712 dc_start(ifp); 3713 3714 DC_UNLOCK(sc); 3715 } 3716 3717 /* 3718 * Stop the adapter and free any mbufs allocated to the 3719 * RX and TX lists. 3720 */ 3721 static void 3722 dc_stop(struct dc_softc *sc) 3723 { 3724 struct ifnet *ifp; 3725 struct dc_list_data *ld; 3726 struct dc_chain_data *cd; 3727 int i; 3728 u_int32_t ctl; 3729 3730 DC_LOCK(sc); 3731 3732 ifp = &sc->arpcom.ac_if; 3733 ifp->if_timer = 0; 3734 ld = sc->dc_ldata; 3735 cd = &sc->dc_cdata; 3736 3737 callout_stop(&sc->dc_stat_ch); 3738 3739 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 3740 #ifdef DEVICE_POLLING 3741 ether_poll_deregister(ifp); 3742 #endif 3743 3744 DC_CLRBIT(sc, DC_NETCFG, (DC_NETCFG_RX_ON | DC_NETCFG_TX_ON)); 3745 CSR_WRITE_4(sc, DC_IMR, 0x00000000); 3746 CSR_WRITE_4(sc, DC_TXADDR, 0x00000000); 3747 CSR_WRITE_4(sc, DC_RXADDR, 0x00000000); 3748 sc->dc_link = 0; 3749 3750 /* 3751 * Free data in the RX lists. 3752 */ 3753 for (i = 0; i < DC_RX_LIST_CNT; i++) { 3754 if (cd->dc_rx_chain[i] != NULL) { 3755 m_freem(cd->dc_rx_chain[i]); 3756 cd->dc_rx_chain[i] = NULL; 3757 } 3758 } 3759 bzero(&ld->dc_rx_list, sizeof(ld->dc_rx_list)); 3760 3761 /* 3762 * Free the TX list buffers. 3763 */ 3764 for (i = 0; i < DC_TX_LIST_CNT; i++) { 3765 if (cd->dc_tx_chain[i] != NULL) { 3766 ctl = le32toh(ld->dc_tx_list[i].dc_ctl); 3767 if ((ctl & DC_TXCTL_SETUP) || 3768 !(ctl & DC_TXCTL_FIRSTFRAG)) { 3769 cd->dc_tx_chain[i] = NULL; 3770 continue; 3771 } 3772 bus_dmamap_unload(sc->dc_mtag, cd->dc_tx_map[i]); 3773 m_freem(cd->dc_tx_chain[i]); 3774 cd->dc_tx_chain[i] = NULL; 3775 } 3776 } 3777 bzero(&ld->dc_tx_list, sizeof(ld->dc_tx_list)); 3778 3779 DC_UNLOCK(sc); 3780 } 3781 3782 /* 3783 * Device suspend routine. Stop the interface and save some PCI 3784 * settings in case the BIOS doesn't restore them properly on 3785 * resume. 3786 */ 3787 static int 3788 dc_suspend(device_t dev) 3789 { 3790 struct dc_softc *sc; 3791 int i, s; 3792 3793 s = splimp(); 3794 3795 sc = device_get_softc(dev); 3796 3797 dc_stop(sc); 3798 3799 for (i = 0; i < 5; i++) 3800 sc->saved_maps[i] = pci_read_config(dev, PCIR_BAR(i), 4); 3801 sc->saved_biosaddr = pci_read_config(dev, PCIR_BIOS, 4); 3802 sc->saved_intline = pci_read_config(dev, PCIR_INTLINE, 1); 3803 sc->saved_cachelnsz = pci_read_config(dev, PCIR_CACHELNSZ, 1); 3804 sc->saved_lattimer = pci_read_config(dev, PCIR_LATTIMER, 1); 3805 3806 sc->suspended = 1; 3807 3808 splx(s); 3809 return (0); 3810 } 3811 3812 /* 3813 * Device resume routine. Restore some PCI settings in case the BIOS 3814 * doesn't, re-enable busmastering, and restart the interface if 3815 * appropriate. 3816 */ 3817 static int 3818 dc_resume(device_t dev) 3819 { 3820 struct dc_softc *sc; 3821 struct ifnet *ifp; 3822 int i, s; 3823 3824 s = splimp(); 3825 3826 sc = device_get_softc(dev); 3827 ifp = &sc->arpcom.ac_if; 3828 #ifndef BURN_BRIDGES 3829 dc_acpi(dev); 3830 #endif 3831 /* better way to do this? */ 3832 for (i = 0; i < 5; i++) 3833 pci_write_config(dev, PCIR_BAR(i), sc->saved_maps[i], 4); 3834 pci_write_config(dev, PCIR_BIOS, sc->saved_biosaddr, 4); 3835 pci_write_config(dev, PCIR_INTLINE, sc->saved_intline, 1); 3836 pci_write_config(dev, PCIR_CACHELNSZ, sc->saved_cachelnsz, 1); 3837 pci_write_config(dev, PCIR_LATTIMER, sc->saved_lattimer, 1); 3838 3839 /* reenable busmastering */ 3840 pci_enable_busmaster(dev); 3841 pci_enable_io(dev, DC_RES); 3842 3843 /* reinitialize interface if necessary */ 3844 if (ifp->if_flags & IFF_UP) 3845 dc_init(sc); 3846 3847 sc->suspended = 0; 3848 3849 splx(s); 3850 return (0); 3851 } 3852 3853 /* 3854 * Stop all chip I/O so that the kernel's probe routines don't 3855 * get confused by errant DMAs when rebooting. 3856 */ 3857 static void 3858 dc_shutdown(device_t dev) 3859 { 3860 struct dc_softc *sc; 3861 3862 sc = device_get_softc(dev); 3863 3864 dc_stop(sc); 3865 } 3866