1 /* 2 * Copyright (c) 1997, 1998, 1999 3 * Bill Paul <wpaul@ee.columbia.edu>. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 3. All advertising materials mentioning features or use of this software 14 * must display the following acknowledgement: 15 * This product includes software developed by Bill Paul. 16 * 4. Neither the name of the author nor the names of any co-contributors 17 * may be used to endorse or promote products derived from this software 18 * without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30 * THE POSSIBILITY OF SUCH DAMAGE. 31 * 32 * $FreeBSD$ 33 */ 34 35 /* 36 * DEC "tulip" clone ethernet driver. Supports the DEC/Intel 21143 37 * series chips and several workalikes including the following: 38 * 39 * Macronix 98713/98715/98725 PMAC (www.macronix.com) 40 * Macronix/Lite-On 82c115 PNIC II (www.macronix.com) 41 * Lite-On 82c168/82c169 PNIC (www.litecom.com) 42 * ASIX Electronics AX88140A (www.asix.com.tw) 43 * ASIX Electronics AX88141 (www.asix.com.tw) 44 * ADMtek AL981 (www.admtek.com.tw) 45 * ADMtek AN985 (www.admtek.com.tw) 46 * Davicom DM9100, DM9102 (www.davicom8.com) 47 * 48 * Datasheets for the 21143 are available at developer.intel.com. 49 * Datasheets for the clone parts can be found at their respective sites. 50 * (Except for the PNIC; see www.freebsd.org/~wpaul/PNIC/pnic.ps.gz.) 51 * The PNIC II is essentially a Macronix 98715A chip; the only difference 52 * worth noting is that its multicast hash table is only 128 bits wide 53 * instead of 512. 54 * 55 * Written by Bill Paul <wpaul@ee.columbia.edu> 56 * Electrical Engineering Department 57 * Columbia University, New York City 58 */ 59 60 /* 61 * The Intel 21143 is the successor to the DEC 21140. It is basically 62 * the same as the 21140 but with a few new features. The 21143 supports 63 * three kinds of media attachments: 64 * 65 * o MII port, for 10Mbps and 100Mbps support and NWAY 66 * autonegotiation provided by an external PHY. 67 * o SYM port, for symbol mode 100Mbps support. 68 * o 10baseT port. 69 * o AUI/BNC port. 70 * 71 * The 100Mbps SYM port and 10baseT port can be used together in 72 * combination with the internal NWAY support to create a 10/100 73 * autosensing configuration. 74 * 75 * Knowing which media is available on a given card is tough: you're 76 * supposed to go slogging through the EEPROM looking for media 77 * description structures. Unfortunately, some card vendors that use 78 * the 21143 don't obey the DEC SROM spec correctly, which means that 79 * what you find in the EEPROM may not agree with reality. Fortunately, 80 * the 21143 provides us a way to get around this issue: lurking in 81 * PCI configuration space is the Configuration Wake-Up Command Register. 82 * This register is loaded with a value from the EEPROM when wake on LAN 83 * mode is enabled; this value tells us quite clearly what kind of media 84 * is attached to the NIC. The main purpose of this register is to tell 85 * the NIC what media to scan when in wake on LAN mode, however by 86 * forcibly enabling wake on LAN mode, we can use to learn what kind of 87 * media a given NIC has available and adapt ourselves accordingly. 88 * 89 * Of course, if the media description blocks in the EEPROM are bogus. 90 * what are the odds that the CWUC aren't bogus as well, right? Well, 91 * the CWUC value is more likely to be correct since wake on LAN mode 92 * won't work correctly without it, and wake on LAN is a big selling 93 * point these days. It's also harder to screw up a single byte than 94 * a whole media descriptor block. 95 * 96 * Note that not all tulip workalikes are handled in this driver: we only 97 * deal with those which are relatively well behaved. The Winbond is 98 * handled separately due to its different register offsets and the 99 * special handling needed for its various bugs. The PNIC is handled 100 * here, but I'm not thrilled about it. 101 * 102 * All of the workalike chips use some form of MII transceiver support 103 * with the exception of the Macronix chips, which also have a SYM port. 104 * The ASIX AX88140A is also documented to have a SYM port, but all 105 * the cards I've seen use an MII transceiver, probably because the 106 * AX88140A doesn't support internal NWAY. 107 */ 108 109 #include <sys/param.h> 110 #include <sys/systm.h> 111 #include <sys/sockio.h> 112 #include <sys/mbuf.h> 113 #include <sys/malloc.h> 114 #include <sys/kernel.h> 115 #include <sys/socket.h> 116 117 #include <net/if.h> 118 #include <net/if_arp.h> 119 #include <net/ethernet.h> 120 #include <net/if_dl.h> 121 #include <net/if_media.h> 122 123 #include <net/bpf.h> 124 125 #include <vm/vm.h> /* for vtophys */ 126 #include <vm/pmap.h> /* for vtophys */ 127 #include <machine/clock.h> /* for DELAY */ 128 #include <machine/bus_pio.h> 129 #include <machine/bus_memio.h> 130 #include <machine/bus.h> 131 #include <machine/resource.h> 132 #include <sys/bus.h> 133 #include <sys/rman.h> 134 135 #include <dev/mii/mii.h> 136 #include <dev/mii/miivar.h> 137 138 #include <pci/pcireg.h> 139 #include <pci/pcivar.h> 140 141 #define DC_USEIOSPACE 142 143 #include <pci/if_dcreg.h> 144 145 /* "controller miibus0" required. See GENERIC if you get errors here. */ 146 #include "miibus_if.h" 147 148 #ifndef lint 149 static const char rcsid[] = 150 "$FreeBSD$"; 151 #endif 152 153 /* 154 * Various supported device vendors/types and their names. 155 */ 156 static struct dc_type dc_devs[] = { 157 { DC_VENDORID_DEC, DC_DEVICEID_21143, 158 "Intel 21143 10/100BaseTX" }, 159 { DC_VENDORID_DAVICOM, DC_DEVICEID_DM9100, 160 "Davicom DM9100 10/100BaseTX" }, 161 { DC_VENDORID_DAVICOM, DC_DEVICEID_DM9102, 162 "Davicom DM9102 10/100BaseTX" }, 163 { DC_VENDORID_ADMTEK, DC_DEVICEID_AL981, 164 "ADMtek AL981 10/100BaseTX" }, 165 { DC_VENDORID_ADMTEK, DC_DEVICEID_AN985, 166 "ADMtek AN985 10/100BaseTX" }, 167 { DC_VENDORID_ASIX, DC_DEVICEID_AX88140A, 168 "ASIX AX88140A 10/100BaseTX" }, 169 { DC_VENDORID_ASIX, DC_DEVICEID_AX88140A, 170 "ASIX AX88141 10/100BaseTX" }, 171 { DC_VENDORID_MX, DC_DEVICEID_98713, 172 "Macronix 98713 10/100BaseTX" }, 173 { DC_VENDORID_MX, DC_DEVICEID_98713, 174 "Macronix 98713A 10/100BaseTX" }, 175 { DC_VENDORID_CP, DC_DEVICEID_98713_CP, 176 "Compex RL100-TX 10/100BaseTX" }, 177 { DC_VENDORID_CP, DC_DEVICEID_98713_CP, 178 "Compex RL100-TX 10/100BaseTX" }, 179 { DC_VENDORID_MX, DC_DEVICEID_987x5, 180 "Macronix 98715/98715A 10/100BaseTX" }, 181 { DC_VENDORID_MX, DC_DEVICEID_987x5, 182 "Macronix 98725 10/100BaseTX" }, 183 { DC_VENDORID_LO, DC_DEVICEID_82C115, 184 "LC82C115 PNIC II 10/100BaseTX" }, 185 { DC_VENDORID_LO, DC_DEVICEID_82C168, 186 "82c168 PNIC 10/100BaseTX" }, 187 { DC_VENDORID_LO, DC_DEVICEID_82C168, 188 "82c169 PNIC 10/100BaseTX" }, 189 { 0, 0, NULL } 190 }; 191 192 static int dc_probe __P((device_t)); 193 static int dc_attach __P((device_t)); 194 static int dc_detach __P((device_t)); 195 static void dc_acpi __P((device_t)); 196 static struct dc_type *dc_devtype __P((device_t)); 197 static int dc_newbuf __P((struct dc_softc *, int, struct mbuf *)); 198 static int dc_encap __P((struct dc_softc *, struct mbuf *, 199 u_int32_t *)); 200 static int dc_coal __P((struct dc_softc *, struct mbuf **)); 201 static void dc_pnic_rx_bug_war __P((struct dc_softc *, int)); 202 static int dc_rx_resync __P((struct dc_softc *)); 203 static void dc_rxeof __P((struct dc_softc *)); 204 static void dc_txeof __P((struct dc_softc *)); 205 static void dc_tick __P((void *)); 206 static void dc_intr __P((void *)); 207 static void dc_start __P((struct ifnet *)); 208 static int dc_ioctl __P((struct ifnet *, u_long, caddr_t)); 209 static void dc_init __P((void *)); 210 static void dc_stop __P((struct dc_softc *)); 211 static void dc_watchdog __P((struct ifnet *)); 212 static void dc_shutdown __P((device_t)); 213 static int dc_ifmedia_upd __P((struct ifnet *)); 214 static void dc_ifmedia_sts __P((struct ifnet *, struct ifmediareq *)); 215 216 static void dc_delay __P((struct dc_softc *)); 217 static void dc_eeprom_idle __P((struct dc_softc *)); 218 static void dc_eeprom_putbyte __P((struct dc_softc *, int)); 219 static void dc_eeprom_getword __P((struct dc_softc *, int, u_int16_t *)); 220 static void dc_eeprom_getword_pnic 221 __P((struct dc_softc *, int, u_int16_t *)); 222 static void dc_read_eeprom __P((struct dc_softc *, caddr_t, int, 223 int, int)); 224 225 static void dc_mii_writebit __P((struct dc_softc *, int)); 226 static int dc_mii_readbit __P((struct dc_softc *)); 227 static void dc_mii_sync __P((struct dc_softc *)); 228 static void dc_mii_send __P((struct dc_softc *, u_int32_t, int)); 229 static int dc_mii_readreg __P((struct dc_softc *, struct dc_mii_frame *)); 230 static int dc_mii_writereg __P((struct dc_softc *, struct dc_mii_frame *)); 231 static int dc_miibus_readreg __P((device_t, int, int)); 232 static int dc_miibus_writereg __P((device_t, int, int, int)); 233 static void dc_miibus_statchg __P((device_t)); 234 235 static void dc_setcfg __P((struct dc_softc *, int)); 236 static u_int32_t dc_crc_le __P((struct dc_softc *, caddr_t)); 237 static u_int32_t dc_crc_be __P((caddr_t)); 238 static void dc_setfilt_21143 __P((struct dc_softc *)); 239 static void dc_setfilt_asix __P((struct dc_softc *)); 240 static void dc_setfilt_admtek __P((struct dc_softc *)); 241 242 static void dc_setfilt __P((struct dc_softc *)); 243 244 static void dc_reset __P((struct dc_softc *)); 245 static int dc_list_rx_init __P((struct dc_softc *)); 246 static int dc_list_tx_init __P((struct dc_softc *)); 247 248 #ifdef DC_USEIOSPACE 249 #define DC_RES SYS_RES_IOPORT 250 #define DC_RID DC_PCI_CFBIO 251 #else 252 #define DC_RES SYS_RES_MEMORY 253 #define DC_RID DC_PCI_CFBMA 254 #endif 255 256 static device_method_t dc_methods[] = { 257 /* Device interface */ 258 DEVMETHOD(device_probe, dc_probe), 259 DEVMETHOD(device_attach, dc_attach), 260 DEVMETHOD(device_detach, dc_detach), 261 DEVMETHOD(device_shutdown, dc_shutdown), 262 263 /* bus interface */ 264 DEVMETHOD(bus_print_child, bus_generic_print_child), 265 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 266 267 /* MII interface */ 268 DEVMETHOD(miibus_readreg, dc_miibus_readreg), 269 DEVMETHOD(miibus_writereg, dc_miibus_writereg), 270 DEVMETHOD(miibus_statchg, dc_miibus_statchg), 271 272 { 0, 0 } 273 }; 274 275 static driver_t dc_driver = { 276 "dc", 277 dc_methods, 278 sizeof(struct dc_softc) 279 }; 280 281 static devclass_t dc_devclass; 282 283 DRIVER_MODULE(if_dc, pci, dc_driver, dc_devclass, 0, 0); 284 DRIVER_MODULE(miibus, dc, miibus_driver, miibus_devclass, 0, 0); 285 286 #define DC_SETBIT(sc, reg, x) \ 287 CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) | (x)) 288 289 #define DC_CLRBIT(sc, reg, x) \ 290 CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) & ~(x)) 291 292 #define SIO_SET(x) DC_SETBIT(sc, DC_SIO, (x)) 293 #define SIO_CLR(x) DC_CLRBIT(sc, DC_SIO, (x)) 294 295 static void dc_delay(sc) 296 struct dc_softc *sc; 297 { 298 int idx; 299 300 for (idx = (300 / 33) + 1; idx > 0; idx--) 301 CSR_READ_4(sc, DC_BUSCTL); 302 } 303 304 static void dc_eeprom_idle(sc) 305 struct dc_softc *sc; 306 { 307 register int i; 308 309 CSR_WRITE_4(sc, DC_SIO, DC_SIO_EESEL); 310 dc_delay(sc); 311 DC_SETBIT(sc, DC_SIO, DC_SIO_ROMCTL_READ); 312 dc_delay(sc); 313 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); 314 dc_delay(sc); 315 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CS); 316 dc_delay(sc); 317 318 for (i = 0; i < 25; i++) { 319 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); 320 dc_delay(sc); 321 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CLK); 322 dc_delay(sc); 323 } 324 325 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); 326 dc_delay(sc); 327 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CS); 328 dc_delay(sc); 329 CSR_WRITE_4(sc, DC_SIO, 0x00000000); 330 331 return; 332 } 333 334 /* 335 * Send a read command and address to the EEPROM, check for ACK. 336 */ 337 static void dc_eeprom_putbyte(sc, addr) 338 struct dc_softc *sc; 339 int addr; 340 { 341 register int d, i; 342 343 /* 344 * The AN985 has a 93C66 EEPROM on it instead of 345 * a 93C46. It uses a different bit sequence for 346 * specifying the "read" opcode. 347 */ 348 if (DC_IS_CENTAUR(sc)) 349 d = addr | (DC_EECMD_READ << 2); 350 else 351 d = addr | DC_EECMD_READ; 352 353 /* 354 * Feed in each bit and strobe the clock. 355 */ 356 for (i = 0x400; i; i >>= 1) { 357 if (d & i) { 358 SIO_SET(DC_SIO_EE_DATAIN); 359 } else { 360 SIO_CLR(DC_SIO_EE_DATAIN); 361 } 362 dc_delay(sc); 363 SIO_SET(DC_SIO_EE_CLK); 364 dc_delay(sc); 365 SIO_CLR(DC_SIO_EE_CLK); 366 dc_delay(sc); 367 } 368 369 return; 370 } 371 372 /* 373 * Read a word of data stored in the EEPROM at address 'addr.' 374 * The PNIC 82c168/82c169 has its own non-standard way to read 375 * the EEPROM. 376 */ 377 static void dc_eeprom_getword_pnic(sc, addr, dest) 378 struct dc_softc *sc; 379 int addr; 380 u_int16_t *dest; 381 { 382 register int i; 383 u_int32_t r; 384 385 CSR_WRITE_4(sc, DC_PN_SIOCTL, DC_PN_EEOPCODE_READ|addr); 386 387 for (i = 0; i < DC_TIMEOUT; i++) { 388 DELAY(1); 389 r = CSR_READ_4(sc, DC_SIO); 390 if (!(r & DC_PN_SIOCTL_BUSY)) { 391 *dest = (u_int16_t)(r & 0xFFFF); 392 return; 393 } 394 } 395 396 return; 397 } 398 399 /* 400 * Read a word of data stored in the EEPROM at address 'addr.' 401 */ 402 static void dc_eeprom_getword(sc, addr, dest) 403 struct dc_softc *sc; 404 int addr; 405 u_int16_t *dest; 406 { 407 register int i; 408 u_int16_t word = 0; 409 410 /* Force EEPROM to idle state. */ 411 dc_eeprom_idle(sc); 412 413 /* Enter EEPROM access mode. */ 414 CSR_WRITE_4(sc, DC_SIO, DC_SIO_EESEL); 415 dc_delay(sc); 416 DC_SETBIT(sc, DC_SIO, DC_SIO_ROMCTL_READ); 417 dc_delay(sc); 418 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); 419 dc_delay(sc); 420 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CS); 421 dc_delay(sc); 422 423 /* 424 * Send address of word we want to read. 425 */ 426 dc_eeprom_putbyte(sc, addr); 427 428 /* 429 * Start reading bits from EEPROM. 430 */ 431 for (i = 0x8000; i; i >>= 1) { 432 SIO_SET(DC_SIO_EE_CLK); 433 dc_delay(sc); 434 if (CSR_READ_4(sc, DC_SIO) & DC_SIO_EE_DATAOUT) 435 word |= i; 436 dc_delay(sc); 437 SIO_CLR(DC_SIO_EE_CLK); 438 dc_delay(sc); 439 } 440 441 /* Turn off EEPROM access mode. */ 442 dc_eeprom_idle(sc); 443 444 *dest = word; 445 446 return; 447 } 448 449 /* 450 * Read a sequence of words from the EEPROM. 451 */ 452 static void dc_read_eeprom(sc, dest, off, cnt, swap) 453 struct dc_softc *sc; 454 caddr_t dest; 455 int off; 456 int cnt; 457 int swap; 458 { 459 int i; 460 u_int16_t word = 0, *ptr; 461 462 for (i = 0; i < cnt; i++) { 463 if (DC_IS_PNIC(sc)) 464 dc_eeprom_getword_pnic(sc, off + i, &word); 465 else 466 dc_eeprom_getword(sc, off + i, &word); 467 ptr = (u_int16_t *)(dest + (i * 2)); 468 if (swap) 469 *ptr = ntohs(word); 470 else 471 *ptr = word; 472 } 473 474 return; 475 } 476 477 /* 478 * The following two routines are taken from the Macronix 98713 479 * Application Notes pp.19-21. 480 */ 481 /* 482 * Write a bit to the MII bus. 483 */ 484 static void dc_mii_writebit(sc, bit) 485 struct dc_softc *sc; 486 int bit; 487 { 488 if (bit) 489 CSR_WRITE_4(sc, DC_SIO, 490 DC_SIO_ROMCTL_WRITE|DC_SIO_MII_DATAOUT); 491 else 492 CSR_WRITE_4(sc, DC_SIO, DC_SIO_ROMCTL_WRITE); 493 494 DC_SETBIT(sc, DC_SIO, DC_SIO_MII_CLK); 495 DC_CLRBIT(sc, DC_SIO, DC_SIO_MII_CLK); 496 497 return; 498 } 499 500 /* 501 * Read a bit from the MII bus. 502 */ 503 static int dc_mii_readbit(sc) 504 struct dc_softc *sc; 505 { 506 CSR_WRITE_4(sc, DC_SIO, DC_SIO_ROMCTL_READ|DC_SIO_MII_DIR); 507 CSR_READ_4(sc, DC_SIO); 508 DC_SETBIT(sc, DC_SIO, DC_SIO_MII_CLK); 509 DC_CLRBIT(sc, DC_SIO, DC_SIO_MII_CLK); 510 if (CSR_READ_4(sc, DC_SIO) & DC_SIO_MII_DATAIN) 511 return(1); 512 513 return(0); 514 } 515 516 /* 517 * Sync the PHYs by setting data bit and strobing the clock 32 times. 518 */ 519 static void dc_mii_sync(sc) 520 struct dc_softc *sc; 521 { 522 register int i; 523 524 CSR_WRITE_4(sc, DC_SIO, DC_SIO_ROMCTL_WRITE); 525 526 for (i = 0; i < 32; i++) 527 dc_mii_writebit(sc, 1); 528 529 return; 530 } 531 532 /* 533 * Clock a series of bits through the MII. 534 */ 535 static void dc_mii_send(sc, bits, cnt) 536 struct dc_softc *sc; 537 u_int32_t bits; 538 int cnt; 539 { 540 int i; 541 542 for (i = (0x1 << (cnt - 1)); i; i >>= 1) 543 dc_mii_writebit(sc, bits & i); 544 } 545 546 /* 547 * Read an PHY register through the MII. 548 */ 549 static int dc_mii_readreg(sc, frame) 550 struct dc_softc *sc; 551 struct dc_mii_frame *frame; 552 553 { 554 int i, ack, s; 555 556 s = splimp(); 557 558 /* 559 * Set up frame for RX. 560 */ 561 frame->mii_stdelim = DC_MII_STARTDELIM; 562 frame->mii_opcode = DC_MII_READOP; 563 frame->mii_turnaround = 0; 564 frame->mii_data = 0; 565 566 /* 567 * Sync the PHYs. 568 */ 569 dc_mii_sync(sc); 570 571 /* 572 * Send command/address info. 573 */ 574 dc_mii_send(sc, frame->mii_stdelim, 2); 575 dc_mii_send(sc, frame->mii_opcode, 2); 576 dc_mii_send(sc, frame->mii_phyaddr, 5); 577 dc_mii_send(sc, frame->mii_regaddr, 5); 578 579 #ifdef notdef 580 /* Idle bit */ 581 dc_mii_writebit(sc, 1); 582 dc_mii_writebit(sc, 0); 583 #endif 584 585 /* Check for ack */ 586 ack = dc_mii_readbit(sc); 587 588 /* 589 * Now try reading data bits. If the ack failed, we still 590 * need to clock through 16 cycles to keep the PHY(s) in sync. 591 */ 592 if (ack) { 593 for(i = 0; i < 16; i++) { 594 dc_mii_readbit(sc); 595 } 596 goto fail; 597 } 598 599 for (i = 0x8000; i; i >>= 1) { 600 if (!ack) { 601 if (dc_mii_readbit(sc)) 602 frame->mii_data |= i; 603 } 604 } 605 606 fail: 607 608 dc_mii_writebit(sc, 0); 609 dc_mii_writebit(sc, 0); 610 611 splx(s); 612 613 if (ack) 614 return(1); 615 return(0); 616 } 617 618 /* 619 * Write to a PHY register through the MII. 620 */ 621 static int dc_mii_writereg(sc, frame) 622 struct dc_softc *sc; 623 struct dc_mii_frame *frame; 624 625 { 626 int s; 627 628 s = splimp(); 629 /* 630 * Set up frame for TX. 631 */ 632 633 frame->mii_stdelim = DC_MII_STARTDELIM; 634 frame->mii_opcode = DC_MII_WRITEOP; 635 frame->mii_turnaround = DC_MII_TURNAROUND; 636 637 /* 638 * Sync the PHYs. 639 */ 640 dc_mii_sync(sc); 641 642 dc_mii_send(sc, frame->mii_stdelim, 2); 643 dc_mii_send(sc, frame->mii_opcode, 2); 644 dc_mii_send(sc, frame->mii_phyaddr, 5); 645 dc_mii_send(sc, frame->mii_regaddr, 5); 646 dc_mii_send(sc, frame->mii_turnaround, 2); 647 dc_mii_send(sc, frame->mii_data, 16); 648 649 /* Idle bit. */ 650 dc_mii_writebit(sc, 0); 651 dc_mii_writebit(sc, 0); 652 653 splx(s); 654 655 return(0); 656 } 657 658 static int dc_miibus_readreg(dev, phy, reg) 659 device_t dev; 660 int phy, reg; 661 { 662 struct dc_mii_frame frame; 663 struct dc_softc *sc; 664 int i, rval, phy_reg; 665 666 sc = device_get_softc(dev); 667 bzero((char *)&frame, sizeof(frame)); 668 669 /* 670 * Note: both the AL981 and AN985 have internal PHYs, 671 * however the AL981 provides direct access to the PHY 672 * registers while the AN985 uses a serial MII interface. 673 * The AN985's MII interface is also buggy in that you 674 * can read from any MII address (0 to 31), but only address 1 675 * behaves normally. To deal with both cases, we pretend 676 * that the PHY is at MII address 1. 677 */ 678 if (DC_IS_ADMTEK(sc) && phy != DC_ADMTEK_PHYADDR) 679 return(0); 680 681 if (sc->dc_pmode == DC_PMODE_SYM) { 682 if (phy == (MII_NPHY - 1)) { 683 switch(reg) { 684 case MII_BMSR: 685 /* 686 * Fake something to make the probe 687 * code think there's a PHY here. 688 */ 689 return(BMSR_MEDIAMASK); 690 break; 691 case MII_PHYIDR1: 692 if (DC_IS_PNIC(sc)) 693 return(DC_VENDORID_LO); 694 return(DC_VENDORID_DEC); 695 break; 696 case MII_PHYIDR2: 697 if (DC_IS_PNIC(sc)) 698 return(DC_DEVICEID_82C168); 699 return(DC_DEVICEID_21143); 700 break; 701 default: 702 return(0); 703 break; 704 } 705 } else 706 return(0); 707 } 708 709 if (DC_IS_PNIC(sc)) { 710 CSR_WRITE_4(sc, DC_PN_MII, DC_PN_MIIOPCODE_READ | 711 (phy << 23) | (reg << 18)); 712 for (i = 0; i < DC_TIMEOUT; i++) { 713 DELAY(1); 714 rval = CSR_READ_4(sc, DC_PN_MII); 715 if (!(rval & DC_PN_MII_BUSY)) { 716 rval &= 0xFFFF; 717 return(rval == 0xFFFF ? 0 : rval); 718 } 719 } 720 return(0); 721 } 722 723 if (DC_IS_COMET(sc)) { 724 switch(reg) { 725 case MII_BMCR: 726 phy_reg = DC_AL_BMCR; 727 break; 728 case MII_BMSR: 729 phy_reg = DC_AL_BMSR; 730 break; 731 case MII_PHYIDR1: 732 phy_reg = DC_AL_VENID; 733 break; 734 case MII_PHYIDR2: 735 phy_reg = DC_AL_DEVID; 736 break; 737 case MII_ANAR: 738 phy_reg = DC_AL_ANAR; 739 break; 740 case MII_ANLPAR: 741 phy_reg = DC_AL_LPAR; 742 break; 743 case MII_ANER: 744 phy_reg = DC_AL_ANER; 745 break; 746 default: 747 printf("dc%d: phy_read: bad phy register %x\n", 748 sc->dc_unit, reg); 749 return(0); 750 break; 751 } 752 753 rval = CSR_READ_4(sc, phy_reg) & 0x0000FFFF; 754 755 if (rval == 0xFFFF) 756 return(0); 757 return(rval); 758 } 759 760 frame.mii_phyaddr = phy; 761 frame.mii_regaddr = reg; 762 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL); 763 dc_mii_readreg(sc, &frame); 764 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL); 765 766 return(frame.mii_data); 767 } 768 769 static int dc_miibus_writereg(dev, phy, reg, data) 770 device_t dev; 771 int phy, reg, data; 772 { 773 struct dc_softc *sc; 774 struct dc_mii_frame frame; 775 int i, phy_reg; 776 777 sc = device_get_softc(dev); 778 bzero((char *)&frame, sizeof(frame)); 779 780 if (DC_IS_ADMTEK(sc) && phy != DC_ADMTEK_PHYADDR) 781 return(0); 782 783 if (DC_IS_PNIC(sc)) { 784 CSR_WRITE_4(sc, DC_PN_MII, DC_PN_MIIOPCODE_WRITE | 785 (phy << 23) | (reg << 10) | data); 786 for (i = 0; i < DC_TIMEOUT; i++) { 787 if (!(CSR_READ_4(sc, DC_PN_MII) & DC_PN_MII_BUSY)) 788 break; 789 } 790 return(0); 791 } 792 793 if (DC_IS_COMET(sc)) { 794 switch(reg) { 795 case MII_BMCR: 796 phy_reg = DC_AL_BMCR; 797 break; 798 case MII_BMSR: 799 phy_reg = DC_AL_BMSR; 800 break; 801 case MII_PHYIDR1: 802 phy_reg = DC_AL_VENID; 803 break; 804 case MII_PHYIDR2: 805 phy_reg = DC_AL_DEVID; 806 break; 807 case MII_ANAR: 808 phy_reg = DC_AL_ANAR; 809 break; 810 case MII_ANLPAR: 811 phy_reg = DC_AL_LPAR; 812 break; 813 case MII_ANER: 814 phy_reg = DC_AL_ANER; 815 break; 816 default: 817 printf("dc%d: phy_write: bad phy register %x\n", 818 sc->dc_unit, reg); 819 return(0); 820 break; 821 } 822 823 CSR_WRITE_4(sc, phy_reg, data); 824 return(0); 825 } 826 827 frame.mii_phyaddr = phy; 828 frame.mii_regaddr = reg; 829 frame.mii_data = data; 830 831 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL); 832 dc_mii_writereg(sc, &frame); 833 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL); 834 835 return(0); 836 } 837 838 static void dc_miibus_statchg(dev) 839 device_t dev; 840 { 841 struct dc_softc *sc; 842 struct mii_data *mii; 843 844 sc = device_get_softc(dev); 845 if (DC_IS_ADMTEK(sc)) 846 return; 847 mii = device_get_softc(sc->dc_miibus); 848 dc_setcfg(sc, mii->mii_media_active); 849 sc->dc_if_media = mii->mii_media_active; 850 851 return; 852 } 853 854 #define DC_POLY 0xEDB88320 855 #define DC_BITS 9 856 #define DC_BITS_PNIC_II 7 857 858 static u_int32_t dc_crc_le(sc, addr) 859 struct dc_softc *sc; 860 caddr_t addr; 861 { 862 u_int32_t idx, bit, data, crc; 863 864 /* Compute CRC for the address value. */ 865 crc = 0xFFFFFFFF; /* initial value */ 866 867 for (idx = 0; idx < 6; idx++) { 868 for (data = *addr++, bit = 0; bit < 8; bit++, data >>= 1) 869 crc = (crc >> 1) ^ (((crc ^ data) & 1) ? DC_POLY : 0); 870 } 871 872 /* The hash table on the PNIC II is only 128 bits wide. */ 873 if (DC_IS_PNICII(sc)) 874 return (crc & ((1 << DC_BITS_PNIC_II) - 1)); 875 876 return (crc & ((1 << DC_BITS) - 1)); 877 } 878 879 /* 880 * Calculate CRC of a multicast group address, return the lower 6 bits. 881 */ 882 static u_int32_t dc_crc_be(addr) 883 caddr_t addr; 884 { 885 u_int32_t crc, carry; 886 int i, j; 887 u_int8_t c; 888 889 /* Compute CRC for the address value. */ 890 crc = 0xFFFFFFFF; /* initial value */ 891 892 for (i = 0; i < 6; i++) { 893 c = *(addr + i); 894 for (j = 0; j < 8; j++) { 895 carry = ((crc & 0x80000000) ? 1 : 0) ^ (c & 0x01); 896 crc <<= 1; 897 c >>= 1; 898 if (carry) 899 crc = (crc ^ 0x04c11db6) | carry; 900 } 901 } 902 903 /* return the filter bit position */ 904 return((crc >> 26) & 0x0000003F); 905 } 906 907 /* 908 * 21143-style RX filter setup routine. Filter programming is done by 909 * downloading a special setup frame into the TX engine. 21143, Macronix, 910 * PNIC, PNIC II and Davicom chips are programmed this way. 911 * 912 * We always program the chip using 'hash perfect' mode, i.e. one perfect 913 * address (our node address) and a 512-bit hash filter for multicast 914 * frames. We also sneak the broadcast address into the hash filter since 915 * we need that too. 916 */ 917 void dc_setfilt_21143(sc) 918 struct dc_softc *sc; 919 { 920 struct dc_desc *sframe; 921 u_int32_t h, *sp; 922 struct ifmultiaddr *ifma; 923 struct ifnet *ifp; 924 int i; 925 926 ifp = &sc->arpcom.ac_if; 927 928 i = sc->dc_cdata.dc_tx_prod; 929 DC_INC(sc->dc_cdata.dc_tx_prod, DC_TX_LIST_CNT); 930 sc->dc_cdata.dc_tx_cnt++; 931 sframe = &sc->dc_ldata->dc_tx_list[i]; 932 sp = (u_int32_t *)&sc->dc_cdata.dc_sbuf; 933 bzero((char *)sp, DC_SFRAME_LEN); 934 935 sframe->dc_data = vtophys(&sc->dc_cdata.dc_sbuf); 936 sframe->dc_ctl = DC_SFRAME_LEN | DC_TXCTL_SETUP | DC_TXCTL_TLINK | 937 DC_FILTER_HASHPERF | DC_TXCTL_FINT; 938 939 sc->dc_cdata.dc_tx_chain[i] = (struct mbuf *)&sc->dc_cdata.dc_sbuf; 940 941 /* If we want promiscuous mode, set the allframes bit. */ 942 if (ifp->if_flags & IFF_PROMISC) 943 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC); 944 else 945 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC); 946 947 if (ifp->if_flags & IFF_ALLMULTI) 948 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI); 949 else 950 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI); 951 952 for (ifma = ifp->if_multiaddrs.lh_first; ifma != NULL; 953 ifma = ifma->ifma_link.le_next) { 954 if (ifma->ifma_addr->sa_family != AF_LINK) 955 continue; 956 h = dc_crc_le(sc, 957 LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 958 sp[h >> 4] |= 1 << (h & 0xF); 959 } 960 961 if (ifp->if_flags & IFF_BROADCAST) { 962 h = dc_crc_le(sc, (caddr_t)ðerbroadcastaddr); 963 sp[h >> 4] |= 1 << (h & 0xF); 964 } 965 966 /* Set our MAC address */ 967 sp[39] = ((u_int16_t *)sc->arpcom.ac_enaddr)[0]; 968 sp[40] = ((u_int16_t *)sc->arpcom.ac_enaddr)[1]; 969 sp[41] = ((u_int16_t *)sc->arpcom.ac_enaddr)[2]; 970 971 sframe->dc_status = DC_TXSTAT_OWN; 972 CSR_WRITE_4(sc, DC_TXSTART, 0xFFFFFFFF); 973 974 /* 975 * The PNIC takes an exceedingly long time to process its 976 * setup frame; wait 10ms after posting the setup frame 977 * before proceeding, just so it has time to swallow its 978 * medicine. 979 */ 980 DELAY(10000); 981 982 ifp->if_timer = 5; 983 984 return; 985 } 986 987 void dc_setfilt_admtek(sc) 988 struct dc_softc *sc; 989 { 990 struct ifnet *ifp; 991 int h = 0; 992 u_int32_t hashes[2] = { 0, 0 }; 993 struct ifmultiaddr *ifma; 994 995 ifp = &sc->arpcom.ac_if; 996 997 /* Init our MAC address */ 998 CSR_WRITE_4(sc, DC_AL_PAR0, *(u_int32_t *)(&sc->arpcom.ac_enaddr[0])); 999 CSR_WRITE_4(sc, DC_AL_PAR1, *(u_int32_t *)(&sc->arpcom.ac_enaddr[4])); 1000 1001 /* If we want promiscuous mode, set the allframes bit. */ 1002 if (ifp->if_flags & IFF_PROMISC) 1003 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC); 1004 else 1005 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC); 1006 1007 if (ifp->if_flags & IFF_ALLMULTI) 1008 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI); 1009 else 1010 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI); 1011 1012 /* first, zot all the existing hash bits */ 1013 CSR_WRITE_4(sc, DC_AL_MAR0, 0); 1014 CSR_WRITE_4(sc, DC_AL_MAR1, 0); 1015 1016 /* 1017 * If we're already in promisc or allmulti mode, we 1018 * don't have to bother programming the multicast filter. 1019 */ 1020 if (ifp->if_flags & (IFF_PROMISC|IFF_ALLMULTI)) 1021 return; 1022 1023 /* now program new ones */ 1024 for (ifma = ifp->if_multiaddrs.lh_first; ifma != NULL; 1025 ifma = ifma->ifma_link.le_next) { 1026 if (ifma->ifma_addr->sa_family != AF_LINK) 1027 continue; 1028 h = dc_crc_be(LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 1029 if (h < 32) 1030 hashes[0] |= (1 << h); 1031 else 1032 hashes[1] |= (1 << (h - 32)); 1033 } 1034 1035 CSR_WRITE_4(sc, DC_AL_MAR0, hashes[0]); 1036 CSR_WRITE_4(sc, DC_AL_MAR1, hashes[1]); 1037 1038 return; 1039 } 1040 1041 void dc_setfilt_asix(sc) 1042 struct dc_softc *sc; 1043 { 1044 struct ifnet *ifp; 1045 int h = 0; 1046 u_int32_t hashes[2] = { 0, 0 }; 1047 struct ifmultiaddr *ifma; 1048 1049 ifp = &sc->arpcom.ac_if; 1050 1051 /* Init our MAC address */ 1052 CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_PAR0); 1053 CSR_WRITE_4(sc, DC_AX_FILTDATA, 1054 *(u_int32_t *)(&sc->arpcom.ac_enaddr[0])); 1055 CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_PAR1); 1056 CSR_WRITE_4(sc, DC_AX_FILTDATA, 1057 *(u_int32_t *)(&sc->arpcom.ac_enaddr[4])); 1058 1059 /* If we want promiscuous mode, set the allframes bit. */ 1060 if (ifp->if_flags & IFF_PROMISC) 1061 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC); 1062 else 1063 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC); 1064 1065 if (ifp->if_flags & IFF_ALLMULTI) 1066 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI); 1067 else 1068 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI); 1069 1070 /* 1071 * The ASIX chip has a special bit to enable reception 1072 * of broadcast frames. 1073 */ 1074 if (ifp->if_flags & IFF_BROADCAST) 1075 DC_SETBIT(sc, DC_NETCFG, DC_AX_NETCFG_RX_BROAD); 1076 else 1077 DC_CLRBIT(sc, DC_NETCFG, DC_AX_NETCFG_RX_BROAD); 1078 1079 /* first, zot all the existing hash bits */ 1080 CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_MAR0); 1081 CSR_WRITE_4(sc, DC_AX_FILTDATA, 0); 1082 CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_MAR1); 1083 CSR_WRITE_4(sc, DC_AX_FILTDATA, 0); 1084 1085 /* 1086 * If we're already in promisc or allmulti mode, we 1087 * don't have to bother programming the multicast filter. 1088 */ 1089 if (ifp->if_flags & (IFF_PROMISC|IFF_ALLMULTI)) 1090 return; 1091 1092 /* now program new ones */ 1093 for (ifma = ifp->if_multiaddrs.lh_first; ifma != NULL; 1094 ifma = ifma->ifma_link.le_next) { 1095 if (ifma->ifma_addr->sa_family != AF_LINK) 1096 continue; 1097 h = dc_crc_be(LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 1098 if (h < 32) 1099 hashes[0] |= (1 << h); 1100 else 1101 hashes[1] |= (1 << (h - 32)); 1102 } 1103 1104 CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_MAR0); 1105 CSR_WRITE_4(sc, DC_AX_FILTDATA, hashes[0]); 1106 CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_MAR1); 1107 CSR_WRITE_4(sc, DC_AX_FILTDATA, hashes[1]); 1108 1109 return; 1110 } 1111 1112 static void dc_setfilt(sc) 1113 struct dc_softc *sc; 1114 { 1115 if (DC_IS_INTEL(sc) || DC_IS_MACRONIX(sc) || DC_IS_PNIC(sc) || 1116 DC_IS_PNICII(sc) || DC_IS_DAVICOM(sc)) 1117 dc_setfilt_21143(sc); 1118 1119 if (DC_IS_ASIX(sc)) 1120 dc_setfilt_asix(sc); 1121 1122 if (DC_IS_ADMTEK(sc)) 1123 dc_setfilt_admtek(sc); 1124 1125 return; 1126 } 1127 1128 /* 1129 * In order to fiddle with the 1130 * 'full-duplex' and '100Mbps' bits in the netconfig register, we 1131 * first have to put the transmit and/or receive logic in the idle state. 1132 */ 1133 static void dc_setcfg(sc, media) 1134 struct dc_softc *sc; 1135 int media; 1136 { 1137 int i, restart = 0; 1138 u_int32_t isr; 1139 1140 if (IFM_SUBTYPE(media) == IFM_NONE) 1141 return; 1142 1143 if (CSR_READ_4(sc, DC_NETCFG) & (DC_NETCFG_TX_ON|DC_NETCFG_RX_ON)) { 1144 restart = 1; 1145 DC_CLRBIT(sc, DC_NETCFG, (DC_NETCFG_TX_ON|DC_NETCFG_RX_ON)); 1146 1147 for (i = 0; i < DC_TIMEOUT; i++) { 1148 DELAY(10); 1149 isr = CSR_READ_4(sc, DC_ISR); 1150 if (isr & DC_ISR_TX_IDLE || 1151 (isr & DC_ISR_RX_STATE) == DC_RXSTATE_STOPPED) 1152 break; 1153 } 1154 1155 if (i == DC_TIMEOUT) 1156 printf("dc%d: failed to force tx and " 1157 "rx to idle state\n", sc->dc_unit); 1158 1159 } 1160 1161 if (IFM_SUBTYPE(media) == IFM_100_TX) { 1162 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_SPEEDSEL); 1163 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_HEARTBEAT); 1164 if (sc->dc_pmode == DC_PMODE_MII) { 1165 DC_SETBIT(sc, DC_WATCHDOG, DC_WDOG_JABBERDIS); 1166 DC_CLRBIT(sc, DC_NETCFG, (DC_NETCFG_PCS| 1167 DC_NETCFG_PORTSEL|DC_NETCFG_SCRAMBLER)); 1168 if (sc->dc_type == DC_TYPE_98713) 1169 DC_SETBIT(sc, DC_NETCFG, (DC_NETCFG_PCS| 1170 DC_NETCFG_SCRAMBLER)); 1171 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL); 1172 DC_CLRBIT(sc, DC_10BTCTRL, 0xFFFF); 1173 } else { 1174 if (DC_IS_PNIC(sc)) { 1175 DC_PN_GPIO_SETBIT(sc, DC_PN_GPIO_SPEEDSEL); 1176 DC_PN_GPIO_SETBIT(sc, DC_PN_GPIO_100TX_LOOP); 1177 DC_SETBIT(sc, DC_PN_NWAY, DC_PN_NWAY_SPEEDSEL); 1178 } 1179 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL| 1180 DC_NETCFG_PCS|DC_NETCFG_SCRAMBLER); 1181 } 1182 } 1183 1184 if (IFM_SUBTYPE(media) == IFM_10_T) { 1185 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_SPEEDSEL); 1186 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_HEARTBEAT); 1187 if (sc->dc_pmode == DC_PMODE_MII) { 1188 DC_SETBIT(sc, DC_WATCHDOG, DC_WDOG_JABBERDIS); 1189 DC_CLRBIT(sc, DC_NETCFG, (DC_NETCFG_PCS| 1190 DC_NETCFG_PORTSEL|DC_NETCFG_SCRAMBLER)); 1191 if (sc->dc_type == DC_TYPE_98713) 1192 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PCS); 1193 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL); 1194 DC_CLRBIT(sc, DC_10BTCTRL, 0xFFFF); 1195 } else { 1196 if (DC_IS_PNIC(sc)) { 1197 DC_PN_GPIO_CLRBIT(sc, DC_PN_GPIO_SPEEDSEL); 1198 DC_PN_GPIO_SETBIT(sc, DC_PN_GPIO_100TX_LOOP); 1199 DC_CLRBIT(sc, DC_PN_NWAY, DC_PN_NWAY_SPEEDSEL); 1200 } 1201 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL); 1202 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_SCRAMBLER); 1203 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PCS); 1204 } 1205 } 1206 1207 if ((media & IFM_GMASK) == IFM_FDX) { 1208 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_FULLDUPLEX); 1209 if (sc->dc_pmode == DC_PMODE_SYM && DC_IS_PNIC(sc)) 1210 DC_SETBIT(sc, DC_PN_NWAY, DC_PN_NWAY_DUPLEX); 1211 } else { 1212 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_FULLDUPLEX); 1213 if (sc->dc_pmode == DC_PMODE_SYM && DC_IS_PNIC(sc)) 1214 DC_CLRBIT(sc, DC_PN_NWAY, DC_PN_NWAY_DUPLEX); 1215 } 1216 1217 if (restart) 1218 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_TX_ON|DC_NETCFG_RX_ON); 1219 1220 return; 1221 } 1222 1223 static void dc_reset(sc) 1224 struct dc_softc *sc; 1225 { 1226 register int i; 1227 1228 DC_SETBIT(sc, DC_BUSCTL, DC_BUSCTL_RESET); 1229 1230 for (i = 0; i < DC_TIMEOUT; i++) { 1231 DELAY(10); 1232 if (!(CSR_READ_4(sc, DC_BUSCTL) & DC_BUSCTL_RESET)) 1233 break; 1234 } 1235 1236 if (DC_IS_ASIX(sc) || DC_IS_ADMTEK(sc)) { 1237 DELAY(10000); 1238 DC_CLRBIT(sc, DC_BUSCTL, DC_BUSCTL_RESET); 1239 i = 0; 1240 } 1241 1242 if (i == DC_TIMEOUT) 1243 printf("dc%d: reset never completed!\n", sc->dc_unit); 1244 1245 /* Wait a little while for the chip to get its brains in order. */ 1246 DELAY(1000); 1247 1248 CSR_WRITE_4(sc, DC_IMR, 0x00000000); 1249 CSR_WRITE_4(sc, DC_BUSCTL, 0x00000000); 1250 CSR_WRITE_4(sc, DC_NETCFG, 0x00000000); 1251 1252 /* 1253 * Bring the SIA out of reset. In some cases, it looks 1254 * like failing to unreset the SIA soon enough gets it 1255 * into a state where it will never come out of reset 1256 * until we reset the whole chip again. 1257 */ 1258 if (DC_IS_INTEL(sc)) 1259 DC_SETBIT(sc, DC_SIARESET, DC_SIA_RESET); 1260 1261 return; 1262 } 1263 1264 static struct dc_type *dc_devtype(dev) 1265 device_t dev; 1266 { 1267 struct dc_type *t; 1268 u_int32_t rev; 1269 1270 t = dc_devs; 1271 1272 while(t->dc_name != NULL) { 1273 if ((pci_get_vendor(dev) == t->dc_vid) && 1274 (pci_get_device(dev) == t->dc_did)) { 1275 /* Check the PCI revision */ 1276 rev = pci_read_config(dev, DC_PCI_CFRV, 4) & 0xFF; 1277 if (t->dc_did == DC_DEVICEID_98713 && 1278 rev >= DC_REVISION_98713A) 1279 t++; 1280 if (t->dc_did == DC_DEVICEID_98713_CP && 1281 rev >= DC_REVISION_98713A) 1282 t++; 1283 if (t->dc_did == DC_DEVICEID_987x5 && 1284 rev >= DC_REVISION_98725) 1285 t++; 1286 if (t->dc_did == DC_DEVICEID_AX88140A && 1287 rev >= DC_REVISION_88141) 1288 t++; 1289 if (t->dc_did == DC_DEVICEID_82C168 && 1290 rev >= DC_REVISION_82C169) 1291 t++; 1292 return(t); 1293 } 1294 t++; 1295 } 1296 1297 return(NULL); 1298 } 1299 1300 /* 1301 * Probe for a 21143 or clone chip. Check the PCI vendor and device 1302 * IDs against our list and return a device name if we find a match. 1303 * We do a little bit of extra work to identify the exact type of 1304 * chip. The MX98713 and MX98713A have the same PCI vendor/device ID, 1305 * but different revision IDs. The same is true for 98715/98715A 1306 * chips and the 98725, as well as the ASIX and ADMtek chips. In some 1307 * cases, the exact chip revision affects driver behavior. 1308 */ 1309 static int dc_probe(dev) 1310 device_t dev; 1311 { 1312 struct dc_type *t; 1313 1314 t = dc_devtype(dev); 1315 1316 if (t != NULL) { 1317 device_set_desc(dev, t->dc_name); 1318 return(0); 1319 } 1320 1321 return(ENXIO); 1322 } 1323 1324 static void dc_acpi(dev) 1325 device_t dev; 1326 { 1327 u_int32_t r, cptr; 1328 int unit; 1329 1330 unit = device_get_unit(dev); 1331 1332 /* Find the location of the capabilities block */ 1333 cptr = pci_read_config(dev, DC_PCI_CCAP, 4) & 0xFF; 1334 1335 r = pci_read_config(dev, cptr, 4) & 0xFF; 1336 if (r == 0x01) { 1337 1338 r = pci_read_config(dev, cptr + 4, 4); 1339 if (r & DC_PSTATE_D3) { 1340 u_int32_t iobase, membase, irq; 1341 1342 /* Save important PCI config data. */ 1343 iobase = pci_read_config(dev, DC_PCI_CFBIO, 4); 1344 membase = pci_read_config(dev, DC_PCI_CFBMA, 4); 1345 irq = pci_read_config(dev, DC_PCI_CFIT, 4); 1346 1347 /* Reset the power state. */ 1348 printf("dc%d: chip is in D%d power mode " 1349 "-- setting to D0\n", unit, r & DC_PSTATE_D3); 1350 r &= 0xFFFFFFFC; 1351 pci_write_config(dev, cptr + 4, r, 4); 1352 1353 /* Restore PCI config data. */ 1354 pci_write_config(dev, DC_PCI_CFBIO, iobase, 4); 1355 pci_write_config(dev, DC_PCI_CFBMA, membase, 4); 1356 pci_write_config(dev, DC_PCI_CFIT, irq, 4); 1357 } 1358 } 1359 return; 1360 } 1361 1362 /* 1363 * Attach the interface. Allocate softc structures, do ifmedia 1364 * setup and ethernet/BPF attach. 1365 */ 1366 static int dc_attach(dev) 1367 device_t dev; 1368 { 1369 int s; 1370 u_char eaddr[ETHER_ADDR_LEN]; 1371 u_int32_t command; 1372 struct dc_softc *sc; 1373 struct ifnet *ifp; 1374 u_int32_t revision; 1375 int unit, error = 0, rid, mac_offset; 1376 1377 s = splimp(); 1378 1379 sc = device_get_softc(dev); 1380 unit = device_get_unit(dev); 1381 bzero(sc, sizeof(struct dc_softc)); 1382 1383 /* 1384 * Handle power management nonsense. 1385 */ 1386 dc_acpi(dev); 1387 1388 /* 1389 * Map control/status registers. 1390 */ 1391 command = pci_read_config(dev, PCI_COMMAND_STATUS_REG, 4); 1392 command |= (PCIM_CMD_PORTEN|PCIM_CMD_MEMEN|PCIM_CMD_BUSMASTEREN); 1393 pci_write_config(dev, PCI_COMMAND_STATUS_REG, command, 4); 1394 command = pci_read_config(dev, PCI_COMMAND_STATUS_REG, 4); 1395 1396 #ifdef DC_USEIOSPACE 1397 if (!(command & PCIM_CMD_PORTEN)) { 1398 printf("dc%d: failed to enable I/O ports!\n", unit); 1399 error = ENXIO; 1400 goto fail; 1401 } 1402 #else 1403 if (!(command & PCIM_CMD_MEMEN)) { 1404 printf("dc%d: failed to enable memory mapping!\n", unit); 1405 error = ENXIO; 1406 goto fail; 1407 } 1408 #endif 1409 1410 rid = DC_RID; 1411 sc->dc_res = bus_alloc_resource(dev, DC_RES, &rid, 1412 0, ~0, 1, RF_ACTIVE); 1413 1414 if (sc->dc_res == NULL) { 1415 printf("dc%d: couldn't map ports/memory\n", unit); 1416 error = ENXIO; 1417 goto fail; 1418 } 1419 1420 sc->dc_btag = rman_get_bustag(sc->dc_res); 1421 sc->dc_bhandle = rman_get_bushandle(sc->dc_res); 1422 1423 /* Allocate interrupt */ 1424 rid = 0; 1425 sc->dc_irq = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, 0, ~0, 1, 1426 RF_SHAREABLE | RF_ACTIVE); 1427 1428 if (sc->dc_irq == NULL) { 1429 printf("dc%d: couldn't map interrupt\n", unit); 1430 bus_release_resource(dev, DC_RES, DC_RID, sc->dc_res); 1431 error = ENXIO; 1432 goto fail; 1433 } 1434 1435 error = bus_setup_intr(dev, sc->dc_irq, INTR_TYPE_NET, 1436 dc_intr, sc, &sc->dc_intrhand); 1437 1438 if (error) { 1439 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->dc_irq); 1440 bus_release_resource(dev, DC_RES, DC_RID, sc->dc_res); 1441 printf("dc%d: couldn't set up irq\n", unit); 1442 goto fail; 1443 } 1444 1445 /* Need this info to decide on a chip type. */ 1446 sc->dc_info = dc_devtype(dev); 1447 revision = pci_read_config(dev, DC_PCI_CFRV, 4) & 0x000000FF; 1448 1449 switch(sc->dc_info->dc_did) { 1450 case DC_DEVICEID_21143: 1451 sc->dc_type = DC_TYPE_21143; 1452 sc->dc_flags |= DC_TX_POLL|DC_TX_USE_TX_INTR; 1453 sc->dc_flags |= DC_REDUCED_MII_POLL; 1454 break; 1455 case DC_DEVICEID_DM9100: 1456 case DC_DEVICEID_DM9102: 1457 sc->dc_type = DC_TYPE_DM9102; 1458 sc->dc_flags |= DC_TX_COALESCE|DC_TX_USE_TX_INTR; 1459 sc->dc_flags |= DC_REDUCED_MII_POLL; 1460 sc->dc_pmode = DC_PMODE_MII; 1461 break; 1462 case DC_DEVICEID_AL981: 1463 sc->dc_type = DC_TYPE_AL981; 1464 sc->dc_flags |= DC_TX_USE_TX_INTR; 1465 sc->dc_flags |= DC_TX_ADMTEK_WAR; 1466 sc->dc_pmode = DC_PMODE_MII; 1467 break; 1468 case DC_DEVICEID_AN985: 1469 sc->dc_type = DC_TYPE_AN985; 1470 sc->dc_flags |= DC_TX_USE_TX_INTR; 1471 sc->dc_flags |= DC_TX_ADMTEK_WAR; 1472 sc->dc_pmode = DC_PMODE_MII; 1473 break; 1474 case DC_DEVICEID_98713: 1475 case DC_DEVICEID_98713_CP: 1476 if (revision < DC_REVISION_98713A) { 1477 sc->dc_type = DC_TYPE_98713; 1478 sc->dc_flags |= DC_REDUCED_MII_POLL; 1479 } 1480 if (revision >= DC_REVISION_98713A) 1481 sc->dc_type = DC_TYPE_98713A; 1482 sc->dc_flags |= DC_TX_POLL|DC_TX_USE_TX_INTR; 1483 break; 1484 case DC_DEVICEID_987x5: 1485 sc->dc_type = DC_TYPE_987x5; 1486 sc->dc_flags |= DC_TX_POLL|DC_TX_USE_TX_INTR; 1487 break; 1488 case DC_DEVICEID_82C115: 1489 sc->dc_type = DC_TYPE_PNICII; 1490 sc->dc_flags |= DC_TX_POLL|DC_TX_USE_TX_INTR; 1491 break; 1492 case DC_DEVICEID_82C168: 1493 sc->dc_type = DC_TYPE_PNIC; 1494 sc->dc_flags |= DC_TX_STORENFWD|DC_TX_INTR_ALWAYS; 1495 sc->dc_flags |= DC_PNIC_RX_BUG_WAR; 1496 sc->dc_pnic_rx_buf = malloc(DC_RXLEN * 5, M_DEVBUF, M_NOWAIT); 1497 if (revision < DC_REVISION_82C169) 1498 sc->dc_pmode = DC_PMODE_SYM; 1499 break; 1500 case DC_DEVICEID_AX88140A: 1501 sc->dc_type = DC_TYPE_ASIX; 1502 sc->dc_flags |= DC_TX_USE_TX_INTR|DC_TX_INTR_FIRSTFRAG; 1503 sc->dc_flags |= DC_REDUCED_MII_POLL; 1504 sc->dc_pmode = DC_PMODE_MII; 1505 break; 1506 default: 1507 printf("dc%d: unknown device: %x\n", sc->dc_unit, 1508 sc->dc_info->dc_did); 1509 break; 1510 } 1511 1512 /* Save the cache line size. */ 1513 sc->dc_cachesize = pci_read_config(dev, DC_PCI_CFLT, 4) & 0xFF; 1514 1515 /* Reset the adapter. */ 1516 dc_reset(sc); 1517 1518 /* Take 21143 out of snooze mode */ 1519 if (DC_IS_INTEL(sc)) { 1520 command = pci_read_config(dev, DC_PCI_CFDD, 4); 1521 command &= ~(DC_CFDD_SNOOZE_MODE|DC_CFDD_SLEEP_MODE); 1522 pci_write_config(dev, DC_PCI_CFDD, command, 4); 1523 } 1524 1525 /* 1526 * Try to learn something about the supported media. 1527 * We know that ASIX and ADMtek and Davicom devices 1528 * will *always* be using MII media, so that's a no-brainer. 1529 * The tricky ones are the Macronix/PNIC II and the 1530 * Intel 21143. 1531 */ 1532 if (DC_IS_INTEL(sc)) { 1533 u_int32_t media, cwuc; 1534 cwuc = pci_read_config(dev, DC_PCI_CWUC, 4); 1535 cwuc |= DC_CWUC_FORCE_WUL; 1536 pci_write_config(dev, DC_PCI_CWUC, cwuc, 4); 1537 DELAY(10000); 1538 media = pci_read_config(dev, DC_PCI_CWUC, 4); 1539 cwuc &= ~DC_CWUC_FORCE_WUL; 1540 pci_write_config(dev, DC_PCI_CWUC, cwuc, 4); 1541 DELAY(10000); 1542 if (media & DC_CWUC_MII_ABILITY) 1543 sc->dc_pmode = DC_PMODE_MII; 1544 if (media & DC_CWUC_SYM_ABILITY) 1545 sc->dc_pmode = DC_PMODE_SYM; 1546 /* 1547 * If none of the bits are set, then this NIC 1548 * isn't meant to support 'wake up LAN' mode. 1549 * This is usually only the case on multiport 1550 * cards, and these cards almost always have 1551 * MII transceivers. 1552 */ 1553 if (media == 0) 1554 sc->dc_pmode = DC_PMODE_MII; 1555 } else if (DC_IS_MACRONIX(sc) || DC_IS_PNICII(sc)) { 1556 if (sc->dc_type == DC_TYPE_98713) 1557 sc->dc_pmode = DC_PMODE_MII; 1558 else 1559 sc->dc_pmode = DC_PMODE_SYM; 1560 } else if (!sc->dc_pmode) 1561 sc->dc_pmode = DC_PMODE_MII; 1562 1563 /* 1564 * Get station address from the EEPROM. 1565 */ 1566 switch(sc->dc_type) { 1567 case DC_TYPE_98713: 1568 case DC_TYPE_98713A: 1569 case DC_TYPE_987x5: 1570 case DC_TYPE_PNICII: 1571 dc_read_eeprom(sc, (caddr_t)&mac_offset, 1572 (DC_EE_NODEADDR_OFFSET / 2), 1, 0); 1573 dc_read_eeprom(sc, (caddr_t)&eaddr, (mac_offset / 2), 3, 0); 1574 break; 1575 case DC_TYPE_PNIC: 1576 dc_read_eeprom(sc, (caddr_t)&eaddr, 0, 3, 1); 1577 break; 1578 case DC_TYPE_DM9102: 1579 case DC_TYPE_21143: 1580 case DC_TYPE_ASIX: 1581 dc_read_eeprom(sc, (caddr_t)&eaddr, DC_EE_NODEADDR, 3, 0); 1582 break; 1583 case DC_TYPE_AL981: 1584 case DC_TYPE_AN985: 1585 dc_read_eeprom(sc, (caddr_t)&eaddr, DC_AL_EE_NODEADDR, 3, 0); 1586 break; 1587 default: 1588 dc_read_eeprom(sc, (caddr_t)&eaddr, DC_EE_NODEADDR, 3, 0); 1589 break; 1590 } 1591 1592 /* 1593 * A 21143 or clone chip was detected. Inform the world. 1594 */ 1595 printf("dc%d: Ethernet address: %6D\n", unit, eaddr, ":"); 1596 1597 sc->dc_unit = unit; 1598 bcopy(eaddr, (char *)&sc->arpcom.ac_enaddr, ETHER_ADDR_LEN); 1599 1600 sc->dc_ldata = contigmalloc(sizeof(struct dc_list_data), M_DEVBUF, 1601 M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0); 1602 1603 if (sc->dc_ldata == NULL) { 1604 printf("dc%d: no memory for list buffers!\n", unit); 1605 bus_teardown_intr(dev, sc->dc_irq, sc->dc_intrhand); 1606 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->dc_irq); 1607 bus_release_resource(dev, DC_RES, DC_RID, sc->dc_res); 1608 error = ENXIO; 1609 goto fail; 1610 } 1611 1612 bzero(sc->dc_ldata, sizeof(struct dc_list_data)); 1613 1614 ifp = &sc->arpcom.ac_if; 1615 ifp->if_softc = sc; 1616 ifp->if_unit = unit; 1617 ifp->if_name = "dc"; 1618 ifp->if_mtu = ETHERMTU; 1619 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 1620 ifp->if_ioctl = dc_ioctl; 1621 ifp->if_output = ether_output; 1622 ifp->if_start = dc_start; 1623 ifp->if_watchdog = dc_watchdog; 1624 ifp->if_init = dc_init; 1625 ifp->if_baudrate = 10000000; 1626 ifp->if_snd.ifq_maxlen = DC_TX_LIST_CNT - 1; 1627 1628 /* 1629 * Do MII setup. 1630 */ 1631 error = mii_phy_probe(dev, &sc->dc_miibus, 1632 dc_ifmedia_upd, dc_ifmedia_sts); 1633 1634 if (error && DC_IS_INTEL(sc)) { 1635 sc->dc_pmode = DC_PMODE_SYM; 1636 mii_phy_probe(dev, &sc->dc_miibus, 1637 dc_ifmedia_upd, dc_ifmedia_sts); 1638 error = 0; 1639 } 1640 1641 if (error) { 1642 printf("dc%d: MII without any PHY!\n", sc->dc_unit); 1643 bus_teardown_intr(dev, sc->dc_irq, sc->dc_intrhand); 1644 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->dc_irq); 1645 bus_release_resource(dev, DC_RES, DC_RID, sc->dc_res); 1646 error = ENXIO; 1647 goto fail; 1648 } 1649 1650 /* 1651 * Call MI attach routines. 1652 */ 1653 if_attach(ifp); 1654 ether_ifattach(ifp); 1655 callout_handle_init(&sc->dc_stat_ch); 1656 1657 bpfattach(ifp, DLT_EN10MB, sizeof(struct ether_header)); 1658 1659 fail: 1660 splx(s); 1661 1662 return(error); 1663 } 1664 1665 static int dc_detach(dev) 1666 device_t dev; 1667 { 1668 struct dc_softc *sc; 1669 struct ifnet *ifp; 1670 int s; 1671 1672 s = splimp(); 1673 1674 sc = device_get_softc(dev); 1675 ifp = &sc->arpcom.ac_if; 1676 1677 dc_stop(sc); 1678 if_detach(ifp); 1679 1680 bus_generic_detach(dev); 1681 device_delete_child(dev, sc->dc_miibus); 1682 1683 bus_teardown_intr(dev, sc->dc_irq, sc->dc_intrhand); 1684 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->dc_irq); 1685 bus_release_resource(dev, DC_RES, DC_RID, sc->dc_res); 1686 1687 contigfree(sc->dc_ldata, sizeof(struct dc_list_data), M_DEVBUF); 1688 if (sc->dc_pnic_rx_buf != NULL) 1689 free(sc->dc_pnic_rx_buf, M_DEVBUF); 1690 1691 splx(s); 1692 1693 return(0); 1694 } 1695 1696 /* 1697 * Initialize the transmit descriptors. 1698 */ 1699 static int dc_list_tx_init(sc) 1700 struct dc_softc *sc; 1701 { 1702 struct dc_chain_data *cd; 1703 struct dc_list_data *ld; 1704 int i; 1705 1706 cd = &sc->dc_cdata; 1707 ld = sc->dc_ldata; 1708 for (i = 0; i < DC_TX_LIST_CNT; i++) { 1709 if (i == (DC_TX_LIST_CNT - 1)) { 1710 ld->dc_tx_list[i].dc_next = 1711 vtophys(&ld->dc_tx_list[0]); 1712 } else { 1713 ld->dc_tx_list[i].dc_next = 1714 vtophys(&ld->dc_tx_list[i + 1]); 1715 } 1716 cd->dc_tx_chain[i] = NULL; 1717 ld->dc_tx_list[i].dc_data = 0; 1718 ld->dc_tx_list[i].dc_ctl = 0; 1719 } 1720 1721 cd->dc_tx_prod = cd->dc_tx_cons = cd->dc_tx_cnt = 0; 1722 1723 return(0); 1724 } 1725 1726 1727 /* 1728 * Initialize the RX descriptors and allocate mbufs for them. Note that 1729 * we arrange the descriptors in a closed ring, so that the last descriptor 1730 * points back to the first. 1731 */ 1732 static int dc_list_rx_init(sc) 1733 struct dc_softc *sc; 1734 { 1735 struct dc_chain_data *cd; 1736 struct dc_list_data *ld; 1737 int i; 1738 1739 cd = &sc->dc_cdata; 1740 ld = sc->dc_ldata; 1741 1742 for (i = 0; i < DC_RX_LIST_CNT; i++) { 1743 if (dc_newbuf(sc, i, NULL) == ENOBUFS) 1744 return(ENOBUFS); 1745 if (i == (DC_RX_LIST_CNT - 1)) { 1746 ld->dc_rx_list[i].dc_next = 1747 vtophys(&ld->dc_rx_list[0]); 1748 } else { 1749 ld->dc_rx_list[i].dc_next = 1750 vtophys(&ld->dc_rx_list[i + 1]); 1751 } 1752 } 1753 1754 cd->dc_rx_prod = 0; 1755 1756 return(0); 1757 } 1758 1759 /* 1760 * Initialize an RX descriptor and attach an MBUF cluster. 1761 */ 1762 static int dc_newbuf(sc, i, m) 1763 struct dc_softc *sc; 1764 int i; 1765 struct mbuf *m; 1766 { 1767 struct mbuf *m_new = NULL; 1768 struct dc_desc *c; 1769 1770 c = &sc->dc_ldata->dc_rx_list[i]; 1771 1772 if (m == NULL) { 1773 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 1774 if (m_new == NULL) { 1775 printf("dc%d: no memory for rx list " 1776 "-- packet dropped!\n", sc->dc_unit); 1777 return(ENOBUFS); 1778 } 1779 1780 MCLGET(m_new, M_DONTWAIT); 1781 if (!(m_new->m_flags & M_EXT)) { 1782 printf("dc%d: no memory for rx list " 1783 "-- packet dropped!\n", sc->dc_unit); 1784 m_freem(m_new); 1785 return(ENOBUFS); 1786 } 1787 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 1788 } else { 1789 m_new = m; 1790 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 1791 m_new->m_data = m_new->m_ext.ext_buf; 1792 } 1793 1794 m_adj(m_new, sizeof(u_int64_t)); 1795 1796 /* 1797 * If this is a PNIC chip, zero the buffer. This is part 1798 * of the workaround for the receive bug in the 82c168 and 1799 * 82c169 chips. 1800 */ 1801 if (sc->dc_flags & DC_PNIC_RX_BUG_WAR) 1802 bzero((char *)mtod(m_new, char *), m_new->m_len); 1803 1804 sc->dc_cdata.dc_rx_chain[i] = m_new; 1805 c->dc_data = vtophys(mtod(m_new, caddr_t)); 1806 c->dc_ctl = DC_RXCTL_RLINK | DC_RXLEN; 1807 c->dc_status = DC_RXSTAT_OWN; 1808 1809 return(0); 1810 } 1811 1812 /* 1813 * Grrrrr. 1814 * The PNIC chip has a terrible bug in it that manifests itself during 1815 * periods of heavy activity. The exact mode of failure if difficult to 1816 * pinpoint: sometimes it only happens in promiscuous mode, sometimes it 1817 * will happen on slow machines. The bug is that sometimes instead of 1818 * uploading one complete frame during reception, it uploads what looks 1819 * like the entire contents of its FIFO memory. The frame we want is at 1820 * the end of the whole mess, but we never know exactly how much data has 1821 * been uploaded, so salvaging the frame is hard. 1822 * 1823 * There is only one way to do it reliably, and it's disgusting. 1824 * Here's what we know: 1825 * 1826 * - We know there will always be somewhere between one and three extra 1827 * descriptors uploaded. 1828 * 1829 * - We know the desired received frame will always be at the end of the 1830 * total data upload. 1831 * 1832 * - We know the size of the desired received frame because it will be 1833 * provided in the length field of the status word in the last descriptor. 1834 * 1835 * Here's what we do: 1836 * 1837 * - When we allocate buffers for the receive ring, we bzero() them. 1838 * This means that we know that the buffer contents should be all 1839 * zeros, except for data uploaded by the chip. 1840 * 1841 * - We also force the PNIC chip to upload frames that include the 1842 * ethernet CRC at the end. 1843 * 1844 * - We gather all of the bogus frame data into a single buffer. 1845 * 1846 * - We then position a pointer at the end of this buffer and scan 1847 * backwards until we encounter the first non-zero byte of data. 1848 * This is the end of the received frame. We know we will encounter 1849 * some data at the end of the frame because the CRC will always be 1850 * there, so even if the sender transmits a packet of all zeros, 1851 * we won't be fooled. 1852 * 1853 * - We know the size of the actual received frame, so we subtract 1854 * that value from the current pointer location. This brings us 1855 * to the start of the actual received packet. 1856 * 1857 * - We copy this into an mbuf and pass it on, along with the actual 1858 * frame length. 1859 * 1860 * The performance hit is tremendous, but it beats dropping frames all 1861 * the time. 1862 */ 1863 1864 #define DC_WHOLEFRAME (DC_RXSTAT_FIRSTFRAG|DC_RXSTAT_LASTFRAG) 1865 static void dc_pnic_rx_bug_war(sc, idx) 1866 struct dc_softc *sc; 1867 int idx; 1868 { 1869 struct dc_desc *cur_rx; 1870 struct dc_desc *c = NULL; 1871 struct mbuf *m = NULL; 1872 unsigned char *ptr; 1873 int i, total_len; 1874 u_int32_t rxstat = 0; 1875 1876 i = sc->dc_pnic_rx_bug_save; 1877 cur_rx = &sc->dc_ldata->dc_rx_list[idx]; 1878 ptr = sc->dc_pnic_rx_buf; 1879 bzero(ptr, sizeof(DC_RXLEN * 5)); 1880 1881 /* Copy all the bytes from the bogus buffers. */ 1882 while (1) { 1883 c = &sc->dc_ldata->dc_rx_list[i]; 1884 rxstat = c->dc_status; 1885 m = sc->dc_cdata.dc_rx_chain[i]; 1886 bcopy(mtod(m, char *), ptr, DC_RXLEN); 1887 ptr += DC_RXLEN; 1888 /* If this is the last buffer, break out. */ 1889 if (i == idx || rxstat & DC_RXSTAT_LASTFRAG) 1890 break; 1891 dc_newbuf(sc, i, m); 1892 DC_INC(i, DC_RX_LIST_CNT); 1893 } 1894 1895 /* Find the length of the actual receive frame. */ 1896 total_len = DC_RXBYTES(rxstat); 1897 1898 /* Scan backwards until we hit a non-zero byte. */ 1899 while(*ptr == 0x00) 1900 ptr--; 1901 1902 /* Round off. */ 1903 if ((uintptr_t)(ptr) & 0x3) 1904 ptr -= 1; 1905 1906 /* Now find the start of the frame. */ 1907 ptr -= total_len; 1908 if (ptr < sc->dc_pnic_rx_buf) 1909 ptr = sc->dc_pnic_rx_buf; 1910 1911 /* 1912 * Now copy the salvaged frame to the last mbuf and fake up 1913 * the status word to make it look like a successful 1914 * frame reception. 1915 */ 1916 dc_newbuf(sc, i, m); 1917 bcopy(ptr, mtod(m, char *), total_len); 1918 cur_rx->dc_status = rxstat | DC_RXSTAT_FIRSTFRAG; 1919 1920 return; 1921 } 1922 1923 /* 1924 * This routine searches the RX ring for dirty descriptors in the 1925 * event that the rxeof routine falls out of sync with the chip's 1926 * current descriptor pointer. This may happen sometimes as a result 1927 * of a "no RX buffer available" condition that happens when the chip 1928 * consumes all of the RX buffers before the driver has a chance to 1929 * process the RX ring. This routine may need to be called more than 1930 * once to bring the driver back in sync with the chip, however we 1931 * should still be getting RX DONE interrupts to drive the search 1932 * for new packets in the RX ring, so we should catch up eventually. 1933 */ 1934 static int dc_rx_resync(sc) 1935 struct dc_softc *sc; 1936 { 1937 int i, pos; 1938 struct dc_desc *cur_rx; 1939 1940 pos = sc->dc_cdata.dc_rx_prod; 1941 1942 for (i = 0; i < DC_RX_LIST_CNT; i++) { 1943 cur_rx = &sc->dc_ldata->dc_rx_list[pos]; 1944 if (!(cur_rx->dc_status & DC_RXSTAT_OWN)) 1945 break; 1946 DC_INC(pos, DC_RX_LIST_CNT); 1947 } 1948 1949 /* If the ring really is empty, then just return. */ 1950 if (i == DC_RX_LIST_CNT) 1951 return(0); 1952 1953 /* We've fallen behing the chip: catch it. */ 1954 sc->dc_cdata.dc_rx_prod = pos; 1955 1956 return(EAGAIN); 1957 } 1958 1959 /* 1960 * A frame has been uploaded: pass the resulting mbuf chain up to 1961 * the higher level protocols. 1962 */ 1963 static void dc_rxeof(sc) 1964 struct dc_softc *sc; 1965 { 1966 struct ether_header *eh; 1967 struct mbuf *m; 1968 struct ifnet *ifp; 1969 struct dc_desc *cur_rx; 1970 int i, total_len = 0; 1971 u_int32_t rxstat; 1972 1973 ifp = &sc->arpcom.ac_if; 1974 i = sc->dc_cdata.dc_rx_prod; 1975 1976 while(!(sc->dc_ldata->dc_rx_list[i].dc_status & DC_RXSTAT_OWN)) { 1977 struct mbuf *m0 = NULL; 1978 1979 cur_rx = &sc->dc_ldata->dc_rx_list[i]; 1980 rxstat = cur_rx->dc_status; 1981 m = sc->dc_cdata.dc_rx_chain[i]; 1982 total_len = DC_RXBYTES(rxstat); 1983 1984 if (sc->dc_flags & DC_PNIC_RX_BUG_WAR) { 1985 if ((rxstat & DC_WHOLEFRAME) != DC_WHOLEFRAME) { 1986 if (rxstat & DC_RXSTAT_FIRSTFRAG) 1987 sc->dc_pnic_rx_bug_save = i; 1988 if ((rxstat & DC_RXSTAT_LASTFRAG) == 0) { 1989 DC_INC(i, DC_RX_LIST_CNT); 1990 continue; 1991 } 1992 dc_pnic_rx_bug_war(sc, i); 1993 rxstat = cur_rx->dc_status; 1994 total_len = DC_RXBYTES(rxstat); 1995 } 1996 } 1997 1998 sc->dc_cdata.dc_rx_chain[i] = NULL; 1999 2000 /* 2001 * If an error occurs, update stats, clear the 2002 * status word and leave the mbuf cluster in place: 2003 * it should simply get re-used next time this descriptor 2004 * comes up in the ring. 2005 */ 2006 if (rxstat & DC_RXSTAT_RXERR) { 2007 ifp->if_ierrors++; 2008 if (rxstat & DC_RXSTAT_COLLSEEN) 2009 ifp->if_collisions++; 2010 dc_newbuf(sc, i, m); 2011 if (rxstat & DC_RXSTAT_CRCERR) { 2012 DC_INC(i, DC_RX_LIST_CNT); 2013 continue; 2014 } else { 2015 dc_init(sc); 2016 return; 2017 } 2018 } 2019 2020 /* No errors; receive the packet. */ 2021 total_len -= ETHER_CRC_LEN; 2022 2023 m0 = m_devget(mtod(m, char *) - ETHER_ALIGN, 2024 total_len + ETHER_ALIGN, 0, ifp, NULL); 2025 dc_newbuf(sc, i, m); 2026 DC_INC(i, DC_RX_LIST_CNT); 2027 if (m0 == NULL) { 2028 ifp->if_ierrors++; 2029 continue; 2030 } 2031 m_adj(m0, ETHER_ALIGN); 2032 m = m0; 2033 2034 ifp->if_ipackets++; 2035 eh = mtod(m, struct ether_header *); 2036 2037 /* 2038 * Handle BPF listeners. Let the BPF user see the packet, but 2039 * don't pass it up to the ether_input() layer unless it's 2040 * a broadcast packet, multicast packet, matches our ethernet 2041 * address or the interface is in promiscuous mode. 2042 */ 2043 if (ifp->if_bpf) { 2044 bpf_mtap(ifp, m); 2045 if (ifp->if_flags & IFF_PROMISC && 2046 (bcmp(eh->ether_dhost, sc->arpcom.ac_enaddr, 2047 ETHER_ADDR_LEN) && 2048 (eh->ether_dhost[0] & 1) == 0)) { 2049 m_freem(m); 2050 continue; 2051 } 2052 } 2053 2054 /* Remove header from mbuf and pass it on. */ 2055 m_adj(m, sizeof(struct ether_header)); 2056 ether_input(ifp, eh, m); 2057 } 2058 2059 sc->dc_cdata.dc_rx_prod = i; 2060 2061 return; 2062 } 2063 2064 /* 2065 * A frame was downloaded to the chip. It's safe for us to clean up 2066 * the list buffers. 2067 */ 2068 2069 static void dc_txeof(sc) 2070 struct dc_softc *sc; 2071 { 2072 struct dc_desc *cur_tx = NULL; 2073 struct ifnet *ifp; 2074 int idx; 2075 2076 ifp = &sc->arpcom.ac_if; 2077 2078 /* Clear the timeout timer. */ 2079 ifp->if_timer = 0; 2080 2081 /* 2082 * Go through our tx list and free mbufs for those 2083 * frames that have been transmitted. 2084 */ 2085 idx = sc->dc_cdata.dc_tx_cons; 2086 while(idx != sc->dc_cdata.dc_tx_prod) { 2087 u_int32_t txstat; 2088 2089 cur_tx = &sc->dc_ldata->dc_tx_list[idx]; 2090 txstat = cur_tx->dc_status; 2091 2092 if (txstat & DC_TXSTAT_OWN) 2093 break; 2094 2095 if (!(cur_tx->dc_ctl & DC_TXCTL_LASTFRAG) || 2096 cur_tx->dc_ctl & DC_TXCTL_SETUP) { 2097 sc->dc_cdata.dc_tx_cnt--; 2098 if (cur_tx->dc_ctl & DC_TXCTL_SETUP) { 2099 /* 2100 * Yes, the PNIC is so brain damaged 2101 * that it will sometimes generate a TX 2102 * underrun error while DMAing the RX 2103 * filter setup frame. If we detect this, 2104 * we have to send the setup frame again, 2105 * or else the filter won't be programmed 2106 * correctly. 2107 */ 2108 if (DC_IS_PNIC(sc)) { 2109 if (txstat & DC_TXSTAT_ERRSUM) 2110 dc_setfilt(sc); 2111 } 2112 sc->dc_cdata.dc_tx_chain[idx] = NULL; 2113 } 2114 DC_INC(idx, DC_TX_LIST_CNT); 2115 continue; 2116 } 2117 2118 if (/*sc->dc_type == DC_TYPE_21143 &&*/ 2119 sc->dc_pmode == DC_PMODE_MII && 2120 ((txstat & 0xFFFF) & ~(DC_TXSTAT_ERRSUM| 2121 DC_TXSTAT_NOCARRIER|DC_TXSTAT_CARRLOST))) 2122 txstat &= ~DC_TXSTAT_ERRSUM; 2123 2124 if (txstat & DC_TXSTAT_ERRSUM) { 2125 ifp->if_oerrors++; 2126 if (txstat & DC_TXSTAT_EXCESSCOLL) 2127 ifp->if_collisions++; 2128 if (txstat & DC_TXSTAT_LATECOLL) 2129 ifp->if_collisions++; 2130 if (!(txstat & DC_TXSTAT_UNDERRUN)) { 2131 dc_init(sc); 2132 return; 2133 } 2134 } 2135 2136 ifp->if_collisions += (txstat & DC_TXSTAT_COLLCNT) >> 3; 2137 2138 ifp->if_opackets++; 2139 if (sc->dc_cdata.dc_tx_chain[idx] != NULL) { 2140 m_freem(sc->dc_cdata.dc_tx_chain[idx]); 2141 sc->dc_cdata.dc_tx_chain[idx] = NULL; 2142 } 2143 2144 sc->dc_cdata.dc_tx_cnt--; 2145 DC_INC(idx, DC_TX_LIST_CNT); 2146 } 2147 2148 sc->dc_cdata.dc_tx_cons = idx; 2149 if (cur_tx != NULL) 2150 ifp->if_flags &= ~IFF_OACTIVE; 2151 2152 return; 2153 } 2154 2155 static void dc_tick(xsc) 2156 void *xsc; 2157 { 2158 struct dc_softc *sc; 2159 struct mii_data *mii; 2160 struct ifnet *ifp; 2161 int s; 2162 u_int32_t r; 2163 2164 s = splimp(); 2165 2166 sc = xsc; 2167 ifp = &sc->arpcom.ac_if; 2168 mii = device_get_softc(sc->dc_miibus); 2169 2170 if (sc->dc_flags & DC_REDUCED_MII_POLL) { 2171 r = CSR_READ_4(sc, DC_ISR); 2172 if (DC_IS_INTEL(sc)) { 2173 if (r & DC_ISR_LINKFAIL) 2174 sc->dc_link = 0; 2175 if (sc->dc_link == 0) 2176 mii_tick(mii); 2177 } else { 2178 if ((r & DC_ISR_RX_STATE) == DC_RXSTATE_WAIT && 2179 sc->dc_cdata.dc_tx_prod == 0) 2180 mii_tick(mii); 2181 } 2182 } else 2183 mii_tick(mii); 2184 2185 /* 2186 * When the init routine completes, we expect to be able to send 2187 * packets right away, and in fact the network code will send a 2188 * gratuitous ARP the moment the init routine marks the interface 2189 * as running. However, even though the MAC may have been initialized, 2190 * there may be a delay of a few seconds before the PHY completes 2191 * autonegotiation and the link is brought up. Any transmissions 2192 * made during that delay will be lost. Dealing with this is tricky: 2193 * we can't just pause in the init routine while waiting for the 2194 * PHY to come ready since that would bring the whole system to 2195 * a screeching halt for several seconds. 2196 * 2197 * What we do here is prevent the TX start routine from sending 2198 * any packets until a link has been established. After the 2199 * interface has been initialized, the tick routine will poll 2200 * the state of the PHY until the IFM_ACTIVE flag is set. Until 2201 * that time, packets will stay in the send queue, and once the 2202 * link comes up, they will be flushed out to the wire. 2203 */ 2204 if (!sc->dc_link) { 2205 mii_pollstat(mii); 2206 if (mii->mii_media_status & IFM_ACTIVE && 2207 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) { 2208 sc->dc_link++; 2209 if (ifp->if_snd.ifq_head != NULL) 2210 dc_start(ifp); 2211 } 2212 } 2213 2214 sc->dc_stat_ch = timeout(dc_tick, sc, hz); 2215 2216 splx(s); 2217 2218 return; 2219 } 2220 2221 static void dc_intr(arg) 2222 void *arg; 2223 { 2224 struct dc_softc *sc; 2225 struct ifnet *ifp; 2226 u_int32_t status; 2227 2228 sc = arg; 2229 ifp = &sc->arpcom.ac_if; 2230 2231 /* Supress unwanted interrupts */ 2232 if (!(ifp->if_flags & IFF_UP)) { 2233 if (CSR_READ_4(sc, DC_ISR) & DC_INTRS) 2234 dc_stop(sc); 2235 return; 2236 } 2237 2238 /* Disable interrupts. */ 2239 CSR_WRITE_4(sc, DC_IMR, 0x00000000); 2240 2241 while((status = CSR_READ_4(sc, DC_ISR)) & DC_INTRS) { 2242 2243 CSR_WRITE_4(sc, DC_ISR, status); 2244 2245 if (status & DC_ISR_RX_OK) { 2246 int curpkts; 2247 curpkts = ifp->if_ipackets; 2248 dc_rxeof(sc); 2249 if (curpkts == ifp->if_ipackets) { 2250 while(dc_rx_resync(sc)) 2251 dc_rxeof(sc); 2252 } 2253 } 2254 2255 if (status & (DC_ISR_TX_OK|DC_ISR_TX_NOBUF)) 2256 dc_txeof(sc); 2257 2258 if (status & DC_ISR_TX_IDLE) { 2259 dc_txeof(sc); 2260 if (sc->dc_cdata.dc_tx_cnt) { 2261 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_TX_ON); 2262 CSR_WRITE_4(sc, DC_TXSTART, 0xFFFFFFFF); 2263 } 2264 } 2265 2266 if (status & DC_ISR_TX_UNDERRUN) { 2267 u_int32_t cfg; 2268 2269 printf("dc%d: TX underrun -- ", sc->dc_unit); 2270 if (DC_IS_DAVICOM(sc) || DC_IS_INTEL(sc)) 2271 dc_init(sc); 2272 cfg = CSR_READ_4(sc, DC_NETCFG); 2273 cfg &= ~DC_NETCFG_TX_THRESH; 2274 if (sc->dc_txthresh == DC_TXTHRESH_160BYTES) { 2275 printf("using store and forward mode\n"); 2276 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_STORENFWD); 2277 } else if (sc->dc_flags & DC_TX_STORENFWD) { 2278 printf("resetting\n"); 2279 } else { 2280 sc->dc_txthresh += 0x4000; 2281 printf("increasing TX threshold\n"); 2282 CSR_WRITE_4(sc, DC_NETCFG, cfg); 2283 DC_SETBIT(sc, DC_NETCFG, sc->dc_txthresh); 2284 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_STORENFWD); 2285 } 2286 } 2287 2288 if ((status & DC_ISR_RX_WATDOGTIMEO) 2289 || (status & DC_ISR_RX_NOBUF)) { 2290 int curpkts; 2291 curpkts = ifp->if_ipackets; 2292 dc_rxeof(sc); 2293 if (curpkts == ifp->if_ipackets) { 2294 while(dc_rx_resync(sc)) 2295 dc_rxeof(sc); 2296 } 2297 } 2298 2299 if (status & DC_ISR_BUS_ERR) { 2300 dc_reset(sc); 2301 dc_init(sc); 2302 } 2303 } 2304 2305 /* Re-enable interrupts. */ 2306 CSR_WRITE_4(sc, DC_IMR, DC_INTRS); 2307 2308 if (ifp->if_snd.ifq_head != NULL) 2309 dc_start(ifp); 2310 2311 return; 2312 } 2313 2314 /* 2315 * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data 2316 * pointers to the fragment pointers. 2317 */ 2318 static int dc_encap(sc, m_head, txidx) 2319 struct dc_softc *sc; 2320 struct mbuf *m_head; 2321 u_int32_t *txidx; 2322 { 2323 struct dc_desc *f = NULL; 2324 struct mbuf *m; 2325 int frag, cur, cnt = 0; 2326 2327 /* 2328 * Start packing the mbufs in this chain into 2329 * the fragment pointers. Stop when we run out 2330 * of fragments or hit the end of the mbuf chain. 2331 */ 2332 m = m_head; 2333 cur = frag = *txidx; 2334 2335 for (m = m_head; m != NULL; m = m->m_next) { 2336 if (m->m_len != 0) { 2337 if (sc->dc_flags & DC_TX_ADMTEK_WAR) { 2338 if (*txidx != sc->dc_cdata.dc_tx_prod && 2339 frag == (DC_TX_LIST_CNT - 1)) 2340 return(ENOBUFS); 2341 } 2342 if ((DC_TX_LIST_CNT - 2343 (sc->dc_cdata.dc_tx_cnt + cnt)) < 5) 2344 return(ENOBUFS); 2345 2346 f = &sc->dc_ldata->dc_tx_list[frag]; 2347 f->dc_ctl = DC_TXCTL_TLINK | m->m_len; 2348 if (cnt == 0) { 2349 f->dc_status = 0; 2350 f->dc_ctl |= DC_TXCTL_FIRSTFRAG; 2351 } else 2352 f->dc_status = DC_TXSTAT_OWN; 2353 f->dc_data = vtophys(mtod(m, vm_offset_t)); 2354 cur = frag; 2355 DC_INC(frag, DC_TX_LIST_CNT); 2356 cnt++; 2357 } 2358 } 2359 2360 if (m != NULL) 2361 return(ENOBUFS); 2362 2363 sc->dc_cdata.dc_tx_cnt += cnt; 2364 sc->dc_cdata.dc_tx_chain[cur] = m_head; 2365 sc->dc_ldata->dc_tx_list[cur].dc_ctl |= DC_TXCTL_LASTFRAG; 2366 if (sc->dc_flags & DC_TX_INTR_FIRSTFRAG) 2367 sc->dc_ldata->dc_tx_list[*txidx].dc_ctl |= DC_TXCTL_FINT; 2368 if (sc->dc_flags & DC_TX_INTR_ALWAYS) 2369 sc->dc_ldata->dc_tx_list[cur].dc_ctl |= DC_TXCTL_FINT; 2370 if (sc->dc_flags & DC_TX_USE_TX_INTR && sc->dc_cdata.dc_tx_cnt > 64) 2371 sc->dc_ldata->dc_tx_list[cur].dc_ctl |= DC_TXCTL_FINT; 2372 sc->dc_ldata->dc_tx_list[*txidx].dc_status = DC_TXSTAT_OWN; 2373 *txidx = frag; 2374 2375 return(0); 2376 } 2377 2378 /* 2379 * Coalesce an mbuf chain into a single mbuf cluster buffer. 2380 * Needed for some really badly behaved chips that just can't 2381 * do scatter/gather correctly. 2382 */ 2383 static int dc_coal(sc, m_head) 2384 struct dc_softc *sc; 2385 struct mbuf **m_head; 2386 { 2387 struct mbuf *m_new, *m; 2388 2389 m = *m_head; 2390 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 2391 if (m_new == NULL) { 2392 printf("dc%d: no memory for tx list", sc->dc_unit); 2393 return(ENOBUFS); 2394 } 2395 if (m->m_pkthdr.len > MHLEN) { 2396 MCLGET(m_new, M_DONTWAIT); 2397 if (!(m_new->m_flags & M_EXT)) { 2398 m_freem(m_new); 2399 printf("dc%d: no memory for tx list", sc->dc_unit); 2400 return(ENOBUFS); 2401 } 2402 } 2403 m_copydata(m, 0, m->m_pkthdr.len, mtod(m_new, caddr_t)); 2404 m_new->m_pkthdr.len = m_new->m_len = m->m_pkthdr.len; 2405 m_freem(m); 2406 *m_head = m_new; 2407 2408 return(0); 2409 } 2410 2411 /* 2412 * Main transmit routine. To avoid having to do mbuf copies, we put pointers 2413 * to the mbuf data regions directly in the transmit lists. We also save a 2414 * copy of the pointers since the transmit list fragment pointers are 2415 * physical addresses. 2416 */ 2417 2418 static void dc_start(ifp) 2419 struct ifnet *ifp; 2420 { 2421 struct dc_softc *sc; 2422 struct mbuf *m_head = NULL; 2423 int idx; 2424 2425 sc = ifp->if_softc; 2426 2427 if (!sc->dc_link) 2428 return; 2429 2430 if (ifp->if_flags & IFF_OACTIVE) 2431 return; 2432 2433 idx = sc->dc_cdata.dc_tx_prod; 2434 2435 while(sc->dc_cdata.dc_tx_chain[idx] == NULL) { 2436 IF_DEQUEUE(&ifp->if_snd, m_head); 2437 if (m_head == NULL) 2438 break; 2439 2440 if (sc->dc_flags & DC_TX_COALESCE) { 2441 if (dc_coal(sc, &m_head)) { 2442 IF_PREPEND(&ifp->if_snd, m_head); 2443 ifp->if_flags |= IFF_OACTIVE; 2444 break; 2445 } 2446 } 2447 2448 if (dc_encap(sc, m_head, &idx)) { 2449 IF_PREPEND(&ifp->if_snd, m_head); 2450 ifp->if_flags |= IFF_OACTIVE; 2451 break; 2452 } 2453 2454 /* 2455 * If there's a BPF listener, bounce a copy of this frame 2456 * to him. 2457 */ 2458 if (ifp->if_bpf) 2459 bpf_mtap(ifp, m_head); 2460 } 2461 2462 /* Transmit */ 2463 sc->dc_cdata.dc_tx_prod = idx; 2464 if (!(sc->dc_flags & DC_TX_POLL)) 2465 CSR_WRITE_4(sc, DC_TXSTART, 0xFFFFFFFF); 2466 2467 /* 2468 * Set a timeout in case the chip goes out to lunch. 2469 */ 2470 ifp->if_timer = 5; 2471 2472 return; 2473 } 2474 2475 static void dc_init(xsc) 2476 void *xsc; 2477 { 2478 struct dc_softc *sc = xsc; 2479 struct ifnet *ifp = &sc->arpcom.ac_if; 2480 struct mii_data *mii; 2481 int s; 2482 2483 s = splimp(); 2484 2485 mii = device_get_softc(sc->dc_miibus); 2486 2487 /* 2488 * Cancel pending I/O and free all RX/TX buffers. 2489 */ 2490 dc_stop(sc); 2491 dc_reset(sc); 2492 2493 /* 2494 * Set cache alignment and burst length. 2495 */ 2496 if (DC_IS_ASIX(sc)) 2497 CSR_WRITE_4(sc, DC_BUSCTL, 0); 2498 else 2499 CSR_WRITE_4(sc, DC_BUSCTL, DC_BUSCTL_MRME|DC_BUSCTL_MRLE); 2500 if (DC_IS_DAVICOM(sc) || DC_IS_INTEL(sc)) { 2501 DC_SETBIT(sc, DC_BUSCTL, DC_BURSTLEN_USECA); 2502 } else { 2503 DC_SETBIT(sc, DC_BUSCTL, DC_BURSTLEN_16LONG); 2504 } 2505 if (sc->dc_flags & DC_TX_POLL) 2506 DC_SETBIT(sc, DC_BUSCTL, DC_TXPOLL_1); 2507 switch(sc->dc_cachesize) { 2508 case 32: 2509 DC_SETBIT(sc, DC_BUSCTL, DC_CACHEALIGN_32LONG); 2510 break; 2511 case 16: 2512 DC_SETBIT(sc, DC_BUSCTL, DC_CACHEALIGN_16LONG); 2513 break; 2514 case 8: 2515 DC_SETBIT(sc, DC_BUSCTL, DC_CACHEALIGN_8LONG); 2516 break; 2517 case 0: 2518 default: 2519 DC_SETBIT(sc, DC_BUSCTL, DC_CACHEALIGN_NONE); 2520 break; 2521 } 2522 2523 if (sc->dc_flags & DC_TX_STORENFWD) 2524 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_STORENFWD); 2525 else { 2526 if (sc->dc_txthresh == DC_TXTHRESH_160BYTES) { 2527 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_STORENFWD); 2528 } else { 2529 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_STORENFWD); 2530 DC_SETBIT(sc, DC_NETCFG, sc->dc_txthresh); 2531 } 2532 } 2533 2534 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_NO_RXCRC); 2535 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_TX_BACKOFF); 2536 2537 if (DC_IS_MACRONIX(sc) || DC_IS_PNICII(sc)) { 2538 /* 2539 * The app notes for the 98713 and 98715A say that 2540 * in order to have the chips operate properly, a magic 2541 * number must be written to CSR16. Macronix does not 2542 * document the meaning of these bits so there's no way 2543 * to know exactly what they do. The 98713 has a magic 2544 * number all its own; the rest all use a different one. 2545 */ 2546 DC_CLRBIT(sc, DC_MX_MAGICPACKET, 0xFFFF0000); 2547 if (sc->dc_type == DC_TYPE_98713) 2548 DC_SETBIT(sc, DC_MX_MAGICPACKET, DC_MX_MAGIC_98713); 2549 else 2550 DC_SETBIT(sc, DC_MX_MAGICPACKET, DC_MX_MAGIC_98715); 2551 } 2552 2553 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_TX_THRESH); 2554 DC_SETBIT(sc, DC_NETCFG, DC_TXTHRESH_72BYTES); 2555 2556 /* Init circular RX list. */ 2557 if (dc_list_rx_init(sc) == ENOBUFS) { 2558 printf("dc%d: initialization failed: no " 2559 "memory for rx buffers\n", sc->dc_unit); 2560 dc_stop(sc); 2561 (void)splx(s); 2562 return; 2563 } 2564 2565 /* 2566 * Init tx descriptors. 2567 */ 2568 dc_list_tx_init(sc); 2569 2570 /* 2571 * Load the address of the RX list. 2572 */ 2573 CSR_WRITE_4(sc, DC_RXADDR, vtophys(&sc->dc_ldata->dc_rx_list[0])); 2574 CSR_WRITE_4(sc, DC_TXADDR, vtophys(&sc->dc_ldata->dc_tx_list[0])); 2575 2576 /* 2577 * Enable interrupts. 2578 */ 2579 CSR_WRITE_4(sc, DC_IMR, DC_INTRS); 2580 CSR_WRITE_4(sc, DC_ISR, 0xFFFFFFFF); 2581 2582 /* Enable transmitter. */ 2583 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_TX_ON); 2584 2585 /* 2586 * Load the RX/multicast filter. We do this sort of late 2587 * because the filter programming scheme on the 21143 and 2588 * some clones requires DMAing a setup frame via the TX 2589 * engine, and we need the transmitter enabled for that. 2590 */ 2591 dc_setfilt(sc); 2592 2593 /* Enable receiver. */ 2594 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_ON); 2595 CSR_WRITE_4(sc, DC_RXSTART, 0xFFFFFFFF); 2596 2597 mii_mediachg(mii); 2598 dc_setcfg(sc, sc->dc_if_media); 2599 2600 ifp->if_flags |= IFF_RUNNING; 2601 ifp->if_flags &= ~IFF_OACTIVE; 2602 2603 (void)splx(s); 2604 2605 sc->dc_stat_ch = timeout(dc_tick, sc, hz); 2606 2607 return; 2608 } 2609 2610 /* 2611 * Set media options. 2612 */ 2613 static int dc_ifmedia_upd(ifp) 2614 struct ifnet *ifp; 2615 { 2616 struct dc_softc *sc; 2617 struct mii_data *mii; 2618 2619 sc = ifp->if_softc; 2620 mii = device_get_softc(sc->dc_miibus); 2621 mii_mediachg(mii); 2622 sc->dc_link = 0; 2623 2624 return(0); 2625 } 2626 2627 /* 2628 * Report current media status. 2629 */ 2630 static void dc_ifmedia_sts(ifp, ifmr) 2631 struct ifnet *ifp; 2632 struct ifmediareq *ifmr; 2633 { 2634 struct dc_softc *sc; 2635 struct mii_data *mii; 2636 2637 sc = ifp->if_softc; 2638 mii = device_get_softc(sc->dc_miibus); 2639 mii_pollstat(mii); 2640 ifmr->ifm_active = mii->mii_media_active; 2641 ifmr->ifm_status = mii->mii_media_status; 2642 2643 return; 2644 } 2645 2646 static int dc_ioctl(ifp, command, data) 2647 struct ifnet *ifp; 2648 u_long command; 2649 caddr_t data; 2650 { 2651 struct dc_softc *sc = ifp->if_softc; 2652 struct ifreq *ifr = (struct ifreq *) data; 2653 struct mii_data *mii; 2654 int s, error = 0; 2655 2656 s = splimp(); 2657 2658 switch(command) { 2659 case SIOCSIFADDR: 2660 case SIOCGIFADDR: 2661 case SIOCSIFMTU: 2662 error = ether_ioctl(ifp, command, data); 2663 break; 2664 case SIOCSIFFLAGS: 2665 if (ifp->if_flags & IFF_UP) { 2666 if (ifp->if_flags & IFF_RUNNING && 2667 ifp->if_flags & IFF_PROMISC && 2668 !(sc->dc_if_flags & IFF_PROMISC)) { 2669 dc_setfilt(sc); 2670 } else if (ifp->if_flags & IFF_RUNNING && 2671 !(ifp->if_flags & IFF_PROMISC) && 2672 sc->dc_if_flags & IFF_PROMISC) { 2673 dc_setfilt(sc); 2674 } else if (!(ifp->if_flags & IFF_RUNNING)) { 2675 sc->dc_txthresh = 0; 2676 dc_init(sc); 2677 } 2678 } else { 2679 if (ifp->if_flags & IFF_RUNNING) 2680 dc_stop(sc); 2681 } 2682 sc->dc_if_flags = ifp->if_flags; 2683 error = 0; 2684 break; 2685 case SIOCADDMULTI: 2686 case SIOCDELMULTI: 2687 dc_setfilt(sc); 2688 error = 0; 2689 break; 2690 case SIOCGIFMEDIA: 2691 case SIOCSIFMEDIA: 2692 mii = device_get_softc(sc->dc_miibus); 2693 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 2694 break; 2695 default: 2696 error = EINVAL; 2697 break; 2698 } 2699 2700 (void)splx(s); 2701 2702 return(error); 2703 } 2704 2705 static void dc_watchdog(ifp) 2706 struct ifnet *ifp; 2707 { 2708 struct dc_softc *sc; 2709 2710 sc = ifp->if_softc; 2711 2712 ifp->if_oerrors++; 2713 printf("dc%d: watchdog timeout\n", sc->dc_unit); 2714 2715 dc_stop(sc); 2716 dc_reset(sc); 2717 dc_init(sc); 2718 2719 if (ifp->if_snd.ifq_head != NULL) 2720 dc_start(ifp); 2721 2722 return; 2723 } 2724 2725 /* 2726 * Stop the adapter and free any mbufs allocated to the 2727 * RX and TX lists. 2728 */ 2729 static void dc_stop(sc) 2730 struct dc_softc *sc; 2731 { 2732 register int i; 2733 struct ifnet *ifp; 2734 2735 ifp = &sc->arpcom.ac_if; 2736 ifp->if_timer = 0; 2737 2738 untimeout(dc_tick, sc, sc->dc_stat_ch); 2739 2740 DC_CLRBIT(sc, DC_NETCFG, (DC_NETCFG_RX_ON|DC_NETCFG_TX_ON)); 2741 CSR_WRITE_4(sc, DC_IMR, 0x00000000); 2742 CSR_WRITE_4(sc, DC_TXADDR, 0x00000000); 2743 CSR_WRITE_4(sc, DC_RXADDR, 0x00000000); 2744 sc->dc_link = 0; 2745 2746 /* 2747 * Free data in the RX lists. 2748 */ 2749 for (i = 0; i < DC_RX_LIST_CNT; i++) { 2750 if (sc->dc_cdata.dc_rx_chain[i] != NULL) { 2751 m_freem(sc->dc_cdata.dc_rx_chain[i]); 2752 sc->dc_cdata.dc_rx_chain[i] = NULL; 2753 } 2754 } 2755 bzero((char *)&sc->dc_ldata->dc_rx_list, 2756 sizeof(sc->dc_ldata->dc_rx_list)); 2757 2758 /* 2759 * Free the TX list buffers. 2760 */ 2761 for (i = 0; i < DC_TX_LIST_CNT; i++) { 2762 if (sc->dc_cdata.dc_tx_chain[i] != NULL) { 2763 if (sc->dc_ldata->dc_tx_list[i].dc_ctl & 2764 DC_TXCTL_SETUP) { 2765 sc->dc_cdata.dc_tx_chain[i] = NULL; 2766 continue; 2767 } 2768 m_freem(sc->dc_cdata.dc_tx_chain[i]); 2769 sc->dc_cdata.dc_tx_chain[i] = NULL; 2770 } 2771 } 2772 2773 bzero((char *)&sc->dc_ldata->dc_tx_list, 2774 sizeof(sc->dc_ldata->dc_tx_list)); 2775 2776 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 2777 2778 return; 2779 } 2780 2781 /* 2782 * Stop all chip I/O so that the kernel's probe routines don't 2783 * get confused by errant DMAs when rebooting. 2784 */ 2785 static void dc_shutdown(dev) 2786 device_t dev; 2787 { 2788 struct dc_softc *sc; 2789 2790 sc = device_get_softc(dev); 2791 2792 dc_stop(sc); 2793 2794 return; 2795 } 2796