1 /* 2 * Copyright (c) 1997, 1998, 1999 3 * Bill Paul <wpaul@ee.columbia.edu>. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 3. All advertising materials mentioning features or use of this software 14 * must display the following acknowledgement: 15 * This product includes software developed by Bill Paul. 16 * 4. Neither the name of the author nor the names of any co-contributors 17 * may be used to endorse or promote products derived from this software 18 * without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30 * THE POSSIBILITY OF SUCH DAMAGE. 31 * 32 * $FreeBSD$ 33 */ 34 35 /* 36 * DEC "tulip" clone ethernet driver. Supports the DEC/Intel 21143 37 * series chips and several workalikes including the following: 38 * 39 * Macronix 98713/98715/98725/98727/98732 PMAC (www.macronix.com) 40 * Macronix/Lite-On 82c115 PNIC II (www.macronix.com) 41 * Lite-On 82c168/82c169 PNIC (www.litecom.com) 42 * ASIX Electronics AX88140A (www.asix.com.tw) 43 * ASIX Electronics AX88141 (www.asix.com.tw) 44 * ADMtek AL981 (www.admtek.com.tw) 45 * ADMtek AN985 (www.admtek.com.tw) 46 * Davicom DM9100, DM9102, DM9102A (www.davicom8.com) 47 * Accton EN1217 (www.accton.com) 48 * Xircom X3201 (www.xircom.com) 49 * Abocom FE2500 50 * 51 * Datasheets for the 21143 are available at developer.intel.com. 52 * Datasheets for the clone parts can be found at their respective sites. 53 * (Except for the PNIC; see www.freebsd.org/~wpaul/PNIC/pnic.ps.gz.) 54 * The PNIC II is essentially a Macronix 98715A chip; the only difference 55 * worth noting is that its multicast hash table is only 128 bits wide 56 * instead of 512. 57 * 58 * Written by Bill Paul <wpaul@ee.columbia.edu> 59 * Electrical Engineering Department 60 * Columbia University, New York City 61 */ 62 63 /* 64 * The Intel 21143 is the successor to the DEC 21140. It is basically 65 * the same as the 21140 but with a few new features. The 21143 supports 66 * three kinds of media attachments: 67 * 68 * o MII port, for 10Mbps and 100Mbps support and NWAY 69 * autonegotiation provided by an external PHY. 70 * o SYM port, for symbol mode 100Mbps support. 71 * o 10baseT port. 72 * o AUI/BNC port. 73 * 74 * The 100Mbps SYM port and 10baseT port can be used together in 75 * combination with the internal NWAY support to create a 10/100 76 * autosensing configuration. 77 * 78 * Note that not all tulip workalikes are handled in this driver: we only 79 * deal with those which are relatively well behaved. The Winbond is 80 * handled separately due to its different register offsets and the 81 * special handling needed for its various bugs. The PNIC is handled 82 * here, but I'm not thrilled about it. 83 * 84 * All of the workalike chips use some form of MII transceiver support 85 * with the exception of the Macronix chips, which also have a SYM port. 86 * The ASIX AX88140A is also documented to have a SYM port, but all 87 * the cards I've seen use an MII transceiver, probably because the 88 * AX88140A doesn't support internal NWAY. 89 */ 90 91 #include <sys/param.h> 92 #include <sys/systm.h> 93 #include <sys/sockio.h> 94 #include <sys/mbuf.h> 95 #include <sys/malloc.h> 96 #include <sys/kernel.h> 97 #include <sys/socket.h> 98 99 #include <net/if.h> 100 #include <net/if_arp.h> 101 #include <net/ethernet.h> 102 #include <net/if_dl.h> 103 #include <net/if_media.h> 104 105 #include <net/bpf.h> 106 107 #include <vm/vm.h> /* for vtophys */ 108 #include <vm/pmap.h> /* for vtophys */ 109 #include <machine/bus_pio.h> 110 #include <machine/bus_memio.h> 111 #include <machine/bus.h> 112 #include <machine/resource.h> 113 #include <sys/bus.h> 114 #include <sys/rman.h> 115 116 #include <dev/mii/mii.h> 117 #include <dev/mii/miivar.h> 118 119 #include <pci/pcireg.h> 120 #include <pci/pcivar.h> 121 122 #define DC_USEIOSPACE 123 #ifdef __alpha__ 124 #define SRM_MEDIA 125 #endif 126 127 #include <pci/if_dcreg.h> 128 129 MODULE_DEPEND(dc, miibus, 1, 1, 1); 130 131 /* "controller miibus0" required. See GENERIC if you get errors here. */ 132 #include "miibus_if.h" 133 134 #ifndef lint 135 static const char rcsid[] = 136 "$FreeBSD$"; 137 #endif 138 139 /* 140 * Various supported device vendors/types and their names. 141 */ 142 static struct dc_type dc_devs[] = { 143 { DC_VENDORID_DEC, DC_DEVICEID_21143, 144 "Intel 21143 10/100BaseTX" }, 145 { DC_VENDORID_DAVICOM, DC_DEVICEID_DM9100, 146 "Davicom DM9100 10/100BaseTX" }, 147 { DC_VENDORID_DAVICOM, DC_DEVICEID_DM9102, 148 "Davicom DM9102 10/100BaseTX" }, 149 { DC_VENDORID_DAVICOM, DC_DEVICEID_DM9102, 150 "Davicom DM9102A 10/100BaseTX" }, 151 { DC_VENDORID_ADMTEK, DC_DEVICEID_AL981, 152 "ADMtek AL981 10/100BaseTX" }, 153 { DC_VENDORID_ADMTEK, DC_DEVICEID_AN985, 154 "ADMtek AN985 10/100BaseTX" }, 155 { DC_VENDORID_ASIX, DC_DEVICEID_AX88140A, 156 "ASIX AX88140A 10/100BaseTX" }, 157 { DC_VENDORID_ASIX, DC_DEVICEID_AX88140A, 158 "ASIX AX88141 10/100BaseTX" }, 159 { DC_VENDORID_MX, DC_DEVICEID_98713, 160 "Macronix 98713 10/100BaseTX" }, 161 { DC_VENDORID_MX, DC_DEVICEID_98713, 162 "Macronix 98713A 10/100BaseTX" }, 163 { DC_VENDORID_CP, DC_DEVICEID_98713_CP, 164 "Compex RL100-TX 10/100BaseTX" }, 165 { DC_VENDORID_CP, DC_DEVICEID_98713_CP, 166 "Compex RL100-TX 10/100BaseTX" }, 167 { DC_VENDORID_MX, DC_DEVICEID_987x5, 168 "Macronix 98715/98715A 10/100BaseTX" }, 169 { DC_VENDORID_MX, DC_DEVICEID_987x5, 170 "Macronix 98715AEC-C 10/100BaseTX" }, 171 { DC_VENDORID_MX, DC_DEVICEID_987x5, 172 "Macronix 98725 10/100BaseTX" }, 173 { DC_VENDORID_MX, DC_DEVICEID_98727, 174 "Macronix 98727/98732 10/100BaseTX" }, 175 { DC_VENDORID_LO, DC_DEVICEID_82C115, 176 "LC82C115 PNIC II 10/100BaseTX" }, 177 { DC_VENDORID_LO, DC_DEVICEID_82C168, 178 "82c168 PNIC 10/100BaseTX" }, 179 { DC_VENDORID_LO, DC_DEVICEID_82C168, 180 "82c169 PNIC 10/100BaseTX" }, 181 { DC_VENDORID_ACCTON, DC_DEVICEID_EN1217, 182 "Accton EN1217 10/100BaseTX" }, 183 { DC_VENDORID_XIRCOM, DC_DEVICEID_X3201, 184 "Xircom X3201 10/100BaseTX" }, 185 { DC_VENDORID_ABOCOM, DC_DEVICEID_FE2500, 186 "Abocom FE2500 10/100BaseTX" }, 187 { 0, 0, NULL } 188 }; 189 190 static int dc_probe __P((device_t)); 191 static int dc_attach __P((device_t)); 192 static int dc_detach __P((device_t)); 193 static void dc_acpi __P((device_t)); 194 static struct dc_type *dc_devtype __P((device_t)); 195 static int dc_newbuf __P((struct dc_softc *, int, struct mbuf *)); 196 static int dc_encap __P((struct dc_softc *, struct mbuf *, 197 u_int32_t *)); 198 static int dc_coal __P((struct dc_softc *, struct mbuf **)); 199 static void dc_pnic_rx_bug_war __P((struct dc_softc *, int)); 200 static int dc_rx_resync __P((struct dc_softc *)); 201 static void dc_rxeof __P((struct dc_softc *)); 202 static void dc_txeof __P((struct dc_softc *)); 203 static void dc_tick __P((void *)); 204 static void dc_intr __P((void *)); 205 static void dc_start __P((struct ifnet *)); 206 static int dc_ioctl __P((struct ifnet *, u_long, caddr_t)); 207 static void dc_init __P((void *)); 208 static void dc_stop __P((struct dc_softc *)); 209 static void dc_watchdog __P((struct ifnet *)); 210 static void dc_shutdown __P((device_t)); 211 static int dc_ifmedia_upd __P((struct ifnet *)); 212 static void dc_ifmedia_sts __P((struct ifnet *, struct ifmediareq *)); 213 214 static void dc_delay __P((struct dc_softc *)); 215 static void dc_eeprom_idle __P((struct dc_softc *)); 216 static void dc_eeprom_putbyte __P((struct dc_softc *, int)); 217 static void dc_eeprom_getword __P((struct dc_softc *, int, u_int16_t *)); 218 static void dc_eeprom_getword_pnic 219 __P((struct dc_softc *, int, u_int16_t *)); 220 static void dc_eeprom_getword_xircom 221 __P((struct dc_softc *, int, u_int16_t *)); 222 static void dc_read_eeprom __P((struct dc_softc *, caddr_t, int, 223 int, int)); 224 225 static void dc_mii_writebit __P((struct dc_softc *, int)); 226 static int dc_mii_readbit __P((struct dc_softc *)); 227 static void dc_mii_sync __P((struct dc_softc *)); 228 static void dc_mii_send __P((struct dc_softc *, u_int32_t, int)); 229 static int dc_mii_readreg __P((struct dc_softc *, struct dc_mii_frame *)); 230 static int dc_mii_writereg __P((struct dc_softc *, struct dc_mii_frame *)); 231 static int dc_miibus_readreg __P((device_t, int, int)); 232 static int dc_miibus_writereg __P((device_t, int, int, int)); 233 static void dc_miibus_statchg __P((device_t)); 234 static void dc_miibus_mediainit __P((device_t)); 235 236 static void dc_setcfg __P((struct dc_softc *, int)); 237 static u_int32_t dc_crc_le __P((struct dc_softc *, caddr_t)); 238 static u_int32_t dc_crc_be __P((caddr_t)); 239 static void dc_setfilt_21143 __P((struct dc_softc *)); 240 static void dc_setfilt_asix __P((struct dc_softc *)); 241 static void dc_setfilt_admtek __P((struct dc_softc *)); 242 static void dc_setfilt_xircom __P((struct dc_softc *)); 243 244 static void dc_setfilt __P((struct dc_softc *)); 245 246 static void dc_reset __P((struct dc_softc *)); 247 static int dc_list_rx_init __P((struct dc_softc *)); 248 static int dc_list_tx_init __P((struct dc_softc *)); 249 250 static void dc_parse_21143_srom __P((struct dc_softc *)); 251 static void dc_decode_leaf_sia __P((struct dc_softc *, 252 struct dc_eblock_sia *)); 253 static void dc_decode_leaf_mii __P((struct dc_softc *, 254 struct dc_eblock_mii *)); 255 static void dc_decode_leaf_sym __P((struct dc_softc *, 256 struct dc_eblock_sym *)); 257 static void dc_apply_fixup __P((struct dc_softc *, int)); 258 259 #ifdef DC_USEIOSPACE 260 #define DC_RES SYS_RES_IOPORT 261 #define DC_RID DC_PCI_CFBIO 262 #else 263 #define DC_RES SYS_RES_MEMORY 264 #define DC_RID DC_PCI_CFBMA 265 #endif 266 267 static device_method_t dc_methods[] = { 268 /* Device interface */ 269 DEVMETHOD(device_probe, dc_probe), 270 DEVMETHOD(device_attach, dc_attach), 271 DEVMETHOD(device_detach, dc_detach), 272 DEVMETHOD(device_shutdown, dc_shutdown), 273 274 /* bus interface */ 275 DEVMETHOD(bus_print_child, bus_generic_print_child), 276 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 277 278 /* MII interface */ 279 DEVMETHOD(miibus_readreg, dc_miibus_readreg), 280 DEVMETHOD(miibus_writereg, dc_miibus_writereg), 281 DEVMETHOD(miibus_statchg, dc_miibus_statchg), 282 DEVMETHOD(miibus_mediainit, dc_miibus_mediainit), 283 284 { 0, 0 } 285 }; 286 287 static driver_t dc_driver = { 288 "dc", 289 dc_methods, 290 sizeof(struct dc_softc) 291 }; 292 293 static devclass_t dc_devclass; 294 295 DRIVER_MODULE(if_dc, cardbus, dc_driver, dc_devclass, 0, 0); 296 DRIVER_MODULE(if_dc, pci, dc_driver, dc_devclass, 0, 0); 297 DRIVER_MODULE(miibus, dc, miibus_driver, miibus_devclass, 0, 0); 298 299 #define DC_SETBIT(sc, reg, x) \ 300 CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) | (x)) 301 302 #define DC_CLRBIT(sc, reg, x) \ 303 CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) & ~(x)) 304 305 #define SIO_SET(x) DC_SETBIT(sc, DC_SIO, (x)) 306 #define SIO_CLR(x) DC_CLRBIT(sc, DC_SIO, (x)) 307 308 static void dc_delay(sc) 309 struct dc_softc *sc; 310 { 311 int idx; 312 313 for (idx = (300 / 33) + 1; idx > 0; idx--) 314 CSR_READ_4(sc, DC_BUSCTL); 315 } 316 317 static void dc_eeprom_idle(sc) 318 struct dc_softc *sc; 319 { 320 register int i; 321 322 CSR_WRITE_4(sc, DC_SIO, DC_SIO_EESEL); 323 dc_delay(sc); 324 DC_SETBIT(sc, DC_SIO, DC_SIO_ROMCTL_READ); 325 dc_delay(sc); 326 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); 327 dc_delay(sc); 328 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CS); 329 dc_delay(sc); 330 331 for (i = 0; i < 25; i++) { 332 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); 333 dc_delay(sc); 334 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CLK); 335 dc_delay(sc); 336 } 337 338 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); 339 dc_delay(sc); 340 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CS); 341 dc_delay(sc); 342 CSR_WRITE_4(sc, DC_SIO, 0x00000000); 343 344 return; 345 } 346 347 /* 348 * Send a read command and address to the EEPROM, check for ACK. 349 */ 350 static void dc_eeprom_putbyte(sc, addr) 351 struct dc_softc *sc; 352 int addr; 353 { 354 register int d, i; 355 356 /* 357 * The AN985 has a 93C66 EEPROM on it instead of 358 * a 93C46. It uses a different bit sequence for 359 * specifying the "read" opcode. 360 */ 361 if (DC_IS_CENTAUR(sc)) 362 d = addr | (DC_EECMD_READ << 2); 363 else 364 d = addr | DC_EECMD_READ; 365 366 /* 367 * Feed in each bit and strobe the clock. 368 */ 369 for (i = 0x400; i; i >>= 1) { 370 if (d & i) { 371 SIO_SET(DC_SIO_EE_DATAIN); 372 } else { 373 SIO_CLR(DC_SIO_EE_DATAIN); 374 } 375 dc_delay(sc); 376 SIO_SET(DC_SIO_EE_CLK); 377 dc_delay(sc); 378 SIO_CLR(DC_SIO_EE_CLK); 379 dc_delay(sc); 380 } 381 382 return; 383 } 384 385 /* 386 * Read a word of data stored in the EEPROM at address 'addr.' 387 * The PNIC 82c168/82c169 has its own non-standard way to read 388 * the EEPROM. 389 */ 390 static void dc_eeprom_getword_pnic(sc, addr, dest) 391 struct dc_softc *sc; 392 int addr; 393 u_int16_t *dest; 394 { 395 register int i; 396 u_int32_t r; 397 398 CSR_WRITE_4(sc, DC_PN_SIOCTL, DC_PN_EEOPCODE_READ|addr); 399 400 for (i = 0; i < DC_TIMEOUT; i++) { 401 DELAY(1); 402 r = CSR_READ_4(sc, DC_SIO); 403 if (!(r & DC_PN_SIOCTL_BUSY)) { 404 *dest = (u_int16_t)(r & 0xFFFF); 405 return; 406 } 407 } 408 409 return; 410 } 411 412 /* 413 * Read a word of data stored in the EEPROM at address 'addr.' 414 * The Xircom X3201 has its own non-standard way to read 415 * the EEPROM, too. 416 */ 417 static void dc_eeprom_getword_xircom(sc, addr, dest) 418 struct dc_softc *sc; 419 int addr; 420 u_int16_t *dest; 421 { 422 SIO_SET(DC_SIO_ROMSEL | DC_SIO_ROMCTL_READ); 423 424 addr *= 2; 425 CSR_WRITE_4(sc, DC_ROM, addr | 0x160); 426 *dest = (u_int16_t)CSR_READ_4(sc, DC_SIO)&0xff; 427 addr += 1; 428 CSR_WRITE_4(sc, DC_ROM, addr | 0x160); 429 *dest |= ((u_int16_t)CSR_READ_4(sc, DC_SIO)&0xff) << 8; 430 431 SIO_CLR(DC_SIO_ROMSEL | DC_SIO_ROMCTL_READ); 432 return; 433 } 434 435 /* 436 * Read a word of data stored in the EEPROM at address 'addr.' 437 */ 438 static void dc_eeprom_getword(sc, addr, dest) 439 struct dc_softc *sc; 440 int addr; 441 u_int16_t *dest; 442 { 443 register int i; 444 u_int16_t word = 0; 445 446 /* Force EEPROM to idle state. */ 447 dc_eeprom_idle(sc); 448 449 /* Enter EEPROM access mode. */ 450 CSR_WRITE_4(sc, DC_SIO, DC_SIO_EESEL); 451 dc_delay(sc); 452 DC_SETBIT(sc, DC_SIO, DC_SIO_ROMCTL_READ); 453 dc_delay(sc); 454 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); 455 dc_delay(sc); 456 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CS); 457 dc_delay(sc); 458 459 /* 460 * Send address of word we want to read. 461 */ 462 dc_eeprom_putbyte(sc, addr); 463 464 /* 465 * Start reading bits from EEPROM. 466 */ 467 for (i = 0x8000; i; i >>= 1) { 468 SIO_SET(DC_SIO_EE_CLK); 469 dc_delay(sc); 470 if (CSR_READ_4(sc, DC_SIO) & DC_SIO_EE_DATAOUT) 471 word |= i; 472 dc_delay(sc); 473 SIO_CLR(DC_SIO_EE_CLK); 474 dc_delay(sc); 475 } 476 477 /* Turn off EEPROM access mode. */ 478 dc_eeprom_idle(sc); 479 480 *dest = word; 481 482 return; 483 } 484 485 /* 486 * Read a sequence of words from the EEPROM. 487 */ 488 static void dc_read_eeprom(sc, dest, off, cnt, swap) 489 struct dc_softc *sc; 490 caddr_t dest; 491 int off; 492 int cnt; 493 int swap; 494 { 495 int i; 496 u_int16_t word = 0, *ptr; 497 498 for (i = 0; i < cnt; i++) { 499 if (DC_IS_PNIC(sc)) 500 dc_eeprom_getword_pnic(sc, off + i, &word); 501 else if (DC_IS_XIRCOM(sc)) 502 dc_eeprom_getword_xircom(sc, off + i, &word); 503 else 504 dc_eeprom_getword(sc, off + i, &word); 505 ptr = (u_int16_t *)(dest + (i * 2)); 506 if (swap) 507 *ptr = ntohs(word); 508 else 509 *ptr = word; 510 } 511 512 return; 513 } 514 515 /* 516 * The following two routines are taken from the Macronix 98713 517 * Application Notes pp.19-21. 518 */ 519 /* 520 * Write a bit to the MII bus. 521 */ 522 static void dc_mii_writebit(sc, bit) 523 struct dc_softc *sc; 524 int bit; 525 { 526 if (bit) 527 CSR_WRITE_4(sc, DC_SIO, 528 DC_SIO_ROMCTL_WRITE|DC_SIO_MII_DATAOUT); 529 else 530 CSR_WRITE_4(sc, DC_SIO, DC_SIO_ROMCTL_WRITE); 531 532 DC_SETBIT(sc, DC_SIO, DC_SIO_MII_CLK); 533 DC_CLRBIT(sc, DC_SIO, DC_SIO_MII_CLK); 534 535 return; 536 } 537 538 /* 539 * Read a bit from the MII bus. 540 */ 541 static int dc_mii_readbit(sc) 542 struct dc_softc *sc; 543 { 544 CSR_WRITE_4(sc, DC_SIO, DC_SIO_ROMCTL_READ|DC_SIO_MII_DIR); 545 CSR_READ_4(sc, DC_SIO); 546 DC_SETBIT(sc, DC_SIO, DC_SIO_MII_CLK); 547 DC_CLRBIT(sc, DC_SIO, DC_SIO_MII_CLK); 548 if (CSR_READ_4(sc, DC_SIO) & DC_SIO_MII_DATAIN) 549 return(1); 550 551 return(0); 552 } 553 554 /* 555 * Sync the PHYs by setting data bit and strobing the clock 32 times. 556 */ 557 static void dc_mii_sync(sc) 558 struct dc_softc *sc; 559 { 560 register int i; 561 562 CSR_WRITE_4(sc, DC_SIO, DC_SIO_ROMCTL_WRITE); 563 564 for (i = 0; i < 32; i++) 565 dc_mii_writebit(sc, 1); 566 567 return; 568 } 569 570 /* 571 * Clock a series of bits through the MII. 572 */ 573 static void dc_mii_send(sc, bits, cnt) 574 struct dc_softc *sc; 575 u_int32_t bits; 576 int cnt; 577 { 578 int i; 579 580 for (i = (0x1 << (cnt - 1)); i; i >>= 1) 581 dc_mii_writebit(sc, bits & i); 582 } 583 584 /* 585 * Read an PHY register through the MII. 586 */ 587 static int dc_mii_readreg(sc, frame) 588 struct dc_softc *sc; 589 struct dc_mii_frame *frame; 590 591 { 592 int i, ack; 593 594 DC_LOCK(sc); 595 596 /* 597 * Set up frame for RX. 598 */ 599 frame->mii_stdelim = DC_MII_STARTDELIM; 600 frame->mii_opcode = DC_MII_READOP; 601 frame->mii_turnaround = 0; 602 frame->mii_data = 0; 603 604 /* 605 * Sync the PHYs. 606 */ 607 dc_mii_sync(sc); 608 609 /* 610 * Send command/address info. 611 */ 612 dc_mii_send(sc, frame->mii_stdelim, 2); 613 dc_mii_send(sc, frame->mii_opcode, 2); 614 dc_mii_send(sc, frame->mii_phyaddr, 5); 615 dc_mii_send(sc, frame->mii_regaddr, 5); 616 617 #ifdef notdef 618 /* Idle bit */ 619 dc_mii_writebit(sc, 1); 620 dc_mii_writebit(sc, 0); 621 #endif 622 623 /* Check for ack */ 624 ack = dc_mii_readbit(sc); 625 626 /* 627 * Now try reading data bits. If the ack failed, we still 628 * need to clock through 16 cycles to keep the PHY(s) in sync. 629 */ 630 if (ack) { 631 for(i = 0; i < 16; i++) { 632 dc_mii_readbit(sc); 633 } 634 goto fail; 635 } 636 637 for (i = 0x8000; i; i >>= 1) { 638 if (!ack) { 639 if (dc_mii_readbit(sc)) 640 frame->mii_data |= i; 641 } 642 } 643 644 fail: 645 646 dc_mii_writebit(sc, 0); 647 dc_mii_writebit(sc, 0); 648 649 DC_UNLOCK(sc); 650 651 if (ack) 652 return(1); 653 return(0); 654 } 655 656 /* 657 * Write to a PHY register through the MII. 658 */ 659 static int dc_mii_writereg(sc, frame) 660 struct dc_softc *sc; 661 struct dc_mii_frame *frame; 662 663 { 664 DC_LOCK(sc); 665 /* 666 * Set up frame for TX. 667 */ 668 669 frame->mii_stdelim = DC_MII_STARTDELIM; 670 frame->mii_opcode = DC_MII_WRITEOP; 671 frame->mii_turnaround = DC_MII_TURNAROUND; 672 673 /* 674 * Sync the PHYs. 675 */ 676 dc_mii_sync(sc); 677 678 dc_mii_send(sc, frame->mii_stdelim, 2); 679 dc_mii_send(sc, frame->mii_opcode, 2); 680 dc_mii_send(sc, frame->mii_phyaddr, 5); 681 dc_mii_send(sc, frame->mii_regaddr, 5); 682 dc_mii_send(sc, frame->mii_turnaround, 2); 683 dc_mii_send(sc, frame->mii_data, 16); 684 685 /* Idle bit. */ 686 dc_mii_writebit(sc, 0); 687 dc_mii_writebit(sc, 0); 688 689 DC_UNLOCK(sc); 690 691 return(0); 692 } 693 694 static int dc_miibus_readreg(dev, phy, reg) 695 device_t dev; 696 int phy, reg; 697 { 698 struct dc_mii_frame frame; 699 struct dc_softc *sc; 700 int i, rval, phy_reg; 701 702 sc = device_get_softc(dev); 703 bzero((char *)&frame, sizeof(frame)); 704 705 /* 706 * Note: both the AL981 and AN985 have internal PHYs, 707 * however the AL981 provides direct access to the PHY 708 * registers while the AN985 uses a serial MII interface. 709 * The AN985's MII interface is also buggy in that you 710 * can read from any MII address (0 to 31), but only address 1 711 * behaves normally. To deal with both cases, we pretend 712 * that the PHY is at MII address 1. 713 */ 714 if (DC_IS_ADMTEK(sc) && phy != DC_ADMTEK_PHYADDR) 715 return(0); 716 717 if (sc->dc_pmode != DC_PMODE_MII) { 718 if (phy == (MII_NPHY - 1)) { 719 switch(reg) { 720 case MII_BMSR: 721 /* 722 * Fake something to make the probe 723 * code think there's a PHY here. 724 */ 725 return(BMSR_MEDIAMASK); 726 break; 727 case MII_PHYIDR1: 728 if (DC_IS_PNIC(sc)) 729 return(DC_VENDORID_LO); 730 return(DC_VENDORID_DEC); 731 break; 732 case MII_PHYIDR2: 733 if (DC_IS_PNIC(sc)) 734 return(DC_DEVICEID_82C168); 735 return(DC_DEVICEID_21143); 736 break; 737 default: 738 return(0); 739 break; 740 } 741 } else 742 return(0); 743 } 744 745 if (DC_IS_PNIC(sc)) { 746 CSR_WRITE_4(sc, DC_PN_MII, DC_PN_MIIOPCODE_READ | 747 (phy << 23) | (reg << 18)); 748 for (i = 0; i < DC_TIMEOUT; i++) { 749 DELAY(1); 750 rval = CSR_READ_4(sc, DC_PN_MII); 751 if (!(rval & DC_PN_MII_BUSY)) { 752 rval &= 0xFFFF; 753 return(rval == 0xFFFF ? 0 : rval); 754 } 755 } 756 return(0); 757 } 758 759 if (DC_IS_COMET(sc)) { 760 switch(reg) { 761 case MII_BMCR: 762 phy_reg = DC_AL_BMCR; 763 break; 764 case MII_BMSR: 765 phy_reg = DC_AL_BMSR; 766 break; 767 case MII_PHYIDR1: 768 phy_reg = DC_AL_VENID; 769 break; 770 case MII_PHYIDR2: 771 phy_reg = DC_AL_DEVID; 772 break; 773 case MII_ANAR: 774 phy_reg = DC_AL_ANAR; 775 break; 776 case MII_ANLPAR: 777 phy_reg = DC_AL_LPAR; 778 break; 779 case MII_ANER: 780 phy_reg = DC_AL_ANER; 781 break; 782 default: 783 printf("dc%d: phy_read: bad phy register %x\n", 784 sc->dc_unit, reg); 785 return(0); 786 break; 787 } 788 789 rval = CSR_READ_4(sc, phy_reg) & 0x0000FFFF; 790 791 if (rval == 0xFFFF) 792 return(0); 793 return(rval); 794 } 795 796 frame.mii_phyaddr = phy; 797 frame.mii_regaddr = reg; 798 phy_reg = CSR_READ_4(sc, DC_NETCFG); 799 CSR_WRITE_4(sc, DC_NETCFG, phy_reg & ~DC_NETCFG_PORTSEL); 800 dc_mii_readreg(sc, &frame); 801 CSR_WRITE_4(sc, DC_NETCFG, phy_reg); 802 803 return(frame.mii_data); 804 } 805 806 static int dc_miibus_writereg(dev, phy, reg, data) 807 device_t dev; 808 int phy, reg, data; 809 { 810 struct dc_softc *sc; 811 struct dc_mii_frame frame; 812 int i, phy_reg; 813 814 sc = device_get_softc(dev); 815 bzero((char *)&frame, sizeof(frame)); 816 817 if (DC_IS_ADMTEK(sc) && phy != DC_ADMTEK_PHYADDR) 818 return(0); 819 820 if (DC_IS_PNIC(sc)) { 821 CSR_WRITE_4(sc, DC_PN_MII, DC_PN_MIIOPCODE_WRITE | 822 (phy << 23) | (reg << 10) | data); 823 for (i = 0; i < DC_TIMEOUT; i++) { 824 if (!(CSR_READ_4(sc, DC_PN_MII) & DC_PN_MII_BUSY)) 825 break; 826 } 827 return(0); 828 } 829 830 if (DC_IS_COMET(sc)) { 831 switch(reg) { 832 case MII_BMCR: 833 phy_reg = DC_AL_BMCR; 834 break; 835 case MII_BMSR: 836 phy_reg = DC_AL_BMSR; 837 break; 838 case MII_PHYIDR1: 839 phy_reg = DC_AL_VENID; 840 break; 841 case MII_PHYIDR2: 842 phy_reg = DC_AL_DEVID; 843 break; 844 case MII_ANAR: 845 phy_reg = DC_AL_ANAR; 846 break; 847 case MII_ANLPAR: 848 phy_reg = DC_AL_LPAR; 849 break; 850 case MII_ANER: 851 phy_reg = DC_AL_ANER; 852 break; 853 default: 854 printf("dc%d: phy_write: bad phy register %x\n", 855 sc->dc_unit, reg); 856 return(0); 857 break; 858 } 859 860 CSR_WRITE_4(sc, phy_reg, data); 861 return(0); 862 } 863 864 frame.mii_phyaddr = phy; 865 frame.mii_regaddr = reg; 866 frame.mii_data = data; 867 868 phy_reg = CSR_READ_4(sc, DC_NETCFG); 869 CSR_WRITE_4(sc, DC_NETCFG, phy_reg & ~DC_NETCFG_PORTSEL); 870 dc_mii_writereg(sc, &frame); 871 CSR_WRITE_4(sc, DC_NETCFG, phy_reg); 872 873 return(0); 874 } 875 876 static void dc_miibus_statchg(dev) 877 device_t dev; 878 { 879 struct dc_softc *sc; 880 struct mii_data *mii; 881 struct ifmedia *ifm; 882 883 sc = device_get_softc(dev); 884 if (DC_IS_ADMTEK(sc)) 885 return; 886 887 mii = device_get_softc(sc->dc_miibus); 888 ifm = &mii->mii_media; 889 if (DC_IS_DAVICOM(sc) && 890 IFM_SUBTYPE(ifm->ifm_media) == IFM_homePNA) { 891 dc_setcfg(sc, ifm->ifm_media); 892 sc->dc_if_media = ifm->ifm_media; 893 } else { 894 dc_setcfg(sc, mii->mii_media_active); 895 sc->dc_if_media = mii->mii_media_active; 896 } 897 898 return; 899 } 900 901 /* 902 * Special support for DM9102A cards with HomePNA PHYs. Note: 903 * with the Davicom DM9102A/DM9801 eval board that I have, it seems 904 * to be impossible to talk to the management interface of the DM9801 905 * PHY (its MDIO pin is not connected to anything). Consequently, 906 * the driver has to just 'know' about the additional mode and deal 907 * with it itself. *sigh* 908 */ 909 static void dc_miibus_mediainit(dev) 910 device_t dev; 911 { 912 struct dc_softc *sc; 913 struct mii_data *mii; 914 struct ifmedia *ifm; 915 int rev; 916 917 rev = pci_read_config(dev, DC_PCI_CFRV, 4) & 0xFF; 918 919 sc = device_get_softc(dev); 920 mii = device_get_softc(sc->dc_miibus); 921 ifm = &mii->mii_media; 922 923 if (DC_IS_DAVICOM(sc) && rev >= DC_REVISION_DM9102A) 924 ifmedia_add(ifm, IFM_ETHER|IFM_homePNA, 0, NULL); 925 926 return; 927 } 928 929 #define DC_POLY 0xEDB88320 930 #define DC_BITS_512 9 931 #define DC_BITS_128 7 932 #define DC_BITS_64 6 933 934 static u_int32_t dc_crc_le(sc, addr) 935 struct dc_softc *sc; 936 caddr_t addr; 937 { 938 u_int32_t idx, bit, data, crc; 939 940 /* Compute CRC for the address value. */ 941 crc = 0xFFFFFFFF; /* initial value */ 942 943 for (idx = 0; idx < 6; idx++) { 944 for (data = *addr++, bit = 0; bit < 8; bit++, data >>= 1) 945 crc = (crc >> 1) ^ (((crc ^ data) & 1) ? DC_POLY : 0); 946 } 947 948 /* 949 * The hash table on the PNIC II and the MX98715AEC-C/D/E 950 * chips is only 128 bits wide. 951 */ 952 if (sc->dc_flags & DC_128BIT_HASH) 953 return (crc & ((1 << DC_BITS_128) - 1)); 954 955 /* The hash table on the MX98715BEC is only 64 bits wide. */ 956 if (sc->dc_flags & DC_64BIT_HASH) 957 return (crc & ((1 << DC_BITS_64) - 1)); 958 959 /* Xircom's hash filtering table is different (read: weird) */ 960 /* Xircom uses the LEAST significant bits */ 961 if (DC_IS_XIRCOM(sc)) { 962 if ((crc & 0x180) == 0x180) 963 return (crc & 0x0F) + (crc & 0x70)*3 + (14 << 4); 964 else 965 return (crc & 0x1F) + ((crc>>1) & 0xF0)*3 + (12 << 4); 966 } 967 968 return (crc & ((1 << DC_BITS_512) - 1)); 969 } 970 971 /* 972 * Calculate CRC of a multicast group address, return the lower 6 bits. 973 */ 974 static u_int32_t dc_crc_be(addr) 975 caddr_t addr; 976 { 977 u_int32_t crc, carry; 978 int i, j; 979 u_int8_t c; 980 981 /* Compute CRC for the address value. */ 982 crc = 0xFFFFFFFF; /* initial value */ 983 984 for (i = 0; i < 6; i++) { 985 c = *(addr + i); 986 for (j = 0; j < 8; j++) { 987 carry = ((crc & 0x80000000) ? 1 : 0) ^ (c & 0x01); 988 crc <<= 1; 989 c >>= 1; 990 if (carry) 991 crc = (crc ^ 0x04c11db6) | carry; 992 } 993 } 994 995 /* return the filter bit position */ 996 return((crc >> 26) & 0x0000003F); 997 } 998 999 /* 1000 * 21143-style RX filter setup routine. Filter programming is done by 1001 * downloading a special setup frame into the TX engine. 21143, Macronix, 1002 * PNIC, PNIC II and Davicom chips are programmed this way. 1003 * 1004 * We always program the chip using 'hash perfect' mode, i.e. one perfect 1005 * address (our node address) and a 512-bit hash filter for multicast 1006 * frames. We also sneak the broadcast address into the hash filter since 1007 * we need that too. 1008 */ 1009 void dc_setfilt_21143(sc) 1010 struct dc_softc *sc; 1011 { 1012 struct dc_desc *sframe; 1013 u_int32_t h, *sp; 1014 struct ifmultiaddr *ifma; 1015 struct ifnet *ifp; 1016 int i; 1017 1018 ifp = &sc->arpcom.ac_if; 1019 1020 i = sc->dc_cdata.dc_tx_prod; 1021 DC_INC(sc->dc_cdata.dc_tx_prod, DC_TX_LIST_CNT); 1022 sc->dc_cdata.dc_tx_cnt++; 1023 sframe = &sc->dc_ldata->dc_tx_list[i]; 1024 sp = (u_int32_t *)&sc->dc_cdata.dc_sbuf; 1025 bzero((char *)sp, DC_SFRAME_LEN); 1026 1027 sframe->dc_data = vtophys(&sc->dc_cdata.dc_sbuf); 1028 sframe->dc_ctl = DC_SFRAME_LEN | DC_TXCTL_SETUP | DC_TXCTL_TLINK | 1029 DC_FILTER_HASHPERF | DC_TXCTL_FINT; 1030 1031 sc->dc_cdata.dc_tx_chain[i] = (struct mbuf *)&sc->dc_cdata.dc_sbuf; 1032 1033 /* If we want promiscuous mode, set the allframes bit. */ 1034 if (ifp->if_flags & IFF_PROMISC) 1035 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC); 1036 else 1037 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC); 1038 1039 if (ifp->if_flags & IFF_ALLMULTI) 1040 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI); 1041 else 1042 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI); 1043 1044 for (ifma = ifp->if_multiaddrs.lh_first; ifma != NULL; 1045 ifma = ifma->ifma_link.le_next) { 1046 if (ifma->ifma_addr->sa_family != AF_LINK) 1047 continue; 1048 h = dc_crc_le(sc, 1049 LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 1050 sp[h >> 4] |= 1 << (h & 0xF); 1051 } 1052 1053 if (ifp->if_flags & IFF_BROADCAST) { 1054 h = dc_crc_le(sc, (caddr_t)ðerbroadcastaddr); 1055 sp[h >> 4] |= 1 << (h & 0xF); 1056 } 1057 1058 /* Set our MAC address */ 1059 sp[39] = ((u_int16_t *)sc->arpcom.ac_enaddr)[0]; 1060 sp[40] = ((u_int16_t *)sc->arpcom.ac_enaddr)[1]; 1061 sp[41] = ((u_int16_t *)sc->arpcom.ac_enaddr)[2]; 1062 1063 sframe->dc_status = DC_TXSTAT_OWN; 1064 CSR_WRITE_4(sc, DC_TXSTART, 0xFFFFFFFF); 1065 1066 /* 1067 * The PNIC takes an exceedingly long time to process its 1068 * setup frame; wait 10ms after posting the setup frame 1069 * before proceeding, just so it has time to swallow its 1070 * medicine. 1071 */ 1072 DELAY(10000); 1073 1074 ifp->if_timer = 5; 1075 1076 return; 1077 } 1078 1079 void dc_setfilt_admtek(sc) 1080 struct dc_softc *sc; 1081 { 1082 struct ifnet *ifp; 1083 int h = 0; 1084 u_int32_t hashes[2] = { 0, 0 }; 1085 struct ifmultiaddr *ifma; 1086 1087 ifp = &sc->arpcom.ac_if; 1088 1089 /* Init our MAC address */ 1090 CSR_WRITE_4(sc, DC_AL_PAR0, *(u_int32_t *)(&sc->arpcom.ac_enaddr[0])); 1091 CSR_WRITE_4(sc, DC_AL_PAR1, *(u_int32_t *)(&sc->arpcom.ac_enaddr[4])); 1092 1093 /* If we want promiscuous mode, set the allframes bit. */ 1094 if (ifp->if_flags & IFF_PROMISC) 1095 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC); 1096 else 1097 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC); 1098 1099 if (ifp->if_flags & IFF_ALLMULTI) 1100 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI); 1101 else 1102 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI); 1103 1104 /* first, zot all the existing hash bits */ 1105 CSR_WRITE_4(sc, DC_AL_MAR0, 0); 1106 CSR_WRITE_4(sc, DC_AL_MAR1, 0); 1107 1108 /* 1109 * If we're already in promisc or allmulti mode, we 1110 * don't have to bother programming the multicast filter. 1111 */ 1112 if (ifp->if_flags & (IFF_PROMISC|IFF_ALLMULTI)) 1113 return; 1114 1115 /* now program new ones */ 1116 for (ifma = ifp->if_multiaddrs.lh_first; ifma != NULL; 1117 ifma = ifma->ifma_link.le_next) { 1118 if (ifma->ifma_addr->sa_family != AF_LINK) 1119 continue; 1120 h = dc_crc_be(LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 1121 if (h < 32) 1122 hashes[0] |= (1 << h); 1123 else 1124 hashes[1] |= (1 << (h - 32)); 1125 } 1126 1127 CSR_WRITE_4(sc, DC_AL_MAR0, hashes[0]); 1128 CSR_WRITE_4(sc, DC_AL_MAR1, hashes[1]); 1129 1130 return; 1131 } 1132 1133 void dc_setfilt_asix(sc) 1134 struct dc_softc *sc; 1135 { 1136 struct ifnet *ifp; 1137 int h = 0; 1138 u_int32_t hashes[2] = { 0, 0 }; 1139 struct ifmultiaddr *ifma; 1140 1141 ifp = &sc->arpcom.ac_if; 1142 1143 /* Init our MAC address */ 1144 CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_PAR0); 1145 CSR_WRITE_4(sc, DC_AX_FILTDATA, 1146 *(u_int32_t *)(&sc->arpcom.ac_enaddr[0])); 1147 CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_PAR1); 1148 CSR_WRITE_4(sc, DC_AX_FILTDATA, 1149 *(u_int32_t *)(&sc->arpcom.ac_enaddr[4])); 1150 1151 /* If we want promiscuous mode, set the allframes bit. */ 1152 if (ifp->if_flags & IFF_PROMISC) 1153 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC); 1154 else 1155 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC); 1156 1157 if (ifp->if_flags & IFF_ALLMULTI) 1158 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI); 1159 else 1160 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI); 1161 1162 /* 1163 * The ASIX chip has a special bit to enable reception 1164 * of broadcast frames. 1165 */ 1166 if (ifp->if_flags & IFF_BROADCAST) 1167 DC_SETBIT(sc, DC_NETCFG, DC_AX_NETCFG_RX_BROAD); 1168 else 1169 DC_CLRBIT(sc, DC_NETCFG, DC_AX_NETCFG_RX_BROAD); 1170 1171 /* first, zot all the existing hash bits */ 1172 CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_MAR0); 1173 CSR_WRITE_4(sc, DC_AX_FILTDATA, 0); 1174 CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_MAR1); 1175 CSR_WRITE_4(sc, DC_AX_FILTDATA, 0); 1176 1177 /* 1178 * If we're already in promisc or allmulti mode, we 1179 * don't have to bother programming the multicast filter. 1180 */ 1181 if (ifp->if_flags & (IFF_PROMISC|IFF_ALLMULTI)) 1182 return; 1183 1184 /* now program new ones */ 1185 for (ifma = ifp->if_multiaddrs.lh_first; ifma != NULL; 1186 ifma = ifma->ifma_link.le_next) { 1187 if (ifma->ifma_addr->sa_family != AF_LINK) 1188 continue; 1189 h = dc_crc_be(LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 1190 if (h < 32) 1191 hashes[0] |= (1 << h); 1192 else 1193 hashes[1] |= (1 << (h - 32)); 1194 } 1195 1196 CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_MAR0); 1197 CSR_WRITE_4(sc, DC_AX_FILTDATA, hashes[0]); 1198 CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_MAR1); 1199 CSR_WRITE_4(sc, DC_AX_FILTDATA, hashes[1]); 1200 1201 return; 1202 } 1203 1204 void dc_setfilt_xircom(sc) 1205 struct dc_softc *sc; 1206 { 1207 struct dc_desc *sframe; 1208 u_int32_t h, *sp; 1209 struct ifmultiaddr *ifma; 1210 struct ifnet *ifp; 1211 int i; 1212 1213 ifp = &sc->arpcom.ac_if; 1214 DC_CLRBIT(sc, DC_NETCFG, (DC_NETCFG_TX_ON|DC_NETCFG_RX_ON)); 1215 1216 i = sc->dc_cdata.dc_tx_prod; 1217 DC_INC(sc->dc_cdata.dc_tx_prod, DC_TX_LIST_CNT); 1218 sc->dc_cdata.dc_tx_cnt++; 1219 sframe = &sc->dc_ldata->dc_tx_list[i]; 1220 sp = (u_int32_t *)&sc->dc_cdata.dc_sbuf; 1221 bzero((char *)sp, DC_SFRAME_LEN); 1222 1223 sframe->dc_data = vtophys(&sc->dc_cdata.dc_sbuf); 1224 sframe->dc_ctl = DC_SFRAME_LEN | DC_TXCTL_SETUP | DC_TXCTL_TLINK | 1225 DC_FILTER_HASHPERF | DC_TXCTL_FINT; 1226 1227 sc->dc_cdata.dc_tx_chain[i] = (struct mbuf *)&sc->dc_cdata.dc_sbuf; 1228 1229 /* If we want promiscuous mode, set the allframes bit. */ 1230 if (ifp->if_flags & IFF_PROMISC) 1231 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC); 1232 else 1233 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC); 1234 1235 if (ifp->if_flags & IFF_ALLMULTI) 1236 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI); 1237 else 1238 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI); 1239 1240 for (ifma = ifp->if_multiaddrs.lh_first; ifma != NULL; 1241 ifma = ifma->ifma_link.le_next) { 1242 if (ifma->ifma_addr->sa_family != AF_LINK) 1243 continue; 1244 h = dc_crc_le(sc, 1245 LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 1246 sp[h >> 4] |= 1 << (h & 0xF); 1247 } 1248 1249 if (ifp->if_flags & IFF_BROADCAST) { 1250 h = dc_crc_le(sc, (caddr_t)ðerbroadcastaddr); 1251 sp[h >> 4] |= 1 << (h & 0xF); 1252 } 1253 1254 /* Set our MAC address */ 1255 sp[0] = ((u_int16_t *)sc->arpcom.ac_enaddr)[0]; 1256 sp[1] = ((u_int16_t *)sc->arpcom.ac_enaddr)[1]; 1257 sp[2] = ((u_int16_t *)sc->arpcom.ac_enaddr)[2]; 1258 1259 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_TX_ON); 1260 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_ON); 1261 ifp->if_flags |= IFF_RUNNING; 1262 sframe->dc_status = DC_TXSTAT_OWN; 1263 CSR_WRITE_4(sc, DC_TXSTART, 0xFFFFFFFF); 1264 1265 /* 1266 * wait some time... 1267 */ 1268 DELAY(1000); 1269 1270 ifp->if_timer = 5; 1271 1272 return; 1273 } 1274 1275 static void dc_setfilt(sc) 1276 struct dc_softc *sc; 1277 { 1278 if (DC_IS_INTEL(sc) || DC_IS_MACRONIX(sc) || DC_IS_PNIC(sc) || 1279 DC_IS_PNICII(sc) || DC_IS_DAVICOM(sc)) 1280 dc_setfilt_21143(sc); 1281 1282 if (DC_IS_ASIX(sc)) 1283 dc_setfilt_asix(sc); 1284 1285 if (DC_IS_ADMTEK(sc)) 1286 dc_setfilt_admtek(sc); 1287 1288 if (DC_IS_XIRCOM(sc)) 1289 dc_setfilt_xircom(sc); 1290 1291 return; 1292 } 1293 1294 /* 1295 * In order to fiddle with the 1296 * 'full-duplex' and '100Mbps' bits in the netconfig register, we 1297 * first have to put the transmit and/or receive logic in the idle state. 1298 */ 1299 static void dc_setcfg(sc, media) 1300 struct dc_softc *sc; 1301 int media; 1302 { 1303 int i, restart = 0; 1304 u_int32_t isr; 1305 1306 if (IFM_SUBTYPE(media) == IFM_NONE) 1307 return; 1308 1309 if (CSR_READ_4(sc, DC_NETCFG) & (DC_NETCFG_TX_ON|DC_NETCFG_RX_ON)) { 1310 restart = 1; 1311 DC_CLRBIT(sc, DC_NETCFG, (DC_NETCFG_TX_ON|DC_NETCFG_RX_ON)); 1312 1313 for (i = 0; i < DC_TIMEOUT; i++) { 1314 DELAY(10); 1315 isr = CSR_READ_4(sc, DC_ISR); 1316 if (isr & DC_ISR_TX_IDLE || 1317 (isr & DC_ISR_RX_STATE) == DC_RXSTATE_STOPPED) 1318 break; 1319 } 1320 1321 if (i == DC_TIMEOUT) 1322 printf("dc%d: failed to force tx and " 1323 "rx to idle state\n", sc->dc_unit); 1324 1325 } 1326 1327 if (IFM_SUBTYPE(media) == IFM_100_TX) { 1328 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_SPEEDSEL); 1329 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_HEARTBEAT); 1330 if (sc->dc_pmode == DC_PMODE_MII) { 1331 int watchdogreg; 1332 1333 if (DC_IS_INTEL(sc)) { 1334 /* there's a write enable bit here that reads as 1 */ 1335 watchdogreg = CSR_READ_4(sc, DC_WATCHDOG); 1336 watchdogreg &= ~DC_WDOG_CTLWREN; 1337 watchdogreg |= DC_WDOG_JABBERDIS; 1338 CSR_WRITE_4(sc, DC_WATCHDOG, watchdogreg); 1339 } else { 1340 DC_SETBIT(sc, DC_WATCHDOG, DC_WDOG_JABBERDIS); 1341 } 1342 DC_CLRBIT(sc, DC_NETCFG, (DC_NETCFG_PCS| 1343 DC_NETCFG_PORTSEL|DC_NETCFG_SCRAMBLER)); 1344 if (sc->dc_type == DC_TYPE_98713) 1345 DC_SETBIT(sc, DC_NETCFG, (DC_NETCFG_PCS| 1346 DC_NETCFG_SCRAMBLER)); 1347 if (!DC_IS_DAVICOM(sc)) 1348 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL); 1349 DC_CLRBIT(sc, DC_10BTCTRL, 0xFFFF); 1350 if (DC_IS_INTEL(sc)) 1351 dc_apply_fixup(sc, IFM_AUTO); 1352 } else { 1353 if (DC_IS_PNIC(sc)) { 1354 DC_PN_GPIO_SETBIT(sc, DC_PN_GPIO_SPEEDSEL); 1355 DC_PN_GPIO_SETBIT(sc, DC_PN_GPIO_100TX_LOOP); 1356 DC_SETBIT(sc, DC_PN_NWAY, DC_PN_NWAY_SPEEDSEL); 1357 } 1358 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL); 1359 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PCS); 1360 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_SCRAMBLER); 1361 if (DC_IS_INTEL(sc)) 1362 dc_apply_fixup(sc, 1363 (media & IFM_GMASK) == IFM_FDX ? 1364 IFM_100_TX|IFM_FDX : IFM_100_TX); 1365 } 1366 } 1367 1368 if (IFM_SUBTYPE(media) == IFM_10_T) { 1369 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_SPEEDSEL); 1370 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_HEARTBEAT); 1371 if (sc->dc_pmode == DC_PMODE_MII) { 1372 int watchdogreg; 1373 1374 /* there's a write enable bit here that reads as 1 */ 1375 if (DC_IS_INTEL(sc)) { 1376 watchdogreg = CSR_READ_4(sc, DC_WATCHDOG); 1377 watchdogreg &= ~DC_WDOG_CTLWREN; 1378 watchdogreg |= DC_WDOG_JABBERDIS; 1379 CSR_WRITE_4(sc, DC_WATCHDOG, watchdogreg); 1380 } else { 1381 DC_SETBIT(sc, DC_WATCHDOG, DC_WDOG_JABBERDIS); 1382 } 1383 DC_CLRBIT(sc, DC_NETCFG, (DC_NETCFG_PCS| 1384 DC_NETCFG_PORTSEL|DC_NETCFG_SCRAMBLER)); 1385 if (sc->dc_type == DC_TYPE_98713) 1386 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PCS); 1387 if (!DC_IS_DAVICOM(sc)) 1388 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL); 1389 DC_CLRBIT(sc, DC_10BTCTRL, 0xFFFF); 1390 if (DC_IS_INTEL(sc)) 1391 dc_apply_fixup(sc, IFM_AUTO); 1392 } else { 1393 if (DC_IS_PNIC(sc)) { 1394 DC_PN_GPIO_CLRBIT(sc, DC_PN_GPIO_SPEEDSEL); 1395 DC_PN_GPIO_SETBIT(sc, DC_PN_GPIO_100TX_LOOP); 1396 DC_CLRBIT(sc, DC_PN_NWAY, DC_PN_NWAY_SPEEDSEL); 1397 } 1398 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL); 1399 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_PCS); 1400 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_SCRAMBLER); 1401 if (DC_IS_INTEL(sc)) { 1402 DC_CLRBIT(sc, DC_SIARESET, DC_SIA_RESET); 1403 DC_CLRBIT(sc, DC_10BTCTRL, 0xFFFF); 1404 if ((media & IFM_GMASK) == IFM_FDX) 1405 DC_SETBIT(sc, DC_10BTCTRL, 0x7F3D); 1406 else 1407 DC_SETBIT(sc, DC_10BTCTRL, 0x7F3F); 1408 DC_SETBIT(sc, DC_SIARESET, DC_SIA_RESET); 1409 DC_CLRBIT(sc, DC_10BTCTRL, 1410 DC_TCTL_AUTONEGENBL); 1411 dc_apply_fixup(sc, 1412 (media & IFM_GMASK) == IFM_FDX ? 1413 IFM_10_T|IFM_FDX : IFM_10_T); 1414 DELAY(20000); 1415 } 1416 } 1417 } 1418 1419 /* 1420 * If this is a Davicom DM9102A card with a DM9801 HomePNA 1421 * PHY and we want HomePNA mode, set the portsel bit to turn 1422 * on the external MII port. 1423 */ 1424 if (DC_IS_DAVICOM(sc)) { 1425 if (IFM_SUBTYPE(media) == IFM_homePNA) { 1426 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL); 1427 sc->dc_link = 1; 1428 } else { 1429 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL); 1430 } 1431 } 1432 1433 if ((media & IFM_GMASK) == IFM_FDX) { 1434 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_FULLDUPLEX); 1435 if (sc->dc_pmode == DC_PMODE_SYM && DC_IS_PNIC(sc)) 1436 DC_SETBIT(sc, DC_PN_NWAY, DC_PN_NWAY_DUPLEX); 1437 } else { 1438 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_FULLDUPLEX); 1439 if (sc->dc_pmode == DC_PMODE_SYM && DC_IS_PNIC(sc)) 1440 DC_CLRBIT(sc, DC_PN_NWAY, DC_PN_NWAY_DUPLEX); 1441 } 1442 1443 if (restart) 1444 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_TX_ON|DC_NETCFG_RX_ON); 1445 1446 return; 1447 } 1448 1449 static void dc_reset(sc) 1450 struct dc_softc *sc; 1451 { 1452 register int i; 1453 1454 DC_SETBIT(sc, DC_BUSCTL, DC_BUSCTL_RESET); 1455 1456 for (i = 0; i < DC_TIMEOUT; i++) { 1457 DELAY(10); 1458 if (!(CSR_READ_4(sc, DC_BUSCTL) & DC_BUSCTL_RESET)) 1459 break; 1460 } 1461 1462 if (DC_IS_ASIX(sc) || DC_IS_ADMTEK(sc) || 1463 DC_IS_XIRCOM(sc) || DC_IS_INTEL(sc)) { 1464 DELAY(10000); 1465 DC_CLRBIT(sc, DC_BUSCTL, DC_BUSCTL_RESET); 1466 i = 0; 1467 } 1468 1469 if (i == DC_TIMEOUT) 1470 printf("dc%d: reset never completed!\n", sc->dc_unit); 1471 1472 /* Wait a little while for the chip to get its brains in order. */ 1473 DELAY(1000); 1474 1475 CSR_WRITE_4(sc, DC_IMR, 0x00000000); 1476 CSR_WRITE_4(sc, DC_BUSCTL, 0x00000000); 1477 CSR_WRITE_4(sc, DC_NETCFG, 0x00000000); 1478 1479 /* 1480 * Bring the SIA out of reset. In some cases, it looks 1481 * like failing to unreset the SIA soon enough gets it 1482 * into a state where it will never come out of reset 1483 * until we reset the whole chip again. 1484 */ 1485 if (DC_IS_INTEL(sc)) { 1486 DC_SETBIT(sc, DC_SIARESET, DC_SIA_RESET); 1487 CSR_WRITE_4(sc, DC_10BTCTRL, 0); 1488 CSR_WRITE_4(sc, DC_WATCHDOG, 0); 1489 } 1490 1491 return; 1492 } 1493 1494 static struct dc_type *dc_devtype(dev) 1495 device_t dev; 1496 { 1497 struct dc_type *t; 1498 u_int32_t rev; 1499 1500 t = dc_devs; 1501 1502 while(t->dc_name != NULL) { 1503 if ((pci_get_vendor(dev) == t->dc_vid) && 1504 (pci_get_device(dev) == t->dc_did)) { 1505 /* Check the PCI revision */ 1506 rev = pci_read_config(dev, DC_PCI_CFRV, 4) & 0xFF; 1507 if (t->dc_did == DC_DEVICEID_98713 && 1508 rev >= DC_REVISION_98713A) 1509 t++; 1510 if (t->dc_did == DC_DEVICEID_98713_CP && 1511 rev >= DC_REVISION_98713A) 1512 t++; 1513 if (t->dc_did == DC_DEVICEID_987x5 && 1514 rev >= DC_REVISION_98715AEC_C) 1515 t++; 1516 if (t->dc_did == DC_DEVICEID_987x5 && 1517 rev >= DC_REVISION_98725) 1518 t++; 1519 if (t->dc_did == DC_DEVICEID_AX88140A && 1520 rev >= DC_REVISION_88141) 1521 t++; 1522 if (t->dc_did == DC_DEVICEID_82C168 && 1523 rev >= DC_REVISION_82C169) 1524 t++; 1525 if (t->dc_did == DC_DEVICEID_DM9102 && 1526 rev >= DC_REVISION_DM9102A) 1527 t++; 1528 return(t); 1529 } 1530 t++; 1531 } 1532 1533 return(NULL); 1534 } 1535 1536 /* 1537 * Probe for a 21143 or clone chip. Check the PCI vendor and device 1538 * IDs against our list and return a device name if we find a match. 1539 * We do a little bit of extra work to identify the exact type of 1540 * chip. The MX98713 and MX98713A have the same PCI vendor/device ID, 1541 * but different revision IDs. The same is true for 98715/98715A 1542 * chips and the 98725, as well as the ASIX and ADMtek chips. In some 1543 * cases, the exact chip revision affects driver behavior. 1544 */ 1545 static int dc_probe(dev) 1546 device_t dev; 1547 { 1548 struct dc_type *t; 1549 1550 t = dc_devtype(dev); 1551 1552 if (t != NULL) { 1553 device_set_desc(dev, t->dc_name); 1554 return(0); 1555 } 1556 1557 return(ENXIO); 1558 } 1559 1560 static void dc_acpi(dev) 1561 device_t dev; 1562 { 1563 u_int32_t r, cptr; 1564 int unit; 1565 1566 unit = device_get_unit(dev); 1567 1568 /* Find the location of the capabilities block */ 1569 cptr = pci_read_config(dev, DC_PCI_CCAP, 4) & 0xFF; 1570 1571 r = pci_read_config(dev, cptr, 4) & 0xFF; 1572 if (r == 0x01) { 1573 1574 r = pci_read_config(dev, cptr + 4, 4); 1575 if (r & DC_PSTATE_D3) { 1576 u_int32_t iobase, membase, irq; 1577 1578 /* Save important PCI config data. */ 1579 iobase = pci_read_config(dev, DC_PCI_CFBIO, 4); 1580 membase = pci_read_config(dev, DC_PCI_CFBMA, 4); 1581 irq = pci_read_config(dev, DC_PCI_CFIT, 4); 1582 1583 /* Reset the power state. */ 1584 printf("dc%d: chip is in D%d power mode " 1585 "-- setting to D0\n", unit, r & DC_PSTATE_D3); 1586 r &= 0xFFFFFFFC; 1587 pci_write_config(dev, cptr + 4, r, 4); 1588 1589 /* Restore PCI config data. */ 1590 pci_write_config(dev, DC_PCI_CFBIO, iobase, 4); 1591 pci_write_config(dev, DC_PCI_CFBMA, membase, 4); 1592 pci_write_config(dev, DC_PCI_CFIT, irq, 4); 1593 } 1594 } 1595 return; 1596 } 1597 1598 static void dc_apply_fixup(sc, media) 1599 struct dc_softc *sc; 1600 int media; 1601 { 1602 struct dc_mediainfo *m; 1603 u_int8_t *p; 1604 int i; 1605 u_int32_t reg; 1606 1607 m = sc->dc_mi; 1608 1609 while (m != NULL) { 1610 if (m->dc_media == media) 1611 break; 1612 m = m->dc_next; 1613 } 1614 1615 if (m == NULL) 1616 return; 1617 1618 for (i = 0, p = m->dc_reset_ptr; i < m->dc_reset_len; i++, p += 2) { 1619 reg = (p[0] | (p[1] << 8)) << 16; 1620 CSR_WRITE_4(sc, DC_WATCHDOG, reg); 1621 } 1622 1623 for (i = 0, p = m->dc_gp_ptr; i < m->dc_gp_len; i++, p += 2) { 1624 reg = (p[0] | (p[1] << 8)) << 16; 1625 CSR_WRITE_4(sc, DC_WATCHDOG, reg); 1626 } 1627 1628 return; 1629 } 1630 1631 static void dc_decode_leaf_sia(sc, l) 1632 struct dc_softc *sc; 1633 struct dc_eblock_sia *l; 1634 { 1635 struct dc_mediainfo *m; 1636 1637 m = malloc(sizeof(struct dc_mediainfo), M_DEVBUF, M_NOWAIT); 1638 if (l->dc_sia_code == DC_SIA_CODE_10BT) 1639 m->dc_media = IFM_10_T; 1640 1641 if (l->dc_sia_code == DC_SIA_CODE_10BT_FDX) 1642 m->dc_media = IFM_10_T|IFM_FDX; 1643 1644 if (l->dc_sia_code == DC_SIA_CODE_10B2) 1645 m->dc_media = IFM_10_2; 1646 1647 if (l->dc_sia_code == DC_SIA_CODE_10B5) 1648 m->dc_media = IFM_10_5; 1649 1650 m->dc_gp_len = 2; 1651 m->dc_gp_ptr = (u_int8_t *)&l->dc_sia_gpio_ctl; 1652 1653 m->dc_next = sc->dc_mi; 1654 sc->dc_mi = m; 1655 1656 sc->dc_pmode = DC_PMODE_SIA; 1657 1658 return; 1659 } 1660 1661 static void dc_decode_leaf_sym(sc, l) 1662 struct dc_softc *sc; 1663 struct dc_eblock_sym *l; 1664 { 1665 struct dc_mediainfo *m; 1666 1667 m = malloc(sizeof(struct dc_mediainfo), M_DEVBUF, M_NOWAIT); 1668 if (l->dc_sym_code == DC_SYM_CODE_100BT) 1669 m->dc_media = IFM_100_TX; 1670 1671 if (l->dc_sym_code == DC_SYM_CODE_100BT_FDX) 1672 m->dc_media = IFM_100_TX|IFM_FDX; 1673 1674 m->dc_gp_len = 2; 1675 m->dc_gp_ptr = (u_int8_t *)&l->dc_sym_gpio_ctl; 1676 1677 m->dc_next = sc->dc_mi; 1678 sc->dc_mi = m; 1679 1680 sc->dc_pmode = DC_PMODE_SYM; 1681 1682 return; 1683 } 1684 1685 static void dc_decode_leaf_mii(sc, l) 1686 struct dc_softc *sc; 1687 struct dc_eblock_mii *l; 1688 { 1689 u_int8_t *p; 1690 struct dc_mediainfo *m; 1691 1692 m = malloc(sizeof(struct dc_mediainfo), M_DEVBUF, M_NOWAIT); 1693 /* We abuse IFM_AUTO to represent MII. */ 1694 m->dc_media = IFM_AUTO; 1695 m->dc_gp_len = l->dc_gpr_len; 1696 1697 p = (u_int8_t *)l; 1698 p += sizeof(struct dc_eblock_mii); 1699 m->dc_gp_ptr = p; 1700 p += 2 * l->dc_gpr_len; 1701 m->dc_reset_len = *p; 1702 p++; 1703 m->dc_reset_ptr = p; 1704 1705 m->dc_next = sc->dc_mi; 1706 sc->dc_mi = m; 1707 1708 return; 1709 } 1710 1711 static void dc_parse_21143_srom(sc) 1712 struct dc_softc *sc; 1713 { 1714 struct dc_leaf_hdr *lhdr; 1715 struct dc_eblock_hdr *hdr; 1716 int i, loff; 1717 char *ptr; 1718 1719 loff = sc->dc_srom[27]; 1720 lhdr = (struct dc_leaf_hdr *)&(sc->dc_srom[loff]); 1721 1722 ptr = (char *)lhdr; 1723 ptr += sizeof(struct dc_leaf_hdr) - 1; 1724 for (i = 0; i < lhdr->dc_mcnt; i++) { 1725 hdr = (struct dc_eblock_hdr *)ptr; 1726 switch(hdr->dc_type) { 1727 case DC_EBLOCK_MII: 1728 dc_decode_leaf_mii(sc, (struct dc_eblock_mii *)hdr); 1729 break; 1730 case DC_EBLOCK_SIA: 1731 dc_decode_leaf_sia(sc, (struct dc_eblock_sia *)hdr); 1732 break; 1733 case DC_EBLOCK_SYM: 1734 dc_decode_leaf_sym(sc, (struct dc_eblock_sym *)hdr); 1735 break; 1736 default: 1737 /* Don't care. Yet. */ 1738 break; 1739 } 1740 ptr += (hdr->dc_len & 0x7F); 1741 ptr++; 1742 } 1743 1744 return; 1745 } 1746 1747 /* 1748 * Attach the interface. Allocate softc structures, do ifmedia 1749 * setup and ethernet/BPF attach. 1750 */ 1751 static int dc_attach(dev) 1752 device_t dev; 1753 { 1754 int tmp = 0; 1755 u_char eaddr[ETHER_ADDR_LEN]; 1756 u_int32_t command; 1757 struct dc_softc *sc; 1758 struct ifnet *ifp; 1759 u_int32_t revision; 1760 int unit, error = 0, rid, mac_offset; 1761 1762 sc = device_get_softc(dev); 1763 unit = device_get_unit(dev); 1764 bzero(sc, sizeof(struct dc_softc)); 1765 1766 /* 1767 * Handle power management nonsense. 1768 */ 1769 dc_acpi(dev); 1770 1771 /* 1772 * Map control/status registers. 1773 */ 1774 command = pci_read_config(dev, PCIR_COMMAND, 4); 1775 command |= (PCIM_CMD_PORTEN|PCIM_CMD_MEMEN|PCIM_CMD_BUSMASTEREN); 1776 pci_write_config(dev, PCIR_COMMAND, command, 4); 1777 command = pci_read_config(dev, PCIR_COMMAND, 4); 1778 1779 #ifdef DC_USEIOSPACE 1780 if (!(command & PCIM_CMD_PORTEN)) { 1781 printf("dc%d: failed to enable I/O ports!\n", unit); 1782 error = ENXIO; 1783 goto fail; 1784 } 1785 #else 1786 if (!(command & PCIM_CMD_MEMEN)) { 1787 printf("dc%d: failed to enable memory mapping!\n", unit); 1788 error = ENXIO; 1789 goto fail; 1790 } 1791 #endif 1792 1793 rid = DC_RID; 1794 sc->dc_res = bus_alloc_resource(dev, DC_RES, &rid, 1795 0, ~0, 1, RF_ACTIVE); 1796 1797 if (sc->dc_res == NULL) { 1798 printf("dc%d: couldn't map ports/memory\n", unit); 1799 error = ENXIO; 1800 goto fail; 1801 } 1802 1803 sc->dc_btag = rman_get_bustag(sc->dc_res); 1804 sc->dc_bhandle = rman_get_bushandle(sc->dc_res); 1805 1806 /* Allocate interrupt */ 1807 rid = 0; 1808 sc->dc_irq = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, 0, ~0, 1, 1809 RF_SHAREABLE | RF_ACTIVE); 1810 1811 if (sc->dc_irq == NULL) { 1812 printf("dc%d: couldn't map interrupt\n", unit); 1813 bus_release_resource(dev, DC_RES, DC_RID, sc->dc_res); 1814 error = ENXIO; 1815 goto fail; 1816 } 1817 1818 error = bus_setup_intr(dev, sc->dc_irq, INTR_TYPE_NET, 1819 dc_intr, sc, &sc->dc_intrhand); 1820 1821 if (error) { 1822 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->dc_irq); 1823 bus_release_resource(dev, DC_RES, DC_RID, sc->dc_res); 1824 printf("dc%d: couldn't set up irq\n", unit); 1825 goto fail; 1826 } 1827 1828 mtx_init(&sc->dc_mtx, device_get_nameunit(dev), MTX_DEF); 1829 DC_LOCK(sc); 1830 /* Need this info to decide on a chip type. */ 1831 sc->dc_info = dc_devtype(dev); 1832 revision = pci_read_config(dev, DC_PCI_CFRV, 4) & 0x000000FF; 1833 1834 switch(sc->dc_info->dc_did) { 1835 case DC_DEVICEID_21143: 1836 sc->dc_type = DC_TYPE_21143; 1837 sc->dc_flags |= DC_TX_POLL|DC_TX_USE_TX_INTR; 1838 sc->dc_flags |= DC_REDUCED_MII_POLL; 1839 /* Save EEPROM contents so we can parse them later. */ 1840 dc_read_eeprom(sc, (caddr_t)&sc->dc_srom, 0, 512, 0); 1841 break; 1842 case DC_DEVICEID_DM9100: 1843 case DC_DEVICEID_DM9102: 1844 sc->dc_type = DC_TYPE_DM9102; 1845 sc->dc_flags |= DC_TX_COALESCE|DC_TX_INTR_ALWAYS; 1846 sc->dc_flags |= DC_REDUCED_MII_POLL|DC_TX_STORENFWD; 1847 sc->dc_pmode = DC_PMODE_MII; 1848 /* Increase the latency timer value. */ 1849 command = pci_read_config(dev, DC_PCI_CFLT, 4); 1850 command &= 0xFFFF00FF; 1851 command |= 0x00008000; 1852 pci_write_config(dev, DC_PCI_CFLT, command, 4); 1853 break; 1854 case DC_DEVICEID_AL981: 1855 sc->dc_type = DC_TYPE_AL981; 1856 sc->dc_flags |= DC_TX_USE_TX_INTR; 1857 sc->dc_flags |= DC_TX_ADMTEK_WAR; 1858 sc->dc_pmode = DC_PMODE_MII; 1859 break; 1860 case DC_DEVICEID_AN985: 1861 case DC_DEVICEID_FE2500: 1862 sc->dc_type = DC_TYPE_AN985; 1863 sc->dc_flags |= DC_TX_USE_TX_INTR; 1864 sc->dc_flags |= DC_TX_ADMTEK_WAR; 1865 sc->dc_pmode = DC_PMODE_MII; 1866 break; 1867 case DC_DEVICEID_98713: 1868 case DC_DEVICEID_98713_CP: 1869 if (revision < DC_REVISION_98713A) { 1870 sc->dc_type = DC_TYPE_98713; 1871 } 1872 if (revision >= DC_REVISION_98713A) { 1873 sc->dc_type = DC_TYPE_98713A; 1874 sc->dc_flags |= DC_21143_NWAY; 1875 } 1876 sc->dc_flags |= DC_REDUCED_MII_POLL; 1877 sc->dc_flags |= DC_TX_POLL|DC_TX_USE_TX_INTR; 1878 break; 1879 case DC_DEVICEID_987x5: 1880 case DC_DEVICEID_EN1217: 1881 /* 1882 * Macronix MX98715AEC-C/D/E parts have only a 1883 * 128-bit hash table. We need to deal with these 1884 * in the same manner as the PNIC II so that we 1885 * get the right number of bits out of the 1886 * CRC routine. 1887 */ 1888 if (revision >= DC_REVISION_98715AEC_C && 1889 revision < DC_REVISION_98725) 1890 sc->dc_flags |= DC_128BIT_HASH; 1891 sc->dc_type = DC_TYPE_987x5; 1892 sc->dc_flags |= DC_TX_POLL|DC_TX_USE_TX_INTR; 1893 sc->dc_flags |= DC_REDUCED_MII_POLL|DC_21143_NWAY; 1894 break; 1895 case DC_DEVICEID_98727: 1896 sc->dc_type = DC_TYPE_987x5; 1897 sc->dc_flags |= DC_TX_POLL|DC_TX_USE_TX_INTR; 1898 sc->dc_flags |= DC_REDUCED_MII_POLL|DC_21143_NWAY; 1899 break; 1900 case DC_DEVICEID_82C115: 1901 sc->dc_type = DC_TYPE_PNICII; 1902 sc->dc_flags |= DC_TX_POLL|DC_TX_USE_TX_INTR|DC_128BIT_HASH; 1903 sc->dc_flags |= DC_REDUCED_MII_POLL|DC_21143_NWAY; 1904 break; 1905 case DC_DEVICEID_82C168: 1906 sc->dc_type = DC_TYPE_PNIC; 1907 sc->dc_flags |= DC_TX_STORENFWD|DC_TX_INTR_ALWAYS; 1908 sc->dc_flags |= DC_PNIC_RX_BUG_WAR; 1909 sc->dc_pnic_rx_buf = malloc(DC_RXLEN * 5, M_DEVBUF, M_NOWAIT); 1910 if (revision < DC_REVISION_82C169) 1911 sc->dc_pmode = DC_PMODE_SYM; 1912 break; 1913 case DC_DEVICEID_AX88140A: 1914 sc->dc_type = DC_TYPE_ASIX; 1915 sc->dc_flags |= DC_TX_USE_TX_INTR|DC_TX_INTR_FIRSTFRAG; 1916 sc->dc_flags |= DC_REDUCED_MII_POLL; 1917 sc->dc_pmode = DC_PMODE_MII; 1918 break; 1919 case DC_DEVICEID_X3201: 1920 sc->dc_type = DC_TYPE_XIRCOM; 1921 sc->dc_flags |= DC_TX_INTR_ALWAYS | DC_TX_COALESCE; 1922 /* 1923 * We don't actually need to coalesce, but we're doing 1924 * it to obtain a double word aligned buffer. 1925 */ 1926 break; 1927 default: 1928 printf("dc%d: unknown device: %x\n", sc->dc_unit, 1929 sc->dc_info->dc_did); 1930 break; 1931 } 1932 1933 /* Save the cache line size. */ 1934 if (DC_IS_DAVICOM(sc)) 1935 sc->dc_cachesize = 0; 1936 else 1937 sc->dc_cachesize = pci_read_config(dev, 1938 DC_PCI_CFLT, 4) & 0xFF; 1939 1940 /* Reset the adapter. */ 1941 dc_reset(sc); 1942 1943 /* Take 21143 out of snooze mode */ 1944 if (DC_IS_INTEL(sc) || DC_IS_XIRCOM(sc)) { 1945 command = pci_read_config(dev, DC_PCI_CFDD, 4); 1946 command &= ~(DC_CFDD_SNOOZE_MODE|DC_CFDD_SLEEP_MODE); 1947 pci_write_config(dev, DC_PCI_CFDD, command, 4); 1948 } 1949 1950 /* 1951 * Try to learn something about the supported media. 1952 * We know that ASIX and ADMtek and Davicom devices 1953 * will *always* be using MII media, so that's a no-brainer. 1954 * The tricky ones are the Macronix/PNIC II and the 1955 * Intel 21143. 1956 */ 1957 if (DC_IS_INTEL(sc)) 1958 dc_parse_21143_srom(sc); 1959 else if (DC_IS_MACRONIX(sc) || DC_IS_PNICII(sc)) { 1960 if (sc->dc_type == DC_TYPE_98713) 1961 sc->dc_pmode = DC_PMODE_MII; 1962 else 1963 sc->dc_pmode = DC_PMODE_SYM; 1964 } else if (!sc->dc_pmode) 1965 sc->dc_pmode = DC_PMODE_MII; 1966 1967 /* 1968 * Get station address from the EEPROM. 1969 */ 1970 switch(sc->dc_type) { 1971 case DC_TYPE_98713: 1972 case DC_TYPE_98713A: 1973 case DC_TYPE_987x5: 1974 case DC_TYPE_PNICII: 1975 dc_read_eeprom(sc, (caddr_t)&mac_offset, 1976 (DC_EE_NODEADDR_OFFSET / 2), 1, 0); 1977 dc_read_eeprom(sc, (caddr_t)&eaddr, (mac_offset / 2), 3, 0); 1978 break; 1979 case DC_TYPE_PNIC: 1980 dc_read_eeprom(sc, (caddr_t)&eaddr, 0, 3, 1); 1981 break; 1982 case DC_TYPE_DM9102: 1983 case DC_TYPE_21143: 1984 case DC_TYPE_ASIX: 1985 dc_read_eeprom(sc, (caddr_t)&eaddr, DC_EE_NODEADDR, 3, 0); 1986 break; 1987 case DC_TYPE_AL981: 1988 case DC_TYPE_AN985: 1989 dc_read_eeprom(sc, (caddr_t)&eaddr, DC_AL_EE_NODEADDR, 3, 0); 1990 break; 1991 case DC_TYPE_XIRCOM: 1992 dc_read_eeprom(sc, (caddr_t)&eaddr, 3, 3, 0); 1993 break; 1994 default: 1995 dc_read_eeprom(sc, (caddr_t)&eaddr, DC_EE_NODEADDR, 3, 0); 1996 break; 1997 } 1998 1999 /* 2000 * A 21143 or clone chip was detected. Inform the world. 2001 */ 2002 printf("dc%d: Ethernet address: %6D\n", unit, eaddr, ":"); 2003 2004 sc->dc_unit = unit; 2005 bcopy(eaddr, (char *)&sc->arpcom.ac_enaddr, ETHER_ADDR_LEN); 2006 2007 sc->dc_ldata = contigmalloc(sizeof(struct dc_list_data), M_DEVBUF, 2008 M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0); 2009 2010 if (sc->dc_ldata == NULL) { 2011 printf("dc%d: no memory for list buffers!\n", unit); 2012 bus_teardown_intr(dev, sc->dc_irq, sc->dc_intrhand); 2013 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->dc_irq); 2014 bus_release_resource(dev, DC_RES, DC_RID, sc->dc_res); 2015 error = ENXIO; 2016 goto fail; 2017 } 2018 2019 bzero(sc->dc_ldata, sizeof(struct dc_list_data)); 2020 2021 ifp = &sc->arpcom.ac_if; 2022 ifp->if_softc = sc; 2023 ifp->if_unit = unit; 2024 ifp->if_name = "dc"; 2025 /* XXX: bleah, MTU gets overwritten in ether_ifattach() */ 2026 ifp->if_mtu = ETHERMTU; 2027 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 2028 ifp->if_ioctl = dc_ioctl; 2029 ifp->if_output = ether_output; 2030 ifp->if_start = dc_start; 2031 ifp->if_watchdog = dc_watchdog; 2032 ifp->if_init = dc_init; 2033 ifp->if_baudrate = 10000000; 2034 ifp->if_snd.ifq_maxlen = DC_TX_LIST_CNT - 1; 2035 2036 /* 2037 * Do MII setup. If this is a 21143, check for a PHY on the 2038 * MII bus after applying any necessary fixups to twiddle the 2039 * GPIO bits. If we don't end up finding a PHY, restore the 2040 * old selection (SIA only or SIA/SYM) and attach the dcphy 2041 * driver instead. 2042 */ 2043 if (DC_IS_INTEL(sc)) { 2044 dc_apply_fixup(sc, IFM_AUTO); 2045 tmp = sc->dc_pmode; 2046 sc->dc_pmode = DC_PMODE_MII; 2047 } 2048 2049 error = mii_phy_probe(dev, &sc->dc_miibus, 2050 dc_ifmedia_upd, dc_ifmedia_sts); 2051 2052 if (error && DC_IS_INTEL(sc)) { 2053 sc->dc_pmode = tmp; 2054 if (sc->dc_pmode != DC_PMODE_SIA) 2055 sc->dc_pmode = DC_PMODE_SYM; 2056 sc->dc_flags |= DC_21143_NWAY; 2057 mii_phy_probe(dev, &sc->dc_miibus, 2058 dc_ifmedia_upd, dc_ifmedia_sts); 2059 /* 2060 * For non-MII cards, we need to have the 21143 2061 * drive the LEDs. Except there are some systems 2062 * like the NEC VersaPro NoteBook PC which have no 2063 * LEDs, and twiddling these bits has adverse effects 2064 * on them. (I.e. you suddenly can't get a link.) 2065 */ 2066 if (pci_read_config(dev, DC_PCI_CSID, 4) != 0x80281033) 2067 sc->dc_flags |= DC_TULIP_LEDS; 2068 error = 0; 2069 } 2070 2071 if (error) { 2072 printf("dc%d: MII without any PHY!\n", sc->dc_unit); 2073 bus_teardown_intr(dev, sc->dc_irq, sc->dc_intrhand); 2074 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->dc_irq); 2075 bus_release_resource(dev, DC_RES, DC_RID, sc->dc_res); 2076 error = ENXIO; 2077 goto fail; 2078 } 2079 2080 if (DC_IS_XIRCOM(sc)) { 2081 /* 2082 * setup General Purpose Port mode and data so the tulip 2083 * can talk to the MII. 2084 */ 2085 CSR_WRITE_4(sc, DC_SIAGP, DC_SIAGP_WRITE_EN | DC_SIAGP_INT1_EN | 2086 DC_SIAGP_MD_GP2_OUTPUT | DC_SIAGP_MD_GP0_OUTPUT); 2087 DELAY(10); 2088 CSR_WRITE_4(sc, DC_SIAGP, DC_SIAGP_INT1_EN | 2089 DC_SIAGP_MD_GP2_OUTPUT | DC_SIAGP_MD_GP0_OUTPUT); 2090 DELAY(10); 2091 } 2092 2093 /* 2094 * Call MI attach routine. 2095 */ 2096 ether_ifattach(ifp, ETHER_BPF_SUPPORTED); 2097 callout_handle_init(&sc->dc_stat_ch); 2098 2099 #ifdef SRM_MEDIA 2100 sc->dc_srm_media = 0; 2101 2102 /* Remember the SRM console media setting */ 2103 if (DC_IS_INTEL(sc)) { 2104 command = pci_read_config(dev, DC_PCI_CFDD, 4); 2105 command &= ~(DC_CFDD_SNOOZE_MODE|DC_CFDD_SLEEP_MODE); 2106 switch ((command >> 8) & 0xff) { 2107 case 3: 2108 sc->dc_srm_media = IFM_10_T; 2109 break; 2110 case 4: 2111 sc->dc_srm_media = IFM_10_T | IFM_FDX; 2112 break; 2113 case 5: 2114 sc->dc_srm_media = IFM_100_TX; 2115 break; 2116 case 6: 2117 sc->dc_srm_media = IFM_100_TX | IFM_FDX; 2118 break; 2119 } 2120 if (sc->dc_srm_media) 2121 sc->dc_srm_media |= IFM_ACTIVE | IFM_ETHER; 2122 } 2123 #endif 2124 2125 DC_UNLOCK(sc); 2126 return(0); 2127 2128 fail: 2129 DC_UNLOCK(sc); 2130 mtx_destroy(&sc->dc_mtx); 2131 return(error); 2132 } 2133 2134 static int dc_detach(dev) 2135 device_t dev; 2136 { 2137 struct dc_softc *sc; 2138 struct ifnet *ifp; 2139 struct dc_mediainfo *m; 2140 2141 sc = device_get_softc(dev); 2142 2143 DC_LOCK(sc); 2144 2145 ifp = &sc->arpcom.ac_if; 2146 2147 dc_stop(sc); 2148 ether_ifdetach(ifp, ETHER_BPF_SUPPORTED); 2149 2150 bus_generic_detach(dev); 2151 device_delete_child(dev, sc->dc_miibus); 2152 2153 bus_teardown_intr(dev, sc->dc_irq, sc->dc_intrhand); 2154 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->dc_irq); 2155 bus_release_resource(dev, DC_RES, DC_RID, sc->dc_res); 2156 2157 contigfree(sc->dc_ldata, sizeof(struct dc_list_data), M_DEVBUF); 2158 if (sc->dc_pnic_rx_buf != NULL) 2159 free(sc->dc_pnic_rx_buf, M_DEVBUF); 2160 2161 while(sc->dc_mi != NULL) { 2162 m = sc->dc_mi->dc_next; 2163 free(sc->dc_mi, M_DEVBUF); 2164 sc->dc_mi = m; 2165 } 2166 2167 DC_UNLOCK(sc); 2168 mtx_destroy(&sc->dc_mtx); 2169 2170 return(0); 2171 } 2172 2173 /* 2174 * Initialize the transmit descriptors. 2175 */ 2176 static int dc_list_tx_init(sc) 2177 struct dc_softc *sc; 2178 { 2179 struct dc_chain_data *cd; 2180 struct dc_list_data *ld; 2181 int i; 2182 2183 cd = &sc->dc_cdata; 2184 ld = sc->dc_ldata; 2185 for (i = 0; i < DC_TX_LIST_CNT; i++) { 2186 if (i == (DC_TX_LIST_CNT - 1)) { 2187 ld->dc_tx_list[i].dc_next = 2188 vtophys(&ld->dc_tx_list[0]); 2189 } else { 2190 ld->dc_tx_list[i].dc_next = 2191 vtophys(&ld->dc_tx_list[i + 1]); 2192 } 2193 cd->dc_tx_chain[i] = NULL; 2194 ld->dc_tx_list[i].dc_data = 0; 2195 ld->dc_tx_list[i].dc_ctl = 0; 2196 } 2197 2198 cd->dc_tx_prod = cd->dc_tx_cons = cd->dc_tx_cnt = 0; 2199 2200 return(0); 2201 } 2202 2203 2204 /* 2205 * Initialize the RX descriptors and allocate mbufs for them. Note that 2206 * we arrange the descriptors in a closed ring, so that the last descriptor 2207 * points back to the first. 2208 */ 2209 static int dc_list_rx_init(sc) 2210 struct dc_softc *sc; 2211 { 2212 struct dc_chain_data *cd; 2213 struct dc_list_data *ld; 2214 int i; 2215 2216 cd = &sc->dc_cdata; 2217 ld = sc->dc_ldata; 2218 2219 for (i = 0; i < DC_RX_LIST_CNT; i++) { 2220 if (dc_newbuf(sc, i, NULL) == ENOBUFS) 2221 return(ENOBUFS); 2222 if (i == (DC_RX_LIST_CNT - 1)) { 2223 ld->dc_rx_list[i].dc_next = 2224 vtophys(&ld->dc_rx_list[0]); 2225 } else { 2226 ld->dc_rx_list[i].dc_next = 2227 vtophys(&ld->dc_rx_list[i + 1]); 2228 } 2229 } 2230 2231 cd->dc_rx_prod = 0; 2232 2233 return(0); 2234 } 2235 2236 /* 2237 * Initialize an RX descriptor and attach an MBUF cluster. 2238 */ 2239 static int dc_newbuf(sc, i, m) 2240 struct dc_softc *sc; 2241 int i; 2242 struct mbuf *m; 2243 { 2244 struct mbuf *m_new = NULL; 2245 struct dc_desc *c; 2246 2247 c = &sc->dc_ldata->dc_rx_list[i]; 2248 2249 if (m == NULL) { 2250 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 2251 if (m_new == NULL) { 2252 printf("dc%d: no memory for rx list " 2253 "-- packet dropped!\n", sc->dc_unit); 2254 return(ENOBUFS); 2255 } 2256 2257 MCLGET(m_new, M_DONTWAIT); 2258 if (!(m_new->m_flags & M_EXT)) { 2259 printf("dc%d: no memory for rx list " 2260 "-- packet dropped!\n", sc->dc_unit); 2261 m_freem(m_new); 2262 return(ENOBUFS); 2263 } 2264 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 2265 } else { 2266 m_new = m; 2267 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 2268 m_new->m_data = m_new->m_ext.ext_buf; 2269 } 2270 2271 m_adj(m_new, sizeof(u_int64_t)); 2272 2273 /* 2274 * If this is a PNIC chip, zero the buffer. This is part 2275 * of the workaround for the receive bug in the 82c168 and 2276 * 82c169 chips. 2277 */ 2278 if (sc->dc_flags & DC_PNIC_RX_BUG_WAR) 2279 bzero((char *)mtod(m_new, char *), m_new->m_len); 2280 2281 sc->dc_cdata.dc_rx_chain[i] = m_new; 2282 c->dc_data = vtophys(mtod(m_new, caddr_t)); 2283 c->dc_ctl = DC_RXCTL_RLINK | DC_RXLEN; 2284 c->dc_status = DC_RXSTAT_OWN; 2285 2286 return(0); 2287 } 2288 2289 /* 2290 * Grrrrr. 2291 * The PNIC chip has a terrible bug in it that manifests itself during 2292 * periods of heavy activity. The exact mode of failure if difficult to 2293 * pinpoint: sometimes it only happens in promiscuous mode, sometimes it 2294 * will happen on slow machines. The bug is that sometimes instead of 2295 * uploading one complete frame during reception, it uploads what looks 2296 * like the entire contents of its FIFO memory. The frame we want is at 2297 * the end of the whole mess, but we never know exactly how much data has 2298 * been uploaded, so salvaging the frame is hard. 2299 * 2300 * There is only one way to do it reliably, and it's disgusting. 2301 * Here's what we know: 2302 * 2303 * - We know there will always be somewhere between one and three extra 2304 * descriptors uploaded. 2305 * 2306 * - We know the desired received frame will always be at the end of the 2307 * total data upload. 2308 * 2309 * - We know the size of the desired received frame because it will be 2310 * provided in the length field of the status word in the last descriptor. 2311 * 2312 * Here's what we do: 2313 * 2314 * - When we allocate buffers for the receive ring, we bzero() them. 2315 * This means that we know that the buffer contents should be all 2316 * zeros, except for data uploaded by the chip. 2317 * 2318 * - We also force the PNIC chip to upload frames that include the 2319 * ethernet CRC at the end. 2320 * 2321 * - We gather all of the bogus frame data into a single buffer. 2322 * 2323 * - We then position a pointer at the end of this buffer and scan 2324 * backwards until we encounter the first non-zero byte of data. 2325 * This is the end of the received frame. We know we will encounter 2326 * some data at the end of the frame because the CRC will always be 2327 * there, so even if the sender transmits a packet of all zeros, 2328 * we won't be fooled. 2329 * 2330 * - We know the size of the actual received frame, so we subtract 2331 * that value from the current pointer location. This brings us 2332 * to the start of the actual received packet. 2333 * 2334 * - We copy this into an mbuf and pass it on, along with the actual 2335 * frame length. 2336 * 2337 * The performance hit is tremendous, but it beats dropping frames all 2338 * the time. 2339 */ 2340 2341 #define DC_WHOLEFRAME (DC_RXSTAT_FIRSTFRAG|DC_RXSTAT_LASTFRAG) 2342 static void dc_pnic_rx_bug_war(sc, idx) 2343 struct dc_softc *sc; 2344 int idx; 2345 { 2346 struct dc_desc *cur_rx; 2347 struct dc_desc *c = NULL; 2348 struct mbuf *m = NULL; 2349 unsigned char *ptr; 2350 int i, total_len; 2351 u_int32_t rxstat = 0; 2352 2353 i = sc->dc_pnic_rx_bug_save; 2354 cur_rx = &sc->dc_ldata->dc_rx_list[idx]; 2355 ptr = sc->dc_pnic_rx_buf; 2356 bzero(ptr, sizeof(DC_RXLEN * 5)); 2357 2358 /* Copy all the bytes from the bogus buffers. */ 2359 while (1) { 2360 c = &sc->dc_ldata->dc_rx_list[i]; 2361 rxstat = c->dc_status; 2362 m = sc->dc_cdata.dc_rx_chain[i]; 2363 bcopy(mtod(m, char *), ptr, DC_RXLEN); 2364 ptr += DC_RXLEN; 2365 /* If this is the last buffer, break out. */ 2366 if (i == idx || rxstat & DC_RXSTAT_LASTFRAG) 2367 break; 2368 dc_newbuf(sc, i, m); 2369 DC_INC(i, DC_RX_LIST_CNT); 2370 } 2371 2372 /* Find the length of the actual receive frame. */ 2373 total_len = DC_RXBYTES(rxstat); 2374 2375 /* Scan backwards until we hit a non-zero byte. */ 2376 while(*ptr == 0x00) 2377 ptr--; 2378 2379 /* Round off. */ 2380 if ((uintptr_t)(ptr) & 0x3) 2381 ptr -= 1; 2382 2383 /* Now find the start of the frame. */ 2384 ptr -= total_len; 2385 if (ptr < sc->dc_pnic_rx_buf) 2386 ptr = sc->dc_pnic_rx_buf; 2387 2388 /* 2389 * Now copy the salvaged frame to the last mbuf and fake up 2390 * the status word to make it look like a successful 2391 * frame reception. 2392 */ 2393 dc_newbuf(sc, i, m); 2394 bcopy(ptr, mtod(m, char *), total_len); 2395 cur_rx->dc_status = rxstat | DC_RXSTAT_FIRSTFRAG; 2396 2397 return; 2398 } 2399 2400 /* 2401 * This routine searches the RX ring for dirty descriptors in the 2402 * event that the rxeof routine falls out of sync with the chip's 2403 * current descriptor pointer. This may happen sometimes as a result 2404 * of a "no RX buffer available" condition that happens when the chip 2405 * consumes all of the RX buffers before the driver has a chance to 2406 * process the RX ring. This routine may need to be called more than 2407 * once to bring the driver back in sync with the chip, however we 2408 * should still be getting RX DONE interrupts to drive the search 2409 * for new packets in the RX ring, so we should catch up eventually. 2410 */ 2411 static int dc_rx_resync(sc) 2412 struct dc_softc *sc; 2413 { 2414 int i, pos; 2415 struct dc_desc *cur_rx; 2416 2417 pos = sc->dc_cdata.dc_rx_prod; 2418 2419 for (i = 0; i < DC_RX_LIST_CNT; i++) { 2420 cur_rx = &sc->dc_ldata->dc_rx_list[pos]; 2421 if (!(cur_rx->dc_status & DC_RXSTAT_OWN)) 2422 break; 2423 DC_INC(pos, DC_RX_LIST_CNT); 2424 } 2425 2426 /* If the ring really is empty, then just return. */ 2427 if (i == DC_RX_LIST_CNT) 2428 return(0); 2429 2430 /* We've fallen behing the chip: catch it. */ 2431 sc->dc_cdata.dc_rx_prod = pos; 2432 2433 return(EAGAIN); 2434 } 2435 2436 /* 2437 * A frame has been uploaded: pass the resulting mbuf chain up to 2438 * the higher level protocols. 2439 */ 2440 static void dc_rxeof(sc) 2441 struct dc_softc *sc; 2442 { 2443 struct ether_header *eh; 2444 struct mbuf *m; 2445 struct ifnet *ifp; 2446 struct dc_desc *cur_rx; 2447 int i, total_len = 0; 2448 u_int32_t rxstat; 2449 2450 ifp = &sc->arpcom.ac_if; 2451 i = sc->dc_cdata.dc_rx_prod; 2452 2453 while(!(sc->dc_ldata->dc_rx_list[i].dc_status & DC_RXSTAT_OWN)) { 2454 struct mbuf *m0 = NULL; 2455 2456 cur_rx = &sc->dc_ldata->dc_rx_list[i]; 2457 rxstat = cur_rx->dc_status; 2458 m = sc->dc_cdata.dc_rx_chain[i]; 2459 total_len = DC_RXBYTES(rxstat); 2460 2461 if (sc->dc_flags & DC_PNIC_RX_BUG_WAR) { 2462 if ((rxstat & DC_WHOLEFRAME) != DC_WHOLEFRAME) { 2463 if (rxstat & DC_RXSTAT_FIRSTFRAG) 2464 sc->dc_pnic_rx_bug_save = i; 2465 if ((rxstat & DC_RXSTAT_LASTFRAG) == 0) { 2466 DC_INC(i, DC_RX_LIST_CNT); 2467 continue; 2468 } 2469 dc_pnic_rx_bug_war(sc, i); 2470 rxstat = cur_rx->dc_status; 2471 total_len = DC_RXBYTES(rxstat); 2472 } 2473 } 2474 2475 sc->dc_cdata.dc_rx_chain[i] = NULL; 2476 2477 /* 2478 * If an error occurs, update stats, clear the 2479 * status word and leave the mbuf cluster in place: 2480 * it should simply get re-used next time this descriptor 2481 * comes up in the ring. 2482 */ 2483 if (rxstat & DC_RXSTAT_RXERR) { 2484 ifp->if_ierrors++; 2485 if (rxstat & DC_RXSTAT_COLLSEEN) 2486 ifp->if_collisions++; 2487 dc_newbuf(sc, i, m); 2488 if (rxstat & DC_RXSTAT_CRCERR) { 2489 DC_INC(i, DC_RX_LIST_CNT); 2490 continue; 2491 } else { 2492 dc_init(sc); 2493 return; 2494 } 2495 } 2496 2497 /* No errors; receive the packet. */ 2498 total_len -= ETHER_CRC_LEN; 2499 2500 m0 = m_devget(mtod(m, char *) - ETHER_ALIGN, 2501 total_len + ETHER_ALIGN, 0, ifp, NULL); 2502 dc_newbuf(sc, i, m); 2503 DC_INC(i, DC_RX_LIST_CNT); 2504 if (m0 == NULL) { 2505 ifp->if_ierrors++; 2506 continue; 2507 } 2508 m_adj(m0, ETHER_ALIGN); 2509 m = m0; 2510 2511 ifp->if_ipackets++; 2512 eh = mtod(m, struct ether_header *); 2513 2514 /* Remove header from mbuf and pass it on. */ 2515 m_adj(m, sizeof(struct ether_header)); 2516 ether_input(ifp, eh, m); 2517 } 2518 2519 sc->dc_cdata.dc_rx_prod = i; 2520 } 2521 2522 /* 2523 * A frame was downloaded to the chip. It's safe for us to clean up 2524 * the list buffers. 2525 */ 2526 2527 static void dc_txeof(sc) 2528 struct dc_softc *sc; 2529 { 2530 struct dc_desc *cur_tx = NULL; 2531 struct ifnet *ifp; 2532 int idx; 2533 2534 ifp = &sc->arpcom.ac_if; 2535 2536 /* Clear the timeout timer. */ 2537 ifp->if_timer = 0; 2538 2539 /* 2540 * Go through our tx list and free mbufs for those 2541 * frames that have been transmitted. 2542 */ 2543 idx = sc->dc_cdata.dc_tx_cons; 2544 while(idx != sc->dc_cdata.dc_tx_prod) { 2545 u_int32_t txstat; 2546 2547 cur_tx = &sc->dc_ldata->dc_tx_list[idx]; 2548 txstat = cur_tx->dc_status; 2549 2550 if (txstat & DC_TXSTAT_OWN) 2551 break; 2552 2553 if (!(cur_tx->dc_ctl & DC_TXCTL_LASTFRAG) || 2554 cur_tx->dc_ctl & DC_TXCTL_SETUP) { 2555 sc->dc_cdata.dc_tx_cnt--; 2556 if (cur_tx->dc_ctl & DC_TXCTL_SETUP) { 2557 /* 2558 * Yes, the PNIC is so brain damaged 2559 * that it will sometimes generate a TX 2560 * underrun error while DMAing the RX 2561 * filter setup frame. If we detect this, 2562 * we have to send the setup frame again, 2563 * or else the filter won't be programmed 2564 * correctly. 2565 */ 2566 if (DC_IS_PNIC(sc)) { 2567 if (txstat & DC_TXSTAT_ERRSUM) 2568 dc_setfilt(sc); 2569 } 2570 sc->dc_cdata.dc_tx_chain[idx] = NULL; 2571 } 2572 DC_INC(idx, DC_TX_LIST_CNT); 2573 continue; 2574 } 2575 2576 if (DC_IS_XIRCOM(sc)) { 2577 /* 2578 * XXX: Why does my Xircom taunt me so? 2579 * For some reason it likes setting the CARRLOST flag 2580 * even when the carrier is there. wtf?!? */ 2581 if (/*sc->dc_type == DC_TYPE_21143 &&*/ 2582 sc->dc_pmode == DC_PMODE_MII && 2583 ((txstat & 0xFFFF) & ~(DC_TXSTAT_ERRSUM| 2584 DC_TXSTAT_NOCARRIER))) 2585 txstat &= ~DC_TXSTAT_ERRSUM; 2586 } else { 2587 if (/*sc->dc_type == DC_TYPE_21143 &&*/ 2588 sc->dc_pmode == DC_PMODE_MII && 2589 ((txstat & 0xFFFF) & ~(DC_TXSTAT_ERRSUM| 2590 DC_TXSTAT_NOCARRIER|DC_TXSTAT_CARRLOST))) 2591 txstat &= ~DC_TXSTAT_ERRSUM; 2592 } 2593 2594 if (txstat & DC_TXSTAT_ERRSUM) { 2595 ifp->if_oerrors++; 2596 if (txstat & DC_TXSTAT_EXCESSCOLL) 2597 ifp->if_collisions++; 2598 if (txstat & DC_TXSTAT_LATECOLL) 2599 ifp->if_collisions++; 2600 if (!(txstat & DC_TXSTAT_UNDERRUN)) { 2601 dc_init(sc); 2602 return; 2603 } 2604 } 2605 2606 ifp->if_collisions += (txstat & DC_TXSTAT_COLLCNT) >> 3; 2607 2608 ifp->if_opackets++; 2609 if (sc->dc_cdata.dc_tx_chain[idx] != NULL) { 2610 m_freem(sc->dc_cdata.dc_tx_chain[idx]); 2611 sc->dc_cdata.dc_tx_chain[idx] = NULL; 2612 } 2613 2614 sc->dc_cdata.dc_tx_cnt--; 2615 DC_INC(idx, DC_TX_LIST_CNT); 2616 } 2617 2618 sc->dc_cdata.dc_tx_cons = idx; 2619 if (cur_tx != NULL) 2620 ifp->if_flags &= ~IFF_OACTIVE; 2621 2622 return; 2623 } 2624 2625 static void dc_tick(xsc) 2626 void *xsc; 2627 { 2628 struct dc_softc *sc; 2629 struct mii_data *mii; 2630 struct ifnet *ifp; 2631 u_int32_t r; 2632 2633 sc = xsc; 2634 DC_LOCK(sc); 2635 ifp = &sc->arpcom.ac_if; 2636 mii = device_get_softc(sc->dc_miibus); 2637 2638 if (sc->dc_flags & DC_REDUCED_MII_POLL) { 2639 if (sc->dc_flags & DC_21143_NWAY) { 2640 r = CSR_READ_4(sc, DC_10BTSTAT); 2641 if (IFM_SUBTYPE(mii->mii_media_active) == 2642 IFM_100_TX && (r & DC_TSTAT_LS100)) { 2643 sc->dc_link = 0; 2644 mii_mediachg(mii); 2645 } 2646 if (IFM_SUBTYPE(mii->mii_media_active) == 2647 IFM_10_T && (r & DC_TSTAT_LS10)) { 2648 sc->dc_link = 0; 2649 mii_mediachg(mii); 2650 } 2651 if (sc->dc_link == 0) 2652 mii_tick(mii); 2653 } else { 2654 r = CSR_READ_4(sc, DC_ISR); 2655 if ((r & DC_ISR_RX_STATE) == DC_RXSTATE_WAIT && 2656 sc->dc_cdata.dc_tx_cnt == 0) 2657 mii_tick(mii); 2658 if (!(mii->mii_media_status & IFM_ACTIVE)) 2659 sc->dc_link = 0; 2660 } 2661 } else 2662 mii_tick(mii); 2663 2664 /* 2665 * When the init routine completes, we expect to be able to send 2666 * packets right away, and in fact the network code will send a 2667 * gratuitous ARP the moment the init routine marks the interface 2668 * as running. However, even though the MAC may have been initialized, 2669 * there may be a delay of a few seconds before the PHY completes 2670 * autonegotiation and the link is brought up. Any transmissions 2671 * made during that delay will be lost. Dealing with this is tricky: 2672 * we can't just pause in the init routine while waiting for the 2673 * PHY to come ready since that would bring the whole system to 2674 * a screeching halt for several seconds. 2675 * 2676 * What we do here is prevent the TX start routine from sending 2677 * any packets until a link has been established. After the 2678 * interface has been initialized, the tick routine will poll 2679 * the state of the PHY until the IFM_ACTIVE flag is set. Until 2680 * that time, packets will stay in the send queue, and once the 2681 * link comes up, they will be flushed out to the wire. 2682 */ 2683 if (!sc->dc_link) { 2684 mii_pollstat(mii); 2685 if (mii->mii_media_status & IFM_ACTIVE && 2686 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) { 2687 sc->dc_link++; 2688 if (ifp->if_snd.ifq_head != NULL) 2689 dc_start(ifp); 2690 } 2691 } 2692 2693 if (sc->dc_flags & DC_21143_NWAY && !sc->dc_link) 2694 sc->dc_stat_ch = timeout(dc_tick, sc, hz/10); 2695 else 2696 sc->dc_stat_ch = timeout(dc_tick, sc, hz); 2697 2698 DC_UNLOCK(sc); 2699 2700 return; 2701 } 2702 2703 static void dc_intr(arg) 2704 void *arg; 2705 { 2706 struct dc_softc *sc; 2707 struct ifnet *ifp; 2708 u_int32_t status; 2709 2710 sc = arg; 2711 DC_LOCK(sc); 2712 ifp = &sc->arpcom.ac_if; 2713 2714 /* Supress unwanted interrupts */ 2715 if (!(ifp->if_flags & IFF_UP)) { 2716 if (CSR_READ_4(sc, DC_ISR) & DC_INTRS) 2717 dc_stop(sc); 2718 DC_UNLOCK(sc); 2719 return; 2720 } 2721 2722 /* Disable interrupts. */ 2723 CSR_WRITE_4(sc, DC_IMR, 0x00000000); 2724 2725 while(((status = CSR_READ_4(sc, DC_ISR)) & DC_INTRS) 2726 && status != 0xFFFFFFFF) { 2727 2728 CSR_WRITE_4(sc, DC_ISR, status); 2729 2730 if (status & DC_ISR_RX_OK) { 2731 int curpkts; 2732 curpkts = ifp->if_ipackets; 2733 dc_rxeof(sc); 2734 if (curpkts == ifp->if_ipackets) { 2735 while(dc_rx_resync(sc)) 2736 dc_rxeof(sc); 2737 } 2738 } 2739 2740 if (status & (DC_ISR_TX_OK|DC_ISR_TX_NOBUF)) 2741 dc_txeof(sc); 2742 2743 if (status & DC_ISR_TX_IDLE) { 2744 dc_txeof(sc); 2745 if (sc->dc_cdata.dc_tx_cnt) { 2746 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_TX_ON); 2747 CSR_WRITE_4(sc, DC_TXSTART, 0xFFFFFFFF); 2748 } 2749 } 2750 2751 if (status & DC_ISR_TX_UNDERRUN) { 2752 u_int32_t cfg; 2753 2754 printf("dc%d: TX underrun -- ", sc->dc_unit); 2755 if (DC_IS_DAVICOM(sc) || DC_IS_INTEL(sc)) 2756 dc_init(sc); 2757 cfg = CSR_READ_4(sc, DC_NETCFG); 2758 cfg &= ~DC_NETCFG_TX_THRESH; 2759 if (sc->dc_txthresh == DC_TXTHRESH_160BYTES) { 2760 printf("using store and forward mode\n"); 2761 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_STORENFWD); 2762 } else if (sc->dc_flags & DC_TX_STORENFWD) { 2763 printf("resetting\n"); 2764 } else { 2765 sc->dc_txthresh += 0x4000; 2766 printf("increasing TX threshold\n"); 2767 CSR_WRITE_4(sc, DC_NETCFG, cfg); 2768 DC_SETBIT(sc, DC_NETCFG, sc->dc_txthresh); 2769 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_STORENFWD); 2770 } 2771 } 2772 2773 if ((status & DC_ISR_RX_WATDOGTIMEO) 2774 || (status & DC_ISR_RX_NOBUF)) { 2775 int curpkts; 2776 curpkts = ifp->if_ipackets; 2777 dc_rxeof(sc); 2778 if (curpkts == ifp->if_ipackets) { 2779 while(dc_rx_resync(sc)) 2780 dc_rxeof(sc); 2781 } 2782 } 2783 2784 if (status & DC_ISR_BUS_ERR) { 2785 dc_reset(sc); 2786 dc_init(sc); 2787 } 2788 } 2789 2790 /* Re-enable interrupts. */ 2791 CSR_WRITE_4(sc, DC_IMR, DC_INTRS); 2792 2793 if (ifp->if_snd.ifq_head != NULL) 2794 dc_start(ifp); 2795 2796 DC_UNLOCK(sc); 2797 2798 return; 2799 } 2800 2801 /* 2802 * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data 2803 * pointers to the fragment pointers. 2804 */ 2805 static int dc_encap(sc, m_head, txidx) 2806 struct dc_softc *sc; 2807 struct mbuf *m_head; 2808 u_int32_t *txidx; 2809 { 2810 struct dc_desc *f = NULL; 2811 struct mbuf *m; 2812 int frag, cur, cnt = 0; 2813 2814 /* 2815 * Start packing the mbufs in this chain into 2816 * the fragment pointers. Stop when we run out 2817 * of fragments or hit the end of the mbuf chain. 2818 */ 2819 m = m_head; 2820 cur = frag = *txidx; 2821 2822 for (m = m_head; m != NULL; m = m->m_next) { 2823 if (m->m_len != 0) { 2824 if (sc->dc_flags & DC_TX_ADMTEK_WAR) { 2825 if (*txidx != sc->dc_cdata.dc_tx_prod && 2826 frag == (DC_TX_LIST_CNT - 1)) 2827 return(ENOBUFS); 2828 } 2829 if ((DC_TX_LIST_CNT - 2830 (sc->dc_cdata.dc_tx_cnt + cnt)) < 5) 2831 return(ENOBUFS); 2832 2833 f = &sc->dc_ldata->dc_tx_list[frag]; 2834 f->dc_ctl = DC_TXCTL_TLINK | m->m_len; 2835 if (cnt == 0) { 2836 f->dc_status = 0; 2837 f->dc_ctl |= DC_TXCTL_FIRSTFRAG; 2838 } else 2839 f->dc_status = DC_TXSTAT_OWN; 2840 f->dc_data = vtophys(mtod(m, vm_offset_t)); 2841 cur = frag; 2842 DC_INC(frag, DC_TX_LIST_CNT); 2843 cnt++; 2844 } 2845 } 2846 2847 if (m != NULL) 2848 return(ENOBUFS); 2849 2850 sc->dc_cdata.dc_tx_cnt += cnt; 2851 sc->dc_cdata.dc_tx_chain[cur] = m_head; 2852 sc->dc_ldata->dc_tx_list[cur].dc_ctl |= DC_TXCTL_LASTFRAG; 2853 if (sc->dc_flags & DC_TX_INTR_FIRSTFRAG) 2854 sc->dc_ldata->dc_tx_list[*txidx].dc_ctl |= DC_TXCTL_FINT; 2855 if (sc->dc_flags & DC_TX_INTR_ALWAYS) 2856 sc->dc_ldata->dc_tx_list[cur].dc_ctl |= DC_TXCTL_FINT; 2857 if (sc->dc_flags & DC_TX_USE_TX_INTR && sc->dc_cdata.dc_tx_cnt > 64) 2858 sc->dc_ldata->dc_tx_list[cur].dc_ctl |= DC_TXCTL_FINT; 2859 sc->dc_ldata->dc_tx_list[*txidx].dc_status = DC_TXSTAT_OWN; 2860 *txidx = frag; 2861 2862 return(0); 2863 } 2864 2865 /* 2866 * Coalesce an mbuf chain into a single mbuf cluster buffer. 2867 * Needed for some really badly behaved chips that just can't 2868 * do scatter/gather correctly. 2869 */ 2870 static int dc_coal(sc, m_head) 2871 struct dc_softc *sc; 2872 struct mbuf **m_head; 2873 { 2874 struct mbuf *m_new, *m; 2875 2876 m = *m_head; 2877 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 2878 if (m_new == NULL) { 2879 printf("dc%d: no memory for tx list", sc->dc_unit); 2880 return(ENOBUFS); 2881 } 2882 if (m->m_pkthdr.len > MHLEN) { 2883 MCLGET(m_new, M_DONTWAIT); 2884 if (!(m_new->m_flags & M_EXT)) { 2885 m_freem(m_new); 2886 printf("dc%d: no memory for tx list", sc->dc_unit); 2887 return(ENOBUFS); 2888 } 2889 } 2890 m_copydata(m, 0, m->m_pkthdr.len, mtod(m_new, caddr_t)); 2891 m_new->m_pkthdr.len = m_new->m_len = m->m_pkthdr.len; 2892 m_freem(m); 2893 *m_head = m_new; 2894 2895 return(0); 2896 } 2897 2898 /* 2899 * Main transmit routine. To avoid having to do mbuf copies, we put pointers 2900 * to the mbuf data regions directly in the transmit lists. We also save a 2901 * copy of the pointers since the transmit list fragment pointers are 2902 * physical addresses. 2903 */ 2904 2905 static void dc_start(ifp) 2906 struct ifnet *ifp; 2907 { 2908 struct dc_softc *sc; 2909 struct mbuf *m_head = NULL; 2910 int idx; 2911 2912 sc = ifp->if_softc; 2913 2914 DC_LOCK(sc); 2915 2916 if (!sc->dc_link) { 2917 DC_UNLOCK(sc); 2918 return; 2919 } 2920 2921 if (ifp->if_flags & IFF_OACTIVE) { 2922 DC_UNLOCK(sc); 2923 return; 2924 } 2925 2926 idx = sc->dc_cdata.dc_tx_prod; 2927 2928 while(sc->dc_cdata.dc_tx_chain[idx] == NULL) { 2929 IF_DEQUEUE(&ifp->if_snd, m_head); 2930 if (m_head == NULL) 2931 break; 2932 2933 if (sc->dc_flags & DC_TX_COALESCE) { 2934 if (dc_coal(sc, &m_head)) { 2935 IF_PREPEND(&ifp->if_snd, m_head); 2936 ifp->if_flags |= IFF_OACTIVE; 2937 break; 2938 } 2939 } 2940 2941 if (dc_encap(sc, m_head, &idx)) { 2942 IF_PREPEND(&ifp->if_snd, m_head); 2943 ifp->if_flags |= IFF_OACTIVE; 2944 break; 2945 } 2946 2947 /* 2948 * If there's a BPF listener, bounce a copy of this frame 2949 * to him. 2950 */ 2951 if (ifp->if_bpf) 2952 bpf_mtap(ifp, m_head); 2953 2954 if (sc->dc_flags & DC_TX_ONE) { 2955 ifp->if_flags |= IFF_OACTIVE; 2956 break; 2957 } 2958 } 2959 2960 /* Transmit */ 2961 sc->dc_cdata.dc_tx_prod = idx; 2962 if (!(sc->dc_flags & DC_TX_POLL)) 2963 CSR_WRITE_4(sc, DC_TXSTART, 0xFFFFFFFF); 2964 2965 /* 2966 * Set a timeout in case the chip goes out to lunch. 2967 */ 2968 ifp->if_timer = 5; 2969 2970 DC_UNLOCK(sc); 2971 2972 return; 2973 } 2974 2975 static void dc_init(xsc) 2976 void *xsc; 2977 { 2978 struct dc_softc *sc = xsc; 2979 struct ifnet *ifp = &sc->arpcom.ac_if; 2980 struct mii_data *mii; 2981 2982 DC_LOCK(sc); 2983 2984 mii = device_get_softc(sc->dc_miibus); 2985 2986 /* 2987 * Cancel pending I/O and free all RX/TX buffers. 2988 */ 2989 dc_stop(sc); 2990 dc_reset(sc); 2991 2992 /* 2993 * Set cache alignment and burst length. 2994 */ 2995 if (DC_IS_ASIX(sc) || DC_IS_DAVICOM(sc)) 2996 CSR_WRITE_4(sc, DC_BUSCTL, 0); 2997 else 2998 CSR_WRITE_4(sc, DC_BUSCTL, DC_BUSCTL_MRME|DC_BUSCTL_MRLE); 2999 if (DC_IS_DAVICOM(sc) || DC_IS_INTEL(sc)) { 3000 DC_SETBIT(sc, DC_BUSCTL, DC_BURSTLEN_USECA); 3001 } else { 3002 DC_SETBIT(sc, DC_BUSCTL, DC_BURSTLEN_16LONG); 3003 } 3004 if (sc->dc_flags & DC_TX_POLL) 3005 DC_SETBIT(sc, DC_BUSCTL, DC_TXPOLL_1); 3006 switch(sc->dc_cachesize) { 3007 case 32: 3008 DC_SETBIT(sc, DC_BUSCTL, DC_CACHEALIGN_32LONG); 3009 break; 3010 case 16: 3011 DC_SETBIT(sc, DC_BUSCTL, DC_CACHEALIGN_16LONG); 3012 break; 3013 case 8: 3014 DC_SETBIT(sc, DC_BUSCTL, DC_CACHEALIGN_8LONG); 3015 break; 3016 case 0: 3017 default: 3018 DC_SETBIT(sc, DC_BUSCTL, DC_CACHEALIGN_NONE); 3019 break; 3020 } 3021 3022 if (sc->dc_flags & DC_TX_STORENFWD) 3023 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_STORENFWD); 3024 else { 3025 if (sc->dc_txthresh == DC_TXTHRESH_160BYTES) { 3026 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_STORENFWD); 3027 } else { 3028 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_STORENFWD); 3029 DC_SETBIT(sc, DC_NETCFG, sc->dc_txthresh); 3030 } 3031 } 3032 3033 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_NO_RXCRC); 3034 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_TX_BACKOFF); 3035 3036 if (DC_IS_MACRONIX(sc) || DC_IS_PNICII(sc)) { 3037 /* 3038 * The app notes for the 98713 and 98715A say that 3039 * in order to have the chips operate properly, a magic 3040 * number must be written to CSR16. Macronix does not 3041 * document the meaning of these bits so there's no way 3042 * to know exactly what they do. The 98713 has a magic 3043 * number all its own; the rest all use a different one. 3044 */ 3045 DC_CLRBIT(sc, DC_MX_MAGICPACKET, 0xFFFF0000); 3046 if (sc->dc_type == DC_TYPE_98713) 3047 DC_SETBIT(sc, DC_MX_MAGICPACKET, DC_MX_MAGIC_98713); 3048 else 3049 DC_SETBIT(sc, DC_MX_MAGICPACKET, DC_MX_MAGIC_98715); 3050 } 3051 3052 if (DC_IS_XIRCOM(sc)) { 3053 /* 3054 * setup General Purpose Port mode and data so the tulip 3055 * can talk to the MII. 3056 */ 3057 CSR_WRITE_4(sc, DC_SIAGP, DC_SIAGP_WRITE_EN | DC_SIAGP_INT1_EN | 3058 DC_SIAGP_MD_GP2_OUTPUT | DC_SIAGP_MD_GP0_OUTPUT); 3059 DELAY(10); 3060 CSR_WRITE_4(sc, DC_SIAGP, DC_SIAGP_INT1_EN | 3061 DC_SIAGP_MD_GP2_OUTPUT | DC_SIAGP_MD_GP0_OUTPUT); 3062 DELAY(10); 3063 } 3064 3065 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_TX_THRESH); 3066 DC_SETBIT(sc, DC_NETCFG, DC_TXTHRESH_72BYTES); 3067 3068 /* Init circular RX list. */ 3069 if (dc_list_rx_init(sc) == ENOBUFS) { 3070 printf("dc%d: initialization failed: no " 3071 "memory for rx buffers\n", sc->dc_unit); 3072 dc_stop(sc); 3073 DC_UNLOCK(sc); 3074 return; 3075 } 3076 3077 /* 3078 * Init tx descriptors. 3079 */ 3080 dc_list_tx_init(sc); 3081 3082 /* 3083 * Load the address of the RX list. 3084 */ 3085 CSR_WRITE_4(sc, DC_RXADDR, vtophys(&sc->dc_ldata->dc_rx_list[0])); 3086 CSR_WRITE_4(sc, DC_TXADDR, vtophys(&sc->dc_ldata->dc_tx_list[0])); 3087 3088 /* 3089 * Enable interrupts. 3090 */ 3091 CSR_WRITE_4(sc, DC_IMR, DC_INTRS); 3092 CSR_WRITE_4(sc, DC_ISR, 0xFFFFFFFF); 3093 3094 /* Enable transmitter. */ 3095 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_TX_ON); 3096 3097 /* 3098 * If this is an Intel 21143 and we're not using the 3099 * MII port, program the LED control pins so we get 3100 * link and activity indications. 3101 */ 3102 if (sc->dc_flags & DC_TULIP_LEDS) { 3103 CSR_WRITE_4(sc, DC_WATCHDOG, 3104 DC_WDOG_CTLWREN|DC_WDOG_LINK|DC_WDOG_ACTIVITY); 3105 CSR_WRITE_4(sc, DC_WATCHDOG, 0); 3106 } 3107 3108 /* 3109 * Load the RX/multicast filter. We do this sort of late 3110 * because the filter programming scheme on the 21143 and 3111 * some clones requires DMAing a setup frame via the TX 3112 * engine, and we need the transmitter enabled for that. 3113 */ 3114 dc_setfilt(sc); 3115 3116 /* Enable receiver. */ 3117 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_ON); 3118 CSR_WRITE_4(sc, DC_RXSTART, 0xFFFFFFFF); 3119 3120 mii_mediachg(mii); 3121 dc_setcfg(sc, sc->dc_if_media); 3122 3123 ifp->if_flags |= IFF_RUNNING; 3124 ifp->if_flags &= ~IFF_OACTIVE; 3125 3126 /* Don't start the ticker if this is a homePNA link. */ 3127 if (IFM_SUBTYPE(mii->mii_media.ifm_media) == IFM_homePNA) 3128 sc->dc_link = 1; 3129 else { 3130 if (sc->dc_flags & DC_21143_NWAY) 3131 sc->dc_stat_ch = timeout(dc_tick, sc, hz/10); 3132 else 3133 sc->dc_stat_ch = timeout(dc_tick, sc, hz); 3134 } 3135 3136 #ifdef SRM_MEDIA 3137 if(sc->dc_srm_media) { 3138 struct ifreq ifr; 3139 3140 ifr.ifr_media = sc->dc_srm_media; 3141 ifmedia_ioctl(ifp, &ifr, &mii->mii_media, SIOCSIFMEDIA); 3142 sc->dc_srm_media = 0; 3143 } 3144 #endif 3145 DC_UNLOCK(sc); 3146 return; 3147 } 3148 3149 /* 3150 * Set media options. 3151 */ 3152 static int dc_ifmedia_upd(ifp) 3153 struct ifnet *ifp; 3154 { 3155 struct dc_softc *sc; 3156 struct mii_data *mii; 3157 struct ifmedia *ifm; 3158 3159 sc = ifp->if_softc; 3160 mii = device_get_softc(sc->dc_miibus); 3161 mii_mediachg(mii); 3162 ifm = &mii->mii_media; 3163 3164 if (DC_IS_DAVICOM(sc) && 3165 IFM_SUBTYPE(ifm->ifm_media) == IFM_homePNA) 3166 dc_setcfg(sc, ifm->ifm_media); 3167 else 3168 sc->dc_link = 0; 3169 3170 return(0); 3171 } 3172 3173 /* 3174 * Report current media status. 3175 */ 3176 static void dc_ifmedia_sts(ifp, ifmr) 3177 struct ifnet *ifp; 3178 struct ifmediareq *ifmr; 3179 { 3180 struct dc_softc *sc; 3181 struct mii_data *mii; 3182 struct ifmedia *ifm; 3183 3184 sc = ifp->if_softc; 3185 mii = device_get_softc(sc->dc_miibus); 3186 mii_pollstat(mii); 3187 ifm = &mii->mii_media; 3188 if (DC_IS_DAVICOM(sc)) { 3189 if (IFM_SUBTYPE(ifm->ifm_media) == IFM_homePNA) { 3190 ifmr->ifm_active = ifm->ifm_media; 3191 ifmr->ifm_status = 0; 3192 return; 3193 } 3194 } 3195 ifmr->ifm_active = mii->mii_media_active; 3196 ifmr->ifm_status = mii->mii_media_status; 3197 3198 return; 3199 } 3200 3201 static int dc_ioctl(ifp, command, data) 3202 struct ifnet *ifp; 3203 u_long command; 3204 caddr_t data; 3205 { 3206 struct dc_softc *sc = ifp->if_softc; 3207 struct ifreq *ifr = (struct ifreq *) data; 3208 struct mii_data *mii; 3209 int error = 0; 3210 3211 DC_LOCK(sc); 3212 3213 switch(command) { 3214 case SIOCSIFADDR: 3215 case SIOCGIFADDR: 3216 case SIOCSIFMTU: 3217 error = ether_ioctl(ifp, command, data); 3218 break; 3219 case SIOCSIFFLAGS: 3220 if (ifp->if_flags & IFF_UP) { 3221 if (ifp->if_flags & IFF_RUNNING && 3222 ifp->if_flags & IFF_PROMISC && 3223 !(sc->dc_if_flags & IFF_PROMISC)) { 3224 dc_setfilt(sc); 3225 } else if (ifp->if_flags & IFF_RUNNING && 3226 !(ifp->if_flags & IFF_PROMISC) && 3227 sc->dc_if_flags & IFF_PROMISC) { 3228 dc_setfilt(sc); 3229 } else if (!(ifp->if_flags & IFF_RUNNING)) { 3230 sc->dc_txthresh = 0; 3231 dc_init(sc); 3232 } 3233 } else { 3234 if (ifp->if_flags & IFF_RUNNING) 3235 dc_stop(sc); 3236 } 3237 sc->dc_if_flags = ifp->if_flags; 3238 error = 0; 3239 break; 3240 case SIOCADDMULTI: 3241 case SIOCDELMULTI: 3242 dc_setfilt(sc); 3243 error = 0; 3244 break; 3245 case SIOCGIFMEDIA: 3246 case SIOCSIFMEDIA: 3247 mii = device_get_softc(sc->dc_miibus); 3248 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 3249 #ifdef SRM_MEDIA 3250 if (sc->dc_srm_media) 3251 sc->dc_srm_media = 0; 3252 #endif 3253 break; 3254 default: 3255 error = EINVAL; 3256 break; 3257 } 3258 3259 DC_UNLOCK(sc); 3260 3261 return(error); 3262 } 3263 3264 static void dc_watchdog(ifp) 3265 struct ifnet *ifp; 3266 { 3267 struct dc_softc *sc; 3268 3269 sc = ifp->if_softc; 3270 3271 DC_LOCK(sc); 3272 3273 ifp->if_oerrors++; 3274 printf("dc%d: watchdog timeout\n", sc->dc_unit); 3275 3276 dc_stop(sc); 3277 dc_reset(sc); 3278 dc_init(sc); 3279 3280 if (ifp->if_snd.ifq_head != NULL) 3281 dc_start(ifp); 3282 3283 DC_UNLOCK(sc); 3284 3285 return; 3286 } 3287 3288 /* 3289 * Stop the adapter and free any mbufs allocated to the 3290 * RX and TX lists. 3291 */ 3292 static void dc_stop(sc) 3293 struct dc_softc *sc; 3294 { 3295 register int i; 3296 struct ifnet *ifp; 3297 3298 DC_LOCK(sc); 3299 3300 ifp = &sc->arpcom.ac_if; 3301 ifp->if_timer = 0; 3302 3303 untimeout(dc_tick, sc, sc->dc_stat_ch); 3304 3305 DC_CLRBIT(sc, DC_NETCFG, (DC_NETCFG_RX_ON|DC_NETCFG_TX_ON)); 3306 CSR_WRITE_4(sc, DC_IMR, 0x00000000); 3307 CSR_WRITE_4(sc, DC_TXADDR, 0x00000000); 3308 CSR_WRITE_4(sc, DC_RXADDR, 0x00000000); 3309 sc->dc_link = 0; 3310 3311 /* 3312 * Free data in the RX lists. 3313 */ 3314 for (i = 0; i < DC_RX_LIST_CNT; i++) { 3315 if (sc->dc_cdata.dc_rx_chain[i] != NULL) { 3316 m_freem(sc->dc_cdata.dc_rx_chain[i]); 3317 sc->dc_cdata.dc_rx_chain[i] = NULL; 3318 } 3319 } 3320 bzero((char *)&sc->dc_ldata->dc_rx_list, 3321 sizeof(sc->dc_ldata->dc_rx_list)); 3322 3323 /* 3324 * Free the TX list buffers. 3325 */ 3326 for (i = 0; i < DC_TX_LIST_CNT; i++) { 3327 if (sc->dc_cdata.dc_tx_chain[i] != NULL) { 3328 if (sc->dc_ldata->dc_tx_list[i].dc_ctl & 3329 DC_TXCTL_SETUP) { 3330 sc->dc_cdata.dc_tx_chain[i] = NULL; 3331 continue; 3332 } 3333 m_freem(sc->dc_cdata.dc_tx_chain[i]); 3334 sc->dc_cdata.dc_tx_chain[i] = NULL; 3335 } 3336 } 3337 3338 bzero((char *)&sc->dc_ldata->dc_tx_list, 3339 sizeof(sc->dc_ldata->dc_tx_list)); 3340 3341 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 3342 3343 DC_UNLOCK(sc); 3344 3345 return; 3346 } 3347 3348 /* 3349 * Stop all chip I/O so that the kernel's probe routines don't 3350 * get confused by errant DMAs when rebooting. 3351 */ 3352 static void dc_shutdown(dev) 3353 device_t dev; 3354 { 3355 struct dc_softc *sc; 3356 3357 sc = device_get_softc(dev); 3358 3359 dc_stop(sc); 3360 3361 return; 3362 } 3363