1 /*- 2 * Copyright (c) 1997, 1998, 1999 3 * Bill Paul <wpaul@ee.columbia.edu>. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 3. All advertising materials mentioning features or use of this software 14 * must display the following acknowledgement: 15 * This product includes software developed by Bill Paul. 16 * 4. Neither the name of the author nor the names of any co-contributors 17 * may be used to endorse or promote products derived from this software 18 * without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30 * THE POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33 #include <sys/cdefs.h> 34 __FBSDID("$FreeBSD$"); 35 36 /* 37 * DEC "tulip" clone ethernet driver. Supports the DEC/Intel 21143 38 * series chips and several workalikes including the following: 39 * 40 * Macronix 98713/98715/98725/98727/98732 PMAC (www.macronix.com) 41 * Macronix/Lite-On 82c115 PNIC II (www.macronix.com) 42 * Lite-On 82c168/82c169 PNIC (www.litecom.com) 43 * ASIX Electronics AX88140A (www.asix.com.tw) 44 * ASIX Electronics AX88141 (www.asix.com.tw) 45 * ADMtek AL981 (www.admtek.com.tw) 46 * ADMtek AN985 (www.admtek.com.tw) 47 * Netgear FA511 (www.netgear.com) Appears to be rebadged ADMTek AN985 48 * Davicom DM9100, DM9102, DM9102A (www.davicom8.com) 49 * Accton EN1217 (www.accton.com) 50 * Xircom X3201 (www.xircom.com) 51 * Abocom FE2500 52 * Conexant LANfinity (www.conexant.com) 53 * 3Com OfficeConnect 10/100B 3CSOHO100B (www.3com.com) 54 * 55 * Datasheets for the 21143 are available at developer.intel.com. 56 * Datasheets for the clone parts can be found at their respective sites. 57 * (Except for the PNIC; see www.freebsd.org/~wpaul/PNIC/pnic.ps.gz.) 58 * The PNIC II is essentially a Macronix 98715A chip; the only difference 59 * worth noting is that its multicast hash table is only 128 bits wide 60 * instead of 512. 61 * 62 * Written by Bill Paul <wpaul@ee.columbia.edu> 63 * Electrical Engineering Department 64 * Columbia University, New York City 65 */ 66 /* 67 * The Intel 21143 is the successor to the DEC 21140. It is basically 68 * the same as the 21140 but with a few new features. The 21143 supports 69 * three kinds of media attachments: 70 * 71 * o MII port, for 10Mbps and 100Mbps support and NWAY 72 * autonegotiation provided by an external PHY. 73 * o SYM port, for symbol mode 100Mbps support. 74 * o 10baseT port. 75 * o AUI/BNC port. 76 * 77 * The 100Mbps SYM port and 10baseT port can be used together in 78 * combination with the internal NWAY support to create a 10/100 79 * autosensing configuration. 80 * 81 * Note that not all tulip workalikes are handled in this driver: we only 82 * deal with those which are relatively well behaved. The Winbond is 83 * handled separately due to its different register offsets and the 84 * special handling needed for its various bugs. The PNIC is handled 85 * here, but I'm not thrilled about it. 86 * 87 * All of the workalike chips use some form of MII transceiver support 88 * with the exception of the Macronix chips, which also have a SYM port. 89 * The ASIX AX88140A is also documented to have a SYM port, but all 90 * the cards I've seen use an MII transceiver, probably because the 91 * AX88140A doesn't support internal NWAY. 92 */ 93 94 #ifdef HAVE_KERNEL_OPTION_HEADERS 95 #include "opt_device_polling.h" 96 #endif 97 98 #include <sys/param.h> 99 #include <sys/endian.h> 100 #include <sys/systm.h> 101 #include <sys/sockio.h> 102 #include <sys/mbuf.h> 103 #include <sys/malloc.h> 104 #include <sys/kernel.h> 105 #include <sys/module.h> 106 #include <sys/socket.h> 107 #include <sys/sysctl.h> 108 109 #include <net/if.h> 110 #include <net/if_arp.h> 111 #include <net/ethernet.h> 112 #include <net/if_dl.h> 113 #include <net/if_media.h> 114 #include <net/if_types.h> 115 #include <net/if_vlan_var.h> 116 117 #include <net/bpf.h> 118 119 #include <machine/bus.h> 120 #include <machine/resource.h> 121 #include <sys/bus.h> 122 #include <sys/rman.h> 123 124 #include <dev/mii/mii.h> 125 #include <dev/mii/miivar.h> 126 127 #include <dev/pci/pcireg.h> 128 #include <dev/pci/pcivar.h> 129 130 #define DC_USEIOSPACE 131 #ifdef __alpha__ 132 #define SRM_MEDIA 133 #endif 134 135 #include <dev/dc/if_dcreg.h> 136 137 #ifdef __sparc64__ 138 #include <dev/ofw/openfirm.h> 139 #include <machine/ofw_machdep.h> 140 #endif 141 142 MODULE_DEPEND(dc, pci, 1, 1, 1); 143 MODULE_DEPEND(dc, ether, 1, 1, 1); 144 MODULE_DEPEND(dc, miibus, 1, 1, 1); 145 146 /* 147 * "device miibus" is required in kernel config. See GENERIC if you get 148 * errors here. 149 */ 150 #include "miibus_if.h" 151 152 /* 153 * Various supported device vendors/types and their names. 154 */ 155 static struct dc_type dc_devs[] = { 156 { DC_VENDORID_DEC, DC_DEVICEID_21143, 157 "Intel 21143 10/100BaseTX" }, 158 { DC_VENDORID_DAVICOM, DC_DEVICEID_DM9009, 159 "Davicom DM9009 10/100BaseTX" }, 160 { DC_VENDORID_DAVICOM, DC_DEVICEID_DM9100, 161 "Davicom DM9100 10/100BaseTX" }, 162 { DC_VENDORID_DAVICOM, DC_DEVICEID_DM9102, 163 "Davicom DM9102 10/100BaseTX" }, 164 { DC_VENDORID_DAVICOM, DC_DEVICEID_DM9102, 165 "Davicom DM9102A 10/100BaseTX" }, 166 { DC_VENDORID_ADMTEK, DC_DEVICEID_AL981, 167 "ADMtek AL981 10/100BaseTX" }, 168 { DC_VENDORID_ADMTEK, DC_DEVICEID_AN985, 169 "ADMtek AN985 10/100BaseTX" }, 170 { DC_VENDORID_ADMTEK, DC_DEVICEID_ADM9511, 171 "ADMtek ADM9511 10/100BaseTX" }, 172 { DC_VENDORID_ADMTEK, DC_DEVICEID_ADM9513, 173 "ADMtek ADM9513 10/100BaseTX" }, 174 { DC_VENDORID_ADMTEK, DC_DEVICEID_FA511, 175 "Netgear FA511 10/100BaseTX" }, 176 { DC_VENDORID_ASIX, DC_DEVICEID_AX88140A, 177 "ASIX AX88140A 10/100BaseTX" }, 178 { DC_VENDORID_ASIX, DC_DEVICEID_AX88140A, 179 "ASIX AX88141 10/100BaseTX" }, 180 { DC_VENDORID_MX, DC_DEVICEID_98713, 181 "Macronix 98713 10/100BaseTX" }, 182 { DC_VENDORID_MX, DC_DEVICEID_98713, 183 "Macronix 98713A 10/100BaseTX" }, 184 { DC_VENDORID_CP, DC_DEVICEID_98713_CP, 185 "Compex RL100-TX 10/100BaseTX" }, 186 { DC_VENDORID_CP, DC_DEVICEID_98713_CP, 187 "Compex RL100-TX 10/100BaseTX" }, 188 { DC_VENDORID_MX, DC_DEVICEID_987x5, 189 "Macronix 98715/98715A 10/100BaseTX" }, 190 { DC_VENDORID_MX, DC_DEVICEID_987x5, 191 "Macronix 98715AEC-C 10/100BaseTX" }, 192 { DC_VENDORID_MX, DC_DEVICEID_987x5, 193 "Macronix 98725 10/100BaseTX" }, 194 { DC_VENDORID_MX, DC_DEVICEID_98727, 195 "Macronix 98727/98732 10/100BaseTX" }, 196 { DC_VENDORID_LO, DC_DEVICEID_82C115, 197 "LC82C115 PNIC II 10/100BaseTX" }, 198 { DC_VENDORID_LO, DC_DEVICEID_82C168, 199 "82c168 PNIC 10/100BaseTX" }, 200 { DC_VENDORID_LO, DC_DEVICEID_82C168, 201 "82c169 PNIC 10/100BaseTX" }, 202 { DC_VENDORID_ACCTON, DC_DEVICEID_EN1217, 203 "Accton EN1217 10/100BaseTX" }, 204 { DC_VENDORID_ACCTON, DC_DEVICEID_EN2242, 205 "Accton EN2242 MiniPCI 10/100BaseTX" }, 206 { DC_VENDORID_XIRCOM, DC_DEVICEID_X3201, 207 "Xircom X3201 10/100BaseTX" }, 208 { DC_VENDORID_ABOCOM, DC_DEVICEID_FE2500, 209 "Abocom FE2500 10/100BaseTX" }, 210 { DC_VENDORID_ABOCOM, DC_DEVICEID_FE2500MX, 211 "Abocom FE2500MX 10/100BaseTX" }, 212 { DC_VENDORID_CONEXANT, DC_DEVICEID_RS7112, 213 "Conexant LANfinity MiniPCI 10/100BaseTX" }, 214 { DC_VENDORID_HAWKING, DC_DEVICEID_HAWKING_PN672TX, 215 "Hawking CB102 CardBus 10/100" }, 216 { DC_VENDORID_PLANEX, DC_DEVICEID_FNW3602T, 217 "PlaneX FNW-3602-T CardBus 10/100" }, 218 { DC_VENDORID_3COM, DC_DEVICEID_3CSOHOB, 219 "3Com OfficeConnect 10/100B" }, 220 { DC_VENDORID_MICROSOFT, DC_DEVICEID_MSMN120, 221 "Microsoft MN-120 CardBus 10/100" }, 222 { DC_VENDORID_MICROSOFT, DC_DEVICEID_MSMN130, 223 "Microsoft MN-130 10/100" }, 224 { DC_VENDORID_MICROSOFT, DC_DEVICEID_MSMN130_FAKE, 225 "Microsoft MN-130 10/100" }, 226 { 0, 0, NULL } 227 }; 228 229 static int dc_probe(device_t); 230 static int dc_attach(device_t); 231 static int dc_detach(device_t); 232 static int dc_suspend(device_t); 233 static int dc_resume(device_t); 234 static struct dc_type *dc_devtype(device_t); 235 static int dc_newbuf(struct dc_softc *, int, int); 236 static int dc_encap(struct dc_softc *, struct mbuf **); 237 static void dc_pnic_rx_bug_war(struct dc_softc *, int); 238 static int dc_rx_resync(struct dc_softc *); 239 static void dc_rxeof(struct dc_softc *); 240 static void dc_txeof(struct dc_softc *); 241 static void dc_tick(void *); 242 static void dc_tx_underrun(struct dc_softc *); 243 static void dc_intr(void *); 244 static void dc_start(struct ifnet *); 245 static void dc_start_locked(struct ifnet *); 246 static int dc_ioctl(struct ifnet *, u_long, caddr_t); 247 static void dc_init(void *); 248 static void dc_init_locked(struct dc_softc *); 249 static void dc_stop(struct dc_softc *); 250 static void dc_watchdog(struct ifnet *); 251 static void dc_shutdown(device_t); 252 static int dc_ifmedia_upd(struct ifnet *); 253 static void dc_ifmedia_sts(struct ifnet *, struct ifmediareq *); 254 255 static void dc_delay(struct dc_softc *); 256 static void dc_eeprom_idle(struct dc_softc *); 257 static void dc_eeprom_putbyte(struct dc_softc *, int); 258 static void dc_eeprom_getword(struct dc_softc *, int, u_int16_t *); 259 static void dc_eeprom_getword_pnic(struct dc_softc *, int, u_int16_t *); 260 static void dc_eeprom_getword_xircom(struct dc_softc *, int, u_int16_t *); 261 static void dc_eeprom_width(struct dc_softc *); 262 static void dc_read_eeprom(struct dc_softc *, caddr_t, int, int, int); 263 264 static void dc_mii_writebit(struct dc_softc *, int); 265 static int dc_mii_readbit(struct dc_softc *); 266 static void dc_mii_sync(struct dc_softc *); 267 static void dc_mii_send(struct dc_softc *, u_int32_t, int); 268 static int dc_mii_readreg(struct dc_softc *, struct dc_mii_frame *); 269 static int dc_mii_writereg(struct dc_softc *, struct dc_mii_frame *); 270 static int dc_miibus_readreg(device_t, int, int); 271 static int dc_miibus_writereg(device_t, int, int, int); 272 static void dc_miibus_statchg(device_t); 273 static void dc_miibus_mediainit(device_t); 274 275 static void dc_setcfg(struct dc_softc *, int); 276 static uint32_t dc_mchash_le(struct dc_softc *, const uint8_t *); 277 static uint32_t dc_mchash_be(const uint8_t *); 278 static void dc_setfilt_21143(struct dc_softc *); 279 static void dc_setfilt_asix(struct dc_softc *); 280 static void dc_setfilt_admtek(struct dc_softc *); 281 static void dc_setfilt_xircom(struct dc_softc *); 282 283 static void dc_setfilt(struct dc_softc *); 284 285 static void dc_reset(struct dc_softc *); 286 static int dc_list_rx_init(struct dc_softc *); 287 static int dc_list_tx_init(struct dc_softc *); 288 289 static void dc_read_srom(struct dc_softc *, int); 290 static void dc_parse_21143_srom(struct dc_softc *); 291 static void dc_decode_leaf_sia(struct dc_softc *, struct dc_eblock_sia *); 292 static void dc_decode_leaf_mii(struct dc_softc *, struct dc_eblock_mii *); 293 static void dc_decode_leaf_sym(struct dc_softc *, struct dc_eblock_sym *); 294 static void dc_apply_fixup(struct dc_softc *, int); 295 296 static void dc_dma_map_txbuf(void *, bus_dma_segment_t *, int, bus_size_t, int); 297 static void dc_dma_map_rxbuf(void *, bus_dma_segment_t *, int, bus_size_t, int); 298 299 #ifdef DC_USEIOSPACE 300 #define DC_RES SYS_RES_IOPORT 301 #define DC_RID DC_PCI_CFBIO 302 #else 303 #define DC_RES SYS_RES_MEMORY 304 #define DC_RID DC_PCI_CFBMA 305 #endif 306 307 static device_method_t dc_methods[] = { 308 /* Device interface */ 309 DEVMETHOD(device_probe, dc_probe), 310 DEVMETHOD(device_attach, dc_attach), 311 DEVMETHOD(device_detach, dc_detach), 312 DEVMETHOD(device_suspend, dc_suspend), 313 DEVMETHOD(device_resume, dc_resume), 314 DEVMETHOD(device_shutdown, dc_shutdown), 315 316 /* bus interface */ 317 DEVMETHOD(bus_print_child, bus_generic_print_child), 318 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 319 320 /* MII interface */ 321 DEVMETHOD(miibus_readreg, dc_miibus_readreg), 322 DEVMETHOD(miibus_writereg, dc_miibus_writereg), 323 DEVMETHOD(miibus_statchg, dc_miibus_statchg), 324 DEVMETHOD(miibus_mediainit, dc_miibus_mediainit), 325 326 { 0, 0 } 327 }; 328 329 static driver_t dc_driver = { 330 "dc", 331 dc_methods, 332 sizeof(struct dc_softc) 333 }; 334 335 static devclass_t dc_devclass; 336 #ifdef __i386__ 337 static int dc_quick = 1; 338 SYSCTL_INT(_hw, OID_AUTO, dc_quick, CTLFLAG_RW, &dc_quick, 0, 339 "do not m_devget() in dc driver"); 340 #endif 341 342 DRIVER_MODULE(dc, cardbus, dc_driver, dc_devclass, 0, 0); 343 DRIVER_MODULE(dc, pci, dc_driver, dc_devclass, 0, 0); 344 DRIVER_MODULE(miibus, dc, miibus_driver, miibus_devclass, 0, 0); 345 346 #define DC_SETBIT(sc, reg, x) \ 347 CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) | (x)) 348 349 #define DC_CLRBIT(sc, reg, x) \ 350 CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) & ~(x)) 351 352 #define SIO_SET(x) DC_SETBIT(sc, DC_SIO, (x)) 353 #define SIO_CLR(x) DC_CLRBIT(sc, DC_SIO, (x)) 354 355 static void 356 dc_delay(struct dc_softc *sc) 357 { 358 int idx; 359 360 for (idx = (300 / 33) + 1; idx > 0; idx--) 361 CSR_READ_4(sc, DC_BUSCTL); 362 } 363 364 static void 365 dc_eeprom_width(struct dc_softc *sc) 366 { 367 int i; 368 369 /* Force EEPROM to idle state. */ 370 dc_eeprom_idle(sc); 371 372 /* Enter EEPROM access mode. */ 373 CSR_WRITE_4(sc, DC_SIO, DC_SIO_EESEL); 374 dc_delay(sc); 375 DC_SETBIT(sc, DC_SIO, DC_SIO_ROMCTL_READ); 376 dc_delay(sc); 377 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); 378 dc_delay(sc); 379 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CS); 380 dc_delay(sc); 381 382 for (i = 3; i--;) { 383 if (6 & (1 << i)) 384 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_DATAIN); 385 else 386 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_DATAIN); 387 dc_delay(sc); 388 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CLK); 389 dc_delay(sc); 390 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); 391 dc_delay(sc); 392 } 393 394 for (i = 1; i <= 12; i++) { 395 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CLK); 396 dc_delay(sc); 397 if (!(CSR_READ_4(sc, DC_SIO) & DC_SIO_EE_DATAOUT)) { 398 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); 399 dc_delay(sc); 400 break; 401 } 402 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); 403 dc_delay(sc); 404 } 405 406 /* Turn off EEPROM access mode. */ 407 dc_eeprom_idle(sc); 408 409 if (i < 4 || i > 12) 410 sc->dc_romwidth = 6; 411 else 412 sc->dc_romwidth = i; 413 414 /* Enter EEPROM access mode. */ 415 CSR_WRITE_4(sc, DC_SIO, DC_SIO_EESEL); 416 dc_delay(sc); 417 DC_SETBIT(sc, DC_SIO, DC_SIO_ROMCTL_READ); 418 dc_delay(sc); 419 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); 420 dc_delay(sc); 421 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CS); 422 dc_delay(sc); 423 424 /* Turn off EEPROM access mode. */ 425 dc_eeprom_idle(sc); 426 } 427 428 static void 429 dc_eeprom_idle(struct dc_softc *sc) 430 { 431 int i; 432 433 CSR_WRITE_4(sc, DC_SIO, DC_SIO_EESEL); 434 dc_delay(sc); 435 DC_SETBIT(sc, DC_SIO, DC_SIO_ROMCTL_READ); 436 dc_delay(sc); 437 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); 438 dc_delay(sc); 439 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CS); 440 dc_delay(sc); 441 442 for (i = 0; i < 25; i++) { 443 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); 444 dc_delay(sc); 445 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CLK); 446 dc_delay(sc); 447 } 448 449 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); 450 dc_delay(sc); 451 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CS); 452 dc_delay(sc); 453 CSR_WRITE_4(sc, DC_SIO, 0x00000000); 454 } 455 456 /* 457 * Send a read command and address to the EEPROM, check for ACK. 458 */ 459 static void 460 dc_eeprom_putbyte(struct dc_softc *sc, int addr) 461 { 462 int d, i; 463 464 d = DC_EECMD_READ >> 6; 465 for (i = 3; i--; ) { 466 if (d & (1 << i)) 467 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_DATAIN); 468 else 469 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_DATAIN); 470 dc_delay(sc); 471 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CLK); 472 dc_delay(sc); 473 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); 474 dc_delay(sc); 475 } 476 477 /* 478 * Feed in each bit and strobe the clock. 479 */ 480 for (i = sc->dc_romwidth; i--;) { 481 if (addr & (1 << i)) { 482 SIO_SET(DC_SIO_EE_DATAIN); 483 } else { 484 SIO_CLR(DC_SIO_EE_DATAIN); 485 } 486 dc_delay(sc); 487 SIO_SET(DC_SIO_EE_CLK); 488 dc_delay(sc); 489 SIO_CLR(DC_SIO_EE_CLK); 490 dc_delay(sc); 491 } 492 } 493 494 /* 495 * Read a word of data stored in the EEPROM at address 'addr.' 496 * The PNIC 82c168/82c169 has its own non-standard way to read 497 * the EEPROM. 498 */ 499 static void 500 dc_eeprom_getword_pnic(struct dc_softc *sc, int addr, u_int16_t *dest) 501 { 502 int i; 503 u_int32_t r; 504 505 CSR_WRITE_4(sc, DC_PN_SIOCTL, DC_PN_EEOPCODE_READ | addr); 506 507 for (i = 0; i < DC_TIMEOUT; i++) { 508 DELAY(1); 509 r = CSR_READ_4(sc, DC_SIO); 510 if (!(r & DC_PN_SIOCTL_BUSY)) { 511 *dest = (u_int16_t)(r & 0xFFFF); 512 return; 513 } 514 } 515 } 516 517 /* 518 * Read a word of data stored in the EEPROM at address 'addr.' 519 * The Xircom X3201 has its own non-standard way to read 520 * the EEPROM, too. 521 */ 522 static void 523 dc_eeprom_getword_xircom(struct dc_softc *sc, int addr, u_int16_t *dest) 524 { 525 526 SIO_SET(DC_SIO_ROMSEL | DC_SIO_ROMCTL_READ); 527 528 addr *= 2; 529 CSR_WRITE_4(sc, DC_ROM, addr | 0x160); 530 *dest = (u_int16_t)CSR_READ_4(sc, DC_SIO) & 0xff; 531 addr += 1; 532 CSR_WRITE_4(sc, DC_ROM, addr | 0x160); 533 *dest |= ((u_int16_t)CSR_READ_4(sc, DC_SIO) & 0xff) << 8; 534 535 SIO_CLR(DC_SIO_ROMSEL | DC_SIO_ROMCTL_READ); 536 } 537 538 /* 539 * Read a word of data stored in the EEPROM at address 'addr.' 540 */ 541 static void 542 dc_eeprom_getword(struct dc_softc *sc, int addr, u_int16_t *dest) 543 { 544 int i; 545 u_int16_t word = 0; 546 547 /* Force EEPROM to idle state. */ 548 dc_eeprom_idle(sc); 549 550 /* Enter EEPROM access mode. */ 551 CSR_WRITE_4(sc, DC_SIO, DC_SIO_EESEL); 552 dc_delay(sc); 553 DC_SETBIT(sc, DC_SIO, DC_SIO_ROMCTL_READ); 554 dc_delay(sc); 555 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); 556 dc_delay(sc); 557 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CS); 558 dc_delay(sc); 559 560 /* 561 * Send address of word we want to read. 562 */ 563 dc_eeprom_putbyte(sc, addr); 564 565 /* 566 * Start reading bits from EEPROM. 567 */ 568 for (i = 0x8000; i; i >>= 1) { 569 SIO_SET(DC_SIO_EE_CLK); 570 dc_delay(sc); 571 if (CSR_READ_4(sc, DC_SIO) & DC_SIO_EE_DATAOUT) 572 word |= i; 573 dc_delay(sc); 574 SIO_CLR(DC_SIO_EE_CLK); 575 dc_delay(sc); 576 } 577 578 /* Turn off EEPROM access mode. */ 579 dc_eeprom_idle(sc); 580 581 *dest = word; 582 } 583 584 /* 585 * Read a sequence of words from the EEPROM. 586 */ 587 static void 588 dc_read_eeprom(struct dc_softc *sc, caddr_t dest, int off, int cnt, int be) 589 { 590 int i; 591 u_int16_t word = 0, *ptr; 592 593 for (i = 0; i < cnt; i++) { 594 if (DC_IS_PNIC(sc)) 595 dc_eeprom_getword_pnic(sc, off + i, &word); 596 else if (DC_IS_XIRCOM(sc)) 597 dc_eeprom_getword_xircom(sc, off + i, &word); 598 else 599 dc_eeprom_getword(sc, off + i, &word); 600 ptr = (u_int16_t *)(dest + (i * 2)); 601 if (be) 602 *ptr = be16toh(word); 603 else 604 *ptr = le16toh(word); 605 } 606 } 607 608 /* 609 * The following two routines are taken from the Macronix 98713 610 * Application Notes pp.19-21. 611 */ 612 /* 613 * Write a bit to the MII bus. 614 */ 615 static void 616 dc_mii_writebit(struct dc_softc *sc, int bit) 617 { 618 619 if (bit) 620 CSR_WRITE_4(sc, DC_SIO, 621 DC_SIO_ROMCTL_WRITE | DC_SIO_MII_DATAOUT); 622 else 623 CSR_WRITE_4(sc, DC_SIO, DC_SIO_ROMCTL_WRITE); 624 625 DC_SETBIT(sc, DC_SIO, DC_SIO_MII_CLK); 626 DC_CLRBIT(sc, DC_SIO, DC_SIO_MII_CLK); 627 } 628 629 /* 630 * Read a bit from the MII bus. 631 */ 632 static int 633 dc_mii_readbit(struct dc_softc *sc) 634 { 635 636 CSR_WRITE_4(sc, DC_SIO, DC_SIO_ROMCTL_READ | DC_SIO_MII_DIR); 637 CSR_READ_4(sc, DC_SIO); 638 DC_SETBIT(sc, DC_SIO, DC_SIO_MII_CLK); 639 DC_CLRBIT(sc, DC_SIO, DC_SIO_MII_CLK); 640 if (CSR_READ_4(sc, DC_SIO) & DC_SIO_MII_DATAIN) 641 return (1); 642 643 return (0); 644 } 645 646 /* 647 * Sync the PHYs by setting data bit and strobing the clock 32 times. 648 */ 649 static void 650 dc_mii_sync(struct dc_softc *sc) 651 { 652 int i; 653 654 CSR_WRITE_4(sc, DC_SIO, DC_SIO_ROMCTL_WRITE); 655 656 for (i = 0; i < 32; i++) 657 dc_mii_writebit(sc, 1); 658 } 659 660 /* 661 * Clock a series of bits through the MII. 662 */ 663 static void 664 dc_mii_send(struct dc_softc *sc, u_int32_t bits, int cnt) 665 { 666 int i; 667 668 for (i = (0x1 << (cnt - 1)); i; i >>= 1) 669 dc_mii_writebit(sc, bits & i); 670 } 671 672 /* 673 * Read an PHY register through the MII. 674 */ 675 static int 676 dc_mii_readreg(struct dc_softc *sc, struct dc_mii_frame *frame) 677 { 678 int i, ack; 679 680 /* 681 * Set up frame for RX. 682 */ 683 frame->mii_stdelim = DC_MII_STARTDELIM; 684 frame->mii_opcode = DC_MII_READOP; 685 frame->mii_turnaround = 0; 686 frame->mii_data = 0; 687 688 /* 689 * Sync the PHYs. 690 */ 691 dc_mii_sync(sc); 692 693 /* 694 * Send command/address info. 695 */ 696 dc_mii_send(sc, frame->mii_stdelim, 2); 697 dc_mii_send(sc, frame->mii_opcode, 2); 698 dc_mii_send(sc, frame->mii_phyaddr, 5); 699 dc_mii_send(sc, frame->mii_regaddr, 5); 700 701 #ifdef notdef 702 /* Idle bit */ 703 dc_mii_writebit(sc, 1); 704 dc_mii_writebit(sc, 0); 705 #endif 706 707 /* Check for ack. */ 708 ack = dc_mii_readbit(sc); 709 710 /* 711 * Now try reading data bits. If the ack failed, we still 712 * need to clock through 16 cycles to keep the PHY(s) in sync. 713 */ 714 if (ack) { 715 for (i = 0; i < 16; i++) 716 dc_mii_readbit(sc); 717 goto fail; 718 } 719 720 for (i = 0x8000; i; i >>= 1) { 721 if (!ack) { 722 if (dc_mii_readbit(sc)) 723 frame->mii_data |= i; 724 } 725 } 726 727 fail: 728 729 dc_mii_writebit(sc, 0); 730 dc_mii_writebit(sc, 0); 731 732 if (ack) 733 return (1); 734 return (0); 735 } 736 737 /* 738 * Write to a PHY register through the MII. 739 */ 740 static int 741 dc_mii_writereg(struct dc_softc *sc, struct dc_mii_frame *frame) 742 { 743 744 /* 745 * Set up frame for TX. 746 */ 747 748 frame->mii_stdelim = DC_MII_STARTDELIM; 749 frame->mii_opcode = DC_MII_WRITEOP; 750 frame->mii_turnaround = DC_MII_TURNAROUND; 751 752 /* 753 * Sync the PHYs. 754 */ 755 dc_mii_sync(sc); 756 757 dc_mii_send(sc, frame->mii_stdelim, 2); 758 dc_mii_send(sc, frame->mii_opcode, 2); 759 dc_mii_send(sc, frame->mii_phyaddr, 5); 760 dc_mii_send(sc, frame->mii_regaddr, 5); 761 dc_mii_send(sc, frame->mii_turnaround, 2); 762 dc_mii_send(sc, frame->mii_data, 16); 763 764 /* Idle bit. */ 765 dc_mii_writebit(sc, 0); 766 dc_mii_writebit(sc, 0); 767 768 return (0); 769 } 770 771 static int 772 dc_miibus_readreg(device_t dev, int phy, int reg) 773 { 774 struct dc_mii_frame frame; 775 struct dc_softc *sc; 776 int i, rval, phy_reg = 0; 777 778 sc = device_get_softc(dev); 779 bzero(&frame, sizeof(frame)); 780 781 /* 782 * Note: both the AL981 and AN985 have internal PHYs, 783 * however the AL981 provides direct access to the PHY 784 * registers while the AN985 uses a serial MII interface. 785 * The AN985's MII interface is also buggy in that you 786 * can read from any MII address (0 to 31), but only address 1 787 * behaves normally. To deal with both cases, we pretend 788 * that the PHY is at MII address 1. 789 */ 790 if (DC_IS_ADMTEK(sc) && phy != DC_ADMTEK_PHYADDR) 791 return (0); 792 793 /* 794 * Note: the ukphy probes of the RS7112 report a PHY at 795 * MII address 0 (possibly HomePNA?) and 1 (ethernet) 796 * so we only respond to correct one. 797 */ 798 if (DC_IS_CONEXANT(sc) && phy != DC_CONEXANT_PHYADDR) 799 return (0); 800 801 if (sc->dc_pmode != DC_PMODE_MII) { 802 if (phy == (MII_NPHY - 1)) { 803 switch (reg) { 804 case MII_BMSR: 805 /* 806 * Fake something to make the probe 807 * code think there's a PHY here. 808 */ 809 return (BMSR_MEDIAMASK); 810 break; 811 case MII_PHYIDR1: 812 if (DC_IS_PNIC(sc)) 813 return (DC_VENDORID_LO); 814 return (DC_VENDORID_DEC); 815 break; 816 case MII_PHYIDR2: 817 if (DC_IS_PNIC(sc)) 818 return (DC_DEVICEID_82C168); 819 return (DC_DEVICEID_21143); 820 break; 821 default: 822 return (0); 823 break; 824 } 825 } else 826 return (0); 827 } 828 829 if (DC_IS_PNIC(sc)) { 830 CSR_WRITE_4(sc, DC_PN_MII, DC_PN_MIIOPCODE_READ | 831 (phy << 23) | (reg << 18)); 832 for (i = 0; i < DC_TIMEOUT; i++) { 833 DELAY(1); 834 rval = CSR_READ_4(sc, DC_PN_MII); 835 if (!(rval & DC_PN_MII_BUSY)) { 836 rval &= 0xFFFF; 837 return (rval == 0xFFFF ? 0 : rval); 838 } 839 } 840 return (0); 841 } 842 843 if (DC_IS_COMET(sc)) { 844 switch (reg) { 845 case MII_BMCR: 846 phy_reg = DC_AL_BMCR; 847 break; 848 case MII_BMSR: 849 phy_reg = DC_AL_BMSR; 850 break; 851 case MII_PHYIDR1: 852 phy_reg = DC_AL_VENID; 853 break; 854 case MII_PHYIDR2: 855 phy_reg = DC_AL_DEVID; 856 break; 857 case MII_ANAR: 858 phy_reg = DC_AL_ANAR; 859 break; 860 case MII_ANLPAR: 861 phy_reg = DC_AL_LPAR; 862 break; 863 case MII_ANER: 864 phy_reg = DC_AL_ANER; 865 break; 866 default: 867 device_printf(dev, "phy_read: bad phy register %x\n", 868 reg); 869 return (0); 870 break; 871 } 872 873 rval = CSR_READ_4(sc, phy_reg) & 0x0000FFFF; 874 875 if (rval == 0xFFFF) 876 return (0); 877 return (rval); 878 } 879 880 frame.mii_phyaddr = phy; 881 frame.mii_regaddr = reg; 882 if (sc->dc_type == DC_TYPE_98713) { 883 phy_reg = CSR_READ_4(sc, DC_NETCFG); 884 CSR_WRITE_4(sc, DC_NETCFG, phy_reg & ~DC_NETCFG_PORTSEL); 885 } 886 dc_mii_readreg(sc, &frame); 887 if (sc->dc_type == DC_TYPE_98713) 888 CSR_WRITE_4(sc, DC_NETCFG, phy_reg); 889 890 return (frame.mii_data); 891 } 892 893 static int 894 dc_miibus_writereg(device_t dev, int phy, int reg, int data) 895 { 896 struct dc_softc *sc; 897 struct dc_mii_frame frame; 898 int i, phy_reg = 0; 899 900 sc = device_get_softc(dev); 901 bzero(&frame, sizeof(frame)); 902 903 if (DC_IS_ADMTEK(sc) && phy != DC_ADMTEK_PHYADDR) 904 return (0); 905 906 if (DC_IS_CONEXANT(sc) && phy != DC_CONEXANT_PHYADDR) 907 return (0); 908 909 if (DC_IS_PNIC(sc)) { 910 CSR_WRITE_4(sc, DC_PN_MII, DC_PN_MIIOPCODE_WRITE | 911 (phy << 23) | (reg << 10) | data); 912 for (i = 0; i < DC_TIMEOUT; i++) { 913 if (!(CSR_READ_4(sc, DC_PN_MII) & DC_PN_MII_BUSY)) 914 break; 915 } 916 return (0); 917 } 918 919 if (DC_IS_COMET(sc)) { 920 switch (reg) { 921 case MII_BMCR: 922 phy_reg = DC_AL_BMCR; 923 break; 924 case MII_BMSR: 925 phy_reg = DC_AL_BMSR; 926 break; 927 case MII_PHYIDR1: 928 phy_reg = DC_AL_VENID; 929 break; 930 case MII_PHYIDR2: 931 phy_reg = DC_AL_DEVID; 932 break; 933 case MII_ANAR: 934 phy_reg = DC_AL_ANAR; 935 break; 936 case MII_ANLPAR: 937 phy_reg = DC_AL_LPAR; 938 break; 939 case MII_ANER: 940 phy_reg = DC_AL_ANER; 941 break; 942 default: 943 device_printf(dev, "phy_write: bad phy register %x\n", 944 reg); 945 return (0); 946 break; 947 } 948 949 CSR_WRITE_4(sc, phy_reg, data); 950 return (0); 951 } 952 953 frame.mii_phyaddr = phy; 954 frame.mii_regaddr = reg; 955 frame.mii_data = data; 956 957 if (sc->dc_type == DC_TYPE_98713) { 958 phy_reg = CSR_READ_4(sc, DC_NETCFG); 959 CSR_WRITE_4(sc, DC_NETCFG, phy_reg & ~DC_NETCFG_PORTSEL); 960 } 961 dc_mii_writereg(sc, &frame); 962 if (sc->dc_type == DC_TYPE_98713) 963 CSR_WRITE_4(sc, DC_NETCFG, phy_reg); 964 965 return (0); 966 } 967 968 static void 969 dc_miibus_statchg(device_t dev) 970 { 971 struct dc_softc *sc; 972 struct mii_data *mii; 973 struct ifmedia *ifm; 974 975 sc = device_get_softc(dev); 976 if (DC_IS_ADMTEK(sc)) 977 return; 978 979 mii = device_get_softc(sc->dc_miibus); 980 ifm = &mii->mii_media; 981 if (DC_IS_DAVICOM(sc) && 982 IFM_SUBTYPE(ifm->ifm_media) == IFM_HPNA_1) { 983 dc_setcfg(sc, ifm->ifm_media); 984 sc->dc_if_media = ifm->ifm_media; 985 } else { 986 dc_setcfg(sc, mii->mii_media_active); 987 sc->dc_if_media = mii->mii_media_active; 988 } 989 } 990 991 /* 992 * Special support for DM9102A cards with HomePNA PHYs. Note: 993 * with the Davicom DM9102A/DM9801 eval board that I have, it seems 994 * to be impossible to talk to the management interface of the DM9801 995 * PHY (its MDIO pin is not connected to anything). Consequently, 996 * the driver has to just 'know' about the additional mode and deal 997 * with it itself. *sigh* 998 */ 999 static void 1000 dc_miibus_mediainit(device_t dev) 1001 { 1002 struct dc_softc *sc; 1003 struct mii_data *mii; 1004 struct ifmedia *ifm; 1005 int rev; 1006 1007 rev = pci_read_config(dev, DC_PCI_CFRV, 4) & 0xFF; 1008 1009 sc = device_get_softc(dev); 1010 mii = device_get_softc(sc->dc_miibus); 1011 ifm = &mii->mii_media; 1012 1013 if (DC_IS_DAVICOM(sc) && rev >= DC_REVISION_DM9102A) 1014 ifmedia_add(ifm, IFM_ETHER | IFM_HPNA_1, 0, NULL); 1015 } 1016 1017 #define DC_BITS_512 9 1018 #define DC_BITS_128 7 1019 #define DC_BITS_64 6 1020 1021 static uint32_t 1022 dc_mchash_le(struct dc_softc *sc, const uint8_t *addr) 1023 { 1024 uint32_t crc; 1025 1026 /* Compute CRC for the address value. */ 1027 crc = ether_crc32_le(addr, ETHER_ADDR_LEN); 1028 1029 /* 1030 * The hash table on the PNIC II and the MX98715AEC-C/D/E 1031 * chips is only 128 bits wide. 1032 */ 1033 if (sc->dc_flags & DC_128BIT_HASH) 1034 return (crc & ((1 << DC_BITS_128) - 1)); 1035 1036 /* The hash table on the MX98715BEC is only 64 bits wide. */ 1037 if (sc->dc_flags & DC_64BIT_HASH) 1038 return (crc & ((1 << DC_BITS_64) - 1)); 1039 1040 /* Xircom's hash filtering table is different (read: weird) */ 1041 /* Xircom uses the LEAST significant bits */ 1042 if (DC_IS_XIRCOM(sc)) { 1043 if ((crc & 0x180) == 0x180) 1044 return ((crc & 0x0F) + (crc & 0x70) * 3 + (14 << 4)); 1045 else 1046 return ((crc & 0x1F) + ((crc >> 1) & 0xF0) * 3 + 1047 (12 << 4)); 1048 } 1049 1050 return (crc & ((1 << DC_BITS_512) - 1)); 1051 } 1052 1053 /* 1054 * Calculate CRC of a multicast group address, return the lower 6 bits. 1055 */ 1056 static uint32_t 1057 dc_mchash_be(const uint8_t *addr) 1058 { 1059 uint32_t crc; 1060 1061 /* Compute CRC for the address value. */ 1062 crc = ether_crc32_be(addr, ETHER_ADDR_LEN); 1063 1064 /* Return the filter bit position. */ 1065 return ((crc >> 26) & 0x0000003F); 1066 } 1067 1068 /* 1069 * 21143-style RX filter setup routine. Filter programming is done by 1070 * downloading a special setup frame into the TX engine. 21143, Macronix, 1071 * PNIC, PNIC II and Davicom chips are programmed this way. 1072 * 1073 * We always program the chip using 'hash perfect' mode, i.e. one perfect 1074 * address (our node address) and a 512-bit hash filter for multicast 1075 * frames. We also sneak the broadcast address into the hash filter since 1076 * we need that too. 1077 */ 1078 static void 1079 dc_setfilt_21143(struct dc_softc *sc) 1080 { 1081 uint16_t eaddr[(ETHER_ADDR_LEN+1)/2]; 1082 struct dc_desc *sframe; 1083 u_int32_t h, *sp; 1084 struct ifmultiaddr *ifma; 1085 struct ifnet *ifp; 1086 int i; 1087 1088 ifp = sc->dc_ifp; 1089 1090 i = sc->dc_cdata.dc_tx_prod; 1091 DC_INC(sc->dc_cdata.dc_tx_prod, DC_TX_LIST_CNT); 1092 sc->dc_cdata.dc_tx_cnt++; 1093 sframe = &sc->dc_ldata->dc_tx_list[i]; 1094 sp = sc->dc_cdata.dc_sbuf; 1095 bzero(sp, DC_SFRAME_LEN); 1096 1097 sframe->dc_data = htole32(sc->dc_saddr); 1098 sframe->dc_ctl = htole32(DC_SFRAME_LEN | DC_TXCTL_SETUP | 1099 DC_TXCTL_TLINK | DC_FILTER_HASHPERF | DC_TXCTL_FINT); 1100 1101 sc->dc_cdata.dc_tx_chain[i] = (struct mbuf *)sc->dc_cdata.dc_sbuf; 1102 1103 /* If we want promiscuous mode, set the allframes bit. */ 1104 if (ifp->if_flags & IFF_PROMISC) 1105 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC); 1106 else 1107 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC); 1108 1109 if (ifp->if_flags & IFF_ALLMULTI) 1110 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI); 1111 else 1112 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI); 1113 1114 IF_ADDR_LOCK(ifp); 1115 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 1116 if (ifma->ifma_addr->sa_family != AF_LINK) 1117 continue; 1118 h = dc_mchash_le(sc, 1119 LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 1120 sp[h >> 4] |= htole32(1 << (h & 0xF)); 1121 } 1122 IF_ADDR_UNLOCK(ifp); 1123 1124 if (ifp->if_flags & IFF_BROADCAST) { 1125 h = dc_mchash_le(sc, ifp->if_broadcastaddr); 1126 sp[h >> 4] |= htole32(1 << (h & 0xF)); 1127 } 1128 1129 /* Set our MAC address. */ 1130 bcopy(IF_LLADDR(sc->dc_ifp), eaddr, ETHER_ADDR_LEN); 1131 sp[39] = DC_SP_MAC(eaddr[0]); 1132 sp[40] = DC_SP_MAC(eaddr[1]); 1133 sp[41] = DC_SP_MAC(eaddr[2]); 1134 1135 sframe->dc_status = htole32(DC_TXSTAT_OWN); 1136 CSR_WRITE_4(sc, DC_TXSTART, 0xFFFFFFFF); 1137 1138 /* 1139 * The PNIC takes an exceedingly long time to process its 1140 * setup frame; wait 10ms after posting the setup frame 1141 * before proceeding, just so it has time to swallow its 1142 * medicine. 1143 */ 1144 DELAY(10000); 1145 1146 ifp->if_timer = 5; 1147 } 1148 1149 static void 1150 dc_setfilt_admtek(struct dc_softc *sc) 1151 { 1152 uint32_t eaddr[(ETHER_ADDR_LEN+3)/4]; 1153 struct ifnet *ifp; 1154 struct ifmultiaddr *ifma; 1155 int h = 0; 1156 u_int32_t hashes[2] = { 0, 0 }; 1157 1158 ifp = sc->dc_ifp; 1159 1160 /* Init our MAC address. */ 1161 bcopy(IF_LLADDR(sc->dc_ifp), eaddr, ETHER_ADDR_LEN); 1162 CSR_WRITE_4(sc, DC_AL_PAR0, eaddr[0]); 1163 CSR_WRITE_4(sc, DC_AL_PAR1, eaddr[1]); 1164 1165 /* If we want promiscuous mode, set the allframes bit. */ 1166 if (ifp->if_flags & IFF_PROMISC) 1167 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC); 1168 else 1169 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC); 1170 1171 if (ifp->if_flags & IFF_ALLMULTI) 1172 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI); 1173 else 1174 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI); 1175 1176 /* First, zot all the existing hash bits. */ 1177 CSR_WRITE_4(sc, DC_AL_MAR0, 0); 1178 CSR_WRITE_4(sc, DC_AL_MAR1, 0); 1179 1180 /* 1181 * If we're already in promisc or allmulti mode, we 1182 * don't have to bother programming the multicast filter. 1183 */ 1184 if (ifp->if_flags & (IFF_PROMISC | IFF_ALLMULTI)) 1185 return; 1186 1187 /* Now program new ones. */ 1188 IF_ADDR_LOCK(ifp); 1189 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 1190 if (ifma->ifma_addr->sa_family != AF_LINK) 1191 continue; 1192 if (DC_IS_CENTAUR(sc)) 1193 h = dc_mchash_le(sc, 1194 LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 1195 else 1196 h = dc_mchash_be( 1197 LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 1198 if (h < 32) 1199 hashes[0] |= (1 << h); 1200 else 1201 hashes[1] |= (1 << (h - 32)); 1202 } 1203 IF_ADDR_UNLOCK(ifp); 1204 1205 CSR_WRITE_4(sc, DC_AL_MAR0, hashes[0]); 1206 CSR_WRITE_4(sc, DC_AL_MAR1, hashes[1]); 1207 } 1208 1209 static void 1210 dc_setfilt_asix(struct dc_softc *sc) 1211 { 1212 uint32_t eaddr[(ETHER_ADDR_LEN+3)/4]; 1213 struct ifnet *ifp; 1214 struct ifmultiaddr *ifma; 1215 int h = 0; 1216 u_int32_t hashes[2] = { 0, 0 }; 1217 1218 ifp = sc->dc_ifp; 1219 1220 /* Init our MAC address. */ 1221 bcopy(IF_LLADDR(sc->dc_ifp), eaddr, ETHER_ADDR_LEN); 1222 CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_PAR0); 1223 CSR_WRITE_4(sc, DC_AX_FILTDATA, eaddr[0]); 1224 CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_PAR1); 1225 CSR_WRITE_4(sc, DC_AX_FILTDATA, eaddr[1]); 1226 1227 /* If we want promiscuous mode, set the allframes bit. */ 1228 if (ifp->if_flags & IFF_PROMISC) 1229 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC); 1230 else 1231 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC); 1232 1233 if (ifp->if_flags & IFF_ALLMULTI) 1234 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI); 1235 else 1236 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI); 1237 1238 /* 1239 * The ASIX chip has a special bit to enable reception 1240 * of broadcast frames. 1241 */ 1242 if (ifp->if_flags & IFF_BROADCAST) 1243 DC_SETBIT(sc, DC_NETCFG, DC_AX_NETCFG_RX_BROAD); 1244 else 1245 DC_CLRBIT(sc, DC_NETCFG, DC_AX_NETCFG_RX_BROAD); 1246 1247 /* first, zot all the existing hash bits */ 1248 CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_MAR0); 1249 CSR_WRITE_4(sc, DC_AX_FILTDATA, 0); 1250 CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_MAR1); 1251 CSR_WRITE_4(sc, DC_AX_FILTDATA, 0); 1252 1253 /* 1254 * If we're already in promisc or allmulti mode, we 1255 * don't have to bother programming the multicast filter. 1256 */ 1257 if (ifp->if_flags & (IFF_PROMISC | IFF_ALLMULTI)) 1258 return; 1259 1260 /* now program new ones */ 1261 IF_ADDR_LOCK(ifp); 1262 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 1263 if (ifma->ifma_addr->sa_family != AF_LINK) 1264 continue; 1265 h = dc_mchash_be(LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 1266 if (h < 32) 1267 hashes[0] |= (1 << h); 1268 else 1269 hashes[1] |= (1 << (h - 32)); 1270 } 1271 IF_ADDR_UNLOCK(ifp); 1272 1273 CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_MAR0); 1274 CSR_WRITE_4(sc, DC_AX_FILTDATA, hashes[0]); 1275 CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_MAR1); 1276 CSR_WRITE_4(sc, DC_AX_FILTDATA, hashes[1]); 1277 } 1278 1279 static void 1280 dc_setfilt_xircom(struct dc_softc *sc) 1281 { 1282 uint16_t eaddr[(ETHER_ADDR_LEN+1)/2]; 1283 struct ifnet *ifp; 1284 struct ifmultiaddr *ifma; 1285 struct dc_desc *sframe; 1286 u_int32_t h, *sp; 1287 int i; 1288 1289 ifp = sc->dc_ifp; 1290 DC_CLRBIT(sc, DC_NETCFG, (DC_NETCFG_TX_ON | DC_NETCFG_RX_ON)); 1291 1292 i = sc->dc_cdata.dc_tx_prod; 1293 DC_INC(sc->dc_cdata.dc_tx_prod, DC_TX_LIST_CNT); 1294 sc->dc_cdata.dc_tx_cnt++; 1295 sframe = &sc->dc_ldata->dc_tx_list[i]; 1296 sp = sc->dc_cdata.dc_sbuf; 1297 bzero(sp, DC_SFRAME_LEN); 1298 1299 sframe->dc_data = htole32(sc->dc_saddr); 1300 sframe->dc_ctl = htole32(DC_SFRAME_LEN | DC_TXCTL_SETUP | 1301 DC_TXCTL_TLINK | DC_FILTER_HASHPERF | DC_TXCTL_FINT); 1302 1303 sc->dc_cdata.dc_tx_chain[i] = (struct mbuf *)sc->dc_cdata.dc_sbuf; 1304 1305 /* If we want promiscuous mode, set the allframes bit. */ 1306 if (ifp->if_flags & IFF_PROMISC) 1307 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC); 1308 else 1309 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC); 1310 1311 if (ifp->if_flags & IFF_ALLMULTI) 1312 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI); 1313 else 1314 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI); 1315 1316 IF_ADDR_LOCK(ifp); 1317 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 1318 if (ifma->ifma_addr->sa_family != AF_LINK) 1319 continue; 1320 h = dc_mchash_le(sc, 1321 LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 1322 sp[h >> 4] |= htole32(1 << (h & 0xF)); 1323 } 1324 IF_ADDR_UNLOCK(ifp); 1325 1326 if (ifp->if_flags & IFF_BROADCAST) { 1327 h = dc_mchash_le(sc, ifp->if_broadcastaddr); 1328 sp[h >> 4] |= htole32(1 << (h & 0xF)); 1329 } 1330 1331 /* Set our MAC address. */ 1332 bcopy(IF_LLADDR(sc->dc_ifp), eaddr, ETHER_ADDR_LEN); 1333 sp[0] = DC_SP_MAC(eaddr[0]); 1334 sp[1] = DC_SP_MAC(eaddr[1]); 1335 sp[2] = DC_SP_MAC(eaddr[2]); 1336 1337 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_TX_ON); 1338 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_ON); 1339 ifp->if_drv_flags |= IFF_DRV_RUNNING; 1340 sframe->dc_status = htole32(DC_TXSTAT_OWN); 1341 CSR_WRITE_4(sc, DC_TXSTART, 0xFFFFFFFF); 1342 1343 /* 1344 * Wait some time... 1345 */ 1346 DELAY(1000); 1347 1348 ifp->if_timer = 5; 1349 } 1350 1351 static void 1352 dc_setfilt(struct dc_softc *sc) 1353 { 1354 1355 if (DC_IS_INTEL(sc) || DC_IS_MACRONIX(sc) || DC_IS_PNIC(sc) || 1356 DC_IS_PNICII(sc) || DC_IS_DAVICOM(sc) || DC_IS_CONEXANT(sc)) 1357 dc_setfilt_21143(sc); 1358 1359 if (DC_IS_ASIX(sc)) 1360 dc_setfilt_asix(sc); 1361 1362 if (DC_IS_ADMTEK(sc)) 1363 dc_setfilt_admtek(sc); 1364 1365 if (DC_IS_XIRCOM(sc)) 1366 dc_setfilt_xircom(sc); 1367 } 1368 1369 /* 1370 * In order to fiddle with the 'full-duplex' and '100Mbps' bits in 1371 * the netconfig register, we first have to put the transmit and/or 1372 * receive logic in the idle state. 1373 */ 1374 static void 1375 dc_setcfg(struct dc_softc *sc, int media) 1376 { 1377 int i, restart = 0, watchdogreg; 1378 u_int32_t isr; 1379 1380 if (IFM_SUBTYPE(media) == IFM_NONE) 1381 return; 1382 1383 if (CSR_READ_4(sc, DC_NETCFG) & (DC_NETCFG_TX_ON | DC_NETCFG_RX_ON)) { 1384 restart = 1; 1385 DC_CLRBIT(sc, DC_NETCFG, (DC_NETCFG_TX_ON | DC_NETCFG_RX_ON)); 1386 1387 for (i = 0; i < DC_TIMEOUT; i++) { 1388 isr = CSR_READ_4(sc, DC_ISR); 1389 if (isr & DC_ISR_TX_IDLE && 1390 ((isr & DC_ISR_RX_STATE) == DC_RXSTATE_STOPPED || 1391 (isr & DC_ISR_RX_STATE) == DC_RXSTATE_WAIT)) 1392 break; 1393 DELAY(10); 1394 } 1395 1396 if (i == DC_TIMEOUT) 1397 if_printf(sc->dc_ifp, 1398 "failed to force tx and rx to idle state\n"); 1399 } 1400 1401 if (IFM_SUBTYPE(media) == IFM_100_TX) { 1402 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_SPEEDSEL); 1403 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_HEARTBEAT); 1404 if (sc->dc_pmode == DC_PMODE_MII) { 1405 if (DC_IS_INTEL(sc)) { 1406 /* There's a write enable bit here that reads as 1. */ 1407 watchdogreg = CSR_READ_4(sc, DC_WATCHDOG); 1408 watchdogreg &= ~DC_WDOG_CTLWREN; 1409 watchdogreg |= DC_WDOG_JABBERDIS; 1410 CSR_WRITE_4(sc, DC_WATCHDOG, watchdogreg); 1411 } else { 1412 DC_SETBIT(sc, DC_WATCHDOG, DC_WDOG_JABBERDIS); 1413 } 1414 DC_CLRBIT(sc, DC_NETCFG, (DC_NETCFG_PCS | 1415 DC_NETCFG_PORTSEL | DC_NETCFG_SCRAMBLER)); 1416 if (sc->dc_type == DC_TYPE_98713) 1417 DC_SETBIT(sc, DC_NETCFG, (DC_NETCFG_PCS | 1418 DC_NETCFG_SCRAMBLER)); 1419 if (!DC_IS_DAVICOM(sc)) 1420 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL); 1421 DC_CLRBIT(sc, DC_10BTCTRL, 0xFFFF); 1422 if (DC_IS_INTEL(sc)) 1423 dc_apply_fixup(sc, IFM_AUTO); 1424 } else { 1425 if (DC_IS_PNIC(sc)) { 1426 DC_PN_GPIO_SETBIT(sc, DC_PN_GPIO_SPEEDSEL); 1427 DC_PN_GPIO_SETBIT(sc, DC_PN_GPIO_100TX_LOOP); 1428 DC_SETBIT(sc, DC_PN_NWAY, DC_PN_NWAY_SPEEDSEL); 1429 } 1430 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL); 1431 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PCS); 1432 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_SCRAMBLER); 1433 if (DC_IS_INTEL(sc)) 1434 dc_apply_fixup(sc, 1435 (media & IFM_GMASK) == IFM_FDX ? 1436 IFM_100_TX | IFM_FDX : IFM_100_TX); 1437 } 1438 } 1439 1440 if (IFM_SUBTYPE(media) == IFM_10_T) { 1441 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_SPEEDSEL); 1442 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_HEARTBEAT); 1443 if (sc->dc_pmode == DC_PMODE_MII) { 1444 /* There's a write enable bit here that reads as 1. */ 1445 if (DC_IS_INTEL(sc)) { 1446 watchdogreg = CSR_READ_4(sc, DC_WATCHDOG); 1447 watchdogreg &= ~DC_WDOG_CTLWREN; 1448 watchdogreg |= DC_WDOG_JABBERDIS; 1449 CSR_WRITE_4(sc, DC_WATCHDOG, watchdogreg); 1450 } else { 1451 DC_SETBIT(sc, DC_WATCHDOG, DC_WDOG_JABBERDIS); 1452 } 1453 DC_CLRBIT(sc, DC_NETCFG, (DC_NETCFG_PCS | 1454 DC_NETCFG_PORTSEL | DC_NETCFG_SCRAMBLER)); 1455 if (sc->dc_type == DC_TYPE_98713) 1456 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PCS); 1457 if (!DC_IS_DAVICOM(sc)) 1458 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL); 1459 DC_CLRBIT(sc, DC_10BTCTRL, 0xFFFF); 1460 if (DC_IS_INTEL(sc)) 1461 dc_apply_fixup(sc, IFM_AUTO); 1462 } else { 1463 if (DC_IS_PNIC(sc)) { 1464 DC_PN_GPIO_CLRBIT(sc, DC_PN_GPIO_SPEEDSEL); 1465 DC_PN_GPIO_SETBIT(sc, DC_PN_GPIO_100TX_LOOP); 1466 DC_CLRBIT(sc, DC_PN_NWAY, DC_PN_NWAY_SPEEDSEL); 1467 } 1468 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL); 1469 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_PCS); 1470 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_SCRAMBLER); 1471 if (DC_IS_INTEL(sc)) { 1472 DC_CLRBIT(sc, DC_SIARESET, DC_SIA_RESET); 1473 DC_CLRBIT(sc, DC_10BTCTRL, 0xFFFF); 1474 if ((media & IFM_GMASK) == IFM_FDX) 1475 DC_SETBIT(sc, DC_10BTCTRL, 0x7F3D); 1476 else 1477 DC_SETBIT(sc, DC_10BTCTRL, 0x7F3F); 1478 DC_SETBIT(sc, DC_SIARESET, DC_SIA_RESET); 1479 DC_CLRBIT(sc, DC_10BTCTRL, 1480 DC_TCTL_AUTONEGENBL); 1481 dc_apply_fixup(sc, 1482 (media & IFM_GMASK) == IFM_FDX ? 1483 IFM_10_T | IFM_FDX : IFM_10_T); 1484 DELAY(20000); 1485 } 1486 } 1487 } 1488 1489 /* 1490 * If this is a Davicom DM9102A card with a DM9801 HomePNA 1491 * PHY and we want HomePNA mode, set the portsel bit to turn 1492 * on the external MII port. 1493 */ 1494 if (DC_IS_DAVICOM(sc)) { 1495 if (IFM_SUBTYPE(media) == IFM_HPNA_1) { 1496 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL); 1497 sc->dc_link = 1; 1498 } else { 1499 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL); 1500 } 1501 } 1502 1503 if ((media & IFM_GMASK) == IFM_FDX) { 1504 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_FULLDUPLEX); 1505 if (sc->dc_pmode == DC_PMODE_SYM && DC_IS_PNIC(sc)) 1506 DC_SETBIT(sc, DC_PN_NWAY, DC_PN_NWAY_DUPLEX); 1507 } else { 1508 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_FULLDUPLEX); 1509 if (sc->dc_pmode == DC_PMODE_SYM && DC_IS_PNIC(sc)) 1510 DC_CLRBIT(sc, DC_PN_NWAY, DC_PN_NWAY_DUPLEX); 1511 } 1512 1513 if (restart) 1514 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_TX_ON | DC_NETCFG_RX_ON); 1515 } 1516 1517 static void 1518 dc_reset(struct dc_softc *sc) 1519 { 1520 int i; 1521 1522 DC_SETBIT(sc, DC_BUSCTL, DC_BUSCTL_RESET); 1523 1524 for (i = 0; i < DC_TIMEOUT; i++) { 1525 DELAY(10); 1526 if (!(CSR_READ_4(sc, DC_BUSCTL) & DC_BUSCTL_RESET)) 1527 break; 1528 } 1529 1530 if (DC_IS_ASIX(sc) || DC_IS_ADMTEK(sc) || DC_IS_CONEXANT(sc) || 1531 DC_IS_XIRCOM(sc) || DC_IS_INTEL(sc)) { 1532 DELAY(10000); 1533 DC_CLRBIT(sc, DC_BUSCTL, DC_BUSCTL_RESET); 1534 i = 0; 1535 } 1536 1537 if (i == DC_TIMEOUT) 1538 if_printf(sc->dc_ifp, "reset never completed!\n"); 1539 1540 /* Wait a little while for the chip to get its brains in order. */ 1541 DELAY(1000); 1542 1543 CSR_WRITE_4(sc, DC_IMR, 0x00000000); 1544 CSR_WRITE_4(sc, DC_BUSCTL, 0x00000000); 1545 CSR_WRITE_4(sc, DC_NETCFG, 0x00000000); 1546 1547 /* 1548 * Bring the SIA out of reset. In some cases, it looks 1549 * like failing to unreset the SIA soon enough gets it 1550 * into a state where it will never come out of reset 1551 * until we reset the whole chip again. 1552 */ 1553 if (DC_IS_INTEL(sc)) { 1554 DC_SETBIT(sc, DC_SIARESET, DC_SIA_RESET); 1555 CSR_WRITE_4(sc, DC_10BTCTRL, 0); 1556 CSR_WRITE_4(sc, DC_WATCHDOG, 0); 1557 } 1558 } 1559 1560 static struct dc_type * 1561 dc_devtype(device_t dev) 1562 { 1563 struct dc_type *t; 1564 u_int32_t rev; 1565 1566 t = dc_devs; 1567 1568 while (t->dc_name != NULL) { 1569 if ((pci_get_vendor(dev) == t->dc_vid) && 1570 (pci_get_device(dev) == t->dc_did)) { 1571 /* Check the PCI revision */ 1572 rev = pci_read_config(dev, DC_PCI_CFRV, 4) & 0xFF; 1573 if (t->dc_did == DC_DEVICEID_98713 && 1574 rev >= DC_REVISION_98713A) 1575 t++; 1576 if (t->dc_did == DC_DEVICEID_98713_CP && 1577 rev >= DC_REVISION_98713A) 1578 t++; 1579 if (t->dc_did == DC_DEVICEID_987x5 && 1580 rev >= DC_REVISION_98715AEC_C) 1581 t++; 1582 if (t->dc_did == DC_DEVICEID_987x5 && 1583 rev >= DC_REVISION_98725) 1584 t++; 1585 if (t->dc_did == DC_DEVICEID_AX88140A && 1586 rev >= DC_REVISION_88141) 1587 t++; 1588 if (t->dc_did == DC_DEVICEID_82C168 && 1589 rev >= DC_REVISION_82C169) 1590 t++; 1591 if (t->dc_did == DC_DEVICEID_DM9102 && 1592 rev >= DC_REVISION_DM9102A) 1593 t++; 1594 /* 1595 * The Microsoft MN-130 has a device ID of 0x0002, 1596 * which happens to be the same as the PNIC 82c168. 1597 * To keep dc_attach() from getting confused, we 1598 * pretend its ID is something different. 1599 * XXX: ideally, dc_attach() should be checking 1600 * vendorid+deviceid together to avoid such 1601 * collisions. 1602 */ 1603 if (t->dc_vid == DC_VENDORID_MICROSOFT && 1604 t->dc_did == DC_DEVICEID_MSMN130) 1605 t++; 1606 return (t); 1607 } 1608 t++; 1609 } 1610 1611 return (NULL); 1612 } 1613 1614 /* 1615 * Probe for a 21143 or clone chip. Check the PCI vendor and device 1616 * IDs against our list and return a device name if we find a match. 1617 * We do a little bit of extra work to identify the exact type of 1618 * chip. The MX98713 and MX98713A have the same PCI vendor/device ID, 1619 * but different revision IDs. The same is true for 98715/98715A 1620 * chips and the 98725, as well as the ASIX and ADMtek chips. In some 1621 * cases, the exact chip revision affects driver behavior. 1622 */ 1623 static int 1624 dc_probe(device_t dev) 1625 { 1626 struct dc_type *t; 1627 1628 t = dc_devtype(dev); 1629 1630 if (t != NULL) { 1631 device_set_desc(dev, t->dc_name); 1632 return (BUS_PROBE_DEFAULT); 1633 } 1634 1635 return (ENXIO); 1636 } 1637 1638 static void 1639 dc_apply_fixup(struct dc_softc *sc, int media) 1640 { 1641 struct dc_mediainfo *m; 1642 u_int8_t *p; 1643 int i; 1644 u_int32_t reg; 1645 1646 m = sc->dc_mi; 1647 1648 while (m != NULL) { 1649 if (m->dc_media == media) 1650 break; 1651 m = m->dc_next; 1652 } 1653 1654 if (m == NULL) 1655 return; 1656 1657 for (i = 0, p = m->dc_reset_ptr; i < m->dc_reset_len; i++, p += 2) { 1658 reg = (p[0] | (p[1] << 8)) << 16; 1659 CSR_WRITE_4(sc, DC_WATCHDOG, reg); 1660 } 1661 1662 for (i = 0, p = m->dc_gp_ptr; i < m->dc_gp_len; i++, p += 2) { 1663 reg = (p[0] | (p[1] << 8)) << 16; 1664 CSR_WRITE_4(sc, DC_WATCHDOG, reg); 1665 } 1666 } 1667 1668 static void 1669 dc_decode_leaf_sia(struct dc_softc *sc, struct dc_eblock_sia *l) 1670 { 1671 struct dc_mediainfo *m; 1672 1673 m = malloc(sizeof(struct dc_mediainfo), M_DEVBUF, M_NOWAIT | M_ZERO); 1674 switch (l->dc_sia_code & ~DC_SIA_CODE_EXT) { 1675 case DC_SIA_CODE_10BT: 1676 m->dc_media = IFM_10_T; 1677 break; 1678 case DC_SIA_CODE_10BT_FDX: 1679 m->dc_media = IFM_10_T | IFM_FDX; 1680 break; 1681 case DC_SIA_CODE_10B2: 1682 m->dc_media = IFM_10_2; 1683 break; 1684 case DC_SIA_CODE_10B5: 1685 m->dc_media = IFM_10_5; 1686 break; 1687 default: 1688 break; 1689 } 1690 1691 /* 1692 * We need to ignore CSR13, CSR14, CSR15 for SIA mode. 1693 * Things apparently already work for cards that do 1694 * supply Media Specific Data. 1695 */ 1696 if (l->dc_sia_code & DC_SIA_CODE_EXT) { 1697 m->dc_gp_len = 2; 1698 m->dc_gp_ptr = 1699 (u_int8_t *)&l->dc_un.dc_sia_ext.dc_sia_gpio_ctl; 1700 } else { 1701 m->dc_gp_len = 2; 1702 m->dc_gp_ptr = 1703 (u_int8_t *)&l->dc_un.dc_sia_noext.dc_sia_gpio_ctl; 1704 } 1705 1706 m->dc_next = sc->dc_mi; 1707 sc->dc_mi = m; 1708 1709 sc->dc_pmode = DC_PMODE_SIA; 1710 } 1711 1712 static void 1713 dc_decode_leaf_sym(struct dc_softc *sc, struct dc_eblock_sym *l) 1714 { 1715 struct dc_mediainfo *m; 1716 1717 m = malloc(sizeof(struct dc_mediainfo), M_DEVBUF, M_NOWAIT | M_ZERO); 1718 if (l->dc_sym_code == DC_SYM_CODE_100BT) 1719 m->dc_media = IFM_100_TX; 1720 1721 if (l->dc_sym_code == DC_SYM_CODE_100BT_FDX) 1722 m->dc_media = IFM_100_TX | IFM_FDX; 1723 1724 m->dc_gp_len = 2; 1725 m->dc_gp_ptr = (u_int8_t *)&l->dc_sym_gpio_ctl; 1726 1727 m->dc_next = sc->dc_mi; 1728 sc->dc_mi = m; 1729 1730 sc->dc_pmode = DC_PMODE_SYM; 1731 } 1732 1733 static void 1734 dc_decode_leaf_mii(struct dc_softc *sc, struct dc_eblock_mii *l) 1735 { 1736 struct dc_mediainfo *m; 1737 u_int8_t *p; 1738 1739 m = malloc(sizeof(struct dc_mediainfo), M_DEVBUF, M_NOWAIT | M_ZERO); 1740 /* We abuse IFM_AUTO to represent MII. */ 1741 m->dc_media = IFM_AUTO; 1742 m->dc_gp_len = l->dc_gpr_len; 1743 1744 p = (u_int8_t *)l; 1745 p += sizeof(struct dc_eblock_mii); 1746 m->dc_gp_ptr = p; 1747 p += 2 * l->dc_gpr_len; 1748 m->dc_reset_len = *p; 1749 p++; 1750 m->dc_reset_ptr = p; 1751 1752 m->dc_next = sc->dc_mi; 1753 sc->dc_mi = m; 1754 } 1755 1756 static void 1757 dc_read_srom(struct dc_softc *sc, int bits) 1758 { 1759 int size; 1760 1761 size = 2 << bits; 1762 sc->dc_srom = malloc(size, M_DEVBUF, M_NOWAIT); 1763 dc_read_eeprom(sc, (caddr_t)sc->dc_srom, 0, (size / 2), 0); 1764 } 1765 1766 static void 1767 dc_parse_21143_srom(struct dc_softc *sc) 1768 { 1769 struct dc_leaf_hdr *lhdr; 1770 struct dc_eblock_hdr *hdr; 1771 int have_mii, i, loff; 1772 char *ptr; 1773 1774 have_mii = 0; 1775 loff = sc->dc_srom[27]; 1776 lhdr = (struct dc_leaf_hdr *)&(sc->dc_srom[loff]); 1777 1778 ptr = (char *)lhdr; 1779 ptr += sizeof(struct dc_leaf_hdr) - 1; 1780 /* 1781 * Look if we got a MII media block. 1782 */ 1783 for (i = 0; i < lhdr->dc_mcnt; i++) { 1784 hdr = (struct dc_eblock_hdr *)ptr; 1785 if (hdr->dc_type == DC_EBLOCK_MII) 1786 have_mii++; 1787 1788 ptr += (hdr->dc_len & 0x7F); 1789 ptr++; 1790 } 1791 1792 /* 1793 * Do the same thing again. Only use SIA and SYM media 1794 * blocks if no MII media block is available. 1795 */ 1796 ptr = (char *)lhdr; 1797 ptr += sizeof(struct dc_leaf_hdr) - 1; 1798 for (i = 0; i < lhdr->dc_mcnt; i++) { 1799 hdr = (struct dc_eblock_hdr *)ptr; 1800 switch (hdr->dc_type) { 1801 case DC_EBLOCK_MII: 1802 dc_decode_leaf_mii(sc, (struct dc_eblock_mii *)hdr); 1803 break; 1804 case DC_EBLOCK_SIA: 1805 if (! have_mii) 1806 dc_decode_leaf_sia(sc, 1807 (struct dc_eblock_sia *)hdr); 1808 break; 1809 case DC_EBLOCK_SYM: 1810 if (! have_mii) 1811 dc_decode_leaf_sym(sc, 1812 (struct dc_eblock_sym *)hdr); 1813 break; 1814 default: 1815 /* Don't care. Yet. */ 1816 break; 1817 } 1818 ptr += (hdr->dc_len & 0x7F); 1819 ptr++; 1820 } 1821 } 1822 1823 static void 1824 dc_dma_map_addr(void *arg, bus_dma_segment_t *segs, int nseg, int error) 1825 { 1826 u_int32_t *paddr; 1827 1828 KASSERT(nseg == 1, ("wrong number of segments, should be 1")); 1829 paddr = arg; 1830 *paddr = segs->ds_addr; 1831 } 1832 1833 /* 1834 * Attach the interface. Allocate softc structures, do ifmedia 1835 * setup and ethernet/BPF attach. 1836 */ 1837 static int 1838 dc_attach(device_t dev) 1839 { 1840 int tmp = 0; 1841 uint32_t eaddr[(ETHER_ADDR_LEN+3)/4]; 1842 u_int32_t command; 1843 struct dc_softc *sc; 1844 struct ifnet *ifp; 1845 u_int32_t revision; 1846 int error = 0, rid, mac_offset; 1847 int i; 1848 u_int8_t *mac; 1849 1850 sc = device_get_softc(dev); 1851 1852 mtx_init(&sc->dc_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 1853 MTX_DEF); 1854 1855 /* 1856 * Map control/status registers. 1857 */ 1858 pci_enable_busmaster(dev); 1859 1860 rid = DC_RID; 1861 sc->dc_res = bus_alloc_resource_any(dev, DC_RES, &rid, RF_ACTIVE); 1862 1863 if (sc->dc_res == NULL) { 1864 device_printf(dev, "couldn't map ports/memory\n"); 1865 error = ENXIO; 1866 goto fail; 1867 } 1868 1869 sc->dc_btag = rman_get_bustag(sc->dc_res); 1870 sc->dc_bhandle = rman_get_bushandle(sc->dc_res); 1871 1872 /* Allocate interrupt. */ 1873 rid = 0; 1874 sc->dc_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 1875 RF_SHAREABLE | RF_ACTIVE); 1876 1877 if (sc->dc_irq == NULL) { 1878 device_printf(dev, "couldn't map interrupt\n"); 1879 error = ENXIO; 1880 goto fail; 1881 } 1882 1883 /* Need this info to decide on a chip type. */ 1884 sc->dc_info = dc_devtype(dev); 1885 revision = pci_read_config(dev, DC_PCI_CFRV, 4) & 0x000000FF; 1886 1887 /* Get the eeprom width, but PNIC and XIRCOM have diff eeprom */ 1888 if (sc->dc_info->dc_did != DC_DEVICEID_82C168 && 1889 sc->dc_info->dc_did != DC_DEVICEID_X3201) 1890 dc_eeprom_width(sc); 1891 1892 switch (sc->dc_info->dc_did) { 1893 case DC_DEVICEID_21143: 1894 sc->dc_type = DC_TYPE_21143; 1895 sc->dc_flags |= DC_TX_POLL | DC_TX_USE_TX_INTR; 1896 sc->dc_flags |= DC_REDUCED_MII_POLL; 1897 /* Save EEPROM contents so we can parse them later. */ 1898 dc_read_srom(sc, sc->dc_romwidth); 1899 break; 1900 case DC_DEVICEID_DM9009: 1901 case DC_DEVICEID_DM9100: 1902 case DC_DEVICEID_DM9102: 1903 sc->dc_type = DC_TYPE_DM9102; 1904 sc->dc_flags |= DC_TX_COALESCE | DC_TX_INTR_ALWAYS; 1905 sc->dc_flags |= DC_REDUCED_MII_POLL | DC_TX_STORENFWD; 1906 sc->dc_flags |= DC_TX_ALIGN; 1907 sc->dc_pmode = DC_PMODE_MII; 1908 /* Increase the latency timer value. */ 1909 command = pci_read_config(dev, DC_PCI_CFLT, 4); 1910 command &= 0xFFFF00FF; 1911 command |= 0x00008000; 1912 pci_write_config(dev, DC_PCI_CFLT, command, 4); 1913 break; 1914 case DC_DEVICEID_AL981: 1915 sc->dc_type = DC_TYPE_AL981; 1916 sc->dc_flags |= DC_TX_USE_TX_INTR; 1917 sc->dc_flags |= DC_TX_ADMTEK_WAR; 1918 sc->dc_pmode = DC_PMODE_MII; 1919 dc_read_srom(sc, sc->dc_romwidth); 1920 break; 1921 case DC_DEVICEID_AN985: 1922 case DC_DEVICEID_ADM9511: 1923 case DC_DEVICEID_ADM9513: 1924 case DC_DEVICEID_FA511: 1925 case DC_DEVICEID_FE2500: 1926 case DC_DEVICEID_EN2242: 1927 case DC_DEVICEID_HAWKING_PN672TX: 1928 case DC_DEVICEID_3CSOHOB: 1929 case DC_DEVICEID_MSMN120: 1930 case DC_DEVICEID_MSMN130_FAKE: /* XXX avoid collision with PNIC*/ 1931 sc->dc_type = DC_TYPE_AN985; 1932 sc->dc_flags |= DC_64BIT_HASH; 1933 sc->dc_flags |= DC_TX_USE_TX_INTR; 1934 sc->dc_flags |= DC_TX_ADMTEK_WAR; 1935 sc->dc_pmode = DC_PMODE_MII; 1936 /* Don't read SROM for - auto-loaded on reset */ 1937 break; 1938 case DC_DEVICEID_98713: 1939 case DC_DEVICEID_98713_CP: 1940 if (revision < DC_REVISION_98713A) { 1941 sc->dc_type = DC_TYPE_98713; 1942 } 1943 if (revision >= DC_REVISION_98713A) { 1944 sc->dc_type = DC_TYPE_98713A; 1945 sc->dc_flags |= DC_21143_NWAY; 1946 } 1947 sc->dc_flags |= DC_REDUCED_MII_POLL; 1948 sc->dc_flags |= DC_TX_POLL | DC_TX_USE_TX_INTR; 1949 break; 1950 case DC_DEVICEID_987x5: 1951 case DC_DEVICEID_EN1217: 1952 /* 1953 * Macronix MX98715AEC-C/D/E parts have only a 1954 * 128-bit hash table. We need to deal with these 1955 * in the same manner as the PNIC II so that we 1956 * get the right number of bits out of the 1957 * CRC routine. 1958 */ 1959 if (revision >= DC_REVISION_98715AEC_C && 1960 revision < DC_REVISION_98725) 1961 sc->dc_flags |= DC_128BIT_HASH; 1962 sc->dc_type = DC_TYPE_987x5; 1963 sc->dc_flags |= DC_TX_POLL | DC_TX_USE_TX_INTR; 1964 sc->dc_flags |= DC_REDUCED_MII_POLL | DC_21143_NWAY; 1965 break; 1966 case DC_DEVICEID_98727: 1967 sc->dc_type = DC_TYPE_987x5; 1968 sc->dc_flags |= DC_TX_POLL | DC_TX_USE_TX_INTR; 1969 sc->dc_flags |= DC_REDUCED_MII_POLL | DC_21143_NWAY; 1970 break; 1971 case DC_DEVICEID_82C115: 1972 sc->dc_type = DC_TYPE_PNICII; 1973 sc->dc_flags |= DC_TX_POLL | DC_TX_USE_TX_INTR | DC_128BIT_HASH; 1974 sc->dc_flags |= DC_REDUCED_MII_POLL | DC_21143_NWAY; 1975 break; 1976 case DC_DEVICEID_82C168: 1977 sc->dc_type = DC_TYPE_PNIC; 1978 sc->dc_flags |= DC_TX_STORENFWD | DC_TX_INTR_ALWAYS; 1979 sc->dc_flags |= DC_PNIC_RX_BUG_WAR; 1980 sc->dc_pnic_rx_buf = malloc(DC_RXLEN * 5, M_DEVBUF, M_NOWAIT); 1981 if (revision < DC_REVISION_82C169) 1982 sc->dc_pmode = DC_PMODE_SYM; 1983 break; 1984 case DC_DEVICEID_AX88140A: 1985 sc->dc_type = DC_TYPE_ASIX; 1986 sc->dc_flags |= DC_TX_USE_TX_INTR | DC_TX_INTR_FIRSTFRAG; 1987 sc->dc_flags |= DC_REDUCED_MII_POLL; 1988 sc->dc_pmode = DC_PMODE_MII; 1989 break; 1990 case DC_DEVICEID_X3201: 1991 sc->dc_type = DC_TYPE_XIRCOM; 1992 sc->dc_flags |= DC_TX_INTR_ALWAYS | DC_TX_COALESCE | 1993 DC_TX_ALIGN; 1994 /* 1995 * We don't actually need to coalesce, but we're doing 1996 * it to obtain a double word aligned buffer. 1997 * The DC_TX_COALESCE flag is required. 1998 */ 1999 sc->dc_pmode = DC_PMODE_MII; 2000 break; 2001 case DC_DEVICEID_RS7112: 2002 sc->dc_type = DC_TYPE_CONEXANT; 2003 sc->dc_flags |= DC_TX_INTR_ALWAYS; 2004 sc->dc_flags |= DC_REDUCED_MII_POLL; 2005 sc->dc_pmode = DC_PMODE_MII; 2006 dc_read_srom(sc, sc->dc_romwidth); 2007 break; 2008 default: 2009 device_printf(dev, "unknown device: %x\n", sc->dc_info->dc_did); 2010 break; 2011 } 2012 2013 /* Save the cache line size. */ 2014 if (DC_IS_DAVICOM(sc)) 2015 sc->dc_cachesize = 0; 2016 else 2017 sc->dc_cachesize = pci_read_config(dev, 2018 DC_PCI_CFLT, 4) & 0xFF; 2019 2020 /* Reset the adapter. */ 2021 dc_reset(sc); 2022 2023 /* Take 21143 out of snooze mode */ 2024 if (DC_IS_INTEL(sc) || DC_IS_XIRCOM(sc)) { 2025 command = pci_read_config(dev, DC_PCI_CFDD, 4); 2026 command &= ~(DC_CFDD_SNOOZE_MODE | DC_CFDD_SLEEP_MODE); 2027 pci_write_config(dev, DC_PCI_CFDD, command, 4); 2028 } 2029 2030 /* 2031 * Try to learn something about the supported media. 2032 * We know that ASIX and ADMtek and Davicom devices 2033 * will *always* be using MII media, so that's a no-brainer. 2034 * The tricky ones are the Macronix/PNIC II and the 2035 * Intel 21143. 2036 */ 2037 if (DC_IS_INTEL(sc)) 2038 dc_parse_21143_srom(sc); 2039 else if (DC_IS_MACRONIX(sc) || DC_IS_PNICII(sc)) { 2040 if (sc->dc_type == DC_TYPE_98713) 2041 sc->dc_pmode = DC_PMODE_MII; 2042 else 2043 sc->dc_pmode = DC_PMODE_SYM; 2044 } else if (!sc->dc_pmode) 2045 sc->dc_pmode = DC_PMODE_MII; 2046 2047 /* 2048 * Get station address from the EEPROM. 2049 */ 2050 switch(sc->dc_type) { 2051 case DC_TYPE_98713: 2052 case DC_TYPE_98713A: 2053 case DC_TYPE_987x5: 2054 case DC_TYPE_PNICII: 2055 dc_read_eeprom(sc, (caddr_t)&mac_offset, 2056 (DC_EE_NODEADDR_OFFSET / 2), 1, 0); 2057 dc_read_eeprom(sc, (caddr_t)&eaddr, (mac_offset / 2), 3, 0); 2058 break; 2059 case DC_TYPE_PNIC: 2060 dc_read_eeprom(sc, (caddr_t)&eaddr, 0, 3, 1); 2061 break; 2062 case DC_TYPE_DM9102: 2063 dc_read_eeprom(sc, (caddr_t)&eaddr, DC_EE_NODEADDR, 3, 0); 2064 #ifdef __sparc64__ 2065 /* 2066 * If this is an onboard dc(4) the station address read from 2067 * the EEPROM is all zero and we have to get it from the FCode. 2068 */ 2069 if (eaddr[0] == 0 && (eaddr[1] & ~0xffff) == 0) 2070 OF_getetheraddr(dev, (caddr_t)&eaddr); 2071 #endif 2072 break; 2073 case DC_TYPE_21143: 2074 case DC_TYPE_ASIX: 2075 dc_read_eeprom(sc, (caddr_t)&eaddr, DC_EE_NODEADDR, 3, 0); 2076 break; 2077 case DC_TYPE_AL981: 2078 case DC_TYPE_AN985: 2079 eaddr[0] = CSR_READ_4(sc, DC_AL_PAR0); 2080 eaddr[1] = CSR_READ_4(sc, DC_AL_PAR1); 2081 break; 2082 case DC_TYPE_CONEXANT: 2083 bcopy(sc->dc_srom + DC_CONEXANT_EE_NODEADDR, &eaddr, 2084 ETHER_ADDR_LEN); 2085 break; 2086 case DC_TYPE_XIRCOM: 2087 /* The MAC comes from the CIS. */ 2088 mac = pci_get_ether(dev); 2089 if (!mac) { 2090 device_printf(dev, "No station address in CIS!\n"); 2091 error = ENXIO; 2092 goto fail; 2093 } 2094 bcopy(mac, eaddr, ETHER_ADDR_LEN); 2095 break; 2096 default: 2097 dc_read_eeprom(sc, (caddr_t)&eaddr, DC_EE_NODEADDR, 3, 0); 2098 break; 2099 } 2100 2101 /* Allocate a busdma tag and DMA safe memory for TX/RX descriptors. */ 2102 error = bus_dma_tag_create(NULL, PAGE_SIZE, 0, BUS_SPACE_MAXADDR_32BIT, 2103 BUS_SPACE_MAXADDR, NULL, NULL, sizeof(struct dc_list_data), 1, 2104 sizeof(struct dc_list_data), 0, NULL, NULL, &sc->dc_ltag); 2105 if (error) { 2106 device_printf(dev, "failed to allocate busdma tag\n"); 2107 error = ENXIO; 2108 goto fail; 2109 } 2110 error = bus_dmamem_alloc(sc->dc_ltag, (void **)&sc->dc_ldata, 2111 BUS_DMA_NOWAIT | BUS_DMA_ZERO, &sc->dc_lmap); 2112 if (error) { 2113 device_printf(dev, "failed to allocate DMA safe memory\n"); 2114 error = ENXIO; 2115 goto fail; 2116 } 2117 error = bus_dmamap_load(sc->dc_ltag, sc->dc_lmap, sc->dc_ldata, 2118 sizeof(struct dc_list_data), dc_dma_map_addr, &sc->dc_laddr, 2119 BUS_DMA_NOWAIT); 2120 if (error) { 2121 device_printf(dev, "cannot get address of the descriptors\n"); 2122 error = ENXIO; 2123 goto fail; 2124 } 2125 2126 /* 2127 * Allocate a busdma tag and DMA safe memory for the multicast 2128 * setup frame. 2129 */ 2130 error = bus_dma_tag_create(NULL, PAGE_SIZE, 0, BUS_SPACE_MAXADDR_32BIT, 2131 BUS_SPACE_MAXADDR, NULL, NULL, DC_SFRAME_LEN + DC_MIN_FRAMELEN, 1, 2132 DC_SFRAME_LEN + DC_MIN_FRAMELEN, 0, NULL, NULL, &sc->dc_stag); 2133 if (error) { 2134 device_printf(dev, "failed to allocate busdma tag\n"); 2135 error = ENXIO; 2136 goto fail; 2137 } 2138 error = bus_dmamem_alloc(sc->dc_stag, (void **)&sc->dc_cdata.dc_sbuf, 2139 BUS_DMA_NOWAIT, &sc->dc_smap); 2140 if (error) { 2141 device_printf(dev, "failed to allocate DMA safe memory\n"); 2142 error = ENXIO; 2143 goto fail; 2144 } 2145 error = bus_dmamap_load(sc->dc_stag, sc->dc_smap, sc->dc_cdata.dc_sbuf, 2146 DC_SFRAME_LEN, dc_dma_map_addr, &sc->dc_saddr, BUS_DMA_NOWAIT); 2147 if (error) { 2148 device_printf(dev, "cannot get address of the descriptors\n"); 2149 error = ENXIO; 2150 goto fail; 2151 } 2152 2153 /* Allocate a busdma tag for mbufs. */ 2154 error = bus_dma_tag_create(NULL, 1, 0, BUS_SPACE_MAXADDR_32BIT, 2155 BUS_SPACE_MAXADDR, NULL, NULL, MCLBYTES, DC_TX_LIST_CNT, MCLBYTES, 2156 0, NULL, NULL, &sc->dc_mtag); 2157 if (error) { 2158 device_printf(dev, "failed to allocate busdma tag\n"); 2159 error = ENXIO; 2160 goto fail; 2161 } 2162 2163 /* Create the TX/RX busdma maps. */ 2164 for (i = 0; i < DC_TX_LIST_CNT; i++) { 2165 error = bus_dmamap_create(sc->dc_mtag, 0, 2166 &sc->dc_cdata.dc_tx_map[i]); 2167 if (error) { 2168 device_printf(dev, "failed to init TX ring\n"); 2169 error = ENXIO; 2170 goto fail; 2171 } 2172 } 2173 for (i = 0; i < DC_RX_LIST_CNT; i++) { 2174 error = bus_dmamap_create(sc->dc_mtag, 0, 2175 &sc->dc_cdata.dc_rx_map[i]); 2176 if (error) { 2177 device_printf(dev, "failed to init RX ring\n"); 2178 error = ENXIO; 2179 goto fail; 2180 } 2181 } 2182 error = bus_dmamap_create(sc->dc_mtag, 0, &sc->dc_sparemap); 2183 if (error) { 2184 device_printf(dev, "failed to init RX ring\n"); 2185 error = ENXIO; 2186 goto fail; 2187 } 2188 2189 ifp = sc->dc_ifp = if_alloc(IFT_ETHER); 2190 if (ifp == NULL) { 2191 device_printf(dev, "can not if_alloc()\n"); 2192 error = ENOSPC; 2193 goto fail; 2194 } 2195 ifp->if_softc = sc; 2196 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 2197 /* XXX: bleah, MTU gets overwritten in ether_ifattach() */ 2198 ifp->if_mtu = ETHERMTU; 2199 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 2200 ifp->if_ioctl = dc_ioctl; 2201 ifp->if_start = dc_start; 2202 ifp->if_watchdog = dc_watchdog; 2203 ifp->if_init = dc_init; 2204 ifp->if_baudrate = 10000000; 2205 IFQ_SET_MAXLEN(&ifp->if_snd, DC_TX_LIST_CNT - 1); 2206 ifp->if_snd.ifq_drv_maxlen = DC_TX_LIST_CNT - 1; 2207 IFQ_SET_READY(&ifp->if_snd); 2208 2209 /* 2210 * Do MII setup. If this is a 21143, check for a PHY on the 2211 * MII bus after applying any necessary fixups to twiddle the 2212 * GPIO bits. If we don't end up finding a PHY, restore the 2213 * old selection (SIA only or SIA/SYM) and attach the dcphy 2214 * driver instead. 2215 */ 2216 if (DC_IS_INTEL(sc)) { 2217 dc_apply_fixup(sc, IFM_AUTO); 2218 tmp = sc->dc_pmode; 2219 sc->dc_pmode = DC_PMODE_MII; 2220 } 2221 2222 /* 2223 * Setup General Purpose port mode and data so the tulip can talk 2224 * to the MII. This needs to be done before mii_phy_probe so that 2225 * we can actually see them. 2226 */ 2227 if (DC_IS_XIRCOM(sc)) { 2228 CSR_WRITE_4(sc, DC_SIAGP, DC_SIAGP_WRITE_EN | DC_SIAGP_INT1_EN | 2229 DC_SIAGP_MD_GP2_OUTPUT | DC_SIAGP_MD_GP0_OUTPUT); 2230 DELAY(10); 2231 CSR_WRITE_4(sc, DC_SIAGP, DC_SIAGP_INT1_EN | 2232 DC_SIAGP_MD_GP2_OUTPUT | DC_SIAGP_MD_GP0_OUTPUT); 2233 DELAY(10); 2234 } 2235 2236 error = mii_phy_probe(dev, &sc->dc_miibus, 2237 dc_ifmedia_upd, dc_ifmedia_sts); 2238 2239 if (error && DC_IS_INTEL(sc)) { 2240 sc->dc_pmode = tmp; 2241 if (sc->dc_pmode != DC_PMODE_SIA) 2242 sc->dc_pmode = DC_PMODE_SYM; 2243 sc->dc_flags |= DC_21143_NWAY; 2244 mii_phy_probe(dev, &sc->dc_miibus, 2245 dc_ifmedia_upd, dc_ifmedia_sts); 2246 /* 2247 * For non-MII cards, we need to have the 21143 2248 * drive the LEDs. Except there are some systems 2249 * like the NEC VersaPro NoteBook PC which have no 2250 * LEDs, and twiddling these bits has adverse effects 2251 * on them. (I.e. you suddenly can't get a link.) 2252 */ 2253 if (pci_read_config(dev, DC_PCI_CSID, 4) != 0x80281033) 2254 sc->dc_flags |= DC_TULIP_LEDS; 2255 error = 0; 2256 } 2257 2258 if (error) { 2259 device_printf(dev, "MII without any PHY!\n"); 2260 goto fail; 2261 } 2262 2263 if (DC_IS_ADMTEK(sc)) { 2264 /* 2265 * Set automatic TX underrun recovery for the ADMtek chips 2266 */ 2267 DC_SETBIT(sc, DC_AL_CR, DC_AL_CR_ATUR); 2268 } 2269 2270 /* 2271 * Tell the upper layer(s) we support long frames. 2272 */ 2273 ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header); 2274 ifp->if_capabilities |= IFCAP_VLAN_MTU; 2275 ifp->if_capenable = ifp->if_capabilities; 2276 #ifdef DEVICE_POLLING 2277 ifp->if_capabilities |= IFCAP_POLLING; 2278 #endif 2279 2280 callout_init_mtx(&sc->dc_stat_ch, &sc->dc_mtx, 0); 2281 2282 #ifdef SRM_MEDIA 2283 sc->dc_srm_media = 0; 2284 2285 /* Remember the SRM console media setting */ 2286 if (DC_IS_INTEL(sc)) { 2287 command = pci_read_config(dev, DC_PCI_CFDD, 4); 2288 command &= ~(DC_CFDD_SNOOZE_MODE | DC_CFDD_SLEEP_MODE); 2289 switch ((command >> 8) & 0xff) { 2290 case 3: 2291 sc->dc_srm_media = IFM_10_T; 2292 break; 2293 case 4: 2294 sc->dc_srm_media = IFM_10_T | IFM_FDX; 2295 break; 2296 case 5: 2297 sc->dc_srm_media = IFM_100_TX; 2298 break; 2299 case 6: 2300 sc->dc_srm_media = IFM_100_TX | IFM_FDX; 2301 break; 2302 } 2303 if (sc->dc_srm_media) 2304 sc->dc_srm_media |= IFM_ACTIVE | IFM_ETHER; 2305 } 2306 #endif 2307 2308 /* 2309 * Call MI attach routine. 2310 */ 2311 ether_ifattach(ifp, (caddr_t)eaddr); 2312 2313 /* Hook interrupt last to avoid having to lock softc */ 2314 error = bus_setup_intr(dev, sc->dc_irq, INTR_TYPE_NET | INTR_MPSAFE, 2315 dc_intr, sc, &sc->dc_intrhand); 2316 2317 if (error) { 2318 device_printf(dev, "couldn't set up irq\n"); 2319 ether_ifdetach(ifp); 2320 goto fail; 2321 } 2322 2323 fail: 2324 if (error) 2325 dc_detach(dev); 2326 return (error); 2327 } 2328 2329 /* 2330 * Shutdown hardware and free up resources. This can be called any 2331 * time after the mutex has been initialized. It is called in both 2332 * the error case in attach and the normal detach case so it needs 2333 * to be careful about only freeing resources that have actually been 2334 * allocated. 2335 */ 2336 static int 2337 dc_detach(device_t dev) 2338 { 2339 struct dc_softc *sc; 2340 struct ifnet *ifp; 2341 struct dc_mediainfo *m; 2342 int i; 2343 2344 sc = device_get_softc(dev); 2345 KASSERT(mtx_initialized(&sc->dc_mtx), ("dc mutex not initialized")); 2346 2347 ifp = sc->dc_ifp; 2348 2349 #ifdef DEVICE_POLLING 2350 if (ifp->if_capenable & IFCAP_POLLING) 2351 ether_poll_deregister(ifp); 2352 #endif 2353 2354 /* These should only be active if attach succeeded */ 2355 if (device_is_attached(dev)) { 2356 DC_LOCK(sc); 2357 dc_stop(sc); 2358 DC_UNLOCK(sc); 2359 callout_drain(&sc->dc_stat_ch); 2360 ether_ifdetach(ifp); 2361 } 2362 if (sc->dc_miibus) 2363 device_delete_child(dev, sc->dc_miibus); 2364 bus_generic_detach(dev); 2365 2366 if (sc->dc_intrhand) 2367 bus_teardown_intr(dev, sc->dc_irq, sc->dc_intrhand); 2368 if (sc->dc_irq) 2369 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->dc_irq); 2370 if (sc->dc_res) 2371 bus_release_resource(dev, DC_RES, DC_RID, sc->dc_res); 2372 2373 if (ifp) 2374 if_free(ifp); 2375 2376 if (sc->dc_cdata.dc_sbuf != NULL) 2377 bus_dmamem_free(sc->dc_stag, sc->dc_cdata.dc_sbuf, sc->dc_smap); 2378 if (sc->dc_ldata != NULL) 2379 bus_dmamem_free(sc->dc_ltag, sc->dc_ldata, sc->dc_lmap); 2380 if (sc->dc_mtag) { 2381 for (i = 0; i < DC_TX_LIST_CNT; i++) 2382 if (sc->dc_cdata.dc_tx_map[i] != NULL) 2383 bus_dmamap_destroy(sc->dc_mtag, 2384 sc->dc_cdata.dc_tx_map[i]); 2385 for (i = 0; i < DC_RX_LIST_CNT; i++) 2386 if (sc->dc_cdata.dc_rx_map[i] != NULL) 2387 bus_dmamap_destroy(sc->dc_mtag, 2388 sc->dc_cdata.dc_rx_map[i]); 2389 bus_dmamap_destroy(sc->dc_mtag, sc->dc_sparemap); 2390 } 2391 if (sc->dc_stag) 2392 bus_dma_tag_destroy(sc->dc_stag); 2393 if (sc->dc_mtag) 2394 bus_dma_tag_destroy(sc->dc_mtag); 2395 if (sc->dc_ltag) 2396 bus_dma_tag_destroy(sc->dc_ltag); 2397 2398 free(sc->dc_pnic_rx_buf, M_DEVBUF); 2399 2400 while (sc->dc_mi != NULL) { 2401 m = sc->dc_mi->dc_next; 2402 free(sc->dc_mi, M_DEVBUF); 2403 sc->dc_mi = m; 2404 } 2405 free(sc->dc_srom, M_DEVBUF); 2406 2407 mtx_destroy(&sc->dc_mtx); 2408 2409 return (0); 2410 } 2411 2412 /* 2413 * Initialize the transmit descriptors. 2414 */ 2415 static int 2416 dc_list_tx_init(struct dc_softc *sc) 2417 { 2418 struct dc_chain_data *cd; 2419 struct dc_list_data *ld; 2420 int i, nexti; 2421 2422 cd = &sc->dc_cdata; 2423 ld = sc->dc_ldata; 2424 for (i = 0; i < DC_TX_LIST_CNT; i++) { 2425 if (i == DC_TX_LIST_CNT - 1) 2426 nexti = 0; 2427 else 2428 nexti = i + 1; 2429 ld->dc_tx_list[i].dc_next = htole32(DC_TXDESC(sc, nexti)); 2430 cd->dc_tx_chain[i] = NULL; 2431 ld->dc_tx_list[i].dc_data = 0; 2432 ld->dc_tx_list[i].dc_ctl = 0; 2433 } 2434 2435 cd->dc_tx_prod = cd->dc_tx_cons = cd->dc_tx_cnt = 0; 2436 bus_dmamap_sync(sc->dc_ltag, sc->dc_lmap, 2437 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2438 return (0); 2439 } 2440 2441 2442 /* 2443 * Initialize the RX descriptors and allocate mbufs for them. Note that 2444 * we arrange the descriptors in a closed ring, so that the last descriptor 2445 * points back to the first. 2446 */ 2447 static int 2448 dc_list_rx_init(struct dc_softc *sc) 2449 { 2450 struct dc_chain_data *cd; 2451 struct dc_list_data *ld; 2452 int i, nexti; 2453 2454 cd = &sc->dc_cdata; 2455 ld = sc->dc_ldata; 2456 2457 for (i = 0; i < DC_RX_LIST_CNT; i++) { 2458 if (dc_newbuf(sc, i, 1) != 0) 2459 return (ENOBUFS); 2460 if (i == DC_RX_LIST_CNT - 1) 2461 nexti = 0; 2462 else 2463 nexti = i + 1; 2464 ld->dc_rx_list[i].dc_next = htole32(DC_RXDESC(sc, nexti)); 2465 } 2466 2467 cd->dc_rx_prod = 0; 2468 bus_dmamap_sync(sc->dc_ltag, sc->dc_lmap, 2469 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2470 return (0); 2471 } 2472 2473 static void 2474 dc_dma_map_rxbuf(arg, segs, nseg, mapsize, error) 2475 void *arg; 2476 bus_dma_segment_t *segs; 2477 int nseg; 2478 bus_size_t mapsize; 2479 int error; 2480 { 2481 struct dc_softc *sc; 2482 struct dc_desc *c; 2483 2484 sc = arg; 2485 c = &sc->dc_ldata->dc_rx_list[sc->dc_cdata.dc_rx_cur]; 2486 if (error) { 2487 sc->dc_cdata.dc_rx_err = error; 2488 return; 2489 } 2490 2491 KASSERT(nseg == 1, ("wrong number of segments, should be 1")); 2492 sc->dc_cdata.dc_rx_err = 0; 2493 c->dc_data = htole32(segs->ds_addr); 2494 } 2495 2496 /* 2497 * Initialize an RX descriptor and attach an MBUF cluster. 2498 */ 2499 static int 2500 dc_newbuf(struct dc_softc *sc, int i, int alloc) 2501 { 2502 struct mbuf *m_new; 2503 bus_dmamap_t tmp; 2504 int error; 2505 2506 if (alloc) { 2507 m_new = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR); 2508 if (m_new == NULL) 2509 return (ENOBUFS); 2510 } else { 2511 m_new = sc->dc_cdata.dc_rx_chain[i]; 2512 m_new->m_data = m_new->m_ext.ext_buf; 2513 } 2514 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 2515 m_adj(m_new, sizeof(u_int64_t)); 2516 2517 /* 2518 * If this is a PNIC chip, zero the buffer. This is part 2519 * of the workaround for the receive bug in the 82c168 and 2520 * 82c169 chips. 2521 */ 2522 if (sc->dc_flags & DC_PNIC_RX_BUG_WAR) 2523 bzero(mtod(m_new, char *), m_new->m_len); 2524 2525 /* No need to remap the mbuf if we're reusing it. */ 2526 if (alloc) { 2527 sc->dc_cdata.dc_rx_cur = i; 2528 error = bus_dmamap_load_mbuf(sc->dc_mtag, sc->dc_sparemap, 2529 m_new, dc_dma_map_rxbuf, sc, 0); 2530 if (error) { 2531 m_freem(m_new); 2532 return (error); 2533 } 2534 if (sc->dc_cdata.dc_rx_err != 0) { 2535 m_freem(m_new); 2536 return (sc->dc_cdata.dc_rx_err); 2537 } 2538 bus_dmamap_unload(sc->dc_mtag, sc->dc_cdata.dc_rx_map[i]); 2539 tmp = sc->dc_cdata.dc_rx_map[i]; 2540 sc->dc_cdata.dc_rx_map[i] = sc->dc_sparemap; 2541 sc->dc_sparemap = tmp; 2542 sc->dc_cdata.dc_rx_chain[i] = m_new; 2543 } 2544 2545 sc->dc_ldata->dc_rx_list[i].dc_ctl = htole32(DC_RXCTL_RLINK | DC_RXLEN); 2546 sc->dc_ldata->dc_rx_list[i].dc_status = htole32(DC_RXSTAT_OWN); 2547 bus_dmamap_sync(sc->dc_mtag, sc->dc_cdata.dc_rx_map[i], 2548 BUS_DMASYNC_PREREAD); 2549 bus_dmamap_sync(sc->dc_ltag, sc->dc_lmap, 2550 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2551 return (0); 2552 } 2553 2554 /* 2555 * Grrrrr. 2556 * The PNIC chip has a terrible bug in it that manifests itself during 2557 * periods of heavy activity. The exact mode of failure if difficult to 2558 * pinpoint: sometimes it only happens in promiscuous mode, sometimes it 2559 * will happen on slow machines. The bug is that sometimes instead of 2560 * uploading one complete frame during reception, it uploads what looks 2561 * like the entire contents of its FIFO memory. The frame we want is at 2562 * the end of the whole mess, but we never know exactly how much data has 2563 * been uploaded, so salvaging the frame is hard. 2564 * 2565 * There is only one way to do it reliably, and it's disgusting. 2566 * Here's what we know: 2567 * 2568 * - We know there will always be somewhere between one and three extra 2569 * descriptors uploaded. 2570 * 2571 * - We know the desired received frame will always be at the end of the 2572 * total data upload. 2573 * 2574 * - We know the size of the desired received frame because it will be 2575 * provided in the length field of the status word in the last descriptor. 2576 * 2577 * Here's what we do: 2578 * 2579 * - When we allocate buffers for the receive ring, we bzero() them. 2580 * This means that we know that the buffer contents should be all 2581 * zeros, except for data uploaded by the chip. 2582 * 2583 * - We also force the PNIC chip to upload frames that include the 2584 * ethernet CRC at the end. 2585 * 2586 * - We gather all of the bogus frame data into a single buffer. 2587 * 2588 * - We then position a pointer at the end of this buffer and scan 2589 * backwards until we encounter the first non-zero byte of data. 2590 * This is the end of the received frame. We know we will encounter 2591 * some data at the end of the frame because the CRC will always be 2592 * there, so even if the sender transmits a packet of all zeros, 2593 * we won't be fooled. 2594 * 2595 * - We know the size of the actual received frame, so we subtract 2596 * that value from the current pointer location. This brings us 2597 * to the start of the actual received packet. 2598 * 2599 * - We copy this into an mbuf and pass it on, along with the actual 2600 * frame length. 2601 * 2602 * The performance hit is tremendous, but it beats dropping frames all 2603 * the time. 2604 */ 2605 2606 #define DC_WHOLEFRAME (DC_RXSTAT_FIRSTFRAG | DC_RXSTAT_LASTFRAG) 2607 static void 2608 dc_pnic_rx_bug_war(struct dc_softc *sc, int idx) 2609 { 2610 struct dc_desc *cur_rx; 2611 struct dc_desc *c = NULL; 2612 struct mbuf *m = NULL; 2613 unsigned char *ptr; 2614 int i, total_len; 2615 u_int32_t rxstat = 0; 2616 2617 i = sc->dc_pnic_rx_bug_save; 2618 cur_rx = &sc->dc_ldata->dc_rx_list[idx]; 2619 ptr = sc->dc_pnic_rx_buf; 2620 bzero(ptr, DC_RXLEN * 5); 2621 2622 /* Copy all the bytes from the bogus buffers. */ 2623 while (1) { 2624 c = &sc->dc_ldata->dc_rx_list[i]; 2625 rxstat = le32toh(c->dc_status); 2626 m = sc->dc_cdata.dc_rx_chain[i]; 2627 bcopy(mtod(m, char *), ptr, DC_RXLEN); 2628 ptr += DC_RXLEN; 2629 /* If this is the last buffer, break out. */ 2630 if (i == idx || rxstat & DC_RXSTAT_LASTFRAG) 2631 break; 2632 dc_newbuf(sc, i, 0); 2633 DC_INC(i, DC_RX_LIST_CNT); 2634 } 2635 2636 /* Find the length of the actual receive frame. */ 2637 total_len = DC_RXBYTES(rxstat); 2638 2639 /* Scan backwards until we hit a non-zero byte. */ 2640 while (*ptr == 0x00) 2641 ptr--; 2642 2643 /* Round off. */ 2644 if ((uintptr_t)(ptr) & 0x3) 2645 ptr -= 1; 2646 2647 /* Now find the start of the frame. */ 2648 ptr -= total_len; 2649 if (ptr < sc->dc_pnic_rx_buf) 2650 ptr = sc->dc_pnic_rx_buf; 2651 2652 /* 2653 * Now copy the salvaged frame to the last mbuf and fake up 2654 * the status word to make it look like a successful 2655 * frame reception. 2656 */ 2657 dc_newbuf(sc, i, 0); 2658 bcopy(ptr, mtod(m, char *), total_len); 2659 cur_rx->dc_status = htole32(rxstat | DC_RXSTAT_FIRSTFRAG); 2660 } 2661 2662 /* 2663 * This routine searches the RX ring for dirty descriptors in the 2664 * event that the rxeof routine falls out of sync with the chip's 2665 * current descriptor pointer. This may happen sometimes as a result 2666 * of a "no RX buffer available" condition that happens when the chip 2667 * consumes all of the RX buffers before the driver has a chance to 2668 * process the RX ring. This routine may need to be called more than 2669 * once to bring the driver back in sync with the chip, however we 2670 * should still be getting RX DONE interrupts to drive the search 2671 * for new packets in the RX ring, so we should catch up eventually. 2672 */ 2673 static int 2674 dc_rx_resync(struct dc_softc *sc) 2675 { 2676 struct dc_desc *cur_rx; 2677 int i, pos; 2678 2679 pos = sc->dc_cdata.dc_rx_prod; 2680 2681 for (i = 0; i < DC_RX_LIST_CNT; i++) { 2682 cur_rx = &sc->dc_ldata->dc_rx_list[pos]; 2683 if (!(le32toh(cur_rx->dc_status) & DC_RXSTAT_OWN)) 2684 break; 2685 DC_INC(pos, DC_RX_LIST_CNT); 2686 } 2687 2688 /* If the ring really is empty, then just return. */ 2689 if (i == DC_RX_LIST_CNT) 2690 return (0); 2691 2692 /* We've fallen behing the chip: catch it. */ 2693 sc->dc_cdata.dc_rx_prod = pos; 2694 2695 return (EAGAIN); 2696 } 2697 2698 /* 2699 * A frame has been uploaded: pass the resulting mbuf chain up to 2700 * the higher level protocols. 2701 */ 2702 static void 2703 dc_rxeof(struct dc_softc *sc) 2704 { 2705 struct mbuf *m; 2706 struct ifnet *ifp; 2707 struct dc_desc *cur_rx; 2708 int i, total_len = 0; 2709 u_int32_t rxstat; 2710 2711 DC_LOCK_ASSERT(sc); 2712 2713 ifp = sc->dc_ifp; 2714 i = sc->dc_cdata.dc_rx_prod; 2715 2716 bus_dmamap_sync(sc->dc_ltag, sc->dc_lmap, BUS_DMASYNC_POSTREAD); 2717 while (!(le32toh(sc->dc_ldata->dc_rx_list[i].dc_status) & 2718 DC_RXSTAT_OWN)) { 2719 #ifdef DEVICE_POLLING 2720 if (ifp->if_capenable & IFCAP_POLLING) { 2721 if (sc->rxcycles <= 0) 2722 break; 2723 sc->rxcycles--; 2724 } 2725 #endif 2726 cur_rx = &sc->dc_ldata->dc_rx_list[i]; 2727 rxstat = le32toh(cur_rx->dc_status); 2728 m = sc->dc_cdata.dc_rx_chain[i]; 2729 bus_dmamap_sync(sc->dc_mtag, sc->dc_cdata.dc_rx_map[i], 2730 BUS_DMASYNC_POSTREAD); 2731 total_len = DC_RXBYTES(rxstat); 2732 2733 if (sc->dc_flags & DC_PNIC_RX_BUG_WAR) { 2734 if ((rxstat & DC_WHOLEFRAME) != DC_WHOLEFRAME) { 2735 if (rxstat & DC_RXSTAT_FIRSTFRAG) 2736 sc->dc_pnic_rx_bug_save = i; 2737 if ((rxstat & DC_RXSTAT_LASTFRAG) == 0) { 2738 DC_INC(i, DC_RX_LIST_CNT); 2739 continue; 2740 } 2741 dc_pnic_rx_bug_war(sc, i); 2742 rxstat = le32toh(cur_rx->dc_status); 2743 total_len = DC_RXBYTES(rxstat); 2744 } 2745 } 2746 2747 /* 2748 * If an error occurs, update stats, clear the 2749 * status word and leave the mbuf cluster in place: 2750 * it should simply get re-used next time this descriptor 2751 * comes up in the ring. However, don't report long 2752 * frames as errors since they could be vlans. 2753 */ 2754 if ((rxstat & DC_RXSTAT_RXERR)) { 2755 if (!(rxstat & DC_RXSTAT_GIANT) || 2756 (rxstat & (DC_RXSTAT_CRCERR | DC_RXSTAT_DRIBBLE | 2757 DC_RXSTAT_MIIERE | DC_RXSTAT_COLLSEEN | 2758 DC_RXSTAT_RUNT | DC_RXSTAT_DE))) { 2759 ifp->if_ierrors++; 2760 if (rxstat & DC_RXSTAT_COLLSEEN) 2761 ifp->if_collisions++; 2762 dc_newbuf(sc, i, 0); 2763 if (rxstat & DC_RXSTAT_CRCERR) { 2764 DC_INC(i, DC_RX_LIST_CNT); 2765 continue; 2766 } else { 2767 dc_init_locked(sc); 2768 return; 2769 } 2770 } 2771 } 2772 2773 /* No errors; receive the packet. */ 2774 total_len -= ETHER_CRC_LEN; 2775 #ifdef __i386__ 2776 /* 2777 * On the x86 we do not have alignment problems, so try to 2778 * allocate a new buffer for the receive ring, and pass up 2779 * the one where the packet is already, saving the expensive 2780 * copy done in m_devget(). 2781 * If we are on an architecture with alignment problems, or 2782 * if the allocation fails, then use m_devget and leave the 2783 * existing buffer in the receive ring. 2784 */ 2785 if (dc_quick && dc_newbuf(sc, i, 1) == 0) { 2786 m->m_pkthdr.rcvif = ifp; 2787 m->m_pkthdr.len = m->m_len = total_len; 2788 DC_INC(i, DC_RX_LIST_CNT); 2789 } else 2790 #endif 2791 { 2792 struct mbuf *m0; 2793 2794 m0 = m_devget(mtod(m, char *), total_len, 2795 ETHER_ALIGN, ifp, NULL); 2796 dc_newbuf(sc, i, 0); 2797 DC_INC(i, DC_RX_LIST_CNT); 2798 if (m0 == NULL) { 2799 ifp->if_ierrors++; 2800 continue; 2801 } 2802 m = m0; 2803 } 2804 2805 ifp->if_ipackets++; 2806 DC_UNLOCK(sc); 2807 (*ifp->if_input)(ifp, m); 2808 DC_LOCK(sc); 2809 } 2810 2811 sc->dc_cdata.dc_rx_prod = i; 2812 } 2813 2814 /* 2815 * A frame was downloaded to the chip. It's safe for us to clean up 2816 * the list buffers. 2817 */ 2818 2819 static void 2820 dc_txeof(struct dc_softc *sc) 2821 { 2822 struct dc_desc *cur_tx = NULL; 2823 struct ifnet *ifp; 2824 int idx; 2825 u_int32_t ctl, txstat; 2826 2827 ifp = sc->dc_ifp; 2828 2829 /* 2830 * Go through our tx list and free mbufs for those 2831 * frames that have been transmitted. 2832 */ 2833 bus_dmamap_sync(sc->dc_ltag, sc->dc_lmap, BUS_DMASYNC_POSTREAD); 2834 idx = sc->dc_cdata.dc_tx_cons; 2835 while (idx != sc->dc_cdata.dc_tx_prod) { 2836 2837 cur_tx = &sc->dc_ldata->dc_tx_list[idx]; 2838 txstat = le32toh(cur_tx->dc_status); 2839 ctl = le32toh(cur_tx->dc_ctl); 2840 2841 if (txstat & DC_TXSTAT_OWN) 2842 break; 2843 2844 if (!(ctl & DC_TXCTL_LASTFRAG) || ctl & DC_TXCTL_SETUP) { 2845 if (ctl & DC_TXCTL_SETUP) { 2846 /* 2847 * Yes, the PNIC is so brain damaged 2848 * that it will sometimes generate a TX 2849 * underrun error while DMAing the RX 2850 * filter setup frame. If we detect this, 2851 * we have to send the setup frame again, 2852 * or else the filter won't be programmed 2853 * correctly. 2854 */ 2855 if (DC_IS_PNIC(sc)) { 2856 if (txstat & DC_TXSTAT_ERRSUM) 2857 dc_setfilt(sc); 2858 } 2859 sc->dc_cdata.dc_tx_chain[idx] = NULL; 2860 } 2861 sc->dc_cdata.dc_tx_cnt--; 2862 DC_INC(idx, DC_TX_LIST_CNT); 2863 continue; 2864 } 2865 2866 if (DC_IS_XIRCOM(sc) || DC_IS_CONEXANT(sc)) { 2867 /* 2868 * XXX: Why does my Xircom taunt me so? 2869 * For some reason it likes setting the CARRLOST flag 2870 * even when the carrier is there. wtf?!? 2871 * Who knows, but Conexant chips have the 2872 * same problem. Maybe they took lessons 2873 * from Xircom. 2874 */ 2875 if (/*sc->dc_type == DC_TYPE_21143 &&*/ 2876 sc->dc_pmode == DC_PMODE_MII && 2877 ((txstat & 0xFFFF) & ~(DC_TXSTAT_ERRSUM | 2878 DC_TXSTAT_NOCARRIER))) 2879 txstat &= ~DC_TXSTAT_ERRSUM; 2880 } else { 2881 if (/*sc->dc_type == DC_TYPE_21143 &&*/ 2882 sc->dc_pmode == DC_PMODE_MII && 2883 ((txstat & 0xFFFF) & ~(DC_TXSTAT_ERRSUM | 2884 DC_TXSTAT_NOCARRIER | DC_TXSTAT_CARRLOST))) 2885 txstat &= ~DC_TXSTAT_ERRSUM; 2886 } 2887 2888 if (txstat & DC_TXSTAT_ERRSUM) { 2889 ifp->if_oerrors++; 2890 if (txstat & DC_TXSTAT_EXCESSCOLL) 2891 ifp->if_collisions++; 2892 if (txstat & DC_TXSTAT_LATECOLL) 2893 ifp->if_collisions++; 2894 if (!(txstat & DC_TXSTAT_UNDERRUN)) { 2895 dc_init_locked(sc); 2896 return; 2897 } 2898 } 2899 2900 ifp->if_collisions += (txstat & DC_TXSTAT_COLLCNT) >> 3; 2901 2902 ifp->if_opackets++; 2903 if (sc->dc_cdata.dc_tx_chain[idx] != NULL) { 2904 bus_dmamap_sync(sc->dc_mtag, 2905 sc->dc_cdata.dc_tx_map[idx], 2906 BUS_DMASYNC_POSTWRITE); 2907 bus_dmamap_unload(sc->dc_mtag, 2908 sc->dc_cdata.dc_tx_map[idx]); 2909 m_freem(sc->dc_cdata.dc_tx_chain[idx]); 2910 sc->dc_cdata.dc_tx_chain[idx] = NULL; 2911 } 2912 2913 sc->dc_cdata.dc_tx_cnt--; 2914 DC_INC(idx, DC_TX_LIST_CNT); 2915 } 2916 2917 if (idx != sc->dc_cdata.dc_tx_cons) { 2918 /* Some buffers have been freed. */ 2919 sc->dc_cdata.dc_tx_cons = idx; 2920 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 2921 } 2922 ifp->if_timer = (sc->dc_cdata.dc_tx_cnt == 0) ? 0 : 5; 2923 } 2924 2925 static void 2926 dc_tick(void *xsc) 2927 { 2928 struct dc_softc *sc; 2929 struct mii_data *mii; 2930 struct ifnet *ifp; 2931 u_int32_t r; 2932 2933 sc = xsc; 2934 DC_LOCK_ASSERT(sc); 2935 ifp = sc->dc_ifp; 2936 mii = device_get_softc(sc->dc_miibus); 2937 2938 if (sc->dc_flags & DC_REDUCED_MII_POLL) { 2939 if (sc->dc_flags & DC_21143_NWAY) { 2940 r = CSR_READ_4(sc, DC_10BTSTAT); 2941 if (IFM_SUBTYPE(mii->mii_media_active) == 2942 IFM_100_TX && (r & DC_TSTAT_LS100)) { 2943 sc->dc_link = 0; 2944 mii_mediachg(mii); 2945 } 2946 if (IFM_SUBTYPE(mii->mii_media_active) == 2947 IFM_10_T && (r & DC_TSTAT_LS10)) { 2948 sc->dc_link = 0; 2949 mii_mediachg(mii); 2950 } 2951 if (sc->dc_link == 0) 2952 mii_tick(mii); 2953 } else { 2954 r = CSR_READ_4(sc, DC_ISR); 2955 if ((r & DC_ISR_RX_STATE) == DC_RXSTATE_WAIT && 2956 sc->dc_cdata.dc_tx_cnt == 0) { 2957 mii_tick(mii); 2958 if (!(mii->mii_media_status & IFM_ACTIVE)) 2959 sc->dc_link = 0; 2960 } 2961 } 2962 } else 2963 mii_tick(mii); 2964 2965 /* 2966 * When the init routine completes, we expect to be able to send 2967 * packets right away, and in fact the network code will send a 2968 * gratuitous ARP the moment the init routine marks the interface 2969 * as running. However, even though the MAC may have been initialized, 2970 * there may be a delay of a few seconds before the PHY completes 2971 * autonegotiation and the link is brought up. Any transmissions 2972 * made during that delay will be lost. Dealing with this is tricky: 2973 * we can't just pause in the init routine while waiting for the 2974 * PHY to come ready since that would bring the whole system to 2975 * a screeching halt for several seconds. 2976 * 2977 * What we do here is prevent the TX start routine from sending 2978 * any packets until a link has been established. After the 2979 * interface has been initialized, the tick routine will poll 2980 * the state of the PHY until the IFM_ACTIVE flag is set. Until 2981 * that time, packets will stay in the send queue, and once the 2982 * link comes up, they will be flushed out to the wire. 2983 */ 2984 if (!sc->dc_link && mii->mii_media_status & IFM_ACTIVE && 2985 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) { 2986 sc->dc_link++; 2987 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 2988 dc_start_locked(ifp); 2989 } 2990 2991 if (sc->dc_flags & DC_21143_NWAY && !sc->dc_link) 2992 callout_reset(&sc->dc_stat_ch, hz/10, dc_tick, sc); 2993 else 2994 callout_reset(&sc->dc_stat_ch, hz, dc_tick, sc); 2995 } 2996 2997 /* 2998 * A transmit underrun has occurred. Back off the transmit threshold, 2999 * or switch to store and forward mode if we have to. 3000 */ 3001 static void 3002 dc_tx_underrun(struct dc_softc *sc) 3003 { 3004 u_int32_t isr; 3005 int i; 3006 3007 if (DC_IS_DAVICOM(sc)) 3008 dc_init_locked(sc); 3009 3010 if (DC_IS_INTEL(sc)) { 3011 /* 3012 * The real 21143 requires that the transmitter be idle 3013 * in order to change the transmit threshold or store 3014 * and forward state. 3015 */ 3016 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_TX_ON); 3017 3018 for (i = 0; i < DC_TIMEOUT; i++) { 3019 isr = CSR_READ_4(sc, DC_ISR); 3020 if (isr & DC_ISR_TX_IDLE) 3021 break; 3022 DELAY(10); 3023 } 3024 if (i == DC_TIMEOUT) { 3025 if_printf(sc->dc_ifp, 3026 "failed to force tx to idle state\n"); 3027 dc_init_locked(sc); 3028 } 3029 } 3030 3031 if_printf(sc->dc_ifp, "TX underrun -- "); 3032 sc->dc_txthresh += DC_TXTHRESH_INC; 3033 if (sc->dc_txthresh > DC_TXTHRESH_MAX) { 3034 printf("using store and forward mode\n"); 3035 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_STORENFWD); 3036 } else { 3037 printf("increasing TX threshold\n"); 3038 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_TX_THRESH); 3039 DC_SETBIT(sc, DC_NETCFG, sc->dc_txthresh); 3040 } 3041 3042 if (DC_IS_INTEL(sc)) 3043 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_TX_ON); 3044 } 3045 3046 #ifdef DEVICE_POLLING 3047 static poll_handler_t dc_poll; 3048 3049 static void 3050 dc_poll(struct ifnet *ifp, enum poll_cmd cmd, int count) 3051 { 3052 struct dc_softc *sc = ifp->if_softc; 3053 3054 DC_LOCK(sc); 3055 3056 if (!(ifp->if_drv_flags & IFF_DRV_RUNNING)) { 3057 DC_UNLOCK(sc); 3058 return; 3059 } 3060 3061 sc->rxcycles = count; 3062 dc_rxeof(sc); 3063 dc_txeof(sc); 3064 if (!IFQ_IS_EMPTY(&ifp->if_snd) && 3065 !(ifp->if_drv_flags & IFF_DRV_OACTIVE)) 3066 dc_start_locked(ifp); 3067 3068 if (cmd == POLL_AND_CHECK_STATUS) { /* also check status register */ 3069 u_int32_t status; 3070 3071 status = CSR_READ_4(sc, DC_ISR); 3072 status &= (DC_ISR_RX_WATDOGTIMEO | DC_ISR_RX_NOBUF | 3073 DC_ISR_TX_NOBUF | DC_ISR_TX_IDLE | DC_ISR_TX_UNDERRUN | 3074 DC_ISR_BUS_ERR); 3075 if (!status) { 3076 DC_UNLOCK(sc); 3077 return; 3078 } 3079 /* ack what we have */ 3080 CSR_WRITE_4(sc, DC_ISR, status); 3081 3082 if (status & (DC_ISR_RX_WATDOGTIMEO | DC_ISR_RX_NOBUF)) { 3083 u_int32_t r = CSR_READ_4(sc, DC_FRAMESDISCARDED); 3084 ifp->if_ierrors += (r & 0xffff) + ((r >> 17) & 0x7ff); 3085 3086 if (dc_rx_resync(sc)) 3087 dc_rxeof(sc); 3088 } 3089 /* restart transmit unit if necessary */ 3090 if (status & DC_ISR_TX_IDLE && sc->dc_cdata.dc_tx_cnt) 3091 CSR_WRITE_4(sc, DC_TXSTART, 0xFFFFFFFF); 3092 3093 if (status & DC_ISR_TX_UNDERRUN) 3094 dc_tx_underrun(sc); 3095 3096 if (status & DC_ISR_BUS_ERR) { 3097 if_printf(ifp, "dc_poll: bus error\n"); 3098 dc_reset(sc); 3099 dc_init_locked(sc); 3100 } 3101 } 3102 DC_UNLOCK(sc); 3103 } 3104 #endif /* DEVICE_POLLING */ 3105 3106 static void 3107 dc_intr(void *arg) 3108 { 3109 struct dc_softc *sc; 3110 struct ifnet *ifp; 3111 u_int32_t status; 3112 3113 sc = arg; 3114 3115 if (sc->suspended) 3116 return; 3117 3118 if ((CSR_READ_4(sc, DC_ISR) & DC_INTRS) == 0) 3119 return; 3120 3121 DC_LOCK(sc); 3122 ifp = sc->dc_ifp; 3123 #ifdef DEVICE_POLLING 3124 if (ifp->if_capenable & IFCAP_POLLING) { 3125 DC_UNLOCK(sc); 3126 return; 3127 } 3128 #endif 3129 3130 /* Suppress unwanted interrupts */ 3131 if (!(ifp->if_flags & IFF_UP)) { 3132 if (CSR_READ_4(sc, DC_ISR) & DC_INTRS) 3133 dc_stop(sc); 3134 DC_UNLOCK(sc); 3135 return; 3136 } 3137 3138 /* Disable interrupts. */ 3139 CSR_WRITE_4(sc, DC_IMR, 0x00000000); 3140 3141 while (((status = CSR_READ_4(sc, DC_ISR)) & DC_INTRS) 3142 && status != 0xFFFFFFFF) { 3143 3144 CSR_WRITE_4(sc, DC_ISR, status); 3145 3146 if (status & DC_ISR_RX_OK) { 3147 int curpkts; 3148 curpkts = ifp->if_ipackets; 3149 dc_rxeof(sc); 3150 if (curpkts == ifp->if_ipackets) { 3151 while (dc_rx_resync(sc)) 3152 dc_rxeof(sc); 3153 } 3154 } 3155 3156 if (status & (DC_ISR_TX_OK | DC_ISR_TX_NOBUF)) 3157 dc_txeof(sc); 3158 3159 if (status & DC_ISR_TX_IDLE) { 3160 dc_txeof(sc); 3161 if (sc->dc_cdata.dc_tx_cnt) { 3162 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_TX_ON); 3163 CSR_WRITE_4(sc, DC_TXSTART, 0xFFFFFFFF); 3164 } 3165 } 3166 3167 if (status & DC_ISR_TX_UNDERRUN) 3168 dc_tx_underrun(sc); 3169 3170 if ((status & DC_ISR_RX_WATDOGTIMEO) 3171 || (status & DC_ISR_RX_NOBUF)) { 3172 int curpkts; 3173 curpkts = ifp->if_ipackets; 3174 dc_rxeof(sc); 3175 if (curpkts == ifp->if_ipackets) { 3176 while (dc_rx_resync(sc)) 3177 dc_rxeof(sc); 3178 } 3179 } 3180 3181 if (status & DC_ISR_BUS_ERR) { 3182 dc_reset(sc); 3183 dc_init_locked(sc); 3184 } 3185 } 3186 3187 /* Re-enable interrupts. */ 3188 CSR_WRITE_4(sc, DC_IMR, DC_INTRS); 3189 3190 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 3191 dc_start_locked(ifp); 3192 3193 DC_UNLOCK(sc); 3194 } 3195 3196 static void 3197 dc_dma_map_txbuf(arg, segs, nseg, mapsize, error) 3198 void *arg; 3199 bus_dma_segment_t *segs; 3200 int nseg; 3201 bus_size_t mapsize; 3202 int error; 3203 { 3204 struct dc_softc *sc; 3205 struct dc_desc *f; 3206 int cur, first, frag, i; 3207 3208 sc = arg; 3209 if (error) { 3210 sc->dc_cdata.dc_tx_err = error; 3211 return; 3212 } 3213 3214 first = cur = frag = sc->dc_cdata.dc_tx_prod; 3215 for (i = 0; i < nseg; i++) { 3216 if ((sc->dc_flags & DC_TX_ADMTEK_WAR) && 3217 (frag == (DC_TX_LIST_CNT - 1)) && 3218 (first != sc->dc_cdata.dc_tx_first)) { 3219 bus_dmamap_unload(sc->dc_mtag, 3220 sc->dc_cdata.dc_tx_map[first]); 3221 sc->dc_cdata.dc_tx_err = ENOBUFS; 3222 return; 3223 } 3224 3225 f = &sc->dc_ldata->dc_tx_list[frag]; 3226 f->dc_ctl = htole32(DC_TXCTL_TLINK | segs[i].ds_len); 3227 if (i == 0) { 3228 f->dc_status = 0; 3229 f->dc_ctl |= htole32(DC_TXCTL_FIRSTFRAG); 3230 } else 3231 f->dc_status = htole32(DC_TXSTAT_OWN); 3232 f->dc_data = htole32(segs[i].ds_addr); 3233 cur = frag; 3234 DC_INC(frag, DC_TX_LIST_CNT); 3235 } 3236 3237 sc->dc_cdata.dc_tx_err = 0; 3238 sc->dc_cdata.dc_tx_prod = frag; 3239 sc->dc_cdata.dc_tx_cnt += nseg; 3240 sc->dc_ldata->dc_tx_list[cur].dc_ctl |= htole32(DC_TXCTL_LASTFRAG); 3241 sc->dc_cdata.dc_tx_chain[cur] = sc->dc_cdata.dc_tx_mapping; 3242 if (sc->dc_flags & DC_TX_INTR_FIRSTFRAG) 3243 sc->dc_ldata->dc_tx_list[first].dc_ctl |= 3244 htole32(DC_TXCTL_FINT); 3245 if (sc->dc_flags & DC_TX_INTR_ALWAYS) 3246 sc->dc_ldata->dc_tx_list[cur].dc_ctl |= htole32(DC_TXCTL_FINT); 3247 if (sc->dc_flags & DC_TX_USE_TX_INTR && sc->dc_cdata.dc_tx_cnt > 64) 3248 sc->dc_ldata->dc_tx_list[cur].dc_ctl |= htole32(DC_TXCTL_FINT); 3249 sc->dc_ldata->dc_tx_list[first].dc_status = htole32(DC_TXSTAT_OWN); 3250 } 3251 3252 /* 3253 * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data 3254 * pointers to the fragment pointers. 3255 */ 3256 static int 3257 dc_encap(struct dc_softc *sc, struct mbuf **m_head) 3258 { 3259 struct mbuf *m; 3260 int error, idx, chainlen = 0; 3261 3262 /* 3263 * If there's no way we can send any packets, return now. 3264 */ 3265 if (DC_TX_LIST_CNT - sc->dc_cdata.dc_tx_cnt < 6) 3266 return (ENOBUFS); 3267 3268 /* 3269 * Count the number of frags in this chain to see if 3270 * we need to m_defrag. Since the descriptor list is shared 3271 * by all packets, we'll m_defrag long chains so that they 3272 * do not use up the entire list, even if they would fit. 3273 */ 3274 for (m = *m_head; m != NULL; m = m->m_next) 3275 chainlen++; 3276 3277 if ((chainlen > DC_TX_LIST_CNT / 4) || 3278 ((DC_TX_LIST_CNT - (chainlen + sc->dc_cdata.dc_tx_cnt)) < 6)) { 3279 m = m_defrag(*m_head, M_DONTWAIT); 3280 if (m == NULL) 3281 return (ENOBUFS); 3282 *m_head = m; 3283 } 3284 3285 /* 3286 * Start packing the mbufs in this chain into 3287 * the fragment pointers. Stop when we run out 3288 * of fragments or hit the end of the mbuf chain. 3289 */ 3290 idx = sc->dc_cdata.dc_tx_prod; 3291 sc->dc_cdata.dc_tx_mapping = *m_head; 3292 error = bus_dmamap_load_mbuf(sc->dc_mtag, sc->dc_cdata.dc_tx_map[idx], 3293 *m_head, dc_dma_map_txbuf, sc, 0); 3294 if (error) 3295 return (error); 3296 if (sc->dc_cdata.dc_tx_err != 0) 3297 return (sc->dc_cdata.dc_tx_err); 3298 bus_dmamap_sync(sc->dc_mtag, sc->dc_cdata.dc_tx_map[idx], 3299 BUS_DMASYNC_PREWRITE); 3300 bus_dmamap_sync(sc->dc_ltag, sc->dc_lmap, 3301 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3302 return (0); 3303 } 3304 3305 /* 3306 * Main transmit routine. To avoid having to do mbuf copies, we put pointers 3307 * to the mbuf data regions directly in the transmit lists. We also save a 3308 * copy of the pointers since the transmit list fragment pointers are 3309 * physical addresses. 3310 */ 3311 3312 static void 3313 dc_start(struct ifnet *ifp) 3314 { 3315 struct dc_softc *sc; 3316 3317 sc = ifp->if_softc; 3318 DC_LOCK(sc); 3319 dc_start_locked(ifp); 3320 DC_UNLOCK(sc); 3321 } 3322 3323 static void 3324 dc_start_locked(struct ifnet *ifp) 3325 { 3326 struct dc_softc *sc; 3327 struct mbuf *m_head = NULL, *m; 3328 unsigned int queued = 0; 3329 int idx; 3330 3331 sc = ifp->if_softc; 3332 3333 DC_LOCK_ASSERT(sc); 3334 3335 if (!sc->dc_link && ifp->if_snd.ifq_len < 10) 3336 return; 3337 3338 if (ifp->if_drv_flags & IFF_DRV_OACTIVE) 3339 return; 3340 3341 idx = sc->dc_cdata.dc_tx_first = sc->dc_cdata.dc_tx_prod; 3342 3343 while (sc->dc_cdata.dc_tx_chain[idx] == NULL) { 3344 IFQ_DRV_DEQUEUE(&ifp->if_snd, m_head); 3345 if (m_head == NULL) 3346 break; 3347 3348 if (sc->dc_flags & DC_TX_COALESCE && 3349 (m_head->m_next != NULL || 3350 sc->dc_flags & DC_TX_ALIGN)) { 3351 m = m_defrag(m_head, M_DONTWAIT); 3352 if (m == NULL) { 3353 IFQ_DRV_PREPEND(&ifp->if_snd, m_head); 3354 ifp->if_drv_flags |= IFF_DRV_OACTIVE; 3355 break; 3356 } else { 3357 m_head = m; 3358 } 3359 } 3360 3361 if (dc_encap(sc, &m_head)) { 3362 IFQ_DRV_PREPEND(&ifp->if_snd, m_head); 3363 ifp->if_drv_flags |= IFF_DRV_OACTIVE; 3364 break; 3365 } 3366 idx = sc->dc_cdata.dc_tx_prod; 3367 3368 queued++; 3369 /* 3370 * If there's a BPF listener, bounce a copy of this frame 3371 * to him. 3372 */ 3373 BPF_MTAP(ifp, m_head); 3374 3375 if (sc->dc_flags & DC_TX_ONE) { 3376 ifp->if_drv_flags |= IFF_DRV_OACTIVE; 3377 break; 3378 } 3379 } 3380 3381 if (queued > 0) { 3382 /* Transmit */ 3383 if (!(sc->dc_flags & DC_TX_POLL)) 3384 CSR_WRITE_4(sc, DC_TXSTART, 0xFFFFFFFF); 3385 3386 /* 3387 * Set a timeout in case the chip goes out to lunch. 3388 */ 3389 ifp->if_timer = 5; 3390 } 3391 } 3392 3393 static void 3394 dc_init(void *xsc) 3395 { 3396 struct dc_softc *sc = xsc; 3397 3398 DC_LOCK(sc); 3399 dc_init_locked(sc); 3400 #ifdef SRM_MEDIA 3401 if(sc->dc_srm_media) { 3402 struct ifreq ifr; 3403 struct mii_data *mii; 3404 3405 ifr.ifr_media = sc->dc_srm_media; 3406 sc->dc_srm_media = 0; 3407 DC_UNLOCK(sc); 3408 mii = device_get_softc(sc->dc_miibus); 3409 ifmedia_ioctl(sc->dc_ifp, &ifr, &mii->mii_media, SIOCSIFMEDIA); 3410 } else 3411 #endif 3412 DC_UNLOCK(sc); 3413 } 3414 3415 static void 3416 dc_init_locked(struct dc_softc *sc) 3417 { 3418 struct ifnet *ifp = sc->dc_ifp; 3419 struct mii_data *mii; 3420 3421 DC_LOCK_ASSERT(sc); 3422 3423 mii = device_get_softc(sc->dc_miibus); 3424 3425 /* 3426 * Cancel pending I/O and free all RX/TX buffers. 3427 */ 3428 dc_stop(sc); 3429 dc_reset(sc); 3430 3431 /* 3432 * Set cache alignment and burst length. 3433 */ 3434 if (DC_IS_ASIX(sc) || DC_IS_DAVICOM(sc)) 3435 CSR_WRITE_4(sc, DC_BUSCTL, 0); 3436 else 3437 CSR_WRITE_4(sc, DC_BUSCTL, DC_BUSCTL_MRME | DC_BUSCTL_MRLE); 3438 /* 3439 * Evenly share the bus between receive and transmit process. 3440 */ 3441 if (DC_IS_INTEL(sc)) 3442 DC_SETBIT(sc, DC_BUSCTL, DC_BUSCTL_ARBITRATION); 3443 if (DC_IS_DAVICOM(sc) || DC_IS_INTEL(sc)) { 3444 DC_SETBIT(sc, DC_BUSCTL, DC_BURSTLEN_USECA); 3445 } else { 3446 DC_SETBIT(sc, DC_BUSCTL, DC_BURSTLEN_16LONG); 3447 } 3448 if (sc->dc_flags & DC_TX_POLL) 3449 DC_SETBIT(sc, DC_BUSCTL, DC_TXPOLL_1); 3450 switch(sc->dc_cachesize) { 3451 case 32: 3452 DC_SETBIT(sc, DC_BUSCTL, DC_CACHEALIGN_32LONG); 3453 break; 3454 case 16: 3455 DC_SETBIT(sc, DC_BUSCTL, DC_CACHEALIGN_16LONG); 3456 break; 3457 case 8: 3458 DC_SETBIT(sc, DC_BUSCTL, DC_CACHEALIGN_8LONG); 3459 break; 3460 case 0: 3461 default: 3462 DC_SETBIT(sc, DC_BUSCTL, DC_CACHEALIGN_NONE); 3463 break; 3464 } 3465 3466 if (sc->dc_flags & DC_TX_STORENFWD) 3467 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_STORENFWD); 3468 else { 3469 if (sc->dc_txthresh > DC_TXTHRESH_MAX) { 3470 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_STORENFWD); 3471 } else { 3472 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_STORENFWD); 3473 DC_SETBIT(sc, DC_NETCFG, sc->dc_txthresh); 3474 } 3475 } 3476 3477 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_NO_RXCRC); 3478 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_TX_BACKOFF); 3479 3480 if (DC_IS_MACRONIX(sc) || DC_IS_PNICII(sc)) { 3481 /* 3482 * The app notes for the 98713 and 98715A say that 3483 * in order to have the chips operate properly, a magic 3484 * number must be written to CSR16. Macronix does not 3485 * document the meaning of these bits so there's no way 3486 * to know exactly what they do. The 98713 has a magic 3487 * number all its own; the rest all use a different one. 3488 */ 3489 DC_CLRBIT(sc, DC_MX_MAGICPACKET, 0xFFFF0000); 3490 if (sc->dc_type == DC_TYPE_98713) 3491 DC_SETBIT(sc, DC_MX_MAGICPACKET, DC_MX_MAGIC_98713); 3492 else 3493 DC_SETBIT(sc, DC_MX_MAGICPACKET, DC_MX_MAGIC_98715); 3494 } 3495 3496 if (DC_IS_XIRCOM(sc)) { 3497 /* 3498 * setup General Purpose Port mode and data so the tulip 3499 * can talk to the MII. 3500 */ 3501 CSR_WRITE_4(sc, DC_SIAGP, DC_SIAGP_WRITE_EN | DC_SIAGP_INT1_EN | 3502 DC_SIAGP_MD_GP2_OUTPUT | DC_SIAGP_MD_GP0_OUTPUT); 3503 DELAY(10); 3504 CSR_WRITE_4(sc, DC_SIAGP, DC_SIAGP_INT1_EN | 3505 DC_SIAGP_MD_GP2_OUTPUT | DC_SIAGP_MD_GP0_OUTPUT); 3506 DELAY(10); 3507 } 3508 3509 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_TX_THRESH); 3510 DC_SETBIT(sc, DC_NETCFG, DC_TXTHRESH_MIN); 3511 3512 /* Init circular RX list. */ 3513 if (dc_list_rx_init(sc) == ENOBUFS) { 3514 if_printf(ifp, 3515 "initialization failed: no memory for rx buffers\n"); 3516 dc_stop(sc); 3517 return; 3518 } 3519 3520 /* 3521 * Init TX descriptors. 3522 */ 3523 dc_list_tx_init(sc); 3524 3525 /* 3526 * Load the address of the RX list. 3527 */ 3528 CSR_WRITE_4(sc, DC_RXADDR, DC_RXDESC(sc, 0)); 3529 CSR_WRITE_4(sc, DC_TXADDR, DC_TXDESC(sc, 0)); 3530 3531 /* 3532 * Enable interrupts. 3533 */ 3534 #ifdef DEVICE_POLLING 3535 /* 3536 * ... but only if we are not polling, and make sure they are off in 3537 * the case of polling. Some cards (e.g. fxp) turn interrupts on 3538 * after a reset. 3539 */ 3540 if (ifp->if_capenable & IFCAP_POLLING) 3541 CSR_WRITE_4(sc, DC_IMR, 0x00000000); 3542 else 3543 #endif 3544 CSR_WRITE_4(sc, DC_IMR, DC_INTRS); 3545 CSR_WRITE_4(sc, DC_ISR, 0xFFFFFFFF); 3546 3547 /* Enable transmitter. */ 3548 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_TX_ON); 3549 3550 /* 3551 * If this is an Intel 21143 and we're not using the 3552 * MII port, program the LED control pins so we get 3553 * link and activity indications. 3554 */ 3555 if (sc->dc_flags & DC_TULIP_LEDS) { 3556 CSR_WRITE_4(sc, DC_WATCHDOG, 3557 DC_WDOG_CTLWREN | DC_WDOG_LINK | DC_WDOG_ACTIVITY); 3558 CSR_WRITE_4(sc, DC_WATCHDOG, 0); 3559 } 3560 3561 /* 3562 * Load the RX/multicast filter. We do this sort of late 3563 * because the filter programming scheme on the 21143 and 3564 * some clones requires DMAing a setup frame via the TX 3565 * engine, and we need the transmitter enabled for that. 3566 */ 3567 dc_setfilt(sc); 3568 3569 /* Enable receiver. */ 3570 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_ON); 3571 CSR_WRITE_4(sc, DC_RXSTART, 0xFFFFFFFF); 3572 3573 mii_mediachg(mii); 3574 dc_setcfg(sc, sc->dc_if_media); 3575 3576 ifp->if_drv_flags |= IFF_DRV_RUNNING; 3577 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 3578 3579 /* Don't start the ticker if this is a homePNA link. */ 3580 if (IFM_SUBTYPE(mii->mii_media.ifm_media) == IFM_HPNA_1) 3581 sc->dc_link = 1; 3582 else { 3583 if (sc->dc_flags & DC_21143_NWAY) 3584 callout_reset(&sc->dc_stat_ch, hz/10, dc_tick, sc); 3585 else 3586 callout_reset(&sc->dc_stat_ch, hz, dc_tick, sc); 3587 } 3588 } 3589 3590 /* 3591 * Set media options. 3592 */ 3593 static int 3594 dc_ifmedia_upd(struct ifnet *ifp) 3595 { 3596 struct dc_softc *sc; 3597 struct mii_data *mii; 3598 struct ifmedia *ifm; 3599 3600 sc = ifp->if_softc; 3601 mii = device_get_softc(sc->dc_miibus); 3602 DC_LOCK(sc); 3603 mii_mediachg(mii); 3604 ifm = &mii->mii_media; 3605 3606 if (DC_IS_DAVICOM(sc) && 3607 IFM_SUBTYPE(ifm->ifm_media) == IFM_HPNA_1) 3608 dc_setcfg(sc, ifm->ifm_media); 3609 else 3610 sc->dc_link = 0; 3611 DC_UNLOCK(sc); 3612 3613 return (0); 3614 } 3615 3616 /* 3617 * Report current media status. 3618 */ 3619 static void 3620 dc_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 3621 { 3622 struct dc_softc *sc; 3623 struct mii_data *mii; 3624 struct ifmedia *ifm; 3625 3626 sc = ifp->if_softc; 3627 mii = device_get_softc(sc->dc_miibus); 3628 DC_LOCK(sc); 3629 mii_pollstat(mii); 3630 ifm = &mii->mii_media; 3631 if (DC_IS_DAVICOM(sc)) { 3632 if (IFM_SUBTYPE(ifm->ifm_media) == IFM_HPNA_1) { 3633 ifmr->ifm_active = ifm->ifm_media; 3634 ifmr->ifm_status = 0; 3635 return; 3636 } 3637 } 3638 ifmr->ifm_active = mii->mii_media_active; 3639 ifmr->ifm_status = mii->mii_media_status; 3640 DC_UNLOCK(sc); 3641 } 3642 3643 static int 3644 dc_ioctl(struct ifnet *ifp, u_long command, caddr_t data) 3645 { 3646 struct dc_softc *sc = ifp->if_softc; 3647 struct ifreq *ifr = (struct ifreq *)data; 3648 struct mii_data *mii; 3649 int error = 0; 3650 3651 switch (command) { 3652 case SIOCSIFFLAGS: 3653 DC_LOCK(sc); 3654 if (ifp->if_flags & IFF_UP) { 3655 int need_setfilt = (ifp->if_flags ^ sc->dc_if_flags) & 3656 (IFF_PROMISC | IFF_ALLMULTI); 3657 3658 if (ifp->if_drv_flags & IFF_DRV_RUNNING) { 3659 if (need_setfilt) 3660 dc_setfilt(sc); 3661 } else { 3662 sc->dc_txthresh = 0; 3663 dc_init_locked(sc); 3664 } 3665 } else { 3666 if (ifp->if_drv_flags & IFF_DRV_RUNNING) 3667 dc_stop(sc); 3668 } 3669 sc->dc_if_flags = ifp->if_flags; 3670 DC_UNLOCK(sc); 3671 error = 0; 3672 break; 3673 case SIOCADDMULTI: 3674 case SIOCDELMULTI: 3675 DC_LOCK(sc); 3676 dc_setfilt(sc); 3677 DC_UNLOCK(sc); 3678 error = 0; 3679 break; 3680 case SIOCGIFMEDIA: 3681 case SIOCSIFMEDIA: 3682 mii = device_get_softc(sc->dc_miibus); 3683 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 3684 #ifdef SRM_MEDIA 3685 DC_LOCK(sc); 3686 if (sc->dc_srm_media) 3687 sc->dc_srm_media = 0; 3688 DC_UNLOCK(sc); 3689 #endif 3690 break; 3691 case SIOCSIFCAP: 3692 #ifdef DEVICE_POLLING 3693 if (ifr->ifr_reqcap & IFCAP_POLLING && 3694 !(ifp->if_capenable & IFCAP_POLLING)) { 3695 error = ether_poll_register(dc_poll, ifp); 3696 if (error) 3697 return(error); 3698 DC_LOCK(sc); 3699 /* Disable interrupts */ 3700 CSR_WRITE_4(sc, DC_IMR, 0x00000000); 3701 ifp->if_capenable |= IFCAP_POLLING; 3702 DC_UNLOCK(sc); 3703 return (error); 3704 3705 } 3706 if (!(ifr->ifr_reqcap & IFCAP_POLLING) && 3707 ifp->if_capenable & IFCAP_POLLING) { 3708 error = ether_poll_deregister(ifp); 3709 /* Enable interrupts. */ 3710 DC_LOCK(sc); 3711 CSR_WRITE_4(sc, DC_IMR, DC_INTRS); 3712 ifp->if_capenable &= ~IFCAP_POLLING; 3713 DC_UNLOCK(sc); 3714 return (error); 3715 } 3716 #endif /* DEVICE_POLLING */ 3717 break; 3718 default: 3719 error = ether_ioctl(ifp, command, data); 3720 break; 3721 } 3722 3723 return (error); 3724 } 3725 3726 static void 3727 dc_watchdog(struct ifnet *ifp) 3728 { 3729 struct dc_softc *sc; 3730 3731 sc = ifp->if_softc; 3732 3733 DC_LOCK(sc); 3734 3735 ifp->if_oerrors++; 3736 if_printf(ifp, "watchdog timeout\n"); 3737 3738 dc_stop(sc); 3739 dc_reset(sc); 3740 dc_init_locked(sc); 3741 3742 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 3743 dc_start_locked(ifp); 3744 3745 DC_UNLOCK(sc); 3746 } 3747 3748 /* 3749 * Stop the adapter and free any mbufs allocated to the 3750 * RX and TX lists. 3751 */ 3752 static void 3753 dc_stop(struct dc_softc *sc) 3754 { 3755 struct ifnet *ifp; 3756 struct dc_list_data *ld; 3757 struct dc_chain_data *cd; 3758 int i; 3759 u_int32_t ctl; 3760 3761 DC_LOCK_ASSERT(sc); 3762 3763 ifp = sc->dc_ifp; 3764 ifp->if_timer = 0; 3765 ld = sc->dc_ldata; 3766 cd = &sc->dc_cdata; 3767 3768 callout_stop(&sc->dc_stat_ch); 3769 3770 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE); 3771 3772 DC_CLRBIT(sc, DC_NETCFG, (DC_NETCFG_RX_ON | DC_NETCFG_TX_ON)); 3773 CSR_WRITE_4(sc, DC_IMR, 0x00000000); 3774 CSR_WRITE_4(sc, DC_TXADDR, 0x00000000); 3775 CSR_WRITE_4(sc, DC_RXADDR, 0x00000000); 3776 sc->dc_link = 0; 3777 3778 /* 3779 * Free data in the RX lists. 3780 */ 3781 for (i = 0; i < DC_RX_LIST_CNT; i++) { 3782 if (cd->dc_rx_chain[i] != NULL) { 3783 m_freem(cd->dc_rx_chain[i]); 3784 cd->dc_rx_chain[i] = NULL; 3785 } 3786 } 3787 bzero(&ld->dc_rx_list, sizeof(ld->dc_rx_list)); 3788 3789 /* 3790 * Free the TX list buffers. 3791 */ 3792 for (i = 0; i < DC_TX_LIST_CNT; i++) { 3793 if (cd->dc_tx_chain[i] != NULL) { 3794 ctl = le32toh(ld->dc_tx_list[i].dc_ctl); 3795 if ((ctl & DC_TXCTL_SETUP) || 3796 !(ctl & DC_TXCTL_LASTFRAG)) { 3797 cd->dc_tx_chain[i] = NULL; 3798 continue; 3799 } 3800 bus_dmamap_unload(sc->dc_mtag, cd->dc_tx_map[i]); 3801 m_freem(cd->dc_tx_chain[i]); 3802 cd->dc_tx_chain[i] = NULL; 3803 } 3804 } 3805 bzero(&ld->dc_tx_list, sizeof(ld->dc_tx_list)); 3806 } 3807 3808 /* 3809 * Device suspend routine. Stop the interface and save some PCI 3810 * settings in case the BIOS doesn't restore them properly on 3811 * resume. 3812 */ 3813 static int 3814 dc_suspend(device_t dev) 3815 { 3816 struct dc_softc *sc; 3817 3818 sc = device_get_softc(dev); 3819 DC_LOCK(sc); 3820 dc_stop(sc); 3821 sc->suspended = 1; 3822 DC_UNLOCK(sc); 3823 3824 return (0); 3825 } 3826 3827 /* 3828 * Device resume routine. Restore some PCI settings in case the BIOS 3829 * doesn't, re-enable busmastering, and restart the interface if 3830 * appropriate. 3831 */ 3832 static int 3833 dc_resume(device_t dev) 3834 { 3835 struct dc_softc *sc; 3836 struct ifnet *ifp; 3837 3838 sc = device_get_softc(dev); 3839 ifp = sc->dc_ifp; 3840 3841 /* reinitialize interface if necessary */ 3842 DC_LOCK(sc); 3843 if (ifp->if_flags & IFF_UP) 3844 dc_init_locked(sc); 3845 3846 sc->suspended = 0; 3847 DC_UNLOCK(sc); 3848 3849 return (0); 3850 } 3851 3852 /* 3853 * Stop all chip I/O so that the kernel's probe routines don't 3854 * get confused by errant DMAs when rebooting. 3855 */ 3856 static void 3857 dc_shutdown(device_t dev) 3858 { 3859 struct dc_softc *sc; 3860 3861 sc = device_get_softc(dev); 3862 3863 DC_LOCK(sc); 3864 dc_stop(sc); 3865 DC_UNLOCK(sc); 3866 } 3867