1 /* 2 * Copyright (c) 1997, 1998, 1999 3 * Bill Paul <wpaul@ee.columbia.edu>. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 3. All advertising materials mentioning features or use of this software 14 * must display the following acknowledgement: 15 * This product includes software developed by Bill Paul. 16 * 4. Neither the name of the author nor the names of any co-contributors 17 * may be used to endorse or promote products derived from this software 18 * without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30 * THE POSSIBILITY OF SUCH DAMAGE. 31 * 32 * $FreeBSD$ 33 */ 34 35 /* 36 * DEC "tulip" clone ethernet driver. Supports the DEC/Intel 21143 37 * series chips and several workalikes including the following: 38 * 39 * Macronix 98713/98715/98725 PMAC (www.macronix.com) 40 * Macronix/Lite-On 82c115 PNIC II (www.macronix.com) 41 * Lite-On 82c168/82c169 PNIC (www.litecom.com) 42 * ASIX Electronics AX88140A (www.asix.com.tw) 43 * ASIX Electronics AX88141 (www.asix.com.tw) 44 * ADMtek AL981 (www.admtek.com.tw) 45 * ADMtek AN985 (www.admtek.com.tw) 46 * Davicom DM9100, DM9102, DM9102A (www.davicom8.com) 47 * 48 * Datasheets for the 21143 are available at developer.intel.com. 49 * Datasheets for the clone parts can be found at their respective sites. 50 * (Except for the PNIC; see www.freebsd.org/~wpaul/PNIC/pnic.ps.gz.) 51 * The PNIC II is essentially a Macronix 98715A chip; the only difference 52 * worth noting is that its multicast hash table is only 128 bits wide 53 * instead of 512. 54 * 55 * Written by Bill Paul <wpaul@ee.columbia.edu> 56 * Electrical Engineering Department 57 * Columbia University, New York City 58 */ 59 60 /* 61 * The Intel 21143 is the successor to the DEC 21140. It is basically 62 * the same as the 21140 but with a few new features. The 21143 supports 63 * three kinds of media attachments: 64 * 65 * o MII port, for 10Mbps and 100Mbps support and NWAY 66 * autonegotiation provided by an external PHY. 67 * o SYM port, for symbol mode 100Mbps support. 68 * o 10baseT port. 69 * o AUI/BNC port. 70 * 71 * The 100Mbps SYM port and 10baseT port can be used together in 72 * combination with the internal NWAY support to create a 10/100 73 * autosensing configuration. 74 * 75 * Knowing which media is available on a given card is tough: you're 76 * supposed to go slogging through the EEPROM looking for media 77 * description structures. Unfortunately, some card vendors that use 78 * the 21143 don't obey the DEC SROM spec correctly, which means that 79 * what you find in the EEPROM may not agree with reality. Fortunately, 80 * the 21143 provides us a way to get around this issue: lurking in 81 * PCI configuration space is the Configuration Wake-Up Command Register. 82 * This register is loaded with a value from the EEPROM when wake on LAN 83 * mode is enabled; this value tells us quite clearly what kind of media 84 * is attached to the NIC. The main purpose of this register is to tell 85 * the NIC what media to scan when in wake on LAN mode, however by 86 * forcibly enabling wake on LAN mode, we can use to learn what kind of 87 * media a given NIC has available and adapt ourselves accordingly. 88 * 89 * Of course, if the media description blocks in the EEPROM are bogus. 90 * what are the odds that the CWUC aren't bogus as well, right? Well, 91 * the CWUC value is more likely to be correct since wake on LAN mode 92 * won't work correctly without it, and wake on LAN is a big selling 93 * point these days. It's also harder to screw up a single byte than 94 * a whole media descriptor block. 95 * 96 * Note that not all tulip workalikes are handled in this driver: we only 97 * deal with those which are relatively well behaved. The Winbond is 98 * handled separately due to its different register offsets and the 99 * special handling needed for its various bugs. The PNIC is handled 100 * here, but I'm not thrilled about it. 101 * 102 * All of the workalike chips use some form of MII transceiver support 103 * with the exception of the Macronix chips, which also have a SYM port. 104 * The ASIX AX88140A is also documented to have a SYM port, but all 105 * the cards I've seen use an MII transceiver, probably because the 106 * AX88140A doesn't support internal NWAY. 107 */ 108 109 #include <sys/param.h> 110 #include <sys/systm.h> 111 #include <sys/sockio.h> 112 #include <sys/mbuf.h> 113 #include <sys/malloc.h> 114 #include <sys/kernel.h> 115 #include <sys/socket.h> 116 117 #include <net/if.h> 118 #include <net/if_arp.h> 119 #include <net/ethernet.h> 120 #include <net/if_dl.h> 121 #include <net/if_media.h> 122 123 #include <net/bpf.h> 124 125 #include "opt_bdg.h" 126 #ifdef BRIDGE 127 #include <net/bridge.h> 128 #endif 129 130 #include <vm/vm.h> /* for vtophys */ 131 #include <vm/pmap.h> /* for vtophys */ 132 #include <machine/clock.h> /* for DELAY */ 133 #include <machine/bus_pio.h> 134 #include <machine/bus_memio.h> 135 #include <machine/bus.h> 136 #include <machine/resource.h> 137 #include <sys/bus.h> 138 #include <sys/rman.h> 139 140 #include <dev/mii/mii.h> 141 #include <dev/mii/miivar.h> 142 143 #include <pci/pcireg.h> 144 #include <pci/pcivar.h> 145 146 #define DC_USEIOSPACE 147 148 #include <pci/if_dcreg.h> 149 150 MODULE_DEPEND(dc, miibus, 1, 1, 1); 151 152 /* "controller miibus0" required. See GENERIC if you get errors here. */ 153 #include "miibus_if.h" 154 155 #ifndef lint 156 static const char rcsid[] = 157 "$FreeBSD$"; 158 #endif 159 160 /* 161 * Various supported device vendors/types and their names. 162 */ 163 static struct dc_type dc_devs[] = { 164 { DC_VENDORID_DEC, DC_DEVICEID_21143, 165 "Intel 21143 10/100BaseTX" }, 166 { DC_VENDORID_DAVICOM, DC_DEVICEID_DM9100, 167 "Davicom DM9100 10/100BaseTX" }, 168 { DC_VENDORID_DAVICOM, DC_DEVICEID_DM9102, 169 "Davicom DM9102 10/100BaseTX" }, 170 { DC_VENDORID_DAVICOM, DC_DEVICEID_DM9102, 171 "Davicom DM9102A 10/100BaseTX" }, 172 { DC_VENDORID_ADMTEK, DC_DEVICEID_AL981, 173 "ADMtek AL981 10/100BaseTX" }, 174 { DC_VENDORID_ADMTEK, DC_DEVICEID_AN985, 175 "ADMtek AN985 10/100BaseTX" }, 176 { DC_VENDORID_ASIX, DC_DEVICEID_AX88140A, 177 "ASIX AX88140A 10/100BaseTX" }, 178 { DC_VENDORID_ASIX, DC_DEVICEID_AX88140A, 179 "ASIX AX88141 10/100BaseTX" }, 180 { DC_VENDORID_MX, DC_DEVICEID_98713, 181 "Macronix 98713 10/100BaseTX" }, 182 { DC_VENDORID_MX, DC_DEVICEID_98713, 183 "Macronix 98713A 10/100BaseTX" }, 184 { DC_VENDORID_CP, DC_DEVICEID_98713_CP, 185 "Compex RL100-TX 10/100BaseTX" }, 186 { DC_VENDORID_CP, DC_DEVICEID_98713_CP, 187 "Compex RL100-TX 10/100BaseTX" }, 188 { DC_VENDORID_MX, DC_DEVICEID_987x5, 189 "Macronix 98715/98715A 10/100BaseTX" }, 190 { DC_VENDORID_MX, DC_DEVICEID_987x5, 191 "Macronix 98725 10/100BaseTX" }, 192 { DC_VENDORID_LO, DC_DEVICEID_82C115, 193 "LC82C115 PNIC II 10/100BaseTX" }, 194 { DC_VENDORID_LO, DC_DEVICEID_82C168, 195 "82c168 PNIC 10/100BaseTX" }, 196 { DC_VENDORID_LO, DC_DEVICEID_82C168, 197 "82c169 PNIC 10/100BaseTX" }, 198 { 0, 0, NULL } 199 }; 200 201 static int dc_probe __P((device_t)); 202 static int dc_attach __P((device_t)); 203 static int dc_detach __P((device_t)); 204 static void dc_acpi __P((device_t)); 205 static struct dc_type *dc_devtype __P((device_t)); 206 static int dc_newbuf __P((struct dc_softc *, int, struct mbuf *)); 207 static int dc_encap __P((struct dc_softc *, struct mbuf *, 208 u_int32_t *)); 209 static int dc_coal __P((struct dc_softc *, struct mbuf **)); 210 static void dc_pnic_rx_bug_war __P((struct dc_softc *, int)); 211 static int dc_rx_resync __P((struct dc_softc *)); 212 static void dc_rxeof __P((struct dc_softc *)); 213 static void dc_txeof __P((struct dc_softc *)); 214 static void dc_tick __P((void *)); 215 static void dc_intr __P((void *)); 216 static void dc_start __P((struct ifnet *)); 217 static int dc_ioctl __P((struct ifnet *, u_long, caddr_t)); 218 static void dc_init __P((void *)); 219 static void dc_stop __P((struct dc_softc *)); 220 static void dc_watchdog __P((struct ifnet *)); 221 static void dc_shutdown __P((device_t)); 222 static int dc_ifmedia_upd __P((struct ifnet *)); 223 static void dc_ifmedia_sts __P((struct ifnet *, struct ifmediareq *)); 224 225 static void dc_delay __P((struct dc_softc *)); 226 static void dc_eeprom_idle __P((struct dc_softc *)); 227 static void dc_eeprom_putbyte __P((struct dc_softc *, int)); 228 static void dc_eeprom_getword __P((struct dc_softc *, int, u_int16_t *)); 229 static void dc_eeprom_getword_pnic 230 __P((struct dc_softc *, int, u_int16_t *)); 231 static void dc_read_eeprom __P((struct dc_softc *, caddr_t, int, 232 int, int)); 233 234 static void dc_mii_writebit __P((struct dc_softc *, int)); 235 static int dc_mii_readbit __P((struct dc_softc *)); 236 static void dc_mii_sync __P((struct dc_softc *)); 237 static void dc_mii_send __P((struct dc_softc *, u_int32_t, int)); 238 static int dc_mii_readreg __P((struct dc_softc *, struct dc_mii_frame *)); 239 static int dc_mii_writereg __P((struct dc_softc *, struct dc_mii_frame *)); 240 static int dc_miibus_readreg __P((device_t, int, int)); 241 static int dc_miibus_writereg __P((device_t, int, int, int)); 242 static void dc_miibus_statchg __P((device_t)); 243 static void dc_miibus_mediainit __P((device_t)); 244 245 static void dc_setcfg __P((struct dc_softc *, int)); 246 static u_int32_t dc_crc_le __P((struct dc_softc *, caddr_t)); 247 static u_int32_t dc_crc_be __P((caddr_t)); 248 static void dc_setfilt_21143 __P((struct dc_softc *)); 249 static void dc_setfilt_asix __P((struct dc_softc *)); 250 static void dc_setfilt_admtek __P((struct dc_softc *)); 251 252 static void dc_setfilt __P((struct dc_softc *)); 253 254 static void dc_reset __P((struct dc_softc *)); 255 static int dc_list_rx_init __P((struct dc_softc *)); 256 static int dc_list_tx_init __P((struct dc_softc *)); 257 258 #ifdef DC_USEIOSPACE 259 #define DC_RES SYS_RES_IOPORT 260 #define DC_RID DC_PCI_CFBIO 261 #else 262 #define DC_RES SYS_RES_MEMORY 263 #define DC_RID DC_PCI_CFBMA 264 #endif 265 266 static device_method_t dc_methods[] = { 267 /* Device interface */ 268 DEVMETHOD(device_probe, dc_probe), 269 DEVMETHOD(device_attach, dc_attach), 270 DEVMETHOD(device_detach, dc_detach), 271 DEVMETHOD(device_shutdown, dc_shutdown), 272 273 /* bus interface */ 274 DEVMETHOD(bus_print_child, bus_generic_print_child), 275 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 276 277 /* MII interface */ 278 DEVMETHOD(miibus_readreg, dc_miibus_readreg), 279 DEVMETHOD(miibus_writereg, dc_miibus_writereg), 280 DEVMETHOD(miibus_statchg, dc_miibus_statchg), 281 DEVMETHOD(miibus_mediainit, dc_miibus_mediainit), 282 283 { 0, 0 } 284 }; 285 286 static driver_t dc_driver = { 287 "dc", 288 dc_methods, 289 sizeof(struct dc_softc) 290 }; 291 292 static devclass_t dc_devclass; 293 294 DRIVER_MODULE(if_dc, pci, dc_driver, dc_devclass, 0, 0); 295 DRIVER_MODULE(miibus, dc, miibus_driver, miibus_devclass, 0, 0); 296 297 #define DC_SETBIT(sc, reg, x) \ 298 CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) | (x)) 299 300 #define DC_CLRBIT(sc, reg, x) \ 301 CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) & ~(x)) 302 303 #define SIO_SET(x) DC_SETBIT(sc, DC_SIO, (x)) 304 #define SIO_CLR(x) DC_CLRBIT(sc, DC_SIO, (x)) 305 306 static void dc_delay(sc) 307 struct dc_softc *sc; 308 { 309 int idx; 310 311 for (idx = (300 / 33) + 1; idx > 0; idx--) 312 CSR_READ_4(sc, DC_BUSCTL); 313 } 314 315 static void dc_eeprom_idle(sc) 316 struct dc_softc *sc; 317 { 318 register int i; 319 320 CSR_WRITE_4(sc, DC_SIO, DC_SIO_EESEL); 321 dc_delay(sc); 322 DC_SETBIT(sc, DC_SIO, DC_SIO_ROMCTL_READ); 323 dc_delay(sc); 324 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); 325 dc_delay(sc); 326 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CS); 327 dc_delay(sc); 328 329 for (i = 0; i < 25; i++) { 330 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); 331 dc_delay(sc); 332 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CLK); 333 dc_delay(sc); 334 } 335 336 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); 337 dc_delay(sc); 338 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CS); 339 dc_delay(sc); 340 CSR_WRITE_4(sc, DC_SIO, 0x00000000); 341 342 return; 343 } 344 345 /* 346 * Send a read command and address to the EEPROM, check for ACK. 347 */ 348 static void dc_eeprom_putbyte(sc, addr) 349 struct dc_softc *sc; 350 int addr; 351 { 352 register int d, i; 353 354 /* 355 * The AN985 has a 93C66 EEPROM on it instead of 356 * a 93C46. It uses a different bit sequence for 357 * specifying the "read" opcode. 358 */ 359 if (DC_IS_CENTAUR(sc)) 360 d = addr | (DC_EECMD_READ << 2); 361 else 362 d = addr | DC_EECMD_READ; 363 364 /* 365 * Feed in each bit and strobe the clock. 366 */ 367 for (i = 0x400; i; i >>= 1) { 368 if (d & i) { 369 SIO_SET(DC_SIO_EE_DATAIN); 370 } else { 371 SIO_CLR(DC_SIO_EE_DATAIN); 372 } 373 dc_delay(sc); 374 SIO_SET(DC_SIO_EE_CLK); 375 dc_delay(sc); 376 SIO_CLR(DC_SIO_EE_CLK); 377 dc_delay(sc); 378 } 379 380 return; 381 } 382 383 /* 384 * Read a word of data stored in the EEPROM at address 'addr.' 385 * The PNIC 82c168/82c169 has its own non-standard way to read 386 * the EEPROM. 387 */ 388 static void dc_eeprom_getword_pnic(sc, addr, dest) 389 struct dc_softc *sc; 390 int addr; 391 u_int16_t *dest; 392 { 393 register int i; 394 u_int32_t r; 395 396 CSR_WRITE_4(sc, DC_PN_SIOCTL, DC_PN_EEOPCODE_READ|addr); 397 398 for (i = 0; i < DC_TIMEOUT; i++) { 399 DELAY(1); 400 r = CSR_READ_4(sc, DC_SIO); 401 if (!(r & DC_PN_SIOCTL_BUSY)) { 402 *dest = (u_int16_t)(r & 0xFFFF); 403 return; 404 } 405 } 406 407 return; 408 } 409 410 /* 411 * Read a word of data stored in the EEPROM at address 'addr.' 412 */ 413 static void dc_eeprom_getword(sc, addr, dest) 414 struct dc_softc *sc; 415 int addr; 416 u_int16_t *dest; 417 { 418 register int i; 419 u_int16_t word = 0; 420 421 /* Force EEPROM to idle state. */ 422 dc_eeprom_idle(sc); 423 424 /* Enter EEPROM access mode. */ 425 CSR_WRITE_4(sc, DC_SIO, DC_SIO_EESEL); 426 dc_delay(sc); 427 DC_SETBIT(sc, DC_SIO, DC_SIO_ROMCTL_READ); 428 dc_delay(sc); 429 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); 430 dc_delay(sc); 431 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CS); 432 dc_delay(sc); 433 434 /* 435 * Send address of word we want to read. 436 */ 437 dc_eeprom_putbyte(sc, addr); 438 439 /* 440 * Start reading bits from EEPROM. 441 */ 442 for (i = 0x8000; i; i >>= 1) { 443 SIO_SET(DC_SIO_EE_CLK); 444 dc_delay(sc); 445 if (CSR_READ_4(sc, DC_SIO) & DC_SIO_EE_DATAOUT) 446 word |= i; 447 dc_delay(sc); 448 SIO_CLR(DC_SIO_EE_CLK); 449 dc_delay(sc); 450 } 451 452 /* Turn off EEPROM access mode. */ 453 dc_eeprom_idle(sc); 454 455 *dest = word; 456 457 return; 458 } 459 460 /* 461 * Read a sequence of words from the EEPROM. 462 */ 463 static void dc_read_eeprom(sc, dest, off, cnt, swap) 464 struct dc_softc *sc; 465 caddr_t dest; 466 int off; 467 int cnt; 468 int swap; 469 { 470 int i; 471 u_int16_t word = 0, *ptr; 472 473 for (i = 0; i < cnt; i++) { 474 if (DC_IS_PNIC(sc)) 475 dc_eeprom_getword_pnic(sc, off + i, &word); 476 else 477 dc_eeprom_getword(sc, off + i, &word); 478 ptr = (u_int16_t *)(dest + (i * 2)); 479 if (swap) 480 *ptr = ntohs(word); 481 else 482 *ptr = word; 483 } 484 485 return; 486 } 487 488 /* 489 * The following two routines are taken from the Macronix 98713 490 * Application Notes pp.19-21. 491 */ 492 /* 493 * Write a bit to the MII bus. 494 */ 495 static void dc_mii_writebit(sc, bit) 496 struct dc_softc *sc; 497 int bit; 498 { 499 if (bit) 500 CSR_WRITE_4(sc, DC_SIO, 501 DC_SIO_ROMCTL_WRITE|DC_SIO_MII_DATAOUT); 502 else 503 CSR_WRITE_4(sc, DC_SIO, DC_SIO_ROMCTL_WRITE); 504 505 DC_SETBIT(sc, DC_SIO, DC_SIO_MII_CLK); 506 DC_CLRBIT(sc, DC_SIO, DC_SIO_MII_CLK); 507 508 return; 509 } 510 511 /* 512 * Read a bit from the MII bus. 513 */ 514 static int dc_mii_readbit(sc) 515 struct dc_softc *sc; 516 { 517 CSR_WRITE_4(sc, DC_SIO, DC_SIO_ROMCTL_READ|DC_SIO_MII_DIR); 518 CSR_READ_4(sc, DC_SIO); 519 DC_SETBIT(sc, DC_SIO, DC_SIO_MII_CLK); 520 DC_CLRBIT(sc, DC_SIO, DC_SIO_MII_CLK); 521 if (CSR_READ_4(sc, DC_SIO) & DC_SIO_MII_DATAIN) 522 return(1); 523 524 return(0); 525 } 526 527 /* 528 * Sync the PHYs by setting data bit and strobing the clock 32 times. 529 */ 530 static void dc_mii_sync(sc) 531 struct dc_softc *sc; 532 { 533 register int i; 534 535 CSR_WRITE_4(sc, DC_SIO, DC_SIO_ROMCTL_WRITE); 536 537 for (i = 0; i < 32; i++) 538 dc_mii_writebit(sc, 1); 539 540 return; 541 } 542 543 /* 544 * Clock a series of bits through the MII. 545 */ 546 static void dc_mii_send(sc, bits, cnt) 547 struct dc_softc *sc; 548 u_int32_t bits; 549 int cnt; 550 { 551 int i; 552 553 for (i = (0x1 << (cnt - 1)); i; i >>= 1) 554 dc_mii_writebit(sc, bits & i); 555 } 556 557 /* 558 * Read an PHY register through the MII. 559 */ 560 static int dc_mii_readreg(sc, frame) 561 struct dc_softc *sc; 562 struct dc_mii_frame *frame; 563 564 { 565 int i, ack, s; 566 567 s = splimp(); 568 569 /* 570 * Set up frame for RX. 571 */ 572 frame->mii_stdelim = DC_MII_STARTDELIM; 573 frame->mii_opcode = DC_MII_READOP; 574 frame->mii_turnaround = 0; 575 frame->mii_data = 0; 576 577 /* 578 * Sync the PHYs. 579 */ 580 dc_mii_sync(sc); 581 582 /* 583 * Send command/address info. 584 */ 585 dc_mii_send(sc, frame->mii_stdelim, 2); 586 dc_mii_send(sc, frame->mii_opcode, 2); 587 dc_mii_send(sc, frame->mii_phyaddr, 5); 588 dc_mii_send(sc, frame->mii_regaddr, 5); 589 590 #ifdef notdef 591 /* Idle bit */ 592 dc_mii_writebit(sc, 1); 593 dc_mii_writebit(sc, 0); 594 #endif 595 596 /* Check for ack */ 597 ack = dc_mii_readbit(sc); 598 599 /* 600 * Now try reading data bits. If the ack failed, we still 601 * need to clock through 16 cycles to keep the PHY(s) in sync. 602 */ 603 if (ack) { 604 for(i = 0; i < 16; i++) { 605 dc_mii_readbit(sc); 606 } 607 goto fail; 608 } 609 610 for (i = 0x8000; i; i >>= 1) { 611 if (!ack) { 612 if (dc_mii_readbit(sc)) 613 frame->mii_data |= i; 614 } 615 } 616 617 fail: 618 619 dc_mii_writebit(sc, 0); 620 dc_mii_writebit(sc, 0); 621 622 splx(s); 623 624 if (ack) 625 return(1); 626 return(0); 627 } 628 629 /* 630 * Write to a PHY register through the MII. 631 */ 632 static int dc_mii_writereg(sc, frame) 633 struct dc_softc *sc; 634 struct dc_mii_frame *frame; 635 636 { 637 int s; 638 639 s = splimp(); 640 /* 641 * Set up frame for TX. 642 */ 643 644 frame->mii_stdelim = DC_MII_STARTDELIM; 645 frame->mii_opcode = DC_MII_WRITEOP; 646 frame->mii_turnaround = DC_MII_TURNAROUND; 647 648 /* 649 * Sync the PHYs. 650 */ 651 dc_mii_sync(sc); 652 653 dc_mii_send(sc, frame->mii_stdelim, 2); 654 dc_mii_send(sc, frame->mii_opcode, 2); 655 dc_mii_send(sc, frame->mii_phyaddr, 5); 656 dc_mii_send(sc, frame->mii_regaddr, 5); 657 dc_mii_send(sc, frame->mii_turnaround, 2); 658 dc_mii_send(sc, frame->mii_data, 16); 659 660 /* Idle bit. */ 661 dc_mii_writebit(sc, 0); 662 dc_mii_writebit(sc, 0); 663 664 splx(s); 665 666 return(0); 667 } 668 669 static int dc_miibus_readreg(dev, phy, reg) 670 device_t dev; 671 int phy, reg; 672 { 673 struct dc_mii_frame frame; 674 struct dc_softc *sc; 675 int i, rval, phy_reg; 676 677 sc = device_get_softc(dev); 678 bzero((char *)&frame, sizeof(frame)); 679 680 /* 681 * Note: both the AL981 and AN985 have internal PHYs, 682 * however the AL981 provides direct access to the PHY 683 * registers while the AN985 uses a serial MII interface. 684 * The AN985's MII interface is also buggy in that you 685 * can read from any MII address (0 to 31), but only address 1 686 * behaves normally. To deal with both cases, we pretend 687 * that the PHY is at MII address 1. 688 */ 689 if (DC_IS_ADMTEK(sc) && phy != DC_ADMTEK_PHYADDR) 690 return(0); 691 692 if (sc->dc_pmode == DC_PMODE_SYM) { 693 if (phy == (MII_NPHY - 1)) { 694 switch(reg) { 695 case MII_BMSR: 696 /* 697 * Fake something to make the probe 698 * code think there's a PHY here. 699 */ 700 return(BMSR_MEDIAMASK); 701 break; 702 case MII_PHYIDR1: 703 if (DC_IS_PNIC(sc)) 704 return(DC_VENDORID_LO); 705 return(DC_VENDORID_DEC); 706 break; 707 case MII_PHYIDR2: 708 if (DC_IS_PNIC(sc)) 709 return(DC_DEVICEID_82C168); 710 return(DC_DEVICEID_21143); 711 break; 712 default: 713 return(0); 714 break; 715 } 716 } else 717 return(0); 718 } 719 720 if (DC_IS_PNIC(sc)) { 721 CSR_WRITE_4(sc, DC_PN_MII, DC_PN_MIIOPCODE_READ | 722 (phy << 23) | (reg << 18)); 723 for (i = 0; i < DC_TIMEOUT; i++) { 724 DELAY(1); 725 rval = CSR_READ_4(sc, DC_PN_MII); 726 if (!(rval & DC_PN_MII_BUSY)) { 727 rval &= 0xFFFF; 728 return(rval == 0xFFFF ? 0 : rval); 729 } 730 } 731 return(0); 732 } 733 734 if (DC_IS_COMET(sc)) { 735 switch(reg) { 736 case MII_BMCR: 737 phy_reg = DC_AL_BMCR; 738 break; 739 case MII_BMSR: 740 phy_reg = DC_AL_BMSR; 741 break; 742 case MII_PHYIDR1: 743 phy_reg = DC_AL_VENID; 744 break; 745 case MII_PHYIDR2: 746 phy_reg = DC_AL_DEVID; 747 break; 748 case MII_ANAR: 749 phy_reg = DC_AL_ANAR; 750 break; 751 case MII_ANLPAR: 752 phy_reg = DC_AL_LPAR; 753 break; 754 case MII_ANER: 755 phy_reg = DC_AL_ANER; 756 break; 757 default: 758 printf("dc%d: phy_read: bad phy register %x\n", 759 sc->dc_unit, reg); 760 return(0); 761 break; 762 } 763 764 rval = CSR_READ_4(sc, phy_reg) & 0x0000FFFF; 765 766 if (rval == 0xFFFF) 767 return(0); 768 return(rval); 769 } 770 771 frame.mii_phyaddr = phy; 772 frame.mii_regaddr = reg; 773 phy_reg = CSR_READ_4(sc, DC_NETCFG); 774 CSR_WRITE_4(sc, DC_NETCFG, phy_reg & ~DC_NETCFG_PORTSEL); 775 dc_mii_readreg(sc, &frame); 776 CSR_WRITE_4(sc, DC_NETCFG, phy_reg); 777 778 return(frame.mii_data); 779 } 780 781 static int dc_miibus_writereg(dev, phy, reg, data) 782 device_t dev; 783 int phy, reg, data; 784 { 785 struct dc_softc *sc; 786 struct dc_mii_frame frame; 787 int i, phy_reg; 788 789 sc = device_get_softc(dev); 790 bzero((char *)&frame, sizeof(frame)); 791 792 if (DC_IS_ADMTEK(sc) && phy != DC_ADMTEK_PHYADDR) 793 return(0); 794 795 if (DC_IS_PNIC(sc)) { 796 CSR_WRITE_4(sc, DC_PN_MII, DC_PN_MIIOPCODE_WRITE | 797 (phy << 23) | (reg << 10) | data); 798 for (i = 0; i < DC_TIMEOUT; i++) { 799 if (!(CSR_READ_4(sc, DC_PN_MII) & DC_PN_MII_BUSY)) 800 break; 801 } 802 return(0); 803 } 804 805 if (DC_IS_COMET(sc)) { 806 switch(reg) { 807 case MII_BMCR: 808 phy_reg = DC_AL_BMCR; 809 break; 810 case MII_BMSR: 811 phy_reg = DC_AL_BMSR; 812 break; 813 case MII_PHYIDR1: 814 phy_reg = DC_AL_VENID; 815 break; 816 case MII_PHYIDR2: 817 phy_reg = DC_AL_DEVID; 818 break; 819 case MII_ANAR: 820 phy_reg = DC_AL_ANAR; 821 break; 822 case MII_ANLPAR: 823 phy_reg = DC_AL_LPAR; 824 break; 825 case MII_ANER: 826 phy_reg = DC_AL_ANER; 827 break; 828 default: 829 printf("dc%d: phy_write: bad phy register %x\n", 830 sc->dc_unit, reg); 831 return(0); 832 break; 833 } 834 835 CSR_WRITE_4(sc, phy_reg, data); 836 return(0); 837 } 838 839 frame.mii_phyaddr = phy; 840 frame.mii_regaddr = reg; 841 frame.mii_data = data; 842 843 phy_reg = CSR_READ_4(sc, DC_NETCFG); 844 CSR_WRITE_4(sc, DC_NETCFG, phy_reg & ~DC_NETCFG_PORTSEL); 845 dc_mii_writereg(sc, &frame); 846 CSR_WRITE_4(sc, DC_NETCFG, phy_reg); 847 848 return(0); 849 } 850 851 static void dc_miibus_statchg(dev) 852 device_t dev; 853 { 854 struct dc_softc *sc; 855 struct mii_data *mii; 856 struct ifmedia *ifm; 857 858 sc = device_get_softc(dev); 859 if (DC_IS_ADMTEK(sc)) 860 return; 861 mii = device_get_softc(sc->dc_miibus); 862 ifm = &mii->mii_media; 863 if (DC_IS_DAVICOM(sc) && 864 IFM_SUBTYPE(ifm->ifm_media) == IFM_homePNA) { 865 dc_setcfg(sc, ifm->ifm_media); 866 sc->dc_if_media = ifm->ifm_media; 867 } else { 868 dc_setcfg(sc, mii->mii_media_active); 869 sc->dc_if_media = mii->mii_media_active; 870 } 871 872 return; 873 } 874 875 /* 876 * Special support for DM9102A cards with HomePNA PHYs. Note: 877 * with the Davicom DM9102A/DM9801 eval board that I have, it seems 878 * to be impossible to talk to the management interface of the DM9801 879 * PHY (its MDIO pin is not connected to anything). Consequently, 880 * the driver has to just 'know' about the additional mode and deal 881 * with it itself. *sigh* 882 */ 883 static void dc_miibus_mediainit(dev) 884 device_t dev; 885 { 886 struct dc_softc *sc; 887 struct mii_data *mii; 888 struct ifmedia *ifm; 889 int rev; 890 891 rev = pci_read_config(dev, DC_PCI_CFRV, 4) & 0xFF; 892 893 sc = device_get_softc(dev); 894 mii = device_get_softc(sc->dc_miibus); 895 ifm = &mii->mii_media; 896 897 if (DC_IS_DAVICOM(sc) && rev >= DC_REVISION_DM9102A) 898 ifmedia_add(ifm, IFM_ETHER|IFM_homePNA, 0, NULL); 899 900 return; 901 } 902 903 #define DC_POLY 0xEDB88320 904 #define DC_BITS 9 905 #define DC_BITS_PNIC_II 7 906 907 static u_int32_t dc_crc_le(sc, addr) 908 struct dc_softc *sc; 909 caddr_t addr; 910 { 911 u_int32_t idx, bit, data, crc; 912 913 /* Compute CRC for the address value. */ 914 crc = 0xFFFFFFFF; /* initial value */ 915 916 for (idx = 0; idx < 6; idx++) { 917 for (data = *addr++, bit = 0; bit < 8; bit++, data >>= 1) 918 crc = (crc >> 1) ^ (((crc ^ data) & 1) ? DC_POLY : 0); 919 } 920 921 /* The hash table on the PNIC II is only 128 bits wide. */ 922 if (DC_IS_PNICII(sc)) 923 return (crc & ((1 << DC_BITS_PNIC_II) - 1)); 924 925 return (crc & ((1 << DC_BITS) - 1)); 926 } 927 928 /* 929 * Calculate CRC of a multicast group address, return the lower 6 bits. 930 */ 931 static u_int32_t dc_crc_be(addr) 932 caddr_t addr; 933 { 934 u_int32_t crc, carry; 935 int i, j; 936 u_int8_t c; 937 938 /* Compute CRC for the address value. */ 939 crc = 0xFFFFFFFF; /* initial value */ 940 941 for (i = 0; i < 6; i++) { 942 c = *(addr + i); 943 for (j = 0; j < 8; j++) { 944 carry = ((crc & 0x80000000) ? 1 : 0) ^ (c & 0x01); 945 crc <<= 1; 946 c >>= 1; 947 if (carry) 948 crc = (crc ^ 0x04c11db6) | carry; 949 } 950 } 951 952 /* return the filter bit position */ 953 return((crc >> 26) & 0x0000003F); 954 } 955 956 /* 957 * 21143-style RX filter setup routine. Filter programming is done by 958 * downloading a special setup frame into the TX engine. 21143, Macronix, 959 * PNIC, PNIC II and Davicom chips are programmed this way. 960 * 961 * We always program the chip using 'hash perfect' mode, i.e. one perfect 962 * address (our node address) and a 512-bit hash filter for multicast 963 * frames. We also sneak the broadcast address into the hash filter since 964 * we need that too. 965 */ 966 void dc_setfilt_21143(sc) 967 struct dc_softc *sc; 968 { 969 struct dc_desc *sframe; 970 u_int32_t h, *sp; 971 struct ifmultiaddr *ifma; 972 struct ifnet *ifp; 973 int i; 974 975 ifp = &sc->arpcom.ac_if; 976 977 i = sc->dc_cdata.dc_tx_prod; 978 DC_INC(sc->dc_cdata.dc_tx_prod, DC_TX_LIST_CNT); 979 sc->dc_cdata.dc_tx_cnt++; 980 sframe = &sc->dc_ldata->dc_tx_list[i]; 981 sp = (u_int32_t *)&sc->dc_cdata.dc_sbuf; 982 bzero((char *)sp, DC_SFRAME_LEN); 983 984 sframe->dc_data = vtophys(&sc->dc_cdata.dc_sbuf); 985 sframe->dc_ctl = DC_SFRAME_LEN | DC_TXCTL_SETUP | DC_TXCTL_TLINK | 986 DC_FILTER_HASHPERF | DC_TXCTL_FINT; 987 988 sc->dc_cdata.dc_tx_chain[i] = (struct mbuf *)&sc->dc_cdata.dc_sbuf; 989 990 /* If we want promiscuous mode, set the allframes bit. */ 991 if (ifp->if_flags & IFF_PROMISC) 992 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC); 993 else 994 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC); 995 996 if (ifp->if_flags & IFF_ALLMULTI) 997 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI); 998 else 999 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI); 1000 1001 for (ifma = ifp->if_multiaddrs.lh_first; ifma != NULL; 1002 ifma = ifma->ifma_link.le_next) { 1003 if (ifma->ifma_addr->sa_family != AF_LINK) 1004 continue; 1005 h = dc_crc_le(sc, 1006 LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 1007 sp[h >> 4] |= 1 << (h & 0xF); 1008 } 1009 1010 if (ifp->if_flags & IFF_BROADCAST) { 1011 h = dc_crc_le(sc, (caddr_t)ðerbroadcastaddr); 1012 sp[h >> 4] |= 1 << (h & 0xF); 1013 } 1014 1015 /* Set our MAC address */ 1016 sp[39] = ((u_int16_t *)sc->arpcom.ac_enaddr)[0]; 1017 sp[40] = ((u_int16_t *)sc->arpcom.ac_enaddr)[1]; 1018 sp[41] = ((u_int16_t *)sc->arpcom.ac_enaddr)[2]; 1019 1020 sframe->dc_status = DC_TXSTAT_OWN; 1021 CSR_WRITE_4(sc, DC_TXSTART, 0xFFFFFFFF); 1022 1023 /* 1024 * The PNIC takes an exceedingly long time to process its 1025 * setup frame; wait 10ms after posting the setup frame 1026 * before proceeding, just so it has time to swallow its 1027 * medicine. 1028 */ 1029 DELAY(10000); 1030 1031 ifp->if_timer = 5; 1032 1033 return; 1034 } 1035 1036 void dc_setfilt_admtek(sc) 1037 struct dc_softc *sc; 1038 { 1039 struct ifnet *ifp; 1040 int h = 0; 1041 u_int32_t hashes[2] = { 0, 0 }; 1042 struct ifmultiaddr *ifma; 1043 1044 ifp = &sc->arpcom.ac_if; 1045 1046 /* Init our MAC address */ 1047 CSR_WRITE_4(sc, DC_AL_PAR0, *(u_int32_t *)(&sc->arpcom.ac_enaddr[0])); 1048 CSR_WRITE_4(sc, DC_AL_PAR1, *(u_int32_t *)(&sc->arpcom.ac_enaddr[4])); 1049 1050 /* If we want promiscuous mode, set the allframes bit. */ 1051 if (ifp->if_flags & IFF_PROMISC) 1052 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC); 1053 else 1054 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC); 1055 1056 if (ifp->if_flags & IFF_ALLMULTI) 1057 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI); 1058 else 1059 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI); 1060 1061 /* first, zot all the existing hash bits */ 1062 CSR_WRITE_4(sc, DC_AL_MAR0, 0); 1063 CSR_WRITE_4(sc, DC_AL_MAR1, 0); 1064 1065 /* 1066 * If we're already in promisc or allmulti mode, we 1067 * don't have to bother programming the multicast filter. 1068 */ 1069 if (ifp->if_flags & (IFF_PROMISC|IFF_ALLMULTI)) 1070 return; 1071 1072 /* now program new ones */ 1073 for (ifma = ifp->if_multiaddrs.lh_first; ifma != NULL; 1074 ifma = ifma->ifma_link.le_next) { 1075 if (ifma->ifma_addr->sa_family != AF_LINK) 1076 continue; 1077 h = dc_crc_be(LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 1078 if (h < 32) 1079 hashes[0] |= (1 << h); 1080 else 1081 hashes[1] |= (1 << (h - 32)); 1082 } 1083 1084 CSR_WRITE_4(sc, DC_AL_MAR0, hashes[0]); 1085 CSR_WRITE_4(sc, DC_AL_MAR1, hashes[1]); 1086 1087 return; 1088 } 1089 1090 void dc_setfilt_asix(sc) 1091 struct dc_softc *sc; 1092 { 1093 struct ifnet *ifp; 1094 int h = 0; 1095 u_int32_t hashes[2] = { 0, 0 }; 1096 struct ifmultiaddr *ifma; 1097 1098 ifp = &sc->arpcom.ac_if; 1099 1100 /* Init our MAC address */ 1101 CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_PAR0); 1102 CSR_WRITE_4(sc, DC_AX_FILTDATA, 1103 *(u_int32_t *)(&sc->arpcom.ac_enaddr[0])); 1104 CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_PAR1); 1105 CSR_WRITE_4(sc, DC_AX_FILTDATA, 1106 *(u_int32_t *)(&sc->arpcom.ac_enaddr[4])); 1107 1108 /* If we want promiscuous mode, set the allframes bit. */ 1109 if (ifp->if_flags & IFF_PROMISC) 1110 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC); 1111 else 1112 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC); 1113 1114 if (ifp->if_flags & IFF_ALLMULTI) 1115 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI); 1116 else 1117 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI); 1118 1119 /* 1120 * The ASIX chip has a special bit to enable reception 1121 * of broadcast frames. 1122 */ 1123 if (ifp->if_flags & IFF_BROADCAST) 1124 DC_SETBIT(sc, DC_NETCFG, DC_AX_NETCFG_RX_BROAD); 1125 else 1126 DC_CLRBIT(sc, DC_NETCFG, DC_AX_NETCFG_RX_BROAD); 1127 1128 /* first, zot all the existing hash bits */ 1129 CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_MAR0); 1130 CSR_WRITE_4(sc, DC_AX_FILTDATA, 0); 1131 CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_MAR1); 1132 CSR_WRITE_4(sc, DC_AX_FILTDATA, 0); 1133 1134 /* 1135 * If we're already in promisc or allmulti mode, we 1136 * don't have to bother programming the multicast filter. 1137 */ 1138 if (ifp->if_flags & (IFF_PROMISC|IFF_ALLMULTI)) 1139 return; 1140 1141 /* now program new ones */ 1142 for (ifma = ifp->if_multiaddrs.lh_first; ifma != NULL; 1143 ifma = ifma->ifma_link.le_next) { 1144 if (ifma->ifma_addr->sa_family != AF_LINK) 1145 continue; 1146 h = dc_crc_be(LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 1147 if (h < 32) 1148 hashes[0] |= (1 << h); 1149 else 1150 hashes[1] |= (1 << (h - 32)); 1151 } 1152 1153 CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_MAR0); 1154 CSR_WRITE_4(sc, DC_AX_FILTDATA, hashes[0]); 1155 CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_MAR1); 1156 CSR_WRITE_4(sc, DC_AX_FILTDATA, hashes[1]); 1157 1158 return; 1159 } 1160 1161 static void dc_setfilt(sc) 1162 struct dc_softc *sc; 1163 { 1164 if (DC_IS_INTEL(sc) || DC_IS_MACRONIX(sc) || DC_IS_PNIC(sc) || 1165 DC_IS_PNICII(sc) || DC_IS_DAVICOM(sc)) 1166 dc_setfilt_21143(sc); 1167 1168 if (DC_IS_ASIX(sc)) 1169 dc_setfilt_asix(sc); 1170 1171 if (DC_IS_ADMTEK(sc)) 1172 dc_setfilt_admtek(sc); 1173 1174 return; 1175 } 1176 1177 /* 1178 * In order to fiddle with the 1179 * 'full-duplex' and '100Mbps' bits in the netconfig register, we 1180 * first have to put the transmit and/or receive logic in the idle state. 1181 */ 1182 static void dc_setcfg(sc, media) 1183 struct dc_softc *sc; 1184 int media; 1185 { 1186 int i, restart = 0; 1187 u_int32_t isr; 1188 1189 if (IFM_SUBTYPE(media) == IFM_NONE) 1190 return; 1191 1192 if (CSR_READ_4(sc, DC_NETCFG) & (DC_NETCFG_TX_ON|DC_NETCFG_RX_ON)) { 1193 restart = 1; 1194 DC_CLRBIT(sc, DC_NETCFG, (DC_NETCFG_TX_ON|DC_NETCFG_RX_ON)); 1195 1196 for (i = 0; i < DC_TIMEOUT; i++) { 1197 DELAY(10); 1198 isr = CSR_READ_4(sc, DC_ISR); 1199 if (isr & DC_ISR_TX_IDLE || 1200 (isr & DC_ISR_RX_STATE) == DC_RXSTATE_STOPPED) 1201 break; 1202 } 1203 1204 if (i == DC_TIMEOUT) 1205 printf("dc%d: failed to force tx and " 1206 "rx to idle state\n", sc->dc_unit); 1207 1208 } 1209 1210 if (IFM_SUBTYPE(media) == IFM_100_TX) { 1211 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_SPEEDSEL); 1212 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_HEARTBEAT); 1213 if (sc->dc_pmode == DC_PMODE_MII) { 1214 DC_SETBIT(sc, DC_WATCHDOG, DC_WDOG_JABBERDIS); 1215 DC_CLRBIT(sc, DC_NETCFG, (DC_NETCFG_PCS| 1216 DC_NETCFG_PORTSEL|DC_NETCFG_SCRAMBLER)); 1217 if (sc->dc_type == DC_TYPE_98713) 1218 DC_SETBIT(sc, DC_NETCFG, (DC_NETCFG_PCS| 1219 DC_NETCFG_SCRAMBLER)); 1220 if (!DC_IS_DAVICOM(sc)) 1221 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL); 1222 DC_CLRBIT(sc, DC_10BTCTRL, 0xFFFF); 1223 } else { 1224 if (DC_IS_PNIC(sc)) { 1225 DC_PN_GPIO_SETBIT(sc, DC_PN_GPIO_SPEEDSEL); 1226 DC_PN_GPIO_SETBIT(sc, DC_PN_GPIO_100TX_LOOP); 1227 DC_SETBIT(sc, DC_PN_NWAY, DC_PN_NWAY_SPEEDSEL); 1228 } 1229 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL| 1230 DC_NETCFG_PCS|DC_NETCFG_SCRAMBLER); 1231 } 1232 } 1233 1234 if (IFM_SUBTYPE(media) == IFM_10_T) { 1235 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_SPEEDSEL); 1236 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_HEARTBEAT); 1237 if (sc->dc_pmode == DC_PMODE_MII) { 1238 DC_SETBIT(sc, DC_WATCHDOG, DC_WDOG_JABBERDIS); 1239 DC_CLRBIT(sc, DC_NETCFG, (DC_NETCFG_PCS| 1240 DC_NETCFG_PORTSEL|DC_NETCFG_SCRAMBLER)); 1241 if (sc->dc_type == DC_TYPE_98713) 1242 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PCS); 1243 if (!DC_IS_DAVICOM(sc)) 1244 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL); 1245 DC_CLRBIT(sc, DC_10BTCTRL, 0xFFFF); 1246 } else { 1247 if (DC_IS_PNIC(sc)) { 1248 DC_PN_GPIO_CLRBIT(sc, DC_PN_GPIO_SPEEDSEL); 1249 DC_PN_GPIO_SETBIT(sc, DC_PN_GPIO_100TX_LOOP); 1250 DC_CLRBIT(sc, DC_PN_NWAY, DC_PN_NWAY_SPEEDSEL); 1251 } 1252 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL); 1253 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_SCRAMBLER); 1254 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PCS); 1255 } 1256 } 1257 1258 /* 1259 * If this is a Davicom DM9102A card with a DM9801 HomePNA 1260 * PHY and we want HomePNA mode, set the portsel bit to turn 1261 * on the external MII port. 1262 */ 1263 if (DC_IS_DAVICOM(sc)) { 1264 if (IFM_SUBTYPE(media) == IFM_homePNA) { 1265 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL); 1266 sc->dc_link = 1; 1267 } else { 1268 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL); 1269 } 1270 } 1271 1272 if ((media & IFM_GMASK) == IFM_FDX) { 1273 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_FULLDUPLEX); 1274 if (sc->dc_pmode == DC_PMODE_SYM && DC_IS_PNIC(sc)) 1275 DC_SETBIT(sc, DC_PN_NWAY, DC_PN_NWAY_DUPLEX); 1276 } else { 1277 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_FULLDUPLEX); 1278 if (sc->dc_pmode == DC_PMODE_SYM && DC_IS_PNIC(sc)) 1279 DC_CLRBIT(sc, DC_PN_NWAY, DC_PN_NWAY_DUPLEX); 1280 } 1281 1282 if (restart) 1283 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_TX_ON|DC_NETCFG_RX_ON); 1284 1285 return; 1286 } 1287 1288 static void dc_reset(sc) 1289 struct dc_softc *sc; 1290 { 1291 register int i; 1292 1293 DC_SETBIT(sc, DC_BUSCTL, DC_BUSCTL_RESET); 1294 1295 for (i = 0; i < DC_TIMEOUT; i++) { 1296 DELAY(10); 1297 if (!(CSR_READ_4(sc, DC_BUSCTL) & DC_BUSCTL_RESET)) 1298 break; 1299 } 1300 1301 if (DC_IS_ASIX(sc) || DC_IS_ADMTEK(sc)) { 1302 DELAY(10000); 1303 DC_CLRBIT(sc, DC_BUSCTL, DC_BUSCTL_RESET); 1304 i = 0; 1305 } 1306 1307 if (i == DC_TIMEOUT) 1308 printf("dc%d: reset never completed!\n", sc->dc_unit); 1309 1310 /* Wait a little while for the chip to get its brains in order. */ 1311 DELAY(1000); 1312 1313 CSR_WRITE_4(sc, DC_IMR, 0x00000000); 1314 CSR_WRITE_4(sc, DC_BUSCTL, 0x00000000); 1315 CSR_WRITE_4(sc, DC_NETCFG, 0x00000000); 1316 1317 /* 1318 * Bring the SIA out of reset. In some cases, it looks 1319 * like failing to unreset the SIA soon enough gets it 1320 * into a state where it will never come out of reset 1321 * until we reset the whole chip again. 1322 */ 1323 if (DC_IS_INTEL(sc)) 1324 DC_SETBIT(sc, DC_SIARESET, DC_SIA_RESET); 1325 1326 return; 1327 } 1328 1329 static struct dc_type *dc_devtype(dev) 1330 device_t dev; 1331 { 1332 struct dc_type *t; 1333 u_int32_t rev; 1334 1335 t = dc_devs; 1336 1337 while(t->dc_name != NULL) { 1338 if ((pci_get_vendor(dev) == t->dc_vid) && 1339 (pci_get_device(dev) == t->dc_did)) { 1340 /* Check the PCI revision */ 1341 rev = pci_read_config(dev, DC_PCI_CFRV, 4) & 0xFF; 1342 if (t->dc_did == DC_DEVICEID_98713 && 1343 rev >= DC_REVISION_98713A) 1344 t++; 1345 if (t->dc_did == DC_DEVICEID_98713_CP && 1346 rev >= DC_REVISION_98713A) 1347 t++; 1348 if (t->dc_did == DC_DEVICEID_987x5 && 1349 rev >= DC_REVISION_98725) 1350 t++; 1351 if (t->dc_did == DC_DEVICEID_AX88140A && 1352 rev >= DC_REVISION_88141) 1353 t++; 1354 if (t->dc_did == DC_DEVICEID_82C168 && 1355 rev >= DC_REVISION_82C169) 1356 t++; 1357 if (t->dc_did == DC_DEVICEID_DM9102 && 1358 rev >= DC_REVISION_DM9102A) 1359 t++; 1360 return(t); 1361 } 1362 t++; 1363 } 1364 1365 return(NULL); 1366 } 1367 1368 /* 1369 * Probe for a 21143 or clone chip. Check the PCI vendor and device 1370 * IDs against our list and return a device name if we find a match. 1371 * We do a little bit of extra work to identify the exact type of 1372 * chip. The MX98713 and MX98713A have the same PCI vendor/device ID, 1373 * but different revision IDs. The same is true for 98715/98715A 1374 * chips and the 98725, as well as the ASIX and ADMtek chips. In some 1375 * cases, the exact chip revision affects driver behavior. 1376 */ 1377 static int dc_probe(dev) 1378 device_t dev; 1379 { 1380 struct dc_type *t; 1381 1382 t = dc_devtype(dev); 1383 1384 if (t != NULL) { 1385 device_set_desc(dev, t->dc_name); 1386 return(0); 1387 } 1388 1389 return(ENXIO); 1390 } 1391 1392 static void dc_acpi(dev) 1393 device_t dev; 1394 { 1395 u_int32_t r, cptr; 1396 int unit; 1397 1398 unit = device_get_unit(dev); 1399 1400 /* Find the location of the capabilities block */ 1401 cptr = pci_read_config(dev, DC_PCI_CCAP, 4) & 0xFF; 1402 1403 r = pci_read_config(dev, cptr, 4) & 0xFF; 1404 if (r == 0x01) { 1405 1406 r = pci_read_config(dev, cptr + 4, 4); 1407 if (r & DC_PSTATE_D3) { 1408 u_int32_t iobase, membase, irq; 1409 1410 /* Save important PCI config data. */ 1411 iobase = pci_read_config(dev, DC_PCI_CFBIO, 4); 1412 membase = pci_read_config(dev, DC_PCI_CFBMA, 4); 1413 irq = pci_read_config(dev, DC_PCI_CFIT, 4); 1414 1415 /* Reset the power state. */ 1416 printf("dc%d: chip is in D%d power mode " 1417 "-- setting to D0\n", unit, r & DC_PSTATE_D3); 1418 r &= 0xFFFFFFFC; 1419 pci_write_config(dev, cptr + 4, r, 4); 1420 1421 /* Restore PCI config data. */ 1422 pci_write_config(dev, DC_PCI_CFBIO, iobase, 4); 1423 pci_write_config(dev, DC_PCI_CFBMA, membase, 4); 1424 pci_write_config(dev, DC_PCI_CFIT, irq, 4); 1425 } 1426 } 1427 return; 1428 } 1429 1430 /* 1431 * Attach the interface. Allocate softc structures, do ifmedia 1432 * setup and ethernet/BPF attach. 1433 */ 1434 static int dc_attach(dev) 1435 device_t dev; 1436 { 1437 int s; 1438 u_char eaddr[ETHER_ADDR_LEN]; 1439 u_int32_t command; 1440 struct dc_softc *sc; 1441 struct ifnet *ifp; 1442 u_int32_t revision; 1443 int unit, error = 0, rid, mac_offset; 1444 1445 s = splimp(); 1446 1447 sc = device_get_softc(dev); 1448 unit = device_get_unit(dev); 1449 bzero(sc, sizeof(struct dc_softc)); 1450 1451 /* 1452 * Handle power management nonsense. 1453 */ 1454 dc_acpi(dev); 1455 1456 /* 1457 * Map control/status registers. 1458 */ 1459 command = pci_read_config(dev, PCI_COMMAND_STATUS_REG, 4); 1460 command |= (PCIM_CMD_PORTEN|PCIM_CMD_MEMEN|PCIM_CMD_BUSMASTEREN); 1461 pci_write_config(dev, PCI_COMMAND_STATUS_REG, command, 4); 1462 command = pci_read_config(dev, PCI_COMMAND_STATUS_REG, 4); 1463 1464 #ifdef DC_USEIOSPACE 1465 if (!(command & PCIM_CMD_PORTEN)) { 1466 printf("dc%d: failed to enable I/O ports!\n", unit); 1467 error = ENXIO; 1468 goto fail; 1469 } 1470 #else 1471 if (!(command & PCIM_CMD_MEMEN)) { 1472 printf("dc%d: failed to enable memory mapping!\n", unit); 1473 error = ENXIO; 1474 goto fail; 1475 } 1476 #endif 1477 1478 rid = DC_RID; 1479 sc->dc_res = bus_alloc_resource(dev, DC_RES, &rid, 1480 0, ~0, 1, RF_ACTIVE); 1481 1482 if (sc->dc_res == NULL) { 1483 printf("dc%d: couldn't map ports/memory\n", unit); 1484 error = ENXIO; 1485 goto fail; 1486 } 1487 1488 sc->dc_btag = rman_get_bustag(sc->dc_res); 1489 sc->dc_bhandle = rman_get_bushandle(sc->dc_res); 1490 1491 /* Allocate interrupt */ 1492 rid = 0; 1493 sc->dc_irq = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, 0, ~0, 1, 1494 RF_SHAREABLE | RF_ACTIVE); 1495 1496 if (sc->dc_irq == NULL) { 1497 printf("dc%d: couldn't map interrupt\n", unit); 1498 bus_release_resource(dev, DC_RES, DC_RID, sc->dc_res); 1499 error = ENXIO; 1500 goto fail; 1501 } 1502 1503 error = bus_setup_intr(dev, sc->dc_irq, INTR_TYPE_NET, 1504 dc_intr, sc, &sc->dc_intrhand); 1505 1506 if (error) { 1507 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->dc_irq); 1508 bus_release_resource(dev, DC_RES, DC_RID, sc->dc_res); 1509 printf("dc%d: couldn't set up irq\n", unit); 1510 goto fail; 1511 } 1512 1513 /* Need this info to decide on a chip type. */ 1514 sc->dc_info = dc_devtype(dev); 1515 revision = pci_read_config(dev, DC_PCI_CFRV, 4) & 0x000000FF; 1516 1517 switch(sc->dc_info->dc_did) { 1518 case DC_DEVICEID_21143: 1519 sc->dc_type = DC_TYPE_21143; 1520 sc->dc_flags |= DC_TX_POLL|DC_TX_USE_TX_INTR; 1521 sc->dc_flags |= DC_REDUCED_MII_POLL; 1522 break; 1523 case DC_DEVICEID_DM9100: 1524 case DC_DEVICEID_DM9102: 1525 sc->dc_type = DC_TYPE_DM9102; 1526 sc->dc_flags |= DC_TX_COALESCE|DC_TX_USE_TX_INTR; 1527 sc->dc_flags |= DC_REDUCED_MII_POLL; 1528 sc->dc_pmode = DC_PMODE_MII; 1529 break; 1530 case DC_DEVICEID_AL981: 1531 sc->dc_type = DC_TYPE_AL981; 1532 sc->dc_flags |= DC_TX_USE_TX_INTR; 1533 sc->dc_flags |= DC_TX_ADMTEK_WAR; 1534 sc->dc_pmode = DC_PMODE_MII; 1535 break; 1536 case DC_DEVICEID_AN985: 1537 sc->dc_type = DC_TYPE_AN985; 1538 sc->dc_flags |= DC_TX_USE_TX_INTR; 1539 sc->dc_flags |= DC_TX_ADMTEK_WAR; 1540 sc->dc_pmode = DC_PMODE_MII; 1541 break; 1542 case DC_DEVICEID_98713: 1543 case DC_DEVICEID_98713_CP: 1544 if (revision < DC_REVISION_98713A) { 1545 sc->dc_type = DC_TYPE_98713; 1546 sc->dc_flags |= DC_REDUCED_MII_POLL; 1547 } 1548 if (revision >= DC_REVISION_98713A) 1549 sc->dc_type = DC_TYPE_98713A; 1550 sc->dc_flags |= DC_TX_POLL|DC_TX_USE_TX_INTR; 1551 break; 1552 case DC_DEVICEID_987x5: 1553 sc->dc_type = DC_TYPE_987x5; 1554 sc->dc_flags |= DC_TX_POLL|DC_TX_USE_TX_INTR; 1555 break; 1556 case DC_DEVICEID_82C115: 1557 sc->dc_type = DC_TYPE_PNICII; 1558 sc->dc_flags |= DC_TX_POLL|DC_TX_USE_TX_INTR; 1559 break; 1560 case DC_DEVICEID_82C168: 1561 sc->dc_type = DC_TYPE_PNIC; 1562 sc->dc_flags |= DC_TX_STORENFWD|DC_TX_INTR_ALWAYS; 1563 sc->dc_flags |= DC_PNIC_RX_BUG_WAR; 1564 sc->dc_pnic_rx_buf = malloc(DC_RXLEN * 5, M_DEVBUF, M_NOWAIT); 1565 if (revision < DC_REVISION_82C169) 1566 sc->dc_pmode = DC_PMODE_SYM; 1567 break; 1568 case DC_DEVICEID_AX88140A: 1569 sc->dc_type = DC_TYPE_ASIX; 1570 sc->dc_flags |= DC_TX_USE_TX_INTR|DC_TX_INTR_FIRSTFRAG; 1571 sc->dc_flags |= DC_REDUCED_MII_POLL; 1572 sc->dc_pmode = DC_PMODE_MII; 1573 break; 1574 default: 1575 printf("dc%d: unknown device: %x\n", sc->dc_unit, 1576 sc->dc_info->dc_did); 1577 break; 1578 } 1579 1580 /* Save the cache line size. */ 1581 if (DC_IS_DAVICOM(sc)) 1582 sc->dc_cachesize = 0; 1583 else 1584 sc->dc_cachesize = pci_read_config(dev, 1585 DC_PCI_CFLT, 4) & 0xFF; 1586 1587 /* Reset the adapter. */ 1588 dc_reset(sc); 1589 1590 /* Take 21143 out of snooze mode */ 1591 if (DC_IS_INTEL(sc)) { 1592 command = pci_read_config(dev, DC_PCI_CFDD, 4); 1593 command &= ~(DC_CFDD_SNOOZE_MODE|DC_CFDD_SLEEP_MODE); 1594 pci_write_config(dev, DC_PCI_CFDD, command, 4); 1595 } 1596 1597 /* 1598 * Try to learn something about the supported media. 1599 * We know that ASIX and ADMtek and Davicom devices 1600 * will *always* be using MII media, so that's a no-brainer. 1601 * The tricky ones are the Macronix/PNIC II and the 1602 * Intel 21143. 1603 */ 1604 if (DC_IS_INTEL(sc)) { 1605 u_int32_t media, cwuc; 1606 cwuc = pci_read_config(dev, DC_PCI_CWUC, 4); 1607 cwuc |= DC_CWUC_FORCE_WUL; 1608 pci_write_config(dev, DC_PCI_CWUC, cwuc, 4); 1609 DELAY(10000); 1610 media = pci_read_config(dev, DC_PCI_CWUC, 4); 1611 cwuc &= ~DC_CWUC_FORCE_WUL; 1612 pci_write_config(dev, DC_PCI_CWUC, cwuc, 4); 1613 DELAY(10000); 1614 if (media & DC_CWUC_MII_ABILITY) 1615 sc->dc_pmode = DC_PMODE_MII; 1616 if (media & DC_CWUC_SYM_ABILITY) 1617 sc->dc_pmode = DC_PMODE_SYM; 1618 /* 1619 * If none of the bits are set, then this NIC 1620 * isn't meant to support 'wake up LAN' mode. 1621 * This is usually only the case on multiport 1622 * cards, and these cards almost always have 1623 * MII transceivers. 1624 */ 1625 if (media == 0) 1626 sc->dc_pmode = DC_PMODE_MII; 1627 } else if (DC_IS_MACRONIX(sc) || DC_IS_PNICII(sc)) { 1628 if (sc->dc_type == DC_TYPE_98713) 1629 sc->dc_pmode = DC_PMODE_MII; 1630 else 1631 sc->dc_pmode = DC_PMODE_SYM; 1632 } else if (!sc->dc_pmode) 1633 sc->dc_pmode = DC_PMODE_MII; 1634 1635 /* 1636 * Get station address from the EEPROM. 1637 */ 1638 switch(sc->dc_type) { 1639 case DC_TYPE_98713: 1640 case DC_TYPE_98713A: 1641 case DC_TYPE_987x5: 1642 case DC_TYPE_PNICII: 1643 dc_read_eeprom(sc, (caddr_t)&mac_offset, 1644 (DC_EE_NODEADDR_OFFSET / 2), 1, 0); 1645 dc_read_eeprom(sc, (caddr_t)&eaddr, (mac_offset / 2), 3, 0); 1646 break; 1647 case DC_TYPE_PNIC: 1648 dc_read_eeprom(sc, (caddr_t)&eaddr, 0, 3, 1); 1649 break; 1650 case DC_TYPE_DM9102: 1651 case DC_TYPE_21143: 1652 case DC_TYPE_ASIX: 1653 dc_read_eeprom(sc, (caddr_t)&eaddr, DC_EE_NODEADDR, 3, 0); 1654 break; 1655 case DC_TYPE_AL981: 1656 case DC_TYPE_AN985: 1657 dc_read_eeprom(sc, (caddr_t)&eaddr, DC_AL_EE_NODEADDR, 3, 0); 1658 break; 1659 default: 1660 dc_read_eeprom(sc, (caddr_t)&eaddr, DC_EE_NODEADDR, 3, 0); 1661 break; 1662 } 1663 1664 /* 1665 * A 21143 or clone chip was detected. Inform the world. 1666 */ 1667 printf("dc%d: Ethernet address: %6D\n", unit, eaddr, ":"); 1668 1669 sc->dc_unit = unit; 1670 bcopy(eaddr, (char *)&sc->arpcom.ac_enaddr, ETHER_ADDR_LEN); 1671 1672 sc->dc_ldata = contigmalloc(sizeof(struct dc_list_data), M_DEVBUF, 1673 M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0); 1674 1675 if (sc->dc_ldata == NULL) { 1676 printf("dc%d: no memory for list buffers!\n", unit); 1677 bus_teardown_intr(dev, sc->dc_irq, sc->dc_intrhand); 1678 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->dc_irq); 1679 bus_release_resource(dev, DC_RES, DC_RID, sc->dc_res); 1680 error = ENXIO; 1681 goto fail; 1682 } 1683 1684 bzero(sc->dc_ldata, sizeof(struct dc_list_data)); 1685 1686 ifp = &sc->arpcom.ac_if; 1687 ifp->if_softc = sc; 1688 ifp->if_unit = unit; 1689 ifp->if_name = "dc"; 1690 ifp->if_mtu = ETHERMTU; 1691 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 1692 ifp->if_ioctl = dc_ioctl; 1693 ifp->if_output = ether_output; 1694 ifp->if_start = dc_start; 1695 ifp->if_watchdog = dc_watchdog; 1696 ifp->if_init = dc_init; 1697 ifp->if_baudrate = 10000000; 1698 ifp->if_snd.ifq_maxlen = DC_TX_LIST_CNT - 1; 1699 1700 /* 1701 * Do MII setup. 1702 */ 1703 error = mii_phy_probe(dev, &sc->dc_miibus, 1704 dc_ifmedia_upd, dc_ifmedia_sts); 1705 1706 if (error && DC_IS_INTEL(sc)) { 1707 sc->dc_pmode = DC_PMODE_SYM; 1708 mii_phy_probe(dev, &sc->dc_miibus, 1709 dc_ifmedia_upd, dc_ifmedia_sts); 1710 error = 0; 1711 } 1712 1713 if (error) { 1714 printf("dc%d: MII without any PHY!\n", sc->dc_unit); 1715 bus_teardown_intr(dev, sc->dc_irq, sc->dc_intrhand); 1716 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->dc_irq); 1717 bus_release_resource(dev, DC_RES, DC_RID, sc->dc_res); 1718 error = ENXIO; 1719 goto fail; 1720 } 1721 1722 /* 1723 * Call MI attach routines. 1724 */ 1725 if_attach(ifp); 1726 ether_ifattach(ifp); 1727 callout_handle_init(&sc->dc_stat_ch); 1728 1729 bpfattach(ifp, DLT_EN10MB, sizeof(struct ether_header)); 1730 1731 #ifdef __alpha__ 1732 sc->dc_srm_media = 0; 1733 1734 /* Remember the SRM console media setting */ 1735 if (DC_IS_INTEL(sc)) { 1736 command = pci_read_config(dev, DC_PCI_CFDD, 4); 1737 command &= ~(DC_CFDD_SNOOZE_MODE|DC_CFDD_SLEEP_MODE); 1738 switch ((command >> 8) & 0xff) { 1739 case 3: 1740 sc->dc_srm_media = IFM_10_T; 1741 break; 1742 case 4: 1743 sc->dc_srm_media = IFM_10_T | IFM_FDX; 1744 break; 1745 case 5: 1746 sc->dc_srm_media = IFM_100_TX; 1747 break; 1748 case 6: 1749 sc->dc_srm_media = IFM_100_TX | IFM_FDX; 1750 break; 1751 } 1752 if (sc->dc_srm_media) 1753 sc->dc_srm_media |= IFM_ACTIVE | IFM_ETHER; 1754 } 1755 #endif 1756 1757 1758 fail: 1759 splx(s); 1760 1761 return(error); 1762 } 1763 1764 static int dc_detach(dev) 1765 device_t dev; 1766 { 1767 struct dc_softc *sc; 1768 struct ifnet *ifp; 1769 int s; 1770 1771 s = splimp(); 1772 1773 sc = device_get_softc(dev); 1774 ifp = &sc->arpcom.ac_if; 1775 1776 dc_stop(sc); 1777 if_detach(ifp); 1778 1779 bus_generic_detach(dev); 1780 device_delete_child(dev, sc->dc_miibus); 1781 1782 bus_teardown_intr(dev, sc->dc_irq, sc->dc_intrhand); 1783 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->dc_irq); 1784 bus_release_resource(dev, DC_RES, DC_RID, sc->dc_res); 1785 1786 contigfree(sc->dc_ldata, sizeof(struct dc_list_data), M_DEVBUF); 1787 if (sc->dc_pnic_rx_buf != NULL) 1788 free(sc->dc_pnic_rx_buf, M_DEVBUF); 1789 1790 splx(s); 1791 1792 return(0); 1793 } 1794 1795 /* 1796 * Initialize the transmit descriptors. 1797 */ 1798 static int dc_list_tx_init(sc) 1799 struct dc_softc *sc; 1800 { 1801 struct dc_chain_data *cd; 1802 struct dc_list_data *ld; 1803 int i; 1804 1805 cd = &sc->dc_cdata; 1806 ld = sc->dc_ldata; 1807 for (i = 0; i < DC_TX_LIST_CNT; i++) { 1808 if (i == (DC_TX_LIST_CNT - 1)) { 1809 ld->dc_tx_list[i].dc_next = 1810 vtophys(&ld->dc_tx_list[0]); 1811 } else { 1812 ld->dc_tx_list[i].dc_next = 1813 vtophys(&ld->dc_tx_list[i + 1]); 1814 } 1815 cd->dc_tx_chain[i] = NULL; 1816 ld->dc_tx_list[i].dc_data = 0; 1817 ld->dc_tx_list[i].dc_ctl = 0; 1818 } 1819 1820 cd->dc_tx_prod = cd->dc_tx_cons = cd->dc_tx_cnt = 0; 1821 1822 return(0); 1823 } 1824 1825 1826 /* 1827 * Initialize the RX descriptors and allocate mbufs for them. Note that 1828 * we arrange the descriptors in a closed ring, so that the last descriptor 1829 * points back to the first. 1830 */ 1831 static int dc_list_rx_init(sc) 1832 struct dc_softc *sc; 1833 { 1834 struct dc_chain_data *cd; 1835 struct dc_list_data *ld; 1836 int i; 1837 1838 cd = &sc->dc_cdata; 1839 ld = sc->dc_ldata; 1840 1841 for (i = 0; i < DC_RX_LIST_CNT; i++) { 1842 if (dc_newbuf(sc, i, NULL) == ENOBUFS) 1843 return(ENOBUFS); 1844 if (i == (DC_RX_LIST_CNT - 1)) { 1845 ld->dc_rx_list[i].dc_next = 1846 vtophys(&ld->dc_rx_list[0]); 1847 } else { 1848 ld->dc_rx_list[i].dc_next = 1849 vtophys(&ld->dc_rx_list[i + 1]); 1850 } 1851 } 1852 1853 cd->dc_rx_prod = 0; 1854 1855 return(0); 1856 } 1857 1858 /* 1859 * Initialize an RX descriptor and attach an MBUF cluster. 1860 */ 1861 static int dc_newbuf(sc, i, m) 1862 struct dc_softc *sc; 1863 int i; 1864 struct mbuf *m; 1865 { 1866 struct mbuf *m_new = NULL; 1867 struct dc_desc *c; 1868 1869 c = &sc->dc_ldata->dc_rx_list[i]; 1870 1871 if (m == NULL) { 1872 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 1873 if (m_new == NULL) { 1874 printf("dc%d: no memory for rx list " 1875 "-- packet dropped!\n", sc->dc_unit); 1876 return(ENOBUFS); 1877 } 1878 1879 MCLGET(m_new, M_DONTWAIT); 1880 if (!(m_new->m_flags & M_EXT)) { 1881 printf("dc%d: no memory for rx list " 1882 "-- packet dropped!\n", sc->dc_unit); 1883 m_freem(m_new); 1884 return(ENOBUFS); 1885 } 1886 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 1887 } else { 1888 m_new = m; 1889 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 1890 m_new->m_data = m_new->m_ext.ext_buf; 1891 } 1892 1893 m_adj(m_new, sizeof(u_int64_t)); 1894 1895 /* 1896 * If this is a PNIC chip, zero the buffer. This is part 1897 * of the workaround for the receive bug in the 82c168 and 1898 * 82c169 chips. 1899 */ 1900 if (sc->dc_flags & DC_PNIC_RX_BUG_WAR) 1901 bzero((char *)mtod(m_new, char *), m_new->m_len); 1902 1903 sc->dc_cdata.dc_rx_chain[i] = m_new; 1904 c->dc_data = vtophys(mtod(m_new, caddr_t)); 1905 c->dc_ctl = DC_RXCTL_RLINK | DC_RXLEN; 1906 c->dc_status = DC_RXSTAT_OWN; 1907 1908 return(0); 1909 } 1910 1911 /* 1912 * Grrrrr. 1913 * The PNIC chip has a terrible bug in it that manifests itself during 1914 * periods of heavy activity. The exact mode of failure if difficult to 1915 * pinpoint: sometimes it only happens in promiscuous mode, sometimes it 1916 * will happen on slow machines. The bug is that sometimes instead of 1917 * uploading one complete frame during reception, it uploads what looks 1918 * like the entire contents of its FIFO memory. The frame we want is at 1919 * the end of the whole mess, but we never know exactly how much data has 1920 * been uploaded, so salvaging the frame is hard. 1921 * 1922 * There is only one way to do it reliably, and it's disgusting. 1923 * Here's what we know: 1924 * 1925 * - We know there will always be somewhere between one and three extra 1926 * descriptors uploaded. 1927 * 1928 * - We know the desired received frame will always be at the end of the 1929 * total data upload. 1930 * 1931 * - We know the size of the desired received frame because it will be 1932 * provided in the length field of the status word in the last descriptor. 1933 * 1934 * Here's what we do: 1935 * 1936 * - When we allocate buffers for the receive ring, we bzero() them. 1937 * This means that we know that the buffer contents should be all 1938 * zeros, except for data uploaded by the chip. 1939 * 1940 * - We also force the PNIC chip to upload frames that include the 1941 * ethernet CRC at the end. 1942 * 1943 * - We gather all of the bogus frame data into a single buffer. 1944 * 1945 * - We then position a pointer at the end of this buffer and scan 1946 * backwards until we encounter the first non-zero byte of data. 1947 * This is the end of the received frame. We know we will encounter 1948 * some data at the end of the frame because the CRC will always be 1949 * there, so even if the sender transmits a packet of all zeros, 1950 * we won't be fooled. 1951 * 1952 * - We know the size of the actual received frame, so we subtract 1953 * that value from the current pointer location. This brings us 1954 * to the start of the actual received packet. 1955 * 1956 * - We copy this into an mbuf and pass it on, along with the actual 1957 * frame length. 1958 * 1959 * The performance hit is tremendous, but it beats dropping frames all 1960 * the time. 1961 */ 1962 1963 #define DC_WHOLEFRAME (DC_RXSTAT_FIRSTFRAG|DC_RXSTAT_LASTFRAG) 1964 static void dc_pnic_rx_bug_war(sc, idx) 1965 struct dc_softc *sc; 1966 int idx; 1967 { 1968 struct dc_desc *cur_rx; 1969 struct dc_desc *c = NULL; 1970 struct mbuf *m = NULL; 1971 unsigned char *ptr; 1972 int i, total_len; 1973 u_int32_t rxstat = 0; 1974 1975 i = sc->dc_pnic_rx_bug_save; 1976 cur_rx = &sc->dc_ldata->dc_rx_list[idx]; 1977 ptr = sc->dc_pnic_rx_buf; 1978 bzero(ptr, sizeof(DC_RXLEN * 5)); 1979 1980 /* Copy all the bytes from the bogus buffers. */ 1981 while (1) { 1982 c = &sc->dc_ldata->dc_rx_list[i]; 1983 rxstat = c->dc_status; 1984 m = sc->dc_cdata.dc_rx_chain[i]; 1985 bcopy(mtod(m, char *), ptr, DC_RXLEN); 1986 ptr += DC_RXLEN; 1987 /* If this is the last buffer, break out. */ 1988 if (i == idx || rxstat & DC_RXSTAT_LASTFRAG) 1989 break; 1990 dc_newbuf(sc, i, m); 1991 DC_INC(i, DC_RX_LIST_CNT); 1992 } 1993 1994 /* Find the length of the actual receive frame. */ 1995 total_len = DC_RXBYTES(rxstat); 1996 1997 /* Scan backwards until we hit a non-zero byte. */ 1998 while(*ptr == 0x00) 1999 ptr--; 2000 2001 /* Round off. */ 2002 if ((uintptr_t)(ptr) & 0x3) 2003 ptr -= 1; 2004 2005 /* Now find the start of the frame. */ 2006 ptr -= total_len; 2007 if (ptr < sc->dc_pnic_rx_buf) 2008 ptr = sc->dc_pnic_rx_buf; 2009 2010 /* 2011 * Now copy the salvaged frame to the last mbuf and fake up 2012 * the status word to make it look like a successful 2013 * frame reception. 2014 */ 2015 dc_newbuf(sc, i, m); 2016 bcopy(ptr, mtod(m, char *), total_len); 2017 cur_rx->dc_status = rxstat | DC_RXSTAT_FIRSTFRAG; 2018 2019 return; 2020 } 2021 2022 /* 2023 * This routine searches the RX ring for dirty descriptors in the 2024 * event that the rxeof routine falls out of sync with the chip's 2025 * current descriptor pointer. This may happen sometimes as a result 2026 * of a "no RX buffer available" condition that happens when the chip 2027 * consumes all of the RX buffers before the driver has a chance to 2028 * process the RX ring. This routine may need to be called more than 2029 * once to bring the driver back in sync with the chip, however we 2030 * should still be getting RX DONE interrupts to drive the search 2031 * for new packets in the RX ring, so we should catch up eventually. 2032 */ 2033 static int dc_rx_resync(sc) 2034 struct dc_softc *sc; 2035 { 2036 int i, pos; 2037 struct dc_desc *cur_rx; 2038 2039 pos = sc->dc_cdata.dc_rx_prod; 2040 2041 for (i = 0; i < DC_RX_LIST_CNT; i++) { 2042 cur_rx = &sc->dc_ldata->dc_rx_list[pos]; 2043 if (!(cur_rx->dc_status & DC_RXSTAT_OWN)) 2044 break; 2045 DC_INC(pos, DC_RX_LIST_CNT); 2046 } 2047 2048 /* If the ring really is empty, then just return. */ 2049 if (i == DC_RX_LIST_CNT) 2050 return(0); 2051 2052 /* We've fallen behing the chip: catch it. */ 2053 sc->dc_cdata.dc_rx_prod = pos; 2054 2055 return(EAGAIN); 2056 } 2057 2058 /* 2059 * A frame has been uploaded: pass the resulting mbuf chain up to 2060 * the higher level protocols. 2061 */ 2062 static void dc_rxeof(sc) 2063 struct dc_softc *sc; 2064 { 2065 struct ether_header *eh; 2066 struct mbuf *m; 2067 struct ifnet *ifp; 2068 struct dc_desc *cur_rx; 2069 int i, total_len = 0; 2070 u_int32_t rxstat; 2071 2072 ifp = &sc->arpcom.ac_if; 2073 i = sc->dc_cdata.dc_rx_prod; 2074 2075 while(!(sc->dc_ldata->dc_rx_list[i].dc_status & DC_RXSTAT_OWN)) { 2076 struct mbuf *m0 = NULL; 2077 2078 cur_rx = &sc->dc_ldata->dc_rx_list[i]; 2079 rxstat = cur_rx->dc_status; 2080 m = sc->dc_cdata.dc_rx_chain[i]; 2081 total_len = DC_RXBYTES(rxstat); 2082 2083 if (sc->dc_flags & DC_PNIC_RX_BUG_WAR) { 2084 if ((rxstat & DC_WHOLEFRAME) != DC_WHOLEFRAME) { 2085 if (rxstat & DC_RXSTAT_FIRSTFRAG) 2086 sc->dc_pnic_rx_bug_save = i; 2087 if ((rxstat & DC_RXSTAT_LASTFRAG) == 0) { 2088 DC_INC(i, DC_RX_LIST_CNT); 2089 continue; 2090 } 2091 dc_pnic_rx_bug_war(sc, i); 2092 rxstat = cur_rx->dc_status; 2093 total_len = DC_RXBYTES(rxstat); 2094 } 2095 } 2096 2097 sc->dc_cdata.dc_rx_chain[i] = NULL; 2098 2099 /* 2100 * If an error occurs, update stats, clear the 2101 * status word and leave the mbuf cluster in place: 2102 * it should simply get re-used next time this descriptor 2103 * comes up in the ring. 2104 */ 2105 if (rxstat & DC_RXSTAT_RXERR) { 2106 ifp->if_ierrors++; 2107 if (rxstat & DC_RXSTAT_COLLSEEN) 2108 ifp->if_collisions++; 2109 dc_newbuf(sc, i, m); 2110 if (rxstat & DC_RXSTAT_CRCERR) { 2111 DC_INC(i, DC_RX_LIST_CNT); 2112 continue; 2113 } else { 2114 dc_init(sc); 2115 return; 2116 } 2117 } 2118 2119 /* No errors; receive the packet. */ 2120 total_len -= ETHER_CRC_LEN; 2121 2122 m0 = m_devget(mtod(m, char *) - ETHER_ALIGN, 2123 total_len + ETHER_ALIGN, 0, ifp, NULL); 2124 dc_newbuf(sc, i, m); 2125 DC_INC(i, DC_RX_LIST_CNT); 2126 if (m0 == NULL) { 2127 ifp->if_ierrors++; 2128 continue; 2129 } 2130 m_adj(m0, ETHER_ALIGN); 2131 m = m0; 2132 2133 ifp->if_ipackets++; 2134 eh = mtod(m, struct ether_header *); 2135 2136 /* Handle BPF listeners. Let the BPF user see the packet */ 2137 if (ifp->if_bpf) 2138 bpf_mtap(ifp, m); 2139 2140 #ifdef BRIDGE 2141 if (do_bridge) { 2142 struct ifnet *bdg_ifp ; 2143 bdg_ifp = bridge_in(m); 2144 if (bdg_ifp != BDG_LOCAL && bdg_ifp != BDG_DROP) 2145 bdg_forward(&m, bdg_ifp); 2146 if (((bdg_ifp != BDG_LOCAL) && (bdg_ifp != BDG_BCAST) && (bdg_ifp != BDG_MCAST)) || bdg_ifp == BDG_DROP) { 2147 m_freem(m); 2148 continue; 2149 } 2150 } 2151 2152 eh = mtod(m, struct ether_header *); 2153 #endif 2154 2155 /* Don't pass it up to the ether_input() layer unless it's 2156 * a broadcast packet, multicast packet, matches our ethernet 2157 * address or the interface is in promiscuous mode. 2158 */ 2159 if (ifp->if_bpf) { 2160 if (ifp->if_flags & IFF_PROMISC && 2161 (bcmp(eh->ether_dhost, sc->arpcom.ac_enaddr, 2162 ETHER_ADDR_LEN) && 2163 (eh->ether_dhost[0] & 1) == 0)) { 2164 m_freem(m); 2165 continue; 2166 } 2167 } 2168 2169 /* Remove header from mbuf and pass it on. */ 2170 m_adj(m, sizeof(struct ether_header)); 2171 ether_input(ifp, eh, m); 2172 } 2173 2174 sc->dc_cdata.dc_rx_prod = i; 2175 2176 return; 2177 } 2178 2179 /* 2180 * A frame was downloaded to the chip. It's safe for us to clean up 2181 * the list buffers. 2182 */ 2183 2184 static void dc_txeof(sc) 2185 struct dc_softc *sc; 2186 { 2187 struct dc_desc *cur_tx = NULL; 2188 struct ifnet *ifp; 2189 int idx; 2190 2191 ifp = &sc->arpcom.ac_if; 2192 2193 /* Clear the timeout timer. */ 2194 ifp->if_timer = 0; 2195 2196 /* 2197 * Go through our tx list and free mbufs for those 2198 * frames that have been transmitted. 2199 */ 2200 idx = sc->dc_cdata.dc_tx_cons; 2201 while(idx != sc->dc_cdata.dc_tx_prod) { 2202 u_int32_t txstat; 2203 2204 cur_tx = &sc->dc_ldata->dc_tx_list[idx]; 2205 txstat = cur_tx->dc_status; 2206 2207 if (txstat & DC_TXSTAT_OWN) 2208 break; 2209 2210 if (!(cur_tx->dc_ctl & DC_TXCTL_LASTFRAG) || 2211 cur_tx->dc_ctl & DC_TXCTL_SETUP) { 2212 sc->dc_cdata.dc_tx_cnt--; 2213 if (cur_tx->dc_ctl & DC_TXCTL_SETUP) { 2214 /* 2215 * Yes, the PNIC is so brain damaged 2216 * that it will sometimes generate a TX 2217 * underrun error while DMAing the RX 2218 * filter setup frame. If we detect this, 2219 * we have to send the setup frame again, 2220 * or else the filter won't be programmed 2221 * correctly. 2222 */ 2223 if (DC_IS_PNIC(sc)) { 2224 if (txstat & DC_TXSTAT_ERRSUM) 2225 dc_setfilt(sc); 2226 } 2227 sc->dc_cdata.dc_tx_chain[idx] = NULL; 2228 } 2229 DC_INC(idx, DC_TX_LIST_CNT); 2230 continue; 2231 } 2232 2233 if (/*sc->dc_type == DC_TYPE_21143 &&*/ 2234 sc->dc_pmode == DC_PMODE_MII && 2235 ((txstat & 0xFFFF) & ~(DC_TXSTAT_ERRSUM| 2236 DC_TXSTAT_NOCARRIER|DC_TXSTAT_CARRLOST))) 2237 txstat &= ~DC_TXSTAT_ERRSUM; 2238 2239 if (txstat & DC_TXSTAT_ERRSUM) { 2240 ifp->if_oerrors++; 2241 if (txstat & DC_TXSTAT_EXCESSCOLL) 2242 ifp->if_collisions++; 2243 if (txstat & DC_TXSTAT_LATECOLL) 2244 ifp->if_collisions++; 2245 if (!(txstat & DC_TXSTAT_UNDERRUN)) { 2246 dc_init(sc); 2247 return; 2248 } 2249 } 2250 2251 ifp->if_collisions += (txstat & DC_TXSTAT_COLLCNT) >> 3; 2252 2253 ifp->if_opackets++; 2254 if (sc->dc_cdata.dc_tx_chain[idx] != NULL) { 2255 m_freem(sc->dc_cdata.dc_tx_chain[idx]); 2256 sc->dc_cdata.dc_tx_chain[idx] = NULL; 2257 } 2258 2259 sc->dc_cdata.dc_tx_cnt--; 2260 DC_INC(idx, DC_TX_LIST_CNT); 2261 } 2262 2263 sc->dc_cdata.dc_tx_cons = idx; 2264 if (cur_tx != NULL) 2265 ifp->if_flags &= ~IFF_OACTIVE; 2266 2267 return; 2268 } 2269 2270 static void dc_tick(xsc) 2271 void *xsc; 2272 { 2273 struct dc_softc *sc; 2274 struct mii_data *mii; 2275 struct ifnet *ifp; 2276 int s; 2277 u_int32_t r; 2278 2279 s = splimp(); 2280 2281 sc = xsc; 2282 ifp = &sc->arpcom.ac_if; 2283 mii = device_get_softc(sc->dc_miibus); 2284 2285 if (sc->dc_flags & DC_REDUCED_MII_POLL) { 2286 r = CSR_READ_4(sc, DC_ISR); 2287 if (DC_IS_INTEL(sc)) { 2288 if (r & DC_ISR_LINKFAIL) 2289 sc->dc_link = 0; 2290 if (sc->dc_link == 0) 2291 mii_tick(mii); 2292 } else { 2293 if ((r & DC_ISR_RX_STATE) == DC_RXSTATE_WAIT && 2294 sc->dc_cdata.dc_tx_prod == 0) 2295 mii_tick(mii); 2296 } 2297 } else 2298 mii_tick(mii); 2299 2300 /* 2301 * When the init routine completes, we expect to be able to send 2302 * packets right away, and in fact the network code will send a 2303 * gratuitous ARP the moment the init routine marks the interface 2304 * as running. However, even though the MAC may have been initialized, 2305 * there may be a delay of a few seconds before the PHY completes 2306 * autonegotiation and the link is brought up. Any transmissions 2307 * made during that delay will be lost. Dealing with this is tricky: 2308 * we can't just pause in the init routine while waiting for the 2309 * PHY to come ready since that would bring the whole system to 2310 * a screeching halt for several seconds. 2311 * 2312 * What we do here is prevent the TX start routine from sending 2313 * any packets until a link has been established. After the 2314 * interface has been initialized, the tick routine will poll 2315 * the state of the PHY until the IFM_ACTIVE flag is set. Until 2316 * that time, packets will stay in the send queue, and once the 2317 * link comes up, they will be flushed out to the wire. 2318 */ 2319 if (!sc->dc_link) { 2320 mii_pollstat(mii); 2321 if (mii->mii_media_status & IFM_ACTIVE && 2322 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) { 2323 sc->dc_link++; 2324 if (ifp->if_snd.ifq_head != NULL) 2325 dc_start(ifp); 2326 } 2327 } 2328 2329 sc->dc_stat_ch = timeout(dc_tick, sc, hz); 2330 2331 splx(s); 2332 2333 return; 2334 } 2335 2336 static void dc_intr(arg) 2337 void *arg; 2338 { 2339 struct dc_softc *sc; 2340 struct ifnet *ifp; 2341 u_int32_t status; 2342 2343 sc = arg; 2344 ifp = &sc->arpcom.ac_if; 2345 2346 /* Supress unwanted interrupts */ 2347 if (!(ifp->if_flags & IFF_UP)) { 2348 if (CSR_READ_4(sc, DC_ISR) & DC_INTRS) 2349 dc_stop(sc); 2350 return; 2351 } 2352 2353 /* Disable interrupts. */ 2354 CSR_WRITE_4(sc, DC_IMR, 0x00000000); 2355 2356 while((status = CSR_READ_4(sc, DC_ISR)) & DC_INTRS) { 2357 2358 CSR_WRITE_4(sc, DC_ISR, status); 2359 2360 if (status & DC_ISR_RX_OK) { 2361 int curpkts; 2362 curpkts = ifp->if_ipackets; 2363 dc_rxeof(sc); 2364 if (curpkts == ifp->if_ipackets) { 2365 while(dc_rx_resync(sc)) 2366 dc_rxeof(sc); 2367 } 2368 } 2369 2370 if (status & (DC_ISR_TX_OK|DC_ISR_TX_NOBUF)) 2371 dc_txeof(sc); 2372 2373 if (status & DC_ISR_TX_IDLE) { 2374 dc_txeof(sc); 2375 if (sc->dc_cdata.dc_tx_cnt) { 2376 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_TX_ON); 2377 CSR_WRITE_4(sc, DC_TXSTART, 0xFFFFFFFF); 2378 } 2379 } 2380 2381 if (status & DC_ISR_TX_UNDERRUN) { 2382 u_int32_t cfg; 2383 2384 printf("dc%d: TX underrun -- ", sc->dc_unit); 2385 if (DC_IS_DAVICOM(sc) || DC_IS_INTEL(sc)) 2386 dc_init(sc); 2387 cfg = CSR_READ_4(sc, DC_NETCFG); 2388 cfg &= ~DC_NETCFG_TX_THRESH; 2389 if (sc->dc_txthresh == DC_TXTHRESH_160BYTES) { 2390 printf("using store and forward mode\n"); 2391 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_STORENFWD); 2392 } else if (sc->dc_flags & DC_TX_STORENFWD) { 2393 printf("resetting\n"); 2394 } else { 2395 sc->dc_txthresh += 0x4000; 2396 printf("increasing TX threshold\n"); 2397 CSR_WRITE_4(sc, DC_NETCFG, cfg); 2398 DC_SETBIT(sc, DC_NETCFG, sc->dc_txthresh); 2399 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_STORENFWD); 2400 } 2401 } 2402 2403 if ((status & DC_ISR_RX_WATDOGTIMEO) 2404 || (status & DC_ISR_RX_NOBUF)) { 2405 int curpkts; 2406 curpkts = ifp->if_ipackets; 2407 dc_rxeof(sc); 2408 if (curpkts == ifp->if_ipackets) { 2409 while(dc_rx_resync(sc)) 2410 dc_rxeof(sc); 2411 } 2412 } 2413 2414 if (status & DC_ISR_BUS_ERR) { 2415 dc_reset(sc); 2416 dc_init(sc); 2417 } 2418 } 2419 2420 /* Re-enable interrupts. */ 2421 CSR_WRITE_4(sc, DC_IMR, DC_INTRS); 2422 2423 if (ifp->if_snd.ifq_head != NULL) 2424 dc_start(ifp); 2425 2426 return; 2427 } 2428 2429 /* 2430 * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data 2431 * pointers to the fragment pointers. 2432 */ 2433 static int dc_encap(sc, m_head, txidx) 2434 struct dc_softc *sc; 2435 struct mbuf *m_head; 2436 u_int32_t *txidx; 2437 { 2438 struct dc_desc *f = NULL; 2439 struct mbuf *m; 2440 int frag, cur, cnt = 0; 2441 2442 /* 2443 * Start packing the mbufs in this chain into 2444 * the fragment pointers. Stop when we run out 2445 * of fragments or hit the end of the mbuf chain. 2446 */ 2447 m = m_head; 2448 cur = frag = *txidx; 2449 2450 for (m = m_head; m != NULL; m = m->m_next) { 2451 if (m->m_len != 0) { 2452 if (sc->dc_flags & DC_TX_ADMTEK_WAR) { 2453 if (*txidx != sc->dc_cdata.dc_tx_prod && 2454 frag == (DC_TX_LIST_CNT - 1)) 2455 return(ENOBUFS); 2456 } 2457 if ((DC_TX_LIST_CNT - 2458 (sc->dc_cdata.dc_tx_cnt + cnt)) < 5) 2459 return(ENOBUFS); 2460 2461 f = &sc->dc_ldata->dc_tx_list[frag]; 2462 f->dc_ctl = DC_TXCTL_TLINK | m->m_len; 2463 if (cnt == 0) { 2464 f->dc_status = 0; 2465 f->dc_ctl |= DC_TXCTL_FIRSTFRAG; 2466 } else 2467 f->dc_status = DC_TXSTAT_OWN; 2468 f->dc_data = vtophys(mtod(m, vm_offset_t)); 2469 cur = frag; 2470 DC_INC(frag, DC_TX_LIST_CNT); 2471 cnt++; 2472 } 2473 } 2474 2475 if (m != NULL) 2476 return(ENOBUFS); 2477 2478 sc->dc_cdata.dc_tx_cnt += cnt; 2479 sc->dc_cdata.dc_tx_chain[cur] = m_head; 2480 sc->dc_ldata->dc_tx_list[cur].dc_ctl |= DC_TXCTL_LASTFRAG; 2481 if (sc->dc_flags & DC_TX_INTR_FIRSTFRAG) 2482 sc->dc_ldata->dc_tx_list[*txidx].dc_ctl |= DC_TXCTL_FINT; 2483 if (sc->dc_flags & DC_TX_INTR_ALWAYS) 2484 sc->dc_ldata->dc_tx_list[cur].dc_ctl |= DC_TXCTL_FINT; 2485 if (sc->dc_flags & DC_TX_USE_TX_INTR && sc->dc_cdata.dc_tx_cnt > 64) 2486 sc->dc_ldata->dc_tx_list[cur].dc_ctl |= DC_TXCTL_FINT; 2487 sc->dc_ldata->dc_tx_list[*txidx].dc_status = DC_TXSTAT_OWN; 2488 *txidx = frag; 2489 2490 return(0); 2491 } 2492 2493 /* 2494 * Coalesce an mbuf chain into a single mbuf cluster buffer. 2495 * Needed for some really badly behaved chips that just can't 2496 * do scatter/gather correctly. 2497 */ 2498 static int dc_coal(sc, m_head) 2499 struct dc_softc *sc; 2500 struct mbuf **m_head; 2501 { 2502 struct mbuf *m_new, *m; 2503 2504 m = *m_head; 2505 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 2506 if (m_new == NULL) { 2507 printf("dc%d: no memory for tx list", sc->dc_unit); 2508 return(ENOBUFS); 2509 } 2510 if (m->m_pkthdr.len > MHLEN) { 2511 MCLGET(m_new, M_DONTWAIT); 2512 if (!(m_new->m_flags & M_EXT)) { 2513 m_freem(m_new); 2514 printf("dc%d: no memory for tx list", sc->dc_unit); 2515 return(ENOBUFS); 2516 } 2517 } 2518 m_copydata(m, 0, m->m_pkthdr.len, mtod(m_new, caddr_t)); 2519 m_new->m_pkthdr.len = m_new->m_len = m->m_pkthdr.len; 2520 m_freem(m); 2521 *m_head = m_new; 2522 2523 return(0); 2524 } 2525 2526 /* 2527 * Main transmit routine. To avoid having to do mbuf copies, we put pointers 2528 * to the mbuf data regions directly in the transmit lists. We also save a 2529 * copy of the pointers since the transmit list fragment pointers are 2530 * physical addresses. 2531 */ 2532 2533 static void dc_start(ifp) 2534 struct ifnet *ifp; 2535 { 2536 struct dc_softc *sc; 2537 struct mbuf *m_head = NULL; 2538 int idx; 2539 2540 sc = ifp->if_softc; 2541 2542 if (!sc->dc_link) 2543 return; 2544 2545 if (ifp->if_flags & IFF_OACTIVE) 2546 return; 2547 2548 idx = sc->dc_cdata.dc_tx_prod; 2549 2550 while(sc->dc_cdata.dc_tx_chain[idx] == NULL) { 2551 IF_DEQUEUE(&ifp->if_snd, m_head); 2552 if (m_head == NULL) 2553 break; 2554 2555 if (sc->dc_flags & DC_TX_COALESCE) { 2556 if (dc_coal(sc, &m_head)) { 2557 IF_PREPEND(&ifp->if_snd, m_head); 2558 ifp->if_flags |= IFF_OACTIVE; 2559 break; 2560 } 2561 } 2562 2563 if (dc_encap(sc, m_head, &idx)) { 2564 IF_PREPEND(&ifp->if_snd, m_head); 2565 ifp->if_flags |= IFF_OACTIVE; 2566 break; 2567 } 2568 2569 /* 2570 * If there's a BPF listener, bounce a copy of this frame 2571 * to him. 2572 */ 2573 if (ifp->if_bpf) 2574 bpf_mtap(ifp, m_head); 2575 } 2576 2577 /* Transmit */ 2578 sc->dc_cdata.dc_tx_prod = idx; 2579 if (!(sc->dc_flags & DC_TX_POLL)) 2580 CSR_WRITE_4(sc, DC_TXSTART, 0xFFFFFFFF); 2581 2582 /* 2583 * Set a timeout in case the chip goes out to lunch. 2584 */ 2585 ifp->if_timer = 5; 2586 2587 return; 2588 } 2589 2590 static void dc_init(xsc) 2591 void *xsc; 2592 { 2593 struct dc_softc *sc = xsc; 2594 struct ifnet *ifp = &sc->arpcom.ac_if; 2595 struct mii_data *mii; 2596 int s; 2597 2598 s = splimp(); 2599 2600 mii = device_get_softc(sc->dc_miibus); 2601 2602 /* 2603 * Cancel pending I/O and free all RX/TX buffers. 2604 */ 2605 dc_stop(sc); 2606 dc_reset(sc); 2607 2608 /* 2609 * Set cache alignment and burst length. 2610 */ 2611 if (DC_IS_ASIX(sc) || DC_IS_DAVICOM(sc)) 2612 CSR_WRITE_4(sc, DC_BUSCTL, 0); 2613 else 2614 CSR_WRITE_4(sc, DC_BUSCTL, DC_BUSCTL_MRME|DC_BUSCTL_MRLE); 2615 if (DC_IS_DAVICOM(sc) || DC_IS_INTEL(sc)) { 2616 DC_SETBIT(sc, DC_BUSCTL, DC_BURSTLEN_USECA); 2617 } else { 2618 DC_SETBIT(sc, DC_BUSCTL, DC_BURSTLEN_16LONG); 2619 } 2620 if (sc->dc_flags & DC_TX_POLL) 2621 DC_SETBIT(sc, DC_BUSCTL, DC_TXPOLL_1); 2622 switch(sc->dc_cachesize) { 2623 case 32: 2624 DC_SETBIT(sc, DC_BUSCTL, DC_CACHEALIGN_32LONG); 2625 break; 2626 case 16: 2627 DC_SETBIT(sc, DC_BUSCTL, DC_CACHEALIGN_16LONG); 2628 break; 2629 case 8: 2630 DC_SETBIT(sc, DC_BUSCTL, DC_CACHEALIGN_8LONG); 2631 break; 2632 case 0: 2633 default: 2634 DC_SETBIT(sc, DC_BUSCTL, DC_CACHEALIGN_NONE); 2635 break; 2636 } 2637 2638 if (sc->dc_flags & DC_TX_STORENFWD) 2639 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_STORENFWD); 2640 else { 2641 if (sc->dc_txthresh == DC_TXTHRESH_160BYTES) { 2642 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_STORENFWD); 2643 } else { 2644 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_STORENFWD); 2645 DC_SETBIT(sc, DC_NETCFG, sc->dc_txthresh); 2646 } 2647 } 2648 2649 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_NO_RXCRC); 2650 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_TX_BACKOFF); 2651 2652 if (DC_IS_MACRONIX(sc) || DC_IS_PNICII(sc)) { 2653 /* 2654 * The app notes for the 98713 and 98715A say that 2655 * in order to have the chips operate properly, a magic 2656 * number must be written to CSR16. Macronix does not 2657 * document the meaning of these bits so there's no way 2658 * to know exactly what they do. The 98713 has a magic 2659 * number all its own; the rest all use a different one. 2660 */ 2661 DC_CLRBIT(sc, DC_MX_MAGICPACKET, 0xFFFF0000); 2662 if (sc->dc_type == DC_TYPE_98713) 2663 DC_SETBIT(sc, DC_MX_MAGICPACKET, DC_MX_MAGIC_98713); 2664 else 2665 DC_SETBIT(sc, DC_MX_MAGICPACKET, DC_MX_MAGIC_98715); 2666 } 2667 2668 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_TX_THRESH); 2669 DC_SETBIT(sc, DC_NETCFG, DC_TXTHRESH_72BYTES); 2670 2671 /* Init circular RX list. */ 2672 if (dc_list_rx_init(sc) == ENOBUFS) { 2673 printf("dc%d: initialization failed: no " 2674 "memory for rx buffers\n", sc->dc_unit); 2675 dc_stop(sc); 2676 (void)splx(s); 2677 return; 2678 } 2679 2680 /* 2681 * Init tx descriptors. 2682 */ 2683 dc_list_tx_init(sc); 2684 2685 /* 2686 * Load the address of the RX list. 2687 */ 2688 CSR_WRITE_4(sc, DC_RXADDR, vtophys(&sc->dc_ldata->dc_rx_list[0])); 2689 CSR_WRITE_4(sc, DC_TXADDR, vtophys(&sc->dc_ldata->dc_tx_list[0])); 2690 2691 /* 2692 * Enable interrupts. 2693 */ 2694 CSR_WRITE_4(sc, DC_IMR, DC_INTRS); 2695 CSR_WRITE_4(sc, DC_ISR, 0xFFFFFFFF); 2696 2697 /* Enable transmitter. */ 2698 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_TX_ON); 2699 2700 /* 2701 * Load the RX/multicast filter. We do this sort of late 2702 * because the filter programming scheme on the 21143 and 2703 * some clones requires DMAing a setup frame via the TX 2704 * engine, and we need the transmitter enabled for that. 2705 */ 2706 dc_setfilt(sc); 2707 2708 /* Enable receiver. */ 2709 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_ON); 2710 CSR_WRITE_4(sc, DC_RXSTART, 0xFFFFFFFF); 2711 2712 mii_mediachg(mii); 2713 dc_setcfg(sc, sc->dc_if_media); 2714 2715 ifp->if_flags |= IFF_RUNNING; 2716 ifp->if_flags &= ~IFF_OACTIVE; 2717 2718 (void)splx(s); 2719 2720 sc->dc_stat_ch = timeout(dc_tick, sc, hz); 2721 2722 #ifdef __alpha__ 2723 if(sc->dc_srm_media) { 2724 struct ifreq ifr; 2725 2726 ifr.ifr_media = sc->dc_srm_media; 2727 ifmedia_ioctl(ifp, &ifr, &mii->mii_media, SIOCSIFMEDIA); 2728 sc->dc_srm_media = 0; 2729 } 2730 #endif 2731 return; 2732 } 2733 2734 /* 2735 * Set media options. 2736 */ 2737 static int dc_ifmedia_upd(ifp) 2738 struct ifnet *ifp; 2739 { 2740 struct dc_softc *sc; 2741 struct mii_data *mii; 2742 struct ifmedia *ifm; 2743 2744 sc = ifp->if_softc; 2745 mii = device_get_softc(sc->dc_miibus); 2746 mii_mediachg(mii); 2747 ifm = &mii->mii_media; 2748 2749 if (DC_IS_DAVICOM(sc) && 2750 IFM_SUBTYPE(ifm->ifm_media) == IFM_homePNA) 2751 dc_setcfg(sc, ifm->ifm_media); 2752 else 2753 sc->dc_link = 0; 2754 2755 return(0); 2756 } 2757 2758 /* 2759 * Report current media status. 2760 */ 2761 static void dc_ifmedia_sts(ifp, ifmr) 2762 struct ifnet *ifp; 2763 struct ifmediareq *ifmr; 2764 { 2765 struct dc_softc *sc; 2766 struct mii_data *mii; 2767 struct ifmedia *ifm; 2768 2769 sc = ifp->if_softc; 2770 mii = device_get_softc(sc->dc_miibus); 2771 mii_pollstat(mii); 2772 ifm = &mii->mii_media; 2773 if (DC_IS_DAVICOM(sc)) { 2774 if (IFM_SUBTYPE(ifm->ifm_media) == IFM_homePNA) { 2775 ifmr->ifm_active = ifm->ifm_media; 2776 ifmr->ifm_status = 0; 2777 return; 2778 } 2779 } 2780 ifmr->ifm_active = mii->mii_media_active; 2781 ifmr->ifm_status = mii->mii_media_status; 2782 2783 return; 2784 } 2785 2786 static int dc_ioctl(ifp, command, data) 2787 struct ifnet *ifp; 2788 u_long command; 2789 caddr_t data; 2790 { 2791 struct dc_softc *sc = ifp->if_softc; 2792 struct ifreq *ifr = (struct ifreq *) data; 2793 struct mii_data *mii; 2794 int s, error = 0; 2795 2796 s = splimp(); 2797 2798 switch(command) { 2799 case SIOCSIFADDR: 2800 case SIOCGIFADDR: 2801 case SIOCSIFMTU: 2802 error = ether_ioctl(ifp, command, data); 2803 break; 2804 case SIOCSIFFLAGS: 2805 if (ifp->if_flags & IFF_UP) { 2806 if (ifp->if_flags & IFF_RUNNING && 2807 ifp->if_flags & IFF_PROMISC && 2808 !(sc->dc_if_flags & IFF_PROMISC)) { 2809 dc_setfilt(sc); 2810 } else if (ifp->if_flags & IFF_RUNNING && 2811 !(ifp->if_flags & IFF_PROMISC) && 2812 sc->dc_if_flags & IFF_PROMISC) { 2813 dc_setfilt(sc); 2814 } else if (!(ifp->if_flags & IFF_RUNNING)) { 2815 sc->dc_txthresh = 0; 2816 dc_init(sc); 2817 } 2818 } else { 2819 if (ifp->if_flags & IFF_RUNNING) 2820 dc_stop(sc); 2821 } 2822 sc->dc_if_flags = ifp->if_flags; 2823 error = 0; 2824 break; 2825 case SIOCADDMULTI: 2826 case SIOCDELMULTI: 2827 dc_setfilt(sc); 2828 error = 0; 2829 break; 2830 case SIOCGIFMEDIA: 2831 case SIOCSIFMEDIA: 2832 mii = device_get_softc(sc->dc_miibus); 2833 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 2834 #ifdef __alpha__ 2835 if (sc->dc_srm_media) 2836 sc->dc_srm_media = 0; 2837 #endif 2838 break; 2839 default: 2840 error = EINVAL; 2841 break; 2842 } 2843 2844 (void)splx(s); 2845 2846 return(error); 2847 } 2848 2849 static void dc_watchdog(ifp) 2850 struct ifnet *ifp; 2851 { 2852 struct dc_softc *sc; 2853 2854 sc = ifp->if_softc; 2855 2856 ifp->if_oerrors++; 2857 printf("dc%d: watchdog timeout\n", sc->dc_unit); 2858 2859 dc_stop(sc); 2860 dc_reset(sc); 2861 dc_init(sc); 2862 2863 if (ifp->if_snd.ifq_head != NULL) 2864 dc_start(ifp); 2865 2866 return; 2867 } 2868 2869 /* 2870 * Stop the adapter and free any mbufs allocated to the 2871 * RX and TX lists. 2872 */ 2873 static void dc_stop(sc) 2874 struct dc_softc *sc; 2875 { 2876 register int i; 2877 struct ifnet *ifp; 2878 2879 ifp = &sc->arpcom.ac_if; 2880 ifp->if_timer = 0; 2881 2882 untimeout(dc_tick, sc, sc->dc_stat_ch); 2883 2884 DC_CLRBIT(sc, DC_NETCFG, (DC_NETCFG_RX_ON|DC_NETCFG_TX_ON)); 2885 CSR_WRITE_4(sc, DC_IMR, 0x00000000); 2886 CSR_WRITE_4(sc, DC_TXADDR, 0x00000000); 2887 CSR_WRITE_4(sc, DC_RXADDR, 0x00000000); 2888 sc->dc_link = 0; 2889 2890 /* 2891 * Free data in the RX lists. 2892 */ 2893 for (i = 0; i < DC_RX_LIST_CNT; i++) { 2894 if (sc->dc_cdata.dc_rx_chain[i] != NULL) { 2895 m_freem(sc->dc_cdata.dc_rx_chain[i]); 2896 sc->dc_cdata.dc_rx_chain[i] = NULL; 2897 } 2898 } 2899 bzero((char *)&sc->dc_ldata->dc_rx_list, 2900 sizeof(sc->dc_ldata->dc_rx_list)); 2901 2902 /* 2903 * Free the TX list buffers. 2904 */ 2905 for (i = 0; i < DC_TX_LIST_CNT; i++) { 2906 if (sc->dc_cdata.dc_tx_chain[i] != NULL) { 2907 if (sc->dc_ldata->dc_tx_list[i].dc_ctl & 2908 DC_TXCTL_SETUP) { 2909 sc->dc_cdata.dc_tx_chain[i] = NULL; 2910 continue; 2911 } 2912 m_freem(sc->dc_cdata.dc_tx_chain[i]); 2913 sc->dc_cdata.dc_tx_chain[i] = NULL; 2914 } 2915 } 2916 2917 bzero((char *)&sc->dc_ldata->dc_tx_list, 2918 sizeof(sc->dc_ldata->dc_tx_list)); 2919 2920 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 2921 2922 return; 2923 } 2924 2925 /* 2926 * Stop all chip I/O so that the kernel's probe routines don't 2927 * get confused by errant DMAs when rebooting. 2928 */ 2929 static void dc_shutdown(dev) 2930 device_t dev; 2931 { 2932 struct dc_softc *sc; 2933 2934 sc = device_get_softc(dev); 2935 2936 dc_stop(sc); 2937 2938 return; 2939 } 2940