1 /* 2 * Copyright (c) 1997, 1998, 1999 3 * Bill Paul <wpaul@ee.columbia.edu>. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 3. All advertising materials mentioning features or use of this software 14 * must display the following acknowledgement: 15 * This product includes software developed by Bill Paul. 16 * 4. Neither the name of the author nor the names of any co-contributors 17 * may be used to endorse or promote products derived from this software 18 * without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30 * THE POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33 #include <sys/cdefs.h> 34 __FBSDID("$FreeBSD$"); 35 36 /* 37 * DEC "tulip" clone ethernet driver. Supports the DEC/Intel 21143 38 * series chips and several workalikes including the following: 39 * 40 * Macronix 98713/98715/98725/98727/98732 PMAC (www.macronix.com) 41 * Macronix/Lite-On 82c115 PNIC II (www.macronix.com) 42 * Lite-On 82c168/82c169 PNIC (www.litecom.com) 43 * ASIX Electronics AX88140A (www.asix.com.tw) 44 * ASIX Electronics AX88141 (www.asix.com.tw) 45 * ADMtek AL981 (www.admtek.com.tw) 46 * ADMtek AN985 (www.admtek.com.tw) 47 * Netgear FA511 (www.netgear.com) Appears to be rebadged ADMTek AN985 48 * Davicom DM9100, DM9102, DM9102A (www.davicom8.com) 49 * Accton EN1217 (www.accton.com) 50 * Xircom X3201 (www.xircom.com) 51 * Abocom FE2500 52 * Conexant LANfinity (www.conexant.com) 53 * 3Com OfficeConnect 10/100B 3CSOHO100B (www.3com.com) 54 * 55 * Datasheets for the 21143 are available at developer.intel.com. 56 * Datasheets for the clone parts can be found at their respective sites. 57 * (Except for the PNIC; see www.freebsd.org/~wpaul/PNIC/pnic.ps.gz.) 58 * The PNIC II is essentially a Macronix 98715A chip; the only difference 59 * worth noting is that its multicast hash table is only 128 bits wide 60 * instead of 512. 61 * 62 * Written by Bill Paul <wpaul@ee.columbia.edu> 63 * Electrical Engineering Department 64 * Columbia University, New York City 65 */ 66 /* 67 * The Intel 21143 is the successor to the DEC 21140. It is basically 68 * the same as the 21140 but with a few new features. The 21143 supports 69 * three kinds of media attachments: 70 * 71 * o MII port, for 10Mbps and 100Mbps support and NWAY 72 * autonegotiation provided by an external PHY. 73 * o SYM port, for symbol mode 100Mbps support. 74 * o 10baseT port. 75 * o AUI/BNC port. 76 * 77 * The 100Mbps SYM port and 10baseT port can be used together in 78 * combination with the internal NWAY support to create a 10/100 79 * autosensing configuration. 80 * 81 * Note that not all tulip workalikes are handled in this driver: we only 82 * deal with those which are relatively well behaved. The Winbond is 83 * handled separately due to its different register offsets and the 84 * special handling needed for its various bugs. The PNIC is handled 85 * here, but I'm not thrilled about it. 86 * 87 * All of the workalike chips use some form of MII transceiver support 88 * with the exception of the Macronix chips, which also have a SYM port. 89 * The ASIX AX88140A is also documented to have a SYM port, but all 90 * the cards I've seen use an MII transceiver, probably because the 91 * AX88140A doesn't support internal NWAY. 92 */ 93 94 #include <sys/param.h> 95 #include <sys/endian.h> 96 #include <sys/systm.h> 97 #include <sys/sockio.h> 98 #include <sys/mbuf.h> 99 #include <sys/malloc.h> 100 #include <sys/kernel.h> 101 #include <sys/socket.h> 102 #include <sys/sysctl.h> 103 104 #include <net/if.h> 105 #include <net/if_arp.h> 106 #include <net/ethernet.h> 107 #include <net/if_dl.h> 108 #include <net/if_media.h> 109 #include <net/if_types.h> 110 #include <net/if_vlan_var.h> 111 112 #include <net/bpf.h> 113 114 #include <machine/bus_pio.h> 115 #include <machine/bus_memio.h> 116 #include <machine/bus.h> 117 #include <machine/resource.h> 118 #include <sys/bus.h> 119 #include <sys/rman.h> 120 121 #include <dev/mii/mii.h> 122 #include <dev/mii/miivar.h> 123 124 #include <dev/pci/pcireg.h> 125 #include <dev/pci/pcivar.h> 126 127 #define DC_USEIOSPACE 128 #ifdef __alpha__ 129 #define SRM_MEDIA 130 #endif 131 132 #include <pci/if_dcreg.h> 133 134 #ifdef __sparc64__ 135 #include <dev/ofw/openfirm.h> 136 #include <machine/ofw_machdep.h> 137 #endif 138 139 MODULE_DEPEND(dc, pci, 1, 1, 1); 140 MODULE_DEPEND(dc, ether, 1, 1, 1); 141 MODULE_DEPEND(dc, miibus, 1, 1, 1); 142 143 /* "controller miibus0" required. See GENERIC if you get errors here. */ 144 #include "miibus_if.h" 145 146 /* 147 * Various supported device vendors/types and their names. 148 */ 149 static struct dc_type dc_devs[] = { 150 { DC_VENDORID_DEC, DC_DEVICEID_21143, 151 "Intel 21143 10/100BaseTX" }, 152 { DC_VENDORID_DAVICOM, DC_DEVICEID_DM9009, 153 "Davicom DM9009 10/100BaseTX" }, 154 { DC_VENDORID_DAVICOM, DC_DEVICEID_DM9100, 155 "Davicom DM9100 10/100BaseTX" }, 156 { DC_VENDORID_DAVICOM, DC_DEVICEID_DM9102, 157 "Davicom DM9102 10/100BaseTX" }, 158 { DC_VENDORID_DAVICOM, DC_DEVICEID_DM9102, 159 "Davicom DM9102A 10/100BaseTX" }, 160 { DC_VENDORID_ADMTEK, DC_DEVICEID_AL981, 161 "ADMtek AL981 10/100BaseTX" }, 162 { DC_VENDORID_ADMTEK, DC_DEVICEID_AN985, 163 "ADMtek AN985 10/100BaseTX" }, 164 { DC_VENDORID_ADMTEK, DC_DEVICEID_ADM9511, 165 "ADMtek ADM9511 10/100BaseTX" }, 166 { DC_VENDORID_ADMTEK, DC_DEVICEID_ADM9513, 167 "ADMtek ADM9513 10/100BaseTX" }, 168 { DC_VENDORID_ADMTEK, DC_DEVICEID_FA511, 169 "Netgear FA511 10/100BaseTX" }, 170 { DC_VENDORID_ASIX, DC_DEVICEID_AX88140A, 171 "ASIX AX88140A 10/100BaseTX" }, 172 { DC_VENDORID_ASIX, DC_DEVICEID_AX88140A, 173 "ASIX AX88141 10/100BaseTX" }, 174 { DC_VENDORID_MX, DC_DEVICEID_98713, 175 "Macronix 98713 10/100BaseTX" }, 176 { DC_VENDORID_MX, DC_DEVICEID_98713, 177 "Macronix 98713A 10/100BaseTX" }, 178 { DC_VENDORID_CP, DC_DEVICEID_98713_CP, 179 "Compex RL100-TX 10/100BaseTX" }, 180 { DC_VENDORID_CP, DC_DEVICEID_98713_CP, 181 "Compex RL100-TX 10/100BaseTX" }, 182 { DC_VENDORID_MX, DC_DEVICEID_987x5, 183 "Macronix 98715/98715A 10/100BaseTX" }, 184 { DC_VENDORID_MX, DC_DEVICEID_987x5, 185 "Macronix 98715AEC-C 10/100BaseTX" }, 186 { DC_VENDORID_MX, DC_DEVICEID_987x5, 187 "Macronix 98725 10/100BaseTX" }, 188 { DC_VENDORID_MX, DC_DEVICEID_98727, 189 "Macronix 98727/98732 10/100BaseTX" }, 190 { DC_VENDORID_LO, DC_DEVICEID_82C115, 191 "LC82C115 PNIC II 10/100BaseTX" }, 192 { DC_VENDORID_LO, DC_DEVICEID_82C168, 193 "82c168 PNIC 10/100BaseTX" }, 194 { DC_VENDORID_LO, DC_DEVICEID_82C168, 195 "82c169 PNIC 10/100BaseTX" }, 196 { DC_VENDORID_ACCTON, DC_DEVICEID_EN1217, 197 "Accton EN1217 10/100BaseTX" }, 198 { DC_VENDORID_ACCTON, DC_DEVICEID_EN2242, 199 "Accton EN2242 MiniPCI 10/100BaseTX" }, 200 { DC_VENDORID_XIRCOM, DC_DEVICEID_X3201, 201 "Xircom X3201 10/100BaseTX" }, 202 { DC_VENDORID_ABOCOM, DC_DEVICEID_FE2500, 203 "Abocom FE2500 10/100BaseTX" }, 204 { DC_VENDORID_ABOCOM, DC_DEVICEID_FE2500MX, 205 "Abocom FE2500MX 10/100BaseTX" }, 206 { DC_VENDORID_CONEXANT, DC_DEVICEID_RS7112, 207 "Conexant LANfinity MiniPCI 10/100BaseTX" }, 208 { DC_VENDORID_HAWKING, DC_DEVICEID_HAWKING_PN672TX, 209 "Hawking CB102 CardBus 10/100" }, 210 { DC_VENDORID_PLANEX, DC_DEVICEID_FNW3602T, 211 "PlaneX FNW-3602-T CardBus 10/100" }, 212 { DC_VENDORID_3COM, DC_DEVICEID_3CSOHOB, 213 "3Com OfficeConnect 10/100B" }, 214 { DC_VENDORID_MICROSOFT, DC_DEVICEID_MSMN120, 215 "Microsoft MN-120 CardBus 10/100" }, 216 { DC_VENDORID_MICROSOFT, DC_DEVICEID_MSMN130, 217 "Microsoft MN-130 10/100" }, 218 { DC_VENDORID_MICROSOFT, DC_DEVICEID_MSMN130_FAKE, 219 "Microsoft MN-130 10/100" }, 220 { 0, 0, NULL } 221 }; 222 223 static int dc_probe (device_t); 224 static int dc_attach (device_t); 225 static int dc_detach (device_t); 226 static int dc_suspend (device_t); 227 static int dc_resume (device_t); 228 #ifndef BURN_BRIDGES 229 static void dc_acpi (device_t); 230 #endif 231 static struct dc_type *dc_devtype (device_t); 232 static int dc_newbuf (struct dc_softc *, int, int); 233 static int dc_encap (struct dc_softc *, struct mbuf **); 234 static void dc_pnic_rx_bug_war (struct dc_softc *, int); 235 static int dc_rx_resync (struct dc_softc *); 236 static void dc_rxeof (struct dc_softc *); 237 static void dc_txeof (struct dc_softc *); 238 static void dc_tick (void *); 239 static void dc_tx_underrun (struct dc_softc *); 240 static void dc_intr (void *); 241 static void dc_start (struct ifnet *); 242 static int dc_ioctl (struct ifnet *, u_long, caddr_t); 243 static void dc_init (void *); 244 static void dc_stop (struct dc_softc *); 245 static void dc_watchdog (struct ifnet *); 246 static void dc_shutdown (device_t); 247 static int dc_ifmedia_upd (struct ifnet *); 248 static void dc_ifmedia_sts (struct ifnet *, struct ifmediareq *); 249 250 static void dc_delay (struct dc_softc *); 251 static void dc_eeprom_idle (struct dc_softc *); 252 static void dc_eeprom_putbyte (struct dc_softc *, int); 253 static void dc_eeprom_getword (struct dc_softc *, int, u_int16_t *); 254 static void dc_eeprom_getword_pnic 255 (struct dc_softc *, int, u_int16_t *); 256 static void dc_eeprom_getword_xircom 257 (struct dc_softc *, int, u_int16_t *); 258 static void dc_eeprom_width (struct dc_softc *); 259 static void dc_read_eeprom (struct dc_softc *, caddr_t, int, int, int); 260 261 static void dc_mii_writebit (struct dc_softc *, int); 262 static int dc_mii_readbit (struct dc_softc *); 263 static void dc_mii_sync (struct dc_softc *); 264 static void dc_mii_send (struct dc_softc *, u_int32_t, int); 265 static int dc_mii_readreg (struct dc_softc *, struct dc_mii_frame *); 266 static int dc_mii_writereg (struct dc_softc *, struct dc_mii_frame *); 267 static int dc_miibus_readreg (device_t, int, int); 268 static int dc_miibus_writereg (device_t, int, int, int); 269 static void dc_miibus_statchg (device_t); 270 static void dc_miibus_mediainit (device_t); 271 272 static void dc_setcfg (struct dc_softc *, int); 273 static uint32_t dc_mchash_le (struct dc_softc *, const uint8_t *); 274 static uint32_t dc_mchash_be (const uint8_t *); 275 static void dc_setfilt_21143 (struct dc_softc *); 276 static void dc_setfilt_asix (struct dc_softc *); 277 static void dc_setfilt_admtek (struct dc_softc *); 278 static void dc_setfilt_xircom (struct dc_softc *); 279 280 static void dc_setfilt (struct dc_softc *); 281 282 static void dc_reset (struct dc_softc *); 283 static int dc_list_rx_init (struct dc_softc *); 284 static int dc_list_tx_init (struct dc_softc *); 285 286 static void dc_read_srom (struct dc_softc *, int); 287 static void dc_parse_21143_srom (struct dc_softc *); 288 static void dc_decode_leaf_sia (struct dc_softc *, struct dc_eblock_sia *); 289 static void dc_decode_leaf_mii (struct dc_softc *, struct dc_eblock_mii *); 290 static void dc_decode_leaf_sym (struct dc_softc *, struct dc_eblock_sym *); 291 static void dc_apply_fixup (struct dc_softc *, int); 292 293 static void dc_dma_map_txbuf (void *, bus_dma_segment_t *, int, bus_size_t, 294 int); 295 static void dc_dma_map_rxbuf (void *, bus_dma_segment_t *, int, bus_size_t, 296 int); 297 298 #ifdef DC_USEIOSPACE 299 #define DC_RES SYS_RES_IOPORT 300 #define DC_RID DC_PCI_CFBIO 301 #else 302 #define DC_RES SYS_RES_MEMORY 303 #define DC_RID DC_PCI_CFBMA 304 #endif 305 306 static device_method_t dc_methods[] = { 307 /* Device interface */ 308 DEVMETHOD(device_probe, dc_probe), 309 DEVMETHOD(device_attach, dc_attach), 310 DEVMETHOD(device_detach, dc_detach), 311 DEVMETHOD(device_suspend, dc_suspend), 312 DEVMETHOD(device_resume, dc_resume), 313 DEVMETHOD(device_shutdown, dc_shutdown), 314 315 /* bus interface */ 316 DEVMETHOD(bus_print_child, bus_generic_print_child), 317 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 318 319 /* MII interface */ 320 DEVMETHOD(miibus_readreg, dc_miibus_readreg), 321 DEVMETHOD(miibus_writereg, dc_miibus_writereg), 322 DEVMETHOD(miibus_statchg, dc_miibus_statchg), 323 DEVMETHOD(miibus_mediainit, dc_miibus_mediainit), 324 325 { 0, 0 } 326 }; 327 328 static driver_t dc_driver = { 329 "dc", 330 dc_methods, 331 sizeof(struct dc_softc) 332 }; 333 334 static devclass_t dc_devclass; 335 #ifdef __i386__ 336 static int dc_quick = 1; 337 SYSCTL_INT(_hw, OID_AUTO, dc_quick, CTLFLAG_RW, &dc_quick, 0, 338 "do not m_devget() in dc driver"); 339 #endif 340 341 DRIVER_MODULE(dc, cardbus, dc_driver, dc_devclass, 0, 0); 342 DRIVER_MODULE(dc, pci, dc_driver, dc_devclass, 0, 0); 343 DRIVER_MODULE(miibus, dc, miibus_driver, miibus_devclass, 0, 0); 344 345 #define DC_SETBIT(sc, reg, x) \ 346 CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) | (x)) 347 348 #define DC_CLRBIT(sc, reg, x) \ 349 CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) & ~(x)) 350 351 #define SIO_SET(x) DC_SETBIT(sc, DC_SIO, (x)) 352 #define SIO_CLR(x) DC_CLRBIT(sc, DC_SIO, (x)) 353 354 #define IS_MPSAFE 0 355 356 static void 357 dc_delay(struct dc_softc *sc) 358 { 359 int idx; 360 361 for (idx = (300 / 33) + 1; idx > 0; idx--) 362 CSR_READ_4(sc, DC_BUSCTL); 363 } 364 365 static void 366 dc_eeprom_width(struct dc_softc *sc) 367 { 368 int i; 369 370 /* Force EEPROM to idle state. */ 371 dc_eeprom_idle(sc); 372 373 /* Enter EEPROM access mode. */ 374 CSR_WRITE_4(sc, DC_SIO, DC_SIO_EESEL); 375 dc_delay(sc); 376 DC_SETBIT(sc, DC_SIO, DC_SIO_ROMCTL_READ); 377 dc_delay(sc); 378 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); 379 dc_delay(sc); 380 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CS); 381 dc_delay(sc); 382 383 for (i = 3; i--;) { 384 if (6 & (1 << i)) 385 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_DATAIN); 386 else 387 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_DATAIN); 388 dc_delay(sc); 389 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CLK); 390 dc_delay(sc); 391 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); 392 dc_delay(sc); 393 } 394 395 for (i = 1; i <= 12; i++) { 396 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CLK); 397 dc_delay(sc); 398 if (!(CSR_READ_4(sc, DC_SIO) & DC_SIO_EE_DATAOUT)) { 399 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); 400 dc_delay(sc); 401 break; 402 } 403 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); 404 dc_delay(sc); 405 } 406 407 /* Turn off EEPROM access mode. */ 408 dc_eeprom_idle(sc); 409 410 if (i < 4 || i > 12) 411 sc->dc_romwidth = 6; 412 else 413 sc->dc_romwidth = i; 414 415 /* Enter EEPROM access mode. */ 416 CSR_WRITE_4(sc, DC_SIO, DC_SIO_EESEL); 417 dc_delay(sc); 418 DC_SETBIT(sc, DC_SIO, DC_SIO_ROMCTL_READ); 419 dc_delay(sc); 420 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); 421 dc_delay(sc); 422 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CS); 423 dc_delay(sc); 424 425 /* Turn off EEPROM access mode. */ 426 dc_eeprom_idle(sc); 427 } 428 429 static void 430 dc_eeprom_idle(struct dc_softc *sc) 431 { 432 int i; 433 434 CSR_WRITE_4(sc, DC_SIO, DC_SIO_EESEL); 435 dc_delay(sc); 436 DC_SETBIT(sc, DC_SIO, DC_SIO_ROMCTL_READ); 437 dc_delay(sc); 438 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); 439 dc_delay(sc); 440 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CS); 441 dc_delay(sc); 442 443 for (i = 0; i < 25; i++) { 444 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); 445 dc_delay(sc); 446 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CLK); 447 dc_delay(sc); 448 } 449 450 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); 451 dc_delay(sc); 452 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CS); 453 dc_delay(sc); 454 CSR_WRITE_4(sc, DC_SIO, 0x00000000); 455 } 456 457 /* 458 * Send a read command and address to the EEPROM, check for ACK. 459 */ 460 static void 461 dc_eeprom_putbyte(struct dc_softc *sc, int addr) 462 { 463 int d, i; 464 465 d = DC_EECMD_READ >> 6; 466 for (i = 3; i--; ) { 467 if (d & (1 << i)) 468 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_DATAIN); 469 else 470 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_DATAIN); 471 dc_delay(sc); 472 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CLK); 473 dc_delay(sc); 474 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); 475 dc_delay(sc); 476 } 477 478 /* 479 * Feed in each bit and strobe the clock. 480 */ 481 for (i = sc->dc_romwidth; i--;) { 482 if (addr & (1 << i)) { 483 SIO_SET(DC_SIO_EE_DATAIN); 484 } else { 485 SIO_CLR(DC_SIO_EE_DATAIN); 486 } 487 dc_delay(sc); 488 SIO_SET(DC_SIO_EE_CLK); 489 dc_delay(sc); 490 SIO_CLR(DC_SIO_EE_CLK); 491 dc_delay(sc); 492 } 493 } 494 495 /* 496 * Read a word of data stored in the EEPROM at address 'addr.' 497 * The PNIC 82c168/82c169 has its own non-standard way to read 498 * the EEPROM. 499 */ 500 static void 501 dc_eeprom_getword_pnic(struct dc_softc *sc, int addr, u_int16_t *dest) 502 { 503 int i; 504 u_int32_t r; 505 506 CSR_WRITE_4(sc, DC_PN_SIOCTL, DC_PN_EEOPCODE_READ | addr); 507 508 for (i = 0; i < DC_TIMEOUT; i++) { 509 DELAY(1); 510 r = CSR_READ_4(sc, DC_SIO); 511 if (!(r & DC_PN_SIOCTL_BUSY)) { 512 *dest = (u_int16_t)(r & 0xFFFF); 513 return; 514 } 515 } 516 } 517 518 /* 519 * Read a word of data stored in the EEPROM at address 'addr.' 520 * The Xircom X3201 has its own non-standard way to read 521 * the EEPROM, too. 522 */ 523 static void 524 dc_eeprom_getword_xircom(struct dc_softc *sc, int addr, u_int16_t *dest) 525 { 526 527 SIO_SET(DC_SIO_ROMSEL | DC_SIO_ROMCTL_READ); 528 529 addr *= 2; 530 CSR_WRITE_4(sc, DC_ROM, addr | 0x160); 531 *dest = (u_int16_t)CSR_READ_4(sc, DC_SIO) & 0xff; 532 addr += 1; 533 CSR_WRITE_4(sc, DC_ROM, addr | 0x160); 534 *dest |= ((u_int16_t)CSR_READ_4(sc, DC_SIO) & 0xff) << 8; 535 536 SIO_CLR(DC_SIO_ROMSEL | DC_SIO_ROMCTL_READ); 537 } 538 539 /* 540 * Read a word of data stored in the EEPROM at address 'addr.' 541 */ 542 static void 543 dc_eeprom_getword(struct dc_softc *sc, int addr, u_int16_t *dest) 544 { 545 int i; 546 u_int16_t word = 0; 547 548 /* Force EEPROM to idle state. */ 549 dc_eeprom_idle(sc); 550 551 /* Enter EEPROM access mode. */ 552 CSR_WRITE_4(sc, DC_SIO, DC_SIO_EESEL); 553 dc_delay(sc); 554 DC_SETBIT(sc, DC_SIO, DC_SIO_ROMCTL_READ); 555 dc_delay(sc); 556 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); 557 dc_delay(sc); 558 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CS); 559 dc_delay(sc); 560 561 /* 562 * Send address of word we want to read. 563 */ 564 dc_eeprom_putbyte(sc, addr); 565 566 /* 567 * Start reading bits from EEPROM. 568 */ 569 for (i = 0x8000; i; i >>= 1) { 570 SIO_SET(DC_SIO_EE_CLK); 571 dc_delay(sc); 572 if (CSR_READ_4(sc, DC_SIO) & DC_SIO_EE_DATAOUT) 573 word |= i; 574 dc_delay(sc); 575 SIO_CLR(DC_SIO_EE_CLK); 576 dc_delay(sc); 577 } 578 579 /* Turn off EEPROM access mode. */ 580 dc_eeprom_idle(sc); 581 582 *dest = word; 583 } 584 585 /* 586 * Read a sequence of words from the EEPROM. 587 */ 588 static void 589 dc_read_eeprom(struct dc_softc *sc, caddr_t dest, int off, int cnt, int swap) 590 { 591 int i; 592 u_int16_t word = 0, *ptr; 593 594 for (i = 0; i < cnt; i++) { 595 if (DC_IS_PNIC(sc)) 596 dc_eeprom_getword_pnic(sc, off + i, &word); 597 else if (DC_IS_XIRCOM(sc)) 598 dc_eeprom_getword_xircom(sc, off + i, &word); 599 else 600 dc_eeprom_getword(sc, off + i, &word); 601 ptr = (u_int16_t *)(dest + (i * 2)); 602 if (swap) 603 *ptr = ntohs(word); 604 else 605 *ptr = word; 606 } 607 } 608 609 /* 610 * The following two routines are taken from the Macronix 98713 611 * Application Notes pp.19-21. 612 */ 613 /* 614 * Write a bit to the MII bus. 615 */ 616 static void 617 dc_mii_writebit(struct dc_softc *sc, int bit) 618 { 619 620 if (bit) 621 CSR_WRITE_4(sc, DC_SIO, 622 DC_SIO_ROMCTL_WRITE | DC_SIO_MII_DATAOUT); 623 else 624 CSR_WRITE_4(sc, DC_SIO, DC_SIO_ROMCTL_WRITE); 625 626 DC_SETBIT(sc, DC_SIO, DC_SIO_MII_CLK); 627 DC_CLRBIT(sc, DC_SIO, DC_SIO_MII_CLK); 628 } 629 630 /* 631 * Read a bit from the MII bus. 632 */ 633 static int 634 dc_mii_readbit(struct dc_softc *sc) 635 { 636 637 CSR_WRITE_4(sc, DC_SIO, DC_SIO_ROMCTL_READ | DC_SIO_MII_DIR); 638 CSR_READ_4(sc, DC_SIO); 639 DC_SETBIT(sc, DC_SIO, DC_SIO_MII_CLK); 640 DC_CLRBIT(sc, DC_SIO, DC_SIO_MII_CLK); 641 if (CSR_READ_4(sc, DC_SIO) & DC_SIO_MII_DATAIN) 642 return (1); 643 644 return (0); 645 } 646 647 /* 648 * Sync the PHYs by setting data bit and strobing the clock 32 times. 649 */ 650 static void 651 dc_mii_sync(struct dc_softc *sc) 652 { 653 int i; 654 655 CSR_WRITE_4(sc, DC_SIO, DC_SIO_ROMCTL_WRITE); 656 657 for (i = 0; i < 32; i++) 658 dc_mii_writebit(sc, 1); 659 } 660 661 /* 662 * Clock a series of bits through the MII. 663 */ 664 static void 665 dc_mii_send(struct dc_softc *sc, u_int32_t bits, int cnt) 666 { 667 int i; 668 669 for (i = (0x1 << (cnt - 1)); i; i >>= 1) 670 dc_mii_writebit(sc, bits & i); 671 } 672 673 /* 674 * Read an PHY register through the MII. 675 */ 676 static int 677 dc_mii_readreg(struct dc_softc *sc, struct dc_mii_frame *frame) 678 { 679 int i, ack; 680 681 DC_LOCK(sc); 682 683 /* 684 * Set up frame for RX. 685 */ 686 frame->mii_stdelim = DC_MII_STARTDELIM; 687 frame->mii_opcode = DC_MII_READOP; 688 frame->mii_turnaround = 0; 689 frame->mii_data = 0; 690 691 /* 692 * Sync the PHYs. 693 */ 694 dc_mii_sync(sc); 695 696 /* 697 * Send command/address info. 698 */ 699 dc_mii_send(sc, frame->mii_stdelim, 2); 700 dc_mii_send(sc, frame->mii_opcode, 2); 701 dc_mii_send(sc, frame->mii_phyaddr, 5); 702 dc_mii_send(sc, frame->mii_regaddr, 5); 703 704 #ifdef notdef 705 /* Idle bit */ 706 dc_mii_writebit(sc, 1); 707 dc_mii_writebit(sc, 0); 708 #endif 709 710 /* Check for ack. */ 711 ack = dc_mii_readbit(sc); 712 713 /* 714 * Now try reading data bits. If the ack failed, we still 715 * need to clock through 16 cycles to keep the PHY(s) in sync. 716 */ 717 if (ack) { 718 for (i = 0; i < 16; i++) 719 dc_mii_readbit(sc); 720 goto fail; 721 } 722 723 for (i = 0x8000; i; i >>= 1) { 724 if (!ack) { 725 if (dc_mii_readbit(sc)) 726 frame->mii_data |= i; 727 } 728 } 729 730 fail: 731 732 dc_mii_writebit(sc, 0); 733 dc_mii_writebit(sc, 0); 734 735 DC_UNLOCK(sc); 736 737 if (ack) 738 return (1); 739 return (0); 740 } 741 742 /* 743 * Write to a PHY register through the MII. 744 */ 745 static int 746 dc_mii_writereg(struct dc_softc *sc, struct dc_mii_frame *frame) 747 { 748 749 DC_LOCK(sc); 750 /* 751 * Set up frame for TX. 752 */ 753 754 frame->mii_stdelim = DC_MII_STARTDELIM; 755 frame->mii_opcode = DC_MII_WRITEOP; 756 frame->mii_turnaround = DC_MII_TURNAROUND; 757 758 /* 759 * Sync the PHYs. 760 */ 761 dc_mii_sync(sc); 762 763 dc_mii_send(sc, frame->mii_stdelim, 2); 764 dc_mii_send(sc, frame->mii_opcode, 2); 765 dc_mii_send(sc, frame->mii_phyaddr, 5); 766 dc_mii_send(sc, frame->mii_regaddr, 5); 767 dc_mii_send(sc, frame->mii_turnaround, 2); 768 dc_mii_send(sc, frame->mii_data, 16); 769 770 /* Idle bit. */ 771 dc_mii_writebit(sc, 0); 772 dc_mii_writebit(sc, 0); 773 774 DC_UNLOCK(sc); 775 776 return (0); 777 } 778 779 static int 780 dc_miibus_readreg(device_t dev, int phy, int reg) 781 { 782 struct dc_mii_frame frame; 783 struct dc_softc *sc; 784 int i, rval, phy_reg = 0; 785 786 sc = device_get_softc(dev); 787 bzero(&frame, sizeof(frame)); 788 789 /* 790 * Note: both the AL981 and AN985 have internal PHYs, 791 * however the AL981 provides direct access to the PHY 792 * registers while the AN985 uses a serial MII interface. 793 * The AN985's MII interface is also buggy in that you 794 * can read from any MII address (0 to 31), but only address 1 795 * behaves normally. To deal with both cases, we pretend 796 * that the PHY is at MII address 1. 797 */ 798 if (DC_IS_ADMTEK(sc) && phy != DC_ADMTEK_PHYADDR) 799 return (0); 800 801 /* 802 * Note: the ukphy probes of the RS7112 report a PHY at 803 * MII address 0 (possibly HomePNA?) and 1 (ethernet) 804 * so we only respond to correct one. 805 */ 806 if (DC_IS_CONEXANT(sc) && phy != DC_CONEXANT_PHYADDR) 807 return (0); 808 809 if (sc->dc_pmode != DC_PMODE_MII) { 810 if (phy == (MII_NPHY - 1)) { 811 switch (reg) { 812 case MII_BMSR: 813 /* 814 * Fake something to make the probe 815 * code think there's a PHY here. 816 */ 817 return (BMSR_MEDIAMASK); 818 break; 819 case MII_PHYIDR1: 820 if (DC_IS_PNIC(sc)) 821 return (DC_VENDORID_LO); 822 return (DC_VENDORID_DEC); 823 break; 824 case MII_PHYIDR2: 825 if (DC_IS_PNIC(sc)) 826 return (DC_DEVICEID_82C168); 827 return (DC_DEVICEID_21143); 828 break; 829 default: 830 return (0); 831 break; 832 } 833 } else 834 return (0); 835 } 836 837 if (DC_IS_PNIC(sc)) { 838 CSR_WRITE_4(sc, DC_PN_MII, DC_PN_MIIOPCODE_READ | 839 (phy << 23) | (reg << 18)); 840 for (i = 0; i < DC_TIMEOUT; i++) { 841 DELAY(1); 842 rval = CSR_READ_4(sc, DC_PN_MII); 843 if (!(rval & DC_PN_MII_BUSY)) { 844 rval &= 0xFFFF; 845 return (rval == 0xFFFF ? 0 : rval); 846 } 847 } 848 return (0); 849 } 850 851 if (DC_IS_COMET(sc)) { 852 switch (reg) { 853 case MII_BMCR: 854 phy_reg = DC_AL_BMCR; 855 break; 856 case MII_BMSR: 857 phy_reg = DC_AL_BMSR; 858 break; 859 case MII_PHYIDR1: 860 phy_reg = DC_AL_VENID; 861 break; 862 case MII_PHYIDR2: 863 phy_reg = DC_AL_DEVID; 864 break; 865 case MII_ANAR: 866 phy_reg = DC_AL_ANAR; 867 break; 868 case MII_ANLPAR: 869 phy_reg = DC_AL_LPAR; 870 break; 871 case MII_ANER: 872 phy_reg = DC_AL_ANER; 873 break; 874 default: 875 printf("dc%d: phy_read: bad phy register %x\n", 876 sc->dc_unit, reg); 877 return (0); 878 break; 879 } 880 881 rval = CSR_READ_4(sc, phy_reg) & 0x0000FFFF; 882 883 if (rval == 0xFFFF) 884 return (0); 885 return (rval); 886 } 887 888 frame.mii_phyaddr = phy; 889 frame.mii_regaddr = reg; 890 if (sc->dc_type == DC_TYPE_98713) { 891 phy_reg = CSR_READ_4(sc, DC_NETCFG); 892 CSR_WRITE_4(sc, DC_NETCFG, phy_reg & ~DC_NETCFG_PORTSEL); 893 } 894 dc_mii_readreg(sc, &frame); 895 if (sc->dc_type == DC_TYPE_98713) 896 CSR_WRITE_4(sc, DC_NETCFG, phy_reg); 897 898 return (frame.mii_data); 899 } 900 901 static int 902 dc_miibus_writereg(device_t dev, int phy, int reg, int data) 903 { 904 struct dc_softc *sc; 905 struct dc_mii_frame frame; 906 int i, phy_reg = 0; 907 908 sc = device_get_softc(dev); 909 bzero(&frame, sizeof(frame)); 910 911 if (DC_IS_ADMTEK(sc) && phy != DC_ADMTEK_PHYADDR) 912 return (0); 913 914 if (DC_IS_CONEXANT(sc) && phy != DC_CONEXANT_PHYADDR) 915 return (0); 916 917 if (DC_IS_PNIC(sc)) { 918 CSR_WRITE_4(sc, DC_PN_MII, DC_PN_MIIOPCODE_WRITE | 919 (phy << 23) | (reg << 10) | data); 920 for (i = 0; i < DC_TIMEOUT; i++) { 921 if (!(CSR_READ_4(sc, DC_PN_MII) & DC_PN_MII_BUSY)) 922 break; 923 } 924 return (0); 925 } 926 927 if (DC_IS_COMET(sc)) { 928 switch (reg) { 929 case MII_BMCR: 930 phy_reg = DC_AL_BMCR; 931 break; 932 case MII_BMSR: 933 phy_reg = DC_AL_BMSR; 934 break; 935 case MII_PHYIDR1: 936 phy_reg = DC_AL_VENID; 937 break; 938 case MII_PHYIDR2: 939 phy_reg = DC_AL_DEVID; 940 break; 941 case MII_ANAR: 942 phy_reg = DC_AL_ANAR; 943 break; 944 case MII_ANLPAR: 945 phy_reg = DC_AL_LPAR; 946 break; 947 case MII_ANER: 948 phy_reg = DC_AL_ANER; 949 break; 950 default: 951 printf("dc%d: phy_write: bad phy register %x\n", 952 sc->dc_unit, reg); 953 return (0); 954 break; 955 } 956 957 CSR_WRITE_4(sc, phy_reg, data); 958 return (0); 959 } 960 961 frame.mii_phyaddr = phy; 962 frame.mii_regaddr = reg; 963 frame.mii_data = data; 964 965 if (sc->dc_type == DC_TYPE_98713) { 966 phy_reg = CSR_READ_4(sc, DC_NETCFG); 967 CSR_WRITE_4(sc, DC_NETCFG, phy_reg & ~DC_NETCFG_PORTSEL); 968 } 969 dc_mii_writereg(sc, &frame); 970 if (sc->dc_type == DC_TYPE_98713) 971 CSR_WRITE_4(sc, DC_NETCFG, phy_reg); 972 973 return (0); 974 } 975 976 static void 977 dc_miibus_statchg(device_t dev) 978 { 979 struct dc_softc *sc; 980 struct mii_data *mii; 981 struct ifmedia *ifm; 982 983 sc = device_get_softc(dev); 984 if (DC_IS_ADMTEK(sc)) 985 return; 986 987 mii = device_get_softc(sc->dc_miibus); 988 ifm = &mii->mii_media; 989 if (DC_IS_DAVICOM(sc) && 990 IFM_SUBTYPE(ifm->ifm_media) == IFM_HPNA_1) { 991 dc_setcfg(sc, ifm->ifm_media); 992 sc->dc_if_media = ifm->ifm_media; 993 } else { 994 dc_setcfg(sc, mii->mii_media_active); 995 sc->dc_if_media = mii->mii_media_active; 996 } 997 } 998 999 /* 1000 * Special support for DM9102A cards with HomePNA PHYs. Note: 1001 * with the Davicom DM9102A/DM9801 eval board that I have, it seems 1002 * to be impossible to talk to the management interface of the DM9801 1003 * PHY (its MDIO pin is not connected to anything). Consequently, 1004 * the driver has to just 'know' about the additional mode and deal 1005 * with it itself. *sigh* 1006 */ 1007 static void 1008 dc_miibus_mediainit(device_t dev) 1009 { 1010 struct dc_softc *sc; 1011 struct mii_data *mii; 1012 struct ifmedia *ifm; 1013 int rev; 1014 1015 rev = pci_read_config(dev, DC_PCI_CFRV, 4) & 0xFF; 1016 1017 sc = device_get_softc(dev); 1018 mii = device_get_softc(sc->dc_miibus); 1019 ifm = &mii->mii_media; 1020 1021 if (DC_IS_DAVICOM(sc) && rev >= DC_REVISION_DM9102A) 1022 ifmedia_add(ifm, IFM_ETHER | IFM_HPNA_1, 0, NULL); 1023 } 1024 1025 #define DC_POLY 0xEDB88320 1026 #define DC_BITS_512 9 1027 #define DC_BITS_128 7 1028 #define DC_BITS_64 6 1029 1030 static uint32_t 1031 dc_mchash_le(struct dc_softc *sc, const uint8_t *addr) 1032 { 1033 uint32_t crc; 1034 int idx, bit; 1035 uint8_t data; 1036 1037 /* Compute CRC for the address value. */ 1038 crc = 0xFFFFFFFF; /* initial value */ 1039 1040 for (idx = 0; idx < 6; idx++) { 1041 for (data = *addr++, bit = 0; bit < 8; bit++, data >>= 1) 1042 crc = (crc >> 1) ^ (((crc ^ data) & 1) ? DC_POLY : 0); 1043 } 1044 1045 /* 1046 * The hash table on the PNIC II and the MX98715AEC-C/D/E 1047 * chips is only 128 bits wide. 1048 */ 1049 if (sc->dc_flags & DC_128BIT_HASH) 1050 return (crc & ((1 << DC_BITS_128) - 1)); 1051 1052 /* The hash table on the MX98715BEC is only 64 bits wide. */ 1053 if (sc->dc_flags & DC_64BIT_HASH) 1054 return (crc & ((1 << DC_BITS_64) - 1)); 1055 1056 /* Xircom's hash filtering table is different (read: weird) */ 1057 /* Xircom uses the LEAST significant bits */ 1058 if (DC_IS_XIRCOM(sc)) { 1059 if ((crc & 0x180) == 0x180) 1060 return ((crc & 0x0F) + (crc & 0x70) * 3 + (14 << 4)); 1061 else 1062 return ((crc & 0x1F) + ((crc >> 1) & 0xF0) * 3 + 1063 (12 << 4)); 1064 } 1065 1066 return (crc & ((1 << DC_BITS_512) - 1)); 1067 } 1068 1069 /* 1070 * Calculate CRC of a multicast group address, return the lower 6 bits. 1071 */ 1072 static uint32_t 1073 dc_mchash_be(const uint8_t *addr) 1074 { 1075 uint32_t crc, carry; 1076 int idx, bit; 1077 uint8_t data; 1078 1079 /* Compute CRC for the address value. */ 1080 crc = 0xFFFFFFFF; /* initial value */ 1081 1082 for (idx = 0; idx < 6; idx++) { 1083 for (data = *addr++, bit = 0; bit < 8; bit++, data >>= 1) { 1084 carry = ((crc & 0x80000000) ? 1 : 0) ^ (data & 0x01); 1085 data >>= 1; 1086 crc <<= 1; 1087 if (carry) 1088 crc = (crc ^ 0x04c11db6) | carry; 1089 } 1090 } 1091 1092 /* Return the filter bit position. */ 1093 return ((crc >> 26) & 0x0000003F); 1094 } 1095 1096 /* 1097 * 21143-style RX filter setup routine. Filter programming is done by 1098 * downloading a special setup frame into the TX engine. 21143, Macronix, 1099 * PNIC, PNIC II and Davicom chips are programmed this way. 1100 * 1101 * We always program the chip using 'hash perfect' mode, i.e. one perfect 1102 * address (our node address) and a 512-bit hash filter for multicast 1103 * frames. We also sneak the broadcast address into the hash filter since 1104 * we need that too. 1105 */ 1106 static void 1107 dc_setfilt_21143(struct dc_softc *sc) 1108 { 1109 struct dc_desc *sframe; 1110 u_int32_t h, *sp; 1111 struct ifmultiaddr *ifma; 1112 struct ifnet *ifp; 1113 int i; 1114 1115 ifp = &sc->arpcom.ac_if; 1116 1117 i = sc->dc_cdata.dc_tx_prod; 1118 DC_INC(sc->dc_cdata.dc_tx_prod, DC_TX_LIST_CNT); 1119 sc->dc_cdata.dc_tx_cnt++; 1120 sframe = &sc->dc_ldata->dc_tx_list[i]; 1121 sp = sc->dc_cdata.dc_sbuf; 1122 bzero(sp, DC_SFRAME_LEN); 1123 1124 sframe->dc_data = htole32(sc->dc_saddr); 1125 sframe->dc_ctl = htole32(DC_SFRAME_LEN | DC_TXCTL_SETUP | 1126 DC_TXCTL_TLINK | DC_FILTER_HASHPERF | DC_TXCTL_FINT); 1127 1128 sc->dc_cdata.dc_tx_chain[i] = (struct mbuf *)sc->dc_cdata.dc_sbuf; 1129 1130 /* If we want promiscuous mode, set the allframes bit. */ 1131 if (ifp->if_flags & IFF_PROMISC) 1132 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC); 1133 else 1134 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC); 1135 1136 if (ifp->if_flags & IFF_ALLMULTI) 1137 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI); 1138 else 1139 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI); 1140 1141 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 1142 if (ifma->ifma_addr->sa_family != AF_LINK) 1143 continue; 1144 h = dc_mchash_le(sc, 1145 LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 1146 sp[h >> 4] |= htole32(1 << (h & 0xF)); 1147 } 1148 1149 if (ifp->if_flags & IFF_BROADCAST) { 1150 h = dc_mchash_le(sc, ifp->if_broadcastaddr); 1151 sp[h >> 4] |= htole32(1 << (h & 0xF)); 1152 } 1153 1154 /* Set our MAC address */ 1155 sp[39] = DC_SP_MAC(((u_int16_t *)sc->arpcom.ac_enaddr)[0]); 1156 sp[40] = DC_SP_MAC(((u_int16_t *)sc->arpcom.ac_enaddr)[1]); 1157 sp[41] = DC_SP_MAC(((u_int16_t *)sc->arpcom.ac_enaddr)[2]); 1158 1159 sframe->dc_status = htole32(DC_TXSTAT_OWN); 1160 CSR_WRITE_4(sc, DC_TXSTART, 0xFFFFFFFF); 1161 1162 /* 1163 * The PNIC takes an exceedingly long time to process its 1164 * setup frame; wait 10ms after posting the setup frame 1165 * before proceeding, just so it has time to swallow its 1166 * medicine. 1167 */ 1168 DELAY(10000); 1169 1170 ifp->if_timer = 5; 1171 } 1172 1173 static void 1174 dc_setfilt_admtek(struct dc_softc *sc) 1175 { 1176 struct ifnet *ifp; 1177 struct ifmultiaddr *ifma; 1178 int h = 0; 1179 u_int32_t hashes[2] = { 0, 0 }; 1180 1181 ifp = &sc->arpcom.ac_if; 1182 1183 /* Init our MAC address. */ 1184 CSR_WRITE_4(sc, DC_AL_PAR0, *(u_int32_t *)(&sc->arpcom.ac_enaddr[0])); 1185 CSR_WRITE_4(sc, DC_AL_PAR1, *(u_int32_t *)(&sc->arpcom.ac_enaddr[4])); 1186 1187 /* If we want promiscuous mode, set the allframes bit. */ 1188 if (ifp->if_flags & IFF_PROMISC) 1189 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC); 1190 else 1191 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC); 1192 1193 if (ifp->if_flags & IFF_ALLMULTI) 1194 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI); 1195 else 1196 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI); 1197 1198 /* First, zot all the existing hash bits. */ 1199 CSR_WRITE_4(sc, DC_AL_MAR0, 0); 1200 CSR_WRITE_4(sc, DC_AL_MAR1, 0); 1201 1202 /* 1203 * If we're already in promisc or allmulti mode, we 1204 * don't have to bother programming the multicast filter. 1205 */ 1206 if (ifp->if_flags & (IFF_PROMISC | IFF_ALLMULTI)) 1207 return; 1208 1209 /* Now program new ones. */ 1210 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 1211 if (ifma->ifma_addr->sa_family != AF_LINK) 1212 continue; 1213 if (DC_IS_CENTAUR(sc)) 1214 h = dc_mchash_le(sc, 1215 LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 1216 else 1217 h = dc_mchash_be( 1218 LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 1219 if (h < 32) 1220 hashes[0] |= (1 << h); 1221 else 1222 hashes[1] |= (1 << (h - 32)); 1223 } 1224 1225 CSR_WRITE_4(sc, DC_AL_MAR0, hashes[0]); 1226 CSR_WRITE_4(sc, DC_AL_MAR1, hashes[1]); 1227 } 1228 1229 static void 1230 dc_setfilt_asix(struct dc_softc *sc) 1231 { 1232 struct ifnet *ifp; 1233 struct ifmultiaddr *ifma; 1234 int h = 0; 1235 u_int32_t hashes[2] = { 0, 0 }; 1236 1237 ifp = &sc->arpcom.ac_if; 1238 1239 /* Init our MAC address */ 1240 CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_PAR0); 1241 CSR_WRITE_4(sc, DC_AX_FILTDATA, 1242 *(u_int32_t *)(&sc->arpcom.ac_enaddr[0])); 1243 CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_PAR1); 1244 CSR_WRITE_4(sc, DC_AX_FILTDATA, 1245 *(u_int32_t *)(&sc->arpcom.ac_enaddr[4])); 1246 1247 /* If we want promiscuous mode, set the allframes bit. */ 1248 if (ifp->if_flags & IFF_PROMISC) 1249 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC); 1250 else 1251 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC); 1252 1253 if (ifp->if_flags & IFF_ALLMULTI) 1254 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI); 1255 else 1256 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI); 1257 1258 /* 1259 * The ASIX chip has a special bit to enable reception 1260 * of broadcast frames. 1261 */ 1262 if (ifp->if_flags & IFF_BROADCAST) 1263 DC_SETBIT(sc, DC_NETCFG, DC_AX_NETCFG_RX_BROAD); 1264 else 1265 DC_CLRBIT(sc, DC_NETCFG, DC_AX_NETCFG_RX_BROAD); 1266 1267 /* first, zot all the existing hash bits */ 1268 CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_MAR0); 1269 CSR_WRITE_4(sc, DC_AX_FILTDATA, 0); 1270 CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_MAR1); 1271 CSR_WRITE_4(sc, DC_AX_FILTDATA, 0); 1272 1273 /* 1274 * If we're already in promisc or allmulti mode, we 1275 * don't have to bother programming the multicast filter. 1276 */ 1277 if (ifp->if_flags & (IFF_PROMISC | IFF_ALLMULTI)) 1278 return; 1279 1280 /* now program new ones */ 1281 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 1282 if (ifma->ifma_addr->sa_family != AF_LINK) 1283 continue; 1284 h = dc_mchash_be(LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 1285 if (h < 32) 1286 hashes[0] |= (1 << h); 1287 else 1288 hashes[1] |= (1 << (h - 32)); 1289 } 1290 1291 CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_MAR0); 1292 CSR_WRITE_4(sc, DC_AX_FILTDATA, hashes[0]); 1293 CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_MAR1); 1294 CSR_WRITE_4(sc, DC_AX_FILTDATA, hashes[1]); 1295 } 1296 1297 static void 1298 dc_setfilt_xircom(struct dc_softc *sc) 1299 { 1300 struct ifnet *ifp; 1301 struct ifmultiaddr *ifma; 1302 struct dc_desc *sframe; 1303 u_int32_t h, *sp; 1304 int i; 1305 1306 ifp = &sc->arpcom.ac_if; 1307 DC_CLRBIT(sc, DC_NETCFG, (DC_NETCFG_TX_ON | DC_NETCFG_RX_ON)); 1308 1309 i = sc->dc_cdata.dc_tx_prod; 1310 DC_INC(sc->dc_cdata.dc_tx_prod, DC_TX_LIST_CNT); 1311 sc->dc_cdata.dc_tx_cnt++; 1312 sframe = &sc->dc_ldata->dc_tx_list[i]; 1313 sp = sc->dc_cdata.dc_sbuf; 1314 bzero(sp, DC_SFRAME_LEN); 1315 1316 sframe->dc_data = htole32(sc->dc_saddr); 1317 sframe->dc_ctl = htole32(DC_SFRAME_LEN | DC_TXCTL_SETUP | 1318 DC_TXCTL_TLINK | DC_FILTER_HASHPERF | DC_TXCTL_FINT); 1319 1320 sc->dc_cdata.dc_tx_chain[i] = (struct mbuf *)sc->dc_cdata.dc_sbuf; 1321 1322 /* If we want promiscuous mode, set the allframes bit. */ 1323 if (ifp->if_flags & IFF_PROMISC) 1324 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC); 1325 else 1326 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC); 1327 1328 if (ifp->if_flags & IFF_ALLMULTI) 1329 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI); 1330 else 1331 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI); 1332 1333 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 1334 if (ifma->ifma_addr->sa_family != AF_LINK) 1335 continue; 1336 h = dc_mchash_le(sc, 1337 LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 1338 sp[h >> 4] |= htole32(1 << (h & 0xF)); 1339 } 1340 1341 if (ifp->if_flags & IFF_BROADCAST) { 1342 h = dc_mchash_le(sc, ifp->if_broadcastaddr); 1343 sp[h >> 4] |= htole32(1 << (h & 0xF)); 1344 } 1345 1346 /* Set our MAC address */ 1347 sp[0] = DC_SP_MAC(((u_int16_t *)sc->arpcom.ac_enaddr)[0]); 1348 sp[1] = DC_SP_MAC(((u_int16_t *)sc->arpcom.ac_enaddr)[1]); 1349 sp[2] = DC_SP_MAC(((u_int16_t *)sc->arpcom.ac_enaddr)[2]); 1350 1351 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_TX_ON); 1352 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_ON); 1353 ifp->if_flags |= IFF_RUNNING; 1354 sframe->dc_status = htole32(DC_TXSTAT_OWN); 1355 CSR_WRITE_4(sc, DC_TXSTART, 0xFFFFFFFF); 1356 1357 /* 1358 * Wait some time... 1359 */ 1360 DELAY(1000); 1361 1362 ifp->if_timer = 5; 1363 } 1364 1365 static void 1366 dc_setfilt(struct dc_softc *sc) 1367 { 1368 1369 if (DC_IS_INTEL(sc) || DC_IS_MACRONIX(sc) || DC_IS_PNIC(sc) || 1370 DC_IS_PNICII(sc) || DC_IS_DAVICOM(sc) || DC_IS_CONEXANT(sc)) 1371 dc_setfilt_21143(sc); 1372 1373 if (DC_IS_ASIX(sc)) 1374 dc_setfilt_asix(sc); 1375 1376 if (DC_IS_ADMTEK(sc)) 1377 dc_setfilt_admtek(sc); 1378 1379 if (DC_IS_XIRCOM(sc)) 1380 dc_setfilt_xircom(sc); 1381 } 1382 1383 /* 1384 * In order to fiddle with the 'full-duplex' and '100Mbps' bits in 1385 * the netconfig register, we first have to put the transmit and/or 1386 * receive logic in the idle state. 1387 */ 1388 static void 1389 dc_setcfg(struct dc_softc *sc, int media) 1390 { 1391 int i, restart = 0, watchdogreg; 1392 u_int32_t isr; 1393 1394 if (IFM_SUBTYPE(media) == IFM_NONE) 1395 return; 1396 1397 if (CSR_READ_4(sc, DC_NETCFG) & (DC_NETCFG_TX_ON | DC_NETCFG_RX_ON)) { 1398 restart = 1; 1399 DC_CLRBIT(sc, DC_NETCFG, (DC_NETCFG_TX_ON | DC_NETCFG_RX_ON)); 1400 1401 for (i = 0; i < DC_TIMEOUT; i++) { 1402 isr = CSR_READ_4(sc, DC_ISR); 1403 if (isr & DC_ISR_TX_IDLE && 1404 ((isr & DC_ISR_RX_STATE) == DC_RXSTATE_STOPPED || 1405 (isr & DC_ISR_RX_STATE) == DC_RXSTATE_WAIT)) 1406 break; 1407 DELAY(10); 1408 } 1409 1410 if (i == DC_TIMEOUT) 1411 printf("dc%d: failed to force tx and " 1412 "rx to idle state\n", sc->dc_unit); 1413 } 1414 1415 if (IFM_SUBTYPE(media) == IFM_100_TX) { 1416 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_SPEEDSEL); 1417 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_HEARTBEAT); 1418 if (sc->dc_pmode == DC_PMODE_MII) { 1419 if (DC_IS_INTEL(sc)) { 1420 /* There's a write enable bit here that reads as 1. */ 1421 watchdogreg = CSR_READ_4(sc, DC_WATCHDOG); 1422 watchdogreg &= ~DC_WDOG_CTLWREN; 1423 watchdogreg |= DC_WDOG_JABBERDIS; 1424 CSR_WRITE_4(sc, DC_WATCHDOG, watchdogreg); 1425 } else { 1426 DC_SETBIT(sc, DC_WATCHDOG, DC_WDOG_JABBERDIS); 1427 } 1428 DC_CLRBIT(sc, DC_NETCFG, (DC_NETCFG_PCS | 1429 DC_NETCFG_PORTSEL | DC_NETCFG_SCRAMBLER)); 1430 if (sc->dc_type == DC_TYPE_98713) 1431 DC_SETBIT(sc, DC_NETCFG, (DC_NETCFG_PCS | 1432 DC_NETCFG_SCRAMBLER)); 1433 if (!DC_IS_DAVICOM(sc)) 1434 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL); 1435 DC_CLRBIT(sc, DC_10BTCTRL, 0xFFFF); 1436 if (DC_IS_INTEL(sc)) 1437 dc_apply_fixup(sc, IFM_AUTO); 1438 } else { 1439 if (DC_IS_PNIC(sc)) { 1440 DC_PN_GPIO_SETBIT(sc, DC_PN_GPIO_SPEEDSEL); 1441 DC_PN_GPIO_SETBIT(sc, DC_PN_GPIO_100TX_LOOP); 1442 DC_SETBIT(sc, DC_PN_NWAY, DC_PN_NWAY_SPEEDSEL); 1443 } 1444 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL); 1445 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PCS); 1446 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_SCRAMBLER); 1447 if (DC_IS_INTEL(sc)) 1448 dc_apply_fixup(sc, 1449 (media & IFM_GMASK) == IFM_FDX ? 1450 IFM_100_TX | IFM_FDX : IFM_100_TX); 1451 } 1452 } 1453 1454 if (IFM_SUBTYPE(media) == IFM_10_T) { 1455 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_SPEEDSEL); 1456 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_HEARTBEAT); 1457 if (sc->dc_pmode == DC_PMODE_MII) { 1458 /* There's a write enable bit here that reads as 1. */ 1459 if (DC_IS_INTEL(sc)) { 1460 watchdogreg = CSR_READ_4(sc, DC_WATCHDOG); 1461 watchdogreg &= ~DC_WDOG_CTLWREN; 1462 watchdogreg |= DC_WDOG_JABBERDIS; 1463 CSR_WRITE_4(sc, DC_WATCHDOG, watchdogreg); 1464 } else { 1465 DC_SETBIT(sc, DC_WATCHDOG, DC_WDOG_JABBERDIS); 1466 } 1467 DC_CLRBIT(sc, DC_NETCFG, (DC_NETCFG_PCS | 1468 DC_NETCFG_PORTSEL | DC_NETCFG_SCRAMBLER)); 1469 if (sc->dc_type == DC_TYPE_98713) 1470 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PCS); 1471 if (!DC_IS_DAVICOM(sc)) 1472 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL); 1473 DC_CLRBIT(sc, DC_10BTCTRL, 0xFFFF); 1474 if (DC_IS_INTEL(sc)) 1475 dc_apply_fixup(sc, IFM_AUTO); 1476 } else { 1477 if (DC_IS_PNIC(sc)) { 1478 DC_PN_GPIO_CLRBIT(sc, DC_PN_GPIO_SPEEDSEL); 1479 DC_PN_GPIO_SETBIT(sc, DC_PN_GPIO_100TX_LOOP); 1480 DC_CLRBIT(sc, DC_PN_NWAY, DC_PN_NWAY_SPEEDSEL); 1481 } 1482 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL); 1483 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_PCS); 1484 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_SCRAMBLER); 1485 if (DC_IS_INTEL(sc)) { 1486 DC_CLRBIT(sc, DC_SIARESET, DC_SIA_RESET); 1487 DC_CLRBIT(sc, DC_10BTCTRL, 0xFFFF); 1488 if ((media & IFM_GMASK) == IFM_FDX) 1489 DC_SETBIT(sc, DC_10BTCTRL, 0x7F3D); 1490 else 1491 DC_SETBIT(sc, DC_10BTCTRL, 0x7F3F); 1492 DC_SETBIT(sc, DC_SIARESET, DC_SIA_RESET); 1493 DC_CLRBIT(sc, DC_10BTCTRL, 1494 DC_TCTL_AUTONEGENBL); 1495 dc_apply_fixup(sc, 1496 (media & IFM_GMASK) == IFM_FDX ? 1497 IFM_10_T | IFM_FDX : IFM_10_T); 1498 DELAY(20000); 1499 } 1500 } 1501 } 1502 1503 /* 1504 * If this is a Davicom DM9102A card with a DM9801 HomePNA 1505 * PHY and we want HomePNA mode, set the portsel bit to turn 1506 * on the external MII port. 1507 */ 1508 if (DC_IS_DAVICOM(sc)) { 1509 if (IFM_SUBTYPE(media) == IFM_HPNA_1) { 1510 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL); 1511 sc->dc_link = 1; 1512 } else { 1513 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL); 1514 } 1515 } 1516 1517 if ((media & IFM_GMASK) == IFM_FDX) { 1518 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_FULLDUPLEX); 1519 if (sc->dc_pmode == DC_PMODE_SYM && DC_IS_PNIC(sc)) 1520 DC_SETBIT(sc, DC_PN_NWAY, DC_PN_NWAY_DUPLEX); 1521 } else { 1522 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_FULLDUPLEX); 1523 if (sc->dc_pmode == DC_PMODE_SYM && DC_IS_PNIC(sc)) 1524 DC_CLRBIT(sc, DC_PN_NWAY, DC_PN_NWAY_DUPLEX); 1525 } 1526 1527 if (restart) 1528 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_TX_ON | DC_NETCFG_RX_ON); 1529 } 1530 1531 static void 1532 dc_reset(struct dc_softc *sc) 1533 { 1534 int i; 1535 1536 DC_SETBIT(sc, DC_BUSCTL, DC_BUSCTL_RESET); 1537 1538 for (i = 0; i < DC_TIMEOUT; i++) { 1539 DELAY(10); 1540 if (!(CSR_READ_4(sc, DC_BUSCTL) & DC_BUSCTL_RESET)) 1541 break; 1542 } 1543 1544 if (DC_IS_ASIX(sc) || DC_IS_ADMTEK(sc) || DC_IS_CONEXANT(sc) || 1545 DC_IS_XIRCOM(sc) || DC_IS_INTEL(sc)) { 1546 DELAY(10000); 1547 DC_CLRBIT(sc, DC_BUSCTL, DC_BUSCTL_RESET); 1548 i = 0; 1549 } 1550 1551 if (i == DC_TIMEOUT) 1552 printf("dc%d: reset never completed!\n", sc->dc_unit); 1553 1554 /* Wait a little while for the chip to get its brains in order. */ 1555 DELAY(1000); 1556 1557 CSR_WRITE_4(sc, DC_IMR, 0x00000000); 1558 CSR_WRITE_4(sc, DC_BUSCTL, 0x00000000); 1559 CSR_WRITE_4(sc, DC_NETCFG, 0x00000000); 1560 1561 /* 1562 * Bring the SIA out of reset. In some cases, it looks 1563 * like failing to unreset the SIA soon enough gets it 1564 * into a state where it will never come out of reset 1565 * until we reset the whole chip again. 1566 */ 1567 if (DC_IS_INTEL(sc)) { 1568 DC_SETBIT(sc, DC_SIARESET, DC_SIA_RESET); 1569 CSR_WRITE_4(sc, DC_10BTCTRL, 0); 1570 CSR_WRITE_4(sc, DC_WATCHDOG, 0); 1571 } 1572 } 1573 1574 static struct dc_type * 1575 dc_devtype(device_t dev) 1576 { 1577 struct dc_type *t; 1578 u_int32_t rev; 1579 1580 t = dc_devs; 1581 1582 while (t->dc_name != NULL) { 1583 if ((pci_get_vendor(dev) == t->dc_vid) && 1584 (pci_get_device(dev) == t->dc_did)) { 1585 /* Check the PCI revision */ 1586 rev = pci_read_config(dev, DC_PCI_CFRV, 4) & 0xFF; 1587 if (t->dc_did == DC_DEVICEID_98713 && 1588 rev >= DC_REVISION_98713A) 1589 t++; 1590 if (t->dc_did == DC_DEVICEID_98713_CP && 1591 rev >= DC_REVISION_98713A) 1592 t++; 1593 if (t->dc_did == DC_DEVICEID_987x5 && 1594 rev >= DC_REVISION_98715AEC_C) 1595 t++; 1596 if (t->dc_did == DC_DEVICEID_987x5 && 1597 rev >= DC_REVISION_98725) 1598 t++; 1599 if (t->dc_did == DC_DEVICEID_AX88140A && 1600 rev >= DC_REVISION_88141) 1601 t++; 1602 if (t->dc_did == DC_DEVICEID_82C168 && 1603 rev >= DC_REVISION_82C169) 1604 t++; 1605 if (t->dc_did == DC_DEVICEID_DM9102 && 1606 rev >= DC_REVISION_DM9102A) 1607 t++; 1608 /* 1609 * The Microsoft MN-130 has a device ID of 0x0002, 1610 * which happens to be the same as the PNIC 82c168. 1611 * To keep dc_attach() from getting confused, we 1612 * pretend its ID is something different. 1613 * XXX: ideally, dc_attach() should be checking 1614 * vendorid+deviceid together to avoid such 1615 * collisions. 1616 */ 1617 if (t->dc_vid == DC_VENDORID_MICROSOFT && 1618 t->dc_did == DC_DEVICEID_MSMN130) 1619 t++; 1620 return (t); 1621 } 1622 t++; 1623 } 1624 1625 return (NULL); 1626 } 1627 1628 /* 1629 * Probe for a 21143 or clone chip. Check the PCI vendor and device 1630 * IDs against our list and return a device name if we find a match. 1631 * We do a little bit of extra work to identify the exact type of 1632 * chip. The MX98713 and MX98713A have the same PCI vendor/device ID, 1633 * but different revision IDs. The same is true for 98715/98715A 1634 * chips and the 98725, as well as the ASIX and ADMtek chips. In some 1635 * cases, the exact chip revision affects driver behavior. 1636 */ 1637 static int 1638 dc_probe(device_t dev) 1639 { 1640 struct dc_type *t; 1641 1642 t = dc_devtype(dev); 1643 1644 if (t != NULL) { 1645 device_set_desc(dev, t->dc_name); 1646 return (0); 1647 } 1648 1649 return (ENXIO); 1650 } 1651 1652 #ifndef BURN_BRIDGES 1653 static void 1654 dc_acpi(device_t dev) 1655 { 1656 int unit; 1657 u_int32_t iobase, membase, irq; 1658 1659 unit = device_get_unit(dev); 1660 1661 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) { 1662 /* Save important PCI config data. */ 1663 iobase = pci_read_config(dev, DC_PCI_CFBIO, 4); 1664 membase = pci_read_config(dev, DC_PCI_CFBMA, 4); 1665 irq = pci_read_config(dev, DC_PCI_CFIT, 4); 1666 1667 /* Reset the power state. */ 1668 printf("dc%d: chip is in D%d power mode " 1669 "-- setting to D0\n", unit, 1670 pci_get_powerstate(dev)); 1671 pci_set_powerstate(dev, PCI_POWERSTATE_D0); 1672 1673 /* Restore PCI config data. */ 1674 pci_write_config(dev, DC_PCI_CFBIO, iobase, 4); 1675 pci_write_config(dev, DC_PCI_CFBMA, membase, 4); 1676 pci_write_config(dev, DC_PCI_CFIT, irq, 4); 1677 } 1678 } 1679 #endif 1680 1681 static void 1682 dc_apply_fixup(struct dc_softc *sc, int media) 1683 { 1684 struct dc_mediainfo *m; 1685 u_int8_t *p; 1686 int i; 1687 u_int32_t reg; 1688 1689 m = sc->dc_mi; 1690 1691 while (m != NULL) { 1692 if (m->dc_media == media) 1693 break; 1694 m = m->dc_next; 1695 } 1696 1697 if (m == NULL) 1698 return; 1699 1700 for (i = 0, p = m->dc_reset_ptr; i < m->dc_reset_len; i++, p += 2) { 1701 reg = (p[0] | (p[1] << 8)) << 16; 1702 CSR_WRITE_4(sc, DC_WATCHDOG, reg); 1703 } 1704 1705 for (i = 0, p = m->dc_gp_ptr; i < m->dc_gp_len; i++, p += 2) { 1706 reg = (p[0] | (p[1] << 8)) << 16; 1707 CSR_WRITE_4(sc, DC_WATCHDOG, reg); 1708 } 1709 } 1710 1711 static void 1712 dc_decode_leaf_sia(struct dc_softc *sc, struct dc_eblock_sia *l) 1713 { 1714 struct dc_mediainfo *m; 1715 1716 m = malloc(sizeof(struct dc_mediainfo), M_DEVBUF, M_NOWAIT | M_ZERO); 1717 switch (l->dc_sia_code & ~DC_SIA_CODE_EXT) { 1718 case DC_SIA_CODE_10BT: 1719 m->dc_media = IFM_10_T; 1720 break; 1721 case DC_SIA_CODE_10BT_FDX: 1722 m->dc_media = IFM_10_T | IFM_FDX; 1723 break; 1724 case DC_SIA_CODE_10B2: 1725 m->dc_media = IFM_10_2; 1726 break; 1727 case DC_SIA_CODE_10B5: 1728 m->dc_media = IFM_10_5; 1729 break; 1730 default: 1731 break; 1732 } 1733 1734 /* 1735 * We need to ignore CSR13, CSR14, CSR15 for SIA mode. 1736 * Things apparently already work for cards that do 1737 * supply Media Specific Data. 1738 */ 1739 if (l->dc_sia_code & DC_SIA_CODE_EXT) { 1740 m->dc_gp_len = 2; 1741 m->dc_gp_ptr = 1742 (u_int8_t *)&l->dc_un.dc_sia_ext.dc_sia_gpio_ctl; 1743 } else { 1744 m->dc_gp_len = 2; 1745 m->dc_gp_ptr = 1746 (u_int8_t *)&l->dc_un.dc_sia_noext.dc_sia_gpio_ctl; 1747 } 1748 1749 m->dc_next = sc->dc_mi; 1750 sc->dc_mi = m; 1751 1752 sc->dc_pmode = DC_PMODE_SIA; 1753 } 1754 1755 static void 1756 dc_decode_leaf_sym(struct dc_softc *sc, struct dc_eblock_sym *l) 1757 { 1758 struct dc_mediainfo *m; 1759 1760 m = malloc(sizeof(struct dc_mediainfo), M_DEVBUF, M_NOWAIT | M_ZERO); 1761 if (l->dc_sym_code == DC_SYM_CODE_100BT) 1762 m->dc_media = IFM_100_TX; 1763 1764 if (l->dc_sym_code == DC_SYM_CODE_100BT_FDX) 1765 m->dc_media = IFM_100_TX | IFM_FDX; 1766 1767 m->dc_gp_len = 2; 1768 m->dc_gp_ptr = (u_int8_t *)&l->dc_sym_gpio_ctl; 1769 1770 m->dc_next = sc->dc_mi; 1771 sc->dc_mi = m; 1772 1773 sc->dc_pmode = DC_PMODE_SYM; 1774 } 1775 1776 static void 1777 dc_decode_leaf_mii(struct dc_softc *sc, struct dc_eblock_mii *l) 1778 { 1779 struct dc_mediainfo *m; 1780 u_int8_t *p; 1781 1782 m = malloc(sizeof(struct dc_mediainfo), M_DEVBUF, M_NOWAIT | M_ZERO); 1783 /* We abuse IFM_AUTO to represent MII. */ 1784 m->dc_media = IFM_AUTO; 1785 m->dc_gp_len = l->dc_gpr_len; 1786 1787 p = (u_int8_t *)l; 1788 p += sizeof(struct dc_eblock_mii); 1789 m->dc_gp_ptr = p; 1790 p += 2 * l->dc_gpr_len; 1791 m->dc_reset_len = *p; 1792 p++; 1793 m->dc_reset_ptr = p; 1794 1795 m->dc_next = sc->dc_mi; 1796 sc->dc_mi = m; 1797 } 1798 1799 static void 1800 dc_read_srom(struct dc_softc *sc, int bits) 1801 { 1802 int size; 1803 1804 size = 2 << bits; 1805 sc->dc_srom = malloc(size, M_DEVBUF, M_NOWAIT); 1806 dc_read_eeprom(sc, (caddr_t)sc->dc_srom, 0, (size / 2), 0); 1807 } 1808 1809 static void 1810 dc_parse_21143_srom(struct dc_softc *sc) 1811 { 1812 struct dc_leaf_hdr *lhdr; 1813 struct dc_eblock_hdr *hdr; 1814 int have_mii, i, loff; 1815 char *ptr; 1816 1817 have_mii = 0; 1818 loff = sc->dc_srom[27]; 1819 lhdr = (struct dc_leaf_hdr *)&(sc->dc_srom[loff]); 1820 1821 ptr = (char *)lhdr; 1822 ptr += sizeof(struct dc_leaf_hdr) - 1; 1823 /* 1824 * Look if we got a MII media block. 1825 */ 1826 for (i = 0; i < lhdr->dc_mcnt; i++) { 1827 hdr = (struct dc_eblock_hdr *)ptr; 1828 if (hdr->dc_type == DC_EBLOCK_MII) 1829 have_mii++; 1830 1831 ptr += (hdr->dc_len & 0x7F); 1832 ptr++; 1833 } 1834 1835 /* 1836 * Do the same thing again. Only use SIA and SYM media 1837 * blocks if no MII media block is available. 1838 */ 1839 ptr = (char *)lhdr; 1840 ptr += sizeof(struct dc_leaf_hdr) - 1; 1841 for (i = 0; i < lhdr->dc_mcnt; i++) { 1842 hdr = (struct dc_eblock_hdr *)ptr; 1843 switch (hdr->dc_type) { 1844 case DC_EBLOCK_MII: 1845 dc_decode_leaf_mii(sc, (struct dc_eblock_mii *)hdr); 1846 break; 1847 case DC_EBLOCK_SIA: 1848 if (! have_mii) 1849 dc_decode_leaf_sia(sc, 1850 (struct dc_eblock_sia *)hdr); 1851 break; 1852 case DC_EBLOCK_SYM: 1853 if (! have_mii) 1854 dc_decode_leaf_sym(sc, 1855 (struct dc_eblock_sym *)hdr); 1856 break; 1857 default: 1858 /* Don't care. Yet. */ 1859 break; 1860 } 1861 ptr += (hdr->dc_len & 0x7F); 1862 ptr++; 1863 } 1864 } 1865 1866 static void 1867 dc_dma_map_addr(void *arg, bus_dma_segment_t *segs, int nseg, int error) 1868 { 1869 u_int32_t *paddr; 1870 1871 KASSERT(nseg == 1, ("wrong number of segments, should be 1")); 1872 paddr = arg; 1873 *paddr = segs->ds_addr; 1874 } 1875 1876 /* 1877 * Attach the interface. Allocate softc structures, do ifmedia 1878 * setup and ethernet/BPF attach. 1879 */ 1880 static int 1881 dc_attach(device_t dev) 1882 { 1883 int tmp = 0; 1884 u_char eaddr[ETHER_ADDR_LEN]; 1885 u_int32_t command; 1886 struct dc_softc *sc; 1887 struct ifnet *ifp; 1888 u_int32_t revision; 1889 int unit, error = 0, rid, mac_offset; 1890 int i; 1891 u_int8_t *mac; 1892 1893 sc = device_get_softc(dev); 1894 unit = device_get_unit(dev); 1895 1896 mtx_init(&sc->dc_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 1897 MTX_DEF | MTX_RECURSE); 1898 #ifndef BURN_BRIDGES 1899 /* 1900 * Handle power management nonsense. 1901 */ 1902 dc_acpi(dev); 1903 #endif 1904 /* 1905 * Map control/status registers. 1906 */ 1907 pci_enable_busmaster(dev); 1908 1909 rid = DC_RID; 1910 sc->dc_res = bus_alloc_resource_any(dev, DC_RES, &rid, RF_ACTIVE); 1911 1912 if (sc->dc_res == NULL) { 1913 printf("dc%d: couldn't map ports/memory\n", unit); 1914 error = ENXIO; 1915 goto fail; 1916 } 1917 1918 sc->dc_btag = rman_get_bustag(sc->dc_res); 1919 sc->dc_bhandle = rman_get_bushandle(sc->dc_res); 1920 1921 /* Allocate interrupt. */ 1922 rid = 0; 1923 sc->dc_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 1924 RF_SHAREABLE | RF_ACTIVE); 1925 1926 if (sc->dc_irq == NULL) { 1927 printf("dc%d: couldn't map interrupt\n", unit); 1928 error = ENXIO; 1929 goto fail; 1930 } 1931 1932 /* Need this info to decide on a chip type. */ 1933 sc->dc_info = dc_devtype(dev); 1934 revision = pci_read_config(dev, DC_PCI_CFRV, 4) & 0x000000FF; 1935 1936 /* Get the eeprom width, but PNIC and XIRCOM have diff eeprom */ 1937 if (sc->dc_info->dc_did != DC_DEVICEID_82C168 && 1938 sc->dc_info->dc_did != DC_DEVICEID_X3201) 1939 dc_eeprom_width(sc); 1940 1941 switch (sc->dc_info->dc_did) { 1942 case DC_DEVICEID_21143: 1943 sc->dc_type = DC_TYPE_21143; 1944 sc->dc_flags |= DC_TX_POLL | DC_TX_USE_TX_INTR; 1945 sc->dc_flags |= DC_REDUCED_MII_POLL; 1946 /* Save EEPROM contents so we can parse them later. */ 1947 dc_read_srom(sc, sc->dc_romwidth); 1948 break; 1949 case DC_DEVICEID_DM9009: 1950 case DC_DEVICEID_DM9100: 1951 case DC_DEVICEID_DM9102: 1952 sc->dc_type = DC_TYPE_DM9102; 1953 sc->dc_flags |= DC_TX_COALESCE | DC_TX_INTR_ALWAYS; 1954 sc->dc_flags |= DC_REDUCED_MII_POLL | DC_TX_STORENFWD; 1955 sc->dc_flags |= DC_TX_ALIGN; 1956 sc->dc_pmode = DC_PMODE_MII; 1957 /* Increase the latency timer value. */ 1958 command = pci_read_config(dev, DC_PCI_CFLT, 4); 1959 command &= 0xFFFF00FF; 1960 command |= 0x00008000; 1961 pci_write_config(dev, DC_PCI_CFLT, command, 4); 1962 break; 1963 case DC_DEVICEID_AL981: 1964 sc->dc_type = DC_TYPE_AL981; 1965 sc->dc_flags |= DC_TX_USE_TX_INTR; 1966 sc->dc_flags |= DC_TX_ADMTEK_WAR; 1967 sc->dc_pmode = DC_PMODE_MII; 1968 dc_read_srom(sc, sc->dc_romwidth); 1969 break; 1970 case DC_DEVICEID_AN985: 1971 case DC_DEVICEID_ADM9511: 1972 case DC_DEVICEID_ADM9513: 1973 case DC_DEVICEID_FA511: 1974 case DC_DEVICEID_FE2500: 1975 case DC_DEVICEID_EN2242: 1976 case DC_DEVICEID_HAWKING_PN672TX: 1977 case DC_DEVICEID_3CSOHOB: 1978 case DC_DEVICEID_MSMN120: 1979 case DC_DEVICEID_MSMN130_FAKE: /* XXX avoid collision with PNIC*/ 1980 sc->dc_type = DC_TYPE_AN985; 1981 sc->dc_flags |= DC_64BIT_HASH; 1982 sc->dc_flags |= DC_TX_USE_TX_INTR; 1983 sc->dc_flags |= DC_TX_ADMTEK_WAR; 1984 sc->dc_pmode = DC_PMODE_MII; 1985 /* Don't read SROM for - auto-loaded on reset */ 1986 break; 1987 case DC_DEVICEID_98713: 1988 case DC_DEVICEID_98713_CP: 1989 if (revision < DC_REVISION_98713A) { 1990 sc->dc_type = DC_TYPE_98713; 1991 } 1992 if (revision >= DC_REVISION_98713A) { 1993 sc->dc_type = DC_TYPE_98713A; 1994 sc->dc_flags |= DC_21143_NWAY; 1995 } 1996 sc->dc_flags |= DC_REDUCED_MII_POLL; 1997 sc->dc_flags |= DC_TX_POLL | DC_TX_USE_TX_INTR; 1998 break; 1999 case DC_DEVICEID_987x5: 2000 case DC_DEVICEID_EN1217: 2001 /* 2002 * Macronix MX98715AEC-C/D/E parts have only a 2003 * 128-bit hash table. We need to deal with these 2004 * in the same manner as the PNIC II so that we 2005 * get the right number of bits out of the 2006 * CRC routine. 2007 */ 2008 if (revision >= DC_REVISION_98715AEC_C && 2009 revision < DC_REVISION_98725) 2010 sc->dc_flags |= DC_128BIT_HASH; 2011 sc->dc_type = DC_TYPE_987x5; 2012 sc->dc_flags |= DC_TX_POLL | DC_TX_USE_TX_INTR; 2013 sc->dc_flags |= DC_REDUCED_MII_POLL | DC_21143_NWAY; 2014 break; 2015 case DC_DEVICEID_98727: 2016 sc->dc_type = DC_TYPE_987x5; 2017 sc->dc_flags |= DC_TX_POLL | DC_TX_USE_TX_INTR; 2018 sc->dc_flags |= DC_REDUCED_MII_POLL | DC_21143_NWAY; 2019 break; 2020 case DC_DEVICEID_82C115: 2021 sc->dc_type = DC_TYPE_PNICII; 2022 sc->dc_flags |= DC_TX_POLL | DC_TX_USE_TX_INTR | DC_128BIT_HASH; 2023 sc->dc_flags |= DC_REDUCED_MII_POLL | DC_21143_NWAY; 2024 break; 2025 case DC_DEVICEID_82C168: 2026 sc->dc_type = DC_TYPE_PNIC; 2027 sc->dc_flags |= DC_TX_STORENFWD | DC_TX_INTR_ALWAYS; 2028 sc->dc_flags |= DC_PNIC_RX_BUG_WAR; 2029 sc->dc_pnic_rx_buf = malloc(DC_RXLEN * 5, M_DEVBUF, M_NOWAIT); 2030 if (revision < DC_REVISION_82C169) 2031 sc->dc_pmode = DC_PMODE_SYM; 2032 break; 2033 case DC_DEVICEID_AX88140A: 2034 sc->dc_type = DC_TYPE_ASIX; 2035 sc->dc_flags |= DC_TX_USE_TX_INTR | DC_TX_INTR_FIRSTFRAG; 2036 sc->dc_flags |= DC_REDUCED_MII_POLL; 2037 sc->dc_pmode = DC_PMODE_MII; 2038 break; 2039 case DC_DEVICEID_X3201: 2040 sc->dc_type = DC_TYPE_XIRCOM; 2041 sc->dc_flags |= DC_TX_INTR_ALWAYS | DC_TX_COALESCE | 2042 DC_TX_ALIGN; 2043 /* 2044 * We don't actually need to coalesce, but we're doing 2045 * it to obtain a double word aligned buffer. 2046 * The DC_TX_COALESCE flag is required. 2047 */ 2048 sc->dc_pmode = DC_PMODE_MII; 2049 break; 2050 case DC_DEVICEID_RS7112: 2051 sc->dc_type = DC_TYPE_CONEXANT; 2052 sc->dc_flags |= DC_TX_INTR_ALWAYS; 2053 sc->dc_flags |= DC_REDUCED_MII_POLL; 2054 sc->dc_pmode = DC_PMODE_MII; 2055 dc_read_srom(sc, sc->dc_romwidth); 2056 break; 2057 default: 2058 printf("dc%d: unknown device: %x\n", sc->dc_unit, 2059 sc->dc_info->dc_did); 2060 break; 2061 } 2062 2063 /* Save the cache line size. */ 2064 if (DC_IS_DAVICOM(sc)) 2065 sc->dc_cachesize = 0; 2066 else 2067 sc->dc_cachesize = pci_read_config(dev, 2068 DC_PCI_CFLT, 4) & 0xFF; 2069 2070 /* Reset the adapter. */ 2071 dc_reset(sc); 2072 2073 /* Take 21143 out of snooze mode */ 2074 if (DC_IS_INTEL(sc) || DC_IS_XIRCOM(sc)) { 2075 command = pci_read_config(dev, DC_PCI_CFDD, 4); 2076 command &= ~(DC_CFDD_SNOOZE_MODE | DC_CFDD_SLEEP_MODE); 2077 pci_write_config(dev, DC_PCI_CFDD, command, 4); 2078 } 2079 2080 /* 2081 * Try to learn something about the supported media. 2082 * We know that ASIX and ADMtek and Davicom devices 2083 * will *always* be using MII media, so that's a no-brainer. 2084 * The tricky ones are the Macronix/PNIC II and the 2085 * Intel 21143. 2086 */ 2087 if (DC_IS_INTEL(sc)) 2088 dc_parse_21143_srom(sc); 2089 else if (DC_IS_MACRONIX(sc) || DC_IS_PNICII(sc)) { 2090 if (sc->dc_type == DC_TYPE_98713) 2091 sc->dc_pmode = DC_PMODE_MII; 2092 else 2093 sc->dc_pmode = DC_PMODE_SYM; 2094 } else if (!sc->dc_pmode) 2095 sc->dc_pmode = DC_PMODE_MII; 2096 2097 /* 2098 * Get station address from the EEPROM. 2099 */ 2100 switch(sc->dc_type) { 2101 case DC_TYPE_98713: 2102 case DC_TYPE_98713A: 2103 case DC_TYPE_987x5: 2104 case DC_TYPE_PNICII: 2105 dc_read_eeprom(sc, (caddr_t)&mac_offset, 2106 (DC_EE_NODEADDR_OFFSET / 2), 1, 0); 2107 dc_read_eeprom(sc, (caddr_t)&eaddr, (mac_offset / 2), 3, 0); 2108 break; 2109 case DC_TYPE_PNIC: 2110 dc_read_eeprom(sc, (caddr_t)&eaddr, 0, 3, 1); 2111 break; 2112 case DC_TYPE_DM9102: 2113 dc_read_eeprom(sc, (caddr_t)&eaddr, DC_EE_NODEADDR, 3, 0); 2114 #ifdef __sparc64__ 2115 /* 2116 * If this is an onboard dc(4) the station address read from 2117 * the EEPROM is all zero and we have to get it from the fcode. 2118 */ 2119 for (i = 0; i < ETHER_ADDR_LEN; i++) 2120 if (eaddr[i] != 0x00) 2121 break; 2122 if (i >= ETHER_ADDR_LEN && OF_getetheraddr2(dev, eaddr) == -1) 2123 OF_getetheraddr(dev, eaddr); 2124 #endif 2125 break; 2126 case DC_TYPE_21143: 2127 case DC_TYPE_ASIX: 2128 dc_read_eeprom(sc, (caddr_t)&eaddr, DC_EE_NODEADDR, 3, 0); 2129 break; 2130 case DC_TYPE_AL981: 2131 case DC_TYPE_AN985: 2132 *(u_int32_t *)(&eaddr[0]) = CSR_READ_4(sc, DC_AL_PAR0); 2133 *(u_int16_t *)(&eaddr[4]) = CSR_READ_4(sc, DC_AL_PAR1); 2134 break; 2135 case DC_TYPE_CONEXANT: 2136 bcopy(sc->dc_srom + DC_CONEXANT_EE_NODEADDR, &eaddr, 2137 ETHER_ADDR_LEN); 2138 break; 2139 case DC_TYPE_XIRCOM: 2140 /* The MAC comes from the CIS. */ 2141 mac = pci_get_ether(dev); 2142 if (!mac) { 2143 device_printf(dev, "No station address in CIS!\n"); 2144 error = ENXIO; 2145 goto fail; 2146 } 2147 bcopy(mac, eaddr, ETHER_ADDR_LEN); 2148 break; 2149 default: 2150 dc_read_eeprom(sc, (caddr_t)&eaddr, DC_EE_NODEADDR, 3, 0); 2151 break; 2152 } 2153 2154 sc->dc_unit = unit; 2155 bcopy(eaddr, &sc->arpcom.ac_enaddr, ETHER_ADDR_LEN); 2156 2157 /* Allocate a busdma tag and DMA safe memory for TX/RX descriptors. */ 2158 error = bus_dma_tag_create(NULL, PAGE_SIZE, 0, BUS_SPACE_MAXADDR_32BIT, 2159 BUS_SPACE_MAXADDR, NULL, NULL, sizeof(struct dc_list_data), 1, 2160 sizeof(struct dc_list_data), 0, NULL, NULL, &sc->dc_ltag); 2161 if (error) { 2162 printf("dc%d: failed to allocate busdma tag\n", unit); 2163 error = ENXIO; 2164 goto fail; 2165 } 2166 error = bus_dmamem_alloc(sc->dc_ltag, (void **)&sc->dc_ldata, 2167 BUS_DMA_NOWAIT | BUS_DMA_ZERO, &sc->dc_lmap); 2168 if (error) { 2169 printf("dc%d: failed to allocate DMA safe memory\n", unit); 2170 error = ENXIO; 2171 goto fail; 2172 } 2173 error = bus_dmamap_load(sc->dc_ltag, sc->dc_lmap, sc->dc_ldata, 2174 sizeof(struct dc_list_data), dc_dma_map_addr, &sc->dc_laddr, 2175 BUS_DMA_NOWAIT); 2176 if (error) { 2177 printf("dc%d: cannot get address of the descriptors\n", unit); 2178 error = ENXIO; 2179 goto fail; 2180 } 2181 2182 /* 2183 * Allocate a busdma tag and DMA safe memory for the multicast 2184 * setup frame. 2185 */ 2186 error = bus_dma_tag_create(NULL, PAGE_SIZE, 0, BUS_SPACE_MAXADDR_32BIT, 2187 BUS_SPACE_MAXADDR, NULL, NULL, DC_SFRAME_LEN + DC_MIN_FRAMELEN, 1, 2188 DC_SFRAME_LEN + DC_MIN_FRAMELEN, 0, NULL, NULL, &sc->dc_stag); 2189 if (error) { 2190 printf("dc%d: failed to allocate busdma tag\n", unit); 2191 error = ENXIO; 2192 goto fail; 2193 } 2194 error = bus_dmamem_alloc(sc->dc_stag, (void **)&sc->dc_cdata.dc_sbuf, 2195 BUS_DMA_NOWAIT, &sc->dc_smap); 2196 if (error) { 2197 printf("dc%d: failed to allocate DMA safe memory\n", unit); 2198 error = ENXIO; 2199 goto fail; 2200 } 2201 error = bus_dmamap_load(sc->dc_stag, sc->dc_smap, sc->dc_cdata.dc_sbuf, 2202 DC_SFRAME_LEN, dc_dma_map_addr, &sc->dc_saddr, BUS_DMA_NOWAIT); 2203 if (error) { 2204 printf("dc%d: cannot get address of the descriptors\n", unit); 2205 error = ENXIO; 2206 goto fail; 2207 } 2208 2209 /* Allocate a busdma tag for mbufs. */ 2210 error = bus_dma_tag_create(NULL, PAGE_SIZE, 0, BUS_SPACE_MAXADDR_32BIT, 2211 BUS_SPACE_MAXADDR, NULL, NULL, MCLBYTES * DC_TX_LIST_CNT, 2212 DC_TX_LIST_CNT, MCLBYTES, 0, NULL, NULL, &sc->dc_mtag); 2213 if (error) { 2214 printf("dc%d: failed to allocate busdma tag\n", unit); 2215 error = ENXIO; 2216 goto fail; 2217 } 2218 2219 /* Create the TX/RX busdma maps. */ 2220 for (i = 0; i < DC_TX_LIST_CNT; i++) { 2221 error = bus_dmamap_create(sc->dc_mtag, 0, 2222 &sc->dc_cdata.dc_tx_map[i]); 2223 if (error) { 2224 printf("dc%d: failed to init TX ring\n", unit); 2225 error = ENXIO; 2226 goto fail; 2227 } 2228 } 2229 for (i = 0; i < DC_RX_LIST_CNT; i++) { 2230 error = bus_dmamap_create(sc->dc_mtag, 0, 2231 &sc->dc_cdata.dc_rx_map[i]); 2232 if (error) { 2233 printf("dc%d: failed to init RX ring\n", unit); 2234 error = ENXIO; 2235 goto fail; 2236 } 2237 } 2238 error = bus_dmamap_create(sc->dc_mtag, 0, &sc->dc_sparemap); 2239 if (error) { 2240 printf("dc%d: failed to init RX ring\n", unit); 2241 error = ENXIO; 2242 goto fail; 2243 } 2244 2245 ifp = &sc->arpcom.ac_if; 2246 ifp->if_softc = sc; 2247 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 2248 /* XXX: bleah, MTU gets overwritten in ether_ifattach() */ 2249 ifp->if_mtu = ETHERMTU; 2250 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 2251 ifp->if_ioctl = dc_ioctl; 2252 ifp->if_start = dc_start; 2253 ifp->if_watchdog = dc_watchdog; 2254 ifp->if_init = dc_init; 2255 ifp->if_baudrate = 10000000; 2256 ifp->if_snd.ifq_maxlen = DC_TX_LIST_CNT - 1; 2257 2258 /* 2259 * Do MII setup. If this is a 21143, check for a PHY on the 2260 * MII bus after applying any necessary fixups to twiddle the 2261 * GPIO bits. If we don't end up finding a PHY, restore the 2262 * old selection (SIA only or SIA/SYM) and attach the dcphy 2263 * driver instead. 2264 */ 2265 if (DC_IS_INTEL(sc)) { 2266 dc_apply_fixup(sc, IFM_AUTO); 2267 tmp = sc->dc_pmode; 2268 sc->dc_pmode = DC_PMODE_MII; 2269 } 2270 2271 error = mii_phy_probe(dev, &sc->dc_miibus, 2272 dc_ifmedia_upd, dc_ifmedia_sts); 2273 2274 if (error && DC_IS_INTEL(sc)) { 2275 sc->dc_pmode = tmp; 2276 if (sc->dc_pmode != DC_PMODE_SIA) 2277 sc->dc_pmode = DC_PMODE_SYM; 2278 sc->dc_flags |= DC_21143_NWAY; 2279 mii_phy_probe(dev, &sc->dc_miibus, 2280 dc_ifmedia_upd, dc_ifmedia_sts); 2281 /* 2282 * For non-MII cards, we need to have the 21143 2283 * drive the LEDs. Except there are some systems 2284 * like the NEC VersaPro NoteBook PC which have no 2285 * LEDs, and twiddling these bits has adverse effects 2286 * on them. (I.e. you suddenly can't get a link.) 2287 */ 2288 if (pci_read_config(dev, DC_PCI_CSID, 4) != 0x80281033) 2289 sc->dc_flags |= DC_TULIP_LEDS; 2290 error = 0; 2291 } 2292 2293 if (error) { 2294 printf("dc%d: MII without any PHY!\n", sc->dc_unit); 2295 goto fail; 2296 } 2297 2298 if (DC_IS_XIRCOM(sc)) { 2299 /* 2300 * setup General Purpose Port mode and data so the tulip 2301 * can talk to the MII. 2302 */ 2303 CSR_WRITE_4(sc, DC_SIAGP, DC_SIAGP_WRITE_EN | DC_SIAGP_INT1_EN | 2304 DC_SIAGP_MD_GP2_OUTPUT | DC_SIAGP_MD_GP0_OUTPUT); 2305 DELAY(10); 2306 CSR_WRITE_4(sc, DC_SIAGP, DC_SIAGP_INT1_EN | 2307 DC_SIAGP_MD_GP2_OUTPUT | DC_SIAGP_MD_GP0_OUTPUT); 2308 DELAY(10); 2309 } 2310 2311 if (DC_IS_ADMTEK(sc)) { 2312 /* 2313 * Set automatic TX underrun recovery for the ADMtek chips 2314 */ 2315 DC_SETBIT(sc, DC_AL_CR, DC_AL_CR_ATUR); 2316 } 2317 2318 /* 2319 * Tell the upper layer(s) we support long frames. 2320 */ 2321 ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header); 2322 ifp->if_capabilities |= IFCAP_VLAN_MTU; 2323 #ifdef DEVICE_POLLING 2324 ifp->if_capabilities |= IFCAP_POLLING; 2325 #endif 2326 ifp->if_capenable = ifp->if_capabilities; 2327 2328 callout_init(&sc->dc_stat_ch, IS_MPSAFE ? CALLOUT_MPSAFE : 0); 2329 2330 #ifdef SRM_MEDIA 2331 sc->dc_srm_media = 0; 2332 2333 /* Remember the SRM console media setting */ 2334 if (DC_IS_INTEL(sc)) { 2335 command = pci_read_config(dev, DC_PCI_CFDD, 4); 2336 command &= ~(DC_CFDD_SNOOZE_MODE | DC_CFDD_SLEEP_MODE); 2337 switch ((command >> 8) & 0xff) { 2338 case 3: 2339 sc->dc_srm_media = IFM_10_T; 2340 break; 2341 case 4: 2342 sc->dc_srm_media = IFM_10_T | IFM_FDX; 2343 break; 2344 case 5: 2345 sc->dc_srm_media = IFM_100_TX; 2346 break; 2347 case 6: 2348 sc->dc_srm_media = IFM_100_TX | IFM_FDX; 2349 break; 2350 } 2351 if (sc->dc_srm_media) 2352 sc->dc_srm_media |= IFM_ACTIVE | IFM_ETHER; 2353 } 2354 #endif 2355 2356 /* 2357 * Call MI attach routine. 2358 */ 2359 ether_ifattach(ifp, eaddr); 2360 2361 /* Hook interrupt last to avoid having to lock softc */ 2362 error = bus_setup_intr(dev, sc->dc_irq, INTR_TYPE_NET | 2363 (IS_MPSAFE ? INTR_MPSAFE : 0), 2364 dc_intr, sc, &sc->dc_intrhand); 2365 2366 if (error) { 2367 printf("dc%d: couldn't set up irq\n", unit); 2368 ether_ifdetach(ifp); 2369 goto fail; 2370 } 2371 2372 fail: 2373 if (error) 2374 dc_detach(dev); 2375 return (error); 2376 } 2377 2378 /* 2379 * Shutdown hardware and free up resources. This can be called any 2380 * time after the mutex has been initialized. It is called in both 2381 * the error case in attach and the normal detach case so it needs 2382 * to be careful about only freeing resources that have actually been 2383 * allocated. 2384 */ 2385 static int 2386 dc_detach(device_t dev) 2387 { 2388 struct dc_softc *sc; 2389 struct ifnet *ifp; 2390 struct dc_mediainfo *m; 2391 int i; 2392 2393 sc = device_get_softc(dev); 2394 KASSERT(mtx_initialized(&sc->dc_mtx), ("dc mutex not initialized")); 2395 DC_LOCK(sc); 2396 2397 ifp = &sc->arpcom.ac_if; 2398 2399 /* These should only be active if attach succeeded */ 2400 if (device_is_attached(dev)) { 2401 dc_stop(sc); 2402 ether_ifdetach(ifp); 2403 } 2404 if (sc->dc_miibus) 2405 device_delete_child(dev, sc->dc_miibus); 2406 bus_generic_detach(dev); 2407 2408 if (sc->dc_intrhand) 2409 bus_teardown_intr(dev, sc->dc_irq, sc->dc_intrhand); 2410 if (sc->dc_irq) 2411 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->dc_irq); 2412 if (sc->dc_res) 2413 bus_release_resource(dev, DC_RES, DC_RID, sc->dc_res); 2414 2415 if (sc->dc_cdata.dc_sbuf != NULL) 2416 bus_dmamem_free(sc->dc_stag, sc->dc_cdata.dc_sbuf, sc->dc_smap); 2417 if (sc->dc_ldata != NULL) 2418 bus_dmamem_free(sc->dc_ltag, sc->dc_ldata, sc->dc_lmap); 2419 for (i = 0; i < DC_TX_LIST_CNT; i++) 2420 bus_dmamap_destroy(sc->dc_mtag, sc->dc_cdata.dc_tx_map[i]); 2421 for (i = 0; i < DC_RX_LIST_CNT; i++) 2422 bus_dmamap_destroy(sc->dc_mtag, sc->dc_cdata.dc_rx_map[i]); 2423 bus_dmamap_destroy(sc->dc_mtag, sc->dc_sparemap); 2424 if (sc->dc_stag) 2425 bus_dma_tag_destroy(sc->dc_stag); 2426 if (sc->dc_mtag) 2427 bus_dma_tag_destroy(sc->dc_mtag); 2428 if (sc->dc_ltag) 2429 bus_dma_tag_destroy(sc->dc_ltag); 2430 2431 free(sc->dc_pnic_rx_buf, M_DEVBUF); 2432 2433 while (sc->dc_mi != NULL) { 2434 m = sc->dc_mi->dc_next; 2435 free(sc->dc_mi, M_DEVBUF); 2436 sc->dc_mi = m; 2437 } 2438 free(sc->dc_srom, M_DEVBUF); 2439 2440 DC_UNLOCK(sc); 2441 mtx_destroy(&sc->dc_mtx); 2442 2443 return (0); 2444 } 2445 2446 /* 2447 * Initialize the transmit descriptors. 2448 */ 2449 static int 2450 dc_list_tx_init(struct dc_softc *sc) 2451 { 2452 struct dc_chain_data *cd; 2453 struct dc_list_data *ld; 2454 int i, nexti; 2455 2456 cd = &sc->dc_cdata; 2457 ld = sc->dc_ldata; 2458 for (i = 0; i < DC_TX_LIST_CNT; i++) { 2459 if (i == DC_TX_LIST_CNT - 1) 2460 nexti = 0; 2461 else 2462 nexti = i + 1; 2463 ld->dc_tx_list[i].dc_next = htole32(DC_TXDESC(sc, nexti)); 2464 cd->dc_tx_chain[i] = NULL; 2465 ld->dc_tx_list[i].dc_data = 0; 2466 ld->dc_tx_list[i].dc_ctl = 0; 2467 } 2468 2469 cd->dc_tx_prod = cd->dc_tx_cons = cd->dc_tx_cnt = 0; 2470 bus_dmamap_sync(sc->dc_ltag, sc->dc_lmap, 2471 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2472 return (0); 2473 } 2474 2475 2476 /* 2477 * Initialize the RX descriptors and allocate mbufs for them. Note that 2478 * we arrange the descriptors in a closed ring, so that the last descriptor 2479 * points back to the first. 2480 */ 2481 static int 2482 dc_list_rx_init(struct dc_softc *sc) 2483 { 2484 struct dc_chain_data *cd; 2485 struct dc_list_data *ld; 2486 int i, nexti; 2487 2488 cd = &sc->dc_cdata; 2489 ld = sc->dc_ldata; 2490 2491 for (i = 0; i < DC_RX_LIST_CNT; i++) { 2492 if (dc_newbuf(sc, i, 1) != 0) 2493 return (ENOBUFS); 2494 if (i == DC_RX_LIST_CNT - 1) 2495 nexti = 0; 2496 else 2497 nexti = i + 1; 2498 ld->dc_rx_list[i].dc_next = htole32(DC_RXDESC(sc, nexti)); 2499 } 2500 2501 cd->dc_rx_prod = 0; 2502 bus_dmamap_sync(sc->dc_ltag, sc->dc_lmap, 2503 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2504 return (0); 2505 } 2506 2507 static void 2508 dc_dma_map_rxbuf(arg, segs, nseg, mapsize, error) 2509 void *arg; 2510 bus_dma_segment_t *segs; 2511 int nseg; 2512 bus_size_t mapsize; 2513 int error; 2514 { 2515 struct dc_softc *sc; 2516 struct dc_desc *c; 2517 2518 sc = arg; 2519 c = &sc->dc_ldata->dc_rx_list[sc->dc_cdata.dc_rx_cur]; 2520 if (error) { 2521 sc->dc_cdata.dc_rx_err = error; 2522 return; 2523 } 2524 2525 KASSERT(nseg == 1, ("wrong number of segments, should be 1")); 2526 sc->dc_cdata.dc_rx_err = 0; 2527 c->dc_data = htole32(segs->ds_addr); 2528 } 2529 2530 /* 2531 * Initialize an RX descriptor and attach an MBUF cluster. 2532 */ 2533 static int 2534 dc_newbuf(struct dc_softc *sc, int i, int alloc) 2535 { 2536 struct mbuf *m_new; 2537 bus_dmamap_t tmp; 2538 int error; 2539 2540 if (alloc) { 2541 m_new = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR); 2542 if (m_new == NULL) 2543 return (ENOBUFS); 2544 } else { 2545 m_new = sc->dc_cdata.dc_rx_chain[i]; 2546 m_new->m_data = m_new->m_ext.ext_buf; 2547 } 2548 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 2549 m_adj(m_new, sizeof(u_int64_t)); 2550 2551 /* 2552 * If this is a PNIC chip, zero the buffer. This is part 2553 * of the workaround for the receive bug in the 82c168 and 2554 * 82c169 chips. 2555 */ 2556 if (sc->dc_flags & DC_PNIC_RX_BUG_WAR) 2557 bzero(mtod(m_new, char *), m_new->m_len); 2558 2559 /* No need to remap the mbuf if we're reusing it. */ 2560 if (alloc) { 2561 sc->dc_cdata.dc_rx_cur = i; 2562 error = bus_dmamap_load_mbuf(sc->dc_mtag, sc->dc_sparemap, 2563 m_new, dc_dma_map_rxbuf, sc, 0); 2564 if (error) { 2565 m_freem(m_new); 2566 return (error); 2567 } 2568 if (sc->dc_cdata.dc_rx_err != 0) { 2569 m_freem(m_new); 2570 return (sc->dc_cdata.dc_rx_err); 2571 } 2572 bus_dmamap_unload(sc->dc_mtag, sc->dc_cdata.dc_rx_map[i]); 2573 tmp = sc->dc_cdata.dc_rx_map[i]; 2574 sc->dc_cdata.dc_rx_map[i] = sc->dc_sparemap; 2575 sc->dc_sparemap = tmp; 2576 sc->dc_cdata.dc_rx_chain[i] = m_new; 2577 } 2578 2579 sc->dc_ldata->dc_rx_list[i].dc_ctl = htole32(DC_RXCTL_RLINK | DC_RXLEN); 2580 sc->dc_ldata->dc_rx_list[i].dc_status = htole32(DC_RXSTAT_OWN); 2581 bus_dmamap_sync(sc->dc_mtag, sc->dc_cdata.dc_rx_map[i], 2582 BUS_DMASYNC_PREREAD); 2583 bus_dmamap_sync(sc->dc_ltag, sc->dc_lmap, 2584 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2585 return (0); 2586 } 2587 2588 /* 2589 * Grrrrr. 2590 * The PNIC chip has a terrible bug in it that manifests itself during 2591 * periods of heavy activity. The exact mode of failure if difficult to 2592 * pinpoint: sometimes it only happens in promiscuous mode, sometimes it 2593 * will happen on slow machines. The bug is that sometimes instead of 2594 * uploading one complete frame during reception, it uploads what looks 2595 * like the entire contents of its FIFO memory. The frame we want is at 2596 * the end of the whole mess, but we never know exactly how much data has 2597 * been uploaded, so salvaging the frame is hard. 2598 * 2599 * There is only one way to do it reliably, and it's disgusting. 2600 * Here's what we know: 2601 * 2602 * - We know there will always be somewhere between one and three extra 2603 * descriptors uploaded. 2604 * 2605 * - We know the desired received frame will always be at the end of the 2606 * total data upload. 2607 * 2608 * - We know the size of the desired received frame because it will be 2609 * provided in the length field of the status word in the last descriptor. 2610 * 2611 * Here's what we do: 2612 * 2613 * - When we allocate buffers for the receive ring, we bzero() them. 2614 * This means that we know that the buffer contents should be all 2615 * zeros, except for data uploaded by the chip. 2616 * 2617 * - We also force the PNIC chip to upload frames that include the 2618 * ethernet CRC at the end. 2619 * 2620 * - We gather all of the bogus frame data into a single buffer. 2621 * 2622 * - We then position a pointer at the end of this buffer and scan 2623 * backwards until we encounter the first non-zero byte of data. 2624 * This is the end of the received frame. We know we will encounter 2625 * some data at the end of the frame because the CRC will always be 2626 * there, so even if the sender transmits a packet of all zeros, 2627 * we won't be fooled. 2628 * 2629 * - We know the size of the actual received frame, so we subtract 2630 * that value from the current pointer location. This brings us 2631 * to the start of the actual received packet. 2632 * 2633 * - We copy this into an mbuf and pass it on, along with the actual 2634 * frame length. 2635 * 2636 * The performance hit is tremendous, but it beats dropping frames all 2637 * the time. 2638 */ 2639 2640 #define DC_WHOLEFRAME (DC_RXSTAT_FIRSTFRAG | DC_RXSTAT_LASTFRAG) 2641 static void 2642 dc_pnic_rx_bug_war(struct dc_softc *sc, int idx) 2643 { 2644 struct dc_desc *cur_rx; 2645 struct dc_desc *c = NULL; 2646 struct mbuf *m = NULL; 2647 unsigned char *ptr; 2648 int i, total_len; 2649 u_int32_t rxstat = 0; 2650 2651 i = sc->dc_pnic_rx_bug_save; 2652 cur_rx = &sc->dc_ldata->dc_rx_list[idx]; 2653 ptr = sc->dc_pnic_rx_buf; 2654 bzero(ptr, DC_RXLEN * 5); 2655 2656 /* Copy all the bytes from the bogus buffers. */ 2657 while (1) { 2658 c = &sc->dc_ldata->dc_rx_list[i]; 2659 rxstat = le32toh(c->dc_status); 2660 m = sc->dc_cdata.dc_rx_chain[i]; 2661 bcopy(mtod(m, char *), ptr, DC_RXLEN); 2662 ptr += DC_RXLEN; 2663 /* If this is the last buffer, break out. */ 2664 if (i == idx || rxstat & DC_RXSTAT_LASTFRAG) 2665 break; 2666 dc_newbuf(sc, i, 0); 2667 DC_INC(i, DC_RX_LIST_CNT); 2668 } 2669 2670 /* Find the length of the actual receive frame. */ 2671 total_len = DC_RXBYTES(rxstat); 2672 2673 /* Scan backwards until we hit a non-zero byte. */ 2674 while (*ptr == 0x00) 2675 ptr--; 2676 2677 /* Round off. */ 2678 if ((uintptr_t)(ptr) & 0x3) 2679 ptr -= 1; 2680 2681 /* Now find the start of the frame. */ 2682 ptr -= total_len; 2683 if (ptr < sc->dc_pnic_rx_buf) 2684 ptr = sc->dc_pnic_rx_buf; 2685 2686 /* 2687 * Now copy the salvaged frame to the last mbuf and fake up 2688 * the status word to make it look like a successful 2689 * frame reception. 2690 */ 2691 dc_newbuf(sc, i, 0); 2692 bcopy(ptr, mtod(m, char *), total_len); 2693 cur_rx->dc_status = htole32(rxstat | DC_RXSTAT_FIRSTFRAG); 2694 } 2695 2696 /* 2697 * This routine searches the RX ring for dirty descriptors in the 2698 * event that the rxeof routine falls out of sync with the chip's 2699 * current descriptor pointer. This may happen sometimes as a result 2700 * of a "no RX buffer available" condition that happens when the chip 2701 * consumes all of the RX buffers before the driver has a chance to 2702 * process the RX ring. This routine may need to be called more than 2703 * once to bring the driver back in sync with the chip, however we 2704 * should still be getting RX DONE interrupts to drive the search 2705 * for new packets in the RX ring, so we should catch up eventually. 2706 */ 2707 static int 2708 dc_rx_resync(struct dc_softc *sc) 2709 { 2710 struct dc_desc *cur_rx; 2711 int i, pos; 2712 2713 pos = sc->dc_cdata.dc_rx_prod; 2714 2715 for (i = 0; i < DC_RX_LIST_CNT; i++) { 2716 cur_rx = &sc->dc_ldata->dc_rx_list[pos]; 2717 if (!(le32toh(cur_rx->dc_status) & DC_RXSTAT_OWN)) 2718 break; 2719 DC_INC(pos, DC_RX_LIST_CNT); 2720 } 2721 2722 /* If the ring really is empty, then just return. */ 2723 if (i == DC_RX_LIST_CNT) 2724 return (0); 2725 2726 /* We've fallen behing the chip: catch it. */ 2727 sc->dc_cdata.dc_rx_prod = pos; 2728 2729 return (EAGAIN); 2730 } 2731 2732 /* 2733 * A frame has been uploaded: pass the resulting mbuf chain up to 2734 * the higher level protocols. 2735 */ 2736 static void 2737 dc_rxeof(struct dc_softc *sc) 2738 { 2739 struct mbuf *m; 2740 struct ifnet *ifp; 2741 struct dc_desc *cur_rx; 2742 int i, total_len = 0; 2743 u_int32_t rxstat; 2744 2745 DC_LOCK_ASSERT(sc); 2746 2747 ifp = &sc->arpcom.ac_if; 2748 i = sc->dc_cdata.dc_rx_prod; 2749 2750 bus_dmamap_sync(sc->dc_ltag, sc->dc_lmap, BUS_DMASYNC_POSTREAD); 2751 while (!(le32toh(sc->dc_ldata->dc_rx_list[i].dc_status) & 2752 DC_RXSTAT_OWN)) { 2753 #ifdef DEVICE_POLLING 2754 if (ifp->if_flags & IFF_POLLING) { 2755 if (sc->rxcycles <= 0) 2756 break; 2757 sc->rxcycles--; 2758 } 2759 #endif 2760 cur_rx = &sc->dc_ldata->dc_rx_list[i]; 2761 rxstat = le32toh(cur_rx->dc_status); 2762 m = sc->dc_cdata.dc_rx_chain[i]; 2763 bus_dmamap_sync(sc->dc_mtag, sc->dc_cdata.dc_rx_map[i], 2764 BUS_DMASYNC_POSTREAD); 2765 total_len = DC_RXBYTES(rxstat); 2766 2767 if (sc->dc_flags & DC_PNIC_RX_BUG_WAR) { 2768 if ((rxstat & DC_WHOLEFRAME) != DC_WHOLEFRAME) { 2769 if (rxstat & DC_RXSTAT_FIRSTFRAG) 2770 sc->dc_pnic_rx_bug_save = i; 2771 if ((rxstat & DC_RXSTAT_LASTFRAG) == 0) { 2772 DC_INC(i, DC_RX_LIST_CNT); 2773 continue; 2774 } 2775 dc_pnic_rx_bug_war(sc, i); 2776 rxstat = le32toh(cur_rx->dc_status); 2777 total_len = DC_RXBYTES(rxstat); 2778 } 2779 } 2780 2781 /* 2782 * If an error occurs, update stats, clear the 2783 * status word and leave the mbuf cluster in place: 2784 * it should simply get re-used next time this descriptor 2785 * comes up in the ring. However, don't report long 2786 * frames as errors since they could be vlans. 2787 */ 2788 if ((rxstat & DC_RXSTAT_RXERR)) { 2789 if (!(rxstat & DC_RXSTAT_GIANT) || 2790 (rxstat & (DC_RXSTAT_CRCERR | DC_RXSTAT_DRIBBLE | 2791 DC_RXSTAT_MIIERE | DC_RXSTAT_COLLSEEN | 2792 DC_RXSTAT_RUNT | DC_RXSTAT_DE))) { 2793 ifp->if_ierrors++; 2794 if (rxstat & DC_RXSTAT_COLLSEEN) 2795 ifp->if_collisions++; 2796 dc_newbuf(sc, i, 0); 2797 if (rxstat & DC_RXSTAT_CRCERR) { 2798 DC_INC(i, DC_RX_LIST_CNT); 2799 continue; 2800 } else { 2801 dc_init(sc); 2802 return; 2803 } 2804 } 2805 } 2806 2807 /* No errors; receive the packet. */ 2808 total_len -= ETHER_CRC_LEN; 2809 #ifdef __i386__ 2810 /* 2811 * On the x86 we do not have alignment problems, so try to 2812 * allocate a new buffer for the receive ring, and pass up 2813 * the one where the packet is already, saving the expensive 2814 * copy done in m_devget(). 2815 * If we are on an architecture with alignment problems, or 2816 * if the allocation fails, then use m_devget and leave the 2817 * existing buffer in the receive ring. 2818 */ 2819 if (dc_quick && dc_newbuf(sc, i, 1) == 0) { 2820 m->m_pkthdr.rcvif = ifp; 2821 m->m_pkthdr.len = m->m_len = total_len; 2822 DC_INC(i, DC_RX_LIST_CNT); 2823 } else 2824 #endif 2825 { 2826 struct mbuf *m0; 2827 2828 m0 = m_devget(mtod(m, char *), total_len, 2829 ETHER_ALIGN, ifp, NULL); 2830 dc_newbuf(sc, i, 0); 2831 DC_INC(i, DC_RX_LIST_CNT); 2832 if (m0 == NULL) { 2833 ifp->if_ierrors++; 2834 continue; 2835 } 2836 m = m0; 2837 } 2838 2839 ifp->if_ipackets++; 2840 DC_UNLOCK(sc); 2841 (*ifp->if_input)(ifp, m); 2842 DC_LOCK(sc); 2843 } 2844 2845 sc->dc_cdata.dc_rx_prod = i; 2846 } 2847 2848 /* 2849 * A frame was downloaded to the chip. It's safe for us to clean up 2850 * the list buffers. 2851 */ 2852 2853 static void 2854 dc_txeof(struct dc_softc *sc) 2855 { 2856 struct dc_desc *cur_tx = NULL; 2857 struct ifnet *ifp; 2858 int idx; 2859 u_int32_t ctl, txstat; 2860 2861 ifp = &sc->arpcom.ac_if; 2862 2863 /* 2864 * Go through our tx list and free mbufs for those 2865 * frames that have been transmitted. 2866 */ 2867 bus_dmamap_sync(sc->dc_ltag, sc->dc_lmap, BUS_DMASYNC_POSTREAD); 2868 idx = sc->dc_cdata.dc_tx_cons; 2869 while (idx != sc->dc_cdata.dc_tx_prod) { 2870 2871 cur_tx = &sc->dc_ldata->dc_tx_list[idx]; 2872 txstat = le32toh(cur_tx->dc_status); 2873 ctl = le32toh(cur_tx->dc_ctl); 2874 2875 if (txstat & DC_TXSTAT_OWN) 2876 break; 2877 2878 if (!(ctl & DC_TXCTL_LASTFRAG) || ctl & DC_TXCTL_SETUP) { 2879 if (ctl & DC_TXCTL_SETUP) { 2880 /* 2881 * Yes, the PNIC is so brain damaged 2882 * that it will sometimes generate a TX 2883 * underrun error while DMAing the RX 2884 * filter setup frame. If we detect this, 2885 * we have to send the setup frame again, 2886 * or else the filter won't be programmed 2887 * correctly. 2888 */ 2889 if (DC_IS_PNIC(sc)) { 2890 if (txstat & DC_TXSTAT_ERRSUM) 2891 dc_setfilt(sc); 2892 } 2893 sc->dc_cdata.dc_tx_chain[idx] = NULL; 2894 } 2895 sc->dc_cdata.dc_tx_cnt--; 2896 DC_INC(idx, DC_TX_LIST_CNT); 2897 continue; 2898 } 2899 2900 if (DC_IS_XIRCOM(sc) || DC_IS_CONEXANT(sc)) { 2901 /* 2902 * XXX: Why does my Xircom taunt me so? 2903 * For some reason it likes setting the CARRLOST flag 2904 * even when the carrier is there. wtf?!? 2905 * Who knows, but Conexant chips have the 2906 * same problem. Maybe they took lessons 2907 * from Xircom. 2908 */ 2909 if (/*sc->dc_type == DC_TYPE_21143 &&*/ 2910 sc->dc_pmode == DC_PMODE_MII && 2911 ((txstat & 0xFFFF) & ~(DC_TXSTAT_ERRSUM | 2912 DC_TXSTAT_NOCARRIER))) 2913 txstat &= ~DC_TXSTAT_ERRSUM; 2914 } else { 2915 if (/*sc->dc_type == DC_TYPE_21143 &&*/ 2916 sc->dc_pmode == DC_PMODE_MII && 2917 ((txstat & 0xFFFF) & ~(DC_TXSTAT_ERRSUM | 2918 DC_TXSTAT_NOCARRIER | DC_TXSTAT_CARRLOST))) 2919 txstat &= ~DC_TXSTAT_ERRSUM; 2920 } 2921 2922 if (txstat & DC_TXSTAT_ERRSUM) { 2923 ifp->if_oerrors++; 2924 if (txstat & DC_TXSTAT_EXCESSCOLL) 2925 ifp->if_collisions++; 2926 if (txstat & DC_TXSTAT_LATECOLL) 2927 ifp->if_collisions++; 2928 if (!(txstat & DC_TXSTAT_UNDERRUN)) { 2929 dc_init(sc); 2930 return; 2931 } 2932 } 2933 2934 ifp->if_collisions += (txstat & DC_TXSTAT_COLLCNT) >> 3; 2935 2936 ifp->if_opackets++; 2937 if (sc->dc_cdata.dc_tx_chain[idx] != NULL) { 2938 bus_dmamap_sync(sc->dc_mtag, 2939 sc->dc_cdata.dc_tx_map[idx], 2940 BUS_DMASYNC_POSTWRITE); 2941 bus_dmamap_unload(sc->dc_mtag, 2942 sc->dc_cdata.dc_tx_map[idx]); 2943 m_freem(sc->dc_cdata.dc_tx_chain[idx]); 2944 sc->dc_cdata.dc_tx_chain[idx] = NULL; 2945 } 2946 2947 sc->dc_cdata.dc_tx_cnt--; 2948 DC_INC(idx, DC_TX_LIST_CNT); 2949 } 2950 2951 if (idx != sc->dc_cdata.dc_tx_cons) { 2952 /* Some buffers have been freed. */ 2953 sc->dc_cdata.dc_tx_cons = idx; 2954 ifp->if_flags &= ~IFF_OACTIVE; 2955 } 2956 ifp->if_timer = (sc->dc_cdata.dc_tx_cnt == 0) ? 0 : 5; 2957 } 2958 2959 static void 2960 dc_tick(void *xsc) 2961 { 2962 struct dc_softc *sc; 2963 struct mii_data *mii; 2964 struct ifnet *ifp; 2965 u_int32_t r; 2966 2967 sc = xsc; 2968 DC_LOCK(sc); 2969 ifp = &sc->arpcom.ac_if; 2970 mii = device_get_softc(sc->dc_miibus); 2971 2972 if (sc->dc_flags & DC_REDUCED_MII_POLL) { 2973 if (sc->dc_flags & DC_21143_NWAY) { 2974 r = CSR_READ_4(sc, DC_10BTSTAT); 2975 if (IFM_SUBTYPE(mii->mii_media_active) == 2976 IFM_100_TX && (r & DC_TSTAT_LS100)) { 2977 sc->dc_link = 0; 2978 mii_mediachg(mii); 2979 } 2980 if (IFM_SUBTYPE(mii->mii_media_active) == 2981 IFM_10_T && (r & DC_TSTAT_LS10)) { 2982 sc->dc_link = 0; 2983 mii_mediachg(mii); 2984 } 2985 if (sc->dc_link == 0) 2986 mii_tick(mii); 2987 } else { 2988 r = CSR_READ_4(sc, DC_ISR); 2989 if ((r & DC_ISR_RX_STATE) == DC_RXSTATE_WAIT && 2990 sc->dc_cdata.dc_tx_cnt == 0) { 2991 mii_tick(mii); 2992 if (!(mii->mii_media_status & IFM_ACTIVE)) 2993 sc->dc_link = 0; 2994 } 2995 } 2996 } else 2997 mii_tick(mii); 2998 2999 /* 3000 * When the init routine completes, we expect to be able to send 3001 * packets right away, and in fact the network code will send a 3002 * gratuitous ARP the moment the init routine marks the interface 3003 * as running. However, even though the MAC may have been initialized, 3004 * there may be a delay of a few seconds before the PHY completes 3005 * autonegotiation and the link is brought up. Any transmissions 3006 * made during that delay will be lost. Dealing with this is tricky: 3007 * we can't just pause in the init routine while waiting for the 3008 * PHY to come ready since that would bring the whole system to 3009 * a screeching halt for several seconds. 3010 * 3011 * What we do here is prevent the TX start routine from sending 3012 * any packets until a link has been established. After the 3013 * interface has been initialized, the tick routine will poll 3014 * the state of the PHY until the IFM_ACTIVE flag is set. Until 3015 * that time, packets will stay in the send queue, and once the 3016 * link comes up, they will be flushed out to the wire. 3017 */ 3018 if (!sc->dc_link && mii->mii_media_status & IFM_ACTIVE && 3019 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) { 3020 sc->dc_link++; 3021 if (ifp->if_snd.ifq_head != NULL) 3022 dc_start(ifp); 3023 } 3024 3025 if (sc->dc_flags & DC_21143_NWAY && !sc->dc_link) 3026 callout_reset(&sc->dc_stat_ch, hz/10, dc_tick, sc); 3027 else 3028 callout_reset(&sc->dc_stat_ch, hz, dc_tick, sc); 3029 3030 DC_UNLOCK(sc); 3031 } 3032 3033 /* 3034 * A transmit underrun has occurred. Back off the transmit threshold, 3035 * or switch to store and forward mode if we have to. 3036 */ 3037 static void 3038 dc_tx_underrun(struct dc_softc *sc) 3039 { 3040 u_int32_t isr; 3041 int i; 3042 3043 if (DC_IS_DAVICOM(sc)) 3044 dc_init(sc); 3045 3046 if (DC_IS_INTEL(sc)) { 3047 /* 3048 * The real 21143 requires that the transmitter be idle 3049 * in order to change the transmit threshold or store 3050 * and forward state. 3051 */ 3052 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_TX_ON); 3053 3054 for (i = 0; i < DC_TIMEOUT; i++) { 3055 isr = CSR_READ_4(sc, DC_ISR); 3056 if (isr & DC_ISR_TX_IDLE) 3057 break; 3058 DELAY(10); 3059 } 3060 if (i == DC_TIMEOUT) { 3061 printf("dc%d: failed to force tx to idle state\n", 3062 sc->dc_unit); 3063 dc_init(sc); 3064 } 3065 } 3066 3067 printf("dc%d: TX underrun -- ", sc->dc_unit); 3068 sc->dc_txthresh += DC_TXTHRESH_INC; 3069 if (sc->dc_txthresh > DC_TXTHRESH_MAX) { 3070 printf("using store and forward mode\n"); 3071 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_STORENFWD); 3072 } else { 3073 printf("increasing TX threshold\n"); 3074 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_TX_THRESH); 3075 DC_SETBIT(sc, DC_NETCFG, sc->dc_txthresh); 3076 } 3077 3078 if (DC_IS_INTEL(sc)) 3079 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_TX_ON); 3080 } 3081 3082 #ifdef DEVICE_POLLING 3083 static poll_handler_t dc_poll; 3084 3085 static void 3086 dc_poll(struct ifnet *ifp, enum poll_cmd cmd, int count) 3087 { 3088 struct dc_softc *sc = ifp->if_softc; 3089 3090 if (!(ifp->if_capenable & IFCAP_POLLING)) { 3091 ether_poll_deregister(ifp); 3092 cmd = POLL_DEREGISTER; 3093 } 3094 if (cmd == POLL_DEREGISTER) { /* final call, enable interrupts */ 3095 /* Re-enable interrupts. */ 3096 CSR_WRITE_4(sc, DC_IMR, DC_INTRS); 3097 return; 3098 } 3099 DC_LOCK(sc); 3100 sc->rxcycles = count; 3101 dc_rxeof(sc); 3102 dc_txeof(sc); 3103 if (ifp->if_snd.ifq_head != NULL && !(ifp->if_flags & IFF_OACTIVE)) 3104 dc_start(ifp); 3105 3106 if (cmd == POLL_AND_CHECK_STATUS) { /* also check status register */ 3107 u_int32_t status; 3108 3109 status = CSR_READ_4(sc, DC_ISR); 3110 status &= (DC_ISR_RX_WATDOGTIMEO | DC_ISR_RX_NOBUF | 3111 DC_ISR_TX_NOBUF | DC_ISR_TX_IDLE | DC_ISR_TX_UNDERRUN | 3112 DC_ISR_BUS_ERR); 3113 if (!status) { 3114 DC_UNLOCK(sc); 3115 return; 3116 } 3117 /* ack what we have */ 3118 CSR_WRITE_4(sc, DC_ISR, status); 3119 3120 if (status & (DC_ISR_RX_WATDOGTIMEO | DC_ISR_RX_NOBUF)) { 3121 u_int32_t r = CSR_READ_4(sc, DC_FRAMESDISCARDED); 3122 ifp->if_ierrors += (r & 0xffff) + ((r >> 17) & 0x7ff); 3123 3124 if (dc_rx_resync(sc)) 3125 dc_rxeof(sc); 3126 } 3127 /* restart transmit unit if necessary */ 3128 if (status & DC_ISR_TX_IDLE && sc->dc_cdata.dc_tx_cnt) 3129 CSR_WRITE_4(sc, DC_TXSTART, 0xFFFFFFFF); 3130 3131 if (status & DC_ISR_TX_UNDERRUN) 3132 dc_tx_underrun(sc); 3133 3134 if (status & DC_ISR_BUS_ERR) { 3135 printf("dc_poll: dc%d bus error\n", sc->dc_unit); 3136 dc_reset(sc); 3137 dc_init(sc); 3138 } 3139 } 3140 DC_UNLOCK(sc); 3141 } 3142 #endif /* DEVICE_POLLING */ 3143 3144 static void 3145 dc_intr(void *arg) 3146 { 3147 struct dc_softc *sc; 3148 struct ifnet *ifp; 3149 u_int32_t status; 3150 3151 sc = arg; 3152 3153 if (sc->suspended) 3154 return; 3155 3156 if ((CSR_READ_4(sc, DC_ISR) & DC_INTRS) == 0) 3157 return; 3158 3159 DC_LOCK(sc); 3160 ifp = &sc->arpcom.ac_if; 3161 #ifdef DEVICE_POLLING 3162 if (ifp->if_flags & IFF_POLLING) 3163 goto done; 3164 if ((ifp->if_capenable & IFCAP_POLLING) && 3165 ether_poll_register(dc_poll, ifp)) { /* ok, disable interrupts */ 3166 CSR_WRITE_4(sc, DC_IMR, 0x00000000); 3167 goto done; 3168 } 3169 #endif 3170 3171 /* Suppress unwanted interrupts */ 3172 if (!(ifp->if_flags & IFF_UP)) { 3173 if (CSR_READ_4(sc, DC_ISR) & DC_INTRS) 3174 dc_stop(sc); 3175 DC_UNLOCK(sc); 3176 return; 3177 } 3178 3179 /* Disable interrupts. */ 3180 CSR_WRITE_4(sc, DC_IMR, 0x00000000); 3181 3182 while (((status = CSR_READ_4(sc, DC_ISR)) & DC_INTRS) 3183 && status != 0xFFFFFFFF) { 3184 3185 CSR_WRITE_4(sc, DC_ISR, status); 3186 3187 if (status & DC_ISR_RX_OK) { 3188 int curpkts; 3189 curpkts = ifp->if_ipackets; 3190 dc_rxeof(sc); 3191 if (curpkts == ifp->if_ipackets) { 3192 while (dc_rx_resync(sc)) 3193 dc_rxeof(sc); 3194 } 3195 } 3196 3197 if (status & (DC_ISR_TX_OK | DC_ISR_TX_NOBUF)) 3198 dc_txeof(sc); 3199 3200 if (status & DC_ISR_TX_IDLE) { 3201 dc_txeof(sc); 3202 if (sc->dc_cdata.dc_tx_cnt) { 3203 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_TX_ON); 3204 CSR_WRITE_4(sc, DC_TXSTART, 0xFFFFFFFF); 3205 } 3206 } 3207 3208 if (status & DC_ISR_TX_UNDERRUN) 3209 dc_tx_underrun(sc); 3210 3211 if ((status & DC_ISR_RX_WATDOGTIMEO) 3212 || (status & DC_ISR_RX_NOBUF)) { 3213 int curpkts; 3214 curpkts = ifp->if_ipackets; 3215 dc_rxeof(sc); 3216 if (curpkts == ifp->if_ipackets) { 3217 while (dc_rx_resync(sc)) 3218 dc_rxeof(sc); 3219 } 3220 } 3221 3222 if (status & DC_ISR_BUS_ERR) { 3223 dc_reset(sc); 3224 dc_init(sc); 3225 } 3226 } 3227 3228 /* Re-enable interrupts. */ 3229 CSR_WRITE_4(sc, DC_IMR, DC_INTRS); 3230 3231 if (ifp->if_snd.ifq_head != NULL) 3232 dc_start(ifp); 3233 3234 #ifdef DEVICE_POLLING 3235 done: 3236 #endif 3237 3238 DC_UNLOCK(sc); 3239 } 3240 3241 static void 3242 dc_dma_map_txbuf(arg, segs, nseg, mapsize, error) 3243 void *arg; 3244 bus_dma_segment_t *segs; 3245 int nseg; 3246 bus_size_t mapsize; 3247 int error; 3248 { 3249 struct dc_softc *sc; 3250 struct dc_desc *f; 3251 int cur, first, frag, i; 3252 3253 sc = arg; 3254 if (error) { 3255 sc->dc_cdata.dc_tx_err = error; 3256 return; 3257 } 3258 3259 first = cur = frag = sc->dc_cdata.dc_tx_prod; 3260 for (i = 0; i < nseg; i++) { 3261 if ((sc->dc_flags & DC_TX_ADMTEK_WAR) && 3262 (frag == (DC_TX_LIST_CNT - 1)) && 3263 (first != sc->dc_cdata.dc_tx_first)) { 3264 bus_dmamap_unload(sc->dc_mtag, 3265 sc->dc_cdata.dc_tx_map[first]); 3266 sc->dc_cdata.dc_tx_err = ENOBUFS; 3267 return; 3268 } 3269 3270 f = &sc->dc_ldata->dc_tx_list[frag]; 3271 f->dc_ctl = htole32(DC_TXCTL_TLINK | segs[i].ds_len); 3272 if (i == 0) { 3273 f->dc_status = 0; 3274 f->dc_ctl |= htole32(DC_TXCTL_FIRSTFRAG); 3275 } else 3276 f->dc_status = htole32(DC_TXSTAT_OWN); 3277 f->dc_data = htole32(segs[i].ds_addr); 3278 cur = frag; 3279 DC_INC(frag, DC_TX_LIST_CNT); 3280 } 3281 3282 sc->dc_cdata.dc_tx_err = 0; 3283 sc->dc_cdata.dc_tx_prod = frag; 3284 sc->dc_cdata.dc_tx_cnt += nseg; 3285 sc->dc_ldata->dc_tx_list[cur].dc_ctl |= htole32(DC_TXCTL_LASTFRAG); 3286 sc->dc_cdata.dc_tx_chain[cur] = sc->dc_cdata.dc_tx_mapping; 3287 if (sc->dc_flags & DC_TX_INTR_FIRSTFRAG) 3288 sc->dc_ldata->dc_tx_list[first].dc_ctl |= 3289 htole32(DC_TXCTL_FINT); 3290 if (sc->dc_flags & DC_TX_INTR_ALWAYS) 3291 sc->dc_ldata->dc_tx_list[cur].dc_ctl |= htole32(DC_TXCTL_FINT); 3292 if (sc->dc_flags & DC_TX_USE_TX_INTR && sc->dc_cdata.dc_tx_cnt > 64) 3293 sc->dc_ldata->dc_tx_list[cur].dc_ctl |= htole32(DC_TXCTL_FINT); 3294 sc->dc_ldata->dc_tx_list[first].dc_status = htole32(DC_TXSTAT_OWN); 3295 } 3296 3297 /* 3298 * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data 3299 * pointers to the fragment pointers. 3300 */ 3301 static int 3302 dc_encap(struct dc_softc *sc, struct mbuf **m_head) 3303 { 3304 struct mbuf *m; 3305 int error, idx, chainlen = 0; 3306 3307 /* 3308 * If there's no way we can send any packets, return now. 3309 */ 3310 if (DC_TX_LIST_CNT - sc->dc_cdata.dc_tx_cnt < 6) 3311 return (ENOBUFS); 3312 3313 /* 3314 * Count the number of frags in this chain to see if 3315 * we need to m_defrag. Since the descriptor list is shared 3316 * by all packets, we'll m_defrag long chains so that they 3317 * do not use up the entire list, even if they would fit. 3318 */ 3319 for (m = *m_head; m != NULL; m = m->m_next) 3320 chainlen++; 3321 3322 if ((chainlen > DC_TX_LIST_CNT / 4) || 3323 ((DC_TX_LIST_CNT - (chainlen + sc->dc_cdata.dc_tx_cnt)) < 6)) { 3324 m = m_defrag(*m_head, M_DONTWAIT); 3325 if (m == NULL) 3326 return (ENOBUFS); 3327 *m_head = m; 3328 } 3329 3330 /* 3331 * Start packing the mbufs in this chain into 3332 * the fragment pointers. Stop when we run out 3333 * of fragments or hit the end of the mbuf chain. 3334 */ 3335 idx = sc->dc_cdata.dc_tx_prod; 3336 sc->dc_cdata.dc_tx_mapping = *m_head; 3337 error = bus_dmamap_load_mbuf(sc->dc_mtag, sc->dc_cdata.dc_tx_map[idx], 3338 *m_head, dc_dma_map_txbuf, sc, 0); 3339 if (error) 3340 return (error); 3341 if (sc->dc_cdata.dc_tx_err != 0) 3342 return (sc->dc_cdata.dc_tx_err); 3343 bus_dmamap_sync(sc->dc_mtag, sc->dc_cdata.dc_tx_map[idx], 3344 BUS_DMASYNC_PREWRITE); 3345 bus_dmamap_sync(sc->dc_ltag, sc->dc_lmap, 3346 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3347 return (0); 3348 } 3349 3350 /* 3351 * Main transmit routine. To avoid having to do mbuf copies, we put pointers 3352 * to the mbuf data regions directly in the transmit lists. We also save a 3353 * copy of the pointers since the transmit list fragment pointers are 3354 * physical addresses. 3355 */ 3356 3357 static void 3358 dc_start(struct ifnet *ifp) 3359 { 3360 struct dc_softc *sc; 3361 struct mbuf *m_head = NULL, *m; 3362 int idx; 3363 3364 sc = ifp->if_softc; 3365 3366 DC_LOCK(sc); 3367 3368 if (!sc->dc_link && ifp->if_snd.ifq_len < 10) { 3369 DC_UNLOCK(sc); 3370 return; 3371 } 3372 3373 if (ifp->if_flags & IFF_OACTIVE) { 3374 DC_UNLOCK(sc); 3375 return; 3376 } 3377 3378 idx = sc->dc_cdata.dc_tx_first = sc->dc_cdata.dc_tx_prod; 3379 3380 while (sc->dc_cdata.dc_tx_chain[idx] == NULL) { 3381 IF_DEQUEUE(&ifp->if_snd, m_head); 3382 if (m_head == NULL) 3383 break; 3384 3385 if (sc->dc_flags & DC_TX_COALESCE && 3386 (m_head->m_next != NULL || 3387 sc->dc_flags & DC_TX_ALIGN)) { 3388 m = m_defrag(m_head, M_DONTWAIT); 3389 if (m == NULL) { 3390 IF_PREPEND(&ifp->if_snd, m_head); 3391 ifp->if_flags |= IFF_OACTIVE; 3392 break; 3393 } else { 3394 m_head = m; 3395 } 3396 } 3397 3398 if (dc_encap(sc, &m_head)) { 3399 IF_PREPEND(&ifp->if_snd, m_head); 3400 ifp->if_flags |= IFF_OACTIVE; 3401 break; 3402 } 3403 idx = sc->dc_cdata.dc_tx_prod; 3404 3405 /* 3406 * If there's a BPF listener, bounce a copy of this frame 3407 * to him. 3408 */ 3409 BPF_MTAP(ifp, m_head); 3410 3411 if (sc->dc_flags & DC_TX_ONE) { 3412 ifp->if_flags |= IFF_OACTIVE; 3413 break; 3414 } 3415 } 3416 3417 /* Transmit */ 3418 if (!(sc->dc_flags & DC_TX_POLL)) 3419 CSR_WRITE_4(sc, DC_TXSTART, 0xFFFFFFFF); 3420 3421 /* 3422 * Set a timeout in case the chip goes out to lunch. 3423 */ 3424 ifp->if_timer = 5; 3425 3426 DC_UNLOCK(sc); 3427 } 3428 3429 static void 3430 dc_init(void *xsc) 3431 { 3432 struct dc_softc *sc = xsc; 3433 struct ifnet *ifp = &sc->arpcom.ac_if; 3434 struct mii_data *mii; 3435 3436 DC_LOCK(sc); 3437 3438 mii = device_get_softc(sc->dc_miibus); 3439 3440 /* 3441 * Cancel pending I/O and free all RX/TX buffers. 3442 */ 3443 dc_stop(sc); 3444 dc_reset(sc); 3445 3446 /* 3447 * Set cache alignment and burst length. 3448 */ 3449 if (DC_IS_ASIX(sc) || DC_IS_DAVICOM(sc)) 3450 CSR_WRITE_4(sc, DC_BUSCTL, 0); 3451 else 3452 CSR_WRITE_4(sc, DC_BUSCTL, DC_BUSCTL_MRME | DC_BUSCTL_MRLE); 3453 /* 3454 * Evenly share the bus between receive and transmit process. 3455 */ 3456 if (DC_IS_INTEL(sc)) 3457 DC_SETBIT(sc, DC_BUSCTL, DC_BUSCTL_ARBITRATION); 3458 if (DC_IS_DAVICOM(sc) || DC_IS_INTEL(sc)) { 3459 DC_SETBIT(sc, DC_BUSCTL, DC_BURSTLEN_USECA); 3460 } else { 3461 DC_SETBIT(sc, DC_BUSCTL, DC_BURSTLEN_16LONG); 3462 } 3463 if (sc->dc_flags & DC_TX_POLL) 3464 DC_SETBIT(sc, DC_BUSCTL, DC_TXPOLL_1); 3465 switch(sc->dc_cachesize) { 3466 case 32: 3467 DC_SETBIT(sc, DC_BUSCTL, DC_CACHEALIGN_32LONG); 3468 break; 3469 case 16: 3470 DC_SETBIT(sc, DC_BUSCTL, DC_CACHEALIGN_16LONG); 3471 break; 3472 case 8: 3473 DC_SETBIT(sc, DC_BUSCTL, DC_CACHEALIGN_8LONG); 3474 break; 3475 case 0: 3476 default: 3477 DC_SETBIT(sc, DC_BUSCTL, DC_CACHEALIGN_NONE); 3478 break; 3479 } 3480 3481 if (sc->dc_flags & DC_TX_STORENFWD) 3482 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_STORENFWD); 3483 else { 3484 if (sc->dc_txthresh > DC_TXTHRESH_MAX) { 3485 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_STORENFWD); 3486 } else { 3487 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_STORENFWD); 3488 DC_SETBIT(sc, DC_NETCFG, sc->dc_txthresh); 3489 } 3490 } 3491 3492 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_NO_RXCRC); 3493 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_TX_BACKOFF); 3494 3495 if (DC_IS_MACRONIX(sc) || DC_IS_PNICII(sc)) { 3496 /* 3497 * The app notes for the 98713 and 98715A say that 3498 * in order to have the chips operate properly, a magic 3499 * number must be written to CSR16. Macronix does not 3500 * document the meaning of these bits so there's no way 3501 * to know exactly what they do. The 98713 has a magic 3502 * number all its own; the rest all use a different one. 3503 */ 3504 DC_CLRBIT(sc, DC_MX_MAGICPACKET, 0xFFFF0000); 3505 if (sc->dc_type == DC_TYPE_98713) 3506 DC_SETBIT(sc, DC_MX_MAGICPACKET, DC_MX_MAGIC_98713); 3507 else 3508 DC_SETBIT(sc, DC_MX_MAGICPACKET, DC_MX_MAGIC_98715); 3509 } 3510 3511 if (DC_IS_XIRCOM(sc)) { 3512 /* 3513 * setup General Purpose Port mode and data so the tulip 3514 * can talk to the MII. 3515 */ 3516 CSR_WRITE_4(sc, DC_SIAGP, DC_SIAGP_WRITE_EN | DC_SIAGP_INT1_EN | 3517 DC_SIAGP_MD_GP2_OUTPUT | DC_SIAGP_MD_GP0_OUTPUT); 3518 DELAY(10); 3519 CSR_WRITE_4(sc, DC_SIAGP, DC_SIAGP_INT1_EN | 3520 DC_SIAGP_MD_GP2_OUTPUT | DC_SIAGP_MD_GP0_OUTPUT); 3521 DELAY(10); 3522 } 3523 3524 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_TX_THRESH); 3525 DC_SETBIT(sc, DC_NETCFG, DC_TXTHRESH_MIN); 3526 3527 /* Init circular RX list. */ 3528 if (dc_list_rx_init(sc) == ENOBUFS) { 3529 printf("dc%d: initialization failed: no " 3530 "memory for rx buffers\n", sc->dc_unit); 3531 dc_stop(sc); 3532 DC_UNLOCK(sc); 3533 return; 3534 } 3535 3536 /* 3537 * Init TX descriptors. 3538 */ 3539 dc_list_tx_init(sc); 3540 3541 /* 3542 * Load the address of the RX list. 3543 */ 3544 CSR_WRITE_4(sc, DC_RXADDR, DC_RXDESC(sc, 0)); 3545 CSR_WRITE_4(sc, DC_TXADDR, DC_TXDESC(sc, 0)); 3546 3547 /* 3548 * Enable interrupts. 3549 */ 3550 #ifdef DEVICE_POLLING 3551 /* 3552 * ... but only if we are not polling, and make sure they are off in 3553 * the case of polling. Some cards (e.g. fxp) turn interrupts on 3554 * after a reset. 3555 */ 3556 if (ifp->if_flags & IFF_POLLING) 3557 CSR_WRITE_4(sc, DC_IMR, 0x00000000); 3558 else 3559 #endif 3560 CSR_WRITE_4(sc, DC_IMR, DC_INTRS); 3561 CSR_WRITE_4(sc, DC_ISR, 0xFFFFFFFF); 3562 3563 /* Enable transmitter. */ 3564 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_TX_ON); 3565 3566 /* 3567 * If this is an Intel 21143 and we're not using the 3568 * MII port, program the LED control pins so we get 3569 * link and activity indications. 3570 */ 3571 if (sc->dc_flags & DC_TULIP_LEDS) { 3572 CSR_WRITE_4(sc, DC_WATCHDOG, 3573 DC_WDOG_CTLWREN | DC_WDOG_LINK | DC_WDOG_ACTIVITY); 3574 CSR_WRITE_4(sc, DC_WATCHDOG, 0); 3575 } 3576 3577 /* 3578 * Load the RX/multicast filter. We do this sort of late 3579 * because the filter programming scheme on the 21143 and 3580 * some clones requires DMAing a setup frame via the TX 3581 * engine, and we need the transmitter enabled for that. 3582 */ 3583 dc_setfilt(sc); 3584 3585 /* Enable receiver. */ 3586 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_ON); 3587 CSR_WRITE_4(sc, DC_RXSTART, 0xFFFFFFFF); 3588 3589 mii_mediachg(mii); 3590 dc_setcfg(sc, sc->dc_if_media); 3591 3592 ifp->if_flags |= IFF_RUNNING; 3593 ifp->if_flags &= ~IFF_OACTIVE; 3594 3595 /* Don't start the ticker if this is a homePNA link. */ 3596 if (IFM_SUBTYPE(mii->mii_media.ifm_media) == IFM_HPNA_1) 3597 sc->dc_link = 1; 3598 else { 3599 if (sc->dc_flags & DC_21143_NWAY) 3600 callout_reset(&sc->dc_stat_ch, hz/10, dc_tick, sc); 3601 else 3602 callout_reset(&sc->dc_stat_ch, hz, dc_tick, sc); 3603 } 3604 3605 #ifdef SRM_MEDIA 3606 if(sc->dc_srm_media) { 3607 struct ifreq ifr; 3608 3609 ifr.ifr_media = sc->dc_srm_media; 3610 ifmedia_ioctl(ifp, &ifr, &mii->mii_media, SIOCSIFMEDIA); 3611 sc->dc_srm_media = 0; 3612 } 3613 #endif 3614 DC_UNLOCK(sc); 3615 } 3616 3617 /* 3618 * Set media options. 3619 */ 3620 static int 3621 dc_ifmedia_upd(struct ifnet *ifp) 3622 { 3623 struct dc_softc *sc; 3624 struct mii_data *mii; 3625 struct ifmedia *ifm; 3626 3627 sc = ifp->if_softc; 3628 mii = device_get_softc(sc->dc_miibus); 3629 mii_mediachg(mii); 3630 ifm = &mii->mii_media; 3631 3632 if (DC_IS_DAVICOM(sc) && 3633 IFM_SUBTYPE(ifm->ifm_media) == IFM_HPNA_1) 3634 dc_setcfg(sc, ifm->ifm_media); 3635 else 3636 sc->dc_link = 0; 3637 3638 return (0); 3639 } 3640 3641 /* 3642 * Report current media status. 3643 */ 3644 static void 3645 dc_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 3646 { 3647 struct dc_softc *sc; 3648 struct mii_data *mii; 3649 struct ifmedia *ifm; 3650 3651 sc = ifp->if_softc; 3652 mii = device_get_softc(sc->dc_miibus); 3653 mii_pollstat(mii); 3654 ifm = &mii->mii_media; 3655 if (DC_IS_DAVICOM(sc)) { 3656 if (IFM_SUBTYPE(ifm->ifm_media) == IFM_HPNA_1) { 3657 ifmr->ifm_active = ifm->ifm_media; 3658 ifmr->ifm_status = 0; 3659 return; 3660 } 3661 } 3662 ifmr->ifm_active = mii->mii_media_active; 3663 ifmr->ifm_status = mii->mii_media_status; 3664 } 3665 3666 static int 3667 dc_ioctl(struct ifnet *ifp, u_long command, caddr_t data) 3668 { 3669 struct dc_softc *sc = ifp->if_softc; 3670 struct ifreq *ifr = (struct ifreq *)data; 3671 struct mii_data *mii; 3672 int error = 0; 3673 3674 DC_LOCK(sc); 3675 3676 switch (command) { 3677 case SIOCSIFFLAGS: 3678 if (ifp->if_flags & IFF_UP) { 3679 int need_setfilt = (ifp->if_flags ^ sc->dc_if_flags) & 3680 (IFF_PROMISC | IFF_ALLMULTI); 3681 3682 if (ifp->if_flags & IFF_RUNNING) { 3683 if (need_setfilt) 3684 dc_setfilt(sc); 3685 } else { 3686 sc->dc_txthresh = 0; 3687 dc_init(sc); 3688 } 3689 } else { 3690 if (ifp->if_flags & IFF_RUNNING) 3691 dc_stop(sc); 3692 } 3693 sc->dc_if_flags = ifp->if_flags; 3694 error = 0; 3695 break; 3696 case SIOCADDMULTI: 3697 case SIOCDELMULTI: 3698 dc_setfilt(sc); 3699 error = 0; 3700 break; 3701 case SIOCGIFMEDIA: 3702 case SIOCSIFMEDIA: 3703 mii = device_get_softc(sc->dc_miibus); 3704 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 3705 #ifdef SRM_MEDIA 3706 if (sc->dc_srm_media) 3707 sc->dc_srm_media = 0; 3708 #endif 3709 break; 3710 case SIOCSIFCAP: 3711 ifp->if_capenable = ifr->ifr_reqcap; 3712 break; 3713 default: 3714 error = ether_ioctl(ifp, command, data); 3715 break; 3716 } 3717 3718 DC_UNLOCK(sc); 3719 3720 return (error); 3721 } 3722 3723 static void 3724 dc_watchdog(struct ifnet *ifp) 3725 { 3726 struct dc_softc *sc; 3727 3728 sc = ifp->if_softc; 3729 3730 DC_LOCK(sc); 3731 3732 ifp->if_oerrors++; 3733 printf("dc%d: watchdog timeout\n", sc->dc_unit); 3734 3735 dc_stop(sc); 3736 dc_reset(sc); 3737 dc_init(sc); 3738 3739 if (ifp->if_snd.ifq_head != NULL) 3740 dc_start(ifp); 3741 3742 DC_UNLOCK(sc); 3743 } 3744 3745 /* 3746 * Stop the adapter and free any mbufs allocated to the 3747 * RX and TX lists. 3748 */ 3749 static void 3750 dc_stop(struct dc_softc *sc) 3751 { 3752 struct ifnet *ifp; 3753 struct dc_list_data *ld; 3754 struct dc_chain_data *cd; 3755 int i; 3756 u_int32_t ctl; 3757 3758 DC_LOCK(sc); 3759 3760 ifp = &sc->arpcom.ac_if; 3761 ifp->if_timer = 0; 3762 ld = sc->dc_ldata; 3763 cd = &sc->dc_cdata; 3764 3765 callout_stop(&sc->dc_stat_ch); 3766 3767 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 3768 #ifdef DEVICE_POLLING 3769 ether_poll_deregister(ifp); 3770 #endif 3771 3772 DC_CLRBIT(sc, DC_NETCFG, (DC_NETCFG_RX_ON | DC_NETCFG_TX_ON)); 3773 CSR_WRITE_4(sc, DC_IMR, 0x00000000); 3774 CSR_WRITE_4(sc, DC_TXADDR, 0x00000000); 3775 CSR_WRITE_4(sc, DC_RXADDR, 0x00000000); 3776 sc->dc_link = 0; 3777 3778 /* 3779 * Free data in the RX lists. 3780 */ 3781 for (i = 0; i < DC_RX_LIST_CNT; i++) { 3782 if (cd->dc_rx_chain[i] != NULL) { 3783 m_freem(cd->dc_rx_chain[i]); 3784 cd->dc_rx_chain[i] = NULL; 3785 } 3786 } 3787 bzero(&ld->dc_rx_list, sizeof(ld->dc_rx_list)); 3788 3789 /* 3790 * Free the TX list buffers. 3791 */ 3792 for (i = 0; i < DC_TX_LIST_CNT; i++) { 3793 if (cd->dc_tx_chain[i] != NULL) { 3794 ctl = le32toh(ld->dc_tx_list[i].dc_ctl); 3795 if ((ctl & DC_TXCTL_SETUP) || 3796 !(ctl & DC_TXCTL_LASTFRAG)) { 3797 cd->dc_tx_chain[i] = NULL; 3798 continue; 3799 } 3800 bus_dmamap_unload(sc->dc_mtag, cd->dc_tx_map[i]); 3801 m_freem(cd->dc_tx_chain[i]); 3802 cd->dc_tx_chain[i] = NULL; 3803 } 3804 } 3805 bzero(&ld->dc_tx_list, sizeof(ld->dc_tx_list)); 3806 3807 DC_UNLOCK(sc); 3808 } 3809 3810 /* 3811 * Device suspend routine. Stop the interface and save some PCI 3812 * settings in case the BIOS doesn't restore them properly on 3813 * resume. 3814 */ 3815 static int 3816 dc_suspend(device_t dev) 3817 { 3818 struct dc_softc *sc; 3819 int i, s; 3820 3821 s = splimp(); 3822 3823 sc = device_get_softc(dev); 3824 3825 dc_stop(sc); 3826 3827 for (i = 0; i < 5; i++) 3828 sc->saved_maps[i] = pci_read_config(dev, PCIR_BAR(i), 4); 3829 sc->saved_biosaddr = pci_read_config(dev, PCIR_BIOS, 4); 3830 sc->saved_intline = pci_read_config(dev, PCIR_INTLINE, 1); 3831 sc->saved_cachelnsz = pci_read_config(dev, PCIR_CACHELNSZ, 1); 3832 sc->saved_lattimer = pci_read_config(dev, PCIR_LATTIMER, 1); 3833 3834 sc->suspended = 1; 3835 3836 splx(s); 3837 return (0); 3838 } 3839 3840 /* 3841 * Device resume routine. Restore some PCI settings in case the BIOS 3842 * doesn't, re-enable busmastering, and restart the interface if 3843 * appropriate. 3844 */ 3845 static int 3846 dc_resume(device_t dev) 3847 { 3848 struct dc_softc *sc; 3849 struct ifnet *ifp; 3850 int i, s; 3851 3852 s = splimp(); 3853 3854 sc = device_get_softc(dev); 3855 ifp = &sc->arpcom.ac_if; 3856 #ifndef BURN_BRIDGES 3857 dc_acpi(dev); 3858 #endif 3859 /* better way to do this? */ 3860 for (i = 0; i < 5; i++) 3861 pci_write_config(dev, PCIR_BAR(i), sc->saved_maps[i], 4); 3862 pci_write_config(dev, PCIR_BIOS, sc->saved_biosaddr, 4); 3863 pci_write_config(dev, PCIR_INTLINE, sc->saved_intline, 1); 3864 pci_write_config(dev, PCIR_CACHELNSZ, sc->saved_cachelnsz, 1); 3865 pci_write_config(dev, PCIR_LATTIMER, sc->saved_lattimer, 1); 3866 3867 /* reenable busmastering */ 3868 pci_enable_busmaster(dev); 3869 pci_enable_io(dev, DC_RES); 3870 3871 /* reinitialize interface if necessary */ 3872 if (ifp->if_flags & IFF_UP) 3873 dc_init(sc); 3874 3875 sc->suspended = 0; 3876 3877 splx(s); 3878 return (0); 3879 } 3880 3881 /* 3882 * Stop all chip I/O so that the kernel's probe routines don't 3883 * get confused by errant DMAs when rebooting. 3884 */ 3885 static void 3886 dc_shutdown(device_t dev) 3887 { 3888 struct dc_softc *sc; 3889 3890 sc = device_get_softc(dev); 3891 3892 dc_stop(sc); 3893 } 3894